2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10
: chip_string
= "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12
: chip_string
= "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14
: chip_string
= "AMD RADV NAVI14"; break;
119 default: chip_string
= "AMD RADV unknown"; break;
122 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
126 radv_get_visible_vram_size(struct radv_physical_device
*device
)
128 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
132 radv_get_vram_size(struct radv_physical_device
*device
)
134 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
138 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
141 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
142 uint64_t vram_size
= radv_get_vram_size(device
);
143 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
144 device
->memory_properties
.memoryHeapCount
= 0;
146 vram_index
= device
->memory_properties
.memoryHeapCount
++;
147 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
149 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
152 if (visible_vram_size
) {
153 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
154 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
155 .size
= visible_vram_size
,
156 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
159 if (device
->rad_info
.gart_size
> 0) {
160 gart_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
162 .size
= device
->rad_info
.gart_size
,
163 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
168 unsigned type_count
= 0;
169 if (vram_index
>= 0) {
170 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
171 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
172 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
173 .heapIndex
= vram_index
,
176 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
177 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
178 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
179 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
181 .heapIndex
= gart_index
,
184 if (visible_vram_index
>= 0) {
185 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
186 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
187 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
190 .heapIndex
= visible_vram_index
,
193 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
194 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
195 * as they have identical property flags, and according to the
196 * spec, for types with identical flags, the one with greater
197 * performance must be given a lower index. */
198 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
199 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
200 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
201 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
202 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
203 .heapIndex
= gart_index
,
206 if (gart_index
>= 0) {
207 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
208 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
209 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
210 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
211 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
212 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
213 .heapIndex
= gart_index
,
216 device
->memory_properties
.memoryTypeCount
= type_count
;
220 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
222 const char *family
= getenv("RADV_FORCE_FAMILY");
228 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
229 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
230 /* Override family and chip_class. */
231 device
->rad_info
.family
= i
;
233 if (i
>= CHIP_NAVI10
)
234 device
->rad_info
.chip_class
= GFX10
;
235 else if (i
>= CHIP_VEGA10
)
236 device
->rad_info
.chip_class
= GFX9
;
237 else if (i
>= CHIP_TONGA
)
238 device
->rad_info
.chip_class
= GFX8
;
239 else if (i
>= CHIP_BONAIRE
)
240 device
->rad_info
.chip_class
= GFX7
;
242 device
->rad_info
.chip_class
= GFX6
;
248 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
253 radv_physical_device_init(struct radv_physical_device
*device
,
254 struct radv_instance
*instance
,
255 drmDevicePtr drm_device
)
257 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
259 drmVersionPtr version
;
263 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
265 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
266 radv_logi("Could not open device '%s'", path
);
268 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
271 version
= drmGetVersion(fd
);
275 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
276 radv_logi("Could not get the kernel driver version for device '%s'", path
);
278 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
279 "failed to get version %s: %m", path
);
282 if (strcmp(version
->name
, "amdgpu")) {
283 drmFreeVersion(version
);
286 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
287 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
289 return VK_ERROR_INCOMPATIBLE_DRIVER
;
291 drmFreeVersion(version
);
293 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
294 radv_logi("Found compatible device '%s'.", path
);
296 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
297 device
->instance
= instance
;
299 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
300 instance
->perftest_flags
);
302 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
306 if (instance
->enabled_extensions
.KHR_display
) {
307 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
308 if (master_fd
>= 0) {
309 uint32_t accel_working
= 0;
310 struct drm_amdgpu_info request
= {
311 .return_pointer
= (uintptr_t)&accel_working
,
312 .return_size
= sizeof(accel_working
),
313 .query
= AMDGPU_INFO_ACCEL_WORKING
316 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
323 device
->master_fd
= master_fd
;
324 device
->local_fd
= fd
;
325 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
327 radv_handle_env_var_force_family(device
);
329 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
331 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
332 device
->ws
->destroy(device
->ws
);
333 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
334 "cannot generate UUID");
338 /* These flags affect shader compilation. */
339 uint64_t shader_env_flags
=
340 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
341 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
343 /* The gpu id is already embedded in the uuid so we just pass "radv"
344 * when creating the cache.
346 char buf
[VK_UUID_SIZE
* 2 + 1];
347 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
348 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
350 if (device
->rad_info
.chip_class
< GFX8
||
351 device
->rad_info
.chip_class
> GFX9
)
352 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
354 radv_get_driver_uuid(&device
->driver_uuid
);
355 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
357 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
358 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
360 device
->dcc_msaa_allowed
=
361 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
363 device
->use_shader_ballot
= device
->rad_info
.chip_class
>= GFX8
&&
364 device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
366 /* Determine the number of threads per wave for all stages. */
367 device
->cs_wave_size
= 64;
368 device
->ps_wave_size
= 64;
369 device
->ge_wave_size
= 64;
371 if (device
->rad_info
.chip_class
>= GFX10
) {
372 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
373 device
->cs_wave_size
= 32;
375 /* For pixel shaders, wave64 is recommanded. */
376 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
377 device
->ps_wave_size
= 32;
379 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
380 device
->ge_wave_size
= 32;
383 radv_physical_device_init_mem_types(device
);
384 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
386 device
->bus_info
= *drm_device
->businfo
.pci
;
388 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
389 ac_print_gpu_info(&device
->rad_info
);
391 /* The WSI is structured as a layer on top of the driver, so this has
392 * to be the last part of initialization (at least until we get other
395 result
= radv_init_wsi(device
);
396 if (result
!= VK_SUCCESS
) {
397 device
->ws
->destroy(device
->ws
);
398 vk_error(instance
, result
);
412 radv_physical_device_finish(struct radv_physical_device
*device
)
414 radv_finish_wsi(device
);
415 device
->ws
->destroy(device
->ws
);
416 disk_cache_destroy(device
->disk_cache
);
417 close(device
->local_fd
);
418 if (device
->master_fd
!= -1)
419 close(device
->master_fd
);
423 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
424 VkSystemAllocationScope allocationScope
)
430 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
431 size_t align
, VkSystemAllocationScope allocationScope
)
433 return realloc(pOriginal
, size
);
437 default_free_func(void *pUserData
, void *pMemory
)
442 static const VkAllocationCallbacks default_alloc
= {
444 .pfnAllocation
= default_alloc_func
,
445 .pfnReallocation
= default_realloc_func
,
446 .pfnFree
= default_free_func
,
449 static const struct debug_control radv_debug_options
[] = {
450 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
451 {"nodcc", RADV_DEBUG_NO_DCC
},
452 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
453 {"nocache", RADV_DEBUG_NO_CACHE
},
454 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
455 {"nohiz", RADV_DEBUG_NO_HIZ
},
456 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
457 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
458 {"allbos", RADV_DEBUG_ALL_BOS
},
459 {"noibs", RADV_DEBUG_NO_IBS
},
460 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
461 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
462 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
463 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
464 {"nosisched", RADV_DEBUG_NO_SISCHED
},
465 {"preoptir", RADV_DEBUG_PREOPTIR
},
466 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
467 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
468 {"info", RADV_DEBUG_INFO
},
469 {"errors", RADV_DEBUG_ERRORS
},
470 {"startup", RADV_DEBUG_STARTUP
},
471 {"checkir", RADV_DEBUG_CHECKIR
},
472 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
473 {"nobinning", RADV_DEBUG_NOBINNING
},
474 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
475 {"nongg", RADV_DEBUG_NO_NGG
},
476 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
477 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
482 radv_get_debug_option_name(int id
)
484 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
485 return radv_debug_options
[id
].string
;
488 static const struct debug_control radv_perftest_options
[] = {
489 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
490 {"sisched", RADV_PERFTEST_SISCHED
},
491 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
492 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
493 {"bolist", RADV_PERFTEST_BO_LIST
},
494 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
495 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
496 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
497 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
498 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
503 radv_get_perftest_option_name(int id
)
505 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
506 return radv_perftest_options
[id
].string
;
510 radv_handle_per_app_options(struct radv_instance
*instance
,
511 const VkApplicationInfo
*info
)
513 const char *name
= info
? info
->pApplicationName
: NULL
;
518 if (!strcmp(name
, "Talos - Linux - 32bit") ||
519 !strcmp(name
, "Talos - Linux - 64bit")) {
520 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
521 /* Force enable LLVM sisched for Talos because it looks
522 * safe and it gives few more FPS.
524 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
526 } else if (!strcmp(name
, "DOOM_VFR")) {
527 /* Work around a Doom VFR game bug */
528 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
529 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
530 /* Workaround for a WaW hazard when LLVM moves/merges
531 * load/store memory operations.
532 * See https://reviews.llvm.org/D61313
534 if (HAVE_LLVM
< 0x900)
535 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
536 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
537 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
)) {
538 /* Force enable VK_AMD_shader_ballot because it looks
539 * safe and it gives a nice boost (+20% on Vega 56 at
542 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
547 static int radv_get_instance_extension_index(const char *name
)
549 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
550 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
556 static const char radv_dri_options_xml
[] =
558 DRI_CONF_SECTION_QUALITY
559 DRI_CONF_ADAPTIVE_SYNC("true")
563 static void radv_init_dri_options(struct radv_instance
*instance
)
565 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
566 driParseConfigFiles(&instance
->dri_options
,
567 &instance
->available_dri_options
,
571 VkResult
radv_CreateInstance(
572 const VkInstanceCreateInfo
* pCreateInfo
,
573 const VkAllocationCallbacks
* pAllocator
,
574 VkInstance
* pInstance
)
576 struct radv_instance
*instance
;
579 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
581 uint32_t client_version
;
582 if (pCreateInfo
->pApplicationInfo
&&
583 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
584 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
586 client_version
= VK_API_VERSION_1_0
;
589 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
590 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
592 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
594 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
597 instance
->alloc
= *pAllocator
;
599 instance
->alloc
= default_alloc
;
601 instance
->apiVersion
= client_version
;
602 instance
->physicalDeviceCount
= -1;
604 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
607 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
608 radv_perftest_options
);
611 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
612 radv_logi("Created an instance");
614 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
615 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
616 int index
= radv_get_instance_extension_index(ext_name
);
618 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
619 vk_free2(&default_alloc
, pAllocator
, instance
);
620 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
623 instance
->enabled_extensions
.extensions
[index
] = true;
626 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
627 if (result
!= VK_SUCCESS
) {
628 vk_free2(&default_alloc
, pAllocator
, instance
);
629 return vk_error(instance
, result
);
633 glsl_type_singleton_init_or_ref();
635 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
637 radv_init_dri_options(instance
);
638 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
640 *pInstance
= radv_instance_to_handle(instance
);
645 void radv_DestroyInstance(
646 VkInstance _instance
,
647 const VkAllocationCallbacks
* pAllocator
)
649 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
654 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
655 radv_physical_device_finish(instance
->physicalDevices
+ i
);
658 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
660 glsl_type_singleton_decref();
663 driDestroyOptionCache(&instance
->dri_options
);
664 driDestroyOptionInfo(&instance
->available_dri_options
);
666 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
668 vk_free(&instance
->alloc
, instance
);
672 radv_enumerate_devices(struct radv_instance
*instance
)
674 /* TODO: Check for more devices ? */
675 drmDevicePtr devices
[8];
676 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
679 instance
->physicalDeviceCount
= 0;
681 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
683 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
684 radv_logi("Found %d drm nodes", max_devices
);
687 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
689 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
690 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
691 devices
[i
]->bustype
== DRM_BUS_PCI
&&
692 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
694 result
= radv_physical_device_init(instance
->physicalDevices
+
695 instance
->physicalDeviceCount
,
698 if (result
== VK_SUCCESS
)
699 ++instance
->physicalDeviceCount
;
700 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
704 drmFreeDevices(devices
, max_devices
);
709 VkResult
radv_EnumeratePhysicalDevices(
710 VkInstance _instance
,
711 uint32_t* pPhysicalDeviceCount
,
712 VkPhysicalDevice
* pPhysicalDevices
)
714 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
717 if (instance
->physicalDeviceCount
< 0) {
718 result
= radv_enumerate_devices(instance
);
719 if (result
!= VK_SUCCESS
&&
720 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
724 if (!pPhysicalDevices
) {
725 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
727 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
728 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
729 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
732 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
736 VkResult
radv_EnumeratePhysicalDeviceGroups(
737 VkInstance _instance
,
738 uint32_t* pPhysicalDeviceGroupCount
,
739 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
741 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
744 if (instance
->physicalDeviceCount
< 0) {
745 result
= radv_enumerate_devices(instance
);
746 if (result
!= VK_SUCCESS
&&
747 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
751 if (!pPhysicalDeviceGroupProperties
) {
752 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
754 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
755 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
756 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
757 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
758 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
761 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
765 void radv_GetPhysicalDeviceFeatures(
766 VkPhysicalDevice physicalDevice
,
767 VkPhysicalDeviceFeatures
* pFeatures
)
769 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
770 memset(pFeatures
, 0, sizeof(*pFeatures
));
772 *pFeatures
= (VkPhysicalDeviceFeatures
) {
773 .robustBufferAccess
= true,
774 .fullDrawIndexUint32
= true,
775 .imageCubeArray
= true,
776 .independentBlend
= true,
777 .geometryShader
= true,
778 .tessellationShader
= true,
779 .sampleRateShading
= true,
780 .dualSrcBlend
= true,
782 .multiDrawIndirect
= true,
783 .drawIndirectFirstInstance
= true,
785 .depthBiasClamp
= true,
786 .fillModeNonSolid
= true,
791 .multiViewport
= true,
792 .samplerAnisotropy
= true,
793 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
794 .textureCompressionASTC_LDR
= false,
795 .textureCompressionBC
= true,
796 .occlusionQueryPrecise
= true,
797 .pipelineStatisticsQuery
= true,
798 .vertexPipelineStoresAndAtomics
= true,
799 .fragmentStoresAndAtomics
= true,
800 .shaderTessellationAndGeometryPointSize
= true,
801 .shaderImageGatherExtended
= true,
802 .shaderStorageImageExtendedFormats
= true,
803 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
804 .shaderUniformBufferArrayDynamicIndexing
= true,
805 .shaderSampledImageArrayDynamicIndexing
= true,
806 .shaderStorageBufferArrayDynamicIndexing
= true,
807 .shaderStorageImageArrayDynamicIndexing
= true,
808 .shaderStorageImageReadWithoutFormat
= true,
809 .shaderStorageImageWriteWithoutFormat
= true,
810 .shaderClipDistance
= true,
811 .shaderCullDistance
= true,
812 .shaderFloat64
= true,
814 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
815 .sparseBinding
= true,
816 .variableMultisampleRate
= true,
817 .inheritedQueries
= true,
821 void radv_GetPhysicalDeviceFeatures2(
822 VkPhysicalDevice physicalDevice
,
823 VkPhysicalDeviceFeatures2
*pFeatures
)
825 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
826 vk_foreach_struct(ext
, pFeatures
->pNext
) {
827 switch (ext
->sType
) {
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
829 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
830 features
->variablePointersStorageBuffer
= true;
831 features
->variablePointers
= true;
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
835 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
836 features
->multiview
= true;
837 features
->multiviewGeometryShader
= true;
838 features
->multiviewTessellationShader
= true;
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
842 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
843 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
844 features
->shaderDrawParameters
= true;
847 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
848 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
849 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
850 features
->protectedMemory
= false;
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
854 VkPhysicalDevice16BitStorageFeatures
*features
=
855 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
856 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
857 features
->storageBuffer16BitAccess
= enabled
;
858 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
859 features
->storagePushConstant16
= enabled
;
860 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
864 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
865 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
866 features
->samplerYcbcrConversion
= true;
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
870 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
871 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
872 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
873 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
874 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
875 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
876 features
->shaderSampledImageArrayNonUniformIndexing
= true;
877 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
878 features
->shaderStorageImageArrayNonUniformIndexing
= true;
879 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
880 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
881 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
882 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
883 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
884 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
885 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
886 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
887 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
888 features
->descriptorBindingUpdateUnusedWhilePending
= true;
889 features
->descriptorBindingPartiallyBound
= true;
890 features
->descriptorBindingVariableDescriptorCount
= true;
891 features
->runtimeDescriptorArray
= true;
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
895 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
896 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
897 features
->conditionalRendering
= true;
898 features
->inheritedConditionalRendering
= false;
901 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
902 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
903 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
904 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
905 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
908 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
909 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
910 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
911 features
->transformFeedback
= true;
912 features
->geometryStreams
= true;
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
916 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
917 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
918 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
922 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
923 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
924 features
->memoryPriority
= VK_TRUE
;
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
928 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
929 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
930 features
->bufferDeviceAddress
= true;
931 features
->bufferDeviceAddressCaptureReplay
= false;
932 features
->bufferDeviceAddressMultiDevice
= false;
935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
936 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
937 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
938 features
->depthClipEnable
= true;
941 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
942 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
943 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
944 features
->hostQueryReset
= true;
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
948 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
949 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
950 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
951 features
->storageBuffer8BitAccess
= enabled
;
952 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
953 features
->storagePushConstant8
= enabled
;
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
957 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
958 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
959 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
960 features
->shaderInt8
= true;
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
964 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
965 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
966 features
->shaderBufferInt64Atomics
= HAVE_LLVM
>= 0x0900;
967 features
->shaderSharedInt64Atomics
= HAVE_LLVM
>= 0x0900;
970 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
971 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
972 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
974 features
->inlineUniformBlock
= true;
975 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
979 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
980 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
981 features
->computeDerivativeGroupQuads
= false;
982 features
->computeDerivativeGroupLinear
= true;
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
986 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
987 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
988 features
->ycbcrImageArrays
= true;
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
992 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
993 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
994 features
->uniformBufferStandardLayout
= true;
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
998 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
999 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1000 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR
: {
1004 VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*features
=
1005 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*)ext
;
1006 features
->imagelessFramebuffer
= true;
1009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1010 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1011 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1012 features
->pipelineExecutableInfo
= true;
1019 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1022 void radv_GetPhysicalDeviceProperties(
1023 VkPhysicalDevice physicalDevice
,
1024 VkPhysicalDeviceProperties
* pProperties
)
1026 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1027 VkSampleCountFlags sample_counts
= 0xf;
1029 /* make sure that the entire descriptor set is addressable with a signed
1030 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1031 * be at most 2 GiB. the combined image & samples object count as one of
1032 * both. This limit is for the pipeline layout, not for the set layout, but
1033 * there is no set limit, so we just set a pipeline limit. I don't think
1034 * any app is going to hit this soon. */
1035 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1036 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1037 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1038 32 /* sampler, largest when combined with image */ +
1039 64 /* sampled image */ +
1040 64 /* storage image */);
1042 VkPhysicalDeviceLimits limits
= {
1043 .maxImageDimension1D
= (1 << 14),
1044 .maxImageDimension2D
= (1 << 14),
1045 .maxImageDimension3D
= (1 << 11),
1046 .maxImageDimensionCube
= (1 << 14),
1047 .maxImageArrayLayers
= (1 << 11),
1048 .maxTexelBufferElements
= 128 * 1024 * 1024,
1049 .maxUniformBufferRange
= UINT32_MAX
,
1050 .maxStorageBufferRange
= UINT32_MAX
,
1051 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1052 .maxMemoryAllocationCount
= UINT32_MAX
,
1053 .maxSamplerAllocationCount
= 64 * 1024,
1054 .bufferImageGranularity
= 64, /* A cache line */
1055 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1056 .maxBoundDescriptorSets
= MAX_SETS
,
1057 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1058 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1059 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1060 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1061 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1062 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1063 .maxPerStageResources
= max_descriptor_set_size
,
1064 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1065 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1066 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1067 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1068 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1069 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1070 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1071 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1072 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1073 .maxVertexInputBindings
= MAX_VBS
,
1074 .maxVertexInputAttributeOffset
= 2047,
1075 .maxVertexInputBindingStride
= 2048,
1076 .maxVertexOutputComponents
= 128,
1077 .maxTessellationGenerationLevel
= 64,
1078 .maxTessellationPatchSize
= 32,
1079 .maxTessellationControlPerVertexInputComponents
= 128,
1080 .maxTessellationControlPerVertexOutputComponents
= 128,
1081 .maxTessellationControlPerPatchOutputComponents
= 120,
1082 .maxTessellationControlTotalOutputComponents
= 4096,
1083 .maxTessellationEvaluationInputComponents
= 128,
1084 .maxTessellationEvaluationOutputComponents
= 128,
1085 .maxGeometryShaderInvocations
= 127,
1086 .maxGeometryInputComponents
= 64,
1087 .maxGeometryOutputComponents
= 128,
1088 .maxGeometryOutputVertices
= 256,
1089 .maxGeometryTotalOutputComponents
= 1024,
1090 .maxFragmentInputComponents
= 128,
1091 .maxFragmentOutputAttachments
= 8,
1092 .maxFragmentDualSrcAttachments
= 1,
1093 .maxFragmentCombinedOutputResources
= 8,
1094 .maxComputeSharedMemorySize
= 32768,
1095 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1096 .maxComputeWorkGroupInvocations
= 2048,
1097 .maxComputeWorkGroupSize
= {
1102 .subPixelPrecisionBits
= 8,
1103 .subTexelPrecisionBits
= 8,
1104 .mipmapPrecisionBits
= 8,
1105 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1106 .maxDrawIndirectCount
= UINT32_MAX
,
1107 .maxSamplerLodBias
= 16,
1108 .maxSamplerAnisotropy
= 16,
1109 .maxViewports
= MAX_VIEWPORTS
,
1110 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1111 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1112 .viewportSubPixelBits
= 8,
1113 .minMemoryMapAlignment
= 4096, /* A page */
1114 .minTexelBufferOffsetAlignment
= 1,
1115 .minUniformBufferOffsetAlignment
= 4,
1116 .minStorageBufferOffsetAlignment
= 4,
1117 .minTexelOffset
= -32,
1118 .maxTexelOffset
= 31,
1119 .minTexelGatherOffset
= -32,
1120 .maxTexelGatherOffset
= 31,
1121 .minInterpolationOffset
= -2,
1122 .maxInterpolationOffset
= 2,
1123 .subPixelInterpolationOffsetBits
= 8,
1124 .maxFramebufferWidth
= (1 << 14),
1125 .maxFramebufferHeight
= (1 << 14),
1126 .maxFramebufferLayers
= (1 << 10),
1127 .framebufferColorSampleCounts
= sample_counts
,
1128 .framebufferDepthSampleCounts
= sample_counts
,
1129 .framebufferStencilSampleCounts
= sample_counts
,
1130 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1131 .maxColorAttachments
= MAX_RTS
,
1132 .sampledImageColorSampleCounts
= sample_counts
,
1133 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1134 .sampledImageDepthSampleCounts
= sample_counts
,
1135 .sampledImageStencilSampleCounts
= sample_counts
,
1136 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1137 .maxSampleMaskWords
= 1,
1138 .timestampComputeAndGraphics
= true,
1139 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1140 .maxClipDistances
= 8,
1141 .maxCullDistances
= 8,
1142 .maxCombinedClipAndCullDistances
= 8,
1143 .discreteQueuePriorities
= 2,
1144 .pointSizeRange
= { 0.0, 8192.0 },
1145 .lineWidthRange
= { 0.0, 7.9921875 },
1146 .pointSizeGranularity
= (1.0 / 8.0),
1147 .lineWidthGranularity
= (1.0 / 128.0),
1148 .strictLines
= false, /* FINISHME */
1149 .standardSampleLocations
= true,
1150 .optimalBufferCopyOffsetAlignment
= 128,
1151 .optimalBufferCopyRowPitchAlignment
= 128,
1152 .nonCoherentAtomSize
= 64,
1155 *pProperties
= (VkPhysicalDeviceProperties
) {
1156 .apiVersion
= radv_physical_device_api_version(pdevice
),
1157 .driverVersion
= vk_get_driver_version(),
1158 .vendorID
= ATI_VENDOR_ID
,
1159 .deviceID
= pdevice
->rad_info
.pci_id
,
1160 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1162 .sparseProperties
= {0},
1165 strcpy(pProperties
->deviceName
, pdevice
->name
);
1166 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1169 void radv_GetPhysicalDeviceProperties2(
1170 VkPhysicalDevice physicalDevice
,
1171 VkPhysicalDeviceProperties2
*pProperties
)
1173 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1174 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1176 vk_foreach_struct(ext
, pProperties
->pNext
) {
1177 switch (ext
->sType
) {
1178 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1179 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1180 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1181 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1185 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1186 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1187 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1188 properties
->deviceLUIDValid
= false;
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1192 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1193 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1194 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1198 VkPhysicalDevicePointClippingProperties
*properties
=
1199 (VkPhysicalDevicePointClippingProperties
*)ext
;
1200 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1204 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1205 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1206 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1210 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1211 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1212 properties
->minImportedHostPointerAlignment
= 4096;
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1216 VkPhysicalDeviceSubgroupProperties
*properties
=
1217 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1218 properties
->subgroupSize
= 64;
1219 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1220 properties
->supportedOperations
=
1221 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1222 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1223 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1224 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1225 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1226 properties
->supportedOperations
|=
1227 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1228 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1229 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1231 properties
->quadOperationsInAllStages
= true;
1234 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1235 VkPhysicalDeviceMaintenance3Properties
*properties
=
1236 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1237 /* Make sure everything is addressable by a signed 32-bit int, and
1238 * our largest descriptors are 96 bytes. */
1239 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1240 /* Our buffer size fields allow only this much */
1241 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1245 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1246 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1247 /* GFX6-8 only support single channel min/max filter. */
1248 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1249 properties
->filterMinmaxSingleComponentFormats
= true;
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1253 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1254 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1256 /* Shader engines. */
1257 properties
->shaderEngineCount
=
1258 pdevice
->rad_info
.max_se
;
1259 properties
->shaderArraysPerEngineCount
=
1260 pdevice
->rad_info
.max_sh_per_se
;
1261 properties
->computeUnitsPerShaderArray
=
1262 pdevice
->rad_info
.num_good_cu_per_sh
;
1263 properties
->simdPerComputeUnit
= 4;
1264 properties
->wavefrontsPerSimd
=
1265 pdevice
->rad_info
.family
== CHIP_TONGA
||
1266 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1267 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1268 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1269 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1270 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1271 properties
->wavefrontSize
= 64;
1274 properties
->sgprsPerSimd
=
1275 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1276 properties
->minSgprAllocation
=
1277 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1278 properties
->maxSgprAllocation
=
1279 pdevice
->rad_info
.family
== CHIP_TONGA
||
1280 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1281 properties
->sgprAllocationGranularity
=
1282 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1285 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1286 properties
->minVgprAllocation
= 4;
1287 properties
->maxVgprAllocation
= 256;
1288 properties
->vgprAllocationGranularity
= 4;
1291 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1292 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1293 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1295 properties
->shaderCoreFeatures
= 0;
1296 properties
->activeComputeUnitCount
=
1297 pdevice
->rad_info
.num_good_compute_units
;
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1301 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1302 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1303 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1306 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1307 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1308 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1309 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1310 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1311 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1312 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1313 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1314 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1315 properties
->robustBufferAccessUpdateAfterBind
= false;
1316 properties
->quadDivergentImplicitLod
= false;
1318 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1319 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1320 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1321 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1322 32 /* sampler, largest when combined with image */ +
1323 64 /* sampled image */ +
1324 64 /* storage image */);
1325 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1326 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1327 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1328 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1329 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1330 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1331 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1332 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1333 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1334 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1335 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1336 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1337 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1338 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1339 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1342 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1343 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1344 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1345 properties
->protectedNoFault
= false;
1348 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1349 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1350 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1351 properties
->primitiveOverestimationSize
= 0;
1352 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1353 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1354 properties
->primitiveUnderestimation
= VK_FALSE
;
1355 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1356 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1357 properties
->degenerateLinesRasterized
= VK_FALSE
;
1358 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1359 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1362 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1363 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1364 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1365 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1366 properties
->pciBus
= pdevice
->bus_info
.bus
;
1367 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1368 properties
->pciFunction
= pdevice
->bus_info
.func
;
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1372 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1373 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1375 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1376 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE_KHR
, "radv");
1377 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1378 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1379 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1381 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1389 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1390 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1391 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1392 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1393 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1394 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1395 properties
->maxTransformFeedbackStreamDataSize
= 512;
1396 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1397 properties
->maxTransformFeedbackBufferDataStride
= 512;
1398 properties
->transformFeedbackQueries
= true;
1399 properties
->transformFeedbackStreamsLinesTriangles
= true;
1400 properties
->transformFeedbackRasterizationStreamSelect
= false;
1401 properties
->transformFeedbackDraw
= true;
1404 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1405 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1406 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1408 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1409 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1410 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1411 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1412 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1415 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1416 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1417 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1418 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1419 VK_SAMPLE_COUNT_4_BIT
|
1420 VK_SAMPLE_COUNT_8_BIT
;
1421 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1422 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1423 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1424 properties
->sampleLocationSubPixelBits
= 4;
1425 properties
->variableSampleLocations
= VK_FALSE
;
1428 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1429 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1430 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1432 /* We support all of the depth resolve modes */
1433 properties
->supportedDepthResolveModes
=
1434 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1435 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1436 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1437 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1439 /* Average doesn't make sense for stencil so we don't support that */
1440 properties
->supportedStencilResolveModes
=
1441 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1442 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1443 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1445 properties
->independentResolveNone
= VK_TRUE
;
1446 properties
->independentResolve
= VK_TRUE
;
1455 static void radv_get_physical_device_queue_family_properties(
1456 struct radv_physical_device
* pdevice
,
1458 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1460 int num_queue_families
= 1;
1462 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1463 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1464 num_queue_families
++;
1466 if (pQueueFamilyProperties
== NULL
) {
1467 *pCount
= num_queue_families
;
1476 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1477 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1478 VK_QUEUE_COMPUTE_BIT
|
1479 VK_QUEUE_TRANSFER_BIT
|
1480 VK_QUEUE_SPARSE_BINDING_BIT
,
1482 .timestampValidBits
= 64,
1483 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1488 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1489 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1490 if (*pCount
> idx
) {
1491 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1492 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1493 VK_QUEUE_TRANSFER_BIT
|
1494 VK_QUEUE_SPARSE_BINDING_BIT
,
1495 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1496 .timestampValidBits
= 64,
1497 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1505 void radv_GetPhysicalDeviceQueueFamilyProperties(
1506 VkPhysicalDevice physicalDevice
,
1508 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1510 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1511 if (!pQueueFamilyProperties
) {
1512 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1515 VkQueueFamilyProperties
*properties
[] = {
1516 pQueueFamilyProperties
+ 0,
1517 pQueueFamilyProperties
+ 1,
1518 pQueueFamilyProperties
+ 2,
1520 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1521 assert(*pCount
<= 3);
1524 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1525 VkPhysicalDevice physicalDevice
,
1527 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1529 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1530 if (!pQueueFamilyProperties
) {
1531 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1534 VkQueueFamilyProperties
*properties
[] = {
1535 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1536 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1537 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1539 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1540 assert(*pCount
<= 3);
1543 void radv_GetPhysicalDeviceMemoryProperties(
1544 VkPhysicalDevice physicalDevice
,
1545 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1547 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1549 *pMemoryProperties
= physical_device
->memory_properties
;
1553 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1554 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1556 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1557 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1558 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1559 uint64_t vram_size
= radv_get_vram_size(device
);
1560 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1561 uint64_t heap_budget
, heap_usage
;
1563 /* For all memory heaps, the computation of budget is as follow:
1564 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1566 * The Vulkan spec 1.1.97 says that the budget should include any
1567 * currently allocated device memory.
1569 * Note that the application heap usages are not really accurate (eg.
1570 * in presence of shared buffers).
1572 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1573 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1575 switch (device
->mem_type_indices
[i
]) {
1576 case RADV_MEM_TYPE_VRAM
:
1577 heap_usage
= device
->ws
->query_value(device
->ws
,
1578 RADEON_ALLOCATED_VRAM
);
1580 heap_budget
= vram_size
-
1581 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1584 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1585 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1587 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1588 heap_usage
= device
->ws
->query_value(device
->ws
,
1589 RADEON_ALLOCATED_VRAM_VIS
);
1591 heap_budget
= visible_vram_size
-
1592 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1595 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1596 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1598 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1599 heap_usage
= device
->ws
->query_value(device
->ws
,
1600 RADEON_ALLOCATED_GTT
);
1602 heap_budget
= gtt_size
-
1603 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1606 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1607 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1614 /* The heapBudget and heapUsage values must be zero for array elements
1615 * greater than or equal to
1616 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1618 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1619 memoryBudget
->heapBudget
[i
] = 0;
1620 memoryBudget
->heapUsage
[i
] = 0;
1624 void radv_GetPhysicalDeviceMemoryProperties2(
1625 VkPhysicalDevice physicalDevice
,
1626 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1628 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1629 &pMemoryProperties
->memoryProperties
);
1631 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1632 vk_find_struct(pMemoryProperties
->pNext
,
1633 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1635 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1638 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1640 VkExternalMemoryHandleTypeFlagBits handleType
,
1641 const void *pHostPointer
,
1642 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1644 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1648 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1649 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1650 uint32_t memoryTypeBits
= 0;
1651 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1652 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1653 memoryTypeBits
= (1 << i
);
1657 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1661 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1665 static enum radeon_ctx_priority
1666 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1668 /* Default to MEDIUM when a specific global priority isn't requested */
1670 return RADEON_CTX_PRIORITY_MEDIUM
;
1672 switch(pObj
->globalPriority
) {
1673 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1674 return RADEON_CTX_PRIORITY_REALTIME
;
1675 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1676 return RADEON_CTX_PRIORITY_HIGH
;
1677 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1678 return RADEON_CTX_PRIORITY_MEDIUM
;
1679 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1680 return RADEON_CTX_PRIORITY_LOW
;
1682 unreachable("Illegal global priority value");
1683 return RADEON_CTX_PRIORITY_INVALID
;
1688 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1689 uint32_t queue_family_index
, int idx
,
1690 VkDeviceQueueCreateFlags flags
,
1691 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1693 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1694 queue
->device
= device
;
1695 queue
->queue_family_index
= queue_family_index
;
1696 queue
->queue_idx
= idx
;
1697 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1698 queue
->flags
= flags
;
1700 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1702 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1708 radv_queue_finish(struct radv_queue
*queue
)
1711 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1713 if (queue
->initial_full_flush_preamble_cs
)
1714 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1715 if (queue
->initial_preamble_cs
)
1716 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1717 if (queue
->continue_preamble_cs
)
1718 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1719 if (queue
->descriptor_bo
)
1720 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1721 if (queue
->scratch_bo
)
1722 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1723 if (queue
->esgs_ring_bo
)
1724 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1725 if (queue
->gsvs_ring_bo
)
1726 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1727 if (queue
->tess_rings_bo
)
1728 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1729 if (queue
->compute_scratch_bo
)
1730 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1734 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1736 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1737 bo_list
->list
.count
= bo_list
->capacity
= 0;
1738 bo_list
->list
.bos
= NULL
;
1742 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1744 free(bo_list
->list
.bos
);
1745 pthread_mutex_destroy(&bo_list
->mutex
);
1748 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1749 struct radeon_winsys_bo
*bo
)
1751 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1756 if (unlikely(!device
->use_global_bo_list
))
1759 pthread_mutex_lock(&bo_list
->mutex
);
1760 if (bo_list
->list
.count
== bo_list
->capacity
) {
1761 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1762 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1765 pthread_mutex_unlock(&bo_list
->mutex
);
1766 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1769 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1770 bo_list
->capacity
= capacity
;
1773 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1774 pthread_mutex_unlock(&bo_list
->mutex
);
1778 static void radv_bo_list_remove(struct radv_device
*device
,
1779 struct radeon_winsys_bo
*bo
)
1781 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1786 if (unlikely(!device
->use_global_bo_list
))
1789 pthread_mutex_lock(&bo_list
->mutex
);
1790 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1791 if (bo_list
->list
.bos
[i
] == bo
) {
1792 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1793 --bo_list
->list
.count
;
1797 pthread_mutex_unlock(&bo_list
->mutex
);
1801 radv_device_init_gs_info(struct radv_device
*device
)
1803 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1804 device
->physical_device
->rad_info
.family
);
1807 static int radv_get_device_extension_index(const char *name
)
1809 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1810 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1817 radv_get_int_debug_option(const char *name
, int default_value
)
1824 result
= default_value
;
1828 result
= strtol(str
, &endptr
, 0);
1829 if (str
== endptr
) {
1830 /* No digits founs. */
1831 result
= default_value
;
1838 VkResult
radv_CreateDevice(
1839 VkPhysicalDevice physicalDevice
,
1840 const VkDeviceCreateInfo
* pCreateInfo
,
1841 const VkAllocationCallbacks
* pAllocator
,
1844 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1846 struct radv_device
*device
;
1848 bool keep_shader_info
= false;
1850 /* Check enabled features */
1851 if (pCreateInfo
->pEnabledFeatures
) {
1852 VkPhysicalDeviceFeatures supported_features
;
1853 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1854 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1855 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1856 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1857 for (uint32_t i
= 0; i
< num_features
; i
++) {
1858 if (enabled_feature
[i
] && !supported_feature
[i
])
1859 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1863 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1865 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1867 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1869 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1870 device
->instance
= physical_device
->instance
;
1871 device
->physical_device
= physical_device
;
1873 device
->ws
= physical_device
->ws
;
1875 device
->alloc
= *pAllocator
;
1877 device
->alloc
= physical_device
->instance
->alloc
;
1879 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1880 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1881 int index
= radv_get_device_extension_index(ext_name
);
1882 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1883 vk_free(&device
->alloc
, device
);
1884 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1887 device
->enabled_extensions
.extensions
[index
] = true;
1890 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1892 /* With update after bind we can't attach bo's to the command buffer
1893 * from the descriptor set anymore, so we have to use a global BO list.
1895 device
->use_global_bo_list
=
1896 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1897 device
->enabled_extensions
.EXT_descriptor_indexing
||
1898 device
->enabled_extensions
.EXT_buffer_device_address
;
1900 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
1901 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
1903 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1904 list_inithead(&device
->shader_slabs
);
1906 radv_bo_list_init(&device
->bo_list
);
1908 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1909 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1910 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1911 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1912 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1914 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1916 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1917 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1918 if (!device
->queues
[qfi
]) {
1919 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1923 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1925 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1927 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1928 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1929 qfi
, q
, queue_create
->flags
,
1931 if (result
!= VK_SUCCESS
)
1936 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1937 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1939 device
->dfsm_allowed
= device
->pbb_allowed
&&
1940 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1941 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
1942 device
->physical_device
->rad_info
.family
== CHIP_RENOIR
);
1945 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1948 /* The maximum number of scratch waves. Scratch space isn't divided
1949 * evenly between CUs. The number is only a function of the number of CUs.
1950 * We can decrease the constant to decrease the scratch buffer size.
1952 * sctx->scratch_waves must be >= the maximum possible size of
1953 * 1 threadgroup, so that the hw doesn't hang from being unable
1956 * The recommended value is 4 per CU at most. Higher numbers don't
1957 * bring much benefit, but they still occupy chip resources (think
1958 * async compute). I've seen ~2% performance difference between 4 and 32.
1960 uint32_t max_threads_per_block
= 2048;
1961 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1962 max_threads_per_block
/ 64);
1964 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
1965 S_00B800_CS_W32_EN(device
->physical_device
->cs_wave_size
== 32);
1967 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1968 /* If the KMD allows it (there is a KMD hw register for it),
1969 * allow launching waves out-of-order.
1971 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1974 radv_device_init_gs_info(device
);
1976 device
->tess_offchip_block_dw_size
=
1977 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1979 if (getenv("RADV_TRACE_FILE")) {
1980 const char *filename
= getenv("RADV_TRACE_FILE");
1982 keep_shader_info
= true;
1984 if (!radv_init_trace(device
))
1987 fprintf(stderr
, "*****************************************************************************\n");
1988 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1989 fprintf(stderr
, "*****************************************************************************\n");
1991 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1992 radv_dump_enabled_options(device
, stderr
);
1995 device
->keep_shader_info
= keep_shader_info
;
1997 result
= radv_device_init_meta(device
);
1998 if (result
!= VK_SUCCESS
)
2001 radv_device_init_msaa(device
);
2003 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2004 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2006 case RADV_QUEUE_GENERAL
:
2007 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2008 if (device
->physical_device
->rad_info
.drm_minor
< 6) {
2009 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2010 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2011 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2014 case RADV_QUEUE_COMPUTE
:
2015 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2016 radeon_emit(device
->empty_cs
[family
], 0);
2019 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2022 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2023 cik_create_gfx_config(device
);
2025 VkPipelineCacheCreateInfo ci
;
2026 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2029 ci
.pInitialData
= NULL
;
2030 ci
.initialDataSize
= 0;
2032 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2034 if (result
!= VK_SUCCESS
)
2037 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2039 device
->force_aniso
=
2040 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2041 if (device
->force_aniso
>= 0) {
2042 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2043 1 << util_logbase2(device
->force_aniso
));
2046 *pDevice
= radv_device_to_handle(device
);
2050 radv_device_finish_meta(device
);
2052 radv_bo_list_finish(&device
->bo_list
);
2054 if (device
->trace_bo
)
2055 device
->ws
->buffer_destroy(device
->trace_bo
);
2057 if (device
->gfx_init
)
2058 device
->ws
->buffer_destroy(device
->gfx_init
);
2060 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2061 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2062 radv_queue_finish(&device
->queues
[i
][q
]);
2063 if (device
->queue_count
[i
])
2064 vk_free(&device
->alloc
, device
->queues
[i
]);
2067 vk_free(&device
->alloc
, device
);
2071 void radv_DestroyDevice(
2073 const VkAllocationCallbacks
* pAllocator
)
2075 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2080 if (device
->trace_bo
)
2081 device
->ws
->buffer_destroy(device
->trace_bo
);
2083 if (device
->gfx_init
)
2084 device
->ws
->buffer_destroy(device
->gfx_init
);
2086 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2087 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2088 radv_queue_finish(&device
->queues
[i
][q
]);
2089 if (device
->queue_count
[i
])
2090 vk_free(&device
->alloc
, device
->queues
[i
]);
2091 if (device
->empty_cs
[i
])
2092 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2094 radv_device_finish_meta(device
);
2096 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2097 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2099 radv_destroy_shader_slabs(device
);
2101 radv_bo_list_finish(&device
->bo_list
);
2102 vk_free(&device
->alloc
, device
);
2105 VkResult
radv_EnumerateInstanceLayerProperties(
2106 uint32_t* pPropertyCount
,
2107 VkLayerProperties
* pProperties
)
2109 if (pProperties
== NULL
) {
2110 *pPropertyCount
= 0;
2114 /* None supported at this time */
2115 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2118 VkResult
radv_EnumerateDeviceLayerProperties(
2119 VkPhysicalDevice physicalDevice
,
2120 uint32_t* pPropertyCount
,
2121 VkLayerProperties
* pProperties
)
2123 if (pProperties
== NULL
) {
2124 *pPropertyCount
= 0;
2128 /* None supported at this time */
2129 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2132 void radv_GetDeviceQueue2(
2134 const VkDeviceQueueInfo2
* pQueueInfo
,
2137 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2138 struct radv_queue
*queue
;
2140 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2141 if (pQueueInfo
->flags
!= queue
->flags
) {
2142 /* From the Vulkan 1.1.70 spec:
2144 * "The queue returned by vkGetDeviceQueue2 must have the same
2145 * flags value from this structure as that used at device
2146 * creation time in a VkDeviceQueueCreateInfo instance. If no
2147 * matching flags were specified at device creation time then
2148 * pQueue will return VK_NULL_HANDLE."
2150 *pQueue
= VK_NULL_HANDLE
;
2154 *pQueue
= radv_queue_to_handle(queue
);
2157 void radv_GetDeviceQueue(
2159 uint32_t queueFamilyIndex
,
2160 uint32_t queueIndex
,
2163 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2164 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2165 .queueFamilyIndex
= queueFamilyIndex
,
2166 .queueIndex
= queueIndex
2169 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2173 fill_geom_tess_rings(struct radv_queue
*queue
,
2175 bool add_sample_positions
,
2176 uint32_t esgs_ring_size
,
2177 struct radeon_winsys_bo
*esgs_ring_bo
,
2178 uint32_t gsvs_ring_size
,
2179 struct radeon_winsys_bo
*gsvs_ring_bo
,
2180 uint32_t tess_factor_ring_size
,
2181 uint32_t tess_offchip_ring_offset
,
2182 uint32_t tess_offchip_ring_size
,
2183 struct radeon_winsys_bo
*tess_rings_bo
)
2185 uint32_t *desc
= &map
[4];
2188 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2190 /* stride 0, num records - size, add tid, swizzle, elsize4,
2193 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2194 S_008F04_SWIZZLE_ENABLE(true);
2195 desc
[2] = esgs_ring_size
;
2196 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2197 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2198 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2199 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2200 S_008F0C_INDEX_STRIDE(3) |
2201 S_008F0C_ADD_TID_ENABLE(1);
2203 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2204 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2205 S_008F0C_OOB_SELECT(2) |
2206 S_008F0C_RESOURCE_LEVEL(1);
2208 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2209 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2210 S_008F0C_ELEMENT_SIZE(1);
2213 /* GS entry for ES->GS ring */
2214 /* stride 0, num records - size, elsize0,
2217 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2218 desc
[6] = esgs_ring_size
;
2219 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2220 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2222 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2224 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2225 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2226 S_008F0C_OOB_SELECT(2) |
2227 S_008F0C_RESOURCE_LEVEL(1);
2229 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2230 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2237 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2239 /* VS entry for GS->VS ring */
2240 /* stride 0, num records - size, elsize0,
2243 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2244 desc
[2] = gsvs_ring_size
;
2245 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2246 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2247 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2248 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2250 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2251 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2255 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2259 /* stride gsvs_itemsize, num records 64
2260 elsize 4, index stride 16 */
2261 /* shader will patch stride and desc[2] */
2263 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
2264 S_008F04_SWIZZLE_ENABLE(1);
2266 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2267 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2268 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2269 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2270 S_008F0C_INDEX_STRIDE(1) |
2271 S_008F0C_ADD_TID_ENABLE(true);
2273 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2274 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2275 S_008F0C_OOB_SELECT(2) |
2276 S_008F0C_RESOURCE_LEVEL(1);
2278 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2279 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2280 S_008F0C_ELEMENT_SIZE(1);
2287 if (tess_rings_bo
) {
2288 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2289 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2292 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
2293 desc
[2] = tess_factor_ring_size
;
2294 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2295 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2296 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2297 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2299 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2300 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2301 S_008F0C_OOB_SELECT(3) |
2302 S_008F0C_RESOURCE_LEVEL(1);
2304 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2308 desc
[4] = tess_offchip_va
;
2309 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
2310 desc
[6] = tess_offchip_ring_size
;
2311 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2312 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2313 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2314 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2316 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2317 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2318 S_008F0C_OOB_SELECT(3) |
2319 S_008F0C_RESOURCE_LEVEL(1);
2321 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2322 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2328 if (add_sample_positions
) {
2329 /* add sample positions after all rings */
2330 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2332 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2334 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2336 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2341 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2343 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2344 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2345 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2346 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2347 unsigned max_offchip_buffers
;
2348 unsigned offchip_granularity
;
2349 unsigned hs_offchip_param
;
2353 * This must be one less than the maximum number due to a hw limitation.
2354 * Various hardware bugs need thGFX7
2357 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2358 * Gfx7 should limit max_offchip_buffers to 508
2359 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2361 * Follow AMDVLK here.
2363 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2364 max_offchip_buffers_per_se
= 256;
2365 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2366 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2367 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2368 --max_offchip_buffers_per_se
;
2370 max_offchip_buffers
= max_offchip_buffers_per_se
*
2371 device
->physical_device
->rad_info
.max_se
;
2373 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2374 * around by setting 4K granularity.
2376 if (device
->tess_offchip_block_dw_size
== 4096) {
2377 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2378 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2380 assert(device
->tess_offchip_block_dw_size
== 8192);
2381 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2384 switch (device
->physical_device
->rad_info
.chip_class
) {
2386 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2391 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2399 *max_offchip_buffers_p
= max_offchip_buffers
;
2400 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2401 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2402 --max_offchip_buffers
;
2404 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2405 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2408 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2410 return hs_offchip_param
;
2414 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2415 struct radeon_winsys_bo
*esgs_ring_bo
,
2416 uint32_t esgs_ring_size
,
2417 struct radeon_winsys_bo
*gsvs_ring_bo
,
2418 uint32_t gsvs_ring_size
)
2420 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2424 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2427 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2429 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2430 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2431 radeon_emit(cs
, esgs_ring_size
>> 8);
2432 radeon_emit(cs
, gsvs_ring_size
>> 8);
2434 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2435 radeon_emit(cs
, esgs_ring_size
>> 8);
2436 radeon_emit(cs
, gsvs_ring_size
>> 8);
2441 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2442 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2443 struct radeon_winsys_bo
*tess_rings_bo
)
2450 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2452 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2454 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2455 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2456 S_030938_SIZE(tf_ring_size
/ 4));
2457 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2460 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2461 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2462 S_030984_BASE_HI(tf_va
>> 40));
2463 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2464 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2465 S_030944_BASE_HI(tf_va
>> 40));
2467 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2470 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2471 S_008988_SIZE(tf_ring_size
/ 4));
2472 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2474 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2480 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2481 struct radeon_winsys_bo
*compute_scratch_bo
)
2483 uint64_t scratch_va
;
2485 if (!compute_scratch_bo
)
2488 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2490 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2492 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2493 radeon_emit(cs
, scratch_va
);
2494 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2495 S_008F04_SWIZZLE_ENABLE(1));
2499 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2500 struct radeon_cmdbuf
*cs
,
2501 struct radeon_winsys_bo
*descriptor_bo
)
2508 va
= radv_buffer_get_va(descriptor_bo
);
2510 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2512 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2513 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2514 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2515 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2516 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2518 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2519 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2522 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2523 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2524 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2525 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2526 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2528 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2529 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2533 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2534 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2535 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2536 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2537 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2538 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2540 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2541 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2548 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2550 struct radv_device
*device
= queue
->device
;
2552 if (device
->gfx_init
) {
2553 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2555 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2556 radeon_emit(cs
, va
);
2557 radeon_emit(cs
, va
>> 32);
2558 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2560 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2562 struct radv_physical_device
*physical_device
= device
->physical_device
;
2563 si_emit_graphics(physical_device
, cs
);
2568 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2570 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2571 si_emit_compute(physical_device
, cs
);
2575 radv_get_preamble_cs(struct radv_queue
*queue
,
2576 uint32_t scratch_size
,
2577 uint32_t compute_scratch_size
,
2578 uint32_t esgs_ring_size
,
2579 uint32_t gsvs_ring_size
,
2580 bool needs_tess_rings
,
2581 bool needs_sample_positions
,
2582 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2583 struct radeon_cmdbuf
**initial_preamble_cs
,
2584 struct radeon_cmdbuf
**continue_preamble_cs
)
2586 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2587 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2588 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2589 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2590 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2591 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2592 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2593 bool add_tess_rings
= false, add_sample_positions
= false;
2594 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2595 unsigned max_offchip_buffers
;
2596 unsigned hs_offchip_param
= 0;
2597 unsigned tess_offchip_ring_offset
;
2598 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2599 if (!queue
->has_tess_rings
) {
2600 if (needs_tess_rings
)
2601 add_tess_rings
= true;
2603 if (!queue
->has_sample_positions
) {
2604 if (needs_sample_positions
)
2605 add_sample_positions
= true;
2607 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2608 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2609 &max_offchip_buffers
);
2610 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2611 tess_offchip_ring_size
= max_offchip_buffers
*
2612 queue
->device
->tess_offchip_block_dw_size
* 4;
2614 if (scratch_size
<= queue
->scratch_size
&&
2615 compute_scratch_size
<= queue
->compute_scratch_size
&&
2616 esgs_ring_size
<= queue
->esgs_ring_size
&&
2617 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2618 !add_tess_rings
&& !add_sample_positions
&&
2619 queue
->initial_preamble_cs
) {
2620 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2621 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2622 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2623 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2624 *continue_preamble_cs
= NULL
;
2628 if (scratch_size
> queue
->scratch_size
) {
2629 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2634 RADV_BO_PRIORITY_SCRATCH
);
2638 scratch_bo
= queue
->scratch_bo
;
2640 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2641 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2642 compute_scratch_size
,
2646 RADV_BO_PRIORITY_SCRATCH
);
2647 if (!compute_scratch_bo
)
2651 compute_scratch_bo
= queue
->compute_scratch_bo
;
2653 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2654 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2659 RADV_BO_PRIORITY_SCRATCH
);
2663 esgs_ring_bo
= queue
->esgs_ring_bo
;
2664 esgs_ring_size
= queue
->esgs_ring_size
;
2667 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2668 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2673 RADV_BO_PRIORITY_SCRATCH
);
2677 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2678 gsvs_ring_size
= queue
->gsvs_ring_size
;
2681 if (add_tess_rings
) {
2682 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2683 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2687 RADV_BO_PRIORITY_SCRATCH
);
2691 tess_rings_bo
= queue
->tess_rings_bo
;
2694 if (scratch_bo
!= queue
->scratch_bo
||
2695 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2696 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2697 tess_rings_bo
!= queue
->tess_rings_bo
||
2698 add_sample_positions
) {
2700 if (gsvs_ring_bo
|| esgs_ring_bo
||
2701 tess_rings_bo
|| add_sample_positions
) {
2702 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2703 if (add_sample_positions
)
2704 size
+= 128; /* 64+32+16+8 = 120 bytes */
2706 else if (scratch_bo
)
2707 size
= 8; /* 2 dword */
2709 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2713 RADEON_FLAG_CPU_ACCESS
|
2714 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2715 RADEON_FLAG_READ_ONLY
,
2716 RADV_BO_PRIORITY_DESCRIPTOR
);
2720 descriptor_bo
= queue
->descriptor_bo
;
2722 if (descriptor_bo
!= queue
->descriptor_bo
) {
2723 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2726 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2727 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2728 S_008F04_SWIZZLE_ENABLE(1);
2729 map
[0] = scratch_va
;
2733 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2734 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2735 esgs_ring_size
, esgs_ring_bo
,
2736 gsvs_ring_size
, gsvs_ring_bo
,
2737 tess_factor_ring_size
,
2738 tess_offchip_ring_offset
,
2739 tess_offchip_ring_size
,
2742 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2745 for(int i
= 0; i
< 3; ++i
) {
2746 struct radeon_cmdbuf
*cs
= NULL
;
2747 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2748 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2755 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2757 /* Emit initial configuration. */
2758 switch (queue
->queue_family_index
) {
2759 case RADV_QUEUE_GENERAL
:
2760 radv_init_graphics_state(cs
, queue
);
2762 case RADV_QUEUE_COMPUTE
:
2763 radv_init_compute_state(cs
, queue
);
2765 case RADV_QUEUE_TRANSFER
:
2769 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2770 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2771 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2773 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2774 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2777 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2778 gsvs_ring_bo
, gsvs_ring_size
);
2779 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2780 tess_factor_ring_size
, tess_rings_bo
);
2781 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2782 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2785 si_cs_emit_cache_flush(cs
,
2786 queue
->device
->physical_device
->rad_info
.chip_class
,
2788 queue
->queue_family_index
== RING_COMPUTE
&&
2789 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2790 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2791 RADV_CMD_FLAG_INV_ICACHE
|
2792 RADV_CMD_FLAG_INV_SCACHE
|
2793 RADV_CMD_FLAG_INV_VCACHE
|
2794 RADV_CMD_FLAG_INV_L2
|
2795 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2796 } else if (i
== 1) {
2797 si_cs_emit_cache_flush(cs
,
2798 queue
->device
->physical_device
->rad_info
.chip_class
,
2800 queue
->queue_family_index
== RING_COMPUTE
&&
2801 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2802 RADV_CMD_FLAG_INV_ICACHE
|
2803 RADV_CMD_FLAG_INV_SCACHE
|
2804 RADV_CMD_FLAG_INV_VCACHE
|
2805 RADV_CMD_FLAG_INV_L2
|
2806 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2809 if (!queue
->device
->ws
->cs_finalize(cs
))
2813 if (queue
->initial_full_flush_preamble_cs
)
2814 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2816 if (queue
->initial_preamble_cs
)
2817 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2819 if (queue
->continue_preamble_cs
)
2820 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2822 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2823 queue
->initial_preamble_cs
= dest_cs
[1];
2824 queue
->continue_preamble_cs
= dest_cs
[2];
2826 if (scratch_bo
!= queue
->scratch_bo
) {
2827 if (queue
->scratch_bo
)
2828 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2829 queue
->scratch_bo
= scratch_bo
;
2830 queue
->scratch_size
= scratch_size
;
2833 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2834 if (queue
->compute_scratch_bo
)
2835 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2836 queue
->compute_scratch_bo
= compute_scratch_bo
;
2837 queue
->compute_scratch_size
= compute_scratch_size
;
2840 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2841 if (queue
->esgs_ring_bo
)
2842 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2843 queue
->esgs_ring_bo
= esgs_ring_bo
;
2844 queue
->esgs_ring_size
= esgs_ring_size
;
2847 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2848 if (queue
->gsvs_ring_bo
)
2849 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2850 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2851 queue
->gsvs_ring_size
= gsvs_ring_size
;
2854 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2855 queue
->tess_rings_bo
= tess_rings_bo
;
2856 queue
->has_tess_rings
= true;
2859 if (descriptor_bo
!= queue
->descriptor_bo
) {
2860 if (queue
->descriptor_bo
)
2861 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2863 queue
->descriptor_bo
= descriptor_bo
;
2866 if (add_sample_positions
)
2867 queue
->has_sample_positions
= true;
2869 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2870 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2871 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2872 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2873 *continue_preamble_cs
= NULL
;
2876 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2878 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2879 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2880 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2881 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2882 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2883 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2884 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2885 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2886 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2887 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2888 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2889 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2890 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2891 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2894 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2895 struct radv_winsys_sem_counts
*counts
,
2897 const VkSemaphore
*sems
,
2901 int syncobj_idx
= 0, sem_idx
= 0;
2903 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2906 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2907 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2909 if (sem
->temp_syncobj
|| sem
->syncobj
)
2910 counts
->syncobj_count
++;
2912 counts
->sem_count
++;
2915 if (_fence
!= VK_NULL_HANDLE
) {
2916 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2917 if (fence
->temp_syncobj
|| fence
->syncobj
)
2918 counts
->syncobj_count
++;
2921 if (counts
->syncobj_count
) {
2922 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2923 if (!counts
->syncobj
)
2924 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2927 if (counts
->sem_count
) {
2928 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2930 free(counts
->syncobj
);
2931 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2935 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2936 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2938 if (sem
->temp_syncobj
) {
2939 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2941 else if (sem
->syncobj
)
2942 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2945 counts
->sem
[sem_idx
++] = sem
->sem
;
2949 if (_fence
!= VK_NULL_HANDLE
) {
2950 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2951 if (fence
->temp_syncobj
)
2952 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2953 else if (fence
->syncobj
)
2954 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2961 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2963 free(sem_info
->wait
.syncobj
);
2964 free(sem_info
->wait
.sem
);
2965 free(sem_info
->signal
.syncobj
);
2966 free(sem_info
->signal
.sem
);
2970 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2972 const VkSemaphore
*sems
)
2974 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2975 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2977 if (sem
->temp_syncobj
) {
2978 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2979 sem
->temp_syncobj
= 0;
2985 radv_alloc_sem_info(struct radv_instance
*instance
,
2986 struct radv_winsys_sem_info
*sem_info
,
2988 const VkSemaphore
*wait_sems
,
2989 int num_signal_sems
,
2990 const VkSemaphore
*signal_sems
,
2994 memset(sem_info
, 0, sizeof(*sem_info
));
2996 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2999 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
3001 radv_free_sem_info(sem_info
);
3003 /* caller can override these */
3004 sem_info
->cs_emit_wait
= true;
3005 sem_info
->cs_emit_signal
= true;
3009 /* Signals fence as soon as all the work currently put on queue is done. */
3010 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
3011 struct radv_fence
*fence
)
3015 struct radv_winsys_sem_info sem_info
;
3017 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
3018 radv_fence_to_handle(fence
));
3019 if (result
!= VK_SUCCESS
)
3022 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3023 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3024 1, NULL
, NULL
, &sem_info
, NULL
,
3025 false, fence
->fence
);
3026 radv_free_sem_info(&sem_info
);
3029 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
3034 VkResult
radv_QueueSubmit(
3036 uint32_t submitCount
,
3037 const VkSubmitInfo
* pSubmits
,
3040 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3041 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3042 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3043 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3045 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3046 uint32_t scratch_size
= 0;
3047 uint32_t compute_scratch_size
= 0;
3048 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3049 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
3051 bool fence_emitted
= false;
3052 bool tess_rings_needed
= false;
3053 bool sample_positions_needed
= false;
3055 /* Do this first so failing to allocate scratch buffers can't result in
3056 * partially executed submissions. */
3057 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3058 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3059 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3060 pSubmits
[i
].pCommandBuffers
[j
]);
3062 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3063 compute_scratch_size
= MAX2(compute_scratch_size
,
3064 cmd_buffer
->compute_scratch_size_needed
);
3065 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3066 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3067 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3068 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3072 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3073 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3074 sample_positions_needed
, &initial_flush_preamble_cs
,
3075 &initial_preamble_cs
, &continue_preamble_cs
);
3076 if (result
!= VK_SUCCESS
)
3079 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3080 struct radeon_cmdbuf
**cs_array
;
3081 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
3082 bool can_patch
= true;
3084 struct radv_winsys_sem_info sem_info
;
3086 result
= radv_alloc_sem_info(queue
->device
->instance
,
3088 pSubmits
[i
].waitSemaphoreCount
,
3089 pSubmits
[i
].pWaitSemaphores
,
3090 pSubmits
[i
].signalSemaphoreCount
,
3091 pSubmits
[i
].pSignalSemaphores
,
3093 if (result
!= VK_SUCCESS
)
3096 if (!pSubmits
[i
].commandBufferCount
) {
3097 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3098 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3099 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3104 radv_loge("failed to submit CS %d\n", i
);
3107 fence_emitted
= true;
3109 radv_free_sem_info(&sem_info
);
3113 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3114 (pSubmits
[i
].commandBufferCount
));
3116 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3117 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3118 pSubmits
[i
].pCommandBuffers
[j
]);
3119 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3121 cs_array
[j
] = cmd_buffer
->cs
;
3122 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3125 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3128 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3129 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3130 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3132 advance
= MIN2(max_cs_submission
,
3133 pSubmits
[i
].commandBufferCount
- j
);
3135 if (queue
->device
->trace_bo
)
3136 *queue
->device
->trace_id_ptr
= 0;
3138 sem_info
.cs_emit_wait
= j
== 0;
3139 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3141 if (unlikely(queue
->device
->use_global_bo_list
)) {
3142 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3143 bo_list
= &queue
->device
->bo_list
.list
;
3146 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3147 advance
, initial_preamble
, continue_preamble_cs
,
3149 can_patch
, base_fence
);
3151 if (unlikely(queue
->device
->use_global_bo_list
))
3152 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3155 radv_loge("failed to submit CS %d\n", i
);
3158 fence_emitted
= true;
3159 if (queue
->device
->trace_bo
) {
3160 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3164 radv_free_temp_syncobjs(queue
->device
,
3165 pSubmits
[i
].waitSemaphoreCount
,
3166 pSubmits
[i
].pWaitSemaphores
);
3167 radv_free_sem_info(&sem_info
);
3172 if (!fence_emitted
) {
3173 result
= radv_signal_fence(queue
, fence
);
3174 if (result
!= VK_SUCCESS
)
3182 VkResult
radv_QueueWaitIdle(
3185 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3187 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3188 radv_queue_family_to_ring(queue
->queue_family_index
),
3193 VkResult
radv_DeviceWaitIdle(
3196 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3198 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3199 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3200 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3206 VkResult
radv_EnumerateInstanceExtensionProperties(
3207 const char* pLayerName
,
3208 uint32_t* pPropertyCount
,
3209 VkExtensionProperties
* pProperties
)
3211 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3213 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3214 if (radv_supported_instance_extensions
.extensions
[i
]) {
3215 vk_outarray_append(&out
, prop
) {
3216 *prop
= radv_instance_extensions
[i
];
3221 return vk_outarray_status(&out
);
3224 VkResult
radv_EnumerateDeviceExtensionProperties(
3225 VkPhysicalDevice physicalDevice
,
3226 const char* pLayerName
,
3227 uint32_t* pPropertyCount
,
3228 VkExtensionProperties
* pProperties
)
3230 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3231 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3233 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3234 if (device
->supported_extensions
.extensions
[i
]) {
3235 vk_outarray_append(&out
, prop
) {
3236 *prop
= radv_device_extensions
[i
];
3241 return vk_outarray_status(&out
);
3244 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3245 VkInstance _instance
,
3248 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3249 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3252 return radv_lookup_entrypoint_unchecked(pName
);
3254 return radv_lookup_entrypoint_checked(pName
,
3255 instance
? instance
->apiVersion
: 0,
3256 instance
? &instance
->enabled_extensions
: NULL
,
3261 /* The loader wants us to expose a second GetInstanceProcAddr function
3262 * to work around certain LD_PRELOAD issues seen in apps.
3265 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3266 VkInstance instance
,
3270 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3271 VkInstance instance
,
3274 return radv_GetInstanceProcAddr(instance
, pName
);
3278 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3279 VkInstance _instance
,
3283 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3284 VkInstance _instance
,
3287 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3289 return radv_lookup_physical_device_entrypoint_checked(pName
,
3290 instance
? instance
->apiVersion
: 0,
3291 instance
? &instance
->enabled_extensions
: NULL
);
3294 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3298 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3299 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3302 return radv_lookup_entrypoint_unchecked(pName
);
3304 return radv_lookup_entrypoint_checked(pName
,
3305 device
->instance
->apiVersion
,
3306 &device
->instance
->enabled_extensions
,
3307 &device
->enabled_extensions
);
3311 bool radv_get_memory_fd(struct radv_device
*device
,
3312 struct radv_device_memory
*memory
,
3315 struct radeon_bo_metadata metadata
;
3317 if (memory
->image
) {
3318 radv_init_metadata(device
, memory
->image
, &metadata
);
3319 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3322 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3326 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3327 const VkMemoryAllocateInfo
* pAllocateInfo
,
3328 const VkAllocationCallbacks
* pAllocator
,
3329 VkDeviceMemory
* pMem
)
3331 struct radv_device_memory
*mem
;
3333 enum radeon_bo_domain domain
;
3335 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3337 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3339 if (pAllocateInfo
->allocationSize
== 0) {
3340 /* Apparently, this is allowed */
3341 *pMem
= VK_NULL_HANDLE
;
3345 const VkImportMemoryFdInfoKHR
*import_info
=
3346 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3347 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3348 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3349 const VkExportMemoryAllocateInfo
*export_info
=
3350 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3351 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3352 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3354 const struct wsi_memory_allocate_info
*wsi_info
=
3355 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3357 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3358 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3360 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3362 if (wsi_info
&& wsi_info
->implicit_sync
)
3363 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3365 if (dedicate_info
) {
3366 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3367 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3373 float priority_float
= 0.5;
3374 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3375 vk_find_struct_const(pAllocateInfo
->pNext
,
3376 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3378 priority_float
= priority_ext
->priority
;
3380 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3381 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3383 mem
->user_ptr
= NULL
;
3386 assert(import_info
->handleType
==
3387 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3388 import_info
->handleType
==
3389 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3390 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3391 priority
, NULL
, NULL
);
3393 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3396 close(import_info
->fd
);
3398 } else if (host_ptr_info
) {
3399 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3400 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3401 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3402 pAllocateInfo
->allocationSize
,
3405 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3408 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3411 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3412 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3413 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3414 domain
= RADEON_DOMAIN_GTT
;
3416 domain
= RADEON_DOMAIN_VRAM
;
3418 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3419 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3421 flags
|= RADEON_FLAG_CPU_ACCESS
;
3423 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3424 flags
|= RADEON_FLAG_GTT_WC
;
3426 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3427 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3428 if (device
->use_global_bo_list
) {
3429 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3433 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3434 domain
, flags
, priority
);
3437 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3440 mem
->type_index
= mem_type_index
;
3443 result
= radv_bo_list_add(device
, mem
->bo
);
3444 if (result
!= VK_SUCCESS
)
3447 *pMem
= radv_device_memory_to_handle(mem
);
3452 device
->ws
->buffer_destroy(mem
->bo
);
3454 vk_free2(&device
->alloc
, pAllocator
, mem
);
3459 VkResult
radv_AllocateMemory(
3461 const VkMemoryAllocateInfo
* pAllocateInfo
,
3462 const VkAllocationCallbacks
* pAllocator
,
3463 VkDeviceMemory
* pMem
)
3465 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3466 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3469 void radv_FreeMemory(
3471 VkDeviceMemory _mem
,
3472 const VkAllocationCallbacks
* pAllocator
)
3474 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3475 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3480 radv_bo_list_remove(device
, mem
->bo
);
3481 device
->ws
->buffer_destroy(mem
->bo
);
3484 vk_free2(&device
->alloc
, pAllocator
, mem
);
3487 VkResult
radv_MapMemory(
3489 VkDeviceMemory _memory
,
3490 VkDeviceSize offset
,
3492 VkMemoryMapFlags flags
,
3495 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3496 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3504 *ppData
= mem
->user_ptr
;
3506 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3513 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3516 void radv_UnmapMemory(
3518 VkDeviceMemory _memory
)
3520 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3521 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3526 if (mem
->user_ptr
== NULL
)
3527 device
->ws
->buffer_unmap(mem
->bo
);
3530 VkResult
radv_FlushMappedMemoryRanges(
3532 uint32_t memoryRangeCount
,
3533 const VkMappedMemoryRange
* pMemoryRanges
)
3538 VkResult
radv_InvalidateMappedMemoryRanges(
3540 uint32_t memoryRangeCount
,
3541 const VkMappedMemoryRange
* pMemoryRanges
)
3546 void radv_GetBufferMemoryRequirements(
3549 VkMemoryRequirements
* pMemoryRequirements
)
3551 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3552 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3554 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3556 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3557 pMemoryRequirements
->alignment
= 4096;
3559 pMemoryRequirements
->alignment
= 16;
3561 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3564 void radv_GetBufferMemoryRequirements2(
3566 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3567 VkMemoryRequirements2
*pMemoryRequirements
)
3569 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3570 &pMemoryRequirements
->memoryRequirements
);
3571 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3572 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3573 switch (ext
->sType
) {
3574 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3575 VkMemoryDedicatedRequirements
*req
=
3576 (VkMemoryDedicatedRequirements
*) ext
;
3577 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3578 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3587 void radv_GetImageMemoryRequirements(
3590 VkMemoryRequirements
* pMemoryRequirements
)
3592 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3593 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3595 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3597 pMemoryRequirements
->size
= image
->size
;
3598 pMemoryRequirements
->alignment
= image
->alignment
;
3601 void radv_GetImageMemoryRequirements2(
3603 const VkImageMemoryRequirementsInfo2
*pInfo
,
3604 VkMemoryRequirements2
*pMemoryRequirements
)
3606 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3607 &pMemoryRequirements
->memoryRequirements
);
3609 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3611 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3612 switch (ext
->sType
) {
3613 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3614 VkMemoryDedicatedRequirements
*req
=
3615 (VkMemoryDedicatedRequirements
*) ext
;
3616 req
->requiresDedicatedAllocation
= image
->shareable
;
3617 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3626 void radv_GetImageSparseMemoryRequirements(
3629 uint32_t* pSparseMemoryRequirementCount
,
3630 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3635 void radv_GetImageSparseMemoryRequirements2(
3637 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3638 uint32_t* pSparseMemoryRequirementCount
,
3639 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3644 void radv_GetDeviceMemoryCommitment(
3646 VkDeviceMemory memory
,
3647 VkDeviceSize
* pCommittedMemoryInBytes
)
3649 *pCommittedMemoryInBytes
= 0;
3652 VkResult
radv_BindBufferMemory2(VkDevice device
,
3653 uint32_t bindInfoCount
,
3654 const VkBindBufferMemoryInfo
*pBindInfos
)
3656 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3657 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3658 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3661 buffer
->bo
= mem
->bo
;
3662 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3670 VkResult
radv_BindBufferMemory(
3673 VkDeviceMemory memory
,
3674 VkDeviceSize memoryOffset
)
3676 const VkBindBufferMemoryInfo info
= {
3677 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3680 .memoryOffset
= memoryOffset
3683 return radv_BindBufferMemory2(device
, 1, &info
);
3686 VkResult
radv_BindImageMemory2(VkDevice device
,
3687 uint32_t bindInfoCount
,
3688 const VkBindImageMemoryInfo
*pBindInfos
)
3690 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3691 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3692 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3695 image
->bo
= mem
->bo
;
3696 image
->offset
= pBindInfos
[i
].memoryOffset
;
3706 VkResult
radv_BindImageMemory(
3709 VkDeviceMemory memory
,
3710 VkDeviceSize memoryOffset
)
3712 const VkBindImageMemoryInfo info
= {
3713 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3716 .memoryOffset
= memoryOffset
3719 return radv_BindImageMemory2(device
, 1, &info
);
3724 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3725 const VkSparseBufferMemoryBindInfo
*bind
)
3727 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3729 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3730 struct radv_device_memory
*mem
= NULL
;
3732 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3733 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3735 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3736 bind
->pBinds
[i
].resourceOffset
,
3737 bind
->pBinds
[i
].size
,
3738 mem
? mem
->bo
: NULL
,
3739 bind
->pBinds
[i
].memoryOffset
);
3744 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3745 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3747 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3749 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3750 struct radv_device_memory
*mem
= NULL
;
3752 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3753 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3755 device
->ws
->buffer_virtual_bind(image
->bo
,
3756 bind
->pBinds
[i
].resourceOffset
,
3757 bind
->pBinds
[i
].size
,
3758 mem
? mem
->bo
: NULL
,
3759 bind
->pBinds
[i
].memoryOffset
);
3763 VkResult
radv_QueueBindSparse(
3765 uint32_t bindInfoCount
,
3766 const VkBindSparseInfo
* pBindInfo
,
3769 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3770 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3771 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3772 bool fence_emitted
= false;
3776 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3777 struct radv_winsys_sem_info sem_info
;
3778 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3779 radv_sparse_buffer_bind_memory(queue
->device
,
3780 pBindInfo
[i
].pBufferBinds
+ j
);
3783 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3784 radv_sparse_image_opaque_bind_memory(queue
->device
,
3785 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3789 result
= radv_alloc_sem_info(queue
->device
->instance
,
3791 pBindInfo
[i
].waitSemaphoreCount
,
3792 pBindInfo
[i
].pWaitSemaphores
,
3793 pBindInfo
[i
].signalSemaphoreCount
,
3794 pBindInfo
[i
].pSignalSemaphores
,
3796 if (result
!= VK_SUCCESS
)
3799 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3800 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3801 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3806 radv_loge("failed to submit CS %d\n", i
);
3810 fence_emitted
= true;
3813 radv_free_sem_info(&sem_info
);
3818 if (!fence_emitted
) {
3819 result
= radv_signal_fence(queue
, fence
);
3820 if (result
!= VK_SUCCESS
)
3828 VkResult
radv_CreateFence(
3830 const VkFenceCreateInfo
* pCreateInfo
,
3831 const VkAllocationCallbacks
* pAllocator
,
3834 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3835 const VkExportFenceCreateInfo
*export
=
3836 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3837 VkExternalFenceHandleTypeFlags handleTypes
=
3838 export
? export
->handleTypes
: 0;
3840 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3842 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3845 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3847 fence
->fence_wsi
= NULL
;
3848 fence
->temp_syncobj
= 0;
3849 if (device
->always_use_syncobj
|| handleTypes
) {
3850 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3852 vk_free2(&device
->alloc
, pAllocator
, fence
);
3853 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3855 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3856 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3858 fence
->fence
= NULL
;
3860 fence
->fence
= device
->ws
->create_fence();
3861 if (!fence
->fence
) {
3862 vk_free2(&device
->alloc
, pAllocator
, fence
);
3863 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3866 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3867 device
->ws
->signal_fence(fence
->fence
);
3870 *pFence
= radv_fence_to_handle(fence
);
3875 void radv_DestroyFence(
3878 const VkAllocationCallbacks
* pAllocator
)
3880 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3881 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3886 if (fence
->temp_syncobj
)
3887 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3889 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3891 device
->ws
->destroy_fence(fence
->fence
);
3892 if (fence
->fence_wsi
)
3893 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3894 vk_free2(&device
->alloc
, pAllocator
, fence
);
3898 uint64_t radv_get_current_time(void)
3901 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3902 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3905 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3907 uint64_t current_time
= radv_get_current_time();
3909 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3911 return current_time
+ timeout
;
3915 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3916 uint32_t fenceCount
, const VkFence
*pFences
)
3918 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3919 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3920 if (fence
->fence
== NULL
|| fence
->syncobj
||
3921 fence
->temp_syncobj
|| fence
->fence_wsi
||
3922 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3928 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3930 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3931 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3932 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3938 VkResult
radv_WaitForFences(
3940 uint32_t fenceCount
,
3941 const VkFence
* pFences
,
3945 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3946 timeout
= radv_get_absolute_timeout(timeout
);
3948 if (device
->always_use_syncobj
&&
3949 radv_all_fences_syncobj(fenceCount
, pFences
))
3951 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3953 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3955 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3956 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3957 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3960 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3963 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3966 if (!waitAll
&& fenceCount
> 1) {
3967 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3968 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3969 uint32_t wait_count
= 0;
3970 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3972 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3974 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3975 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3977 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3982 fences
[wait_count
++] = fence
->fence
;
3985 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3986 waitAll
, timeout
- radv_get_current_time());
3989 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3992 while(radv_get_current_time() <= timeout
) {
3993 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3994 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
4001 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4002 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4003 bool expired
= false;
4005 if (fence
->temp_syncobj
) {
4006 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
4011 if (fence
->syncobj
) {
4012 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
4018 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
4019 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
4020 radv_get_current_time() <= timeout
)
4024 expired
= device
->ws
->fence_wait(device
->ws
,
4031 if (fence
->fence_wsi
) {
4032 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
4033 if (result
!= VK_SUCCESS
)
4041 VkResult
radv_ResetFences(VkDevice _device
,
4042 uint32_t fenceCount
,
4043 const VkFence
*pFences
)
4045 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4047 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4048 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4050 device
->ws
->reset_fence(fence
->fence
);
4052 /* Per spec, we first restore the permanent payload, and then reset, so
4053 * having a temp syncobj should not skip resetting the permanent syncobj. */
4054 if (fence
->temp_syncobj
) {
4055 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4056 fence
->temp_syncobj
= 0;
4059 if (fence
->syncobj
) {
4060 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4067 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4069 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4070 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4072 if (fence
->temp_syncobj
) {
4073 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4074 return success
? VK_SUCCESS
: VK_NOT_READY
;
4077 if (fence
->syncobj
) {
4078 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4079 return success
? VK_SUCCESS
: VK_NOT_READY
;
4083 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4084 return VK_NOT_READY
;
4086 if (fence
->fence_wsi
) {
4087 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4089 if (result
!= VK_SUCCESS
) {
4090 if (result
== VK_TIMEOUT
)
4091 return VK_NOT_READY
;
4099 // Queue semaphore functions
4101 VkResult
radv_CreateSemaphore(
4103 const VkSemaphoreCreateInfo
* pCreateInfo
,
4104 const VkAllocationCallbacks
* pAllocator
,
4105 VkSemaphore
* pSemaphore
)
4107 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4108 const VkExportSemaphoreCreateInfo
*export
=
4109 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4110 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4111 export
? export
->handleTypes
: 0;
4113 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4115 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4117 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4119 sem
->temp_syncobj
= 0;
4120 /* create a syncobject if we are going to export this semaphore */
4121 if (device
->always_use_syncobj
|| handleTypes
) {
4122 assert (device
->physical_device
->rad_info
.has_syncobj
);
4123 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4125 vk_free2(&device
->alloc
, pAllocator
, sem
);
4126 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4130 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4132 vk_free2(&device
->alloc
, pAllocator
, sem
);
4133 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4138 *pSemaphore
= radv_semaphore_to_handle(sem
);
4142 void radv_DestroySemaphore(
4144 VkSemaphore _semaphore
,
4145 const VkAllocationCallbacks
* pAllocator
)
4147 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4148 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4153 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4155 device
->ws
->destroy_sem(sem
->sem
);
4156 vk_free2(&device
->alloc
, pAllocator
, sem
);
4159 VkResult
radv_CreateEvent(
4161 const VkEventCreateInfo
* pCreateInfo
,
4162 const VkAllocationCallbacks
* pAllocator
,
4165 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4166 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4168 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4171 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4173 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4175 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4176 RADV_BO_PRIORITY_FENCE
);
4178 vk_free2(&device
->alloc
, pAllocator
, event
);
4179 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4182 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4184 *pEvent
= radv_event_to_handle(event
);
4189 void radv_DestroyEvent(
4192 const VkAllocationCallbacks
* pAllocator
)
4194 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4195 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4199 device
->ws
->buffer_destroy(event
->bo
);
4200 vk_free2(&device
->alloc
, pAllocator
, event
);
4203 VkResult
radv_GetEventStatus(
4207 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4209 if (*event
->map
== 1)
4210 return VK_EVENT_SET
;
4211 return VK_EVENT_RESET
;
4214 VkResult
radv_SetEvent(
4218 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4224 VkResult
radv_ResetEvent(
4228 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4234 VkResult
radv_CreateBuffer(
4236 const VkBufferCreateInfo
* pCreateInfo
,
4237 const VkAllocationCallbacks
* pAllocator
,
4240 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4241 struct radv_buffer
*buffer
;
4243 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4245 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4246 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4248 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4250 buffer
->size
= pCreateInfo
->size
;
4251 buffer
->usage
= pCreateInfo
->usage
;
4254 buffer
->flags
= pCreateInfo
->flags
;
4256 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4257 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4259 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4260 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4261 align64(buffer
->size
, 4096),
4262 4096, 0, RADEON_FLAG_VIRTUAL
,
4263 RADV_BO_PRIORITY_VIRTUAL
);
4265 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4266 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4270 *pBuffer
= radv_buffer_to_handle(buffer
);
4275 void radv_DestroyBuffer(
4278 const VkAllocationCallbacks
* pAllocator
)
4280 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4281 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4286 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4287 device
->ws
->buffer_destroy(buffer
->bo
);
4289 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4292 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4294 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4296 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4297 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4301 static inline unsigned
4302 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4305 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4307 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4310 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4312 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4316 radv_init_dcc_control_reg(struct radv_device
*device
,
4317 struct radv_image_view
*iview
)
4319 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4320 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4321 unsigned max_compressed_block_size
;
4322 unsigned independent_128b_blocks
;
4323 unsigned independent_64b_blocks
;
4325 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4328 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4329 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4330 * dGPU and 64 for APU because all of our APUs to date use
4331 * DIMMs which have a request granularity size of 64B while all
4332 * other chips have a 32B request size.
4334 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4337 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4338 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4339 independent_64b_blocks
= 0;
4340 independent_128b_blocks
= 1;
4342 independent_128b_blocks
= 0;
4344 if (iview
->image
->info
.samples
> 1) {
4345 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4346 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4347 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4348 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4351 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4352 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4353 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4354 /* If this DCC image is potentially going to be used in texture
4355 * fetches, we need some special settings.
4357 independent_64b_blocks
= 1;
4358 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4360 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4361 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4362 * big as possible for better compression state.
4364 independent_64b_blocks
= 0;
4365 max_compressed_block_size
= max_uncompressed_block_size
;
4369 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4370 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4371 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4372 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4373 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4377 radv_initialise_color_surface(struct radv_device
*device
,
4378 struct radv_color_buffer_info
*cb
,
4379 struct radv_image_view
*iview
)
4381 const struct vk_format_description
*desc
;
4382 unsigned ntype
, format
, swap
, endian
;
4383 unsigned blend_clamp
= 0, blend_bypass
= 0;
4385 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4386 const struct radeon_surf
*surf
= &plane
->surface
;
4388 desc
= vk_format_description(iview
->vk_format
);
4390 memset(cb
, 0, sizeof(*cb
));
4392 /* Intensity is implemented as Red, so treat it that way. */
4393 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4395 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4397 cb
->cb_color_base
= va
>> 8;
4399 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4400 struct gfx9_surf_meta_flags meta
;
4401 if (iview
->image
->dcc_offset
)
4402 meta
= surf
->u
.gfx9
.dcc
;
4404 meta
= surf
->u
.gfx9
.cmask
;
4406 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4407 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4408 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4409 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
4410 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
4412 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4413 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4414 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4415 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4416 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4419 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4420 cb
->cb_color_base
|= surf
->tile_swizzle
;
4422 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4423 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4425 cb
->cb_color_base
+= level_info
->offset
>> 8;
4426 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4427 cb
->cb_color_base
|= surf
->tile_swizzle
;
4429 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4430 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4431 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4433 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4434 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4435 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
4437 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4439 if (radv_image_has_fmask(iview
->image
)) {
4440 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4441 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
4442 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
4443 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
4445 /* This must be set for fast clear to work without FMASK. */
4446 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4447 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4448 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4449 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4453 /* CMASK variables */
4454 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4455 va
+= iview
->image
->cmask_offset
;
4456 cb
->cb_color_cmask
= va
>> 8;
4458 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4459 va
+= iview
->image
->dcc_offset
;
4461 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4462 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4463 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4465 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
4466 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
4468 cb
->cb_dcc_base
= va
>> 8;
4469 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
4471 /* GFX10 field has the same base shift as the GFX6 field. */
4472 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4473 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4474 S_028C6C_SLICE_MAX_GFX10(max_slice
);
4476 if (iview
->image
->info
.samples
> 1) {
4477 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4479 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4480 S_028C74_NUM_FRAGMENTS(log_samples
);
4483 if (radv_image_has_fmask(iview
->image
)) {
4484 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
4485 cb
->cb_color_fmask
= va
>> 8;
4486 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
4488 cb
->cb_color_fmask
= cb
->cb_color_base
;
4491 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4493 vk_format_get_first_non_void_channel(iview
->vk_format
));
4494 format
= radv_translate_colorformat(iview
->vk_format
);
4495 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4496 radv_finishme("Illegal color\n");
4497 swap
= radv_translate_colorswap(iview
->vk_format
, false);
4498 endian
= radv_colorformat_endian_swap(format
);
4500 /* blend clamp should be set for all NORM/SRGB types */
4501 if (ntype
== V_028C70_NUMBER_UNORM
||
4502 ntype
== V_028C70_NUMBER_SNORM
||
4503 ntype
== V_028C70_NUMBER_SRGB
)
4506 /* set blend bypass according to docs if SINT/UINT or
4507 8/24 COLOR variants */
4508 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4509 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4510 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4515 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4516 (format
== V_028C70_COLOR_8
||
4517 format
== V_028C70_COLOR_8_8
||
4518 format
== V_028C70_COLOR_8_8_8_8
))
4519 ->color_is_int8
= true;
4521 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4522 S_028C70_COMP_SWAP(swap
) |
4523 S_028C70_BLEND_CLAMP(blend_clamp
) |
4524 S_028C70_BLEND_BYPASS(blend_bypass
) |
4525 S_028C70_SIMPLE_FLOAT(1) |
4526 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4527 ntype
!= V_028C70_NUMBER_SNORM
&&
4528 ntype
!= V_028C70_NUMBER_SRGB
&&
4529 format
!= V_028C70_COLOR_8_24
&&
4530 format
!= V_028C70_COLOR_24_8
) |
4531 S_028C70_NUMBER_TYPE(ntype
) |
4532 S_028C70_ENDIAN(endian
);
4533 if (radv_image_has_fmask(iview
->image
)) {
4534 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4535 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4536 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
4537 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4540 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4541 /* Allow the texture block to read FMASK directly
4542 * without decompressing it. This bit must be cleared
4543 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4544 * otherwise the operation doesn't happen.
4546 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4548 /* Set CMASK into a tiling format that allows the
4549 * texture block to read it.
4551 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4555 if (radv_image_has_cmask(iview
->image
) &&
4556 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4557 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4559 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4560 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4562 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4564 /* This must be set for fast clear to work without FMASK. */
4565 if (!radv_image_has_fmask(iview
->image
) &&
4566 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4567 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4568 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4571 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4572 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4574 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4575 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4576 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4577 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4579 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4580 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
4582 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
4583 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
4584 S_028EE0_RESOURCE_LEVEL(1);
4586 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4587 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4588 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4591 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4592 S_028C68_MIP0_HEIGHT(height
- 1) |
4593 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4598 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4599 struct radv_image_view
*iview
)
4601 unsigned max_zplanes
= 0;
4603 assert(radv_image_is_tc_compat_htile(iview
->image
));
4605 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4606 /* Default value for 32-bit depth surfaces. */
4609 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4610 iview
->image
->info
.samples
> 1)
4613 max_zplanes
= max_zplanes
+ 1;
4615 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4616 /* Do not enable Z plane compression for 16-bit depth
4617 * surfaces because isn't supported on GFX8. Only
4618 * 32-bit depth surfaces are supported by the hardware.
4619 * This allows to maintain shader compatibility and to
4620 * reduce the number of depth decompressions.
4624 if (iview
->image
->info
.samples
<= 1)
4626 else if (iview
->image
->info
.samples
<= 4)
4637 radv_initialise_ds_surface(struct radv_device
*device
,
4638 struct radv_ds_buffer_info
*ds
,
4639 struct radv_image_view
*iview
)
4641 unsigned level
= iview
->base_mip
;
4642 unsigned format
, stencil_format
;
4643 uint64_t va
, s_offs
, z_offs
;
4644 bool stencil_only
= false;
4645 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4646 const struct radeon_surf
*surf
= &plane
->surface
;
4648 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4650 memset(ds
, 0, sizeof(*ds
));
4651 switch (iview
->image
->vk_format
) {
4652 case VK_FORMAT_D24_UNORM_S8_UINT
:
4653 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4654 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4655 ds
->offset_scale
= 2.0f
;
4657 case VK_FORMAT_D16_UNORM
:
4658 case VK_FORMAT_D16_UNORM_S8_UINT
:
4659 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4660 ds
->offset_scale
= 4.0f
;
4662 case VK_FORMAT_D32_SFLOAT
:
4663 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4664 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4665 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4666 ds
->offset_scale
= 1.0f
;
4668 case VK_FORMAT_S8_UINT
:
4669 stencil_only
= true;
4675 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4676 stencil_format
= surf
->has_stencil
?
4677 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4679 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4680 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4681 S_028008_SLICE_MAX(max_slice
);
4682 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4683 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
4684 S_028008_SLICE_MAX_HI(max_slice
>> 11);
4687 ds
->db_htile_data_base
= 0;
4688 ds
->db_htile_surface
= 0;
4690 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4691 s_offs
= z_offs
= va
;
4693 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4694 assert(surf
->u
.gfx9
.surf_offset
== 0);
4695 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4697 ds
->db_z_info
= S_028038_FORMAT(format
) |
4698 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4699 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4700 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4701 S_028038_ZRANGE_PRECISION(1);
4702 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4703 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4705 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4706 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4707 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4710 ds
->db_depth_view
|= S_028008_MIPID(level
);
4711 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4712 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4714 if (radv_htile_enabled(iview
->image
, level
)) {
4715 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4717 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4718 unsigned max_zplanes
=
4719 radv_calc_decompress_on_z_planes(device
, iview
);
4721 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4723 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4724 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
4725 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
4727 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
4728 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4732 if (!surf
->has_stencil
)
4733 /* Use all of the htile_buffer for depth if there's no stencil. */
4734 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4735 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4736 iview
->image
->htile_offset
;
4737 ds
->db_htile_data_base
= va
>> 8;
4738 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4739 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
4741 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4742 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4746 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4749 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4751 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4752 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4754 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4755 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4756 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4758 if (iview
->image
->info
.samples
> 1)
4759 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4761 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4762 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4763 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4764 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4765 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4766 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4767 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4768 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4771 tile_mode
= stencil_tile_mode
;
4773 ds
->db_depth_info
|=
4774 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4775 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4776 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4777 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4778 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4779 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4780 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4781 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4783 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4784 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4785 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4786 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4788 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4791 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4792 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4793 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4795 if (radv_htile_enabled(iview
->image
, level
)) {
4796 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4798 if (!surf
->has_stencil
&&
4799 !radv_image_is_tc_compat_htile(iview
->image
))
4800 /* Use all of the htile_buffer for depth if there's no stencil. */
4801 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4803 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4804 iview
->image
->htile_offset
;
4805 ds
->db_htile_data_base
= va
>> 8;
4806 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4808 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4809 unsigned max_zplanes
=
4810 radv_calc_decompress_on_z_planes(device
, iview
);
4812 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4813 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4818 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4819 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4822 VkResult
radv_CreateFramebuffer(
4824 const VkFramebufferCreateInfo
* pCreateInfo
,
4825 const VkAllocationCallbacks
* pAllocator
,
4826 VkFramebuffer
* pFramebuffer
)
4828 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4829 struct radv_framebuffer
*framebuffer
;
4830 const VkFramebufferAttachmentsCreateInfoKHR
*imageless_create_info
=
4831 vk_find_struct_const(pCreateInfo
->pNext
,
4832 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR
);
4834 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4836 size_t size
= sizeof(*framebuffer
);
4837 if (!imageless_create_info
)
4838 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
4839 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4840 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4841 if (framebuffer
== NULL
)
4842 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4844 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4845 framebuffer
->width
= pCreateInfo
->width
;
4846 framebuffer
->height
= pCreateInfo
->height
;
4847 framebuffer
->layers
= pCreateInfo
->layers
;
4848 if (imageless_create_info
) {
4849 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
4850 const VkFramebufferAttachmentImageInfoKHR
*attachment
=
4851 imageless_create_info
->pAttachmentImageInfos
+ i
;
4852 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
4853 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
4854 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
4857 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4858 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4859 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4860 framebuffer
->attachments
[i
] = iview
;
4861 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4862 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4863 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4867 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4871 void radv_DestroyFramebuffer(
4874 const VkAllocationCallbacks
* pAllocator
)
4876 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4877 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4881 vk_free2(&device
->alloc
, pAllocator
, fb
);
4884 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4886 switch (address_mode
) {
4887 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4888 return V_008F30_SQ_TEX_WRAP
;
4889 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4890 return V_008F30_SQ_TEX_MIRROR
;
4891 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4892 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4893 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4894 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4895 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4896 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4898 unreachable("illegal tex wrap mode");
4904 radv_tex_compare(VkCompareOp op
)
4907 case VK_COMPARE_OP_NEVER
:
4908 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4909 case VK_COMPARE_OP_LESS
:
4910 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4911 case VK_COMPARE_OP_EQUAL
:
4912 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4913 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4914 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4915 case VK_COMPARE_OP_GREATER
:
4916 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4917 case VK_COMPARE_OP_NOT_EQUAL
:
4918 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4919 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4920 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4921 case VK_COMPARE_OP_ALWAYS
:
4922 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4924 unreachable("illegal compare mode");
4930 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4933 case VK_FILTER_NEAREST
:
4934 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4935 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4936 case VK_FILTER_LINEAR
:
4937 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4938 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4939 case VK_FILTER_CUBIC_IMG
:
4941 fprintf(stderr
, "illegal texture filter");
4947 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4950 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4951 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4952 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4953 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4955 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4960 radv_tex_bordercolor(VkBorderColor bcolor
)
4963 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4964 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4965 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4966 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4967 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4968 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4969 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4970 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4971 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4979 radv_tex_aniso_filter(unsigned filter
)
4993 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4996 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4997 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4998 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4999 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
5000 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
5001 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
5009 radv_get_max_anisotropy(struct radv_device
*device
,
5010 const VkSamplerCreateInfo
*pCreateInfo
)
5012 if (device
->force_aniso
>= 0)
5013 return device
->force_aniso
;
5015 if (pCreateInfo
->anisotropyEnable
&&
5016 pCreateInfo
->maxAnisotropy
> 1.0f
)
5017 return (uint32_t)pCreateInfo
->maxAnisotropy
;
5023 radv_init_sampler(struct radv_device
*device
,
5024 struct radv_sampler
*sampler
,
5025 const VkSamplerCreateInfo
*pCreateInfo
)
5027 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
5028 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
5029 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
5030 device
->physical_device
->rad_info
.chip_class
== GFX9
;
5031 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5033 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
5034 vk_find_struct_const(pCreateInfo
->pNext
,
5035 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
5036 if (sampler_reduction
)
5037 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
5039 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
5040 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
5041 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
5042 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
5043 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
5044 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
5045 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
5046 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
5047 S_008F30_DISABLE_CUBE_WRAP(0) |
5048 S_008F30_COMPAT_MODE(compat_mode
) |
5049 S_008F30_FILTER_MODE(filter_mode
));
5050 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5051 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5052 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5053 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5054 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5055 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5056 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5057 S_008F38_MIP_POINT_PRECLAMP(0));
5058 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5059 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5061 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5062 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5064 sampler
->state
[2] |=
5065 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5066 S_008F38_FILTER_PREC_FIX(1) |
5067 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5071 VkResult
radv_CreateSampler(
5073 const VkSamplerCreateInfo
* pCreateInfo
,
5074 const VkAllocationCallbacks
* pAllocator
,
5075 VkSampler
* pSampler
)
5077 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5078 struct radv_sampler
*sampler
;
5080 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5081 vk_find_struct_const(pCreateInfo
->pNext
,
5082 SAMPLER_YCBCR_CONVERSION_INFO
);
5084 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5086 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5087 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5089 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5091 radv_init_sampler(device
, sampler
, pCreateInfo
);
5093 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5094 *pSampler
= radv_sampler_to_handle(sampler
);
5099 void radv_DestroySampler(
5102 const VkAllocationCallbacks
* pAllocator
)
5104 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5105 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5109 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5112 /* vk_icd.h does not declare this function, so we declare it here to
5113 * suppress Wmissing-prototypes.
5115 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5116 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5118 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5119 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5121 /* For the full details on loader interface versioning, see
5122 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5123 * What follows is a condensed summary, to help you navigate the large and
5124 * confusing official doc.
5126 * - Loader interface v0 is incompatible with later versions. We don't
5129 * - In loader interface v1:
5130 * - The first ICD entrypoint called by the loader is
5131 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5133 * - The ICD must statically expose no other Vulkan symbol unless it is
5134 * linked with -Bsymbolic.
5135 * - Each dispatchable Vulkan handle created by the ICD must be
5136 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5137 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5138 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5139 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5140 * such loader-managed surfaces.
5142 * - Loader interface v2 differs from v1 in:
5143 * - The first ICD entrypoint called by the loader is
5144 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5145 * statically expose this entrypoint.
5147 * - Loader interface v3 differs from v2 in:
5148 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5149 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5150 * because the loader no longer does so.
5152 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5156 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5157 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5160 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5161 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5163 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5165 /* At the moment, we support only the below handle types. */
5166 assert(pGetFdInfo
->handleType
==
5167 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5168 pGetFdInfo
->handleType
==
5169 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5171 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5173 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5177 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5178 VkExternalMemoryHandleTypeFlagBits handleType
,
5180 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5182 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5184 switch (handleType
) {
5185 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5186 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5190 /* The valid usage section for this function says:
5192 * "handleType must not be one of the handle types defined as
5195 * So opaque handle types fall into the default "unsupported" case.
5197 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5201 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5205 uint32_t syncobj_handle
= 0;
5206 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5208 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5211 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5213 *syncobj
= syncobj_handle
;
5219 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5223 /* If we create a syncobj we do it locally so that if we have an error, we don't
5224 * leave a syncobj in an undetermined state in the fence. */
5225 uint32_t syncobj_handle
= *syncobj
;
5226 if (!syncobj_handle
) {
5227 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5229 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5234 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5236 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5238 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5241 *syncobj
= syncobj_handle
;
5248 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5249 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5251 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5252 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5253 uint32_t *syncobj_dst
= NULL
;
5255 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5256 syncobj_dst
= &sem
->temp_syncobj
;
5258 syncobj_dst
= &sem
->syncobj
;
5261 switch(pImportSemaphoreFdInfo
->handleType
) {
5262 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5263 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5264 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5265 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5267 unreachable("Unhandled semaphore handle type");
5271 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5272 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5275 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5276 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5278 uint32_t syncobj_handle
;
5280 if (sem
->temp_syncobj
)
5281 syncobj_handle
= sem
->temp_syncobj
;
5283 syncobj_handle
= sem
->syncobj
;
5285 switch(pGetFdInfo
->handleType
) {
5286 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5287 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5289 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5290 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5292 if (sem
->temp_syncobj
) {
5293 close (sem
->temp_syncobj
);
5294 sem
->temp_syncobj
= 0;
5296 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5301 unreachable("Unhandled semaphore handle type");
5305 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5309 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5310 VkPhysicalDevice physicalDevice
,
5311 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5312 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5314 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5316 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5317 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5318 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5319 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5320 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5321 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5322 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5323 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5324 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5325 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5326 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5327 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5328 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5330 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5331 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5332 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5336 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5337 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5339 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5340 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5341 uint32_t *syncobj_dst
= NULL
;
5344 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5345 syncobj_dst
= &fence
->temp_syncobj
;
5347 syncobj_dst
= &fence
->syncobj
;
5350 switch(pImportFenceFdInfo
->handleType
) {
5351 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5352 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5353 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5354 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5356 unreachable("Unhandled fence handle type");
5360 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5361 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5364 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5365 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5367 uint32_t syncobj_handle
;
5369 if (fence
->temp_syncobj
)
5370 syncobj_handle
= fence
->temp_syncobj
;
5372 syncobj_handle
= fence
->syncobj
;
5374 switch(pGetFdInfo
->handleType
) {
5375 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5376 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5378 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5379 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5381 if (fence
->temp_syncobj
) {
5382 close (fence
->temp_syncobj
);
5383 fence
->temp_syncobj
= 0;
5385 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5390 unreachable("Unhandled fence handle type");
5394 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5398 void radv_GetPhysicalDeviceExternalFenceProperties(
5399 VkPhysicalDevice physicalDevice
,
5400 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5401 VkExternalFenceProperties
*pExternalFenceProperties
)
5403 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5405 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5406 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5407 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5408 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5409 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5410 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5411 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5413 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5414 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5415 pExternalFenceProperties
->externalFenceFeatures
= 0;
5420 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5421 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5422 const VkAllocationCallbacks
* pAllocator
,
5423 VkDebugReportCallbackEXT
* pCallback
)
5425 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5426 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5427 pCreateInfo
, pAllocator
, &instance
->alloc
,
5432 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5433 VkDebugReportCallbackEXT _callback
,
5434 const VkAllocationCallbacks
* pAllocator
)
5436 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5437 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5438 _callback
, pAllocator
, &instance
->alloc
);
5442 radv_DebugReportMessageEXT(VkInstance _instance
,
5443 VkDebugReportFlagsEXT flags
,
5444 VkDebugReportObjectTypeEXT objectType
,
5447 int32_t messageCode
,
5448 const char* pLayerPrefix
,
5449 const char* pMessage
)
5451 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5452 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5453 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5457 radv_GetDeviceGroupPeerMemoryFeatures(
5460 uint32_t localDeviceIndex
,
5461 uint32_t remoteDeviceIndex
,
5462 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5464 assert(localDeviceIndex
== remoteDeviceIndex
);
5466 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5467 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5468 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5469 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5472 static const VkTimeDomainEXT radv_time_domains
[] = {
5473 VK_TIME_DOMAIN_DEVICE_EXT
,
5474 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5475 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5478 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5479 VkPhysicalDevice physicalDevice
,
5480 uint32_t *pTimeDomainCount
,
5481 VkTimeDomainEXT
*pTimeDomains
)
5484 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5486 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5487 vk_outarray_append(&out
, i
) {
5488 *i
= radv_time_domains
[d
];
5492 return vk_outarray_status(&out
);
5496 radv_clock_gettime(clockid_t clock_id
)
5498 struct timespec current
;
5501 ret
= clock_gettime(clock_id
, ¤t
);
5502 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5503 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5507 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5510 VkResult
radv_GetCalibratedTimestampsEXT(
5512 uint32_t timestampCount
,
5513 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5514 uint64_t *pTimestamps
,
5515 uint64_t *pMaxDeviation
)
5517 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5518 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5520 uint64_t begin
, end
;
5521 uint64_t max_clock_period
= 0;
5523 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5525 for (d
= 0; d
< timestampCount
; d
++) {
5526 switch (pTimestampInfos
[d
].timeDomain
) {
5527 case VK_TIME_DOMAIN_DEVICE_EXT
:
5528 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5530 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5531 max_clock_period
= MAX2(max_clock_period
, device_period
);
5533 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5534 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5535 max_clock_period
= MAX2(max_clock_period
, 1);
5538 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5539 pTimestamps
[d
] = begin
;
5547 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5550 * The maximum deviation is the sum of the interval over which we
5551 * perform the sampling and the maximum period of any sampled
5552 * clock. That's because the maximum skew between any two sampled
5553 * clock edges is when the sampled clock with the largest period is
5554 * sampled at the end of that period but right at the beginning of the
5555 * sampling interval and some other clock is sampled right at the
5556 * begining of its sampling period and right at the end of the
5557 * sampling interval. Let's assume the GPU has the longest clock
5558 * period and that the application is sampling GPU and monotonic:
5561 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5562 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5566 * GPU -----_____-----_____-----_____-----_____
5569 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5570 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5572 * Interval <----------------->
5573 * Deviation <-------------------------->
5577 * m = read(monotonic) 2
5580 * We round the sample interval up by one tick to cover sampling error
5581 * in the interval clock
5584 uint64_t sample_interval
= end
- begin
+ 1;
5586 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5591 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5592 VkPhysicalDevice physicalDevice
,
5593 VkSampleCountFlagBits samples
,
5594 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5596 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5597 VK_SAMPLE_COUNT_4_BIT
|
5598 VK_SAMPLE_COUNT_8_BIT
)) {
5599 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5601 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };