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radv: Enable query inheritance.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 {
88 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
89 .specVersion = 1,
90 },
91 };
92
93 static const VkExtensionProperties common_device_extensions[] = {
94 {
95 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
100 .specVersion = 1,
101 },
102 {
103 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
116 .specVersion = 68,
117 },
118 {
119 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 {
123 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
124 .specVersion = 1,
125 },
126 {
127 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
128 .specVersion = 1,
129 },
130 };
131
132 static VkResult
133 radv_extensions_register(struct radv_instance *instance,
134 struct radv_extensions *extensions,
135 const VkExtensionProperties *new_ext,
136 uint32_t num_ext)
137 {
138 size_t new_size;
139 VkExtensionProperties *new_ptr;
140
141 assert(new_ext && num_ext > 0);
142
143 if (!new_ext)
144 return VK_ERROR_INITIALIZATION_FAILED;
145
146 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
147 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
148 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
149
150 /* Old array continues to be valid, update nothing */
151 if (!new_ptr)
152 return VK_ERROR_OUT_OF_HOST_MEMORY;
153
154 memcpy(&new_ptr[extensions->num_ext], new_ext,
155 num_ext * sizeof(VkExtensionProperties));
156 extensions->ext_array = new_ptr;
157 extensions->num_ext += num_ext;
158
159 return VK_SUCCESS;
160 }
161
162 static void
163 radv_extensions_finish(struct radv_instance *instance,
164 struct radv_extensions *extensions)
165 {
166 assert(extensions);
167
168 if (!extensions)
169 radv_loge("Attemted to free invalid extension struct\n");
170
171 if (extensions->ext_array)
172 vk_free(&instance->alloc, extensions->ext_array);
173 }
174
175 static bool
176 is_extension_enabled(const VkExtensionProperties *extensions,
177 size_t num_ext,
178 const char *name)
179 {
180 assert(extensions && name);
181
182 for (uint32_t i = 0; i < num_ext; i++) {
183 if (strcmp(name, extensions[i].extensionName) == 0)
184 return true;
185 }
186
187 return false;
188 }
189
190 static VkResult
191 radv_physical_device_init(struct radv_physical_device *device,
192 struct radv_instance *instance,
193 const char *path)
194 {
195 VkResult result;
196 drmVersionPtr version;
197 int fd;
198
199 fd = open(path, O_RDWR | O_CLOEXEC);
200 if (fd < 0)
201 return VK_ERROR_INCOMPATIBLE_DRIVER;
202
203 version = drmGetVersion(fd);
204 if (!version) {
205 close(fd);
206 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
207 "failed to get version %s: %m", path);
208 }
209
210 if (strcmp(version->name, "amdgpu")) {
211 drmFreeVersion(version);
212 close(fd);
213 return VK_ERROR_INCOMPATIBLE_DRIVER;
214 }
215 drmFreeVersion(version);
216
217 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 device->instance = instance;
219 assert(strlen(path) < ARRAY_SIZE(device->path));
220 strncpy(device->path, path, ARRAY_SIZE(device->path));
221
222 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
223 if (!device->ws) {
224 result = VK_ERROR_INCOMPATIBLE_DRIVER;
225 goto fail;
226 }
227
228 device->local_fd = fd;
229 device->ws->query_info(device->ws, &device->rad_info);
230 result = radv_init_wsi(device);
231 if (result != VK_SUCCESS) {
232 device->ws->destroy(device->ws);
233 goto fail;
234 }
235
236 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
237 radv_finish_wsi(device);
238 device->ws->destroy(device->ws);
239 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
240 "cannot generate UUID");
241 goto fail;
242 }
243
244 result = radv_extensions_register(instance,
245 &device->extensions,
246 common_device_extensions,
247 ARRAY_SIZE(common_device_extensions));
248 if (result != VK_SUCCESS)
249 goto fail;
250
251 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 device->name = device->rad_info.name;
253
254 return VK_SUCCESS;
255
256 fail:
257 close(fd);
258 return result;
259 }
260
261 static void
262 radv_physical_device_finish(struct radv_physical_device *device)
263 {
264 radv_extensions_finish(device->instance, &device->extensions);
265 radv_finish_wsi(device);
266 device->ws->destroy(device->ws);
267 close(device->local_fd);
268 }
269
270
271 static void *
272 default_alloc_func(void *pUserData, size_t size, size_t align,
273 VkSystemAllocationScope allocationScope)
274 {
275 return malloc(size);
276 }
277
278 static void *
279 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
280 size_t align, VkSystemAllocationScope allocationScope)
281 {
282 return realloc(pOriginal, size);
283 }
284
285 static void
286 default_free_func(void *pUserData, void *pMemory)
287 {
288 free(pMemory);
289 }
290
291 static const VkAllocationCallbacks default_alloc = {
292 .pUserData = NULL,
293 .pfnAllocation = default_alloc_func,
294 .pfnReallocation = default_realloc_func,
295 .pfnFree = default_free_func,
296 };
297
298 static const struct debug_control radv_debug_options[] = {
299 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
300 {"nodcc", RADV_DEBUG_NO_DCC},
301 {"shaders", RADV_DEBUG_DUMP_SHADERS},
302 {"nocache", RADV_DEBUG_NO_CACHE},
303 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
304 {"nohiz", RADV_DEBUG_NO_HIZ},
305 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
306 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
307 {"allbos", RADV_DEBUG_ALL_BOS},
308 {"noibs", RADV_DEBUG_NO_IBS},
309 {NULL, 0}
310 };
311
312 VkResult radv_CreateInstance(
313 const VkInstanceCreateInfo* pCreateInfo,
314 const VkAllocationCallbacks* pAllocator,
315 VkInstance* pInstance)
316 {
317 struct radv_instance *instance;
318
319 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
320
321 uint32_t client_version;
322 if (pCreateInfo->pApplicationInfo &&
323 pCreateInfo->pApplicationInfo->apiVersion != 0) {
324 client_version = pCreateInfo->pApplicationInfo->apiVersion;
325 } else {
326 client_version = VK_MAKE_VERSION(1, 0, 0);
327 }
328
329 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
330 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
331 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
332 "Client requested version %d.%d.%d",
333 VK_VERSION_MAJOR(client_version),
334 VK_VERSION_MINOR(client_version),
335 VK_VERSION_PATCH(client_version));
336 }
337
338 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
339 if (!is_extension_enabled(instance_extensions,
340 ARRAY_SIZE(instance_extensions),
341 pCreateInfo->ppEnabledExtensionNames[i]))
342 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
343 }
344
345 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
346 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
347 if (!instance)
348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
349
350 memset(instance, 0, sizeof(*instance));
351
352 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
353
354 if (pAllocator)
355 instance->alloc = *pAllocator;
356 else
357 instance->alloc = default_alloc;
358
359 instance->apiVersion = client_version;
360 instance->physicalDeviceCount = -1;
361
362 _mesa_locale_init();
363
364 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
365
366 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
367 radv_debug_options);
368
369 *pInstance = radv_instance_to_handle(instance);
370
371 return VK_SUCCESS;
372 }
373
374 void radv_DestroyInstance(
375 VkInstance _instance,
376 const VkAllocationCallbacks* pAllocator)
377 {
378 RADV_FROM_HANDLE(radv_instance, instance, _instance);
379
380 if (!instance)
381 return;
382
383 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
384 radv_physical_device_finish(instance->physicalDevices + i);
385 }
386
387 VG(VALGRIND_DESTROY_MEMPOOL(instance));
388
389 _mesa_locale_fini();
390
391 vk_free(&instance->alloc, instance);
392 }
393
394 static VkResult
395 radv_enumerate_devices(struct radv_instance *instance)
396 {
397 /* TODO: Check for more devices ? */
398 drmDevicePtr devices[8];
399 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
400 int max_devices;
401
402 instance->physicalDeviceCount = 0;
403
404 max_devices = drmGetDevices2(0, devices, sizeof(devices));
405 if (max_devices < 1)
406 return VK_ERROR_INCOMPATIBLE_DRIVER;
407
408 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
409 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
410 devices[i]->bustype == DRM_BUS_PCI &&
411 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
412
413 result = radv_physical_device_init(instance->physicalDevices +
414 instance->physicalDeviceCount,
415 instance,
416 devices[i]->nodes[DRM_NODE_RENDER]);
417 if (result == VK_SUCCESS)
418 ++instance->physicalDeviceCount;
419 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
420 return result;
421 }
422 }
423 return result;
424 }
425
426 VkResult radv_EnumeratePhysicalDevices(
427 VkInstance _instance,
428 uint32_t* pPhysicalDeviceCount,
429 VkPhysicalDevice* pPhysicalDevices)
430 {
431 RADV_FROM_HANDLE(radv_instance, instance, _instance);
432 VkResult result;
433
434 if (instance->physicalDeviceCount < 0) {
435 result = radv_enumerate_devices(instance);
436 if (result != VK_SUCCESS &&
437 result != VK_ERROR_INCOMPATIBLE_DRIVER)
438 return result;
439 }
440
441 if (!pPhysicalDevices) {
442 *pPhysicalDeviceCount = instance->physicalDeviceCount;
443 } else {
444 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
445 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
446 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
447 }
448
449 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
450 : VK_SUCCESS;
451 }
452
453 void radv_GetPhysicalDeviceFeatures(
454 VkPhysicalDevice physicalDevice,
455 VkPhysicalDeviceFeatures* pFeatures)
456 {
457 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
458
459 memset(pFeatures, 0, sizeof(*pFeatures));
460
461 *pFeatures = (VkPhysicalDeviceFeatures) {
462 .robustBufferAccess = true,
463 .fullDrawIndexUint32 = true,
464 .imageCubeArray = true,
465 .independentBlend = true,
466 .geometryShader = true,
467 .tessellationShader = true,
468 .sampleRateShading = false,
469 .dualSrcBlend = true,
470 .logicOp = true,
471 .multiDrawIndirect = true,
472 .drawIndirectFirstInstance = true,
473 .depthClamp = true,
474 .depthBiasClamp = true,
475 .fillModeNonSolid = true,
476 .depthBounds = true,
477 .wideLines = true,
478 .largePoints = true,
479 .alphaToOne = true,
480 .multiViewport = true,
481 .samplerAnisotropy = true,
482 .textureCompressionETC2 = false,
483 .textureCompressionASTC_LDR = false,
484 .textureCompressionBC = true,
485 .occlusionQueryPrecise = true,
486 .pipelineStatisticsQuery = true,
487 .vertexPipelineStoresAndAtomics = true,
488 .fragmentStoresAndAtomics = true,
489 .shaderTessellationAndGeometryPointSize = true,
490 .shaderImageGatherExtended = true,
491 .shaderStorageImageExtendedFormats = true,
492 .shaderStorageImageMultisample = false,
493 .shaderUniformBufferArrayDynamicIndexing = true,
494 .shaderSampledImageArrayDynamicIndexing = true,
495 .shaderStorageBufferArrayDynamicIndexing = true,
496 .shaderStorageImageArrayDynamicIndexing = true,
497 .shaderStorageImageReadWithoutFormat = true,
498 .shaderStorageImageWriteWithoutFormat = true,
499 .shaderClipDistance = true,
500 .shaderCullDistance = true,
501 .shaderFloat64 = true,
502 .shaderInt64 = false,
503 .shaderInt16 = false,
504 .sparseBinding = true,
505 .variableMultisampleRate = true,
506 .inheritedQueries = true,
507 };
508 }
509
510 void radv_GetPhysicalDeviceFeatures2KHR(
511 VkPhysicalDevice physicalDevice,
512 VkPhysicalDeviceFeatures2KHR *pFeatures)
513 {
514 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
515 }
516
517 static uint32_t radv_get_driver_version()
518 {
519 const char *minor_string = strchr(VERSION, '.');
520 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
521 int major = atoi(VERSION);
522 int minor = minor_string ? atoi(minor_string + 1) : 0;
523 int patch = patch_string ? atoi(patch_string + 1) : 0;
524 if (strstr(VERSION, "devel")) {
525 if (patch == 0) {
526 patch = 99;
527 if (minor == 0) {
528 minor = 99;
529 --major;
530 } else
531 --minor;
532 } else
533 --patch;
534 }
535 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
536 return version;
537 }
538
539 void radv_GetPhysicalDeviceProperties(
540 VkPhysicalDevice physicalDevice,
541 VkPhysicalDeviceProperties* pProperties)
542 {
543 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
544 VkSampleCountFlags sample_counts = 0xf;
545 VkPhysicalDeviceLimits limits = {
546 .maxImageDimension1D = (1 << 14),
547 .maxImageDimension2D = (1 << 14),
548 .maxImageDimension3D = (1 << 11),
549 .maxImageDimensionCube = (1 << 14),
550 .maxImageArrayLayers = (1 << 11),
551 .maxTexelBufferElements = 128 * 1024 * 1024,
552 .maxUniformBufferRange = UINT32_MAX,
553 .maxStorageBufferRange = UINT32_MAX,
554 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
555 .maxMemoryAllocationCount = UINT32_MAX,
556 .maxSamplerAllocationCount = 64 * 1024,
557 .bufferImageGranularity = 64, /* A cache line */
558 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
559 .maxBoundDescriptorSets = MAX_SETS,
560 .maxPerStageDescriptorSamplers = (1u << 31) / 16,
561 .maxPerStageDescriptorUniformBuffers = (1u << 31) / 16,
562 .maxPerStageDescriptorStorageBuffers = (1u << 31) / 16,
563 .maxPerStageDescriptorSampledImages = (1u << 31) / 96,
564 .maxPerStageDescriptorStorageImages = (1u << 31) / 64,
565 .maxPerStageDescriptorInputAttachments = (1u << 31) / 64,
566 .maxPerStageResources = (1u << 31) / 32,
567 .maxDescriptorSetSamplers = 256,
568 .maxDescriptorSetUniformBuffers = (1u << 31) / 16,
569 .maxDescriptorSetUniformBuffersDynamic = 8,
570 .maxDescriptorSetStorageBuffers = (1u << 31) / 16,
571 .maxDescriptorSetStorageBuffersDynamic = 8,
572 .maxDescriptorSetSampledImages = (1u << 31) / 96,
573 .maxDescriptorSetStorageImages = (1u << 31) / 64,
574 .maxDescriptorSetInputAttachments = (1u << 31) / 64,
575 .maxVertexInputAttributes = 32,
576 .maxVertexInputBindings = 32,
577 .maxVertexInputAttributeOffset = 2047,
578 .maxVertexInputBindingStride = 2048,
579 .maxVertexOutputComponents = 128,
580 .maxTessellationGenerationLevel = 64,
581 .maxTessellationPatchSize = 32,
582 .maxTessellationControlPerVertexInputComponents = 128,
583 .maxTessellationControlPerVertexOutputComponents = 128,
584 .maxTessellationControlPerPatchOutputComponents = 120,
585 .maxTessellationControlTotalOutputComponents = 4096,
586 .maxTessellationEvaluationInputComponents = 128,
587 .maxTessellationEvaluationOutputComponents = 128,
588 .maxGeometryShaderInvocations = 32,
589 .maxGeometryInputComponents = 64,
590 .maxGeometryOutputComponents = 128,
591 .maxGeometryOutputVertices = 256,
592 .maxGeometryTotalOutputComponents = 1024,
593 .maxFragmentInputComponents = 128,
594 .maxFragmentOutputAttachments = 8,
595 .maxFragmentDualSrcAttachments = 1,
596 .maxFragmentCombinedOutputResources = 8,
597 .maxComputeSharedMemorySize = 32768,
598 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
599 .maxComputeWorkGroupInvocations = 2048,
600 .maxComputeWorkGroupSize = {
601 2048,
602 2048,
603 2048
604 },
605 .subPixelPrecisionBits = 4 /* FIXME */,
606 .subTexelPrecisionBits = 4 /* FIXME */,
607 .mipmapPrecisionBits = 4 /* FIXME */,
608 .maxDrawIndexedIndexValue = UINT32_MAX,
609 .maxDrawIndirectCount = UINT32_MAX,
610 .maxSamplerLodBias = 16,
611 .maxSamplerAnisotropy = 16,
612 .maxViewports = MAX_VIEWPORTS,
613 .maxViewportDimensions = { (1 << 14), (1 << 14) },
614 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
615 .viewportSubPixelBits = 13, /* We take a float? */
616 .minMemoryMapAlignment = 4096, /* A page */
617 .minTexelBufferOffsetAlignment = 1,
618 .minUniformBufferOffsetAlignment = 4,
619 .minStorageBufferOffsetAlignment = 4,
620 .minTexelOffset = -32,
621 .maxTexelOffset = 31,
622 .minTexelGatherOffset = -32,
623 .maxTexelGatherOffset = 31,
624 .minInterpolationOffset = -2,
625 .maxInterpolationOffset = 2,
626 .subPixelInterpolationOffsetBits = 8,
627 .maxFramebufferWidth = (1 << 14),
628 .maxFramebufferHeight = (1 << 14),
629 .maxFramebufferLayers = (1 << 10),
630 .framebufferColorSampleCounts = sample_counts,
631 .framebufferDepthSampleCounts = sample_counts,
632 .framebufferStencilSampleCounts = sample_counts,
633 .framebufferNoAttachmentsSampleCounts = sample_counts,
634 .maxColorAttachments = MAX_RTS,
635 .sampledImageColorSampleCounts = sample_counts,
636 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
637 .sampledImageDepthSampleCounts = sample_counts,
638 .sampledImageStencilSampleCounts = sample_counts,
639 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
640 .maxSampleMaskWords = 1,
641 .timestampComputeAndGraphics = false,
642 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
643 .maxClipDistances = 8,
644 .maxCullDistances = 8,
645 .maxCombinedClipAndCullDistances = 8,
646 .discreteQueuePriorities = 1,
647 .pointSizeRange = { 0.125, 255.875 },
648 .lineWidthRange = { 0.0, 7.9921875 },
649 .pointSizeGranularity = (1.0 / 8.0),
650 .lineWidthGranularity = (1.0 / 128.0),
651 .strictLines = false, /* FINISHME */
652 .standardSampleLocations = true,
653 .optimalBufferCopyOffsetAlignment = 128,
654 .optimalBufferCopyRowPitchAlignment = 128,
655 .nonCoherentAtomSize = 64,
656 };
657
658 *pProperties = (VkPhysicalDeviceProperties) {
659 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
660 .driverVersion = radv_get_driver_version(),
661 .vendorID = 0x1002,
662 .deviceID = pdevice->rad_info.pci_id,
663 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
664 .limits = limits,
665 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
666 };
667
668 strcpy(pProperties->deviceName, pdevice->name);
669 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
670 }
671
672 void radv_GetPhysicalDeviceProperties2KHR(
673 VkPhysicalDevice physicalDevice,
674 VkPhysicalDeviceProperties2KHR *pProperties)
675 {
676 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
677
678 vk_foreach_struct(ext, pProperties->pNext) {
679 switch (ext->sType) {
680 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
681 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
682 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
683 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
684 break;
685 }
686 default:
687 break;
688 }
689 }
690 }
691
692 static void radv_get_physical_device_queue_family_properties(
693 struct radv_physical_device* pdevice,
694 uint32_t* pCount,
695 VkQueueFamilyProperties** pQueueFamilyProperties)
696 {
697 int num_queue_families = 1;
698 int idx;
699 if (pdevice->rad_info.compute_rings > 0 &&
700 pdevice->rad_info.chip_class >= CIK &&
701 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
702 num_queue_families++;
703
704 if (pQueueFamilyProperties == NULL) {
705 *pCount = num_queue_families;
706 return;
707 }
708
709 if (!*pCount)
710 return;
711
712 idx = 0;
713 if (*pCount >= 1) {
714 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
715 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
716 VK_QUEUE_COMPUTE_BIT |
717 VK_QUEUE_TRANSFER_BIT |
718 VK_QUEUE_SPARSE_BINDING_BIT,
719 .queueCount = 1,
720 .timestampValidBits = 64,
721 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
722 };
723 idx++;
724 }
725
726 if (pdevice->rad_info.compute_rings > 0 &&
727 pdevice->rad_info.chip_class >= CIK &&
728 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
729 if (*pCount > idx) {
730 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
731 .queueFlags = VK_QUEUE_COMPUTE_BIT |
732 VK_QUEUE_TRANSFER_BIT |
733 VK_QUEUE_SPARSE_BINDING_BIT,
734 .queueCount = pdevice->rad_info.compute_rings,
735 .timestampValidBits = 64,
736 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
737 };
738 idx++;
739 }
740 }
741 *pCount = idx;
742 }
743
744 void radv_GetPhysicalDeviceQueueFamilyProperties(
745 VkPhysicalDevice physicalDevice,
746 uint32_t* pCount,
747 VkQueueFamilyProperties* pQueueFamilyProperties)
748 {
749 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
750 if (!pQueueFamilyProperties) {
751 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
752 return;
753 }
754 VkQueueFamilyProperties *properties[] = {
755 pQueueFamilyProperties + 0,
756 pQueueFamilyProperties + 1,
757 pQueueFamilyProperties + 2,
758 };
759 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
760 assert(*pCount <= 3);
761 }
762
763 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
764 VkPhysicalDevice physicalDevice,
765 uint32_t* pCount,
766 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
767 {
768 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
769 if (!pQueueFamilyProperties) {
770 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
771 return;
772 }
773 VkQueueFamilyProperties *properties[] = {
774 &pQueueFamilyProperties[0].queueFamilyProperties,
775 &pQueueFamilyProperties[1].queueFamilyProperties,
776 &pQueueFamilyProperties[2].queueFamilyProperties,
777 };
778 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
779 assert(*pCount <= 3);
780 }
781
782 void radv_GetPhysicalDeviceMemoryProperties(
783 VkPhysicalDevice physicalDevice,
784 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
785 {
786 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
787
788 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
789
790 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
791 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
792 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
793 .heapIndex = RADV_MEM_HEAP_VRAM,
794 };
795 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
796 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
797 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
798 .heapIndex = RADV_MEM_HEAP_GTT,
799 };
800 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
801 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
802 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
803 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
804 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
805 };
806 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
807 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
808 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
809 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
810 .heapIndex = RADV_MEM_HEAP_GTT,
811 };
812
813 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
814
815 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
816 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
817 .size = physical_device->rad_info.vram_size -
818 physical_device->rad_info.visible_vram_size,
819 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
820 };
821 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
822 .size = physical_device->rad_info.visible_vram_size,
823 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
824 };
825 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
826 .size = physical_device->rad_info.gart_size,
827 .flags = 0,
828 };
829 }
830
831 void radv_GetPhysicalDeviceMemoryProperties2KHR(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
834 {
835 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
836 &pMemoryProperties->memoryProperties);
837 }
838
839 static int
840 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
841 int queue_family_index, int idx)
842 {
843 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
844 queue->device = device;
845 queue->queue_family_index = queue_family_index;
846 queue->queue_idx = idx;
847
848 queue->hw_ctx = device->ws->ctx_create(device->ws);
849 if (!queue->hw_ctx)
850 return VK_ERROR_OUT_OF_HOST_MEMORY;
851
852 return VK_SUCCESS;
853 }
854
855 static void
856 radv_queue_finish(struct radv_queue *queue)
857 {
858 if (queue->hw_ctx)
859 queue->device->ws->ctx_destroy(queue->hw_ctx);
860
861 if (queue->initial_preamble_cs)
862 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
863 if (queue->continue_preamble_cs)
864 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
865 if (queue->descriptor_bo)
866 queue->device->ws->buffer_destroy(queue->descriptor_bo);
867 if (queue->scratch_bo)
868 queue->device->ws->buffer_destroy(queue->scratch_bo);
869 if (queue->esgs_ring_bo)
870 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
871 if (queue->gsvs_ring_bo)
872 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
873 if (queue->tess_factor_ring_bo)
874 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
875 if (queue->tess_offchip_ring_bo)
876 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
877 if (queue->compute_scratch_bo)
878 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
879 }
880
881 static void
882 radv_device_init_gs_info(struct radv_device *device)
883 {
884 switch (device->physical_device->rad_info.family) {
885 case CHIP_OLAND:
886 case CHIP_HAINAN:
887 case CHIP_KAVERI:
888 case CHIP_KABINI:
889 case CHIP_MULLINS:
890 case CHIP_ICELAND:
891 case CHIP_CARRIZO:
892 case CHIP_STONEY:
893 device->gs_table_depth = 16;
894 return;
895 case CHIP_TAHITI:
896 case CHIP_PITCAIRN:
897 case CHIP_VERDE:
898 case CHIP_BONAIRE:
899 case CHIP_HAWAII:
900 case CHIP_TONGA:
901 case CHIP_FIJI:
902 case CHIP_POLARIS10:
903 case CHIP_POLARIS11:
904 device->gs_table_depth = 32;
905 return;
906 default:
907 unreachable("unknown GPU");
908 }
909 }
910
911 VkResult radv_CreateDevice(
912 VkPhysicalDevice physicalDevice,
913 const VkDeviceCreateInfo* pCreateInfo,
914 const VkAllocationCallbacks* pAllocator,
915 VkDevice* pDevice)
916 {
917 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
918 VkResult result;
919 struct radv_device *device;
920
921 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
922 if (!is_extension_enabled(physical_device->extensions.ext_array,
923 physical_device->extensions.num_ext,
924 pCreateInfo->ppEnabledExtensionNames[i]))
925 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
926 }
927
928 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
929 sizeof(*device), 8,
930 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
931 if (!device)
932 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
933
934 memset(device, 0, sizeof(*device));
935
936 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
937 device->instance = physical_device->instance;
938 device->physical_device = physical_device;
939
940 device->debug_flags = device->instance->debug_flags;
941
942 device->ws = physical_device->ws;
943 if (pAllocator)
944 device->alloc = *pAllocator;
945 else
946 device->alloc = physical_device->instance->alloc;
947
948 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
949 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
950 uint32_t qfi = queue_create->queueFamilyIndex;
951
952 device->queues[qfi] = vk_alloc(&device->alloc,
953 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
954 if (!device->queues[qfi]) {
955 result = VK_ERROR_OUT_OF_HOST_MEMORY;
956 goto fail;
957 }
958
959 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
960
961 device->queue_count[qfi] = queue_create->queueCount;
962
963 for (unsigned q = 0; q < queue_create->queueCount; q++) {
964 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
965 if (result != VK_SUCCESS)
966 goto fail;
967 }
968 }
969
970 #if HAVE_LLVM < 0x0400
971 device->llvm_supports_spill = false;
972 #else
973 device->llvm_supports_spill = true;
974 #endif
975
976 /* The maximum number of scratch waves. Scratch space isn't divided
977 * evenly between CUs. The number is only a function of the number of CUs.
978 * We can decrease the constant to decrease the scratch buffer size.
979 *
980 * sctx->scratch_waves must be >= the maximum posible size of
981 * 1 threadgroup, so that the hw doesn't hang from being unable
982 * to start any.
983 *
984 * The recommended value is 4 per CU at most. Higher numbers don't
985 * bring much benefit, but they still occupy chip resources (think
986 * async compute). I've seen ~2% performance difference between 4 and 32.
987 */
988 uint32_t max_threads_per_block = 2048;
989 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
990 max_threads_per_block / 64);
991
992 radv_device_init_gs_info(device);
993
994 device->tess_offchip_block_dw_size =
995 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
996 device->has_distributed_tess =
997 device->physical_device->rad_info.chip_class >= VI &&
998 device->physical_device->rad_info.max_se >= 2;
999
1000 result = radv_device_init_meta(device);
1001 if (result != VK_SUCCESS)
1002 goto fail;
1003
1004 radv_device_init_msaa(device);
1005
1006 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1007 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1008 switch (family) {
1009 case RADV_QUEUE_GENERAL:
1010 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1011 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1012 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1013 break;
1014 case RADV_QUEUE_COMPUTE:
1015 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1016 radeon_emit(device->empty_cs[family], 0);
1017 break;
1018 }
1019 device->ws->cs_finalize(device->empty_cs[family]);
1020
1021 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1022 switch (family) {
1023 case RADV_QUEUE_GENERAL:
1024 case RADV_QUEUE_COMPUTE:
1025 si_cs_emit_cache_flush(device->flush_cs[family],
1026 device->physical_device->rad_info.chip_class,
1027 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1028 RADV_CMD_FLAG_INV_ICACHE |
1029 RADV_CMD_FLAG_INV_SMEM_L1 |
1030 RADV_CMD_FLAG_INV_VMEM_L1 |
1031 RADV_CMD_FLAG_INV_GLOBAL_L2);
1032 break;
1033 }
1034 device->ws->cs_finalize(device->flush_cs[family]);
1035 }
1036
1037 if (getenv("RADV_TRACE_FILE")) {
1038 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1039 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1040 if (!device->trace_bo)
1041 goto fail;
1042
1043 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1044 if (!device->trace_id_ptr)
1045 goto fail;
1046 }
1047
1048 if (device->physical_device->rad_info.chip_class >= CIK)
1049 cik_create_gfx_config(device);
1050
1051 VkPipelineCacheCreateInfo ci;
1052 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1053 ci.pNext = NULL;
1054 ci.flags = 0;
1055 ci.pInitialData = NULL;
1056 ci.initialDataSize = 0;
1057 VkPipelineCache pc;
1058 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1059 &ci, NULL, &pc);
1060 if (result != VK_SUCCESS)
1061 goto fail;
1062
1063 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1064
1065 *pDevice = radv_device_to_handle(device);
1066 return VK_SUCCESS;
1067
1068 fail:
1069 if (device->trace_bo)
1070 device->ws->buffer_destroy(device->trace_bo);
1071
1072 if (device->gfx_init)
1073 device->ws->buffer_destroy(device->gfx_init);
1074
1075 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1076 for (unsigned q = 0; q < device->queue_count[i]; q++)
1077 radv_queue_finish(&device->queues[i][q]);
1078 if (device->queue_count[i])
1079 vk_free(&device->alloc, device->queues[i]);
1080 }
1081
1082 vk_free(&device->alloc, device);
1083 return result;
1084 }
1085
1086 void radv_DestroyDevice(
1087 VkDevice _device,
1088 const VkAllocationCallbacks* pAllocator)
1089 {
1090 RADV_FROM_HANDLE(radv_device, device, _device);
1091
1092 if (!device)
1093 return;
1094
1095 if (device->trace_bo)
1096 device->ws->buffer_destroy(device->trace_bo);
1097
1098 if (device->gfx_init)
1099 device->ws->buffer_destroy(device->gfx_init);
1100
1101 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1102 for (unsigned q = 0; q < device->queue_count[i]; q++)
1103 radv_queue_finish(&device->queues[i][q]);
1104 if (device->queue_count[i])
1105 vk_free(&device->alloc, device->queues[i]);
1106 if (device->empty_cs[i])
1107 device->ws->cs_destroy(device->empty_cs[i]);
1108 if (device->flush_cs[i])
1109 device->ws->cs_destroy(device->flush_cs[i]);
1110 }
1111 radv_device_finish_meta(device);
1112
1113 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1114 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1115
1116 vk_free(&device->alloc, device);
1117 }
1118
1119 VkResult radv_EnumerateInstanceExtensionProperties(
1120 const char* pLayerName,
1121 uint32_t* pPropertyCount,
1122 VkExtensionProperties* pProperties)
1123 {
1124 if (pProperties == NULL) {
1125 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1126 return VK_SUCCESS;
1127 }
1128
1129 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1130 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1131
1132 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1133 return VK_INCOMPLETE;
1134
1135 return VK_SUCCESS;
1136 }
1137
1138 VkResult radv_EnumerateDeviceExtensionProperties(
1139 VkPhysicalDevice physicalDevice,
1140 const char* pLayerName,
1141 uint32_t* pPropertyCount,
1142 VkExtensionProperties* pProperties)
1143 {
1144 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1145
1146 if (pProperties == NULL) {
1147 *pPropertyCount = pdevice->extensions.num_ext;
1148 return VK_SUCCESS;
1149 }
1150
1151 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1152 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1153
1154 if (*pPropertyCount < pdevice->extensions.num_ext)
1155 return VK_INCOMPLETE;
1156
1157 return VK_SUCCESS;
1158 }
1159
1160 VkResult radv_EnumerateInstanceLayerProperties(
1161 uint32_t* pPropertyCount,
1162 VkLayerProperties* pProperties)
1163 {
1164 if (pProperties == NULL) {
1165 *pPropertyCount = 0;
1166 return VK_SUCCESS;
1167 }
1168
1169 /* None supported at this time */
1170 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1171 }
1172
1173 VkResult radv_EnumerateDeviceLayerProperties(
1174 VkPhysicalDevice physicalDevice,
1175 uint32_t* pPropertyCount,
1176 VkLayerProperties* pProperties)
1177 {
1178 if (pProperties == NULL) {
1179 *pPropertyCount = 0;
1180 return VK_SUCCESS;
1181 }
1182
1183 /* None supported at this time */
1184 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1185 }
1186
1187 void radv_GetDeviceQueue(
1188 VkDevice _device,
1189 uint32_t queueFamilyIndex,
1190 uint32_t queueIndex,
1191 VkQueue* pQueue)
1192 {
1193 RADV_FROM_HANDLE(radv_device, device, _device);
1194
1195 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1196 }
1197
1198 static void radv_dump_trace(struct radv_device *device,
1199 struct radeon_winsys_cs *cs)
1200 {
1201 const char *filename = getenv("RADV_TRACE_FILE");
1202 FILE *f = fopen(filename, "w");
1203 if (!f) {
1204 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1205 return;
1206 }
1207
1208 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1209 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1210 fclose(f);
1211 }
1212
1213 static void
1214 fill_geom_tess_rings(struct radv_queue *queue,
1215 uint32_t *map,
1216 bool add_sample_positions,
1217 uint32_t esgs_ring_size,
1218 struct radeon_winsys_bo *esgs_ring_bo,
1219 uint32_t gsvs_ring_size,
1220 struct radeon_winsys_bo *gsvs_ring_bo,
1221 uint32_t tess_factor_ring_size,
1222 struct radeon_winsys_bo *tess_factor_ring_bo,
1223 uint32_t tess_offchip_ring_size,
1224 struct radeon_winsys_bo *tess_offchip_ring_bo)
1225 {
1226 uint64_t esgs_va = 0, gsvs_va = 0;
1227 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1228 uint32_t *desc = &map[4];
1229
1230 if (esgs_ring_bo)
1231 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1232 if (gsvs_ring_bo)
1233 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1234 if (tess_factor_ring_bo)
1235 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1236 if (tess_offchip_ring_bo)
1237 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1238
1239 /* stride 0, num records - size, add tid, swizzle, elsize4,
1240 index stride 64 */
1241 desc[0] = esgs_va;
1242 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1243 S_008F04_STRIDE(0) |
1244 S_008F04_SWIZZLE_ENABLE(true);
1245 desc[2] = esgs_ring_size;
1246 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1247 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1248 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1249 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1250 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1251 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1252 S_008F0C_ELEMENT_SIZE(1) |
1253 S_008F0C_INDEX_STRIDE(3) |
1254 S_008F0C_ADD_TID_ENABLE(true);
1255
1256 desc += 4;
1257 /* GS entry for ES->GS ring */
1258 /* stride 0, num records - size, elsize0,
1259 index stride 0 */
1260 desc[0] = esgs_va;
1261 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1262 S_008F04_STRIDE(0) |
1263 S_008F04_SWIZZLE_ENABLE(false);
1264 desc[2] = esgs_ring_size;
1265 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1266 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1267 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1268 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1269 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1270 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1271 S_008F0C_ELEMENT_SIZE(0) |
1272 S_008F0C_INDEX_STRIDE(0) |
1273 S_008F0C_ADD_TID_ENABLE(false);
1274
1275 desc += 4;
1276 /* VS entry for GS->VS ring */
1277 /* stride 0, num records - size, elsize0,
1278 index stride 0 */
1279 desc[0] = gsvs_va;
1280 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1281 S_008F04_STRIDE(0) |
1282 S_008F04_SWIZZLE_ENABLE(false);
1283 desc[2] = gsvs_ring_size;
1284 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1288 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1290 S_008F0C_ELEMENT_SIZE(0) |
1291 S_008F0C_INDEX_STRIDE(0) |
1292 S_008F0C_ADD_TID_ENABLE(false);
1293 desc += 4;
1294
1295 /* stride gsvs_itemsize, num records 64
1296 elsize 4, index stride 16 */
1297 /* shader will patch stride and desc[2] */
1298 desc[0] = gsvs_va;
1299 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1300 S_008F04_STRIDE(0) |
1301 S_008F04_SWIZZLE_ENABLE(true);
1302 desc[2] = 0;
1303 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1304 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1305 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1306 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1307 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1308 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1309 S_008F0C_ELEMENT_SIZE(1) |
1310 S_008F0C_INDEX_STRIDE(1) |
1311 S_008F0C_ADD_TID_ENABLE(true);
1312 desc += 4;
1313
1314 desc[0] = tess_factor_va;
1315 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1316 S_008F04_STRIDE(0) |
1317 S_008F04_SWIZZLE_ENABLE(false);
1318 desc[2] = tess_factor_ring_size;
1319 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1320 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1321 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1322 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1323 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1325 S_008F0C_ELEMENT_SIZE(0) |
1326 S_008F0C_INDEX_STRIDE(0) |
1327 S_008F0C_ADD_TID_ENABLE(false);
1328 desc += 4;
1329
1330 desc[0] = tess_offchip_va;
1331 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1332 S_008F04_STRIDE(0) |
1333 S_008F04_SWIZZLE_ENABLE(false);
1334 desc[2] = tess_offchip_ring_size;
1335 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1336 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1337 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1338 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1339 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1340 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1341 S_008F0C_ELEMENT_SIZE(0) |
1342 S_008F0C_INDEX_STRIDE(0) |
1343 S_008F0C_ADD_TID_ENABLE(false);
1344 desc += 4;
1345
1346 /* add sample positions after all rings */
1347 memcpy(desc, queue->device->sample_locations_1x, 8);
1348 desc += 2;
1349 memcpy(desc, queue->device->sample_locations_2x, 16);
1350 desc += 4;
1351 memcpy(desc, queue->device->sample_locations_4x, 32);
1352 desc += 8;
1353 memcpy(desc, queue->device->sample_locations_8x, 64);
1354 desc += 16;
1355 memcpy(desc, queue->device->sample_locations_16x, 128);
1356 }
1357
1358 static unsigned
1359 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1360 {
1361 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1362 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1363 device->physical_device->rad_info.family != CHIP_STONEY;
1364 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1365 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1366 device->physical_device->rad_info.max_se;
1367 unsigned offchip_granularity;
1368 unsigned hs_offchip_param;
1369 switch (device->tess_offchip_block_dw_size) {
1370 default:
1371 assert(0);
1372 /* fall through */
1373 case 8192:
1374 offchip_granularity = V_03093C_X_8K_DWORDS;
1375 break;
1376 case 4096:
1377 offchip_granularity = V_03093C_X_4K_DWORDS;
1378 break;
1379 }
1380
1381 switch (device->physical_device->rad_info.chip_class) {
1382 case SI:
1383 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1384 break;
1385 case CIK:
1386 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1387 break;
1388 case VI:
1389 default:
1390 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
1391 break;
1392 }
1393
1394 *max_offchip_buffers_p = max_offchip_buffers;
1395 if (device->physical_device->rad_info.chip_class >= CIK) {
1396 if (device->physical_device->rad_info.chip_class >= VI)
1397 --max_offchip_buffers;
1398 hs_offchip_param =
1399 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1400 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1401 } else {
1402 hs_offchip_param =
1403 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1404 }
1405 return hs_offchip_param;
1406 }
1407
1408 static VkResult
1409 radv_get_preamble_cs(struct radv_queue *queue,
1410 uint32_t scratch_size,
1411 uint32_t compute_scratch_size,
1412 uint32_t esgs_ring_size,
1413 uint32_t gsvs_ring_size,
1414 bool needs_tess_rings,
1415 bool needs_sample_positions,
1416 struct radeon_winsys_cs **initial_preamble_cs,
1417 struct radeon_winsys_cs **continue_preamble_cs)
1418 {
1419 struct radeon_winsys_bo *scratch_bo = NULL;
1420 struct radeon_winsys_bo *descriptor_bo = NULL;
1421 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1422 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1423 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1424 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1425 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1426 struct radeon_winsys_cs *dest_cs[2] = {0};
1427 bool add_tess_rings = false, add_sample_positions = false;
1428 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1429 unsigned max_offchip_buffers;
1430 unsigned hs_offchip_param = 0;
1431 if (!queue->has_tess_rings) {
1432 if (needs_tess_rings)
1433 add_tess_rings = true;
1434 }
1435 if (!queue->has_sample_positions) {
1436 if (needs_sample_positions)
1437 add_sample_positions = true;
1438 }
1439 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1440 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1441 &max_offchip_buffers);
1442 tess_offchip_ring_size = max_offchip_buffers *
1443 queue->device->tess_offchip_block_dw_size * 4;
1444
1445 if (scratch_size <= queue->scratch_size &&
1446 compute_scratch_size <= queue->compute_scratch_size &&
1447 esgs_ring_size <= queue->esgs_ring_size &&
1448 gsvs_ring_size <= queue->gsvs_ring_size &&
1449 !add_tess_rings && !add_sample_positions &&
1450 queue->initial_preamble_cs) {
1451 *initial_preamble_cs = queue->initial_preamble_cs;
1452 *continue_preamble_cs = queue->continue_preamble_cs;
1453 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1454 *continue_preamble_cs = NULL;
1455 return VK_SUCCESS;
1456 }
1457
1458 if (scratch_size > queue->scratch_size) {
1459 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1460 scratch_size,
1461 4096,
1462 RADEON_DOMAIN_VRAM,
1463 RADEON_FLAG_NO_CPU_ACCESS);
1464 if (!scratch_bo)
1465 goto fail;
1466 } else
1467 scratch_bo = queue->scratch_bo;
1468
1469 if (compute_scratch_size > queue->compute_scratch_size) {
1470 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1471 compute_scratch_size,
1472 4096,
1473 RADEON_DOMAIN_VRAM,
1474 RADEON_FLAG_NO_CPU_ACCESS);
1475 if (!compute_scratch_bo)
1476 goto fail;
1477
1478 } else
1479 compute_scratch_bo = queue->compute_scratch_bo;
1480
1481 if (esgs_ring_size > queue->esgs_ring_size) {
1482 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1483 esgs_ring_size,
1484 4096,
1485 RADEON_DOMAIN_VRAM,
1486 RADEON_FLAG_NO_CPU_ACCESS);
1487 if (!esgs_ring_bo)
1488 goto fail;
1489 } else {
1490 esgs_ring_bo = queue->esgs_ring_bo;
1491 esgs_ring_size = queue->esgs_ring_size;
1492 }
1493
1494 if (gsvs_ring_size > queue->gsvs_ring_size) {
1495 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1496 gsvs_ring_size,
1497 4096,
1498 RADEON_DOMAIN_VRAM,
1499 RADEON_FLAG_NO_CPU_ACCESS);
1500 if (!gsvs_ring_bo)
1501 goto fail;
1502 } else {
1503 gsvs_ring_bo = queue->gsvs_ring_bo;
1504 gsvs_ring_size = queue->gsvs_ring_size;
1505 }
1506
1507 if (add_tess_rings) {
1508 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1509 tess_factor_ring_size,
1510 256,
1511 RADEON_DOMAIN_VRAM,
1512 RADEON_FLAG_NO_CPU_ACCESS);
1513 if (!tess_factor_ring_bo)
1514 goto fail;
1515 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1516 tess_offchip_ring_size,
1517 256,
1518 RADEON_DOMAIN_VRAM,
1519 RADEON_FLAG_NO_CPU_ACCESS);
1520 if (!tess_offchip_ring_bo)
1521 goto fail;
1522 } else {
1523 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1524 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1525 }
1526
1527 if (scratch_bo != queue->scratch_bo ||
1528 esgs_ring_bo != queue->esgs_ring_bo ||
1529 gsvs_ring_bo != queue->gsvs_ring_bo ||
1530 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1531 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1532 uint32_t size = 0;
1533 if (gsvs_ring_bo || esgs_ring_bo ||
1534 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1535 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1536 if (add_sample_positions)
1537 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1538 }
1539 else if (scratch_bo)
1540 size = 8; /* 2 dword */
1541
1542 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1543 size,
1544 4096,
1545 RADEON_DOMAIN_VRAM,
1546 RADEON_FLAG_CPU_ACCESS);
1547 if (!descriptor_bo)
1548 goto fail;
1549 } else
1550 descriptor_bo = queue->descriptor_bo;
1551
1552 for(int i = 0; i < 2; ++i) {
1553 struct radeon_winsys_cs *cs = NULL;
1554 cs = queue->device->ws->cs_create(queue->device->ws,
1555 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1556 if (!cs)
1557 goto fail;
1558
1559 dest_cs[i] = cs;
1560
1561 if (scratch_bo)
1562 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1563
1564 if (esgs_ring_bo)
1565 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1566
1567 if (gsvs_ring_bo)
1568 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1569
1570 if (tess_factor_ring_bo)
1571 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1572
1573 if (tess_offchip_ring_bo)
1574 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1575
1576 if (descriptor_bo)
1577 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1578
1579 if (descriptor_bo != queue->descriptor_bo) {
1580 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1581
1582 if (scratch_bo) {
1583 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1584 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1585 S_008F04_SWIZZLE_ENABLE(1);
1586 map[0] = scratch_va;
1587 map[1] = rsrc1;
1588 }
1589
1590 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1591 add_sample_positions)
1592 fill_geom_tess_rings(queue, map, add_sample_positions,
1593 esgs_ring_size, esgs_ring_bo,
1594 gsvs_ring_size, gsvs_ring_bo,
1595 tess_factor_ring_size, tess_factor_ring_bo,
1596 tess_offchip_ring_size, tess_offchip_ring_bo);
1597
1598 queue->device->ws->buffer_unmap(descriptor_bo);
1599 }
1600
1601 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1602 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1603 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1604 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1605 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1606 }
1607
1608 if (esgs_ring_bo || gsvs_ring_bo) {
1609 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1610 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1611 radeon_emit(cs, esgs_ring_size >> 8);
1612 radeon_emit(cs, gsvs_ring_size >> 8);
1613 } else {
1614 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1615 radeon_emit(cs, esgs_ring_size >> 8);
1616 radeon_emit(cs, gsvs_ring_size >> 8);
1617 }
1618 }
1619
1620 if (tess_factor_ring_bo) {
1621 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1622 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1623 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1624 S_030938_SIZE(tess_factor_ring_size / 4));
1625 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1626 tf_va >> 8);
1627 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1628 } else {
1629 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1630 S_008988_SIZE(tess_factor_ring_size / 4));
1631 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1632 tf_va >> 8);
1633 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1634 hs_offchip_param);
1635 }
1636 }
1637
1638 if (descriptor_bo) {
1639 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1640 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1641 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1642 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1643 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1644 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1645
1646 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1647
1648 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1649 radeon_set_sh_reg_seq(cs, regs[i], 2);
1650 radeon_emit(cs, va);
1651 radeon_emit(cs, va >> 32);
1652 }
1653 }
1654
1655 if (compute_scratch_bo) {
1656 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1657 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1658 S_008F04_SWIZZLE_ENABLE(1);
1659
1660 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1661
1662 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1663 radeon_emit(cs, scratch_va);
1664 radeon_emit(cs, rsrc1);
1665 }
1666
1667 if (!i) {
1668 si_cs_emit_cache_flush(cs,
1669 queue->device->physical_device->rad_info.chip_class,
1670 queue->queue_family_index == RING_COMPUTE &&
1671 queue->device->physical_device->rad_info.chip_class >= CIK,
1672 RADV_CMD_FLAG_INV_ICACHE |
1673 RADV_CMD_FLAG_INV_SMEM_L1 |
1674 RADV_CMD_FLAG_INV_VMEM_L1 |
1675 RADV_CMD_FLAG_INV_GLOBAL_L2);
1676 }
1677
1678 if (!queue->device->ws->cs_finalize(cs))
1679 goto fail;
1680 }
1681
1682 if (queue->initial_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1684
1685 if (queue->continue_preamble_cs)
1686 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1687
1688 queue->initial_preamble_cs = dest_cs[0];
1689 queue->continue_preamble_cs = dest_cs[1];
1690
1691 if (scratch_bo != queue->scratch_bo) {
1692 if (queue->scratch_bo)
1693 queue->device->ws->buffer_destroy(queue->scratch_bo);
1694 queue->scratch_bo = scratch_bo;
1695 queue->scratch_size = scratch_size;
1696 }
1697
1698 if (compute_scratch_bo != queue->compute_scratch_bo) {
1699 if (queue->compute_scratch_bo)
1700 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1701 queue->compute_scratch_bo = compute_scratch_bo;
1702 queue->compute_scratch_size = compute_scratch_size;
1703 }
1704
1705 if (esgs_ring_bo != queue->esgs_ring_bo) {
1706 if (queue->esgs_ring_bo)
1707 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1708 queue->esgs_ring_bo = esgs_ring_bo;
1709 queue->esgs_ring_size = esgs_ring_size;
1710 }
1711
1712 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1713 if (queue->gsvs_ring_bo)
1714 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1715 queue->gsvs_ring_bo = gsvs_ring_bo;
1716 queue->gsvs_ring_size = gsvs_ring_size;
1717 }
1718
1719 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1720 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1721 }
1722
1723 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1724 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1725 queue->has_tess_rings = true;
1726 }
1727
1728 if (descriptor_bo != queue->descriptor_bo) {
1729 if (queue->descriptor_bo)
1730 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1731
1732 queue->descriptor_bo = descriptor_bo;
1733 }
1734
1735 if (add_sample_positions)
1736 queue->has_sample_positions = true;
1737
1738 *initial_preamble_cs = queue->initial_preamble_cs;
1739 *continue_preamble_cs = queue->continue_preamble_cs;
1740 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1741 *continue_preamble_cs = NULL;
1742 return VK_SUCCESS;
1743 fail:
1744 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1745 if (dest_cs[i])
1746 queue->device->ws->cs_destroy(dest_cs[i]);
1747 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1748 queue->device->ws->buffer_destroy(descriptor_bo);
1749 if (scratch_bo && scratch_bo != queue->scratch_bo)
1750 queue->device->ws->buffer_destroy(scratch_bo);
1751 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1752 queue->device->ws->buffer_destroy(compute_scratch_bo);
1753 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1754 queue->device->ws->buffer_destroy(esgs_ring_bo);
1755 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1756 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1757 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1758 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1759 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1760 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1761 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1762 }
1763
1764 VkResult radv_QueueSubmit(
1765 VkQueue _queue,
1766 uint32_t submitCount,
1767 const VkSubmitInfo* pSubmits,
1768 VkFence _fence)
1769 {
1770 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1771 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1772 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1773 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1774 int ret;
1775 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1776 uint32_t scratch_size = 0;
1777 uint32_t compute_scratch_size = 0;
1778 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1779 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1780 VkResult result;
1781 bool fence_emitted = false;
1782 bool tess_rings_needed = false;
1783 bool sample_positions_needed = false;
1784
1785 /* Do this first so failing to allocate scratch buffers can't result in
1786 * partially executed submissions. */
1787 for (uint32_t i = 0; i < submitCount; i++) {
1788 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1789 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1790 pSubmits[i].pCommandBuffers[j]);
1791
1792 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1793 compute_scratch_size = MAX2(compute_scratch_size,
1794 cmd_buffer->compute_scratch_size_needed);
1795 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1796 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1797 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1798 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1799 }
1800 }
1801
1802 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1803 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1804 sample_positions_needed,
1805 &initial_preamble_cs, &continue_preamble_cs);
1806 if (result != VK_SUCCESS)
1807 return result;
1808
1809 for (uint32_t i = 0; i < submitCount; i++) {
1810 struct radeon_winsys_cs **cs_array;
1811 bool do_flush = !i;
1812 bool can_patch = !do_flush;
1813 uint32_t advance;
1814
1815 if (!pSubmits[i].commandBufferCount) {
1816 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1817 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1818 &queue->device->empty_cs[queue->queue_family_index],
1819 1, NULL, NULL,
1820 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1821 pSubmits[i].waitSemaphoreCount,
1822 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1823 pSubmits[i].signalSemaphoreCount,
1824 false, base_fence);
1825 if (ret) {
1826 radv_loge("failed to submit CS %d\n", i);
1827 abort();
1828 }
1829 fence_emitted = true;
1830 }
1831 continue;
1832 }
1833
1834 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1835 (pSubmits[i].commandBufferCount + do_flush));
1836
1837 if(do_flush)
1838 cs_array[0] = queue->device->flush_cs[queue->queue_family_index];
1839
1840 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1842 pSubmits[i].pCommandBuffers[j]);
1843 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1844
1845 cs_array[j + do_flush] = cmd_buffer->cs;
1846 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1847 can_patch = false;
1848 }
1849
1850 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1851 advance = MIN2(max_cs_submission,
1852 pSubmits[i].commandBufferCount + do_flush - j);
1853 bool b = j == 0;
1854 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1855
1856 if (queue->device->trace_bo)
1857 *queue->device->trace_id_ptr = 0;
1858
1859 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1860 advance, initial_preamble_cs, continue_preamble_cs,
1861 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1862 b ? pSubmits[i].waitSemaphoreCount : 0,
1863 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1864 e ? pSubmits[i].signalSemaphoreCount : 0,
1865 can_patch, base_fence);
1866
1867 if (ret) {
1868 radv_loge("failed to submit CS %d\n", i);
1869 abort();
1870 }
1871 fence_emitted = true;
1872 if (queue->device->trace_bo) {
1873 bool success = queue->device->ws->ctx_wait_idle(
1874 queue->hw_ctx,
1875 radv_queue_family_to_ring(
1876 queue->queue_family_index),
1877 queue->queue_idx);
1878
1879 if (!success) { /* Hang */
1880 radv_dump_trace(queue->device, cs_array[j]);
1881 abort();
1882 }
1883 }
1884 }
1885 free(cs_array);
1886 }
1887
1888 if (fence) {
1889 if (!fence_emitted)
1890 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1891 &queue->device->empty_cs[queue->queue_family_index],
1892 1, NULL, NULL, NULL, 0, NULL, 0,
1893 false, base_fence);
1894
1895 fence->submitted = true;
1896 }
1897
1898 return VK_SUCCESS;
1899 }
1900
1901 VkResult radv_QueueWaitIdle(
1902 VkQueue _queue)
1903 {
1904 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1905
1906 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1907 radv_queue_family_to_ring(queue->queue_family_index),
1908 queue->queue_idx);
1909 return VK_SUCCESS;
1910 }
1911
1912 VkResult radv_DeviceWaitIdle(
1913 VkDevice _device)
1914 {
1915 RADV_FROM_HANDLE(radv_device, device, _device);
1916
1917 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1918 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1919 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1920 }
1921 }
1922 return VK_SUCCESS;
1923 }
1924
1925 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1926 VkInstance instance,
1927 const char* pName)
1928 {
1929 return radv_lookup_entrypoint(pName);
1930 }
1931
1932 /* The loader wants us to expose a second GetInstanceProcAddr function
1933 * to work around certain LD_PRELOAD issues seen in apps.
1934 */
1935 PUBLIC
1936 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1937 VkInstance instance,
1938 const char* pName);
1939
1940 PUBLIC
1941 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1942 VkInstance instance,
1943 const char* pName)
1944 {
1945 return radv_GetInstanceProcAddr(instance, pName);
1946 }
1947
1948 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1949 VkDevice device,
1950 const char* pName)
1951 {
1952 return radv_lookup_entrypoint(pName);
1953 }
1954
1955 bool radv_get_memory_fd(struct radv_device *device,
1956 struct radv_device_memory *memory,
1957 int *pFD)
1958 {
1959 struct radeon_bo_metadata metadata;
1960
1961 if (memory->image) {
1962 radv_init_metadata(device, memory->image, &metadata);
1963 device->ws->buffer_set_metadata(memory->bo, &metadata);
1964 }
1965
1966 return device->ws->buffer_get_fd(device->ws, memory->bo,
1967 pFD);
1968 }
1969
1970 VkResult radv_AllocateMemory(
1971 VkDevice _device,
1972 const VkMemoryAllocateInfo* pAllocateInfo,
1973 const VkAllocationCallbacks* pAllocator,
1974 VkDeviceMemory* pMem)
1975 {
1976 RADV_FROM_HANDLE(radv_device, device, _device);
1977 struct radv_device_memory *mem;
1978 VkResult result;
1979 enum radeon_bo_domain domain;
1980 uint32_t flags = 0;
1981 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
1982 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1983
1984 if (pAllocateInfo->allocationSize == 0) {
1985 /* Apparently, this is allowed */
1986 *pMem = VK_NULL_HANDLE;
1987 return VK_SUCCESS;
1988 }
1989
1990 vk_foreach_struct(ext, pAllocateInfo->pNext) {
1991 switch (ext->sType) {
1992 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
1993 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
1994 break;
1995 default:
1996 break;
1997 }
1998 }
1999
2000 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2001 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2002 if (mem == NULL)
2003 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2004
2005 if (dedicate_info) {
2006 mem->image = radv_image_from_handle(dedicate_info->image);
2007 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2008 } else {
2009 mem->image = NULL;
2010 mem->buffer = NULL;
2011 }
2012
2013 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2014 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2015 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2016 domain = RADEON_DOMAIN_GTT;
2017 else
2018 domain = RADEON_DOMAIN_VRAM;
2019
2020 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2021 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2022 else
2023 flags |= RADEON_FLAG_CPU_ACCESS;
2024
2025 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2026 flags |= RADEON_FLAG_GTT_WC;
2027
2028 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2029 domain, flags);
2030
2031 if (!mem->bo) {
2032 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2033 goto fail;
2034 }
2035 mem->type_index = pAllocateInfo->memoryTypeIndex;
2036
2037 *pMem = radv_device_memory_to_handle(mem);
2038
2039 return VK_SUCCESS;
2040
2041 fail:
2042 vk_free2(&device->alloc, pAllocator, mem);
2043
2044 return result;
2045 }
2046
2047 void radv_FreeMemory(
2048 VkDevice _device,
2049 VkDeviceMemory _mem,
2050 const VkAllocationCallbacks* pAllocator)
2051 {
2052 RADV_FROM_HANDLE(radv_device, device, _device);
2053 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2054
2055 if (mem == NULL)
2056 return;
2057
2058 device->ws->buffer_destroy(mem->bo);
2059 mem->bo = NULL;
2060
2061 vk_free2(&device->alloc, pAllocator, mem);
2062 }
2063
2064 VkResult radv_MapMemory(
2065 VkDevice _device,
2066 VkDeviceMemory _memory,
2067 VkDeviceSize offset,
2068 VkDeviceSize size,
2069 VkMemoryMapFlags flags,
2070 void** ppData)
2071 {
2072 RADV_FROM_HANDLE(radv_device, device, _device);
2073 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2074
2075 if (mem == NULL) {
2076 *ppData = NULL;
2077 return VK_SUCCESS;
2078 }
2079
2080 *ppData = device->ws->buffer_map(mem->bo);
2081 if (*ppData) {
2082 *ppData += offset;
2083 return VK_SUCCESS;
2084 }
2085
2086 return VK_ERROR_MEMORY_MAP_FAILED;
2087 }
2088
2089 void radv_UnmapMemory(
2090 VkDevice _device,
2091 VkDeviceMemory _memory)
2092 {
2093 RADV_FROM_HANDLE(radv_device, device, _device);
2094 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2095
2096 if (mem == NULL)
2097 return;
2098
2099 device->ws->buffer_unmap(mem->bo);
2100 }
2101
2102 VkResult radv_FlushMappedMemoryRanges(
2103 VkDevice _device,
2104 uint32_t memoryRangeCount,
2105 const VkMappedMemoryRange* pMemoryRanges)
2106 {
2107 return VK_SUCCESS;
2108 }
2109
2110 VkResult radv_InvalidateMappedMemoryRanges(
2111 VkDevice _device,
2112 uint32_t memoryRangeCount,
2113 const VkMappedMemoryRange* pMemoryRanges)
2114 {
2115 return VK_SUCCESS;
2116 }
2117
2118 void radv_GetBufferMemoryRequirements(
2119 VkDevice device,
2120 VkBuffer _buffer,
2121 VkMemoryRequirements* pMemoryRequirements)
2122 {
2123 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2124
2125 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2126
2127 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2128 pMemoryRequirements->alignment = 4096;
2129 else
2130 pMemoryRequirements->alignment = 16;
2131
2132 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2133 }
2134
2135 void radv_GetImageMemoryRequirements(
2136 VkDevice device,
2137 VkImage _image,
2138 VkMemoryRequirements* pMemoryRequirements)
2139 {
2140 RADV_FROM_HANDLE(radv_image, image, _image);
2141
2142 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2143
2144 pMemoryRequirements->size = image->size;
2145 pMemoryRequirements->alignment = image->alignment;
2146 }
2147
2148 void radv_GetImageSparseMemoryRequirements(
2149 VkDevice device,
2150 VkImage image,
2151 uint32_t* pSparseMemoryRequirementCount,
2152 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2153 {
2154 stub();
2155 }
2156
2157 void radv_GetDeviceMemoryCommitment(
2158 VkDevice device,
2159 VkDeviceMemory memory,
2160 VkDeviceSize* pCommittedMemoryInBytes)
2161 {
2162 *pCommittedMemoryInBytes = 0;
2163 }
2164
2165 VkResult radv_BindBufferMemory(
2166 VkDevice device,
2167 VkBuffer _buffer,
2168 VkDeviceMemory _memory,
2169 VkDeviceSize memoryOffset)
2170 {
2171 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2172 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2173
2174 if (mem) {
2175 buffer->bo = mem->bo;
2176 buffer->offset = memoryOffset;
2177 } else {
2178 buffer->bo = NULL;
2179 buffer->offset = 0;
2180 }
2181
2182 return VK_SUCCESS;
2183 }
2184
2185 VkResult radv_BindImageMemory(
2186 VkDevice device,
2187 VkImage _image,
2188 VkDeviceMemory _memory,
2189 VkDeviceSize memoryOffset)
2190 {
2191 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2192 RADV_FROM_HANDLE(radv_image, image, _image);
2193
2194 if (mem) {
2195 image->bo = mem->bo;
2196 image->offset = memoryOffset;
2197 } else {
2198 image->bo = NULL;
2199 image->offset = 0;
2200 }
2201
2202 return VK_SUCCESS;
2203 }
2204
2205
2206 static void
2207 radv_sparse_buffer_bind_memory(struct radv_device *device,
2208 const VkSparseBufferMemoryBindInfo *bind)
2209 {
2210 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2211
2212 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2213 struct radv_device_memory *mem = NULL;
2214
2215 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2216 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2217
2218 device->ws->buffer_virtual_bind(buffer->bo,
2219 bind->pBinds[i].resourceOffset,
2220 bind->pBinds[i].size,
2221 mem ? mem->bo : NULL,
2222 bind->pBinds[i].memoryOffset);
2223 }
2224 }
2225
2226 static void
2227 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2228 const VkSparseImageOpaqueMemoryBindInfo *bind)
2229 {
2230 RADV_FROM_HANDLE(radv_image, image, bind->image);
2231
2232 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2233 struct radv_device_memory *mem = NULL;
2234
2235 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2236 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2237
2238 device->ws->buffer_virtual_bind(image->bo,
2239 bind->pBinds[i].resourceOffset,
2240 bind->pBinds[i].size,
2241 mem ? mem->bo : NULL,
2242 bind->pBinds[i].memoryOffset);
2243 }
2244 }
2245
2246 VkResult radv_QueueBindSparse(
2247 VkQueue _queue,
2248 uint32_t bindInfoCount,
2249 const VkBindSparseInfo* pBindInfo,
2250 VkFence _fence)
2251 {
2252 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2253 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2254 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2255 bool fence_emitted = false;
2256
2257 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2258 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2259 radv_sparse_buffer_bind_memory(queue->device,
2260 pBindInfo[i].pBufferBinds + j);
2261 }
2262
2263 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2264 radv_sparse_image_opaque_bind_memory(queue->device,
2265 pBindInfo[i].pImageOpaqueBinds + j);
2266 }
2267
2268 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2269 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2270 &queue->device->empty_cs[queue->queue_family_index],
2271 1, NULL, NULL,
2272 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2273 pBindInfo[i].waitSemaphoreCount,
2274 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2275 pBindInfo[i].signalSemaphoreCount,
2276 false, base_fence);
2277 fence_emitted = true;
2278 if (fence)
2279 fence->submitted = true;
2280 }
2281 }
2282
2283 if (fence && !fence_emitted) {
2284 fence->signalled = true;
2285 }
2286
2287 return VK_SUCCESS;
2288 }
2289
2290 VkResult radv_CreateFence(
2291 VkDevice _device,
2292 const VkFenceCreateInfo* pCreateInfo,
2293 const VkAllocationCallbacks* pAllocator,
2294 VkFence* pFence)
2295 {
2296 RADV_FROM_HANDLE(radv_device, device, _device);
2297 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2298 sizeof(*fence), 8,
2299 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2300
2301 if (!fence)
2302 return VK_ERROR_OUT_OF_HOST_MEMORY;
2303
2304 memset(fence, 0, sizeof(*fence));
2305 fence->submitted = false;
2306 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2307 fence->fence = device->ws->create_fence();
2308 if (!fence->fence) {
2309 vk_free2(&device->alloc, pAllocator, fence);
2310 return VK_ERROR_OUT_OF_HOST_MEMORY;
2311 }
2312
2313 *pFence = radv_fence_to_handle(fence);
2314
2315 return VK_SUCCESS;
2316 }
2317
2318 void radv_DestroyFence(
2319 VkDevice _device,
2320 VkFence _fence,
2321 const VkAllocationCallbacks* pAllocator)
2322 {
2323 RADV_FROM_HANDLE(radv_device, device, _device);
2324 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2325
2326 if (!fence)
2327 return;
2328 device->ws->destroy_fence(fence->fence);
2329 vk_free2(&device->alloc, pAllocator, fence);
2330 }
2331
2332 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2333 {
2334 uint64_t current_time;
2335 struct timespec tv;
2336
2337 clock_gettime(CLOCK_MONOTONIC, &tv);
2338 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2339
2340 timeout = MIN2(UINT64_MAX - current_time, timeout);
2341
2342 return current_time + timeout;
2343 }
2344
2345 VkResult radv_WaitForFences(
2346 VkDevice _device,
2347 uint32_t fenceCount,
2348 const VkFence* pFences,
2349 VkBool32 waitAll,
2350 uint64_t timeout)
2351 {
2352 RADV_FROM_HANDLE(radv_device, device, _device);
2353 timeout = radv_get_absolute_timeout(timeout);
2354
2355 if (!waitAll && fenceCount > 1) {
2356 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2357 }
2358
2359 for (uint32_t i = 0; i < fenceCount; ++i) {
2360 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2361 bool expired = false;
2362
2363 if (fence->signalled)
2364 continue;
2365
2366 if (!fence->submitted)
2367 return VK_TIMEOUT;
2368
2369 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2370 if (!expired)
2371 return VK_TIMEOUT;
2372
2373 fence->signalled = true;
2374 }
2375
2376 return VK_SUCCESS;
2377 }
2378
2379 VkResult radv_ResetFences(VkDevice device,
2380 uint32_t fenceCount,
2381 const VkFence *pFences)
2382 {
2383 for (unsigned i = 0; i < fenceCount; ++i) {
2384 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2385 fence->submitted = fence->signalled = false;
2386 }
2387
2388 return VK_SUCCESS;
2389 }
2390
2391 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2392 {
2393 RADV_FROM_HANDLE(radv_device, device, _device);
2394 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2395
2396 if (fence->signalled)
2397 return VK_SUCCESS;
2398 if (!fence->submitted)
2399 return VK_NOT_READY;
2400
2401 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2402 return VK_NOT_READY;
2403
2404 return VK_SUCCESS;
2405 }
2406
2407
2408 // Queue semaphore functions
2409
2410 VkResult radv_CreateSemaphore(
2411 VkDevice _device,
2412 const VkSemaphoreCreateInfo* pCreateInfo,
2413 const VkAllocationCallbacks* pAllocator,
2414 VkSemaphore* pSemaphore)
2415 {
2416 RADV_FROM_HANDLE(radv_device, device, _device);
2417 struct radeon_winsys_sem *sem;
2418
2419 sem = device->ws->create_sem(device->ws);
2420 if (!sem)
2421 return VK_ERROR_OUT_OF_HOST_MEMORY;
2422
2423 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_DestroySemaphore(
2428 VkDevice _device,
2429 VkSemaphore _semaphore,
2430 const VkAllocationCallbacks* pAllocator)
2431 {
2432 RADV_FROM_HANDLE(radv_device, device, _device);
2433 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2434 if (!_semaphore)
2435 return;
2436
2437 device->ws->destroy_sem(sem);
2438 }
2439
2440 VkResult radv_CreateEvent(
2441 VkDevice _device,
2442 const VkEventCreateInfo* pCreateInfo,
2443 const VkAllocationCallbacks* pAllocator,
2444 VkEvent* pEvent)
2445 {
2446 RADV_FROM_HANDLE(radv_device, device, _device);
2447 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2448 sizeof(*event), 8,
2449 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2450
2451 if (!event)
2452 return VK_ERROR_OUT_OF_HOST_MEMORY;
2453
2454 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2455 RADEON_DOMAIN_GTT,
2456 RADEON_FLAG_CPU_ACCESS);
2457 if (!event->bo) {
2458 vk_free2(&device->alloc, pAllocator, event);
2459 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2460 }
2461
2462 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2463
2464 *pEvent = radv_event_to_handle(event);
2465
2466 return VK_SUCCESS;
2467 }
2468
2469 void radv_DestroyEvent(
2470 VkDevice _device,
2471 VkEvent _event,
2472 const VkAllocationCallbacks* pAllocator)
2473 {
2474 RADV_FROM_HANDLE(radv_device, device, _device);
2475 RADV_FROM_HANDLE(radv_event, event, _event);
2476
2477 if (!event)
2478 return;
2479 device->ws->buffer_destroy(event->bo);
2480 vk_free2(&device->alloc, pAllocator, event);
2481 }
2482
2483 VkResult radv_GetEventStatus(
2484 VkDevice _device,
2485 VkEvent _event)
2486 {
2487 RADV_FROM_HANDLE(radv_event, event, _event);
2488
2489 if (*event->map == 1)
2490 return VK_EVENT_SET;
2491 return VK_EVENT_RESET;
2492 }
2493
2494 VkResult radv_SetEvent(
2495 VkDevice _device,
2496 VkEvent _event)
2497 {
2498 RADV_FROM_HANDLE(radv_event, event, _event);
2499 *event->map = 1;
2500
2501 return VK_SUCCESS;
2502 }
2503
2504 VkResult radv_ResetEvent(
2505 VkDevice _device,
2506 VkEvent _event)
2507 {
2508 RADV_FROM_HANDLE(radv_event, event, _event);
2509 *event->map = 0;
2510
2511 return VK_SUCCESS;
2512 }
2513
2514 VkResult radv_CreateBuffer(
2515 VkDevice _device,
2516 const VkBufferCreateInfo* pCreateInfo,
2517 const VkAllocationCallbacks* pAllocator,
2518 VkBuffer* pBuffer)
2519 {
2520 RADV_FROM_HANDLE(radv_device, device, _device);
2521 struct radv_buffer *buffer;
2522
2523 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2524
2525 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2526 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2527 if (buffer == NULL)
2528 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2529
2530 buffer->size = pCreateInfo->size;
2531 buffer->usage = pCreateInfo->usage;
2532 buffer->bo = NULL;
2533 buffer->offset = 0;
2534 buffer->flags = pCreateInfo->flags;
2535
2536 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2537 buffer->bo = device->ws->buffer_create(device->ws,
2538 align64(buffer->size, 4096),
2539 4096, 0, RADEON_FLAG_VIRTUAL);
2540 if (!buffer->bo) {
2541 vk_free2(&device->alloc, pAllocator, buffer);
2542 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2543 }
2544 }
2545
2546 *pBuffer = radv_buffer_to_handle(buffer);
2547
2548 return VK_SUCCESS;
2549 }
2550
2551 void radv_DestroyBuffer(
2552 VkDevice _device,
2553 VkBuffer _buffer,
2554 const VkAllocationCallbacks* pAllocator)
2555 {
2556 RADV_FROM_HANDLE(radv_device, device, _device);
2557 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2558
2559 if (!buffer)
2560 return;
2561
2562 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2563 device->ws->buffer_destroy(buffer->bo);
2564
2565 vk_free2(&device->alloc, pAllocator, buffer);
2566 }
2567
2568 static inline unsigned
2569 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2570 {
2571 if (stencil)
2572 return image->surface.stencil_tiling_index[level];
2573 else
2574 return image->surface.tiling_index[level];
2575 }
2576
2577 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2578 {
2579 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2580 }
2581
2582 static void
2583 radv_initialise_color_surface(struct radv_device *device,
2584 struct radv_color_buffer_info *cb,
2585 struct radv_image_view *iview)
2586 {
2587 const struct vk_format_description *desc;
2588 unsigned ntype, format, swap, endian;
2589 unsigned blend_clamp = 0, blend_bypass = 0;
2590 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2591 uint64_t va;
2592 const struct radeon_surf *surf = &iview->image->surface;
2593 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2594
2595 desc = vk_format_description(iview->vk_format);
2596
2597 memset(cb, 0, sizeof(*cb));
2598
2599 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2600 va += level_info->offset;
2601 cb->cb_color_base = va >> 8;
2602
2603 /* CMASK variables */
2604 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2605 va += iview->image->cmask.offset;
2606 cb->cb_color_cmask = va >> 8;
2607 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2608
2609 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2610 va += iview->image->dcc_offset;
2611 cb->cb_dcc_base = va >> 8;
2612
2613 uint32_t max_slice = radv_surface_layer_count(iview);
2614 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2615 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2616
2617 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2618 pitch_tile_max = level_info->nblk_x / 8 - 1;
2619 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2620 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2621
2622 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2623 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2624
2625 /* Intensity is implemented as Red, so treat it that way. */
2626 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2627 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2628
2629 if (iview->image->samples > 1) {
2630 unsigned log_samples = util_logbase2(iview->image->samples);
2631
2632 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2633 S_028C74_NUM_FRAGMENTS(log_samples);
2634 }
2635
2636 if (iview->image->fmask.size) {
2637 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2638 if (device->physical_device->rad_info.chip_class >= CIK)
2639 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2640 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2641 cb->cb_color_fmask = va >> 8;
2642 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2643 } else {
2644 /* This must be set for fast clear to work without FMASK. */
2645 if (device->physical_device->rad_info.chip_class >= CIK)
2646 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2647 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2648 cb->cb_color_fmask = cb->cb_color_base;
2649 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2650 }
2651
2652 ntype = radv_translate_color_numformat(iview->vk_format,
2653 desc,
2654 vk_format_get_first_non_void_channel(iview->vk_format));
2655 format = radv_translate_colorformat(iview->vk_format);
2656 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2657 radv_finishme("Illegal color\n");
2658 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2659 endian = radv_colorformat_endian_swap(format);
2660
2661 /* blend clamp should be set for all NORM/SRGB types */
2662 if (ntype == V_028C70_NUMBER_UNORM ||
2663 ntype == V_028C70_NUMBER_SNORM ||
2664 ntype == V_028C70_NUMBER_SRGB)
2665 blend_clamp = 1;
2666
2667 /* set blend bypass according to docs if SINT/UINT or
2668 8/24 COLOR variants */
2669 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2670 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2671 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2672 blend_clamp = 0;
2673 blend_bypass = 1;
2674 }
2675 #if 0
2676 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2677 (format == V_028C70_COLOR_8 ||
2678 format == V_028C70_COLOR_8_8 ||
2679 format == V_028C70_COLOR_8_8_8_8))
2680 ->color_is_int8 = true;
2681 #endif
2682 cb->cb_color_info = S_028C70_FORMAT(format) |
2683 S_028C70_COMP_SWAP(swap) |
2684 S_028C70_BLEND_CLAMP(blend_clamp) |
2685 S_028C70_BLEND_BYPASS(blend_bypass) |
2686 S_028C70_SIMPLE_FLOAT(1) |
2687 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2688 ntype != V_028C70_NUMBER_SNORM &&
2689 ntype != V_028C70_NUMBER_SRGB &&
2690 format != V_028C70_COLOR_8_24 &&
2691 format != V_028C70_COLOR_24_8) |
2692 S_028C70_NUMBER_TYPE(ntype) |
2693 S_028C70_ENDIAN(endian);
2694 if (iview->image->samples > 1)
2695 if (iview->image->fmask.size)
2696 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2697
2698 if (iview->image->cmask.size &&
2699 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2700 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2701
2702 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2703 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2704
2705 if (device->physical_device->rad_info.chip_class >= VI) {
2706 unsigned max_uncompressed_block_size = 2;
2707 if (iview->image->samples > 1) {
2708 if (iview->image->surface.bpe == 1)
2709 max_uncompressed_block_size = 0;
2710 else if (iview->image->surface.bpe == 2)
2711 max_uncompressed_block_size = 1;
2712 }
2713
2714 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2715 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2716 }
2717
2718 /* This must be set for fast clear to work without FMASK. */
2719 if (!iview->image->fmask.size &&
2720 device->physical_device->rad_info.chip_class == SI) {
2721 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2722 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2723 }
2724 }
2725
2726 static void
2727 radv_initialise_ds_surface(struct radv_device *device,
2728 struct radv_ds_buffer_info *ds,
2729 struct radv_image_view *iview)
2730 {
2731 unsigned level = iview->base_mip;
2732 unsigned format;
2733 uint64_t va, s_offs, z_offs;
2734 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2735 bool stencil_only = false;
2736 memset(ds, 0, sizeof(*ds));
2737 switch (iview->vk_format) {
2738 case VK_FORMAT_D24_UNORM_S8_UINT:
2739 case VK_FORMAT_X8_D24_UNORM_PACK32:
2740 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2741 ds->offset_scale = 2.0f;
2742 break;
2743 case VK_FORMAT_D16_UNORM:
2744 case VK_FORMAT_D16_UNORM_S8_UINT:
2745 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2746 ds->offset_scale = 4.0f;
2747 break;
2748 case VK_FORMAT_D32_SFLOAT:
2749 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2750 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2751 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2752 ds->offset_scale = 1.0f;
2753 break;
2754 case VK_FORMAT_S8_UINT:
2755 stencil_only = true;
2756 level_info = &iview->image->surface.stencil_level[level];
2757 break;
2758 default:
2759 break;
2760 }
2761
2762 format = radv_translate_dbformat(iview->vk_format);
2763
2764 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2765 s_offs = z_offs = va;
2766 z_offs += iview->image->surface.level[level].offset;
2767 s_offs += iview->image->surface.stencil_level[level].offset;
2768
2769 uint32_t max_slice = radv_surface_layer_count(iview);
2770 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2771 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2772 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2773 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2774
2775 if (iview->image->samples > 1)
2776 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2777
2778 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2779 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2780 else
2781 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2782
2783 if (device->physical_device->rad_info.chip_class >= CIK) {
2784 struct radeon_info *info = &device->physical_device->rad_info;
2785 unsigned tiling_index = iview->image->surface.tiling_index[level];
2786 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2787 unsigned macro_index = iview->image->surface.macro_tile_index;
2788 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2789 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2790 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2791
2792 if (stencil_only)
2793 tile_mode = stencil_tile_mode;
2794
2795 ds->db_depth_info |=
2796 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2797 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2798 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2799 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2800 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2801 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2802 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2803 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2804 } else {
2805 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2806 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2807 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2808 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2809 }
2810
2811 if (iview->image->surface.htile_size && !level) {
2812 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2813 S_028040_ALLOW_EXPCLEAR(1);
2814
2815 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2816 /* Workaround: For a not yet understood reason, the
2817 * combination of MSAA, fast stencil clear and stencil
2818 * decompress messes with subsequent stencil buffer
2819 * uses. Problem was reproduced on Verde, Bonaire,
2820 * Tonga, and Carrizo.
2821 *
2822 * Disabling EXPCLEAR works around the problem.
2823 *
2824 * Check piglit's arb_texture_multisample-stencil-clear
2825 * test if you want to try changing this.
2826 */
2827 if (iview->image->samples <= 1)
2828 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2829 } else
2830 /* Use all of the htile_buffer for depth if there's no stencil. */
2831 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2832
2833 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2834 iview->image->htile_offset;
2835 ds->db_htile_data_base = va >> 8;
2836 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2837 } else {
2838 ds->db_htile_data_base = 0;
2839 ds->db_htile_surface = 0;
2840 }
2841
2842 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2843 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2844
2845 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2846 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2847 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2848 }
2849
2850 VkResult radv_CreateFramebuffer(
2851 VkDevice _device,
2852 const VkFramebufferCreateInfo* pCreateInfo,
2853 const VkAllocationCallbacks* pAllocator,
2854 VkFramebuffer* pFramebuffer)
2855 {
2856 RADV_FROM_HANDLE(radv_device, device, _device);
2857 struct radv_framebuffer *framebuffer;
2858
2859 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2860
2861 size_t size = sizeof(*framebuffer) +
2862 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2863 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2864 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2865 if (framebuffer == NULL)
2866 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2867
2868 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2869 framebuffer->width = pCreateInfo->width;
2870 framebuffer->height = pCreateInfo->height;
2871 framebuffer->layers = pCreateInfo->layers;
2872 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2873 VkImageView _iview = pCreateInfo->pAttachments[i];
2874 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2875 framebuffer->attachments[i].attachment = iview;
2876 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2877 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2878 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2879 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2880 }
2881 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2882 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2883 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2884 }
2885
2886 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2887 return VK_SUCCESS;
2888 }
2889
2890 void radv_DestroyFramebuffer(
2891 VkDevice _device,
2892 VkFramebuffer _fb,
2893 const VkAllocationCallbacks* pAllocator)
2894 {
2895 RADV_FROM_HANDLE(radv_device, device, _device);
2896 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2897
2898 if (!fb)
2899 return;
2900 vk_free2(&device->alloc, pAllocator, fb);
2901 }
2902
2903 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2904 {
2905 switch (address_mode) {
2906 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2907 return V_008F30_SQ_TEX_WRAP;
2908 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2909 return V_008F30_SQ_TEX_MIRROR;
2910 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2911 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2912 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2913 return V_008F30_SQ_TEX_CLAMP_BORDER;
2914 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2915 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2916 default:
2917 unreachable("illegal tex wrap mode");
2918 break;
2919 }
2920 }
2921
2922 static unsigned
2923 radv_tex_compare(VkCompareOp op)
2924 {
2925 switch (op) {
2926 case VK_COMPARE_OP_NEVER:
2927 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2928 case VK_COMPARE_OP_LESS:
2929 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2930 case VK_COMPARE_OP_EQUAL:
2931 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2932 case VK_COMPARE_OP_LESS_OR_EQUAL:
2933 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2934 case VK_COMPARE_OP_GREATER:
2935 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2936 case VK_COMPARE_OP_NOT_EQUAL:
2937 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2938 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2939 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2940 case VK_COMPARE_OP_ALWAYS:
2941 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2942 default:
2943 unreachable("illegal compare mode");
2944 break;
2945 }
2946 }
2947
2948 static unsigned
2949 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2950 {
2951 switch (filter) {
2952 case VK_FILTER_NEAREST:
2953 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2954 V_008F38_SQ_TEX_XY_FILTER_POINT);
2955 case VK_FILTER_LINEAR:
2956 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2957 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2958 case VK_FILTER_CUBIC_IMG:
2959 default:
2960 fprintf(stderr, "illegal texture filter");
2961 return 0;
2962 }
2963 }
2964
2965 static unsigned
2966 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2967 {
2968 switch (mode) {
2969 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2970 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2971 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2972 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2973 default:
2974 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2975 }
2976 }
2977
2978 static unsigned
2979 radv_tex_bordercolor(VkBorderColor bcolor)
2980 {
2981 switch (bcolor) {
2982 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2983 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2984 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2985 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2986 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2987 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2988 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2989 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2990 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2991 default:
2992 break;
2993 }
2994 return 0;
2995 }
2996
2997 static unsigned
2998 radv_tex_aniso_filter(unsigned filter)
2999 {
3000 if (filter < 2)
3001 return 0;
3002 if (filter < 4)
3003 return 1;
3004 if (filter < 8)
3005 return 2;
3006 if (filter < 16)
3007 return 3;
3008 return 4;
3009 }
3010
3011 static void
3012 radv_init_sampler(struct radv_device *device,
3013 struct radv_sampler *sampler,
3014 const VkSamplerCreateInfo *pCreateInfo)
3015 {
3016 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3017 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3018 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3019 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3020
3021 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3022 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3023 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3024 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3025 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3026 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3027 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3028 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3029 S_008F30_DISABLE_CUBE_WRAP(0) |
3030 S_008F30_COMPAT_MODE(is_vi));
3031 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3032 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3033 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3034 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3035 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3036 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3037 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3038 S_008F38_MIP_POINT_PRECLAMP(0) |
3039 S_008F38_DISABLE_LSB_CEIL(1) |
3040 S_008F38_FILTER_PREC_FIX(1) |
3041 S_008F38_ANISO_OVERRIDE(is_vi));
3042 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3043 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3044 }
3045
3046 VkResult radv_CreateSampler(
3047 VkDevice _device,
3048 const VkSamplerCreateInfo* pCreateInfo,
3049 const VkAllocationCallbacks* pAllocator,
3050 VkSampler* pSampler)
3051 {
3052 RADV_FROM_HANDLE(radv_device, device, _device);
3053 struct radv_sampler *sampler;
3054
3055 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3056
3057 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3058 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3059 if (!sampler)
3060 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3061
3062 radv_init_sampler(device, sampler, pCreateInfo);
3063 *pSampler = radv_sampler_to_handle(sampler);
3064
3065 return VK_SUCCESS;
3066 }
3067
3068 void radv_DestroySampler(
3069 VkDevice _device,
3070 VkSampler _sampler,
3071 const VkAllocationCallbacks* pAllocator)
3072 {
3073 RADV_FROM_HANDLE(radv_device, device, _device);
3074 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3075
3076 if (!sampler)
3077 return;
3078 vk_free2(&device->alloc, pAllocator, sampler);
3079 }
3080
3081
3082 /* vk_icd.h does not declare this function, so we declare it here to
3083 * suppress Wmissing-prototypes.
3084 */
3085 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3086 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3087
3088 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3089 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3090 {
3091 /* For the full details on loader interface versioning, see
3092 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3093 * What follows is a condensed summary, to help you navigate the large and
3094 * confusing official doc.
3095 *
3096 * - Loader interface v0 is incompatible with later versions. We don't
3097 * support it.
3098 *
3099 * - In loader interface v1:
3100 * - The first ICD entrypoint called by the loader is
3101 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3102 * entrypoint.
3103 * - The ICD must statically expose no other Vulkan symbol unless it is
3104 * linked with -Bsymbolic.
3105 * - Each dispatchable Vulkan handle created by the ICD must be
3106 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3107 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3108 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3109 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3110 * such loader-managed surfaces.
3111 *
3112 * - Loader interface v2 differs from v1 in:
3113 * - The first ICD entrypoint called by the loader is
3114 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3115 * statically expose this entrypoint.
3116 *
3117 * - Loader interface v3 differs from v2 in:
3118 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3119 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3120 * because the loader no longer does so.
3121 */
3122 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3123 return VK_SUCCESS;
3124 }