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vulkan/wsi/x11: add support to detect if we can support rendering (v3)
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "util/strtod.h"
37
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable;
48
49 static int
50 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
51 {
52 Dl_info info;
53 struct stat st;
54 if (!dladdr(ptr, &info) || !info.dli_fname) {
55 return -1;
56 }
57 if (stat(info.dli_fname, &st)) {
58 return -1;
59 }
60 *timestamp = st.st_mtim.tv_sec;
61 return 0;
62 }
63
64 static int
65 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
66 {
67 uint32_t mesa_timestamp, llvm_timestamp;
68 uint16_t f = family;
69 memset(uuid, 0, VK_UUID_SIZE);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
72 return -1;
73
74 memcpy(uuid, &mesa_timestamp, 4);
75 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
76 memcpy((char*)uuid + 8, &f, 2);
77 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
78 return 0;
79 }
80
81 static const VkExtensionProperties instance_extensions[] = {
82 {
83 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
84 .specVersion = 25,
85 },
86 #ifdef VK_USE_PLATFORM_XCB_KHR
87 {
88 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
89 .specVersion = 6,
90 },
91 #endif
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
93 {
94 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
95 .specVersion = 6,
96 },
97 #endif
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
99 {
100 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
101 .specVersion = 5,
102 },
103 #endif
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
117 .specVersion = 68,
118 },
119 {
120 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 };
132
133 static VkResult
134 radv_extensions_register(struct radv_instance *instance,
135 struct radv_extensions *extensions,
136 const VkExtensionProperties *new_ext,
137 uint32_t num_ext)
138 {
139 size_t new_size;
140 VkExtensionProperties *new_ptr;
141
142 assert(new_ext && num_ext > 0);
143
144 if (!new_ext)
145 return VK_ERROR_INITIALIZATION_FAILED;
146
147 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
148 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
149 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
150
151 /* Old array continues to be valid, update nothing */
152 if (!new_ptr)
153 return VK_ERROR_OUT_OF_HOST_MEMORY;
154
155 memcpy(&new_ptr[extensions->num_ext], new_ext,
156 num_ext * sizeof(VkExtensionProperties));
157 extensions->ext_array = new_ptr;
158 extensions->num_ext += num_ext;
159
160 return VK_SUCCESS;
161 }
162
163 static void
164 radv_extensions_finish(struct radv_instance *instance,
165 struct radv_extensions *extensions)
166 {
167 assert(extensions);
168
169 if (!extensions)
170 radv_loge("Attemted to free invalid extension struct\n");
171
172 if (extensions->ext_array)
173 vk_free(&instance->alloc, extensions->ext_array);
174 }
175
176 static bool
177 is_extension_enabled(const VkExtensionProperties *extensions,
178 size_t num_ext,
179 const char *name)
180 {
181 assert(extensions && name);
182
183 for (uint32_t i = 0; i < num_ext; i++) {
184 if (strcmp(name, extensions[i].extensionName) == 0)
185 return true;
186 }
187
188 return false;
189 }
190
191 static VkResult
192 radv_physical_device_init(struct radv_physical_device *device,
193 struct radv_instance *instance,
194 const char *path)
195 {
196 VkResult result;
197 drmVersionPtr version;
198 int fd;
199
200 fd = open(path, O_RDWR | O_CLOEXEC);
201 if (fd < 0)
202 return VK_ERROR_INCOMPATIBLE_DRIVER;
203
204 version = drmGetVersion(fd);
205 if (!version) {
206 close(fd);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
208 "failed to get version %s: %m", path);
209 }
210
211 if (strcmp(version->name, "amdgpu")) {
212 drmFreeVersion(version);
213 close(fd);
214 return VK_ERROR_INCOMPATIBLE_DRIVER;
215 }
216 drmFreeVersion(version);
217
218 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
219 device->instance = instance;
220 assert(strlen(path) < ARRAY_SIZE(device->path));
221 strncpy(device->path, path, ARRAY_SIZE(device->path));
222
223 device->ws = radv_amdgpu_winsys_create(fd);
224 if (!device->ws) {
225 result = VK_ERROR_INCOMPATIBLE_DRIVER;
226 goto fail;
227 }
228
229 device->local_fd = fd;
230 device->ws->query_info(device->ws, &device->rad_info);
231 result = radv_init_wsi(device);
232 if (result != VK_SUCCESS) {
233 device->ws->destroy(device->ws);
234 goto fail;
235 }
236
237 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
238 radv_finish_wsi(device);
239 device->ws->destroy(device->ws);
240 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
241 "cannot generate UUID");
242 goto fail;
243 }
244
245 result = radv_extensions_register(instance,
246 &device->extensions,
247 common_device_extensions,
248 ARRAY_SIZE(common_device_extensions));
249 if (result != VK_SUCCESS)
250 goto fail;
251
252 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
253 device->name = device->rad_info.name;
254
255 return VK_SUCCESS;
256
257 fail:
258 close(fd);
259 return result;
260 }
261
262 static void
263 radv_physical_device_finish(struct radv_physical_device *device)
264 {
265 radv_extensions_finish(device->instance, &device->extensions);
266 radv_finish_wsi(device);
267 device->ws->destroy(device->ws);
268 close(device->local_fd);
269 }
270
271
272 static void *
273 default_alloc_func(void *pUserData, size_t size, size_t align,
274 VkSystemAllocationScope allocationScope)
275 {
276 return malloc(size);
277 }
278
279 static void *
280 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
281 size_t align, VkSystemAllocationScope allocationScope)
282 {
283 return realloc(pOriginal, size);
284 }
285
286 static void
287 default_free_func(void *pUserData, void *pMemory)
288 {
289 free(pMemory);
290 }
291
292 static const VkAllocationCallbacks default_alloc = {
293 .pUserData = NULL,
294 .pfnAllocation = default_alloc_func,
295 .pfnReallocation = default_realloc_func,
296 .pfnFree = default_free_func,
297 };
298
299 static const struct debug_control radv_debug_options[] = {
300 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
301 {"nodcc", RADV_DEBUG_NO_DCC},
302 {"shaders", RADV_DEBUG_DUMP_SHADERS},
303 {"nocache", RADV_DEBUG_NO_CACHE},
304 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
305 {"nohiz", RADV_DEBUG_NO_HIZ},
306 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
307 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
308 {NULL, 0}
309 };
310
311 VkResult radv_CreateInstance(
312 const VkInstanceCreateInfo* pCreateInfo,
313 const VkAllocationCallbacks* pAllocator,
314 VkInstance* pInstance)
315 {
316 struct radv_instance *instance;
317
318 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
319
320 uint32_t client_version;
321 if (pCreateInfo->pApplicationInfo &&
322 pCreateInfo->pApplicationInfo->apiVersion != 0) {
323 client_version = pCreateInfo->pApplicationInfo->apiVersion;
324 } else {
325 client_version = VK_MAKE_VERSION(1, 0, 0);
326 }
327
328 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
329 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
330 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
331 "Client requested version %d.%d.%d",
332 VK_VERSION_MAJOR(client_version),
333 VK_VERSION_MINOR(client_version),
334 VK_VERSION_PATCH(client_version));
335 }
336
337 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
338 if (!is_extension_enabled(instance_extensions,
339 ARRAY_SIZE(instance_extensions),
340 pCreateInfo->ppEnabledExtensionNames[i]))
341 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
342 }
343
344 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
345 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
346 if (!instance)
347 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
348
349 memset(instance, 0, sizeof(*instance));
350
351 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
352
353 if (pAllocator)
354 instance->alloc = *pAllocator;
355 else
356 instance->alloc = default_alloc;
357
358 instance->apiVersion = client_version;
359 instance->physicalDeviceCount = -1;
360
361 _mesa_locale_init();
362
363 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
364
365 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
366 radv_debug_options);
367
368 *pInstance = radv_instance_to_handle(instance);
369
370 return VK_SUCCESS;
371 }
372
373 void radv_DestroyInstance(
374 VkInstance _instance,
375 const VkAllocationCallbacks* pAllocator)
376 {
377 RADV_FROM_HANDLE(radv_instance, instance, _instance);
378
379 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
380 radv_physical_device_finish(instance->physicalDevices + i);
381 }
382
383 VG(VALGRIND_DESTROY_MEMPOOL(instance));
384
385 _mesa_locale_fini();
386
387 vk_free(&instance->alloc, instance);
388 }
389
390 VkResult radv_EnumeratePhysicalDevices(
391 VkInstance _instance,
392 uint32_t* pPhysicalDeviceCount,
393 VkPhysicalDevice* pPhysicalDevices)
394 {
395 RADV_FROM_HANDLE(radv_instance, instance, _instance);
396 VkResult result;
397
398 if (instance->physicalDeviceCount < 0) {
399 char path[20];
400 instance->physicalDeviceCount = 0;
401 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
402 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
403 result = radv_physical_device_init(instance->physicalDevices +
404 instance->physicalDeviceCount,
405 instance, path);
406 if (result == VK_SUCCESS)
407 ++instance->physicalDeviceCount;
408 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
409 return result;
410 }
411 }
412
413 if (!pPhysicalDevices) {
414 *pPhysicalDeviceCount = instance->physicalDeviceCount;
415 } else {
416 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
417 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
418 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
419 }
420
421 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
422 : VK_SUCCESS;
423 }
424
425 void radv_GetPhysicalDeviceFeatures(
426 VkPhysicalDevice physicalDevice,
427 VkPhysicalDeviceFeatures* pFeatures)
428 {
429 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
430
431 memset(pFeatures, 0, sizeof(*pFeatures));
432
433 *pFeatures = (VkPhysicalDeviceFeatures) {
434 .robustBufferAccess = true,
435 .fullDrawIndexUint32 = true,
436 .imageCubeArray = true,
437 .independentBlend = true,
438 .geometryShader = true,
439 .tessellationShader = false,
440 .sampleRateShading = false,
441 .dualSrcBlend = true,
442 .logicOp = true,
443 .multiDrawIndirect = true,
444 .drawIndirectFirstInstance = true,
445 .depthClamp = true,
446 .depthBiasClamp = true,
447 .fillModeNonSolid = true,
448 .depthBounds = true,
449 .wideLines = true,
450 .largePoints = true,
451 .alphaToOne = true,
452 .multiViewport = true,
453 .samplerAnisotropy = true,
454 .textureCompressionETC2 = false,
455 .textureCompressionASTC_LDR = false,
456 .textureCompressionBC = true,
457 .occlusionQueryPrecise = true,
458 .pipelineStatisticsQuery = false,
459 .vertexPipelineStoresAndAtomics = true,
460 .fragmentStoresAndAtomics = true,
461 .shaderTessellationAndGeometryPointSize = true,
462 .shaderImageGatherExtended = true,
463 .shaderStorageImageExtendedFormats = true,
464 .shaderStorageImageMultisample = false,
465 .shaderUniformBufferArrayDynamicIndexing = true,
466 .shaderSampledImageArrayDynamicIndexing = true,
467 .shaderStorageBufferArrayDynamicIndexing = true,
468 .shaderStorageImageArrayDynamicIndexing = true,
469 .shaderStorageImageReadWithoutFormat = true,
470 .shaderStorageImageWriteWithoutFormat = true,
471 .shaderClipDistance = true,
472 .shaderCullDistance = true,
473 .shaderFloat64 = true,
474 .shaderInt64 = false,
475 .shaderInt16 = false,
476 .alphaToOne = true,
477 .variableMultisampleRate = false,
478 .inheritedQueries = false,
479 };
480 }
481
482 void radv_GetPhysicalDeviceFeatures2KHR(
483 VkPhysicalDevice physicalDevice,
484 VkPhysicalDeviceFeatures2KHR *pFeatures)
485 {
486 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
487 }
488
489 void radv_GetPhysicalDeviceProperties(
490 VkPhysicalDevice physicalDevice,
491 VkPhysicalDeviceProperties* pProperties)
492 {
493 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
494 VkSampleCountFlags sample_counts = 0xf;
495 VkPhysicalDeviceLimits limits = {
496 .maxImageDimension1D = (1 << 14),
497 .maxImageDimension2D = (1 << 14),
498 .maxImageDimension3D = (1 << 11),
499 .maxImageDimensionCube = (1 << 14),
500 .maxImageArrayLayers = (1 << 11),
501 .maxTexelBufferElements = 128 * 1024 * 1024,
502 .maxUniformBufferRange = UINT32_MAX,
503 .maxStorageBufferRange = UINT32_MAX,
504 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
505 .maxMemoryAllocationCount = UINT32_MAX,
506 .maxSamplerAllocationCount = 64 * 1024,
507 .bufferImageGranularity = 64, /* A cache line */
508 .sparseAddressSpaceSize = 0,
509 .maxBoundDescriptorSets = MAX_SETS,
510 .maxPerStageDescriptorSamplers = 64,
511 .maxPerStageDescriptorUniformBuffers = 64,
512 .maxPerStageDescriptorStorageBuffers = 64,
513 .maxPerStageDescriptorSampledImages = 64,
514 .maxPerStageDescriptorStorageImages = 64,
515 .maxPerStageDescriptorInputAttachments = 64,
516 .maxPerStageResources = 128,
517 .maxDescriptorSetSamplers = 256,
518 .maxDescriptorSetUniformBuffers = 256,
519 .maxDescriptorSetUniformBuffersDynamic = 256,
520 .maxDescriptorSetStorageBuffers = 256,
521 .maxDescriptorSetStorageBuffersDynamic = 256,
522 .maxDescriptorSetSampledImages = 256,
523 .maxDescriptorSetStorageImages = 256,
524 .maxDescriptorSetInputAttachments = 256,
525 .maxVertexInputAttributes = 32,
526 .maxVertexInputBindings = 32,
527 .maxVertexInputAttributeOffset = 2047,
528 .maxVertexInputBindingStride = 2048,
529 .maxVertexOutputComponents = 128,
530 .maxTessellationGenerationLevel = 0,
531 .maxTessellationPatchSize = 0,
532 .maxTessellationControlPerVertexInputComponents = 0,
533 .maxTessellationControlPerVertexOutputComponents = 0,
534 .maxTessellationControlPerPatchOutputComponents = 0,
535 .maxTessellationControlTotalOutputComponents = 0,
536 .maxTessellationEvaluationInputComponents = 0,
537 .maxTessellationEvaluationOutputComponents = 0,
538 .maxGeometryShaderInvocations = 32,
539 .maxGeometryInputComponents = 64,
540 .maxGeometryOutputComponents = 128,
541 .maxGeometryOutputVertices = 256,
542 .maxGeometryTotalOutputComponents = 1024,
543 .maxFragmentInputComponents = 128,
544 .maxFragmentOutputAttachments = 8,
545 .maxFragmentDualSrcAttachments = 1,
546 .maxFragmentCombinedOutputResources = 8,
547 .maxComputeSharedMemorySize = 32768,
548 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
549 .maxComputeWorkGroupInvocations = 2048,
550 .maxComputeWorkGroupSize = {
551 2048,
552 2048,
553 2048
554 },
555 .subPixelPrecisionBits = 4 /* FIXME */,
556 .subTexelPrecisionBits = 4 /* FIXME */,
557 .mipmapPrecisionBits = 4 /* FIXME */,
558 .maxDrawIndexedIndexValue = UINT32_MAX,
559 .maxDrawIndirectCount = UINT32_MAX,
560 .maxSamplerLodBias = 16,
561 .maxSamplerAnisotropy = 16,
562 .maxViewports = MAX_VIEWPORTS,
563 .maxViewportDimensions = { (1 << 14), (1 << 14) },
564 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
565 .viewportSubPixelBits = 13, /* We take a float? */
566 .minMemoryMapAlignment = 4096, /* A page */
567 .minTexelBufferOffsetAlignment = 1,
568 .minUniformBufferOffsetAlignment = 4,
569 .minStorageBufferOffsetAlignment = 4,
570 .minTexelOffset = -32,
571 .maxTexelOffset = 31,
572 .minTexelGatherOffset = -32,
573 .maxTexelGatherOffset = 31,
574 .minInterpolationOffset = -2,
575 .maxInterpolationOffset = 2,
576 .subPixelInterpolationOffsetBits = 8,
577 .maxFramebufferWidth = (1 << 14),
578 .maxFramebufferHeight = (1 << 14),
579 .maxFramebufferLayers = (1 << 10),
580 .framebufferColorSampleCounts = sample_counts,
581 .framebufferDepthSampleCounts = sample_counts,
582 .framebufferStencilSampleCounts = sample_counts,
583 .framebufferNoAttachmentsSampleCounts = sample_counts,
584 .maxColorAttachments = MAX_RTS,
585 .sampledImageColorSampleCounts = sample_counts,
586 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
587 .sampledImageDepthSampleCounts = sample_counts,
588 .sampledImageStencilSampleCounts = sample_counts,
589 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
590 .maxSampleMaskWords = 1,
591 .timestampComputeAndGraphics = false,
592 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
593 .maxClipDistances = 8,
594 .maxCullDistances = 8,
595 .maxCombinedClipAndCullDistances = 8,
596 .discreteQueuePriorities = 1,
597 .pointSizeRange = { 0.125, 255.875 },
598 .lineWidthRange = { 0.0, 7.9921875 },
599 .pointSizeGranularity = (1.0 / 8.0),
600 .lineWidthGranularity = (1.0 / 128.0),
601 .strictLines = false, /* FINISHME */
602 .standardSampleLocations = true,
603 .optimalBufferCopyOffsetAlignment = 128,
604 .optimalBufferCopyRowPitchAlignment = 128,
605 .nonCoherentAtomSize = 64,
606 };
607
608 *pProperties = (VkPhysicalDeviceProperties) {
609 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
610 .driverVersion = 1,
611 .vendorID = 0x1002,
612 .deviceID = pdevice->rad_info.pci_id,
613 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
614 .limits = limits,
615 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
616 };
617
618 strcpy(pProperties->deviceName, pdevice->name);
619 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
620 }
621
622 void radv_GetPhysicalDeviceProperties2KHR(
623 VkPhysicalDevice physicalDevice,
624 VkPhysicalDeviceProperties2KHR *pProperties)
625 {
626 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
627 }
628
629 static void radv_get_physical_device_queue_family_properties(
630 struct radv_physical_device* pdevice,
631 uint32_t* pCount,
632 VkQueueFamilyProperties** pQueueFamilyProperties)
633 {
634 int num_queue_families = 1;
635 int idx;
636 if (pdevice->rad_info.compute_rings > 0 &&
637 pdevice->rad_info.chip_class >= CIK &&
638 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
639 num_queue_families++;
640
641 if (pQueueFamilyProperties == NULL) {
642 *pCount = num_queue_families;
643 return;
644 }
645
646 if (!*pCount)
647 return;
648
649 idx = 0;
650 if (*pCount >= 1) {
651 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
652 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
653 VK_QUEUE_COMPUTE_BIT |
654 VK_QUEUE_TRANSFER_BIT,
655 .queueCount = 1,
656 .timestampValidBits = 64,
657 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
658 };
659 idx++;
660 }
661
662 if (pdevice->rad_info.compute_rings > 0 &&
663 pdevice->rad_info.chip_class >= CIK &&
664 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
665 if (*pCount > idx) {
666 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
667 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
668 .queueCount = pdevice->rad_info.compute_rings,
669 .timestampValidBits = 64,
670 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
671 };
672 idx++;
673 }
674 }
675 *pCount = idx;
676 }
677
678 void radv_GetPhysicalDeviceQueueFamilyProperties(
679 VkPhysicalDevice physicalDevice,
680 uint32_t* pCount,
681 VkQueueFamilyProperties* pQueueFamilyProperties)
682 {
683 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
684 if (!pQueueFamilyProperties) {
685 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
686 return;
687 }
688 VkQueueFamilyProperties *properties[] = {
689 pQueueFamilyProperties + 0,
690 pQueueFamilyProperties + 1,
691 pQueueFamilyProperties + 2,
692 };
693 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
694 assert(*pCount <= 3);
695 }
696
697 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
698 VkPhysicalDevice physicalDevice,
699 uint32_t* pCount,
700 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
701 {
702 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
703 if (!pQueueFamilyProperties) {
704 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
705 return;
706 }
707 VkQueueFamilyProperties *properties[] = {
708 &pQueueFamilyProperties[0].queueFamilyProperties,
709 &pQueueFamilyProperties[1].queueFamilyProperties,
710 &pQueueFamilyProperties[2].queueFamilyProperties,
711 };
712 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
713 assert(*pCount <= 3);
714 }
715
716 void radv_GetPhysicalDeviceMemoryProperties(
717 VkPhysicalDevice physicalDevice,
718 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
719 {
720 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
721
722 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
723
724 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
725 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
726 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
727 .heapIndex = RADV_MEM_HEAP_VRAM,
728 };
729 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
730 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
731 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
732 .heapIndex = RADV_MEM_HEAP_GTT,
733 };
734 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
735 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
736 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
737 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
738 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
739 };
740 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
741 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
742 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
743 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
744 .heapIndex = RADV_MEM_HEAP_GTT,
745 };
746
747 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
748
749 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
750 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
751 .size = physical_device->rad_info.vram_size -
752 physical_device->rad_info.visible_vram_size,
753 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
754 };
755 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
756 .size = physical_device->rad_info.visible_vram_size,
757 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
758 };
759 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
760 .size = physical_device->rad_info.gart_size,
761 .flags = 0,
762 };
763 }
764
765 void radv_GetPhysicalDeviceMemoryProperties2KHR(
766 VkPhysicalDevice physicalDevice,
767 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
768 {
769 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
770 &pMemoryProperties->memoryProperties);
771 }
772
773 static int
774 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
775 int queue_family_index, int idx)
776 {
777 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
778 queue->device = device;
779 queue->queue_family_index = queue_family_index;
780 queue->queue_idx = idx;
781
782 queue->hw_ctx = device->ws->ctx_create(device->ws);
783 if (!queue->hw_ctx)
784 return VK_ERROR_OUT_OF_HOST_MEMORY;
785
786 return VK_SUCCESS;
787 }
788
789 static void
790 radv_queue_finish(struct radv_queue *queue)
791 {
792 if (queue->hw_ctx)
793 queue->device->ws->ctx_destroy(queue->hw_ctx);
794
795 if (queue->preamble_cs)
796 queue->device->ws->cs_destroy(queue->preamble_cs);
797 if (queue->descriptor_bo)
798 queue->device->ws->buffer_destroy(queue->descriptor_bo);
799 if (queue->scratch_bo)
800 queue->device->ws->buffer_destroy(queue->scratch_bo);
801 if (queue->esgs_ring_bo)
802 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
803 if (queue->gsvs_ring_bo)
804 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
805 if (queue->compute_scratch_bo)
806 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
807 }
808
809 static void
810 radv_device_init_gs_info(struct radv_device *device)
811 {
812 switch (device->physical_device->rad_info.family) {
813 case CHIP_OLAND:
814 case CHIP_HAINAN:
815 case CHIP_KAVERI:
816 case CHIP_KABINI:
817 case CHIP_MULLINS:
818 case CHIP_ICELAND:
819 case CHIP_CARRIZO:
820 case CHIP_STONEY:
821 device->gs_table_depth = 16;
822 return;
823 case CHIP_TAHITI:
824 case CHIP_PITCAIRN:
825 case CHIP_VERDE:
826 case CHIP_BONAIRE:
827 case CHIP_HAWAII:
828 case CHIP_TONGA:
829 case CHIP_FIJI:
830 case CHIP_POLARIS10:
831 case CHIP_POLARIS11:
832 device->gs_table_depth = 32;
833 return;
834 default:
835 unreachable("unknown GPU");
836 }
837 }
838
839 VkResult radv_CreateDevice(
840 VkPhysicalDevice physicalDevice,
841 const VkDeviceCreateInfo* pCreateInfo,
842 const VkAllocationCallbacks* pAllocator,
843 VkDevice* pDevice)
844 {
845 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
846 VkResult result;
847 struct radv_device *device;
848
849 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
850 if (!is_extension_enabled(physical_device->extensions.ext_array,
851 physical_device->extensions.num_ext,
852 pCreateInfo->ppEnabledExtensionNames[i]))
853 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
854 }
855
856 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
857 sizeof(*device), 8,
858 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
859 if (!device)
860 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
861
862 memset(device, 0, sizeof(*device));
863
864 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
865 device->instance = physical_device->instance;
866 device->physical_device = physical_device;
867
868 device->debug_flags = device->instance->debug_flags;
869
870 device->ws = physical_device->ws;
871 if (pAllocator)
872 device->alloc = *pAllocator;
873 else
874 device->alloc = physical_device->instance->alloc;
875
876 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
877 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
878 uint32_t qfi = queue_create->queueFamilyIndex;
879
880 device->queues[qfi] = vk_alloc(&device->alloc,
881 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
882 if (!device->queues[qfi]) {
883 result = VK_ERROR_OUT_OF_HOST_MEMORY;
884 goto fail;
885 }
886
887 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
888
889 device->queue_count[qfi] = queue_create->queueCount;
890
891 for (unsigned q = 0; q < queue_create->queueCount; q++) {
892 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
893 if (result != VK_SUCCESS)
894 goto fail;
895 }
896 }
897
898 #if HAVE_LLVM < 0x0400
899 device->llvm_supports_spill = false;
900 #else
901 device->llvm_supports_spill = true;
902 #endif
903
904 /* The maximum number of scratch waves. Scratch space isn't divided
905 * evenly between CUs. The number is only a function of the number of CUs.
906 * We can decrease the constant to decrease the scratch buffer size.
907 *
908 * sctx->scratch_waves must be >= the maximum posible size of
909 * 1 threadgroup, so that the hw doesn't hang from being unable
910 * to start any.
911 *
912 * The recommended value is 4 per CU at most. Higher numbers don't
913 * bring much benefit, but they still occupy chip resources (think
914 * async compute). I've seen ~2% performance difference between 4 and 32.
915 */
916 uint32_t max_threads_per_block = 2048;
917 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
918 max_threads_per_block / 64);
919
920 radv_device_init_gs_info(device);
921
922 result = radv_device_init_meta(device);
923 if (result != VK_SUCCESS)
924 goto fail;
925
926 radv_device_init_msaa(device);
927
928 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
929 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
930 switch (family) {
931 case RADV_QUEUE_GENERAL:
932 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
933 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
934 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
935 break;
936 case RADV_QUEUE_COMPUTE:
937 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
938 radeon_emit(device->empty_cs[family], 0);
939 break;
940 }
941 device->ws->cs_finalize(device->empty_cs[family]);
942 }
943
944 if (getenv("RADV_TRACE_FILE")) {
945 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
946 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
947 if (!device->trace_bo)
948 goto fail;
949
950 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
951 if (!device->trace_id_ptr)
952 goto fail;
953 }
954
955 if (device->physical_device->rad_info.chip_class >= CIK)
956 cik_create_gfx_config(device);
957
958 *pDevice = radv_device_to_handle(device);
959 return VK_SUCCESS;
960
961 fail:
962 if (device->trace_bo)
963 device->ws->buffer_destroy(device->trace_bo);
964
965 if (device->gfx_init)
966 device->ws->buffer_destroy(device->gfx_init);
967
968 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
969 for (unsigned q = 0; q < device->queue_count[i]; q++)
970 radv_queue_finish(&device->queues[i][q]);
971 if (device->queue_count[i])
972 vk_free(&device->alloc, device->queues[i]);
973 }
974
975 vk_free(&device->alloc, device);
976 return result;
977 }
978
979 void radv_DestroyDevice(
980 VkDevice _device,
981 const VkAllocationCallbacks* pAllocator)
982 {
983 RADV_FROM_HANDLE(radv_device, device, _device);
984
985 if (device->trace_bo)
986 device->ws->buffer_destroy(device->trace_bo);
987
988 if (device->gfx_init)
989 device->ws->buffer_destroy(device->gfx_init);
990
991 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
992 for (unsigned q = 0; q < device->queue_count[i]; q++)
993 radv_queue_finish(&device->queues[i][q]);
994 if (device->queue_count[i])
995 vk_free(&device->alloc, device->queues[i]);
996 }
997 radv_device_finish_meta(device);
998
999 vk_free(&device->alloc, device);
1000 }
1001
1002 VkResult radv_EnumerateInstanceExtensionProperties(
1003 const char* pLayerName,
1004 uint32_t* pPropertyCount,
1005 VkExtensionProperties* pProperties)
1006 {
1007 if (pProperties == NULL) {
1008 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1009 return VK_SUCCESS;
1010 }
1011
1012 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1013 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1014
1015 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1016 return VK_INCOMPLETE;
1017
1018 return VK_SUCCESS;
1019 }
1020
1021 VkResult radv_EnumerateDeviceExtensionProperties(
1022 VkPhysicalDevice physicalDevice,
1023 const char* pLayerName,
1024 uint32_t* pPropertyCount,
1025 VkExtensionProperties* pProperties)
1026 {
1027 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1028
1029 if (pProperties == NULL) {
1030 *pPropertyCount = pdevice->extensions.num_ext;
1031 return VK_SUCCESS;
1032 }
1033
1034 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1035 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1036
1037 if (*pPropertyCount < pdevice->extensions.num_ext)
1038 return VK_INCOMPLETE;
1039
1040 return VK_SUCCESS;
1041 }
1042
1043 VkResult radv_EnumerateInstanceLayerProperties(
1044 uint32_t* pPropertyCount,
1045 VkLayerProperties* pProperties)
1046 {
1047 if (pProperties == NULL) {
1048 *pPropertyCount = 0;
1049 return VK_SUCCESS;
1050 }
1051
1052 /* None supported at this time */
1053 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1054 }
1055
1056 VkResult radv_EnumerateDeviceLayerProperties(
1057 VkPhysicalDevice physicalDevice,
1058 uint32_t* pPropertyCount,
1059 VkLayerProperties* pProperties)
1060 {
1061 if (pProperties == NULL) {
1062 *pPropertyCount = 0;
1063 return VK_SUCCESS;
1064 }
1065
1066 /* None supported at this time */
1067 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1068 }
1069
1070 void radv_GetDeviceQueue(
1071 VkDevice _device,
1072 uint32_t queueFamilyIndex,
1073 uint32_t queueIndex,
1074 VkQueue* pQueue)
1075 {
1076 RADV_FROM_HANDLE(radv_device, device, _device);
1077
1078 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1079 }
1080
1081 static void radv_dump_trace(struct radv_device *device,
1082 struct radeon_winsys_cs *cs)
1083 {
1084 const char *filename = getenv("RADV_TRACE_FILE");
1085 FILE *f = fopen(filename, "w");
1086 if (!f) {
1087 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1088 return;
1089 }
1090
1091 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1092 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1093 fclose(f);
1094 }
1095
1096 static void
1097 fill_geom_rings(struct radv_queue *queue,
1098 uint32_t *map,
1099 uint32_t esgs_ring_size,
1100 struct radeon_winsys_bo *esgs_ring_bo,
1101 uint32_t gsvs_ring_size,
1102 struct radeon_winsys_bo *gsvs_ring_bo)
1103 {
1104 uint64_t esgs_va = 0, gsvs_va = 0;
1105 uint32_t *desc = &map[4];
1106
1107 if (esgs_ring_bo)
1108 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1109 if (gsvs_ring_bo)
1110 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1111
1112 /* stride 0, num records - size, add tid, swizzle, elsize4,
1113 index stride 64 */
1114 desc[0] = esgs_va;
1115 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1116 S_008F04_STRIDE(0) |
1117 S_008F04_SWIZZLE_ENABLE(true);
1118 desc[2] = esgs_ring_size;
1119 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1120 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1121 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1122 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1123 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1124 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1125 S_008F0C_ELEMENT_SIZE(1) |
1126 S_008F0C_INDEX_STRIDE(3) |
1127 S_008F0C_ADD_TID_ENABLE(true);
1128
1129 desc += 4;
1130 /* GS entry for ES->GS ring */
1131 /* stride 0, num records - size, elsize0,
1132 index stride 0 */
1133 desc[0] = esgs_va;
1134 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1135 S_008F04_STRIDE(0) |
1136 S_008F04_SWIZZLE_ENABLE(false);
1137 desc[2] = esgs_ring_size;
1138 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1139 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1140 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1141 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1142 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1143 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1144 S_008F0C_ELEMENT_SIZE(0) |
1145 S_008F0C_INDEX_STRIDE(0) |
1146 S_008F0C_ADD_TID_ENABLE(false);
1147
1148 desc += 4;
1149 /* VS entry for GS->VS ring */
1150 /* stride 0, num records - size, elsize0,
1151 index stride 0 */
1152 desc[0] = gsvs_va;
1153 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1154 S_008F04_STRIDE(0) |
1155 S_008F04_SWIZZLE_ENABLE(false);
1156 desc[2] = gsvs_ring_size;
1157 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1158 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1159 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1160 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1161 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1162 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1163 S_008F0C_ELEMENT_SIZE(0) |
1164 S_008F0C_INDEX_STRIDE(0) |
1165 S_008F0C_ADD_TID_ENABLE(false);
1166 desc += 4;
1167
1168 /* stride gsvs_itemsize, num records 64
1169 elsize 4, index stride 16 */
1170 /* shader will patch stride and desc[2] */
1171 desc[0] = gsvs_va;
1172 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1173 S_008F04_STRIDE(0) |
1174 S_008F04_SWIZZLE_ENABLE(true);
1175 desc[2] = 0;
1176 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1177 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1178 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1179 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1180 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1181 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1182 S_008F0C_ELEMENT_SIZE(1) |
1183 S_008F0C_INDEX_STRIDE(1) |
1184 S_008F0C_ADD_TID_ENABLE(true);
1185 }
1186
1187 static VkResult
1188 radv_get_preamble_cs(struct radv_queue *queue,
1189 uint32_t scratch_size,
1190 uint32_t compute_scratch_size,
1191 uint32_t esgs_ring_size,
1192 uint32_t gsvs_ring_size,
1193 struct radeon_winsys_cs **preamble_cs)
1194 {
1195 struct radeon_winsys_bo *scratch_bo = NULL;
1196 struct radeon_winsys_bo *descriptor_bo = NULL;
1197 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1198 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1199 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1200 struct radeon_winsys_cs *cs = NULL;
1201
1202 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size) {
1203 *preamble_cs = NULL;
1204 return VK_SUCCESS;
1205 }
1206
1207 if (scratch_size <= queue->scratch_size &&
1208 compute_scratch_size <= queue->compute_scratch_size &&
1209 esgs_ring_size <= queue->esgs_ring_size &&
1210 gsvs_ring_size <= queue->gsvs_ring_size) {
1211 *preamble_cs = queue->preamble_cs;
1212 return VK_SUCCESS;
1213 }
1214
1215 if (scratch_size > queue->scratch_size) {
1216 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1217 scratch_size,
1218 4096,
1219 RADEON_DOMAIN_VRAM,
1220 RADEON_FLAG_NO_CPU_ACCESS);
1221 if (!scratch_bo)
1222 goto fail;
1223 } else
1224 scratch_bo = queue->scratch_bo;
1225
1226 if (compute_scratch_size > queue->compute_scratch_size) {
1227 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1228 compute_scratch_size,
1229 4096,
1230 RADEON_DOMAIN_VRAM,
1231 RADEON_FLAG_NO_CPU_ACCESS);
1232 if (!compute_scratch_bo)
1233 goto fail;
1234
1235 } else
1236 compute_scratch_bo = queue->compute_scratch_bo;
1237
1238 if (esgs_ring_size > queue->esgs_ring_size) {
1239 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1240 esgs_ring_size,
1241 4096,
1242 RADEON_DOMAIN_VRAM,
1243 RADEON_FLAG_NO_CPU_ACCESS);
1244 if (!esgs_ring_bo)
1245 goto fail;
1246 } else {
1247 esgs_ring_bo = queue->esgs_ring_bo;
1248 esgs_ring_size = queue->esgs_ring_size;
1249 }
1250
1251 if (gsvs_ring_size > queue->gsvs_ring_size) {
1252 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1253 gsvs_ring_size,
1254 4096,
1255 RADEON_DOMAIN_VRAM,
1256 RADEON_FLAG_NO_CPU_ACCESS);
1257 if (!gsvs_ring_bo)
1258 goto fail;
1259 } else {
1260 gsvs_ring_bo = queue->gsvs_ring_bo;
1261 gsvs_ring_size = queue->gsvs_ring_size;
1262 }
1263
1264 if (scratch_bo != queue->scratch_bo ||
1265 esgs_ring_bo != queue->esgs_ring_bo ||
1266 gsvs_ring_bo != queue->gsvs_ring_bo) {
1267 uint32_t size = 0;
1268 if (gsvs_ring_bo || esgs_ring_bo)
1269 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1270 else if (scratch_bo)
1271 size = 8; /* 2 dword */
1272
1273 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1274 size,
1275 4096,
1276 RADEON_DOMAIN_VRAM,
1277 RADEON_FLAG_CPU_ACCESS);
1278 if (!descriptor_bo)
1279 goto fail;
1280 } else
1281 descriptor_bo = queue->descriptor_bo;
1282
1283 cs = queue->device->ws->cs_create(queue->device->ws,
1284 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1285 if (!cs)
1286 goto fail;
1287
1288
1289 if (scratch_bo)
1290 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1291
1292 if (esgs_ring_bo)
1293 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1294
1295 if (gsvs_ring_bo)
1296 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1297
1298 if (descriptor_bo)
1299 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1300
1301 if (descriptor_bo != queue->descriptor_bo) {
1302 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1303
1304 if (scratch_bo) {
1305 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1306 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1307 S_008F04_SWIZZLE_ENABLE(1);
1308 map[0] = scratch_va;
1309 map[1] = rsrc1;
1310 }
1311
1312 if (esgs_ring_bo || gsvs_ring_bo)
1313 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1314
1315 queue->device->ws->buffer_unmap(descriptor_bo);
1316 }
1317
1318 if (esgs_ring_bo || gsvs_ring_bo) {
1319 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1320 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1321 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1322 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1323
1324 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1325 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1326 radeon_emit(cs, esgs_ring_size >> 8);
1327 radeon_emit(cs, gsvs_ring_size >> 8);
1328 } else {
1329 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1330 radeon_emit(cs, esgs_ring_size >> 8);
1331 radeon_emit(cs, gsvs_ring_size >> 8);
1332 }
1333 }
1334
1335 if (descriptor_bo) {
1336 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1337 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1338 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1339 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1340 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1341 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1342
1343 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1344
1345 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1346 radeon_set_sh_reg_seq(cs, regs[i], 2);
1347 radeon_emit(cs, va);
1348 radeon_emit(cs, va >> 32);
1349 }
1350 }
1351
1352 if (compute_scratch_bo) {
1353 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1354 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1355 S_008F04_SWIZZLE_ENABLE(1);
1356
1357 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1358
1359 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1360 radeon_emit(cs, scratch_va);
1361 radeon_emit(cs, rsrc1);
1362 }
1363
1364 if (!queue->device->ws->cs_finalize(cs))
1365 goto fail;
1366
1367 if (queue->preamble_cs)
1368 queue->device->ws->cs_destroy(queue->preamble_cs);
1369
1370 queue->preamble_cs = cs;
1371
1372 if (scratch_bo != queue->scratch_bo) {
1373 if (queue->scratch_bo)
1374 queue->device->ws->buffer_destroy(queue->scratch_bo);
1375 queue->scratch_bo = scratch_bo;
1376 queue->scratch_size = scratch_size;
1377 }
1378
1379 if (compute_scratch_bo != queue->compute_scratch_bo) {
1380 if (queue->compute_scratch_bo)
1381 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1382 queue->compute_scratch_bo = compute_scratch_bo;
1383 queue->compute_scratch_size = compute_scratch_size;
1384 }
1385
1386 if (esgs_ring_bo != queue->esgs_ring_bo) {
1387 if (queue->esgs_ring_bo)
1388 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1389 queue->esgs_ring_bo = esgs_ring_bo;
1390 queue->esgs_ring_size = esgs_ring_size;
1391 }
1392
1393 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1394 if (queue->gsvs_ring_bo)
1395 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1396 queue->gsvs_ring_bo = gsvs_ring_bo;
1397 queue->gsvs_ring_size = gsvs_ring_size;
1398 }
1399
1400 if (descriptor_bo != queue->descriptor_bo) {
1401 if (queue->descriptor_bo)
1402 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1403
1404 queue->descriptor_bo = descriptor_bo;
1405 }
1406
1407 *preamble_cs = cs;
1408 return VK_SUCCESS;
1409 fail:
1410 if (cs)
1411 queue->device->ws->cs_destroy(cs);
1412 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1413 queue->device->ws->buffer_destroy(descriptor_bo);
1414 if (scratch_bo && scratch_bo != queue->scratch_bo)
1415 queue->device->ws->buffer_destroy(scratch_bo);
1416 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1417 queue->device->ws->buffer_destroy(compute_scratch_bo);
1418 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1419 queue->device->ws->buffer_destroy(esgs_ring_bo);
1420 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1421 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1422 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1423 }
1424
1425 VkResult radv_QueueSubmit(
1426 VkQueue _queue,
1427 uint32_t submitCount,
1428 const VkSubmitInfo* pSubmits,
1429 VkFence _fence)
1430 {
1431 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1432 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1433 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1434 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1435 int ret;
1436 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1437 uint32_t scratch_size = 0;
1438 uint32_t compute_scratch_size = 0;
1439 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1440 struct radeon_winsys_cs *preamble_cs = NULL;
1441 VkResult result;
1442 bool fence_emitted = false;
1443
1444 /* Do this first so failing to allocate scratch buffers can't result in
1445 * partially executed submissions. */
1446 for (uint32_t i = 0; i < submitCount; i++) {
1447 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1448 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1449 pSubmits[i].pCommandBuffers[j]);
1450
1451 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1452 compute_scratch_size = MAX2(compute_scratch_size,
1453 cmd_buffer->compute_scratch_size_needed);
1454 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1455 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1456 }
1457 }
1458
1459 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size, esgs_ring_size, gsvs_ring_size, &preamble_cs);
1460 if (result != VK_SUCCESS)
1461 return result;
1462
1463 for (uint32_t i = 0; i < submitCount; i++) {
1464 struct radeon_winsys_cs **cs_array;
1465 bool can_patch = true;
1466 uint32_t advance;
1467
1468 if (!pSubmits[i].commandBufferCount) {
1469 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1470 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1471 &queue->device->empty_cs[queue->queue_family_index],
1472 1, NULL,
1473 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1474 pSubmits[i].waitSemaphoreCount,
1475 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1476 pSubmits[i].signalSemaphoreCount,
1477 false, base_fence);
1478 if (ret) {
1479 radv_loge("failed to submit CS %d\n", i);
1480 abort();
1481 }
1482 fence_emitted = true;
1483 }
1484 continue;
1485 }
1486
1487 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1488 pSubmits[i].commandBufferCount);
1489
1490 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1491 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1492 pSubmits[i].pCommandBuffers[j]);
1493 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1494
1495 cs_array[j] = cmd_buffer->cs;
1496 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1497 can_patch = false;
1498 }
1499
1500 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1501 advance = MIN2(max_cs_submission,
1502 pSubmits[i].commandBufferCount - j);
1503 bool b = j == 0;
1504 bool e = j + advance == pSubmits[i].commandBufferCount;
1505
1506 if (queue->device->trace_bo)
1507 *queue->device->trace_id_ptr = 0;
1508
1509 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1510 advance, preamble_cs,
1511 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1512 b ? pSubmits[i].waitSemaphoreCount : 0,
1513 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1514 e ? pSubmits[i].signalSemaphoreCount : 0,
1515 can_patch, base_fence);
1516
1517 if (ret) {
1518 radv_loge("failed to submit CS %d\n", i);
1519 abort();
1520 }
1521 fence_emitted = true;
1522 if (queue->device->trace_bo) {
1523 bool success = queue->device->ws->ctx_wait_idle(
1524 queue->hw_ctx,
1525 radv_queue_family_to_ring(
1526 queue->queue_family_index),
1527 queue->queue_idx);
1528
1529 if (!success) { /* Hang */
1530 radv_dump_trace(queue->device, cs_array[j]);
1531 abort();
1532 }
1533 }
1534 }
1535 free(cs_array);
1536 }
1537
1538 if (fence) {
1539 if (!fence_emitted)
1540 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1541 &queue->device->empty_cs[queue->queue_family_index],
1542 1, NULL, NULL, 0, NULL, 0,
1543 false, base_fence);
1544
1545 fence->submitted = true;
1546 }
1547
1548 return VK_SUCCESS;
1549 }
1550
1551 VkResult radv_QueueWaitIdle(
1552 VkQueue _queue)
1553 {
1554 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1555
1556 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1557 radv_queue_family_to_ring(queue->queue_family_index),
1558 queue->queue_idx);
1559 return VK_SUCCESS;
1560 }
1561
1562 VkResult radv_DeviceWaitIdle(
1563 VkDevice _device)
1564 {
1565 RADV_FROM_HANDLE(radv_device, device, _device);
1566
1567 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1568 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1569 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1570 }
1571 }
1572 return VK_SUCCESS;
1573 }
1574
1575 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1576 VkInstance instance,
1577 const char* pName)
1578 {
1579 return radv_lookup_entrypoint(pName);
1580 }
1581
1582 /* The loader wants us to expose a second GetInstanceProcAddr function
1583 * to work around certain LD_PRELOAD issues seen in apps.
1584 */
1585 PUBLIC
1586 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1587 VkInstance instance,
1588 const char* pName);
1589
1590 PUBLIC
1591 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1592 VkInstance instance,
1593 const char* pName)
1594 {
1595 return radv_GetInstanceProcAddr(instance, pName);
1596 }
1597
1598 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1599 VkDevice device,
1600 const char* pName)
1601 {
1602 return radv_lookup_entrypoint(pName);
1603 }
1604
1605 VkResult radv_AllocateMemory(
1606 VkDevice _device,
1607 const VkMemoryAllocateInfo* pAllocateInfo,
1608 const VkAllocationCallbacks* pAllocator,
1609 VkDeviceMemory* pMem)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612 struct radv_device_memory *mem;
1613 VkResult result;
1614 enum radeon_bo_domain domain;
1615 uint32_t flags = 0;
1616 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1617
1618 if (pAllocateInfo->allocationSize == 0) {
1619 /* Apparently, this is allowed */
1620 *pMem = VK_NULL_HANDLE;
1621 return VK_SUCCESS;
1622 }
1623
1624 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1625 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1626 if (mem == NULL)
1627 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1628
1629 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1630 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1631 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1632 domain = RADEON_DOMAIN_GTT;
1633 else
1634 domain = RADEON_DOMAIN_VRAM;
1635
1636 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1637 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1638 else
1639 flags |= RADEON_FLAG_CPU_ACCESS;
1640
1641 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1642 flags |= RADEON_FLAG_GTT_WC;
1643
1644 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
1645 domain, flags);
1646
1647 if (!mem->bo) {
1648 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1649 goto fail;
1650 }
1651 mem->type_index = pAllocateInfo->memoryTypeIndex;
1652
1653 *pMem = radv_device_memory_to_handle(mem);
1654
1655 return VK_SUCCESS;
1656
1657 fail:
1658 vk_free2(&device->alloc, pAllocator, mem);
1659
1660 return result;
1661 }
1662
1663 void radv_FreeMemory(
1664 VkDevice _device,
1665 VkDeviceMemory _mem,
1666 const VkAllocationCallbacks* pAllocator)
1667 {
1668 RADV_FROM_HANDLE(radv_device, device, _device);
1669 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1670
1671 if (mem == NULL)
1672 return;
1673
1674 device->ws->buffer_destroy(mem->bo);
1675 mem->bo = NULL;
1676
1677 vk_free2(&device->alloc, pAllocator, mem);
1678 }
1679
1680 VkResult radv_MapMemory(
1681 VkDevice _device,
1682 VkDeviceMemory _memory,
1683 VkDeviceSize offset,
1684 VkDeviceSize size,
1685 VkMemoryMapFlags flags,
1686 void** ppData)
1687 {
1688 RADV_FROM_HANDLE(radv_device, device, _device);
1689 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1690
1691 if (mem == NULL) {
1692 *ppData = NULL;
1693 return VK_SUCCESS;
1694 }
1695
1696 *ppData = device->ws->buffer_map(mem->bo);
1697 if (*ppData) {
1698 *ppData += offset;
1699 return VK_SUCCESS;
1700 }
1701
1702 return VK_ERROR_MEMORY_MAP_FAILED;
1703 }
1704
1705 void radv_UnmapMemory(
1706 VkDevice _device,
1707 VkDeviceMemory _memory)
1708 {
1709 RADV_FROM_HANDLE(radv_device, device, _device);
1710 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1711
1712 if (mem == NULL)
1713 return;
1714
1715 device->ws->buffer_unmap(mem->bo);
1716 }
1717
1718 VkResult radv_FlushMappedMemoryRanges(
1719 VkDevice _device,
1720 uint32_t memoryRangeCount,
1721 const VkMappedMemoryRange* pMemoryRanges)
1722 {
1723 return VK_SUCCESS;
1724 }
1725
1726 VkResult radv_InvalidateMappedMemoryRanges(
1727 VkDevice _device,
1728 uint32_t memoryRangeCount,
1729 const VkMappedMemoryRange* pMemoryRanges)
1730 {
1731 return VK_SUCCESS;
1732 }
1733
1734 void radv_GetBufferMemoryRequirements(
1735 VkDevice device,
1736 VkBuffer _buffer,
1737 VkMemoryRequirements* pMemoryRequirements)
1738 {
1739 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1740
1741 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1742
1743 pMemoryRequirements->size = buffer->size;
1744 pMemoryRequirements->alignment = 16;
1745 }
1746
1747 void radv_GetImageMemoryRequirements(
1748 VkDevice device,
1749 VkImage _image,
1750 VkMemoryRequirements* pMemoryRequirements)
1751 {
1752 RADV_FROM_HANDLE(radv_image, image, _image);
1753
1754 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1755
1756 pMemoryRequirements->size = image->size;
1757 pMemoryRequirements->alignment = image->alignment;
1758 }
1759
1760 void radv_GetImageSparseMemoryRequirements(
1761 VkDevice device,
1762 VkImage image,
1763 uint32_t* pSparseMemoryRequirementCount,
1764 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1765 {
1766 stub();
1767 }
1768
1769 void radv_GetDeviceMemoryCommitment(
1770 VkDevice device,
1771 VkDeviceMemory memory,
1772 VkDeviceSize* pCommittedMemoryInBytes)
1773 {
1774 *pCommittedMemoryInBytes = 0;
1775 }
1776
1777 VkResult radv_BindBufferMemory(
1778 VkDevice device,
1779 VkBuffer _buffer,
1780 VkDeviceMemory _memory,
1781 VkDeviceSize memoryOffset)
1782 {
1783 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1784 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1785
1786 if (mem) {
1787 buffer->bo = mem->bo;
1788 buffer->offset = memoryOffset;
1789 } else {
1790 buffer->bo = NULL;
1791 buffer->offset = 0;
1792 }
1793
1794 return VK_SUCCESS;
1795 }
1796
1797 VkResult radv_BindImageMemory(
1798 VkDevice device,
1799 VkImage _image,
1800 VkDeviceMemory _memory,
1801 VkDeviceSize memoryOffset)
1802 {
1803 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1804 RADV_FROM_HANDLE(radv_image, image, _image);
1805
1806 if (mem) {
1807 image->bo = mem->bo;
1808 image->offset = memoryOffset;
1809 } else {
1810 image->bo = NULL;
1811 image->offset = 0;
1812 }
1813
1814 return VK_SUCCESS;
1815 }
1816
1817 VkResult radv_QueueBindSparse(
1818 VkQueue queue,
1819 uint32_t bindInfoCount,
1820 const VkBindSparseInfo* pBindInfo,
1821 VkFence fence)
1822 {
1823 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1824 }
1825
1826 VkResult radv_CreateFence(
1827 VkDevice _device,
1828 const VkFenceCreateInfo* pCreateInfo,
1829 const VkAllocationCallbacks* pAllocator,
1830 VkFence* pFence)
1831 {
1832 RADV_FROM_HANDLE(radv_device, device, _device);
1833 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1834 sizeof(*fence), 8,
1835 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1836
1837 if (!fence)
1838 return VK_ERROR_OUT_OF_HOST_MEMORY;
1839
1840 memset(fence, 0, sizeof(*fence));
1841 fence->submitted = false;
1842 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1843 fence->fence = device->ws->create_fence();
1844 if (!fence->fence) {
1845 vk_free2(&device->alloc, pAllocator, fence);
1846 return VK_ERROR_OUT_OF_HOST_MEMORY;
1847 }
1848
1849 *pFence = radv_fence_to_handle(fence);
1850
1851 return VK_SUCCESS;
1852 }
1853
1854 void radv_DestroyFence(
1855 VkDevice _device,
1856 VkFence _fence,
1857 const VkAllocationCallbacks* pAllocator)
1858 {
1859 RADV_FROM_HANDLE(radv_device, device, _device);
1860 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1861
1862 if (!fence)
1863 return;
1864 device->ws->destroy_fence(fence->fence);
1865 vk_free2(&device->alloc, pAllocator, fence);
1866 }
1867
1868 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1869 {
1870 uint64_t current_time;
1871 struct timespec tv;
1872
1873 clock_gettime(CLOCK_MONOTONIC, &tv);
1874 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1875
1876 timeout = MIN2(UINT64_MAX - current_time, timeout);
1877
1878 return current_time + timeout;
1879 }
1880
1881 VkResult radv_WaitForFences(
1882 VkDevice _device,
1883 uint32_t fenceCount,
1884 const VkFence* pFences,
1885 VkBool32 waitAll,
1886 uint64_t timeout)
1887 {
1888 RADV_FROM_HANDLE(radv_device, device, _device);
1889 timeout = radv_get_absolute_timeout(timeout);
1890
1891 if (!waitAll && fenceCount > 1) {
1892 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1893 }
1894
1895 for (uint32_t i = 0; i < fenceCount; ++i) {
1896 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1897 bool expired = false;
1898
1899 if (fence->signalled)
1900 continue;
1901
1902 if (!fence->submitted)
1903 return VK_TIMEOUT;
1904
1905 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1906 if (!expired)
1907 return VK_TIMEOUT;
1908
1909 fence->signalled = true;
1910 }
1911
1912 return VK_SUCCESS;
1913 }
1914
1915 VkResult radv_ResetFences(VkDevice device,
1916 uint32_t fenceCount,
1917 const VkFence *pFences)
1918 {
1919 for (unsigned i = 0; i < fenceCount; ++i) {
1920 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1921 fence->submitted = fence->signalled = false;
1922 }
1923
1924 return VK_SUCCESS;
1925 }
1926
1927 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1928 {
1929 RADV_FROM_HANDLE(radv_device, device, _device);
1930 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1931
1932 if (fence->signalled)
1933 return VK_SUCCESS;
1934 if (!fence->submitted)
1935 return VK_NOT_READY;
1936
1937 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1938 return VK_NOT_READY;
1939
1940 return VK_SUCCESS;
1941 }
1942
1943
1944 // Queue semaphore functions
1945
1946 VkResult radv_CreateSemaphore(
1947 VkDevice _device,
1948 const VkSemaphoreCreateInfo* pCreateInfo,
1949 const VkAllocationCallbacks* pAllocator,
1950 VkSemaphore* pSemaphore)
1951 {
1952 RADV_FROM_HANDLE(radv_device, device, _device);
1953 struct radeon_winsys_sem *sem;
1954
1955 sem = device->ws->create_sem(device->ws);
1956 if (!sem)
1957 return VK_ERROR_OUT_OF_HOST_MEMORY;
1958
1959 *pSemaphore = (VkSemaphore)sem;
1960 return VK_SUCCESS;
1961 }
1962
1963 void radv_DestroySemaphore(
1964 VkDevice _device,
1965 VkSemaphore _semaphore,
1966 const VkAllocationCallbacks* pAllocator)
1967 {
1968 RADV_FROM_HANDLE(radv_device, device, _device);
1969 struct radeon_winsys_sem *sem;
1970 if (!_semaphore)
1971 return;
1972
1973 sem = (struct radeon_winsys_sem *)_semaphore;
1974 device->ws->destroy_sem(sem);
1975 }
1976
1977 VkResult radv_CreateEvent(
1978 VkDevice _device,
1979 const VkEventCreateInfo* pCreateInfo,
1980 const VkAllocationCallbacks* pAllocator,
1981 VkEvent* pEvent)
1982 {
1983 RADV_FROM_HANDLE(radv_device, device, _device);
1984 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1985 sizeof(*event), 8,
1986 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1987
1988 if (!event)
1989 return VK_ERROR_OUT_OF_HOST_MEMORY;
1990
1991 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1992 RADEON_DOMAIN_GTT,
1993 RADEON_FLAG_CPU_ACCESS);
1994 if (!event->bo) {
1995 vk_free2(&device->alloc, pAllocator, event);
1996 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1997 }
1998
1999 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2000
2001 *pEvent = radv_event_to_handle(event);
2002
2003 return VK_SUCCESS;
2004 }
2005
2006 void radv_DestroyEvent(
2007 VkDevice _device,
2008 VkEvent _event,
2009 const VkAllocationCallbacks* pAllocator)
2010 {
2011 RADV_FROM_HANDLE(radv_device, device, _device);
2012 RADV_FROM_HANDLE(radv_event, event, _event);
2013
2014 if (!event)
2015 return;
2016 device->ws->buffer_destroy(event->bo);
2017 vk_free2(&device->alloc, pAllocator, event);
2018 }
2019
2020 VkResult radv_GetEventStatus(
2021 VkDevice _device,
2022 VkEvent _event)
2023 {
2024 RADV_FROM_HANDLE(radv_event, event, _event);
2025
2026 if (*event->map == 1)
2027 return VK_EVENT_SET;
2028 return VK_EVENT_RESET;
2029 }
2030
2031 VkResult radv_SetEvent(
2032 VkDevice _device,
2033 VkEvent _event)
2034 {
2035 RADV_FROM_HANDLE(radv_event, event, _event);
2036 *event->map = 1;
2037
2038 return VK_SUCCESS;
2039 }
2040
2041 VkResult radv_ResetEvent(
2042 VkDevice _device,
2043 VkEvent _event)
2044 {
2045 RADV_FROM_HANDLE(radv_event, event, _event);
2046 *event->map = 0;
2047
2048 return VK_SUCCESS;
2049 }
2050
2051 VkResult radv_CreateBuffer(
2052 VkDevice _device,
2053 const VkBufferCreateInfo* pCreateInfo,
2054 const VkAllocationCallbacks* pAllocator,
2055 VkBuffer* pBuffer)
2056 {
2057 RADV_FROM_HANDLE(radv_device, device, _device);
2058 struct radv_buffer *buffer;
2059
2060 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2061
2062 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2063 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2064 if (buffer == NULL)
2065 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2066
2067 buffer->size = pCreateInfo->size;
2068 buffer->usage = pCreateInfo->usage;
2069 buffer->bo = NULL;
2070 buffer->offset = 0;
2071
2072 *pBuffer = radv_buffer_to_handle(buffer);
2073
2074 return VK_SUCCESS;
2075 }
2076
2077 void radv_DestroyBuffer(
2078 VkDevice _device,
2079 VkBuffer _buffer,
2080 const VkAllocationCallbacks* pAllocator)
2081 {
2082 RADV_FROM_HANDLE(radv_device, device, _device);
2083 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2084
2085 if (!buffer)
2086 return;
2087
2088 vk_free2(&device->alloc, pAllocator, buffer);
2089 }
2090
2091 static inline unsigned
2092 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2093 {
2094 if (stencil)
2095 return image->surface.stencil_tiling_index[level];
2096 else
2097 return image->surface.tiling_index[level];
2098 }
2099
2100 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2101 {
2102 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2103 }
2104
2105 static void
2106 radv_initialise_color_surface(struct radv_device *device,
2107 struct radv_color_buffer_info *cb,
2108 struct radv_image_view *iview)
2109 {
2110 const struct vk_format_description *desc;
2111 unsigned ntype, format, swap, endian;
2112 unsigned blend_clamp = 0, blend_bypass = 0;
2113 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2114 uint64_t va;
2115 const struct radeon_surf *surf = &iview->image->surface;
2116 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2117
2118 desc = vk_format_description(iview->vk_format);
2119
2120 memset(cb, 0, sizeof(*cb));
2121
2122 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2123 va += level_info->offset;
2124 cb->cb_color_base = va >> 8;
2125
2126 /* CMASK variables */
2127 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2128 va += iview->image->cmask.offset;
2129 cb->cb_color_cmask = va >> 8;
2130 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2131
2132 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2133 va += iview->image->dcc_offset;
2134 cb->cb_dcc_base = va >> 8;
2135
2136 uint32_t max_slice = radv_surface_layer_count(iview);
2137 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2138 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2139
2140 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2141 pitch_tile_max = level_info->nblk_x / 8 - 1;
2142 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2143 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2144
2145 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2146 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2147
2148 /* Intensity is implemented as Red, so treat it that way. */
2149 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2150 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2151
2152 if (iview->image->samples > 1) {
2153 unsigned log_samples = util_logbase2(iview->image->samples);
2154
2155 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2156 S_028C74_NUM_FRAGMENTS(log_samples);
2157 }
2158
2159 if (iview->image->fmask.size) {
2160 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2161 if (device->physical_device->rad_info.chip_class >= CIK)
2162 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2163 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2164 cb->cb_color_fmask = va >> 8;
2165 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2166 } else {
2167 /* This must be set for fast clear to work without FMASK. */
2168 if (device->physical_device->rad_info.chip_class >= CIK)
2169 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2170 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2171 cb->cb_color_fmask = cb->cb_color_base;
2172 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2173 }
2174
2175 ntype = radv_translate_color_numformat(iview->vk_format,
2176 desc,
2177 vk_format_get_first_non_void_channel(iview->vk_format));
2178 format = radv_translate_colorformat(iview->vk_format);
2179 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2180 radv_finishme("Illegal color\n");
2181 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2182 endian = radv_colorformat_endian_swap(format);
2183
2184 /* blend clamp should be set for all NORM/SRGB types */
2185 if (ntype == V_028C70_NUMBER_UNORM ||
2186 ntype == V_028C70_NUMBER_SNORM ||
2187 ntype == V_028C70_NUMBER_SRGB)
2188 blend_clamp = 1;
2189
2190 /* set blend bypass according to docs if SINT/UINT or
2191 8/24 COLOR variants */
2192 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2193 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2194 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2195 blend_clamp = 0;
2196 blend_bypass = 1;
2197 }
2198 #if 0
2199 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2200 (format == V_028C70_COLOR_8 ||
2201 format == V_028C70_COLOR_8_8 ||
2202 format == V_028C70_COLOR_8_8_8_8))
2203 ->color_is_int8 = true;
2204 #endif
2205 cb->cb_color_info = S_028C70_FORMAT(format) |
2206 S_028C70_COMP_SWAP(swap) |
2207 S_028C70_BLEND_CLAMP(blend_clamp) |
2208 S_028C70_BLEND_BYPASS(blend_bypass) |
2209 S_028C70_SIMPLE_FLOAT(1) |
2210 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2211 ntype != V_028C70_NUMBER_SNORM &&
2212 ntype != V_028C70_NUMBER_SRGB &&
2213 format != V_028C70_COLOR_8_24 &&
2214 format != V_028C70_COLOR_24_8) |
2215 S_028C70_NUMBER_TYPE(ntype) |
2216 S_028C70_ENDIAN(endian);
2217 if (iview->image->samples > 1)
2218 if (iview->image->fmask.size)
2219 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2220
2221 if (iview->image->cmask.size &&
2222 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2223 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2224
2225 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2226 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2227
2228 if (device->physical_device->rad_info.chip_class >= VI) {
2229 unsigned max_uncompressed_block_size = 2;
2230 if (iview->image->samples > 1) {
2231 if (iview->image->surface.bpe == 1)
2232 max_uncompressed_block_size = 0;
2233 else if (iview->image->surface.bpe == 2)
2234 max_uncompressed_block_size = 1;
2235 }
2236
2237 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2238 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2239 }
2240
2241 /* This must be set for fast clear to work without FMASK. */
2242 if (!iview->image->fmask.size &&
2243 device->physical_device->rad_info.chip_class == SI) {
2244 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2245 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2246 }
2247 }
2248
2249 static void
2250 radv_initialise_ds_surface(struct radv_device *device,
2251 struct radv_ds_buffer_info *ds,
2252 struct radv_image_view *iview)
2253 {
2254 unsigned level = iview->base_mip;
2255 unsigned format;
2256 uint64_t va, s_offs, z_offs;
2257 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2258 memset(ds, 0, sizeof(*ds));
2259 switch (iview->vk_format) {
2260 case VK_FORMAT_D24_UNORM_S8_UINT:
2261 case VK_FORMAT_X8_D24_UNORM_PACK32:
2262 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2263 ds->offset_scale = 2.0f;
2264 break;
2265 case VK_FORMAT_D16_UNORM:
2266 case VK_FORMAT_D16_UNORM_S8_UINT:
2267 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2268 ds->offset_scale = 4.0f;
2269 break;
2270 case VK_FORMAT_D32_SFLOAT:
2271 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2272 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2273 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2274 ds->offset_scale = 1.0f;
2275 break;
2276 default:
2277 break;
2278 }
2279
2280 format = radv_translate_dbformat(iview->vk_format);
2281 if (format == V_028040_Z_INVALID) {
2282 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2283 }
2284
2285 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2286 s_offs = z_offs = va;
2287 z_offs += iview->image->surface.level[level].offset;
2288 s_offs += iview->image->surface.stencil_level[level].offset;
2289
2290 uint32_t max_slice = radv_surface_layer_count(iview);
2291 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2292 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2293 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2294 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2295
2296 if (iview->image->samples > 1)
2297 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2298
2299 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2300 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2301 else
2302 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2303
2304 if (device->physical_device->rad_info.chip_class >= CIK) {
2305 struct radeon_info *info = &device->physical_device->rad_info;
2306 unsigned tiling_index = iview->image->surface.tiling_index[level];
2307 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2308 unsigned macro_index = iview->image->surface.macro_tile_index;
2309 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2310 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2311 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2312
2313 ds->db_depth_info |=
2314 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2315 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2316 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2317 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2318 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2319 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2320 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2321 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2322 } else {
2323 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2324 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2325 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2326 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2327 }
2328
2329 if (iview->image->htile.size && !level) {
2330 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2331 S_028040_ALLOW_EXPCLEAR(1);
2332
2333 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2334 /* Workaround: For a not yet understood reason, the
2335 * combination of MSAA, fast stencil clear and stencil
2336 * decompress messes with subsequent stencil buffer
2337 * uses. Problem was reproduced on Verde, Bonaire,
2338 * Tonga, and Carrizo.
2339 *
2340 * Disabling EXPCLEAR works around the problem.
2341 *
2342 * Check piglit's arb_texture_multisample-stencil-clear
2343 * test if you want to try changing this.
2344 */
2345 if (iview->image->samples <= 1)
2346 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2347 } else
2348 /* Use all of the htile_buffer for depth if there's no stencil. */
2349 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2350
2351 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2352 iview->image->htile.offset;
2353 ds->db_htile_data_base = va >> 8;
2354 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2355 } else {
2356 ds->db_htile_data_base = 0;
2357 ds->db_htile_surface = 0;
2358 }
2359
2360 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2361 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2362
2363 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2364 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2365 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2366 }
2367
2368 VkResult radv_CreateFramebuffer(
2369 VkDevice _device,
2370 const VkFramebufferCreateInfo* pCreateInfo,
2371 const VkAllocationCallbacks* pAllocator,
2372 VkFramebuffer* pFramebuffer)
2373 {
2374 RADV_FROM_HANDLE(radv_device, device, _device);
2375 struct radv_framebuffer *framebuffer;
2376
2377 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2378
2379 size_t size = sizeof(*framebuffer) +
2380 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2381 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2382 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2383 if (framebuffer == NULL)
2384 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2385
2386 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2387 framebuffer->width = pCreateInfo->width;
2388 framebuffer->height = pCreateInfo->height;
2389 framebuffer->layers = pCreateInfo->layers;
2390 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2391 VkImageView _iview = pCreateInfo->pAttachments[i];
2392 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2393 framebuffer->attachments[i].attachment = iview;
2394 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2395 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2396 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2397 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2398 }
2399 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2400 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2401 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2402 }
2403
2404 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2405 return VK_SUCCESS;
2406 }
2407
2408 void radv_DestroyFramebuffer(
2409 VkDevice _device,
2410 VkFramebuffer _fb,
2411 const VkAllocationCallbacks* pAllocator)
2412 {
2413 RADV_FROM_HANDLE(radv_device, device, _device);
2414 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2415
2416 if (!fb)
2417 return;
2418 vk_free2(&device->alloc, pAllocator, fb);
2419 }
2420
2421 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2422 {
2423 switch (address_mode) {
2424 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2425 return V_008F30_SQ_TEX_WRAP;
2426 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2427 return V_008F30_SQ_TEX_MIRROR;
2428 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2429 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2430 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2431 return V_008F30_SQ_TEX_CLAMP_BORDER;
2432 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2433 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2434 default:
2435 unreachable("illegal tex wrap mode");
2436 break;
2437 }
2438 }
2439
2440 static unsigned
2441 radv_tex_compare(VkCompareOp op)
2442 {
2443 switch (op) {
2444 case VK_COMPARE_OP_NEVER:
2445 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2446 case VK_COMPARE_OP_LESS:
2447 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2448 case VK_COMPARE_OP_EQUAL:
2449 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2450 case VK_COMPARE_OP_LESS_OR_EQUAL:
2451 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2452 case VK_COMPARE_OP_GREATER:
2453 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2454 case VK_COMPARE_OP_NOT_EQUAL:
2455 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2456 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2457 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2458 case VK_COMPARE_OP_ALWAYS:
2459 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2460 default:
2461 unreachable("illegal compare mode");
2462 break;
2463 }
2464 }
2465
2466 static unsigned
2467 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2468 {
2469 switch (filter) {
2470 case VK_FILTER_NEAREST:
2471 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2472 V_008F38_SQ_TEX_XY_FILTER_POINT);
2473 case VK_FILTER_LINEAR:
2474 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2475 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2476 case VK_FILTER_CUBIC_IMG:
2477 default:
2478 fprintf(stderr, "illegal texture filter");
2479 return 0;
2480 }
2481 }
2482
2483 static unsigned
2484 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2485 {
2486 switch (mode) {
2487 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2488 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2489 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2490 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2491 default:
2492 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2493 }
2494 }
2495
2496 static unsigned
2497 radv_tex_bordercolor(VkBorderColor bcolor)
2498 {
2499 switch (bcolor) {
2500 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2501 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2502 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2503 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2504 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2505 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2506 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2507 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2508 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2509 default:
2510 break;
2511 }
2512 return 0;
2513 }
2514
2515 static unsigned
2516 radv_tex_aniso_filter(unsigned filter)
2517 {
2518 if (filter < 2)
2519 return 0;
2520 if (filter < 4)
2521 return 1;
2522 if (filter < 8)
2523 return 2;
2524 if (filter < 16)
2525 return 3;
2526 return 4;
2527 }
2528
2529 static void
2530 radv_init_sampler(struct radv_device *device,
2531 struct radv_sampler *sampler,
2532 const VkSamplerCreateInfo *pCreateInfo)
2533 {
2534 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2535 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2536 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2537 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2538
2539 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2540 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2541 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2542 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2543 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2544 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2545 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2546 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2547 S_008F30_DISABLE_CUBE_WRAP(0) |
2548 S_008F30_COMPAT_MODE(is_vi));
2549 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2550 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2551 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2552 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2553 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2554 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2555 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2556 S_008F38_MIP_POINT_PRECLAMP(1) |
2557 S_008F38_DISABLE_LSB_CEIL(1) |
2558 S_008F38_FILTER_PREC_FIX(1) |
2559 S_008F38_ANISO_OVERRIDE(is_vi));
2560 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2561 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2562 }
2563
2564 VkResult radv_CreateSampler(
2565 VkDevice _device,
2566 const VkSamplerCreateInfo* pCreateInfo,
2567 const VkAllocationCallbacks* pAllocator,
2568 VkSampler* pSampler)
2569 {
2570 RADV_FROM_HANDLE(radv_device, device, _device);
2571 struct radv_sampler *sampler;
2572
2573 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2574
2575 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2576 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2577 if (!sampler)
2578 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2579
2580 radv_init_sampler(device, sampler, pCreateInfo);
2581 *pSampler = radv_sampler_to_handle(sampler);
2582
2583 return VK_SUCCESS;
2584 }
2585
2586 void radv_DestroySampler(
2587 VkDevice _device,
2588 VkSampler _sampler,
2589 const VkAllocationCallbacks* pAllocator)
2590 {
2591 RADV_FROM_HANDLE(radv_device, device, _device);
2592 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2593
2594 if (!sampler)
2595 return;
2596 vk_free2(&device->alloc, pAllocator, sampler);
2597 }
2598
2599
2600 /* vk_icd.h does not declare this function, so we declare it here to
2601 * suppress Wmissing-prototypes.
2602 */
2603 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2604 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2605
2606 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2607 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2608 {
2609 /* For the full details on loader interface versioning, see
2610 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2611 * What follows is a condensed summary, to help you navigate the large and
2612 * confusing official doc.
2613 *
2614 * - Loader interface v0 is incompatible with later versions. We don't
2615 * support it.
2616 *
2617 * - In loader interface v1:
2618 * - The first ICD entrypoint called by the loader is
2619 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2620 * entrypoint.
2621 * - The ICD must statically expose no other Vulkan symbol unless it is
2622 * linked with -Bsymbolic.
2623 * - Each dispatchable Vulkan handle created by the ICD must be
2624 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2625 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2626 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2627 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2628 * such loader-managed surfaces.
2629 *
2630 * - Loader interface v2 differs from v1 in:
2631 * - The first ICD entrypoint called by the loader is
2632 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2633 * statically expose this entrypoint.
2634 *
2635 * - Loader interface v3 differs from v2 in:
2636 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2637 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2638 * because the loader no longer does so.
2639 */
2640 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2641 return VK_SUCCESS;
2642 }