projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: add separate fmask tile swizzle counter.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_driver_uuid(void *uuid)
67 {
68 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
69 }
70
71 static void
72 radv_get_device_uuid(struct radeon_info *info, void *uuid)
73 {
74 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
75 }
76
77 static const VkExtensionProperties instance_extensions[] = {
78 {
79 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
80 .specVersion = 25,
81 },
82 #ifdef VK_USE_PLATFORM_XCB_KHR
83 {
84 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
85 .specVersion = 6,
86 },
87 #endif
88 #ifdef VK_USE_PLATFORM_XLIB_KHR
89 {
90 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
91 .specVersion = 6,
92 },
93 #endif
94 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
95 {
96 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
97 .specVersion = 6,
98 },
99 #endif
100 {
101 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
102 .specVersion = 1,
103 },
104 {
105 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
106 .specVersion = 1,
107 },
108 {
109 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
110 .specVersion = 1,
111 },
112 };
113
114 static const VkExtensionProperties common_device_extensions[] = {
115 {
116 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
117 .specVersion = 1,
118 },
119 {
120 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 {
132 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
133 .specVersion = 1,
134 },
135 {
136 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
137 .specVersion = 68,
138 },
139 {
140 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
141 .specVersion = 1,
142 },
143 {
144 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
145 .specVersion = 1,
146 },
147 {
148 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
149 .specVersion = 1,
150 },
151 {
152 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
153 .specVersion = 1,
154 },
155 {
156 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
157 .specVersion = 1,
158 },
159 {
160 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
161 .specVersion = 1,
162 },
163 {
164 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
165 .specVersion = 1,
166 },
167 {
168 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
169 .specVersion = 1,
170 },
171 };
172 static const VkExtensionProperties ext_sema_device_extensions[] = {
173 {
174 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 };
182
183 static VkResult
184 radv_extensions_register(struct radv_instance *instance,
185 struct radv_extensions *extensions,
186 const VkExtensionProperties *new_ext,
187 uint32_t num_ext)
188 {
189 size_t new_size;
190 VkExtensionProperties *new_ptr;
191
192 assert(new_ext && num_ext > 0);
193
194 if (!new_ext)
195 return VK_ERROR_INITIALIZATION_FAILED;
196
197 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
198 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
199 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
200
201 /* Old array continues to be valid, update nothing */
202 if (!new_ptr)
203 return VK_ERROR_OUT_OF_HOST_MEMORY;
204
205 memcpy(&new_ptr[extensions->num_ext], new_ext,
206 num_ext * sizeof(VkExtensionProperties));
207 extensions->ext_array = new_ptr;
208 extensions->num_ext += num_ext;
209
210 return VK_SUCCESS;
211 }
212
213 static void
214 radv_extensions_finish(struct radv_instance *instance,
215 struct radv_extensions *extensions)
216 {
217 assert(extensions);
218
219 if (!extensions)
220 radv_loge("Attemted to free invalid extension struct\n");
221
222 if (extensions->ext_array)
223 vk_free(&instance->alloc, extensions->ext_array);
224 }
225
226 static bool
227 is_extension_enabled(const VkExtensionProperties *extensions,
228 size_t num_ext,
229 const char *name)
230 {
231 assert(extensions && name);
232
233 for (uint32_t i = 0; i < num_ext; i++) {
234 if (strcmp(name, extensions[i].extensionName) == 0)
235 return true;
236 }
237
238 return false;
239 }
240
241 static const char *
242 get_chip_name(enum radeon_family family)
243 {
244 switch (family) {
245 case CHIP_TAHITI: return "AMD RADV TAHITI";
246 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
247 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
248 case CHIP_OLAND: return "AMD RADV OLAND";
249 case CHIP_HAINAN: return "AMD RADV HAINAN";
250 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
251 case CHIP_KAVERI: return "AMD RADV KAVERI";
252 case CHIP_KABINI: return "AMD RADV KABINI";
253 case CHIP_HAWAII: return "AMD RADV HAWAII";
254 case CHIP_MULLINS: return "AMD RADV MULLINS";
255 case CHIP_TONGA: return "AMD RADV TONGA";
256 case CHIP_ICELAND: return "AMD RADV ICELAND";
257 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
258 case CHIP_FIJI: return "AMD RADV FIJI";
259 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
260 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
261 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
262 case CHIP_STONEY: return "AMD RADV STONEY";
263 case CHIP_VEGA10: return "AMD RADV VEGA";
264 case CHIP_RAVEN: return "AMD RADV RAVEN";
265 default: return "AMD RADV unknown";
266 }
267 }
268
269 static VkResult
270 radv_physical_device_init(struct radv_physical_device *device,
271 struct radv_instance *instance,
272 drmDevicePtr drm_device)
273 {
274 const char *path = drm_device->nodes[DRM_NODE_RENDER];
275 VkResult result;
276 drmVersionPtr version;
277 int fd;
278
279 fd = open(path, O_RDWR | O_CLOEXEC);
280 if (fd < 0)
281 return VK_ERROR_INCOMPATIBLE_DRIVER;
282
283 version = drmGetVersion(fd);
284 if (!version) {
285 close(fd);
286 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
287 "failed to get version %s: %m", path);
288 }
289
290 if (strcmp(version->name, "amdgpu")) {
291 drmFreeVersion(version);
292 close(fd);
293 return VK_ERROR_INCOMPATIBLE_DRIVER;
294 }
295 drmFreeVersion(version);
296
297 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
298 device->instance = instance;
299 assert(strlen(path) < ARRAY_SIZE(device->path));
300 strncpy(device->path, path, ARRAY_SIZE(device->path));
301
302 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
303 instance->perftest_flags);
304 if (!device->ws) {
305 result = VK_ERROR_INCOMPATIBLE_DRIVER;
306 goto fail;
307 }
308
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311 result = radv_init_wsi(device);
312 if (result != VK_SUCCESS) {
313 device->ws->destroy(device->ws);
314 goto fail;
315 }
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 radv_finish_wsi(device);
319 device->ws->destroy(device->ws);
320 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
321 "cannot generate UUID");
322 goto fail;
323 }
324
325 result = radv_extensions_register(instance,
326 &device->extensions,
327 common_device_extensions,
328 ARRAY_SIZE(common_device_extensions));
329 if (result != VK_SUCCESS)
330 goto fail;
331
332 if (device->rad_info.has_syncobj) {
333 result = radv_extensions_register(instance,
334 &device->extensions,
335 ext_sema_device_extensions,
336 ARRAY_SIZE(ext_sema_device_extensions));
337 if (result != VK_SUCCESS)
338 goto fail;
339 }
340
341 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
342 device->name = get_chip_name(device->rad_info.family);
343
344 radv_get_driver_uuid(&device->device_uuid);
345 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
346
347 if (device->rad_info.family == CHIP_STONEY ||
348 device->rad_info.chip_class >= GFX9) {
349 device->has_rbplus = true;
350 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
351 }
352
353 return VK_SUCCESS;
354
355 fail:
356 close(fd);
357 return result;
358 }
359
360 static void
361 radv_physical_device_finish(struct radv_physical_device *device)
362 {
363 radv_extensions_finish(device->instance, &device->extensions);
364 radv_finish_wsi(device);
365 device->ws->destroy(device->ws);
366 close(device->local_fd);
367 }
368
369 static void *
370 default_alloc_func(void *pUserData, size_t size, size_t align,
371 VkSystemAllocationScope allocationScope)
372 {
373 return malloc(size);
374 }
375
376 static void *
377 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
378 size_t align, VkSystemAllocationScope allocationScope)
379 {
380 return realloc(pOriginal, size);
381 }
382
383 static void
384 default_free_func(void *pUserData, void *pMemory)
385 {
386 free(pMemory);
387 }
388
389 static const VkAllocationCallbacks default_alloc = {
390 .pUserData = NULL,
391 .pfnAllocation = default_alloc_func,
392 .pfnReallocation = default_realloc_func,
393 .pfnFree = default_free_func,
394 };
395
396 static const struct debug_control radv_debug_options[] = {
397 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
398 {"nodcc", RADV_DEBUG_NO_DCC},
399 {"shaders", RADV_DEBUG_DUMP_SHADERS},
400 {"nocache", RADV_DEBUG_NO_CACHE},
401 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
402 {"nohiz", RADV_DEBUG_NO_HIZ},
403 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
404 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
405 {"allbos", RADV_DEBUG_ALL_BOS},
406 {"noibs", RADV_DEBUG_NO_IBS},
407 {NULL, 0}
408 };
409
410 static const struct debug_control radv_perftest_options[] = {
411 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
412 {"sisched", RADV_PERFTEST_SISCHED},
413 {NULL, 0}
414 };
415
416 VkResult radv_CreateInstance(
417 const VkInstanceCreateInfo* pCreateInfo,
418 const VkAllocationCallbacks* pAllocator,
419 VkInstance* pInstance)
420 {
421 struct radv_instance *instance;
422
423 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
424
425 uint32_t client_version;
426 if (pCreateInfo->pApplicationInfo &&
427 pCreateInfo->pApplicationInfo->apiVersion != 0) {
428 client_version = pCreateInfo->pApplicationInfo->apiVersion;
429 } else {
430 client_version = VK_MAKE_VERSION(1, 0, 0);
431 }
432
433 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
434 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
435 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
436 "Client requested version %d.%d.%d",
437 VK_VERSION_MAJOR(client_version),
438 VK_VERSION_MINOR(client_version),
439 VK_VERSION_PATCH(client_version));
440 }
441
442 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
443 if (!is_extension_enabled(instance_extensions,
444 ARRAY_SIZE(instance_extensions),
445 pCreateInfo->ppEnabledExtensionNames[i]))
446 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
447 }
448
449 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
450 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
451 if (!instance)
452 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
453
454 memset(instance, 0, sizeof(*instance));
455
456 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
457
458 if (pAllocator)
459 instance->alloc = *pAllocator;
460 else
461 instance->alloc = default_alloc;
462
463 instance->apiVersion = client_version;
464 instance->physicalDeviceCount = -1;
465
466 _mesa_locale_init();
467
468 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
469
470 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
471 radv_debug_options);
472
473 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
474 radv_perftest_options);
475
476 *pInstance = radv_instance_to_handle(instance);
477
478 return VK_SUCCESS;
479 }
480
481 void radv_DestroyInstance(
482 VkInstance _instance,
483 const VkAllocationCallbacks* pAllocator)
484 {
485 RADV_FROM_HANDLE(radv_instance, instance, _instance);
486
487 if (!instance)
488 return;
489
490 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
491 radv_physical_device_finish(instance->physicalDevices + i);
492 }
493
494 VG(VALGRIND_DESTROY_MEMPOOL(instance));
495
496 _mesa_locale_fini();
497
498 vk_free(&instance->alloc, instance);
499 }
500
501 static VkResult
502 radv_enumerate_devices(struct radv_instance *instance)
503 {
504 /* TODO: Check for more devices ? */
505 drmDevicePtr devices[8];
506 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
507 int max_devices;
508
509 instance->physicalDeviceCount = 0;
510
511 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
512 if (max_devices < 1)
513 return VK_ERROR_INCOMPATIBLE_DRIVER;
514
515 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
516 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
517 devices[i]->bustype == DRM_BUS_PCI &&
518 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
519
520 result = radv_physical_device_init(instance->physicalDevices +
521 instance->physicalDeviceCount,
522 instance,
523 devices[i]);
524 if (result == VK_SUCCESS)
525 ++instance->physicalDeviceCount;
526 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
527 break;
528 }
529 }
530 drmFreeDevices(devices, max_devices);
531
532 return result;
533 }
534
535 VkResult radv_EnumeratePhysicalDevices(
536 VkInstance _instance,
537 uint32_t* pPhysicalDeviceCount,
538 VkPhysicalDevice* pPhysicalDevices)
539 {
540 RADV_FROM_HANDLE(radv_instance, instance, _instance);
541 VkResult result;
542
543 if (instance->physicalDeviceCount < 0) {
544 result = radv_enumerate_devices(instance);
545 if (result != VK_SUCCESS &&
546 result != VK_ERROR_INCOMPATIBLE_DRIVER)
547 return result;
548 }
549
550 if (!pPhysicalDevices) {
551 *pPhysicalDeviceCount = instance->physicalDeviceCount;
552 } else {
553 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
554 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
555 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
556 }
557
558 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
559 : VK_SUCCESS;
560 }
561
562 void radv_GetPhysicalDeviceFeatures(
563 VkPhysicalDevice physicalDevice,
564 VkPhysicalDeviceFeatures* pFeatures)
565 {
566 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
567 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
568 memset(pFeatures, 0, sizeof(*pFeatures));
569
570 *pFeatures = (VkPhysicalDeviceFeatures) {
571 .robustBufferAccess = true,
572 .fullDrawIndexUint32 = true,
573 .imageCubeArray = true,
574 .independentBlend = true,
575 .geometryShader = !is_gfx9,
576 .tessellationShader = !is_gfx9,
577 .sampleRateShading = true,
578 .dualSrcBlend = true,
579 .logicOp = true,
580 .multiDrawIndirect = true,
581 .drawIndirectFirstInstance = true,
582 .depthClamp = true,
583 .depthBiasClamp = true,
584 .fillModeNonSolid = true,
585 .depthBounds = true,
586 .wideLines = true,
587 .largePoints = true,
588 .alphaToOne = true,
589 .multiViewport = true,
590 .samplerAnisotropy = true,
591 .textureCompressionETC2 = false,
592 .textureCompressionASTC_LDR = false,
593 .textureCompressionBC = true,
594 .occlusionQueryPrecise = true,
595 .pipelineStatisticsQuery = true,
596 .vertexPipelineStoresAndAtomics = true,
597 .fragmentStoresAndAtomics = true,
598 .shaderTessellationAndGeometryPointSize = true,
599 .shaderImageGatherExtended = true,
600 .shaderStorageImageExtendedFormats = true,
601 .shaderStorageImageMultisample = false,
602 .shaderUniformBufferArrayDynamicIndexing = true,
603 .shaderSampledImageArrayDynamicIndexing = true,
604 .shaderStorageBufferArrayDynamicIndexing = true,
605 .shaderStorageImageArrayDynamicIndexing = true,
606 .shaderStorageImageReadWithoutFormat = true,
607 .shaderStorageImageWriteWithoutFormat = true,
608 .shaderClipDistance = true,
609 .shaderCullDistance = true,
610 .shaderFloat64 = true,
611 .shaderInt64 = true,
612 .shaderInt16 = false,
613 .sparseBinding = true,
614 .variableMultisampleRate = true,
615 .inheritedQueries = true,
616 };
617 }
618
619 void radv_GetPhysicalDeviceFeatures2KHR(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceFeatures2KHR *pFeatures)
622 {
623 vk_foreach_struct(ext, pFeatures->pNext) {
624 switch (ext->sType) {
625 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
626 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
627 features->variablePointersStorageBuffer = true;
628 features->variablePointers = false;
629 break;
630 }
631 default:
632 break;
633 }
634 }
635 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
636 }
637
638 void radv_GetPhysicalDeviceProperties(
639 VkPhysicalDevice physicalDevice,
640 VkPhysicalDeviceProperties* pProperties)
641 {
642 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
643 VkSampleCountFlags sample_counts = 0xf;
644
645 /* make sure that the entire descriptor set is addressable with a signed
646 * 32-bit int. So the sum of all limits scaled by descriptor size has to
647 * be at most 2 GiB. the combined image & samples object count as one of
648 * both. This limit is for the pipeline layout, not for the set layout, but
649 * there is no set limit, so we just set a pipeline limit. I don't think
650 * any app is going to hit this soon. */
651 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
652 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
653 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
654 32 /* sampler, largest when combined with image */ +
655 64 /* sampled image */ +
656 64 /* storage image */);
657
658 VkPhysicalDeviceLimits limits = {
659 .maxImageDimension1D = (1 << 14),
660 .maxImageDimension2D = (1 << 14),
661 .maxImageDimension3D = (1 << 11),
662 .maxImageDimensionCube = (1 << 14),
663 .maxImageArrayLayers = (1 << 11),
664 .maxTexelBufferElements = 128 * 1024 * 1024,
665 .maxUniformBufferRange = UINT32_MAX,
666 .maxStorageBufferRange = UINT32_MAX,
667 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
668 .maxMemoryAllocationCount = UINT32_MAX,
669 .maxSamplerAllocationCount = 64 * 1024,
670 .bufferImageGranularity = 64, /* A cache line */
671 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
672 .maxBoundDescriptorSets = MAX_SETS,
673 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
674 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
675 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
676 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
677 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
678 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
679 .maxPerStageResources = max_descriptor_set_size,
680 .maxDescriptorSetSamplers = max_descriptor_set_size,
681 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
682 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
683 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
684 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
685 .maxDescriptorSetSampledImages = max_descriptor_set_size,
686 .maxDescriptorSetStorageImages = max_descriptor_set_size,
687 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
688 .maxVertexInputAttributes = 32,
689 .maxVertexInputBindings = 32,
690 .maxVertexInputAttributeOffset = 2047,
691 .maxVertexInputBindingStride = 2048,
692 .maxVertexOutputComponents = 128,
693 .maxTessellationGenerationLevel = 64,
694 .maxTessellationPatchSize = 32,
695 .maxTessellationControlPerVertexInputComponents = 128,
696 .maxTessellationControlPerVertexOutputComponents = 128,
697 .maxTessellationControlPerPatchOutputComponents = 120,
698 .maxTessellationControlTotalOutputComponents = 4096,
699 .maxTessellationEvaluationInputComponents = 128,
700 .maxTessellationEvaluationOutputComponents = 128,
701 .maxGeometryShaderInvocations = 127,
702 .maxGeometryInputComponents = 64,
703 .maxGeometryOutputComponents = 128,
704 .maxGeometryOutputVertices = 256,
705 .maxGeometryTotalOutputComponents = 1024,
706 .maxFragmentInputComponents = 128,
707 .maxFragmentOutputAttachments = 8,
708 .maxFragmentDualSrcAttachments = 1,
709 .maxFragmentCombinedOutputResources = 8,
710 .maxComputeSharedMemorySize = 32768,
711 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
712 .maxComputeWorkGroupInvocations = 2048,
713 .maxComputeWorkGroupSize = {
714 2048,
715 2048,
716 2048
717 },
718 .subPixelPrecisionBits = 4 /* FIXME */,
719 .subTexelPrecisionBits = 4 /* FIXME */,
720 .mipmapPrecisionBits = 4 /* FIXME */,
721 .maxDrawIndexedIndexValue = UINT32_MAX,
722 .maxDrawIndirectCount = UINT32_MAX,
723 .maxSamplerLodBias = 16,
724 .maxSamplerAnisotropy = 16,
725 .maxViewports = MAX_VIEWPORTS,
726 .maxViewportDimensions = { (1 << 14), (1 << 14) },
727 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
728 .viewportSubPixelBits = 13, /* We take a float? */
729 .minMemoryMapAlignment = 4096, /* A page */
730 .minTexelBufferOffsetAlignment = 1,
731 .minUniformBufferOffsetAlignment = 4,
732 .minStorageBufferOffsetAlignment = 4,
733 .minTexelOffset = -32,
734 .maxTexelOffset = 31,
735 .minTexelGatherOffset = -32,
736 .maxTexelGatherOffset = 31,
737 .minInterpolationOffset = -2,
738 .maxInterpolationOffset = 2,
739 .subPixelInterpolationOffsetBits = 8,
740 .maxFramebufferWidth = (1 << 14),
741 .maxFramebufferHeight = (1 << 14),
742 .maxFramebufferLayers = (1 << 10),
743 .framebufferColorSampleCounts = sample_counts,
744 .framebufferDepthSampleCounts = sample_counts,
745 .framebufferStencilSampleCounts = sample_counts,
746 .framebufferNoAttachmentsSampleCounts = sample_counts,
747 .maxColorAttachments = MAX_RTS,
748 .sampledImageColorSampleCounts = sample_counts,
749 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
750 .sampledImageDepthSampleCounts = sample_counts,
751 .sampledImageStencilSampleCounts = sample_counts,
752 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
753 .maxSampleMaskWords = 1,
754 .timestampComputeAndGraphics = true,
755 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
756 .maxClipDistances = 8,
757 .maxCullDistances = 8,
758 .maxCombinedClipAndCullDistances = 8,
759 .discreteQueuePriorities = 1,
760 .pointSizeRange = { 0.125, 255.875 },
761 .lineWidthRange = { 0.0, 7.9921875 },
762 .pointSizeGranularity = (1.0 / 8.0),
763 .lineWidthGranularity = (1.0 / 128.0),
764 .strictLines = false, /* FINISHME */
765 .standardSampleLocations = true,
766 .optimalBufferCopyOffsetAlignment = 128,
767 .optimalBufferCopyRowPitchAlignment = 128,
768 .nonCoherentAtomSize = 64,
769 };
770
771 *pProperties = (VkPhysicalDeviceProperties) {
772 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
773 .driverVersion = vk_get_driver_version(),
774 .vendorID = 0x1002,
775 .deviceID = pdevice->rad_info.pci_id,
776 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
777 .limits = limits,
778 .sparseProperties = {0},
779 };
780
781 strcpy(pProperties->deviceName, pdevice->name);
782 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
783 }
784
785 void radv_GetPhysicalDeviceProperties2KHR(
786 VkPhysicalDevice physicalDevice,
787 VkPhysicalDeviceProperties2KHR *pProperties)
788 {
789 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
790 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
791
792 vk_foreach_struct(ext, pProperties->pNext) {
793 switch (ext->sType) {
794 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
795 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
796 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
797 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
798 break;
799 }
800 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
801 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
802 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
803 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
804 properties->deviceLUIDValid = false;
805 break;
806 }
807 default:
808 break;
809 }
810 }
811 }
812
813 static void radv_get_physical_device_queue_family_properties(
814 struct radv_physical_device* pdevice,
815 uint32_t* pCount,
816 VkQueueFamilyProperties** pQueueFamilyProperties)
817 {
818 int num_queue_families = 1;
819 int idx;
820 if (pdevice->rad_info.num_compute_rings > 0 &&
821 pdevice->rad_info.chip_class >= CIK &&
822 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
823 num_queue_families++;
824
825 if (pQueueFamilyProperties == NULL) {
826 *pCount = num_queue_families;
827 return;
828 }
829
830 if (!*pCount)
831 return;
832
833 idx = 0;
834 if (*pCount >= 1) {
835 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
836 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
837 VK_QUEUE_COMPUTE_BIT |
838 VK_QUEUE_TRANSFER_BIT |
839 VK_QUEUE_SPARSE_BINDING_BIT,
840 .queueCount = 1,
841 .timestampValidBits = 64,
842 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
843 };
844 idx++;
845 }
846
847 if (pdevice->rad_info.num_compute_rings > 0 &&
848 pdevice->rad_info.chip_class >= CIK &&
849 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
850 if (*pCount > idx) {
851 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
852 .queueFlags = VK_QUEUE_COMPUTE_BIT |
853 VK_QUEUE_TRANSFER_BIT |
854 VK_QUEUE_SPARSE_BINDING_BIT,
855 .queueCount = pdevice->rad_info.num_compute_rings,
856 .timestampValidBits = 64,
857 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
858 };
859 idx++;
860 }
861 }
862 *pCount = idx;
863 }
864
865 void radv_GetPhysicalDeviceQueueFamilyProperties(
866 VkPhysicalDevice physicalDevice,
867 uint32_t* pCount,
868 VkQueueFamilyProperties* pQueueFamilyProperties)
869 {
870 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
871 if (!pQueueFamilyProperties) {
872 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
873 return;
874 }
875 VkQueueFamilyProperties *properties[] = {
876 pQueueFamilyProperties + 0,
877 pQueueFamilyProperties + 1,
878 pQueueFamilyProperties + 2,
879 };
880 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
881 assert(*pCount <= 3);
882 }
883
884 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
885 VkPhysicalDevice physicalDevice,
886 uint32_t* pCount,
887 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
888 {
889 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
890 if (!pQueueFamilyProperties) {
891 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
892 return;
893 }
894 VkQueueFamilyProperties *properties[] = {
895 &pQueueFamilyProperties[0].queueFamilyProperties,
896 &pQueueFamilyProperties[1].queueFamilyProperties,
897 &pQueueFamilyProperties[2].queueFamilyProperties,
898 };
899 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
900 assert(*pCount <= 3);
901 }
902
903 void radv_GetPhysicalDeviceMemoryProperties(
904 VkPhysicalDevice physicalDevice,
905 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
906 {
907 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
908
909 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
910
911 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
912 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
913 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
914 .heapIndex = RADV_MEM_HEAP_VRAM,
915 };
916 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
917 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
918 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
919 .heapIndex = RADV_MEM_HEAP_GTT,
920 };
921 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
922 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
923 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
924 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
925 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
926 };
927 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
928 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
929 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
930 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
931 .heapIndex = RADV_MEM_HEAP_GTT,
932 };
933
934 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
935 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
936 physical_device->rad_info.vram_vis_size);
937
938 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
939 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
940 .size = physical_device->rad_info.vram_size -
941 visible_vram_size,
942 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
943 };
944 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
945 .size = visible_vram_size,
946 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
947 };
948 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
949 .size = physical_device->rad_info.gart_size,
950 .flags = 0,
951 };
952 }
953
954 void radv_GetPhysicalDeviceMemoryProperties2KHR(
955 VkPhysicalDevice physicalDevice,
956 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
957 {
958 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
959 &pMemoryProperties->memoryProperties);
960 }
961
962 static int
963 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
964 int queue_family_index, int idx)
965 {
966 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
967 queue->device = device;
968 queue->queue_family_index = queue_family_index;
969 queue->queue_idx = idx;
970
971 queue->hw_ctx = device->ws->ctx_create(device->ws);
972 if (!queue->hw_ctx)
973 return VK_ERROR_OUT_OF_HOST_MEMORY;
974
975 return VK_SUCCESS;
976 }
977
978 static void
979 radv_queue_finish(struct radv_queue *queue)
980 {
981 if (queue->hw_ctx)
982 queue->device->ws->ctx_destroy(queue->hw_ctx);
983
984 if (queue->initial_preamble_cs)
985 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
986 if (queue->continue_preamble_cs)
987 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
988 if (queue->descriptor_bo)
989 queue->device->ws->buffer_destroy(queue->descriptor_bo);
990 if (queue->scratch_bo)
991 queue->device->ws->buffer_destroy(queue->scratch_bo);
992 if (queue->esgs_ring_bo)
993 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
994 if (queue->gsvs_ring_bo)
995 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
996 if (queue->tess_factor_ring_bo)
997 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
998 if (queue->tess_offchip_ring_bo)
999 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1000 if (queue->compute_scratch_bo)
1001 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1002 }
1003
1004 static void
1005 radv_device_init_gs_info(struct radv_device *device)
1006 {
1007 switch (device->physical_device->rad_info.family) {
1008 case CHIP_OLAND:
1009 case CHIP_HAINAN:
1010 case CHIP_KAVERI:
1011 case CHIP_KABINI:
1012 case CHIP_MULLINS:
1013 case CHIP_ICELAND:
1014 case CHIP_CARRIZO:
1015 case CHIP_STONEY:
1016 device->gs_table_depth = 16;
1017 return;
1018 case CHIP_TAHITI:
1019 case CHIP_PITCAIRN:
1020 case CHIP_VERDE:
1021 case CHIP_BONAIRE:
1022 case CHIP_HAWAII:
1023 case CHIP_TONGA:
1024 case CHIP_FIJI:
1025 case CHIP_POLARIS10:
1026 case CHIP_POLARIS11:
1027 case CHIP_POLARIS12:
1028 case CHIP_VEGA10:
1029 case CHIP_RAVEN:
1030 device->gs_table_depth = 32;
1031 return;
1032 default:
1033 unreachable("unknown GPU");
1034 }
1035 }
1036
1037 VkResult radv_CreateDevice(
1038 VkPhysicalDevice physicalDevice,
1039 const VkDeviceCreateInfo* pCreateInfo,
1040 const VkAllocationCallbacks* pAllocator,
1041 VkDevice* pDevice)
1042 {
1043 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1044 VkResult result;
1045 struct radv_device *device;
1046
1047 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1048 if (!is_extension_enabled(physical_device->extensions.ext_array,
1049 physical_device->extensions.num_ext,
1050 pCreateInfo->ppEnabledExtensionNames[i]))
1051 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1052 }
1053
1054 /* Check enabled features */
1055 if (pCreateInfo->pEnabledFeatures) {
1056 VkPhysicalDeviceFeatures supported_features;
1057 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1058 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1059 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1060 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1061 for (uint32_t i = 0; i < num_features; i++) {
1062 if (enabled_feature[i] && !supported_feature[i])
1063 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1064 }
1065 }
1066
1067 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1068 sizeof(*device), 8,
1069 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1070 if (!device)
1071 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1072
1073 memset(device, 0, sizeof(*device));
1074
1075 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1076 device->instance = physical_device->instance;
1077 device->physical_device = physical_device;
1078
1079 device->debug_flags = device->instance->debug_flags;
1080
1081 device->ws = physical_device->ws;
1082 if (pAllocator)
1083 device->alloc = *pAllocator;
1084 else
1085 device->alloc = physical_device->instance->alloc;
1086
1087 mtx_init(&device->shader_slab_mutex, mtx_plain);
1088 list_inithead(&device->shader_slabs);
1089
1090 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1091 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1092 uint32_t qfi = queue_create->queueFamilyIndex;
1093
1094 device->queues[qfi] = vk_alloc(&device->alloc,
1095 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1096 if (!device->queues[qfi]) {
1097 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1098 goto fail;
1099 }
1100
1101 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1102
1103 device->queue_count[qfi] = queue_create->queueCount;
1104
1105 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1106 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1107 if (result != VK_SUCCESS)
1108 goto fail;
1109 }
1110 }
1111
1112 #if HAVE_LLVM < 0x0400
1113 device->llvm_supports_spill = false;
1114 #else
1115 device->llvm_supports_spill = true;
1116 #endif
1117
1118 /* The maximum number of scratch waves. Scratch space isn't divided
1119 * evenly between CUs. The number is only a function of the number of CUs.
1120 * We can decrease the constant to decrease the scratch buffer size.
1121 *
1122 * sctx->scratch_waves must be >= the maximum posible size of
1123 * 1 threadgroup, so that the hw doesn't hang from being unable
1124 * to start any.
1125 *
1126 * The recommended value is 4 per CU at most. Higher numbers don't
1127 * bring much benefit, but they still occupy chip resources (think
1128 * async compute). I've seen ~2% performance difference between 4 and 32.
1129 */
1130 uint32_t max_threads_per_block = 2048;
1131 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1132 max_threads_per_block / 64);
1133
1134 radv_device_init_gs_info(device);
1135
1136 device->tess_offchip_block_dw_size =
1137 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1138 device->has_distributed_tess =
1139 device->physical_device->rad_info.chip_class >= VI &&
1140 device->physical_device->rad_info.max_se >= 2;
1141
1142 result = radv_device_init_meta(device);
1143 if (result != VK_SUCCESS)
1144 goto fail;
1145
1146 radv_device_init_msaa(device);
1147
1148 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1149 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1150 switch (family) {
1151 case RADV_QUEUE_GENERAL:
1152 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1153 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1154 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1155 break;
1156 case RADV_QUEUE_COMPUTE:
1157 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1158 radeon_emit(device->empty_cs[family], 0);
1159 break;
1160 }
1161 device->ws->cs_finalize(device->empty_cs[family]);
1162
1163 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1164 switch (family) {
1165 case RADV_QUEUE_GENERAL:
1166 case RADV_QUEUE_COMPUTE:
1167 si_cs_emit_cache_flush(device->flush_cs[family],
1168 false,
1169 device->physical_device->rad_info.chip_class,
1170 NULL, 0,
1171 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1172 RADV_CMD_FLAG_INV_ICACHE |
1173 RADV_CMD_FLAG_INV_SMEM_L1 |
1174 RADV_CMD_FLAG_INV_VMEM_L1 |
1175 RADV_CMD_FLAG_INV_GLOBAL_L2);
1176 break;
1177 }
1178 device->ws->cs_finalize(device->flush_cs[family]);
1179
1180 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1181 switch (family) {
1182 case RADV_QUEUE_GENERAL:
1183 case RADV_QUEUE_COMPUTE:
1184 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1185 false,
1186 device->physical_device->rad_info.chip_class,
1187 NULL, 0,
1188 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1189 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1190 RADV_CMD_FLAG_INV_ICACHE |
1191 RADV_CMD_FLAG_INV_SMEM_L1 |
1192 RADV_CMD_FLAG_INV_VMEM_L1 |
1193 RADV_CMD_FLAG_INV_GLOBAL_L2);
1194 break;
1195 }
1196 device->ws->cs_finalize(device->flush_shader_cs[family]);
1197 }
1198
1199 if (getenv("RADV_TRACE_FILE")) {
1200 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1201 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1202 if (!device->trace_bo)
1203 goto fail;
1204
1205 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1206 if (!device->trace_id_ptr)
1207 goto fail;
1208 }
1209
1210 if (device->physical_device->rad_info.chip_class >= CIK)
1211 cik_create_gfx_config(device);
1212
1213 VkPipelineCacheCreateInfo ci;
1214 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1215 ci.pNext = NULL;
1216 ci.flags = 0;
1217 ci.pInitialData = NULL;
1218 ci.initialDataSize = 0;
1219 VkPipelineCache pc;
1220 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1221 &ci, NULL, &pc);
1222 if (result != VK_SUCCESS)
1223 goto fail;
1224
1225 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1226
1227 *pDevice = radv_device_to_handle(device);
1228 return VK_SUCCESS;
1229
1230 fail:
1231 if (device->trace_bo)
1232 device->ws->buffer_destroy(device->trace_bo);
1233
1234 if (device->gfx_init)
1235 device->ws->buffer_destroy(device->gfx_init);
1236
1237 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1238 for (unsigned q = 0; q < device->queue_count[i]; q++)
1239 radv_queue_finish(&device->queues[i][q]);
1240 if (device->queue_count[i])
1241 vk_free(&device->alloc, device->queues[i]);
1242 }
1243
1244 vk_free(&device->alloc, device);
1245 return result;
1246 }
1247
1248 void radv_DestroyDevice(
1249 VkDevice _device,
1250 const VkAllocationCallbacks* pAllocator)
1251 {
1252 RADV_FROM_HANDLE(radv_device, device, _device);
1253
1254 if (!device)
1255 return;
1256
1257 if (device->trace_bo)
1258 device->ws->buffer_destroy(device->trace_bo);
1259
1260 if (device->gfx_init)
1261 device->ws->buffer_destroy(device->gfx_init);
1262
1263 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1264 for (unsigned q = 0; q < device->queue_count[i]; q++)
1265 radv_queue_finish(&device->queues[i][q]);
1266 if (device->queue_count[i])
1267 vk_free(&device->alloc, device->queues[i]);
1268 if (device->empty_cs[i])
1269 device->ws->cs_destroy(device->empty_cs[i]);
1270 if (device->flush_cs[i])
1271 device->ws->cs_destroy(device->flush_cs[i]);
1272 if (device->flush_shader_cs[i])
1273 device->ws->cs_destroy(device->flush_shader_cs[i]);
1274 }
1275 radv_device_finish_meta(device);
1276
1277 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1278 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1279
1280 radv_destroy_shader_slabs(device);
1281
1282 vk_free(&device->alloc, device);
1283 }
1284
1285 VkResult radv_EnumerateInstanceExtensionProperties(
1286 const char* pLayerName,
1287 uint32_t* pPropertyCount,
1288 VkExtensionProperties* pProperties)
1289 {
1290 if (pProperties == NULL) {
1291 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1292 return VK_SUCCESS;
1293 }
1294
1295 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1296 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1297
1298 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1299 return VK_INCOMPLETE;
1300
1301 return VK_SUCCESS;
1302 }
1303
1304 VkResult radv_EnumerateDeviceExtensionProperties(
1305 VkPhysicalDevice physicalDevice,
1306 const char* pLayerName,
1307 uint32_t* pPropertyCount,
1308 VkExtensionProperties* pProperties)
1309 {
1310 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1311
1312 if (pProperties == NULL) {
1313 *pPropertyCount = pdevice->extensions.num_ext;
1314 return VK_SUCCESS;
1315 }
1316
1317 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1318 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1319
1320 if (*pPropertyCount < pdevice->extensions.num_ext)
1321 return VK_INCOMPLETE;
1322
1323 return VK_SUCCESS;
1324 }
1325
1326 VkResult radv_EnumerateInstanceLayerProperties(
1327 uint32_t* pPropertyCount,
1328 VkLayerProperties* pProperties)
1329 {
1330 if (pProperties == NULL) {
1331 *pPropertyCount = 0;
1332 return VK_SUCCESS;
1333 }
1334
1335 /* None supported at this time */
1336 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1337 }
1338
1339 VkResult radv_EnumerateDeviceLayerProperties(
1340 VkPhysicalDevice physicalDevice,
1341 uint32_t* pPropertyCount,
1342 VkLayerProperties* pProperties)
1343 {
1344 if (pProperties == NULL) {
1345 *pPropertyCount = 0;
1346 return VK_SUCCESS;
1347 }
1348
1349 /* None supported at this time */
1350 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1351 }
1352
1353 void radv_GetDeviceQueue(
1354 VkDevice _device,
1355 uint32_t queueFamilyIndex,
1356 uint32_t queueIndex,
1357 VkQueue* pQueue)
1358 {
1359 RADV_FROM_HANDLE(radv_device, device, _device);
1360
1361 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1362 }
1363
1364 static void radv_dump_trace(struct radv_device *device,
1365 struct radeon_winsys_cs *cs)
1366 {
1367 const char *filename = getenv("RADV_TRACE_FILE");
1368 FILE *f = fopen(filename, "w");
1369 if (!f) {
1370 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1371 return;
1372 }
1373
1374 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1375 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1376 fclose(f);
1377 }
1378
1379 static void
1380 fill_geom_tess_rings(struct radv_queue *queue,
1381 uint32_t *map,
1382 bool add_sample_positions,
1383 uint32_t esgs_ring_size,
1384 struct radeon_winsys_bo *esgs_ring_bo,
1385 uint32_t gsvs_ring_size,
1386 struct radeon_winsys_bo *gsvs_ring_bo,
1387 uint32_t tess_factor_ring_size,
1388 struct radeon_winsys_bo *tess_factor_ring_bo,
1389 uint32_t tess_offchip_ring_size,
1390 struct radeon_winsys_bo *tess_offchip_ring_bo)
1391 {
1392 uint64_t esgs_va = 0, gsvs_va = 0;
1393 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1394 uint32_t *desc = &map[4];
1395
1396 if (esgs_ring_bo)
1397 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1398 if (gsvs_ring_bo)
1399 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1400 if (tess_factor_ring_bo)
1401 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1402 if (tess_offchip_ring_bo)
1403 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1404
1405 /* stride 0, num records - size, add tid, swizzle, elsize4,
1406 index stride 64 */
1407 desc[0] = esgs_va;
1408 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1409 S_008F04_STRIDE(0) |
1410 S_008F04_SWIZZLE_ENABLE(true);
1411 desc[2] = esgs_ring_size;
1412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1416 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1418 S_008F0C_ELEMENT_SIZE(1) |
1419 S_008F0C_INDEX_STRIDE(3) |
1420 S_008F0C_ADD_TID_ENABLE(true);
1421
1422 desc += 4;
1423 /* GS entry for ES->GS ring */
1424 /* stride 0, num records - size, elsize0,
1425 index stride 0 */
1426 desc[0] = esgs_va;
1427 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1428 S_008F04_STRIDE(0) |
1429 S_008F04_SWIZZLE_ENABLE(false);
1430 desc[2] = esgs_ring_size;
1431 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1432 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1433 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1434 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1435 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1436 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1437 S_008F0C_ELEMENT_SIZE(0) |
1438 S_008F0C_INDEX_STRIDE(0) |
1439 S_008F0C_ADD_TID_ENABLE(false);
1440
1441 desc += 4;
1442 /* VS entry for GS->VS ring */
1443 /* stride 0, num records - size, elsize0,
1444 index stride 0 */
1445 desc[0] = gsvs_va;
1446 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1447 S_008F04_STRIDE(0) |
1448 S_008F04_SWIZZLE_ENABLE(false);
1449 desc[2] = gsvs_ring_size;
1450 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1451 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1452 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1453 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1454 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1455 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1456 S_008F0C_ELEMENT_SIZE(0) |
1457 S_008F0C_INDEX_STRIDE(0) |
1458 S_008F0C_ADD_TID_ENABLE(false);
1459 desc += 4;
1460
1461 /* stride gsvs_itemsize, num records 64
1462 elsize 4, index stride 16 */
1463 /* shader will patch stride and desc[2] */
1464 desc[0] = gsvs_va;
1465 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1466 S_008F04_STRIDE(0) |
1467 S_008F04_SWIZZLE_ENABLE(true);
1468 desc[2] = 0;
1469 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1470 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1471 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1472 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1473 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1474 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1475 S_008F0C_ELEMENT_SIZE(1) |
1476 S_008F0C_INDEX_STRIDE(1) |
1477 S_008F0C_ADD_TID_ENABLE(true);
1478 desc += 4;
1479
1480 desc[0] = tess_factor_va;
1481 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1482 S_008F04_STRIDE(0) |
1483 S_008F04_SWIZZLE_ENABLE(false);
1484 desc[2] = tess_factor_ring_size;
1485 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1486 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1487 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1488 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1489 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1490 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1491 S_008F0C_ELEMENT_SIZE(0) |
1492 S_008F0C_INDEX_STRIDE(0) |
1493 S_008F0C_ADD_TID_ENABLE(false);
1494 desc += 4;
1495
1496 desc[0] = tess_offchip_va;
1497 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1498 S_008F04_STRIDE(0) |
1499 S_008F04_SWIZZLE_ENABLE(false);
1500 desc[2] = tess_offchip_ring_size;
1501 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1502 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1503 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1504 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1505 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1506 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1507 S_008F0C_ELEMENT_SIZE(0) |
1508 S_008F0C_INDEX_STRIDE(0) |
1509 S_008F0C_ADD_TID_ENABLE(false);
1510 desc += 4;
1511
1512 /* add sample positions after all rings */
1513 memcpy(desc, queue->device->sample_locations_1x, 8);
1514 desc += 2;
1515 memcpy(desc, queue->device->sample_locations_2x, 16);
1516 desc += 4;
1517 memcpy(desc, queue->device->sample_locations_4x, 32);
1518 desc += 8;
1519 memcpy(desc, queue->device->sample_locations_8x, 64);
1520 desc += 16;
1521 memcpy(desc, queue->device->sample_locations_16x, 128);
1522 }
1523
1524 static unsigned
1525 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1526 {
1527 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1528 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1529 device->physical_device->rad_info.family != CHIP_STONEY;
1530 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1531 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1532 device->physical_device->rad_info.max_se;
1533 unsigned offchip_granularity;
1534 unsigned hs_offchip_param;
1535 switch (device->tess_offchip_block_dw_size) {
1536 default:
1537 assert(0);
1538 /* fall through */
1539 case 8192:
1540 offchip_granularity = V_03093C_X_8K_DWORDS;
1541 break;
1542 case 4096:
1543 offchip_granularity = V_03093C_X_4K_DWORDS;
1544 break;
1545 }
1546
1547 switch (device->physical_device->rad_info.chip_class) {
1548 case SI:
1549 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1550 break;
1551 case CIK:
1552 case VI:
1553 case GFX9:
1554 default:
1555 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1556 break;
1557 }
1558
1559 *max_offchip_buffers_p = max_offchip_buffers;
1560 if (device->physical_device->rad_info.chip_class >= CIK) {
1561 if (device->physical_device->rad_info.chip_class >= VI)
1562 --max_offchip_buffers;
1563 hs_offchip_param =
1564 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1565 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1566 } else {
1567 hs_offchip_param =
1568 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1569 }
1570 return hs_offchip_param;
1571 }
1572
1573 static VkResult
1574 radv_get_preamble_cs(struct radv_queue *queue,
1575 uint32_t scratch_size,
1576 uint32_t compute_scratch_size,
1577 uint32_t esgs_ring_size,
1578 uint32_t gsvs_ring_size,
1579 bool needs_tess_rings,
1580 bool needs_sample_positions,
1581 struct radeon_winsys_cs **initial_preamble_cs,
1582 struct radeon_winsys_cs **continue_preamble_cs)
1583 {
1584 struct radeon_winsys_bo *scratch_bo = NULL;
1585 struct radeon_winsys_bo *descriptor_bo = NULL;
1586 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1587 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1588 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1589 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1590 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1591 struct radeon_winsys_cs *dest_cs[2] = {0};
1592 bool add_tess_rings = false, add_sample_positions = false;
1593 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1594 unsigned max_offchip_buffers;
1595 unsigned hs_offchip_param = 0;
1596 if (!queue->has_tess_rings) {
1597 if (needs_tess_rings)
1598 add_tess_rings = true;
1599 }
1600 if (!queue->has_sample_positions) {
1601 if (needs_sample_positions)
1602 add_sample_positions = true;
1603 }
1604 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1605 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1606 &max_offchip_buffers);
1607 tess_offchip_ring_size = max_offchip_buffers *
1608 queue->device->tess_offchip_block_dw_size * 4;
1609
1610 if (scratch_size <= queue->scratch_size &&
1611 compute_scratch_size <= queue->compute_scratch_size &&
1612 esgs_ring_size <= queue->esgs_ring_size &&
1613 gsvs_ring_size <= queue->gsvs_ring_size &&
1614 !add_tess_rings && !add_sample_positions &&
1615 queue->initial_preamble_cs) {
1616 *initial_preamble_cs = queue->initial_preamble_cs;
1617 *continue_preamble_cs = queue->continue_preamble_cs;
1618 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1619 *continue_preamble_cs = NULL;
1620 return VK_SUCCESS;
1621 }
1622
1623 if (scratch_size > queue->scratch_size) {
1624 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1625 scratch_size,
1626 4096,
1627 RADEON_DOMAIN_VRAM,
1628 RADEON_FLAG_NO_CPU_ACCESS);
1629 if (!scratch_bo)
1630 goto fail;
1631 } else
1632 scratch_bo = queue->scratch_bo;
1633
1634 if (compute_scratch_size > queue->compute_scratch_size) {
1635 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1636 compute_scratch_size,
1637 4096,
1638 RADEON_DOMAIN_VRAM,
1639 RADEON_FLAG_NO_CPU_ACCESS);
1640 if (!compute_scratch_bo)
1641 goto fail;
1642
1643 } else
1644 compute_scratch_bo = queue->compute_scratch_bo;
1645
1646 if (esgs_ring_size > queue->esgs_ring_size) {
1647 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1648 esgs_ring_size,
1649 4096,
1650 RADEON_DOMAIN_VRAM,
1651 RADEON_FLAG_NO_CPU_ACCESS);
1652 if (!esgs_ring_bo)
1653 goto fail;
1654 } else {
1655 esgs_ring_bo = queue->esgs_ring_bo;
1656 esgs_ring_size = queue->esgs_ring_size;
1657 }
1658
1659 if (gsvs_ring_size > queue->gsvs_ring_size) {
1660 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1661 gsvs_ring_size,
1662 4096,
1663 RADEON_DOMAIN_VRAM,
1664 RADEON_FLAG_NO_CPU_ACCESS);
1665 if (!gsvs_ring_bo)
1666 goto fail;
1667 } else {
1668 gsvs_ring_bo = queue->gsvs_ring_bo;
1669 gsvs_ring_size = queue->gsvs_ring_size;
1670 }
1671
1672 if (add_tess_rings) {
1673 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1674 tess_factor_ring_size,
1675 256,
1676 RADEON_DOMAIN_VRAM,
1677 RADEON_FLAG_NO_CPU_ACCESS);
1678 if (!tess_factor_ring_bo)
1679 goto fail;
1680 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1681 tess_offchip_ring_size,
1682 256,
1683 RADEON_DOMAIN_VRAM,
1684 RADEON_FLAG_NO_CPU_ACCESS);
1685 if (!tess_offchip_ring_bo)
1686 goto fail;
1687 } else {
1688 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1689 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1690 }
1691
1692 if (scratch_bo != queue->scratch_bo ||
1693 esgs_ring_bo != queue->esgs_ring_bo ||
1694 gsvs_ring_bo != queue->gsvs_ring_bo ||
1695 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1696 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1697 uint32_t size = 0;
1698 if (gsvs_ring_bo || esgs_ring_bo ||
1699 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1700 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1701 if (add_sample_positions)
1702 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1703 }
1704 else if (scratch_bo)
1705 size = 8; /* 2 dword */
1706
1707 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1708 size,
1709 4096,
1710 RADEON_DOMAIN_VRAM,
1711 RADEON_FLAG_CPU_ACCESS);
1712 if (!descriptor_bo)
1713 goto fail;
1714 } else
1715 descriptor_bo = queue->descriptor_bo;
1716
1717 for(int i = 0; i < 2; ++i) {
1718 struct radeon_winsys_cs *cs = NULL;
1719 cs = queue->device->ws->cs_create(queue->device->ws,
1720 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1721 if (!cs)
1722 goto fail;
1723
1724 dest_cs[i] = cs;
1725
1726 if (scratch_bo)
1727 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1728
1729 if (esgs_ring_bo)
1730 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1731
1732 if (gsvs_ring_bo)
1733 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1734
1735 if (tess_factor_ring_bo)
1736 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1737
1738 if (tess_offchip_ring_bo)
1739 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1740
1741 if (descriptor_bo)
1742 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1743
1744 if (descriptor_bo != queue->descriptor_bo) {
1745 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1746
1747 if (scratch_bo) {
1748 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1749 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1750 S_008F04_SWIZZLE_ENABLE(1);
1751 map[0] = scratch_va;
1752 map[1] = rsrc1;
1753 }
1754
1755 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1756 add_sample_positions)
1757 fill_geom_tess_rings(queue, map, add_sample_positions,
1758 esgs_ring_size, esgs_ring_bo,
1759 gsvs_ring_size, gsvs_ring_bo,
1760 tess_factor_ring_size, tess_factor_ring_bo,
1761 tess_offchip_ring_size, tess_offchip_ring_bo);
1762
1763 queue->device->ws->buffer_unmap(descriptor_bo);
1764 }
1765
1766 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1767 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1768 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1769 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1770 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1771 }
1772
1773 if (esgs_ring_bo || gsvs_ring_bo) {
1774 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1775 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1776 radeon_emit(cs, esgs_ring_size >> 8);
1777 radeon_emit(cs, gsvs_ring_size >> 8);
1778 } else {
1779 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1780 radeon_emit(cs, esgs_ring_size >> 8);
1781 radeon_emit(cs, gsvs_ring_size >> 8);
1782 }
1783 }
1784
1785 if (tess_factor_ring_bo) {
1786 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1787 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1788 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1789 S_030938_SIZE(tess_factor_ring_size / 4));
1790 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1791 tf_va >> 8);
1792 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1793 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1794 tf_va >> 40);
1795 }
1796 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1797 } else {
1798 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1799 S_008988_SIZE(tess_factor_ring_size / 4));
1800 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1801 tf_va >> 8);
1802 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1803 hs_offchip_param);
1804 }
1805 }
1806
1807 if (descriptor_bo) {
1808 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1809 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1810 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1811 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1812 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1813 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1814
1815 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1816
1817 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1818 radeon_set_sh_reg_seq(cs, regs[i], 2);
1819 radeon_emit(cs, va);
1820 radeon_emit(cs, va >> 32);
1821 }
1822 }
1823
1824 if (compute_scratch_bo) {
1825 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1826 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1827 S_008F04_SWIZZLE_ENABLE(1);
1828
1829 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1830
1831 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1832 radeon_emit(cs, scratch_va);
1833 radeon_emit(cs, rsrc1);
1834 }
1835
1836 if (!i) {
1837 si_cs_emit_cache_flush(cs,
1838 false,
1839 queue->device->physical_device->rad_info.chip_class,
1840 NULL, 0,
1841 queue->queue_family_index == RING_COMPUTE &&
1842 queue->device->physical_device->rad_info.chip_class >= CIK,
1843 RADV_CMD_FLAG_INV_ICACHE |
1844 RADV_CMD_FLAG_INV_SMEM_L1 |
1845 RADV_CMD_FLAG_INV_VMEM_L1 |
1846 RADV_CMD_FLAG_INV_GLOBAL_L2);
1847 }
1848
1849 if (!queue->device->ws->cs_finalize(cs))
1850 goto fail;
1851 }
1852
1853 if (queue->initial_preamble_cs)
1854 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1855
1856 if (queue->continue_preamble_cs)
1857 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1858
1859 queue->initial_preamble_cs = dest_cs[0];
1860 queue->continue_preamble_cs = dest_cs[1];
1861
1862 if (scratch_bo != queue->scratch_bo) {
1863 if (queue->scratch_bo)
1864 queue->device->ws->buffer_destroy(queue->scratch_bo);
1865 queue->scratch_bo = scratch_bo;
1866 queue->scratch_size = scratch_size;
1867 }
1868
1869 if (compute_scratch_bo != queue->compute_scratch_bo) {
1870 if (queue->compute_scratch_bo)
1871 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1872 queue->compute_scratch_bo = compute_scratch_bo;
1873 queue->compute_scratch_size = compute_scratch_size;
1874 }
1875
1876 if (esgs_ring_bo != queue->esgs_ring_bo) {
1877 if (queue->esgs_ring_bo)
1878 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1879 queue->esgs_ring_bo = esgs_ring_bo;
1880 queue->esgs_ring_size = esgs_ring_size;
1881 }
1882
1883 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1884 if (queue->gsvs_ring_bo)
1885 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1886 queue->gsvs_ring_bo = gsvs_ring_bo;
1887 queue->gsvs_ring_size = gsvs_ring_size;
1888 }
1889
1890 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1891 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1892 }
1893
1894 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1895 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1896 queue->has_tess_rings = true;
1897 }
1898
1899 if (descriptor_bo != queue->descriptor_bo) {
1900 if (queue->descriptor_bo)
1901 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1902
1903 queue->descriptor_bo = descriptor_bo;
1904 }
1905
1906 if (add_sample_positions)
1907 queue->has_sample_positions = true;
1908
1909 *initial_preamble_cs = queue->initial_preamble_cs;
1910 *continue_preamble_cs = queue->continue_preamble_cs;
1911 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1912 *continue_preamble_cs = NULL;
1913 return VK_SUCCESS;
1914 fail:
1915 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1916 if (dest_cs[i])
1917 queue->device->ws->cs_destroy(dest_cs[i]);
1918 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1919 queue->device->ws->buffer_destroy(descriptor_bo);
1920 if (scratch_bo && scratch_bo != queue->scratch_bo)
1921 queue->device->ws->buffer_destroy(scratch_bo);
1922 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1923 queue->device->ws->buffer_destroy(compute_scratch_bo);
1924 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1925 queue->device->ws->buffer_destroy(esgs_ring_bo);
1926 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1927 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1928 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1929 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1930 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1931 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1932 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1933 }
1934
1935 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1936 int num_sems,
1937 const VkSemaphore *sems,
1938 bool reset_temp)
1939 {
1940 int syncobj_idx = 0, sem_idx = 0;
1941
1942 if (num_sems == 0)
1943 return VK_SUCCESS;
1944 for (uint32_t i = 0; i < num_sems; i++) {
1945 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1946
1947 if (sem->temp_syncobj || sem->syncobj)
1948 counts->syncobj_count++;
1949 else
1950 counts->sem_count++;
1951 }
1952
1953 if (counts->syncobj_count) {
1954 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1955 if (!counts->syncobj)
1956 return VK_ERROR_OUT_OF_HOST_MEMORY;
1957 }
1958
1959 if (counts->sem_count) {
1960 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1961 if (!counts->sem) {
1962 free(counts->syncobj);
1963 return VK_ERROR_OUT_OF_HOST_MEMORY;
1964 }
1965 }
1966
1967 for (uint32_t i = 0; i < num_sems; i++) {
1968 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1969
1970 if (sem->temp_syncobj) {
1971 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1972 if (reset_temp) {
1973 /* after we wait on a temp import - drop it */
1974 sem->temp_syncobj = 0;
1975 }
1976 }
1977 else if (sem->syncobj)
1978 counts->syncobj[syncobj_idx++] = sem->syncobj;
1979 else {
1980 assert(sem->sem);
1981 counts->sem[sem_idx++] = sem->sem;
1982 }
1983 }
1984
1985 return VK_SUCCESS;
1986 }
1987
1988 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1989 {
1990 free(sem_info->wait.syncobj);
1991 free(sem_info->wait.sem);
1992 free(sem_info->signal.syncobj);
1993 free(sem_info->signal.sem);
1994 }
1995
1996 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1997 int num_wait_sems,
1998 const VkSemaphore *wait_sems,
1999 int num_signal_sems,
2000 const VkSemaphore *signal_sems)
2001 {
2002 VkResult ret;
2003 memset(sem_info, 0, sizeof(*sem_info));
2004
2005 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2006 if (ret)
2007 return ret;
2008 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2009 if (ret)
2010 radv_free_sem_info(sem_info);
2011
2012 /* caller can override these */
2013 sem_info->cs_emit_wait = true;
2014 sem_info->cs_emit_signal = true;
2015 return ret;
2016 }
2017
2018 VkResult radv_QueueSubmit(
2019 VkQueue _queue,
2020 uint32_t submitCount,
2021 const VkSubmitInfo* pSubmits,
2022 VkFence _fence)
2023 {
2024 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2025 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2026 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2027 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2028 int ret;
2029 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2030 uint32_t scratch_size = 0;
2031 uint32_t compute_scratch_size = 0;
2032 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2033 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
2034 VkResult result;
2035 bool fence_emitted = false;
2036 bool tess_rings_needed = false;
2037 bool sample_positions_needed = false;
2038
2039 /* Do this first so failing to allocate scratch buffers can't result in
2040 * partially executed submissions. */
2041 for (uint32_t i = 0; i < submitCount; i++) {
2042 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2044 pSubmits[i].pCommandBuffers[j]);
2045
2046 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2047 compute_scratch_size = MAX2(compute_scratch_size,
2048 cmd_buffer->compute_scratch_size_needed);
2049 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2050 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2051 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2052 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2053 }
2054 }
2055
2056 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2057 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2058 sample_positions_needed,
2059 &initial_preamble_cs, &continue_preamble_cs);
2060 if (result != VK_SUCCESS)
2061 return result;
2062
2063 for (uint32_t i = 0; i < submitCount; i++) {
2064 struct radeon_winsys_cs **cs_array;
2065 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2066 bool can_patch = !do_flush;
2067 uint32_t advance;
2068 struct radv_winsys_sem_info sem_info;
2069
2070 result = radv_alloc_sem_info(&sem_info,
2071 pSubmits[i].waitSemaphoreCount,
2072 pSubmits[i].pWaitSemaphores,
2073 pSubmits[i].signalSemaphoreCount,
2074 pSubmits[i].pSignalSemaphores);
2075 if (result != VK_SUCCESS)
2076 return result;
2077
2078 if (!pSubmits[i].commandBufferCount) {
2079 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2080 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2081 &queue->device->empty_cs[queue->queue_family_index],
2082 1, NULL, NULL,
2083 &sem_info,
2084 false, base_fence);
2085 if (ret) {
2086 radv_loge("failed to submit CS %d\n", i);
2087 abort();
2088 }
2089 fence_emitted = true;
2090 }
2091 radv_free_sem_info(&sem_info);
2092 continue;
2093 }
2094
2095 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2096 (pSubmits[i].commandBufferCount + do_flush));
2097
2098 if(do_flush)
2099 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
2100 queue->device->flush_shader_cs[queue->queue_family_index] :
2101 queue->device->flush_cs[queue->queue_family_index];
2102
2103 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2104 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2105 pSubmits[i].pCommandBuffers[j]);
2106 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2107
2108 cs_array[j + do_flush] = cmd_buffer->cs;
2109 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2110 can_patch = false;
2111 }
2112
2113 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
2114 advance = MIN2(max_cs_submission,
2115 pSubmits[i].commandBufferCount + do_flush - j);
2116
2117 if (queue->device->trace_bo)
2118 *queue->device->trace_id_ptr = 0;
2119
2120 sem_info.cs_emit_wait = j == 0;
2121 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount + do_flush;
2122
2123 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2124 advance, initial_preamble_cs, continue_preamble_cs,
2125 &sem_info,
2126 can_patch, base_fence);
2127
2128 if (ret) {
2129 radv_loge("failed to submit CS %d\n", i);
2130 abort();
2131 }
2132 fence_emitted = true;
2133 if (queue->device->trace_bo) {
2134 bool success = queue->device->ws->ctx_wait_idle(
2135 queue->hw_ctx,
2136 radv_queue_family_to_ring(
2137 queue->queue_family_index),
2138 queue->queue_idx);
2139
2140 if (!success) { /* Hang */
2141 radv_dump_trace(queue->device, cs_array[j]);
2142 abort();
2143 }
2144 }
2145 }
2146
2147 radv_free_sem_info(&sem_info);
2148 free(cs_array);
2149 }
2150
2151 if (fence) {
2152 if (!fence_emitted) {
2153 struct radv_winsys_sem_info sem_info = {0};
2154 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2155 &queue->device->empty_cs[queue->queue_family_index],
2156 1, NULL, NULL, &sem_info,
2157 false, base_fence);
2158 }
2159 fence->submitted = true;
2160 }
2161
2162 return VK_SUCCESS;
2163 }
2164
2165 VkResult radv_QueueWaitIdle(
2166 VkQueue _queue)
2167 {
2168 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2169
2170 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2171 radv_queue_family_to_ring(queue->queue_family_index),
2172 queue->queue_idx);
2173 return VK_SUCCESS;
2174 }
2175
2176 VkResult radv_DeviceWaitIdle(
2177 VkDevice _device)
2178 {
2179 RADV_FROM_HANDLE(radv_device, device, _device);
2180
2181 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2182 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2183 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2184 }
2185 }
2186 return VK_SUCCESS;
2187 }
2188
2189 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2190 VkInstance instance,
2191 const char* pName)
2192 {
2193 return radv_lookup_entrypoint(pName);
2194 }
2195
2196 /* The loader wants us to expose a second GetInstanceProcAddr function
2197 * to work around certain LD_PRELOAD issues seen in apps.
2198 */
2199 PUBLIC
2200 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2201 VkInstance instance,
2202 const char* pName);
2203
2204 PUBLIC
2205 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2206 VkInstance instance,
2207 const char* pName)
2208 {
2209 return radv_GetInstanceProcAddr(instance, pName);
2210 }
2211
2212 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2213 VkDevice device,
2214 const char* pName)
2215 {
2216 return radv_lookup_entrypoint(pName);
2217 }
2218
2219 bool radv_get_memory_fd(struct radv_device *device,
2220 struct radv_device_memory *memory,
2221 int *pFD)
2222 {
2223 struct radeon_bo_metadata metadata;
2224
2225 if (memory->image) {
2226 radv_init_metadata(device, memory->image, &metadata);
2227 device->ws->buffer_set_metadata(memory->bo, &metadata);
2228 }
2229
2230 return device->ws->buffer_get_fd(device->ws, memory->bo,
2231 pFD);
2232 }
2233
2234 VkResult radv_AllocateMemory(
2235 VkDevice _device,
2236 const VkMemoryAllocateInfo* pAllocateInfo,
2237 const VkAllocationCallbacks* pAllocator,
2238 VkDeviceMemory* pMem)
2239 {
2240 RADV_FROM_HANDLE(radv_device, device, _device);
2241 struct radv_device_memory *mem;
2242 VkResult result;
2243 enum radeon_bo_domain domain;
2244 uint32_t flags = 0;
2245
2246 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2247
2248 if (pAllocateInfo->allocationSize == 0) {
2249 /* Apparently, this is allowed */
2250 *pMem = VK_NULL_HANDLE;
2251 return VK_SUCCESS;
2252 }
2253
2254 const VkImportMemoryFdInfoKHR *import_info =
2255 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2256 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2257 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2258
2259 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2260 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2261 if (mem == NULL)
2262 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2263
2264 if (dedicate_info) {
2265 mem->image = radv_image_from_handle(dedicate_info->image);
2266 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2267 } else {
2268 mem->image = NULL;
2269 mem->buffer = NULL;
2270 }
2271
2272 if (import_info) {
2273 assert(import_info->handleType ==
2274 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2275 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2276 NULL, NULL);
2277 if (!mem->bo) {
2278 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2279 goto fail;
2280 } else {
2281 close(import_info->fd);
2282 goto out_success;
2283 }
2284 }
2285
2286 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2287 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2288 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2289 domain = RADEON_DOMAIN_GTT;
2290 else
2291 domain = RADEON_DOMAIN_VRAM;
2292
2293 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2294 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2295 else
2296 flags |= RADEON_FLAG_CPU_ACCESS;
2297
2298 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2299 flags |= RADEON_FLAG_GTT_WC;
2300
2301 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2302 domain, flags);
2303
2304 if (!mem->bo) {
2305 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2306 goto fail;
2307 }
2308 mem->type_index = pAllocateInfo->memoryTypeIndex;
2309 out_success:
2310 *pMem = radv_device_memory_to_handle(mem);
2311
2312 return VK_SUCCESS;
2313
2314 fail:
2315 vk_free2(&device->alloc, pAllocator, mem);
2316
2317 return result;
2318 }
2319
2320 void radv_FreeMemory(
2321 VkDevice _device,
2322 VkDeviceMemory _mem,
2323 const VkAllocationCallbacks* pAllocator)
2324 {
2325 RADV_FROM_HANDLE(radv_device, device, _device);
2326 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2327
2328 if (mem == NULL)
2329 return;
2330
2331 device->ws->buffer_destroy(mem->bo);
2332 mem->bo = NULL;
2333
2334 vk_free2(&device->alloc, pAllocator, mem);
2335 }
2336
2337 VkResult radv_MapMemory(
2338 VkDevice _device,
2339 VkDeviceMemory _memory,
2340 VkDeviceSize offset,
2341 VkDeviceSize size,
2342 VkMemoryMapFlags flags,
2343 void** ppData)
2344 {
2345 RADV_FROM_HANDLE(radv_device, device, _device);
2346 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2347
2348 if (mem == NULL) {
2349 *ppData = NULL;
2350 return VK_SUCCESS;
2351 }
2352
2353 *ppData = device->ws->buffer_map(mem->bo);
2354 if (*ppData) {
2355 *ppData += offset;
2356 return VK_SUCCESS;
2357 }
2358
2359 return VK_ERROR_MEMORY_MAP_FAILED;
2360 }
2361
2362 void radv_UnmapMemory(
2363 VkDevice _device,
2364 VkDeviceMemory _memory)
2365 {
2366 RADV_FROM_HANDLE(radv_device, device, _device);
2367 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2368
2369 if (mem == NULL)
2370 return;
2371
2372 device->ws->buffer_unmap(mem->bo);
2373 }
2374
2375 VkResult radv_FlushMappedMemoryRanges(
2376 VkDevice _device,
2377 uint32_t memoryRangeCount,
2378 const VkMappedMemoryRange* pMemoryRanges)
2379 {
2380 return VK_SUCCESS;
2381 }
2382
2383 VkResult radv_InvalidateMappedMemoryRanges(
2384 VkDevice _device,
2385 uint32_t memoryRangeCount,
2386 const VkMappedMemoryRange* pMemoryRanges)
2387 {
2388 return VK_SUCCESS;
2389 }
2390
2391 void radv_GetBufferMemoryRequirements(
2392 VkDevice device,
2393 VkBuffer _buffer,
2394 VkMemoryRequirements* pMemoryRequirements)
2395 {
2396 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2397
2398 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2399
2400 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2401 pMemoryRequirements->alignment = 4096;
2402 else
2403 pMemoryRequirements->alignment = 16;
2404
2405 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2406 }
2407
2408 void radv_GetBufferMemoryRequirements2KHR(
2409 VkDevice device,
2410 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2411 VkMemoryRequirements2KHR* pMemoryRequirements)
2412 {
2413 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2414 &pMemoryRequirements->memoryRequirements);
2415
2416 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2417 switch (ext->sType) {
2418 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2419 VkMemoryDedicatedRequirementsKHR *req =
2420 (VkMemoryDedicatedRequirementsKHR *) ext;
2421 req->requiresDedicatedAllocation = false;
2422 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2423 break;
2424 }
2425 default:
2426 break;
2427 }
2428 }
2429 }
2430
2431 void radv_GetImageMemoryRequirements(
2432 VkDevice device,
2433 VkImage _image,
2434 VkMemoryRequirements* pMemoryRequirements)
2435 {
2436 RADV_FROM_HANDLE(radv_image, image, _image);
2437
2438 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2439
2440 pMemoryRequirements->size = image->size;
2441 pMemoryRequirements->alignment = image->alignment;
2442 }
2443
2444 void radv_GetImageMemoryRequirements2KHR(
2445 VkDevice device,
2446 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2447 VkMemoryRequirements2KHR* pMemoryRequirements)
2448 {
2449 radv_GetImageMemoryRequirements(device, pInfo->image,
2450 &pMemoryRequirements->memoryRequirements);
2451
2452 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2453
2454 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2455 switch (ext->sType) {
2456 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2457 VkMemoryDedicatedRequirementsKHR *req =
2458 (VkMemoryDedicatedRequirementsKHR *) ext;
2459 req->requiresDedicatedAllocation = image->shareable;
2460 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2461 break;
2462 }
2463 default:
2464 break;
2465 }
2466 }
2467 }
2468
2469 void radv_GetImageSparseMemoryRequirements(
2470 VkDevice device,
2471 VkImage image,
2472 uint32_t* pSparseMemoryRequirementCount,
2473 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2474 {
2475 stub();
2476 }
2477
2478 void radv_GetImageSparseMemoryRequirements2KHR(
2479 VkDevice device,
2480 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2481 uint32_t* pSparseMemoryRequirementCount,
2482 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2483 {
2484 stub();
2485 }
2486
2487 void radv_GetDeviceMemoryCommitment(
2488 VkDevice device,
2489 VkDeviceMemory memory,
2490 VkDeviceSize* pCommittedMemoryInBytes)
2491 {
2492 *pCommittedMemoryInBytes = 0;
2493 }
2494
2495 VkResult radv_BindBufferMemory(
2496 VkDevice device,
2497 VkBuffer _buffer,
2498 VkDeviceMemory _memory,
2499 VkDeviceSize memoryOffset)
2500 {
2501 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2502 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2503
2504 if (mem) {
2505 buffer->bo = mem->bo;
2506 buffer->offset = memoryOffset;
2507 } else {
2508 buffer->bo = NULL;
2509 buffer->offset = 0;
2510 }
2511
2512 return VK_SUCCESS;
2513 }
2514
2515 VkResult radv_BindImageMemory(
2516 VkDevice device,
2517 VkImage _image,
2518 VkDeviceMemory _memory,
2519 VkDeviceSize memoryOffset)
2520 {
2521 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2522 RADV_FROM_HANDLE(radv_image, image, _image);
2523
2524 if (mem) {
2525 image->bo = mem->bo;
2526 image->offset = memoryOffset;
2527 } else {
2528 image->bo = NULL;
2529 image->offset = 0;
2530 }
2531
2532 return VK_SUCCESS;
2533 }
2534
2535
2536 static void
2537 radv_sparse_buffer_bind_memory(struct radv_device *device,
2538 const VkSparseBufferMemoryBindInfo *bind)
2539 {
2540 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2541
2542 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2543 struct radv_device_memory *mem = NULL;
2544
2545 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2546 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2547
2548 device->ws->buffer_virtual_bind(buffer->bo,
2549 bind->pBinds[i].resourceOffset,
2550 bind->pBinds[i].size,
2551 mem ? mem->bo : NULL,
2552 bind->pBinds[i].memoryOffset);
2553 }
2554 }
2555
2556 static void
2557 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2558 const VkSparseImageOpaqueMemoryBindInfo *bind)
2559 {
2560 RADV_FROM_HANDLE(radv_image, image, bind->image);
2561
2562 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2563 struct radv_device_memory *mem = NULL;
2564
2565 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2566 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2567
2568 device->ws->buffer_virtual_bind(image->bo,
2569 bind->pBinds[i].resourceOffset,
2570 bind->pBinds[i].size,
2571 mem ? mem->bo : NULL,
2572 bind->pBinds[i].memoryOffset);
2573 }
2574 }
2575
2576 VkResult radv_QueueBindSparse(
2577 VkQueue _queue,
2578 uint32_t bindInfoCount,
2579 const VkBindSparseInfo* pBindInfo,
2580 VkFence _fence)
2581 {
2582 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2583 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2584 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2585 bool fence_emitted = false;
2586
2587 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2588 struct radv_winsys_sem_info sem_info;
2589 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2590 radv_sparse_buffer_bind_memory(queue->device,
2591 pBindInfo[i].pBufferBinds + j);
2592 }
2593
2594 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2595 radv_sparse_image_opaque_bind_memory(queue->device,
2596 pBindInfo[i].pImageOpaqueBinds + j);
2597 }
2598
2599 VkResult result;
2600 result = radv_alloc_sem_info(&sem_info,
2601 pBindInfo[i].waitSemaphoreCount,
2602 pBindInfo[i].pWaitSemaphores,
2603 pBindInfo[i].signalSemaphoreCount,
2604 pBindInfo[i].pSignalSemaphores);
2605 if (result != VK_SUCCESS)
2606 return result;
2607
2608 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2609 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2610 &queue->device->empty_cs[queue->queue_family_index],
2611 1, NULL, NULL,
2612 &sem_info,
2613 false, base_fence);
2614 fence_emitted = true;
2615 if (fence)
2616 fence->submitted = true;
2617 }
2618
2619 radv_free_sem_info(&sem_info);
2620
2621 }
2622
2623 if (fence && !fence_emitted) {
2624 fence->signalled = true;
2625 }
2626
2627 return VK_SUCCESS;
2628 }
2629
2630 VkResult radv_CreateFence(
2631 VkDevice _device,
2632 const VkFenceCreateInfo* pCreateInfo,
2633 const VkAllocationCallbacks* pAllocator,
2634 VkFence* pFence)
2635 {
2636 RADV_FROM_HANDLE(radv_device, device, _device);
2637 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2638 sizeof(*fence), 8,
2639 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2640
2641 if (!fence)
2642 return VK_ERROR_OUT_OF_HOST_MEMORY;
2643
2644 memset(fence, 0, sizeof(*fence));
2645 fence->submitted = false;
2646 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2647 fence->fence = device->ws->create_fence();
2648 if (!fence->fence) {
2649 vk_free2(&device->alloc, pAllocator, fence);
2650 return VK_ERROR_OUT_OF_HOST_MEMORY;
2651 }
2652
2653 *pFence = radv_fence_to_handle(fence);
2654
2655 return VK_SUCCESS;
2656 }
2657
2658 void radv_DestroyFence(
2659 VkDevice _device,
2660 VkFence _fence,
2661 const VkAllocationCallbacks* pAllocator)
2662 {
2663 RADV_FROM_HANDLE(radv_device, device, _device);
2664 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2665
2666 if (!fence)
2667 return;
2668 device->ws->destroy_fence(fence->fence);
2669 vk_free2(&device->alloc, pAllocator, fence);
2670 }
2671
2672 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2673 {
2674 uint64_t current_time;
2675 struct timespec tv;
2676
2677 clock_gettime(CLOCK_MONOTONIC, &tv);
2678 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2679
2680 timeout = MIN2(UINT64_MAX - current_time, timeout);
2681
2682 return current_time + timeout;
2683 }
2684
2685 VkResult radv_WaitForFences(
2686 VkDevice _device,
2687 uint32_t fenceCount,
2688 const VkFence* pFences,
2689 VkBool32 waitAll,
2690 uint64_t timeout)
2691 {
2692 RADV_FROM_HANDLE(radv_device, device, _device);
2693 timeout = radv_get_absolute_timeout(timeout);
2694
2695 if (!waitAll && fenceCount > 1) {
2696 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2697 }
2698
2699 for (uint32_t i = 0; i < fenceCount; ++i) {
2700 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2701 bool expired = false;
2702
2703 if (fence->signalled)
2704 continue;
2705
2706 if (!fence->submitted)
2707 return VK_TIMEOUT;
2708
2709 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2710 if (!expired)
2711 return VK_TIMEOUT;
2712
2713 fence->signalled = true;
2714 }
2715
2716 return VK_SUCCESS;
2717 }
2718
2719 VkResult radv_ResetFences(VkDevice device,
2720 uint32_t fenceCount,
2721 const VkFence *pFences)
2722 {
2723 for (unsigned i = 0; i < fenceCount; ++i) {
2724 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2725 fence->submitted = fence->signalled = false;
2726 }
2727
2728 return VK_SUCCESS;
2729 }
2730
2731 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2732 {
2733 RADV_FROM_HANDLE(radv_device, device, _device);
2734 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2735
2736 if (fence->signalled)
2737 return VK_SUCCESS;
2738 if (!fence->submitted)
2739 return VK_NOT_READY;
2740
2741 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2742 return VK_NOT_READY;
2743
2744 return VK_SUCCESS;
2745 }
2746
2747
2748 // Queue semaphore functions
2749
2750 VkResult radv_CreateSemaphore(
2751 VkDevice _device,
2752 const VkSemaphoreCreateInfo* pCreateInfo,
2753 const VkAllocationCallbacks* pAllocator,
2754 VkSemaphore* pSemaphore)
2755 {
2756 RADV_FROM_HANDLE(radv_device, device, _device);
2757 const VkExportSemaphoreCreateInfoKHR *export =
2758 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2759 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2760 export ? export->handleTypes : 0;
2761
2762 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2763 sizeof(*sem), 8,
2764 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2765 if (!sem)
2766 return VK_ERROR_OUT_OF_HOST_MEMORY;
2767
2768 sem->temp_syncobj = 0;
2769 /* create a syncobject if we are going to export this semaphore */
2770 if (handleTypes) {
2771 assert (device->physical_device->rad_info.has_syncobj);
2772 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2773 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2774 if (ret) {
2775 vk_free2(&device->alloc, pAllocator, sem);
2776 return VK_ERROR_OUT_OF_HOST_MEMORY;
2777 }
2778 sem->sem = NULL;
2779 } else {
2780 sem->sem = device->ws->create_sem(device->ws);
2781 if (!sem->sem) {
2782 vk_free2(&device->alloc, pAllocator, sem);
2783 return VK_ERROR_OUT_OF_HOST_MEMORY;
2784 }
2785 sem->syncobj = 0;
2786 }
2787
2788 *pSemaphore = radv_semaphore_to_handle(sem);
2789 return VK_SUCCESS;
2790 }
2791
2792 void radv_DestroySemaphore(
2793 VkDevice _device,
2794 VkSemaphore _semaphore,
2795 const VkAllocationCallbacks* pAllocator)
2796 {
2797 RADV_FROM_HANDLE(radv_device, device, _device);
2798 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2799 if (!_semaphore)
2800 return;
2801
2802 if (sem->syncobj)
2803 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2804 else
2805 device->ws->destroy_sem(sem->sem);
2806 vk_free2(&device->alloc, pAllocator, sem);
2807 }
2808
2809 VkResult radv_CreateEvent(
2810 VkDevice _device,
2811 const VkEventCreateInfo* pCreateInfo,
2812 const VkAllocationCallbacks* pAllocator,
2813 VkEvent* pEvent)
2814 {
2815 RADV_FROM_HANDLE(radv_device, device, _device);
2816 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2817 sizeof(*event), 8,
2818 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2819
2820 if (!event)
2821 return VK_ERROR_OUT_OF_HOST_MEMORY;
2822
2823 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2824 RADEON_DOMAIN_GTT,
2825 RADEON_FLAG_CPU_ACCESS);
2826 if (!event->bo) {
2827 vk_free2(&device->alloc, pAllocator, event);
2828 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2829 }
2830
2831 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2832
2833 *pEvent = radv_event_to_handle(event);
2834
2835 return VK_SUCCESS;
2836 }
2837
2838 void radv_DestroyEvent(
2839 VkDevice _device,
2840 VkEvent _event,
2841 const VkAllocationCallbacks* pAllocator)
2842 {
2843 RADV_FROM_HANDLE(radv_device, device, _device);
2844 RADV_FROM_HANDLE(radv_event, event, _event);
2845
2846 if (!event)
2847 return;
2848 device->ws->buffer_destroy(event->bo);
2849 vk_free2(&device->alloc, pAllocator, event);
2850 }
2851
2852 VkResult radv_GetEventStatus(
2853 VkDevice _device,
2854 VkEvent _event)
2855 {
2856 RADV_FROM_HANDLE(radv_event, event, _event);
2857
2858 if (*event->map == 1)
2859 return VK_EVENT_SET;
2860 return VK_EVENT_RESET;
2861 }
2862
2863 VkResult radv_SetEvent(
2864 VkDevice _device,
2865 VkEvent _event)
2866 {
2867 RADV_FROM_HANDLE(radv_event, event, _event);
2868 *event->map = 1;
2869
2870 return VK_SUCCESS;
2871 }
2872
2873 VkResult radv_ResetEvent(
2874 VkDevice _device,
2875 VkEvent _event)
2876 {
2877 RADV_FROM_HANDLE(radv_event, event, _event);
2878 *event->map = 0;
2879
2880 return VK_SUCCESS;
2881 }
2882
2883 VkResult radv_CreateBuffer(
2884 VkDevice _device,
2885 const VkBufferCreateInfo* pCreateInfo,
2886 const VkAllocationCallbacks* pAllocator,
2887 VkBuffer* pBuffer)
2888 {
2889 RADV_FROM_HANDLE(radv_device, device, _device);
2890 struct radv_buffer *buffer;
2891
2892 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2893
2894 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2895 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2896 if (buffer == NULL)
2897 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2898
2899 buffer->size = pCreateInfo->size;
2900 buffer->usage = pCreateInfo->usage;
2901 buffer->bo = NULL;
2902 buffer->offset = 0;
2903 buffer->flags = pCreateInfo->flags;
2904
2905 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2906 buffer->bo = device->ws->buffer_create(device->ws,
2907 align64(buffer->size, 4096),
2908 4096, 0, RADEON_FLAG_VIRTUAL);
2909 if (!buffer->bo) {
2910 vk_free2(&device->alloc, pAllocator, buffer);
2911 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2912 }
2913 }
2914
2915 *pBuffer = radv_buffer_to_handle(buffer);
2916
2917 return VK_SUCCESS;
2918 }
2919
2920 void radv_DestroyBuffer(
2921 VkDevice _device,
2922 VkBuffer _buffer,
2923 const VkAllocationCallbacks* pAllocator)
2924 {
2925 RADV_FROM_HANDLE(radv_device, device, _device);
2926 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2927
2928 if (!buffer)
2929 return;
2930
2931 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2932 device->ws->buffer_destroy(buffer->bo);
2933
2934 vk_free2(&device->alloc, pAllocator, buffer);
2935 }
2936
2937 static inline unsigned
2938 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2939 {
2940 if (stencil)
2941 return image->surface.u.legacy.stencil_tiling_index[level];
2942 else
2943 return image->surface.u.legacy.tiling_index[level];
2944 }
2945
2946 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2947 {
2948 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2949 }
2950
2951 static void
2952 radv_initialise_color_surface(struct radv_device *device,
2953 struct radv_color_buffer_info *cb,
2954 struct radv_image_view *iview)
2955 {
2956 const struct vk_format_description *desc;
2957 unsigned ntype, format, swap, endian;
2958 unsigned blend_clamp = 0, blend_bypass = 0;
2959 uint64_t va;
2960 const struct radeon_surf *surf = &iview->image->surface;
2961
2962 desc = vk_format_description(iview->vk_format);
2963
2964 memset(cb, 0, sizeof(*cb));
2965
2966 /* Intensity is implemented as Red, so treat it that way. */
2967 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2968
2969 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2970
2971 cb->cb_color_base = va >> 8;
2972
2973 if (device->physical_device->rad_info.chip_class >= GFX9) {
2974 struct gfx9_surf_meta_flags meta;
2975 if (iview->image->dcc_offset)
2976 meta = iview->image->surface.u.gfx9.dcc;
2977 else
2978 meta = iview->image->surface.u.gfx9.cmask;
2979
2980 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2981 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2982 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2983 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2984
2985 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2986 } else {
2987 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2988 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2989
2990 cb->cb_color_base += level_info->offset >> 8;
2991 if (level_info->mode == RADEON_SURF_MODE_2D)
2992 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2993
2994 pitch_tile_max = level_info->nblk_x / 8 - 1;
2995 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2996 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2997
2998 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2999 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3000 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3001
3002 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3003 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3004
3005 if (iview->image->fmask.size) {
3006 if (device->physical_device->rad_info.chip_class >= CIK)
3007 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3008 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3009 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3010 } else {
3011 /* This must be set for fast clear to work without FMASK. */
3012 if (device->physical_device->rad_info.chip_class >= CIK)
3013 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3014 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3015 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3016 }
3017 }
3018
3019 /* CMASK variables */
3020 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3021 va += iview->image->cmask.offset;
3022 cb->cb_color_cmask = va >> 8;
3023
3024 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3025 va += iview->image->dcc_offset;
3026 cb->cb_dcc_base = va >> 8;
3027 if (device->physical_device->rad_info.chip_class < GFX9)
3028 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3029
3030 uint32_t max_slice = radv_surface_layer_count(iview);
3031 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3032 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3033
3034 if (iview->image->info.samples > 1) {
3035 unsigned log_samples = util_logbase2(iview->image->info.samples);
3036
3037 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3038 S_028C74_NUM_FRAGMENTS(log_samples);
3039 }
3040
3041 if (iview->image->fmask.size) {
3042 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3043 cb->cb_color_fmask = va >> 8;
3044 if (device->physical_device->rad_info.chip_class < GFX9)
3045 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3046 } else {
3047 cb->cb_color_fmask = cb->cb_color_base;
3048 }
3049
3050 ntype = radv_translate_color_numformat(iview->vk_format,
3051 desc,
3052 vk_format_get_first_non_void_channel(iview->vk_format));
3053 format = radv_translate_colorformat(iview->vk_format);
3054 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3055 radv_finishme("Illegal color\n");
3056 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3057 endian = radv_colorformat_endian_swap(format);
3058
3059 /* blend clamp should be set for all NORM/SRGB types */
3060 if (ntype == V_028C70_NUMBER_UNORM ||
3061 ntype == V_028C70_NUMBER_SNORM ||
3062 ntype == V_028C70_NUMBER_SRGB)
3063 blend_clamp = 1;
3064
3065 /* set blend bypass according to docs if SINT/UINT or
3066 8/24 COLOR variants */
3067 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3068 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3069 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3070 blend_clamp = 0;
3071 blend_bypass = 1;
3072 }
3073 #if 0
3074 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3075 (format == V_028C70_COLOR_8 ||
3076 format == V_028C70_COLOR_8_8 ||
3077 format == V_028C70_COLOR_8_8_8_8))
3078 ->color_is_int8 = true;
3079 #endif
3080 cb->cb_color_info = S_028C70_FORMAT(format) |
3081 S_028C70_COMP_SWAP(swap) |
3082 S_028C70_BLEND_CLAMP(blend_clamp) |
3083 S_028C70_BLEND_BYPASS(blend_bypass) |
3084 S_028C70_SIMPLE_FLOAT(1) |
3085 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3086 ntype != V_028C70_NUMBER_SNORM &&
3087 ntype != V_028C70_NUMBER_SRGB &&
3088 format != V_028C70_COLOR_8_24 &&
3089 format != V_028C70_COLOR_24_8) |
3090 S_028C70_NUMBER_TYPE(ntype) |
3091 S_028C70_ENDIAN(endian);
3092 if (iview->image->info.samples > 1)
3093 if (iview->image->fmask.size)
3094 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3095
3096 if (iview->image->cmask.size &&
3097 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3098 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3099
3100 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3101 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3102
3103 if (device->physical_device->rad_info.chip_class >= VI) {
3104 unsigned max_uncompressed_block_size = 2;
3105 if (iview->image->info.samples > 1) {
3106 if (iview->image->surface.bpe == 1)
3107 max_uncompressed_block_size = 0;
3108 else if (iview->image->surface.bpe == 2)
3109 max_uncompressed_block_size = 1;
3110 }
3111
3112 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3113 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3114 }
3115
3116 /* This must be set for fast clear to work without FMASK. */
3117 if (!iview->image->fmask.size &&
3118 device->physical_device->rad_info.chip_class == SI) {
3119 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3120 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3121 }
3122
3123 if (device->physical_device->rad_info.chip_class >= GFX9) {
3124 uint32_t max_slice = radv_surface_layer_count(iview);
3125 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3126
3127 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3128 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3129 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3130 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
3131 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
3132 S_028C68_MAX_MIP(iview->image->info.levels);
3133
3134 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3135
3136 }
3137 }
3138
3139 static void
3140 radv_initialise_ds_surface(struct radv_device *device,
3141 struct radv_ds_buffer_info *ds,
3142 struct radv_image_view *iview)
3143 {
3144 unsigned level = iview->base_mip;
3145 unsigned format, stencil_format;
3146 uint64_t va, s_offs, z_offs;
3147 bool stencil_only = false;
3148 memset(ds, 0, sizeof(*ds));
3149 switch (iview->image->vk_format) {
3150 case VK_FORMAT_D24_UNORM_S8_UINT:
3151 case VK_FORMAT_X8_D24_UNORM_PACK32:
3152 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3153 ds->offset_scale = 2.0f;
3154 break;
3155 case VK_FORMAT_D16_UNORM:
3156 case VK_FORMAT_D16_UNORM_S8_UINT:
3157 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3158 ds->offset_scale = 4.0f;
3159 break;
3160 case VK_FORMAT_D32_SFLOAT:
3161 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3162 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3163 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3164 ds->offset_scale = 1.0f;
3165 break;
3166 case VK_FORMAT_S8_UINT:
3167 stencil_only = true;
3168 break;
3169 default:
3170 break;
3171 }
3172
3173 format = radv_translate_dbformat(iview->image->vk_format);
3174 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
3175 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3176
3177 uint32_t max_slice = radv_surface_layer_count(iview);
3178 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3179 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3180
3181 ds->db_htile_data_base = 0;
3182 ds->db_htile_surface = 0;
3183
3184 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3185 s_offs = z_offs = va;
3186
3187 if (device->physical_device->rad_info.chip_class >= GFX9) {
3188 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3189 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3190
3191 ds->db_z_info = S_028038_FORMAT(format) |
3192 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3193 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3194 S_028038_MAXMIP(iview->image->info.levels - 1);
3195 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3196 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3197
3198 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3199 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3200 ds->db_depth_view |= S_028008_MIPID(level);
3201
3202 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3203 S_02801C_Y_MAX(iview->image->info.height - 1);
3204
3205 /* Only use HTILE for the first level. */
3206 if (iview->image->surface.htile_size && !level) {
3207 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3208
3209 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3210 /* Use all of the htile_buffer for depth if there's no stencil. */
3211 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3212 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3213 iview->image->htile_offset;
3214 ds->db_htile_data_base = va >> 8;
3215 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3216 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3217 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3218 }
3219 } else {
3220 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3221
3222 if (stencil_only)
3223 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3224
3225 z_offs += iview->image->surface.u.legacy.level[level].offset;
3226 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3227
3228 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3229 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3230 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3231
3232 if (iview->image->info.samples > 1)
3233 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3234
3235 if (device->physical_device->rad_info.chip_class >= CIK) {
3236 struct radeon_info *info = &device->physical_device->rad_info;
3237 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3238 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3239 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3240 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3241 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3242 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3243
3244 if (stencil_only)
3245 tile_mode = stencil_tile_mode;
3246
3247 ds->db_depth_info |=
3248 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3249 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3250 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3251 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3252 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3253 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3254 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3255 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3256 } else {
3257 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3258 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3259 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3260 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3261 if (stencil_only)
3262 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3263 }
3264
3265 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3266 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3267 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3268
3269 if (iview->image->surface.htile_size && !level) {
3270 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3271
3272 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3273 /* Use all of the htile_buffer for depth if there's no stencil. */
3274 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3275
3276 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3277 iview->image->htile_offset;
3278 ds->db_htile_data_base = va >> 8;
3279 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3280 }
3281 }
3282
3283 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3284 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3285 }
3286
3287 VkResult radv_CreateFramebuffer(
3288 VkDevice _device,
3289 const VkFramebufferCreateInfo* pCreateInfo,
3290 const VkAllocationCallbacks* pAllocator,
3291 VkFramebuffer* pFramebuffer)
3292 {
3293 RADV_FROM_HANDLE(radv_device, device, _device);
3294 struct radv_framebuffer *framebuffer;
3295
3296 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3297
3298 size_t size = sizeof(*framebuffer) +
3299 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3300 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3301 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3302 if (framebuffer == NULL)
3303 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3304
3305 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3306 framebuffer->width = pCreateInfo->width;
3307 framebuffer->height = pCreateInfo->height;
3308 framebuffer->layers = pCreateInfo->layers;
3309 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3310 VkImageView _iview = pCreateInfo->pAttachments[i];
3311 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3312 framebuffer->attachments[i].attachment = iview;
3313 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3314 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3315 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3316 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3317 }
3318 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3319 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3320 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3321 }
3322
3323 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3324 return VK_SUCCESS;
3325 }
3326
3327 void radv_DestroyFramebuffer(
3328 VkDevice _device,
3329 VkFramebuffer _fb,
3330 const VkAllocationCallbacks* pAllocator)
3331 {
3332 RADV_FROM_HANDLE(radv_device, device, _device);
3333 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3334
3335 if (!fb)
3336 return;
3337 vk_free2(&device->alloc, pAllocator, fb);
3338 }
3339
3340 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3341 {
3342 switch (address_mode) {
3343 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3344 return V_008F30_SQ_TEX_WRAP;
3345 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3346 return V_008F30_SQ_TEX_MIRROR;
3347 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3348 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3349 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3350 return V_008F30_SQ_TEX_CLAMP_BORDER;
3351 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3352 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3353 default:
3354 unreachable("illegal tex wrap mode");
3355 break;
3356 }
3357 }
3358
3359 static unsigned
3360 radv_tex_compare(VkCompareOp op)
3361 {
3362 switch (op) {
3363 case VK_COMPARE_OP_NEVER:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3365 case VK_COMPARE_OP_LESS:
3366 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3367 case VK_COMPARE_OP_EQUAL:
3368 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3369 case VK_COMPARE_OP_LESS_OR_EQUAL:
3370 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3371 case VK_COMPARE_OP_GREATER:
3372 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3373 case VK_COMPARE_OP_NOT_EQUAL:
3374 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3375 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3376 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3377 case VK_COMPARE_OP_ALWAYS:
3378 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3379 default:
3380 unreachable("illegal compare mode");
3381 break;
3382 }
3383 }
3384
3385 static unsigned
3386 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3387 {
3388 switch (filter) {
3389 case VK_FILTER_NEAREST:
3390 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3391 V_008F38_SQ_TEX_XY_FILTER_POINT);
3392 case VK_FILTER_LINEAR:
3393 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3394 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3395 case VK_FILTER_CUBIC_IMG:
3396 default:
3397 fprintf(stderr, "illegal texture filter");
3398 return 0;
3399 }
3400 }
3401
3402 static unsigned
3403 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3404 {
3405 switch (mode) {
3406 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3407 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3408 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3409 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3410 default:
3411 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3412 }
3413 }
3414
3415 static unsigned
3416 radv_tex_bordercolor(VkBorderColor bcolor)
3417 {
3418 switch (bcolor) {
3419 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3420 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3421 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3422 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3423 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3424 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3425 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3426 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3427 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3428 default:
3429 break;
3430 }
3431 return 0;
3432 }
3433
3434 static unsigned
3435 radv_tex_aniso_filter(unsigned filter)
3436 {
3437 if (filter < 2)
3438 return 0;
3439 if (filter < 4)
3440 return 1;
3441 if (filter < 8)
3442 return 2;
3443 if (filter < 16)
3444 return 3;
3445 return 4;
3446 }
3447
3448 static void
3449 radv_init_sampler(struct radv_device *device,
3450 struct radv_sampler *sampler,
3451 const VkSamplerCreateInfo *pCreateInfo)
3452 {
3453 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3454 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3455 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3456 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3457
3458 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3459 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3460 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3461 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3462 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3463 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3464 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3465 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3466 S_008F30_DISABLE_CUBE_WRAP(0) |
3467 S_008F30_COMPAT_MODE(is_vi));
3468 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3469 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3470 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3471 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3472 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3473 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3474 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3475 S_008F38_MIP_POINT_PRECLAMP(0) |
3476 S_008F38_DISABLE_LSB_CEIL(1) |
3477 S_008F38_FILTER_PREC_FIX(1) |
3478 S_008F38_ANISO_OVERRIDE(is_vi));
3479 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3480 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3481 }
3482
3483 VkResult radv_CreateSampler(
3484 VkDevice _device,
3485 const VkSamplerCreateInfo* pCreateInfo,
3486 const VkAllocationCallbacks* pAllocator,
3487 VkSampler* pSampler)
3488 {
3489 RADV_FROM_HANDLE(radv_device, device, _device);
3490 struct radv_sampler *sampler;
3491
3492 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3493
3494 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3495 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3496 if (!sampler)
3497 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3498
3499 radv_init_sampler(device, sampler, pCreateInfo);
3500 *pSampler = radv_sampler_to_handle(sampler);
3501
3502 return VK_SUCCESS;
3503 }
3504
3505 void radv_DestroySampler(
3506 VkDevice _device,
3507 VkSampler _sampler,
3508 const VkAllocationCallbacks* pAllocator)
3509 {
3510 RADV_FROM_HANDLE(radv_device, device, _device);
3511 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3512
3513 if (!sampler)
3514 return;
3515 vk_free2(&device->alloc, pAllocator, sampler);
3516 }
3517
3518 /* vk_icd.h does not declare this function, so we declare it here to
3519 * suppress Wmissing-prototypes.
3520 */
3521 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3522 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3523
3524 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3525 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3526 {
3527 /* For the full details on loader interface versioning, see
3528 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3529 * What follows is a condensed summary, to help you navigate the large and
3530 * confusing official doc.
3531 *
3532 * - Loader interface v0 is incompatible with later versions. We don't
3533 * support it.
3534 *
3535 * - In loader interface v1:
3536 * - The first ICD entrypoint called by the loader is
3537 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3538 * entrypoint.
3539 * - The ICD must statically expose no other Vulkan symbol unless it is
3540 * linked with -Bsymbolic.
3541 * - Each dispatchable Vulkan handle created by the ICD must be
3542 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3543 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3544 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3545 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3546 * such loader-managed surfaces.
3547 *
3548 * - Loader interface v2 differs from v1 in:
3549 * - The first ICD entrypoint called by the loader is
3550 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3551 * statically expose this entrypoint.
3552 *
3553 * - Loader interface v3 differs from v2 in:
3554 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3555 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3556 * because the loader no longer does so.
3557 */
3558 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3559 return VK_SUCCESS;
3560 }
3561
3562 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3563 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3564 int *pFD)
3565 {
3566 RADV_FROM_HANDLE(radv_device, device, _device);
3567 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3568
3569 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3570
3571 /* We support only one handle type. */
3572 assert(pGetFdInfo->handleType ==
3573 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3574
3575 bool ret = radv_get_memory_fd(device, memory, pFD);
3576 if (ret == false)
3577 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3578 return VK_SUCCESS;
3579 }
3580
3581 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3582 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3583 int fd,
3584 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3585 {
3586 /* The valid usage section for this function says:
3587 *
3588 * "handleType must not be one of the handle types defined as opaque."
3589 *
3590 * Since we only handle opaque handles for now, there are no FD properties.
3591 */
3592 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3593 }
3594
3595 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3596 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3597 {
3598 RADV_FROM_HANDLE(radv_device, device, _device);
3599 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3600 uint32_t syncobj_handle = 0;
3601 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3602
3603 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3604 if (ret != 0)
3605 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3606
3607 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3608 sem->temp_syncobj = syncobj_handle;
3609 } else {
3610 sem->syncobj = syncobj_handle;
3611 }
3612 close(pImportSemaphoreFdInfo->fd);
3613 return VK_SUCCESS;
3614 }
3615
3616 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3617 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3618 int *pFd)
3619 {
3620 RADV_FROM_HANDLE(radv_device, device, _device);
3621 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3622 int ret;
3623 uint32_t syncobj_handle;
3624
3625 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3626 if (sem->temp_syncobj)
3627 syncobj_handle = sem->temp_syncobj;
3628 else
3629 syncobj_handle = sem->syncobj;
3630 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3631 if (ret)
3632 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3633 return VK_SUCCESS;
3634 }
3635
3636 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3637 VkPhysicalDevice physicalDevice,
3638 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3639 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3640 {
3641 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3642 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3643 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3644 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3645 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3646 } else {
3647 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3648 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3649 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3650 }
3651 }