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anv,radv: disable StorageImageWriteWithoutFormat for now
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 VkResult radv_CreateInstance(
222 const VkInstanceCreateInfo* pCreateInfo,
223 const VkAllocationCallbacks* pAllocator,
224 VkInstance* pInstance)
225 {
226 struct radv_instance *instance;
227
228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
229
230 uint32_t client_version;
231 if (pCreateInfo->pApplicationInfo &&
232 pCreateInfo->pApplicationInfo->apiVersion != 0) {
233 client_version = pCreateInfo->pApplicationInfo->apiVersion;
234 } else {
235 client_version = VK_MAKE_VERSION(1, 0, 0);
236 }
237
238 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
239 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
240 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
241 "Client requested version %d.%d.%d",
242 VK_VERSION_MAJOR(client_version),
243 VK_VERSION_MINOR(client_version),
244 VK_VERSION_PATCH(client_version));
245 }
246
247 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
248 bool found = false;
249 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
250 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
251 global_extensions[j].extensionName) == 0) {
252 found = true;
253 break;
254 }
255 }
256 if (!found)
257 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
258 }
259
260 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
262 if (!instance)
263 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266
267 if (pAllocator)
268 instance->alloc = *pAllocator;
269 else
270 instance->alloc = default_alloc;
271
272 instance->apiVersion = client_version;
273 instance->physicalDeviceCount = -1;
274
275 _mesa_locale_init();
276
277 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
278
279 *pInstance = radv_instance_to_handle(instance);
280
281 return VK_SUCCESS;
282 }
283
284 void radv_DestroyInstance(
285 VkInstance _instance,
286 const VkAllocationCallbacks* pAllocator)
287 {
288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
289
290 if (instance->physicalDeviceCount > 0) {
291 /* We support at most one physical device. */
292 assert(instance->physicalDeviceCount == 1);
293 radv_physical_device_finish(&instance->physicalDevice);
294 }
295
296 VG(VALGRIND_DESTROY_MEMPOOL(instance));
297
298 _mesa_locale_fini();
299
300 vk_free(&instance->alloc, instance);
301 }
302
303 VkResult radv_EnumeratePhysicalDevices(
304 VkInstance _instance,
305 uint32_t* pPhysicalDeviceCount,
306 VkPhysicalDevice* pPhysicalDevices)
307 {
308 RADV_FROM_HANDLE(radv_instance, instance, _instance);
309 VkResult result;
310
311 if (instance->physicalDeviceCount < 0) {
312 char path[20];
313 for (unsigned i = 0; i < 8; i++) {
314 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
315 result = radv_physical_device_init(&instance->physicalDevice,
316 instance, path);
317 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
318 break;
319 }
320
321 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
322 instance->physicalDeviceCount = 0;
323 } else if (result == VK_SUCCESS) {
324 instance->physicalDeviceCount = 1;
325 } else {
326 return result;
327 }
328 }
329
330 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
331 * otherwise it's an inout parameter.
332 *
333 * The Vulkan spec (git aaed022) says:
334 *
335 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
336 * that is initialized with the number of devices the application is
337 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
338 * an array of at least this many VkPhysicalDevice handles [...].
339 *
340 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
341 * overwrites the contents of the variable pointed to by
342 * pPhysicalDeviceCount with the number of physical devices in in the
343 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
344 * pPhysicalDeviceCount with the number of physical handles written to
345 * pPhysicalDevices.
346 */
347 if (!pPhysicalDevices) {
348 *pPhysicalDeviceCount = instance->physicalDeviceCount;
349 } else if (*pPhysicalDeviceCount >= 1) {
350 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
351 *pPhysicalDeviceCount = 1;
352 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
353 return VK_INCOMPLETE;
354 } else {
355 *pPhysicalDeviceCount = 0;
356 }
357
358 return VK_SUCCESS;
359 }
360
361 void radv_GetPhysicalDeviceFeatures(
362 VkPhysicalDevice physicalDevice,
363 VkPhysicalDeviceFeatures* pFeatures)
364 {
365 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
366
367 memset(pFeatures, 0, sizeof(*pFeatures));
368
369 *pFeatures = (VkPhysicalDeviceFeatures) {
370 .robustBufferAccess = true,
371 .fullDrawIndexUint32 = true,
372 .imageCubeArray = true,
373 .independentBlend = true,
374 .geometryShader = false,
375 .tessellationShader = false,
376 .sampleRateShading = false,
377 .dualSrcBlend = true,
378 .logicOp = true,
379 .multiDrawIndirect = true,
380 .drawIndirectFirstInstance = true,
381 .depthClamp = true,
382 .depthBiasClamp = true,
383 .fillModeNonSolid = true,
384 .depthBounds = true,
385 .wideLines = true,
386 .largePoints = true,
387 .alphaToOne = true,
388 .multiViewport = false,
389 .samplerAnisotropy = true,
390 .textureCompressionETC2 = false,
391 .textureCompressionASTC_LDR = false,
392 .textureCompressionBC = true,
393 .occlusionQueryPrecise = true,
394 .pipelineStatisticsQuery = false,
395 .vertexPipelineStoresAndAtomics = true,
396 .fragmentStoresAndAtomics = true,
397 .shaderTessellationAndGeometryPointSize = true,
398 .shaderImageGatherExtended = true,
399 .shaderStorageImageExtendedFormats = true,
400 .shaderStorageImageMultisample = false,
401 .shaderUniformBufferArrayDynamicIndexing = true,
402 .shaderSampledImageArrayDynamicIndexing = true,
403 .shaderStorageBufferArrayDynamicIndexing = true,
404 .shaderStorageImageArrayDynamicIndexing = true,
405 .shaderStorageImageReadWithoutFormat = false,
406 .shaderStorageImageWriteWithoutFormat = false,
407 .shaderClipDistance = true,
408 .shaderCullDistance = true,
409 .shaderFloat64 = false,
410 .shaderInt64 = false,
411 .shaderInt16 = false,
412 .alphaToOne = true,
413 .variableMultisampleRate = false,
414 .inheritedQueries = false,
415 };
416 }
417
418 void radv_GetPhysicalDeviceProperties(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceProperties* pProperties)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 VkSampleCountFlags sample_counts = 0xf;
424 VkPhysicalDeviceLimits limits = {
425 .maxImageDimension1D = (1 << 14),
426 .maxImageDimension2D = (1 << 14),
427 .maxImageDimension3D = (1 << 11),
428 .maxImageDimensionCube = (1 << 14),
429 .maxImageArrayLayers = (1 << 11),
430 .maxTexelBufferElements = 128 * 1024 * 1024,
431 .maxUniformBufferRange = UINT32_MAX,
432 .maxStorageBufferRange = UINT32_MAX,
433 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
434 .maxMemoryAllocationCount = UINT32_MAX,
435 .maxSamplerAllocationCount = 64 * 1024,
436 .bufferImageGranularity = 64, /* A cache line */
437 .sparseAddressSpaceSize = 0,
438 .maxBoundDescriptorSets = MAX_SETS,
439 .maxPerStageDescriptorSamplers = 64,
440 .maxPerStageDescriptorUniformBuffers = 64,
441 .maxPerStageDescriptorStorageBuffers = 64,
442 .maxPerStageDescriptorSampledImages = 64,
443 .maxPerStageDescriptorStorageImages = 64,
444 .maxPerStageDescriptorInputAttachments = 64,
445 .maxPerStageResources = 128,
446 .maxDescriptorSetSamplers = 256,
447 .maxDescriptorSetUniformBuffers = 256,
448 .maxDescriptorSetUniformBuffersDynamic = 256,
449 .maxDescriptorSetStorageBuffers = 256,
450 .maxDescriptorSetStorageBuffersDynamic = 256,
451 .maxDescriptorSetSampledImages = 256,
452 .maxDescriptorSetStorageImages = 256,
453 .maxDescriptorSetInputAttachments = 256,
454 .maxVertexInputAttributes = 32,
455 .maxVertexInputBindings = 32,
456 .maxVertexInputAttributeOffset = 2047,
457 .maxVertexInputBindingStride = 2048,
458 .maxVertexOutputComponents = 128,
459 .maxTessellationGenerationLevel = 0,
460 .maxTessellationPatchSize = 0,
461 .maxTessellationControlPerVertexInputComponents = 0,
462 .maxTessellationControlPerVertexOutputComponents = 0,
463 .maxTessellationControlPerPatchOutputComponents = 0,
464 .maxTessellationControlTotalOutputComponents = 0,
465 .maxTessellationEvaluationInputComponents = 0,
466 .maxTessellationEvaluationOutputComponents = 0,
467 .maxGeometryShaderInvocations = 32,
468 .maxGeometryInputComponents = 64,
469 .maxGeometryOutputComponents = 128,
470 .maxGeometryOutputVertices = 256,
471 .maxGeometryTotalOutputComponents = 1024,
472 .maxFragmentInputComponents = 128,
473 .maxFragmentOutputAttachments = 8,
474 .maxFragmentDualSrcAttachments = 1,
475 .maxFragmentCombinedOutputResources = 8,
476 .maxComputeSharedMemorySize = 32768,
477 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
478 .maxComputeWorkGroupInvocations = 2048,
479 .maxComputeWorkGroupSize = {
480 2048,
481 2048,
482 2048
483 },
484 .subPixelPrecisionBits = 4 /* FIXME */,
485 .subTexelPrecisionBits = 4 /* FIXME */,
486 .mipmapPrecisionBits = 4 /* FIXME */,
487 .maxDrawIndexedIndexValue = UINT32_MAX,
488 .maxDrawIndirectCount = UINT32_MAX,
489 .maxSamplerLodBias = 16,
490 .maxSamplerAnisotropy = 16,
491 .maxViewports = MAX_VIEWPORTS,
492 .maxViewportDimensions = { (1 << 14), (1 << 14) },
493 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
494 .viewportSubPixelBits = 13, /* We take a float? */
495 .minMemoryMapAlignment = 4096, /* A page */
496 .minTexelBufferOffsetAlignment = 1,
497 .minUniformBufferOffsetAlignment = 4,
498 .minStorageBufferOffsetAlignment = 4,
499 .minTexelOffset = -32,
500 .maxTexelOffset = 31,
501 .minTexelGatherOffset = -32,
502 .maxTexelGatherOffset = 31,
503 .minInterpolationOffset = -2,
504 .maxInterpolationOffset = 2,
505 .subPixelInterpolationOffsetBits = 8,
506 .maxFramebufferWidth = (1 << 14),
507 .maxFramebufferHeight = (1 << 14),
508 .maxFramebufferLayers = (1 << 10),
509 .framebufferColorSampleCounts = sample_counts,
510 .framebufferDepthSampleCounts = sample_counts,
511 .framebufferStencilSampleCounts = sample_counts,
512 .framebufferNoAttachmentsSampleCounts = sample_counts,
513 .maxColorAttachments = MAX_RTS,
514 .sampledImageColorSampleCounts = sample_counts,
515 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .sampledImageDepthSampleCounts = sample_counts,
517 .sampledImageStencilSampleCounts = sample_counts,
518 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
519 .maxSampleMaskWords = 1,
520 .timestampComputeAndGraphics = false,
521 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
522 .maxClipDistances = 8,
523 .maxCullDistances = 8,
524 .maxCombinedClipAndCullDistances = 8,
525 .discreteQueuePriorities = 1,
526 .pointSizeRange = { 0.125, 255.875 },
527 .lineWidthRange = { 0.0, 7.9921875 },
528 .pointSizeGranularity = (1.0 / 8.0),
529 .lineWidthGranularity = (1.0 / 128.0),
530 .strictLines = false, /* FINISHME */
531 .standardSampleLocations = true,
532 .optimalBufferCopyOffsetAlignment = 128,
533 .optimalBufferCopyRowPitchAlignment = 128,
534 .nonCoherentAtomSize = 64,
535 };
536
537 *pProperties = (VkPhysicalDeviceProperties) {
538 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
539 .driverVersion = 1,
540 .vendorID = 0x1002,
541 .deviceID = pdevice->rad_info.pci_id,
542 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
543 .limits = limits,
544 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
545 };
546
547 strcpy(pProperties->deviceName, pdevice->name);
548 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
549 }
550
551 void radv_GetPhysicalDeviceQueueFamilyProperties(
552 VkPhysicalDevice physicalDevice,
553 uint32_t* pCount,
554 VkQueueFamilyProperties* pQueueFamilyProperties)
555 {
556 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
557 int num_queue_families = 1;
558 bool all_queues = env_var_as_boolean("RADV_SHOW_QUEUES", true);
559 int idx;
560 if (all_queues && pdevice->rad_info.chip_class >= CIK) {
561 if (pdevice->rad_info.compute_rings > 0)
562 num_queue_families++;
563 }
564
565 if (pQueueFamilyProperties == NULL) {
566 *pCount = num_queue_families;
567 return;
568 }
569
570 if (!*pCount)
571 return;
572
573 idx = 0;
574 if (*pCount >= 1) {
575 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
576 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
577 VK_QUEUE_COMPUTE_BIT |
578 VK_QUEUE_TRANSFER_BIT,
579 .queueCount = 1,
580 .timestampValidBits = 64,
581 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
582 };
583 idx++;
584 }
585
586 if (!all_queues) {
587 *pCount = idx;
588 return;
589 }
590
591 if (pdevice->rad_info.compute_rings > 0 && pdevice->rad_info.chip_class >= CIK) {
592 if (*pCount > idx) {
593 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
594 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
595 .queueCount = pdevice->rad_info.compute_rings,
596 .timestampValidBits = 64,
597 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
598 };
599 idx++;
600 }
601 }
602 *pCount = idx;
603 }
604
605 void radv_GetPhysicalDeviceMemoryProperties(
606 VkPhysicalDevice physicalDevice,
607 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
608 {
609 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
610
611 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
612
613 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
614 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
615 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
616 .heapIndex = RADV_MEM_HEAP_VRAM,
617 };
618 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
619 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
620 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
621 .heapIndex = RADV_MEM_HEAP_GTT,
622 };
623 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
624 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
625 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
626 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
627 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
628 };
629 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
630 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
631 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
632 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
633 .heapIndex = RADV_MEM_HEAP_GTT,
634 };
635
636 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
637
638 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
639 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
640 .size = physical_device->rad_info.vram_size -
641 physical_device->rad_info.visible_vram_size,
642 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
643 };
644 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
645 .size = physical_device->rad_info.visible_vram_size,
646 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
647 };
648 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
649 .size = physical_device->rad_info.gart_size,
650 .flags = 0,
651 };
652 }
653
654 static void
655 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
656 int queue_family_index, int idx)
657 {
658 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
659 queue->device = device;
660 queue->queue_family_index = queue_family_index;
661 queue->queue_idx = idx;
662 }
663
664 static void
665 radv_queue_finish(struct radv_queue *queue)
666 {
667 }
668
669 VkResult radv_CreateDevice(
670 VkPhysicalDevice physicalDevice,
671 const VkDeviceCreateInfo* pCreateInfo,
672 const VkAllocationCallbacks* pAllocator,
673 VkDevice* pDevice)
674 {
675 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
676 VkResult result;
677 struct radv_device *device;
678
679 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
680 bool found = false;
681 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
682 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
683 device_extensions[j].extensionName) == 0) {
684 found = true;
685 break;
686 }
687 }
688 if (!found)
689 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
690 }
691
692 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
693 sizeof(*device), 8,
694 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
695 if (!device)
696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
697
698 memset(device, 0, sizeof(*device));
699
700 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
701 device->instance = physical_device->instance;
702 device->shader_stats_dump = false;
703
704 device->ws = physical_device->ws;
705 if (pAllocator)
706 device->alloc = *pAllocator;
707 else
708 device->alloc = physical_device->instance->alloc;
709
710 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
711 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
712 uint32_t qfi = queue_create->queueFamilyIndex;
713
714 device->queues[qfi] = vk_alloc(&device->alloc,
715 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
716 if (!device->queues[qfi]) {
717 result = VK_ERROR_OUT_OF_HOST_MEMORY;
718 goto fail;
719 }
720
721 device->queue_count[qfi] = queue_create->queueCount;
722
723 for (unsigned q = 0; q < queue_create->queueCount; q++)
724 radv_queue_init(device, &device->queues[qfi][q], qfi, q);
725 }
726
727 device->hw_ctx = device->ws->ctx_create(device->ws);
728 if (!device->hw_ctx) {
729 result = VK_ERROR_OUT_OF_HOST_MEMORY;
730 goto fail;
731 }
732
733 result = radv_device_init_meta(device);
734 if (result != VK_SUCCESS) {
735 device->ws->ctx_destroy(device->hw_ctx);
736 goto fail;
737 }
738 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
739 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
740 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
741
742 if (device->allow_fast_clears && device->allow_dcc)
743 radv_finishme("DCC fast clears have not been tested\n");
744
745 radv_device_init_msaa(device);
746
747 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
748 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
749 switch (family) {
750 case RADV_QUEUE_GENERAL:
751 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
752 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
753 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
754 break;
755 case RADV_QUEUE_COMPUTE:
756 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
757 radeon_emit(device->empty_cs[family], 0);
758 break;
759 }
760 device->ws->cs_finalize(device->empty_cs[family]);
761 }
762
763 *pDevice = radv_device_to_handle(device);
764 return VK_SUCCESS;
765
766 fail:
767 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
768 for (unsigned q = 0; q < device->queue_count[i]; q++)
769 radv_queue_finish(&device->queues[i][q]);
770 if (device->queue_count[i])
771 vk_free(&device->alloc, device->queues[i]);
772 }
773 vk_free(&device->alloc, device);
774 return result;
775 }
776
777 void radv_DestroyDevice(
778 VkDevice _device,
779 const VkAllocationCallbacks* pAllocator)
780 {
781 RADV_FROM_HANDLE(radv_device, device, _device);
782
783 device->ws->ctx_destroy(device->hw_ctx);
784 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
785 for (unsigned q = 0; q < device->queue_count[i]; q++)
786 radv_queue_finish(&device->queues[i][q]);
787 if (device->queue_count[i])
788 vk_free(&device->alloc, device->queues[i]);
789 }
790 radv_device_finish_meta(device);
791
792 vk_free(&device->alloc, device);
793 }
794
795 VkResult radv_EnumerateInstanceExtensionProperties(
796 const char* pLayerName,
797 uint32_t* pPropertyCount,
798 VkExtensionProperties* pProperties)
799 {
800 if (pProperties == NULL) {
801 *pPropertyCount = ARRAY_SIZE(global_extensions);
802 return VK_SUCCESS;
803 }
804
805 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
806 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
807
808 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
809 return VK_INCOMPLETE;
810
811 return VK_SUCCESS;
812 }
813
814 VkResult radv_EnumerateDeviceExtensionProperties(
815 VkPhysicalDevice physicalDevice,
816 const char* pLayerName,
817 uint32_t* pPropertyCount,
818 VkExtensionProperties* pProperties)
819 {
820 if (pProperties == NULL) {
821 *pPropertyCount = ARRAY_SIZE(device_extensions);
822 return VK_SUCCESS;
823 }
824
825 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
826 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
827
828 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
829 return VK_INCOMPLETE;
830
831 return VK_SUCCESS;
832 }
833
834 VkResult radv_EnumerateInstanceLayerProperties(
835 uint32_t* pPropertyCount,
836 VkLayerProperties* pProperties)
837 {
838 if (pProperties == NULL) {
839 *pPropertyCount = 0;
840 return VK_SUCCESS;
841 }
842
843 /* None supported at this time */
844 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
845 }
846
847 VkResult radv_EnumerateDeviceLayerProperties(
848 VkPhysicalDevice physicalDevice,
849 uint32_t* pPropertyCount,
850 VkLayerProperties* pProperties)
851 {
852 if (pProperties == NULL) {
853 *pPropertyCount = 0;
854 return VK_SUCCESS;
855 }
856
857 /* None supported at this time */
858 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
859 }
860
861 void radv_GetDeviceQueue(
862 VkDevice _device,
863 uint32_t queueFamilyIndex,
864 uint32_t queueIndex,
865 VkQueue* pQueue)
866 {
867 RADV_FROM_HANDLE(radv_device, device, _device);
868
869 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
870 }
871
872 VkResult radv_QueueSubmit(
873 VkQueue _queue,
874 uint32_t submitCount,
875 const VkSubmitInfo* pSubmits,
876 VkFence _fence)
877 {
878 RADV_FROM_HANDLE(radv_queue, queue, _queue);
879 RADV_FROM_HANDLE(radv_fence, fence, _fence);
880 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
881 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
882 int ret;
883
884 for (uint32_t i = 0; i < submitCount; i++) {
885 struct radeon_winsys_cs **cs_array;
886 bool can_patch = true;
887
888 if (!pSubmits[i].commandBufferCount)
889 continue;
890
891 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
892 pSubmits[i].commandBufferCount);
893
894 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
896 pSubmits[i].pCommandBuffers[j]);
897 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
898
899 cs_array[j] = cmd_buffer->cs;
900 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
901 can_patch = false;
902 }
903 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array,
904 pSubmits[i].commandBufferCount,
905 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
906 pSubmits[i].waitSemaphoreCount,
907 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
908 pSubmits[i].signalSemaphoreCount,
909 can_patch, base_fence);
910 if (ret)
911 radv_loge("failed to submit CS %d\n", i);
912 free(cs_array);
913 }
914
915 if (fence) {
916 if (!submitCount)
917 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
918 &queue->device->empty_cs[queue->queue_family_index],
919 1, NULL, 0, NULL, 0, false, base_fence);
920
921 fence->submitted = true;
922 }
923
924 return VK_SUCCESS;
925 }
926
927 VkResult radv_QueueWaitIdle(
928 VkQueue _queue)
929 {
930 RADV_FROM_HANDLE(radv_queue, queue, _queue);
931
932 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
933 radv_queue_family_to_ring(queue->queue_family_index),
934 queue->queue_idx);
935 return VK_SUCCESS;
936 }
937
938 VkResult radv_DeviceWaitIdle(
939 VkDevice _device)
940 {
941 RADV_FROM_HANDLE(radv_device, device, _device);
942
943 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
944 for (unsigned q = 0; q < device->queue_count[i]; q++) {
945 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
946 }
947 }
948 return VK_SUCCESS;
949 }
950
951 PFN_vkVoidFunction radv_GetInstanceProcAddr(
952 VkInstance instance,
953 const char* pName)
954 {
955 return radv_lookup_entrypoint(pName);
956 }
957
958 /* The loader wants us to expose a second GetInstanceProcAddr function
959 * to work around certain LD_PRELOAD issues seen in apps.
960 */
961 PUBLIC
962 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
963 VkInstance instance,
964 const char* pName);
965
966 PUBLIC
967 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
968 VkInstance instance,
969 const char* pName)
970 {
971 return radv_GetInstanceProcAddr(instance, pName);
972 }
973
974 PFN_vkVoidFunction radv_GetDeviceProcAddr(
975 VkDevice device,
976 const char* pName)
977 {
978 return radv_lookup_entrypoint(pName);
979 }
980
981 VkResult radv_AllocateMemory(
982 VkDevice _device,
983 const VkMemoryAllocateInfo* pAllocateInfo,
984 const VkAllocationCallbacks* pAllocator,
985 VkDeviceMemory* pMem)
986 {
987 RADV_FROM_HANDLE(radv_device, device, _device);
988 struct radv_device_memory *mem;
989 VkResult result;
990 enum radeon_bo_domain domain;
991 uint32_t flags = 0;
992 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
993
994 if (pAllocateInfo->allocationSize == 0) {
995 /* Apparently, this is allowed */
996 *pMem = VK_NULL_HANDLE;
997 return VK_SUCCESS;
998 }
999
1000 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1001 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1002 if (mem == NULL)
1003 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1004
1005 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1006 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1007 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1008 domain = RADEON_DOMAIN_GTT;
1009 else
1010 domain = RADEON_DOMAIN_VRAM;
1011
1012 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1013 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1014 else
1015 flags |= RADEON_FLAG_CPU_ACCESS;
1016
1017 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1018 flags |= RADEON_FLAG_GTT_WC;
1019
1020 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1021 domain, flags);
1022
1023 if (!mem->bo) {
1024 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1025 goto fail;
1026 }
1027 mem->type_index = pAllocateInfo->memoryTypeIndex;
1028
1029 *pMem = radv_device_memory_to_handle(mem);
1030
1031 return VK_SUCCESS;
1032
1033 fail:
1034 vk_free2(&device->alloc, pAllocator, mem);
1035
1036 return result;
1037 }
1038
1039 void radv_FreeMemory(
1040 VkDevice _device,
1041 VkDeviceMemory _mem,
1042 const VkAllocationCallbacks* pAllocator)
1043 {
1044 RADV_FROM_HANDLE(radv_device, device, _device);
1045 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1046
1047 if (mem == NULL)
1048 return;
1049
1050 device->ws->buffer_destroy(mem->bo);
1051 mem->bo = NULL;
1052
1053 vk_free2(&device->alloc, pAllocator, mem);
1054 }
1055
1056 VkResult radv_MapMemory(
1057 VkDevice _device,
1058 VkDeviceMemory _memory,
1059 VkDeviceSize offset,
1060 VkDeviceSize size,
1061 VkMemoryMapFlags flags,
1062 void** ppData)
1063 {
1064 RADV_FROM_HANDLE(radv_device, device, _device);
1065 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1066
1067 if (mem == NULL) {
1068 *ppData = NULL;
1069 return VK_SUCCESS;
1070 }
1071
1072 *ppData = device->ws->buffer_map(mem->bo);
1073 if (*ppData) {
1074 *ppData += offset;
1075 return VK_SUCCESS;
1076 }
1077
1078 return VK_ERROR_MEMORY_MAP_FAILED;
1079 }
1080
1081 void radv_UnmapMemory(
1082 VkDevice _device,
1083 VkDeviceMemory _memory)
1084 {
1085 RADV_FROM_HANDLE(radv_device, device, _device);
1086 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1087
1088 if (mem == NULL)
1089 return;
1090
1091 device->ws->buffer_unmap(mem->bo);
1092 }
1093
1094 VkResult radv_FlushMappedMemoryRanges(
1095 VkDevice _device,
1096 uint32_t memoryRangeCount,
1097 const VkMappedMemoryRange* pMemoryRanges)
1098 {
1099 return VK_SUCCESS;
1100 }
1101
1102 VkResult radv_InvalidateMappedMemoryRanges(
1103 VkDevice _device,
1104 uint32_t memoryRangeCount,
1105 const VkMappedMemoryRange* pMemoryRanges)
1106 {
1107 return VK_SUCCESS;
1108 }
1109
1110 void radv_GetBufferMemoryRequirements(
1111 VkDevice device,
1112 VkBuffer _buffer,
1113 VkMemoryRequirements* pMemoryRequirements)
1114 {
1115 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1116
1117 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1118
1119 pMemoryRequirements->size = buffer->size;
1120 pMemoryRequirements->alignment = 16;
1121 }
1122
1123 void radv_GetImageMemoryRequirements(
1124 VkDevice device,
1125 VkImage _image,
1126 VkMemoryRequirements* pMemoryRequirements)
1127 {
1128 RADV_FROM_HANDLE(radv_image, image, _image);
1129
1130 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1131
1132 pMemoryRequirements->size = image->size;
1133 pMemoryRequirements->alignment = image->alignment;
1134 }
1135
1136 void radv_GetImageSparseMemoryRequirements(
1137 VkDevice device,
1138 VkImage image,
1139 uint32_t* pSparseMemoryRequirementCount,
1140 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1141 {
1142 stub();
1143 }
1144
1145 void radv_GetDeviceMemoryCommitment(
1146 VkDevice device,
1147 VkDeviceMemory memory,
1148 VkDeviceSize* pCommittedMemoryInBytes)
1149 {
1150 *pCommittedMemoryInBytes = 0;
1151 }
1152
1153 VkResult radv_BindBufferMemory(
1154 VkDevice device,
1155 VkBuffer _buffer,
1156 VkDeviceMemory _memory,
1157 VkDeviceSize memoryOffset)
1158 {
1159 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1160 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1161
1162 if (mem) {
1163 buffer->bo = mem->bo;
1164 buffer->offset = memoryOffset;
1165 } else {
1166 buffer->bo = NULL;
1167 buffer->offset = 0;
1168 }
1169
1170 return VK_SUCCESS;
1171 }
1172
1173 VkResult radv_BindImageMemory(
1174 VkDevice device,
1175 VkImage _image,
1176 VkDeviceMemory _memory,
1177 VkDeviceSize memoryOffset)
1178 {
1179 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1180 RADV_FROM_HANDLE(radv_image, image, _image);
1181
1182 if (mem) {
1183 image->bo = mem->bo;
1184 image->offset = memoryOffset;
1185 } else {
1186 image->bo = NULL;
1187 image->offset = 0;
1188 }
1189
1190 return VK_SUCCESS;
1191 }
1192
1193 VkResult radv_QueueBindSparse(
1194 VkQueue queue,
1195 uint32_t bindInfoCount,
1196 const VkBindSparseInfo* pBindInfo,
1197 VkFence fence)
1198 {
1199 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1200 }
1201
1202 VkResult radv_CreateFence(
1203 VkDevice _device,
1204 const VkFenceCreateInfo* pCreateInfo,
1205 const VkAllocationCallbacks* pAllocator,
1206 VkFence* pFence)
1207 {
1208 RADV_FROM_HANDLE(radv_device, device, _device);
1209 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1210 sizeof(*fence), 8,
1211 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1212
1213 if (!fence)
1214 return VK_ERROR_OUT_OF_HOST_MEMORY;
1215
1216 memset(fence, 0, sizeof(*fence));
1217 fence->submitted = false;
1218 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1219 fence->fence = device->ws->create_fence();
1220 if (!fence->fence) {
1221 vk_free2(&device->alloc, pAllocator, fence);
1222 return VK_ERROR_OUT_OF_HOST_MEMORY;
1223 }
1224
1225 *pFence = radv_fence_to_handle(fence);
1226
1227 return VK_SUCCESS;
1228 }
1229
1230 void radv_DestroyFence(
1231 VkDevice _device,
1232 VkFence _fence,
1233 const VkAllocationCallbacks* pAllocator)
1234 {
1235 RADV_FROM_HANDLE(radv_device, device, _device);
1236 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1237
1238 if (!fence)
1239 return;
1240 device->ws->destroy_fence(fence->fence);
1241 vk_free2(&device->alloc, pAllocator, fence);
1242 }
1243
1244 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1245 {
1246 uint64_t current_time;
1247 struct timespec tv;
1248
1249 clock_gettime(CLOCK_MONOTONIC, &tv);
1250 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1251
1252 timeout = MIN2(UINT64_MAX - current_time, timeout);
1253
1254 return current_time + timeout;
1255 }
1256
1257 VkResult radv_WaitForFences(
1258 VkDevice _device,
1259 uint32_t fenceCount,
1260 const VkFence* pFences,
1261 VkBool32 waitAll,
1262 uint64_t timeout)
1263 {
1264 RADV_FROM_HANDLE(radv_device, device, _device);
1265 timeout = radv_get_absolute_timeout(timeout);
1266
1267 if (!waitAll && fenceCount > 1) {
1268 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1269 }
1270
1271 for (uint32_t i = 0; i < fenceCount; ++i) {
1272 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1273 bool expired = false;
1274
1275 if (fence->signalled)
1276 continue;
1277
1278 if (!fence->submitted)
1279 return VK_TIMEOUT;
1280
1281 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1282 if (!expired)
1283 return VK_TIMEOUT;
1284
1285 fence->signalled = true;
1286 }
1287
1288 return VK_SUCCESS;
1289 }
1290
1291 VkResult radv_ResetFences(VkDevice device,
1292 uint32_t fenceCount,
1293 const VkFence *pFences)
1294 {
1295 for (unsigned i = 0; i < fenceCount; ++i) {
1296 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1297 fence->submitted = fence->signalled = false;
1298 }
1299
1300 return VK_SUCCESS;
1301 }
1302
1303 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1304 {
1305 RADV_FROM_HANDLE(radv_device, device, _device);
1306 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1307
1308 if (fence->signalled)
1309 return VK_SUCCESS;
1310 if (!fence->submitted)
1311 return VK_NOT_READY;
1312
1313 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1314 return VK_NOT_READY;
1315
1316 return VK_SUCCESS;
1317 }
1318
1319
1320 // Queue semaphore functions
1321
1322 VkResult radv_CreateSemaphore(
1323 VkDevice _device,
1324 const VkSemaphoreCreateInfo* pCreateInfo,
1325 const VkAllocationCallbacks* pAllocator,
1326 VkSemaphore* pSemaphore)
1327 {
1328 RADV_FROM_HANDLE(radv_device, device, _device);
1329 struct radeon_winsys_sem *sem;
1330
1331 sem = device->ws->create_sem(device->ws);
1332 if (!sem)
1333 return VK_ERROR_OUT_OF_HOST_MEMORY;
1334
1335 *pSemaphore = (VkSemaphore)sem;
1336 return VK_SUCCESS;
1337 }
1338
1339 void radv_DestroySemaphore(
1340 VkDevice _device,
1341 VkSemaphore _semaphore,
1342 const VkAllocationCallbacks* pAllocator)
1343 {
1344 RADV_FROM_HANDLE(radv_device, device, _device);
1345 struct radeon_winsys_sem *sem;
1346 if (!_semaphore)
1347 return;
1348
1349 sem = (struct radeon_winsys_sem *)_semaphore;
1350 device->ws->destroy_sem(sem);
1351 }
1352
1353 VkResult radv_CreateEvent(
1354 VkDevice _device,
1355 const VkEventCreateInfo* pCreateInfo,
1356 const VkAllocationCallbacks* pAllocator,
1357 VkEvent* pEvent)
1358 {
1359 RADV_FROM_HANDLE(radv_device, device, _device);
1360 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1361 sizeof(*event), 8,
1362 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1363
1364 if (!event)
1365 return VK_ERROR_OUT_OF_HOST_MEMORY;
1366
1367 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1368 RADEON_DOMAIN_GTT,
1369 RADEON_FLAG_CPU_ACCESS);
1370 if (!event->bo) {
1371 vk_free2(&device->alloc, pAllocator, event);
1372 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1373 }
1374
1375 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1376
1377 *pEvent = radv_event_to_handle(event);
1378
1379 return VK_SUCCESS;
1380 }
1381
1382 void radv_DestroyEvent(
1383 VkDevice _device,
1384 VkEvent _event,
1385 const VkAllocationCallbacks* pAllocator)
1386 {
1387 RADV_FROM_HANDLE(radv_device, device, _device);
1388 RADV_FROM_HANDLE(radv_event, event, _event);
1389
1390 if (!event)
1391 return;
1392 device->ws->buffer_destroy(event->bo);
1393 vk_free2(&device->alloc, pAllocator, event);
1394 }
1395
1396 VkResult radv_GetEventStatus(
1397 VkDevice _device,
1398 VkEvent _event)
1399 {
1400 RADV_FROM_HANDLE(radv_event, event, _event);
1401
1402 if (*event->map == 1)
1403 return VK_EVENT_SET;
1404 return VK_EVENT_RESET;
1405 }
1406
1407 VkResult radv_SetEvent(
1408 VkDevice _device,
1409 VkEvent _event)
1410 {
1411 RADV_FROM_HANDLE(radv_event, event, _event);
1412 *event->map = 1;
1413
1414 return VK_SUCCESS;
1415 }
1416
1417 VkResult radv_ResetEvent(
1418 VkDevice _device,
1419 VkEvent _event)
1420 {
1421 RADV_FROM_HANDLE(radv_event, event, _event);
1422 *event->map = 0;
1423
1424 return VK_SUCCESS;
1425 }
1426
1427 VkResult radv_CreateBuffer(
1428 VkDevice _device,
1429 const VkBufferCreateInfo* pCreateInfo,
1430 const VkAllocationCallbacks* pAllocator,
1431 VkBuffer* pBuffer)
1432 {
1433 RADV_FROM_HANDLE(radv_device, device, _device);
1434 struct radv_buffer *buffer;
1435
1436 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1437
1438 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1439 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1440 if (buffer == NULL)
1441 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1442
1443 buffer->size = pCreateInfo->size;
1444 buffer->usage = pCreateInfo->usage;
1445 buffer->bo = NULL;
1446 buffer->offset = 0;
1447
1448 *pBuffer = radv_buffer_to_handle(buffer);
1449
1450 return VK_SUCCESS;
1451 }
1452
1453 void radv_DestroyBuffer(
1454 VkDevice _device,
1455 VkBuffer _buffer,
1456 const VkAllocationCallbacks* pAllocator)
1457 {
1458 RADV_FROM_HANDLE(radv_device, device, _device);
1459 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1460
1461 if (!buffer)
1462 return;
1463
1464 vk_free2(&device->alloc, pAllocator, buffer);
1465 }
1466
1467 static inline unsigned
1468 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1469 {
1470 if (stencil)
1471 return image->surface.stencil_tiling_index[level];
1472 else
1473 return image->surface.tiling_index[level];
1474 }
1475
1476 static void
1477 radv_initialise_color_surface(struct radv_device *device,
1478 struct radv_color_buffer_info *cb,
1479 struct radv_image_view *iview)
1480 {
1481 const struct vk_format_description *desc;
1482 unsigned ntype, format, swap, endian;
1483 unsigned blend_clamp = 0, blend_bypass = 0;
1484 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1485 uint64_t va;
1486 const struct radeon_surf *surf = &iview->image->surface;
1487 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1488
1489 desc = vk_format_description(iview->vk_format);
1490
1491 memset(cb, 0, sizeof(*cb));
1492
1493 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1494 va += level_info->offset;
1495 cb->cb_color_base = va >> 8;
1496
1497 /* CMASK variables */
1498 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1499 va += iview->image->cmask.offset;
1500 cb->cb_color_cmask = va >> 8;
1501 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1502
1503 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1504 va += iview->image->dcc_offset;
1505 cb->cb_dcc_base = va >> 8;
1506
1507 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1508 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1509
1510 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1511 pitch_tile_max = level_info->nblk_x / 8 - 1;
1512 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1513 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1514
1515 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1516 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1517
1518 /* Intensity is implemented as Red, so treat it that way. */
1519 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1520 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1521
1522 if (iview->image->samples > 1) {
1523 unsigned log_samples = util_logbase2(iview->image->samples);
1524
1525 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1526 S_028C74_NUM_FRAGMENTS(log_samples);
1527 }
1528
1529 if (iview->image->fmask.size) {
1530 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1531 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1532 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1533 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1534 cb->cb_color_fmask = va >> 8;
1535 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1536 } else {
1537 /* This must be set for fast clear to work without FMASK. */
1538 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1539 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1540 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1541 cb->cb_color_fmask = cb->cb_color_base;
1542 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1543 }
1544
1545 ntype = radv_translate_color_numformat(iview->vk_format,
1546 desc,
1547 vk_format_get_first_non_void_channel(iview->vk_format));
1548 format = radv_translate_colorformat(iview->vk_format);
1549 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1550 radv_finishme("Illegal color\n");
1551 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1552 endian = radv_colorformat_endian_swap(format);
1553
1554 /* blend clamp should be set for all NORM/SRGB types */
1555 if (ntype == V_028C70_NUMBER_UNORM ||
1556 ntype == V_028C70_NUMBER_SNORM ||
1557 ntype == V_028C70_NUMBER_SRGB)
1558 blend_clamp = 1;
1559
1560 /* set blend bypass according to docs if SINT/UINT or
1561 8/24 COLOR variants */
1562 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1563 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1564 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1565 blend_clamp = 0;
1566 blend_bypass = 1;
1567 }
1568 #if 0
1569 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1570 (format == V_028C70_COLOR_8 ||
1571 format == V_028C70_COLOR_8_8 ||
1572 format == V_028C70_COLOR_8_8_8_8))
1573 ->color_is_int8 = true;
1574 #endif
1575 cb->cb_color_info = S_028C70_FORMAT(format) |
1576 S_028C70_COMP_SWAP(swap) |
1577 S_028C70_BLEND_CLAMP(blend_clamp) |
1578 S_028C70_BLEND_BYPASS(blend_bypass) |
1579 S_028C70_SIMPLE_FLOAT(1) |
1580 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1581 ntype != V_028C70_NUMBER_SNORM &&
1582 ntype != V_028C70_NUMBER_SRGB &&
1583 format != V_028C70_COLOR_8_24 &&
1584 format != V_028C70_COLOR_24_8) |
1585 S_028C70_NUMBER_TYPE(ntype) |
1586 S_028C70_ENDIAN(endian);
1587 if (iview->image->samples > 1)
1588 if (iview->image->fmask.size)
1589 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1590
1591 if (iview->image->cmask.size && device->allow_fast_clears)
1592 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1593
1594 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1595 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1596
1597 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1598 unsigned max_uncompressed_block_size = 2;
1599 if (iview->image->samples > 1) {
1600 if (iview->image->surface.bpe == 1)
1601 max_uncompressed_block_size = 0;
1602 else if (iview->image->surface.bpe == 2)
1603 max_uncompressed_block_size = 1;
1604 }
1605
1606 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1607 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1608 }
1609
1610 /* This must be set for fast clear to work without FMASK. */
1611 if (!iview->image->fmask.size &&
1612 device->instance->physicalDevice.rad_info.chip_class == SI) {
1613 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1614 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1615 }
1616 }
1617
1618 static void
1619 radv_initialise_ds_surface(struct radv_device *device,
1620 struct radv_ds_buffer_info *ds,
1621 struct radv_image_view *iview)
1622 {
1623 unsigned level = iview->base_mip;
1624 unsigned format;
1625 uint64_t va, s_offs, z_offs;
1626 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1627 memset(ds, 0, sizeof(*ds));
1628 switch (iview->vk_format) {
1629 case VK_FORMAT_D24_UNORM_S8_UINT:
1630 case VK_FORMAT_X8_D24_UNORM_PACK32:
1631 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1632 ds->offset_scale = 2.0f;
1633 break;
1634 case VK_FORMAT_D16_UNORM:
1635 case VK_FORMAT_D16_UNORM_S8_UINT:
1636 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1637 ds->offset_scale = 4.0f;
1638 break;
1639 case VK_FORMAT_D32_SFLOAT:
1640 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1641 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1642 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1643 ds->offset_scale = 1.0f;
1644 break;
1645 default:
1646 break;
1647 }
1648
1649 format = radv_translate_dbformat(iview->vk_format);
1650 if (format == V_028040_Z_INVALID) {
1651 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1652 }
1653
1654 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1655 s_offs = z_offs = va;
1656 z_offs += iview->image->surface.level[level].offset;
1657 s_offs += iview->image->surface.stencil_level[level].offset;
1658
1659 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1660 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1661 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1662 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1663
1664 if (iview->image->samples > 1)
1665 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1666
1667 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1668 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1669 else
1670 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1671
1672 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1673 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1674 unsigned tiling_index = iview->image->surface.tiling_index[level];
1675 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1676 unsigned macro_index = iview->image->surface.macro_tile_index;
1677 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1678 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1679 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1680
1681 ds->db_depth_info |=
1682 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1683 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1684 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1685 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1686 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1687 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1688 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1689 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1690 } else {
1691 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1692 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1693 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1694 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1695 }
1696
1697 if (iview->image->htile.size && !level) {
1698 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1699 S_028040_ALLOW_EXPCLEAR(1);
1700
1701 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1702 /* Workaround: For a not yet understood reason, the
1703 * combination of MSAA, fast stencil clear and stencil
1704 * decompress messes with subsequent stencil buffer
1705 * uses. Problem was reproduced on Verde, Bonaire,
1706 * Tonga, and Carrizo.
1707 *
1708 * Disabling EXPCLEAR works around the problem.
1709 *
1710 * Check piglit's arb_texture_multisample-stencil-clear
1711 * test if you want to try changing this.
1712 */
1713 if (iview->image->samples <= 1)
1714 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1715 } else
1716 /* Use all of the htile_buffer for depth if there's no stencil. */
1717 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1718
1719 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1720 iview->image->htile.offset;
1721 ds->db_htile_data_base = va >> 8;
1722 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1723 } else {
1724 ds->db_htile_data_base = 0;
1725 ds->db_htile_surface = 0;
1726 }
1727
1728 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1729 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1730
1731 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1732 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1733 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1734 }
1735
1736 VkResult radv_CreateFramebuffer(
1737 VkDevice _device,
1738 const VkFramebufferCreateInfo* pCreateInfo,
1739 const VkAllocationCallbacks* pAllocator,
1740 VkFramebuffer* pFramebuffer)
1741 {
1742 RADV_FROM_HANDLE(radv_device, device, _device);
1743 struct radv_framebuffer *framebuffer;
1744
1745 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1746
1747 size_t size = sizeof(*framebuffer) +
1748 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1749 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1750 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1751 if (framebuffer == NULL)
1752 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1753
1754 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1755 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1756 VkImageView _iview = pCreateInfo->pAttachments[i];
1757 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1758 framebuffer->attachments[i].attachment = iview;
1759 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1760 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1761 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1762 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1763 }
1764 }
1765
1766 framebuffer->width = pCreateInfo->width;
1767 framebuffer->height = pCreateInfo->height;
1768 framebuffer->layers = pCreateInfo->layers;
1769
1770 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1771 return VK_SUCCESS;
1772 }
1773
1774 void radv_DestroyFramebuffer(
1775 VkDevice _device,
1776 VkFramebuffer _fb,
1777 const VkAllocationCallbacks* pAllocator)
1778 {
1779 RADV_FROM_HANDLE(radv_device, device, _device);
1780 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1781
1782 if (!fb)
1783 return;
1784 vk_free2(&device->alloc, pAllocator, fb);
1785 }
1786
1787 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1788 {
1789 switch (address_mode) {
1790 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1791 return V_008F30_SQ_TEX_WRAP;
1792 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1793 return V_008F30_SQ_TEX_MIRROR;
1794 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1795 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1796 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1797 return V_008F30_SQ_TEX_CLAMP_BORDER;
1798 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1799 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1800 default:
1801 unreachable("illegal tex wrap mode");
1802 break;
1803 }
1804 }
1805
1806 static unsigned
1807 radv_tex_compare(VkCompareOp op)
1808 {
1809 switch (op) {
1810 case VK_COMPARE_OP_NEVER:
1811 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1812 case VK_COMPARE_OP_LESS:
1813 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1814 case VK_COMPARE_OP_EQUAL:
1815 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1816 case VK_COMPARE_OP_LESS_OR_EQUAL:
1817 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1818 case VK_COMPARE_OP_GREATER:
1819 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1820 case VK_COMPARE_OP_NOT_EQUAL:
1821 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1822 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1823 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1824 case VK_COMPARE_OP_ALWAYS:
1825 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1826 default:
1827 unreachable("illegal compare mode");
1828 break;
1829 }
1830 }
1831
1832 static unsigned
1833 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1834 {
1835 switch (filter) {
1836 case VK_FILTER_NEAREST:
1837 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1838 V_008F38_SQ_TEX_XY_FILTER_POINT);
1839 case VK_FILTER_LINEAR:
1840 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1841 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1842 case VK_FILTER_CUBIC_IMG:
1843 default:
1844 fprintf(stderr, "illegal texture filter");
1845 return 0;
1846 }
1847 }
1848
1849 static unsigned
1850 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1851 {
1852 switch (mode) {
1853 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1854 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1855 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1856 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1857 default:
1858 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1859 }
1860 }
1861
1862 static unsigned
1863 radv_tex_bordercolor(VkBorderColor bcolor)
1864 {
1865 switch (bcolor) {
1866 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1867 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1868 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1869 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1870 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1871 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1872 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1873 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1874 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1875 default:
1876 break;
1877 }
1878 return 0;
1879 }
1880
1881 static unsigned
1882 radv_tex_aniso_filter(unsigned filter)
1883 {
1884 if (filter < 2)
1885 return 0;
1886 if (filter < 4)
1887 return 1;
1888 if (filter < 8)
1889 return 2;
1890 if (filter < 16)
1891 return 3;
1892 return 4;
1893 }
1894
1895 static void
1896 radv_init_sampler(struct radv_device *device,
1897 struct radv_sampler *sampler,
1898 const VkSamplerCreateInfo *pCreateInfo)
1899 {
1900 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1901 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1902 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1903 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1904
1905 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1906 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1907 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1908 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1909 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1910 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1911 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1912 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1913 S_008F30_DISABLE_CUBE_WRAP(0) |
1914 S_008F30_COMPAT_MODE(is_vi));
1915 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1916 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1917 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1918 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1919 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1920 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1921 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1922 S_008F38_MIP_POINT_PRECLAMP(1) |
1923 S_008F38_DISABLE_LSB_CEIL(1) |
1924 S_008F38_FILTER_PREC_FIX(1) |
1925 S_008F38_ANISO_OVERRIDE(is_vi));
1926 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1927 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1928 }
1929
1930 VkResult radv_CreateSampler(
1931 VkDevice _device,
1932 const VkSamplerCreateInfo* pCreateInfo,
1933 const VkAllocationCallbacks* pAllocator,
1934 VkSampler* pSampler)
1935 {
1936 RADV_FROM_HANDLE(radv_device, device, _device);
1937 struct radv_sampler *sampler;
1938
1939 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1940
1941 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1942 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1943 if (!sampler)
1944 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1945
1946 radv_init_sampler(device, sampler, pCreateInfo);
1947 *pSampler = radv_sampler_to_handle(sampler);
1948
1949 return VK_SUCCESS;
1950 }
1951
1952 void radv_DestroySampler(
1953 VkDevice _device,
1954 VkSampler _sampler,
1955 const VkAllocationCallbacks* pAllocator)
1956 {
1957 RADV_FROM_HANDLE(radv_device, device, _device);
1958 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1959
1960 if (!sampler)
1961 return;
1962 vk_free2(&device->alloc, pAllocator, sampler);
1963 }