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radv/gfx10: implement radv_initialise_ds_surface()
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
120 }
121
122 static uint64_t
123 radv_get_visible_vram_size(struct radv_physical_device *device)
124 {
125 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
126 }
127
128 static uint64_t
129 radv_get_vram_size(struct radv_physical_device *device)
130 {
131 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
132 }
133
134 static void
135 radv_physical_device_init_mem_types(struct radv_physical_device *device)
136 {
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
138 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
139 uint64_t vram_size = radv_get_vram_size(device);
140 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
141 device->memory_properties.memoryHeapCount = 0;
142 if (vram_size > 0) {
143 vram_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
145 .size = vram_size,
146 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
147 };
148 }
149 if (visible_vram_size) {
150 visible_vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
152 .size = visible_vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156 if (device->rad_info.gart_size > 0) {
157 gart_index = device->memory_properties.memoryHeapCount++;
158 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
159 .size = device->rad_info.gart_size,
160 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
161 };
162 }
163
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
165 unsigned type_count = 0;
166 if (vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index,
171 };
172 }
173 if (gart_index >= 0) {
174 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
175 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
176 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
178 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
179 .heapIndex = gart_index,
180 };
181 }
182 if (visible_vram_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
188 .heapIndex = visible_vram_index,
189 };
190 }
191 if (gart_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
197 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
198 .heapIndex = gart_index,
199 };
200 }
201 device->memory_properties.memoryTypeCount = type_count;
202 }
203
204 static void
205 radv_handle_env_var_force_family(struct radv_physical_device *device)
206 {
207 const char *family = getenv("RADV_FORCE_FAMILY");
208 unsigned i;
209
210 if (!family)
211 return;
212
213 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
214 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
215 /* Override family and chip_class. */
216 device->rad_info.family = i;
217
218 if (i >= CHIP_VEGA10)
219 device->rad_info.chip_class = GFX9;
220 else if (i >= CHIP_TONGA)
221 device->rad_info.chip_class = GFX8;
222 else if (i >= CHIP_BONAIRE)
223 device->rad_info.chip_class = GFX7;
224 else
225 device->rad_info.chip_class = GFX6;
226
227 return;
228 }
229 }
230
231 fprintf(stderr, "radv: Unknown family: %s\n", family);
232 exit(1);
233 }
234
235 static VkResult
236 radv_physical_device_init(struct radv_physical_device *device,
237 struct radv_instance *instance,
238 drmDevicePtr drm_device)
239 {
240 const char *path = drm_device->nodes[DRM_NODE_RENDER];
241 VkResult result;
242 drmVersionPtr version;
243 int fd;
244 int master_fd = -1;
245
246 fd = open(path, O_RDWR | O_CLOEXEC);
247 if (fd < 0) {
248 if (instance->debug_flags & RADV_DEBUG_STARTUP)
249 radv_logi("Could not open device '%s'", path);
250
251 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
252 }
253
254 version = drmGetVersion(fd);
255 if (!version) {
256 close(fd);
257
258 if (instance->debug_flags & RADV_DEBUG_STARTUP)
259 radv_logi("Could not get the kernel driver version for device '%s'", path);
260
261 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
262 "failed to get version %s: %m", path);
263 }
264
265 if (strcmp(version->name, "amdgpu")) {
266 drmFreeVersion(version);
267 close(fd);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
271
272 return VK_ERROR_INCOMPATIBLE_DRIVER;
273 }
274 drmFreeVersion(version);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Found compatible device '%s'.", path);
278
279 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
280 device->instance = instance;
281
282 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
283 instance->perftest_flags);
284 if (!device->ws) {
285 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
286 goto fail;
287 }
288
289 if (instance->enabled_extensions.KHR_display) {
290 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
291 if (master_fd >= 0) {
292 uint32_t accel_working = 0;
293 struct drm_amdgpu_info request = {
294 .return_pointer = (uintptr_t)&accel_working,
295 .return_size = sizeof(accel_working),
296 .query = AMDGPU_INFO_ACCEL_WORKING
297 };
298
299 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
300 close(master_fd);
301 master_fd = -1;
302 }
303 }
304 }
305
306 device->master_fd = master_fd;
307 device->local_fd = fd;
308 device->ws->query_info(device->ws, &device->rad_info);
309
310 radv_handle_env_var_force_family(device);
311
312 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 device->ws->destroy(device->ws);
316 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
317 "cannot generate UUID");
318 goto fail;
319 }
320
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags =
323 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
324 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
325
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
328 */
329 char buf[VK_UUID_SIZE * 2 + 1];
330 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
331 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
332
333 if (device->rad_info.chip_class < GFX8 ||
334 device->rad_info.chip_class > GFX9)
335 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
336
337 radv_get_driver_uuid(&device->driver_uuid);
338 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
339
340 if (device->rad_info.family == CHIP_STONEY ||
341 device->rad_info.chip_class >= GFX9) {
342 device->has_rbplus = true;
343 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.family == CHIP_VEGA12 ||
345 device->rad_info.family == CHIP_RAVEN ||
346 device->rad_info.family == CHIP_RAVEN2;
347 }
348
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
350 * on GFX6.
351 */
352 device->has_clear_state = device->rad_info.chip_class >= GFX7;
353
354 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
355
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
358 device->rad_info.family == CHIP_RAVEN;
359
360 /* Out-of-order primitive rasterization. */
361 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
362 device->rad_info.max_se >= 2;
363 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
364 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
365
366 device->dcc_msaa_allowed =
367 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
368
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
371 (device->rad_info.chip_class >= GFX8 &&
372 device->rad_info.me_fw_feature >= 41);
373
374 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
375
376 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
377
378 radv_physical_device_init_mem_types(device);
379 radv_fill_device_extension_table(device, &device->supported_extensions);
380
381 device->bus_info = *drm_device->businfo.pci;
382
383 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
384 ac_print_gpu_info(&device->rad_info);
385
386 /* The WSI is structured as a layer on top of the driver, so this has
387 * to be the last part of initialization (at least until we get other
388 * semi-layers).
389 */
390 result = radv_init_wsi(device);
391 if (result != VK_SUCCESS) {
392 device->ws->destroy(device->ws);
393 vk_error(instance, result);
394 goto fail;
395 }
396
397 return VK_SUCCESS;
398
399 fail:
400 close(fd);
401 if (master_fd != -1)
402 close(master_fd);
403 return result;
404 }
405
406 static void
407 radv_physical_device_finish(struct radv_physical_device *device)
408 {
409 radv_finish_wsi(device);
410 device->ws->destroy(device->ws);
411 disk_cache_destroy(device->disk_cache);
412 close(device->local_fd);
413 if (device->master_fd != -1)
414 close(device->master_fd);
415 }
416
417 static void *
418 default_alloc_func(void *pUserData, size_t size, size_t align,
419 VkSystemAllocationScope allocationScope)
420 {
421 return malloc(size);
422 }
423
424 static void *
425 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
426 size_t align, VkSystemAllocationScope allocationScope)
427 {
428 return realloc(pOriginal, size);
429 }
430
431 static void
432 default_free_func(void *pUserData, void *pMemory)
433 {
434 free(pMemory);
435 }
436
437 static const VkAllocationCallbacks default_alloc = {
438 .pUserData = NULL,
439 .pfnAllocation = default_alloc_func,
440 .pfnReallocation = default_realloc_func,
441 .pfnFree = default_free_func,
442 };
443
444 static const struct debug_control radv_debug_options[] = {
445 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
446 {"nodcc", RADV_DEBUG_NO_DCC},
447 {"shaders", RADV_DEBUG_DUMP_SHADERS},
448 {"nocache", RADV_DEBUG_NO_CACHE},
449 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
450 {"nohiz", RADV_DEBUG_NO_HIZ},
451 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
452 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
453 {"allbos", RADV_DEBUG_ALL_BOS},
454 {"noibs", RADV_DEBUG_NO_IBS},
455 {"spirv", RADV_DEBUG_DUMP_SPIRV},
456 {"vmfaults", RADV_DEBUG_VM_FAULTS},
457 {"zerovram", RADV_DEBUG_ZERO_VRAM},
458 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
459 {"nosisched", RADV_DEBUG_NO_SISCHED},
460 {"preoptir", RADV_DEBUG_PREOPTIR},
461 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
462 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
463 {"info", RADV_DEBUG_INFO},
464 {"errors", RADV_DEBUG_ERRORS},
465 {"startup", RADV_DEBUG_STARTUP},
466 {"checkir", RADV_DEBUG_CHECKIR},
467 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
468 {"nobinning", RADV_DEBUG_NOBINNING},
469 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
470 {NULL, 0}
471 };
472
473 const char *
474 radv_get_debug_option_name(int id)
475 {
476 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
477 return radv_debug_options[id].string;
478 }
479
480 static const struct debug_control radv_perftest_options[] = {
481 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
482 {"sisched", RADV_PERFTEST_SISCHED},
483 {"localbos", RADV_PERFTEST_LOCAL_BOS},
484 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
485 {"bolist", RADV_PERFTEST_BO_LIST},
486 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
487 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
488 {NULL, 0}
489 };
490
491 const char *
492 radv_get_perftest_option_name(int id)
493 {
494 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
495 return radv_perftest_options[id].string;
496 }
497
498 static void
499 radv_handle_per_app_options(struct radv_instance *instance,
500 const VkApplicationInfo *info)
501 {
502 const char *name = info ? info->pApplicationName : NULL;
503
504 if (!name)
505 return;
506
507 if (!strcmp(name, "Talos - Linux - 32bit") ||
508 !strcmp(name, "Talos - Linux - 64bit")) {
509 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
510 /* Force enable LLVM sisched for Talos because it looks
511 * safe and it gives few more FPS.
512 */
513 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
514 }
515 } else if (!strcmp(name, "DOOM_VFR")) {
516 /* Work around a Doom VFR game bug */
517 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
518 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
519 /* Workaround for a WaW hazard when LLVM moves/merges
520 * load/store memory operations.
521 * See https://reviews.llvm.org/D61313
522 */
523 if (HAVE_LLVM < 0x900)
524 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
525 }
526 }
527
528 static int radv_get_instance_extension_index(const char *name)
529 {
530 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
531 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
532 return i;
533 }
534 return -1;
535 }
536
537 static const char radv_dri_options_xml[] =
538 DRI_CONF_BEGIN
539 DRI_CONF_SECTION_QUALITY
540 DRI_CONF_ADAPTIVE_SYNC("true")
541 DRI_CONF_SECTION_END
542 DRI_CONF_END;
543
544 static void radv_init_dri_options(struct radv_instance *instance)
545 {
546 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
547 driParseConfigFiles(&instance->dri_options,
548 &instance->available_dri_options,
549 0, "radv", NULL);
550 }
551
552 VkResult radv_CreateInstance(
553 const VkInstanceCreateInfo* pCreateInfo,
554 const VkAllocationCallbacks* pAllocator,
555 VkInstance* pInstance)
556 {
557 struct radv_instance *instance;
558 VkResult result;
559
560 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
561
562 uint32_t client_version;
563 if (pCreateInfo->pApplicationInfo &&
564 pCreateInfo->pApplicationInfo->apiVersion != 0) {
565 client_version = pCreateInfo->pApplicationInfo->apiVersion;
566 } else {
567 client_version = VK_API_VERSION_1_0;
568 }
569
570 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
571 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
572 if (!instance)
573 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
574
575 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
576
577 if (pAllocator)
578 instance->alloc = *pAllocator;
579 else
580 instance->alloc = default_alloc;
581
582 instance->apiVersion = client_version;
583 instance->physicalDeviceCount = -1;
584
585 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
586 radv_debug_options);
587
588 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
589 radv_perftest_options);
590
591
592 if (instance->debug_flags & RADV_DEBUG_STARTUP)
593 radv_logi("Created an instance");
594
595 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
596 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
597 int index = radv_get_instance_extension_index(ext_name);
598
599 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
600 vk_free2(&default_alloc, pAllocator, instance);
601 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
602 }
603
604 instance->enabled_extensions.extensions[index] = true;
605 }
606
607 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
608 if (result != VK_SUCCESS) {
609 vk_free2(&default_alloc, pAllocator, instance);
610 return vk_error(instance, result);
611 }
612
613 _mesa_locale_init();
614 glsl_type_singleton_init_or_ref();
615
616 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
617
618 radv_init_dri_options(instance);
619 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
620
621 *pInstance = radv_instance_to_handle(instance);
622
623 return VK_SUCCESS;
624 }
625
626 void radv_DestroyInstance(
627 VkInstance _instance,
628 const VkAllocationCallbacks* pAllocator)
629 {
630 RADV_FROM_HANDLE(radv_instance, instance, _instance);
631
632 if (!instance)
633 return;
634
635 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
636 radv_physical_device_finish(instance->physicalDevices + i);
637 }
638
639 VG(VALGRIND_DESTROY_MEMPOOL(instance));
640
641 glsl_type_singleton_decref();
642 _mesa_locale_fini();
643
644 driDestroyOptionCache(&instance->dri_options);
645 driDestroyOptionInfo(&instance->available_dri_options);
646
647 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
648
649 vk_free(&instance->alloc, instance);
650 }
651
652 static VkResult
653 radv_enumerate_devices(struct radv_instance *instance)
654 {
655 /* TODO: Check for more devices ? */
656 drmDevicePtr devices[8];
657 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
658 int max_devices;
659
660 instance->physicalDeviceCount = 0;
661
662 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
663
664 if (instance->debug_flags & RADV_DEBUG_STARTUP)
665 radv_logi("Found %d drm nodes", max_devices);
666
667 if (max_devices < 1)
668 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
669
670 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
671 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
672 devices[i]->bustype == DRM_BUS_PCI &&
673 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
674
675 result = radv_physical_device_init(instance->physicalDevices +
676 instance->physicalDeviceCount,
677 instance,
678 devices[i]);
679 if (result == VK_SUCCESS)
680 ++instance->physicalDeviceCount;
681 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
682 break;
683 }
684 }
685 drmFreeDevices(devices, max_devices);
686
687 return result;
688 }
689
690 VkResult radv_EnumeratePhysicalDevices(
691 VkInstance _instance,
692 uint32_t* pPhysicalDeviceCount,
693 VkPhysicalDevice* pPhysicalDevices)
694 {
695 RADV_FROM_HANDLE(radv_instance, instance, _instance);
696 VkResult result;
697
698 if (instance->physicalDeviceCount < 0) {
699 result = radv_enumerate_devices(instance);
700 if (result != VK_SUCCESS &&
701 result != VK_ERROR_INCOMPATIBLE_DRIVER)
702 return result;
703 }
704
705 if (!pPhysicalDevices) {
706 *pPhysicalDeviceCount = instance->physicalDeviceCount;
707 } else {
708 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
709 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
710 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
711 }
712
713 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
714 : VK_SUCCESS;
715 }
716
717 VkResult radv_EnumeratePhysicalDeviceGroups(
718 VkInstance _instance,
719 uint32_t* pPhysicalDeviceGroupCount,
720 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
721 {
722 RADV_FROM_HANDLE(radv_instance, instance, _instance);
723 VkResult result;
724
725 if (instance->physicalDeviceCount < 0) {
726 result = radv_enumerate_devices(instance);
727 if (result != VK_SUCCESS &&
728 result != VK_ERROR_INCOMPATIBLE_DRIVER)
729 return result;
730 }
731
732 if (!pPhysicalDeviceGroupProperties) {
733 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
734 } else {
735 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
736 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
737 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
738 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
739 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
740 }
741 }
742 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
743 : VK_SUCCESS;
744 }
745
746 void radv_GetPhysicalDeviceFeatures(
747 VkPhysicalDevice physicalDevice,
748 VkPhysicalDeviceFeatures* pFeatures)
749 {
750 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
751 memset(pFeatures, 0, sizeof(*pFeatures));
752
753 *pFeatures = (VkPhysicalDeviceFeatures) {
754 .robustBufferAccess = true,
755 .fullDrawIndexUint32 = true,
756 .imageCubeArray = true,
757 .independentBlend = true,
758 .geometryShader = true,
759 .tessellationShader = true,
760 .sampleRateShading = true,
761 .dualSrcBlend = true,
762 .logicOp = true,
763 .multiDrawIndirect = true,
764 .drawIndirectFirstInstance = true,
765 .depthClamp = true,
766 .depthBiasClamp = true,
767 .fillModeNonSolid = true,
768 .depthBounds = true,
769 .wideLines = true,
770 .largePoints = true,
771 .alphaToOne = true,
772 .multiViewport = true,
773 .samplerAnisotropy = true,
774 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
775 .textureCompressionASTC_LDR = false,
776 .textureCompressionBC = true,
777 .occlusionQueryPrecise = true,
778 .pipelineStatisticsQuery = true,
779 .vertexPipelineStoresAndAtomics = true,
780 .fragmentStoresAndAtomics = true,
781 .shaderTessellationAndGeometryPointSize = true,
782 .shaderImageGatherExtended = true,
783 .shaderStorageImageExtendedFormats = true,
784 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
785 .shaderUniformBufferArrayDynamicIndexing = true,
786 .shaderSampledImageArrayDynamicIndexing = true,
787 .shaderStorageBufferArrayDynamicIndexing = true,
788 .shaderStorageImageArrayDynamicIndexing = true,
789 .shaderStorageImageReadWithoutFormat = true,
790 .shaderStorageImageWriteWithoutFormat = true,
791 .shaderClipDistance = true,
792 .shaderCullDistance = true,
793 .shaderFloat64 = true,
794 .shaderInt64 = true,
795 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
796 .sparseBinding = true,
797 .variableMultisampleRate = true,
798 .inheritedQueries = true,
799 };
800 }
801
802 void radv_GetPhysicalDeviceFeatures2(
803 VkPhysicalDevice physicalDevice,
804 VkPhysicalDeviceFeatures2 *pFeatures)
805 {
806 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
807 vk_foreach_struct(ext, pFeatures->pNext) {
808 switch (ext->sType) {
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
810 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
811 features->variablePointersStorageBuffer = true;
812 features->variablePointers = true;
813 break;
814 }
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
816 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
817 features->multiview = true;
818 features->multiviewGeometryShader = true;
819 features->multiviewTessellationShader = true;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
823 VkPhysicalDeviceShaderDrawParametersFeatures *features =
824 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
825 features->shaderDrawParameters = true;
826 break;
827 }
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
829 VkPhysicalDeviceProtectedMemoryFeatures *features =
830 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
831 features->protectedMemory = false;
832 break;
833 }
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
835 VkPhysicalDevice16BitStorageFeatures *features =
836 (VkPhysicalDevice16BitStorageFeatures*)ext;
837 bool enabled = pdevice->rad_info.chip_class >= GFX8;
838 features->storageBuffer16BitAccess = enabled;
839 features->uniformAndStorageBuffer16BitAccess = enabled;
840 features->storagePushConstant16 = enabled;
841 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
845 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
846 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
847 features->samplerYcbcrConversion = true;
848 break;
849 }
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
851 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
852 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
853 features->shaderInputAttachmentArrayDynamicIndexing = true;
854 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
855 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
856 features->shaderUniformBufferArrayNonUniformIndexing = true;
857 features->shaderSampledImageArrayNonUniformIndexing = true;
858 features->shaderStorageBufferArrayNonUniformIndexing = true;
859 features->shaderStorageImageArrayNonUniformIndexing = true;
860 features->shaderInputAttachmentArrayNonUniformIndexing = true;
861 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
862 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
863 features->descriptorBindingUniformBufferUpdateAfterBind = true;
864 features->descriptorBindingSampledImageUpdateAfterBind = true;
865 features->descriptorBindingStorageImageUpdateAfterBind = true;
866 features->descriptorBindingStorageBufferUpdateAfterBind = true;
867 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
868 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
869 features->descriptorBindingUpdateUnusedWhilePending = true;
870 features->descriptorBindingPartiallyBound = true;
871 features->descriptorBindingVariableDescriptorCount = true;
872 features->runtimeDescriptorArray = true;
873 break;
874 }
875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
876 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
877 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
878 features->conditionalRendering = true;
879 features->inheritedConditionalRendering = false;
880 break;
881 }
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
883 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
884 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
885 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
886 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
890 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
891 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
892 features->transformFeedback = true;
893 features->geometryStreams = true;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
897 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
898 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
899 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
900 break;
901 }
902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
903 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
904 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
905 features->memoryPriority = VK_TRUE;
906 break;
907 }
908 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
909 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
910 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
911 features->bufferDeviceAddress = true;
912 features->bufferDeviceAddressCaptureReplay = false;
913 features->bufferDeviceAddressMultiDevice = false;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
917 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
918 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
919 features->depthClipEnable = true;
920 break;
921 }
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
923 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
924 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
925 features->hostQueryReset = true;
926 break;
927 }
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
929 VkPhysicalDevice8BitStorageFeaturesKHR *features =
930 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
931 bool enabled = pdevice->rad_info.chip_class >= GFX8;
932 features->storageBuffer8BitAccess = enabled;
933 features->uniformAndStorageBuffer8BitAccess = enabled;
934 features->storagePushConstant8 = enabled;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
938 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
939 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
940 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
941 features->shaderInt8 = true;
942 break;
943 }
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
945 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
946 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
947 /* TODO: Enable this once the driver supports 64-bit
948 * compare&swap atomic operations.
949 */
950 features->shaderBufferInt64Atomics = false;
951 features->shaderSharedInt64Atomics = false;
952 break;
953 }
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
955 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
956 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
957
958 features->inlineUniformBlock = true;
959 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
960 break;
961 }
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
963 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
964 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
965 features->computeDerivativeGroupQuads = false;
966 features->computeDerivativeGroupLinear = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
970 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
971 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
972 features->ycbcrImageArrays = true;
973 break;
974 }
975 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
976 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
977 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
978 features->uniformBufferStandardLayout = true;
979 break;
980 }
981 default:
982 break;
983 }
984 }
985 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
986 }
987
988 void radv_GetPhysicalDeviceProperties(
989 VkPhysicalDevice physicalDevice,
990 VkPhysicalDeviceProperties* pProperties)
991 {
992 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
993 VkSampleCountFlags sample_counts = 0xf;
994
995 /* make sure that the entire descriptor set is addressable with a signed
996 * 32-bit int. So the sum of all limits scaled by descriptor size has to
997 * be at most 2 GiB. the combined image & samples object count as one of
998 * both. This limit is for the pipeline layout, not for the set layout, but
999 * there is no set limit, so we just set a pipeline limit. I don't think
1000 * any app is going to hit this soon. */
1001 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1002 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1003 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1004 32 /* sampler, largest when combined with image */ +
1005 64 /* sampled image */ +
1006 64 /* storage image */);
1007
1008 VkPhysicalDeviceLimits limits = {
1009 .maxImageDimension1D = (1 << 14),
1010 .maxImageDimension2D = (1 << 14),
1011 .maxImageDimension3D = (1 << 11),
1012 .maxImageDimensionCube = (1 << 14),
1013 .maxImageArrayLayers = (1 << 11),
1014 .maxTexelBufferElements = 128 * 1024 * 1024,
1015 .maxUniformBufferRange = UINT32_MAX,
1016 .maxStorageBufferRange = UINT32_MAX,
1017 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1018 .maxMemoryAllocationCount = UINT32_MAX,
1019 .maxSamplerAllocationCount = 64 * 1024,
1020 .bufferImageGranularity = 64, /* A cache line */
1021 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1022 .maxBoundDescriptorSets = MAX_SETS,
1023 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1024 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1025 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1026 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1027 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1028 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1029 .maxPerStageResources = max_descriptor_set_size,
1030 .maxDescriptorSetSamplers = max_descriptor_set_size,
1031 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1032 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1033 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1034 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1035 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1036 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1037 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1038 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1039 .maxVertexInputBindings = MAX_VBS,
1040 .maxVertexInputAttributeOffset = 2047,
1041 .maxVertexInputBindingStride = 2048,
1042 .maxVertexOutputComponents = 128,
1043 .maxTessellationGenerationLevel = 64,
1044 .maxTessellationPatchSize = 32,
1045 .maxTessellationControlPerVertexInputComponents = 128,
1046 .maxTessellationControlPerVertexOutputComponents = 128,
1047 .maxTessellationControlPerPatchOutputComponents = 120,
1048 .maxTessellationControlTotalOutputComponents = 4096,
1049 .maxTessellationEvaluationInputComponents = 128,
1050 .maxTessellationEvaluationOutputComponents = 128,
1051 .maxGeometryShaderInvocations = 127,
1052 .maxGeometryInputComponents = 64,
1053 .maxGeometryOutputComponents = 128,
1054 .maxGeometryOutputVertices = 256,
1055 .maxGeometryTotalOutputComponents = 1024,
1056 .maxFragmentInputComponents = 128,
1057 .maxFragmentOutputAttachments = 8,
1058 .maxFragmentDualSrcAttachments = 1,
1059 .maxFragmentCombinedOutputResources = 8,
1060 .maxComputeSharedMemorySize = 32768,
1061 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1062 .maxComputeWorkGroupInvocations = 2048,
1063 .maxComputeWorkGroupSize = {
1064 2048,
1065 2048,
1066 2048
1067 },
1068 .subPixelPrecisionBits = 8,
1069 .subTexelPrecisionBits = 8,
1070 .mipmapPrecisionBits = 8,
1071 .maxDrawIndexedIndexValue = UINT32_MAX,
1072 .maxDrawIndirectCount = UINT32_MAX,
1073 .maxSamplerLodBias = 16,
1074 .maxSamplerAnisotropy = 16,
1075 .maxViewports = MAX_VIEWPORTS,
1076 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1077 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1078 .viewportSubPixelBits = 8,
1079 .minMemoryMapAlignment = 4096, /* A page */
1080 .minTexelBufferOffsetAlignment = 1,
1081 .minUniformBufferOffsetAlignment = 4,
1082 .minStorageBufferOffsetAlignment = 4,
1083 .minTexelOffset = -32,
1084 .maxTexelOffset = 31,
1085 .minTexelGatherOffset = -32,
1086 .maxTexelGatherOffset = 31,
1087 .minInterpolationOffset = -2,
1088 .maxInterpolationOffset = 2,
1089 .subPixelInterpolationOffsetBits = 8,
1090 .maxFramebufferWidth = (1 << 14),
1091 .maxFramebufferHeight = (1 << 14),
1092 .maxFramebufferLayers = (1 << 10),
1093 .framebufferColorSampleCounts = sample_counts,
1094 .framebufferDepthSampleCounts = sample_counts,
1095 .framebufferStencilSampleCounts = sample_counts,
1096 .framebufferNoAttachmentsSampleCounts = sample_counts,
1097 .maxColorAttachments = MAX_RTS,
1098 .sampledImageColorSampleCounts = sample_counts,
1099 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1100 .sampledImageDepthSampleCounts = sample_counts,
1101 .sampledImageStencilSampleCounts = sample_counts,
1102 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1103 .maxSampleMaskWords = 1,
1104 .timestampComputeAndGraphics = true,
1105 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1106 .maxClipDistances = 8,
1107 .maxCullDistances = 8,
1108 .maxCombinedClipAndCullDistances = 8,
1109 .discreteQueuePriorities = 2,
1110 .pointSizeRange = { 0.0, 8192.0 },
1111 .lineWidthRange = { 0.0, 7.9921875 },
1112 .pointSizeGranularity = (1.0 / 8.0),
1113 .lineWidthGranularity = (1.0 / 128.0),
1114 .strictLines = false, /* FINISHME */
1115 .standardSampleLocations = true,
1116 .optimalBufferCopyOffsetAlignment = 128,
1117 .optimalBufferCopyRowPitchAlignment = 128,
1118 .nonCoherentAtomSize = 64,
1119 };
1120
1121 *pProperties = (VkPhysicalDeviceProperties) {
1122 .apiVersion = radv_physical_device_api_version(pdevice),
1123 .driverVersion = vk_get_driver_version(),
1124 .vendorID = ATI_VENDOR_ID,
1125 .deviceID = pdevice->rad_info.pci_id,
1126 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1127 .limits = limits,
1128 .sparseProperties = {0},
1129 };
1130
1131 strcpy(pProperties->deviceName, pdevice->name);
1132 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1133 }
1134
1135 void radv_GetPhysicalDeviceProperties2(
1136 VkPhysicalDevice physicalDevice,
1137 VkPhysicalDeviceProperties2 *pProperties)
1138 {
1139 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1140 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1141
1142 vk_foreach_struct(ext, pProperties->pNext) {
1143 switch (ext->sType) {
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1145 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1146 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1147 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1151 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1152 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1153 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1154 properties->deviceLUIDValid = false;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1158 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1159 properties->maxMultiviewViewCount = MAX_VIEWS;
1160 properties->maxMultiviewInstanceIndex = INT_MAX;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1164 VkPhysicalDevicePointClippingProperties *properties =
1165 (VkPhysicalDevicePointClippingProperties*)ext;
1166 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1170 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1171 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1172 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1176 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1177 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1178 properties->minImportedHostPointerAlignment = 4096;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1182 VkPhysicalDeviceSubgroupProperties *properties =
1183 (VkPhysicalDeviceSubgroupProperties*)ext;
1184 properties->subgroupSize = 64;
1185 properties->supportedStages = VK_SHADER_STAGE_ALL;
1186 properties->supportedOperations =
1187 VK_SUBGROUP_FEATURE_BASIC_BIT |
1188 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1189 VK_SUBGROUP_FEATURE_QUAD_BIT |
1190 VK_SUBGROUP_FEATURE_VOTE_BIT;
1191 if (pdevice->rad_info.chip_class >= GFX8) {
1192 properties->supportedOperations |=
1193 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1194 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1195 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1196 }
1197 properties->quadOperationsInAllStages = true;
1198 break;
1199 }
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1201 VkPhysicalDeviceMaintenance3Properties *properties =
1202 (VkPhysicalDeviceMaintenance3Properties*)ext;
1203 /* Make sure everything is addressable by a signed 32-bit int, and
1204 * our largest descriptors are 96 bytes. */
1205 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1206 /* Our buffer size fields allow only this much */
1207 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1211 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1212 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1213 /* GFX6-8 only support single channel min/max filter. */
1214 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1215 properties->filterMinmaxSingleComponentFormats = true;
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1219 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1220 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1221
1222 /* Shader engines. */
1223 properties->shaderEngineCount =
1224 pdevice->rad_info.max_se;
1225 properties->shaderArraysPerEngineCount =
1226 pdevice->rad_info.max_sh_per_se;
1227 properties->computeUnitsPerShaderArray =
1228 pdevice->rad_info.num_good_cu_per_sh;
1229 properties->simdPerComputeUnit = 4;
1230 properties->wavefrontsPerSimd =
1231 pdevice->rad_info.family == CHIP_TONGA ||
1232 pdevice->rad_info.family == CHIP_ICELAND ||
1233 pdevice->rad_info.family == CHIP_POLARIS10 ||
1234 pdevice->rad_info.family == CHIP_POLARIS11 ||
1235 pdevice->rad_info.family == CHIP_POLARIS12 ||
1236 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1237 properties->wavefrontSize = 64;
1238
1239 /* SGPR. */
1240 properties->sgprsPerSimd =
1241 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1242 properties->minSgprAllocation =
1243 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1244 properties->maxSgprAllocation =
1245 pdevice->rad_info.family == CHIP_TONGA ||
1246 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1247 properties->sgprAllocationGranularity =
1248 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1249
1250 /* VGPR. */
1251 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1252 properties->minVgprAllocation = 4;
1253 properties->maxVgprAllocation = 256;
1254 properties->vgprAllocationGranularity = 4;
1255 break;
1256 }
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1258 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1259 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1260 properties->maxVertexAttribDivisor = UINT32_MAX;
1261 break;
1262 }
1263 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1264 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1265 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1266 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1267 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1268 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1269 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1270 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1271 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1272 properties->robustBufferAccessUpdateAfterBind = false;
1273 properties->quadDivergentImplicitLod = false;
1274
1275 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1276 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1277 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1278 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1279 32 /* sampler, largest when combined with image */ +
1280 64 /* sampled image */ +
1281 64 /* storage image */);
1282 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1283 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1284 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1285 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1286 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1287 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1288 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1289 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1290 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1292 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1293 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1294 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1295 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1296 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1300 VkPhysicalDeviceProtectedMemoryProperties *properties =
1301 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1302 properties->protectedNoFault = false;
1303 break;
1304 }
1305 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1306 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1307 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1308 properties->primitiveOverestimationSize = 0;
1309 properties->maxExtraPrimitiveOverestimationSize = 0;
1310 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1311 properties->primitiveUnderestimation = VK_FALSE;
1312 properties->conservativePointAndLineRasterization = VK_FALSE;
1313 properties->degenerateTrianglesRasterized = VK_FALSE;
1314 properties->degenerateLinesRasterized = VK_FALSE;
1315 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1316 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1317 break;
1318 }
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1320 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1321 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1322 properties->pciDomain = pdevice->bus_info.domain;
1323 properties->pciBus = pdevice->bus_info.bus;
1324 properties->pciDevice = pdevice->bus_info.dev;
1325 properties->pciFunction = pdevice->bus_info.func;
1326 break;
1327 }
1328 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1329 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1330 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1331
1332 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1333 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1334 strcpy(driver_props->driverName, "radv");
1335
1336 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1337 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1338 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1339 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1340
1341 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1342 .major = 1,
1343 .minor = 1,
1344 .subminor = 2,
1345 .patch = 0,
1346 };
1347 break;
1348 }
1349 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1350 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1351 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1352 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1353 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1354 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1355 properties->maxTransformFeedbackStreamDataSize = 512;
1356 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1357 properties->maxTransformFeedbackBufferDataStride = 512;
1358 properties->transformFeedbackQueries = true;
1359 properties->transformFeedbackStreamsLinesTriangles = true;
1360 properties->transformFeedbackRasterizationStreamSelect = false;
1361 properties->transformFeedbackDraw = true;
1362 break;
1363 }
1364 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1365 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1366 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1367
1368 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1369 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1370 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1371 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1372 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1373 break;
1374 }
1375 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1376 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1377 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1378 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1379 VK_SAMPLE_COUNT_4_BIT |
1380 VK_SAMPLE_COUNT_8_BIT;
1381 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1382 properties->sampleLocationCoordinateRange[0] = 0.0f;
1383 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1384 properties->sampleLocationSubPixelBits = 4;
1385 properties->variableSampleLocations = VK_FALSE;
1386 break;
1387 }
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1389 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1390 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1391
1392 /* We support all of the depth resolve modes */
1393 properties->supportedDepthResolveModes =
1394 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1395 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1396 VK_RESOLVE_MODE_MIN_BIT_KHR |
1397 VK_RESOLVE_MODE_MAX_BIT_KHR;
1398
1399 /* Average doesn't make sense for stencil so we don't support that */
1400 properties->supportedStencilResolveModes =
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1402 VK_RESOLVE_MODE_MIN_BIT_KHR |
1403 VK_RESOLVE_MODE_MAX_BIT_KHR;
1404
1405 properties->independentResolveNone = VK_TRUE;
1406 properties->independentResolve = VK_TRUE;
1407 break;
1408 }
1409 default:
1410 break;
1411 }
1412 }
1413 }
1414
1415 static void radv_get_physical_device_queue_family_properties(
1416 struct radv_physical_device* pdevice,
1417 uint32_t* pCount,
1418 VkQueueFamilyProperties** pQueueFamilyProperties)
1419 {
1420 int num_queue_families = 1;
1421 int idx;
1422 if (pdevice->rad_info.num_compute_rings > 0 &&
1423 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1424 num_queue_families++;
1425
1426 if (pQueueFamilyProperties == NULL) {
1427 *pCount = num_queue_families;
1428 return;
1429 }
1430
1431 if (!*pCount)
1432 return;
1433
1434 idx = 0;
1435 if (*pCount >= 1) {
1436 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1437 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1438 VK_QUEUE_COMPUTE_BIT |
1439 VK_QUEUE_TRANSFER_BIT |
1440 VK_QUEUE_SPARSE_BINDING_BIT,
1441 .queueCount = 1,
1442 .timestampValidBits = 64,
1443 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1444 };
1445 idx++;
1446 }
1447
1448 if (pdevice->rad_info.num_compute_rings > 0 &&
1449 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1450 if (*pCount > idx) {
1451 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1452 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1453 VK_QUEUE_TRANSFER_BIT |
1454 VK_QUEUE_SPARSE_BINDING_BIT,
1455 .queueCount = pdevice->rad_info.num_compute_rings,
1456 .timestampValidBits = 64,
1457 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1458 };
1459 idx++;
1460 }
1461 }
1462 *pCount = idx;
1463 }
1464
1465 void radv_GetPhysicalDeviceQueueFamilyProperties(
1466 VkPhysicalDevice physicalDevice,
1467 uint32_t* pCount,
1468 VkQueueFamilyProperties* pQueueFamilyProperties)
1469 {
1470 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1471 if (!pQueueFamilyProperties) {
1472 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1473 return;
1474 }
1475 VkQueueFamilyProperties *properties[] = {
1476 pQueueFamilyProperties + 0,
1477 pQueueFamilyProperties + 1,
1478 pQueueFamilyProperties + 2,
1479 };
1480 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1481 assert(*pCount <= 3);
1482 }
1483
1484 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1485 VkPhysicalDevice physicalDevice,
1486 uint32_t* pCount,
1487 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1488 {
1489 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1490 if (!pQueueFamilyProperties) {
1491 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1492 return;
1493 }
1494 VkQueueFamilyProperties *properties[] = {
1495 &pQueueFamilyProperties[0].queueFamilyProperties,
1496 &pQueueFamilyProperties[1].queueFamilyProperties,
1497 &pQueueFamilyProperties[2].queueFamilyProperties,
1498 };
1499 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1500 assert(*pCount <= 3);
1501 }
1502
1503 void radv_GetPhysicalDeviceMemoryProperties(
1504 VkPhysicalDevice physicalDevice,
1505 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1506 {
1507 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1508
1509 *pMemoryProperties = physical_device->memory_properties;
1510 }
1511
1512 static void
1513 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1514 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1515 {
1516 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1517 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1518 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1519 uint64_t vram_size = radv_get_vram_size(device);
1520 uint64_t gtt_size = device->rad_info.gart_size;
1521 uint64_t heap_budget, heap_usage;
1522
1523 /* For all memory heaps, the computation of budget is as follow:
1524 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1525 *
1526 * The Vulkan spec 1.1.97 says that the budget should include any
1527 * currently allocated device memory.
1528 *
1529 * Note that the application heap usages are not really accurate (eg.
1530 * in presence of shared buffers).
1531 */
1532 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1533 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1534
1535 switch (device->mem_type_indices[i]) {
1536 case RADV_MEM_TYPE_VRAM:
1537 heap_usage = device->ws->query_value(device->ws,
1538 RADEON_ALLOCATED_VRAM);
1539
1540 heap_budget = vram_size -
1541 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1542 heap_usage;
1543
1544 memoryBudget->heapBudget[heap_index] = heap_budget;
1545 memoryBudget->heapUsage[heap_index] = heap_usage;
1546 break;
1547 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1548 heap_usage = device->ws->query_value(device->ws,
1549 RADEON_ALLOCATED_VRAM_VIS);
1550
1551 heap_budget = visible_vram_size -
1552 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1553 heap_usage;
1554
1555 memoryBudget->heapBudget[heap_index] = heap_budget;
1556 memoryBudget->heapUsage[heap_index] = heap_usage;
1557 break;
1558 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1559 heap_usage = device->ws->query_value(device->ws,
1560 RADEON_ALLOCATED_GTT);
1561
1562 heap_budget = gtt_size -
1563 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1564 heap_usage;
1565
1566 memoryBudget->heapBudget[heap_index] = heap_budget;
1567 memoryBudget->heapUsage[heap_index] = heap_usage;
1568 break;
1569 default:
1570 break;
1571 }
1572 }
1573
1574 /* The heapBudget and heapUsage values must be zero for array elements
1575 * greater than or equal to
1576 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1577 */
1578 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1579 memoryBudget->heapBudget[i] = 0;
1580 memoryBudget->heapUsage[i] = 0;
1581 }
1582 }
1583
1584 void radv_GetPhysicalDeviceMemoryProperties2(
1585 VkPhysicalDevice physicalDevice,
1586 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1587 {
1588 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1589 &pMemoryProperties->memoryProperties);
1590
1591 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1592 vk_find_struct(pMemoryProperties->pNext,
1593 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1594 if (memory_budget)
1595 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1596 }
1597
1598 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1599 VkDevice _device,
1600 VkExternalMemoryHandleTypeFlagBits handleType,
1601 const void *pHostPointer,
1602 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1603 {
1604 RADV_FROM_HANDLE(radv_device, device, _device);
1605
1606 switch (handleType)
1607 {
1608 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1609 const struct radv_physical_device *physical_device = device->physical_device;
1610 uint32_t memoryTypeBits = 0;
1611 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1612 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1613 memoryTypeBits = (1 << i);
1614 break;
1615 }
1616 }
1617 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1618 return VK_SUCCESS;
1619 }
1620 default:
1621 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1622 }
1623 }
1624
1625 static enum radeon_ctx_priority
1626 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1627 {
1628 /* Default to MEDIUM when a specific global priority isn't requested */
1629 if (!pObj)
1630 return RADEON_CTX_PRIORITY_MEDIUM;
1631
1632 switch(pObj->globalPriority) {
1633 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1634 return RADEON_CTX_PRIORITY_REALTIME;
1635 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1636 return RADEON_CTX_PRIORITY_HIGH;
1637 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1638 return RADEON_CTX_PRIORITY_MEDIUM;
1639 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1640 return RADEON_CTX_PRIORITY_LOW;
1641 default:
1642 unreachable("Illegal global priority value");
1643 return RADEON_CTX_PRIORITY_INVALID;
1644 }
1645 }
1646
1647 static int
1648 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1649 uint32_t queue_family_index, int idx,
1650 VkDeviceQueueCreateFlags flags,
1651 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1652 {
1653 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1654 queue->device = device;
1655 queue->queue_family_index = queue_family_index;
1656 queue->queue_idx = idx;
1657 queue->priority = radv_get_queue_global_priority(global_priority);
1658 queue->flags = flags;
1659
1660 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1661 if (!queue->hw_ctx)
1662 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1663
1664 return VK_SUCCESS;
1665 }
1666
1667 static void
1668 radv_queue_finish(struct radv_queue *queue)
1669 {
1670 if (queue->hw_ctx)
1671 queue->device->ws->ctx_destroy(queue->hw_ctx);
1672
1673 if (queue->initial_full_flush_preamble_cs)
1674 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1675 if (queue->initial_preamble_cs)
1676 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1677 if (queue->continue_preamble_cs)
1678 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1679 if (queue->descriptor_bo)
1680 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1681 if (queue->scratch_bo)
1682 queue->device->ws->buffer_destroy(queue->scratch_bo);
1683 if (queue->esgs_ring_bo)
1684 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1685 if (queue->gsvs_ring_bo)
1686 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1687 if (queue->tess_rings_bo)
1688 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1689 if (queue->compute_scratch_bo)
1690 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1691 }
1692
1693 static void
1694 radv_bo_list_init(struct radv_bo_list *bo_list)
1695 {
1696 pthread_mutex_init(&bo_list->mutex, NULL);
1697 bo_list->list.count = bo_list->capacity = 0;
1698 bo_list->list.bos = NULL;
1699 }
1700
1701 static void
1702 radv_bo_list_finish(struct radv_bo_list *bo_list)
1703 {
1704 free(bo_list->list.bos);
1705 pthread_mutex_destroy(&bo_list->mutex);
1706 }
1707
1708 static VkResult radv_bo_list_add(struct radv_device *device,
1709 struct radeon_winsys_bo *bo)
1710 {
1711 struct radv_bo_list *bo_list = &device->bo_list;
1712
1713 if (bo->is_local)
1714 return VK_SUCCESS;
1715
1716 if (unlikely(!device->use_global_bo_list))
1717 return VK_SUCCESS;
1718
1719 pthread_mutex_lock(&bo_list->mutex);
1720 if (bo_list->list.count == bo_list->capacity) {
1721 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1722 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1723
1724 if (!data) {
1725 pthread_mutex_unlock(&bo_list->mutex);
1726 return VK_ERROR_OUT_OF_HOST_MEMORY;
1727 }
1728
1729 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1730 bo_list->capacity = capacity;
1731 }
1732
1733 bo_list->list.bos[bo_list->list.count++] = bo;
1734 pthread_mutex_unlock(&bo_list->mutex);
1735 return VK_SUCCESS;
1736 }
1737
1738 static void radv_bo_list_remove(struct radv_device *device,
1739 struct radeon_winsys_bo *bo)
1740 {
1741 struct radv_bo_list *bo_list = &device->bo_list;
1742
1743 if (bo->is_local)
1744 return;
1745
1746 if (unlikely(!device->use_global_bo_list))
1747 return;
1748
1749 pthread_mutex_lock(&bo_list->mutex);
1750 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1751 if (bo_list->list.bos[i] == bo) {
1752 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1753 --bo_list->list.count;
1754 break;
1755 }
1756 }
1757 pthread_mutex_unlock(&bo_list->mutex);
1758 }
1759
1760 static void
1761 radv_device_init_gs_info(struct radv_device *device)
1762 {
1763 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1764 device->physical_device->rad_info.family);
1765 }
1766
1767 static int radv_get_device_extension_index(const char *name)
1768 {
1769 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1770 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1771 return i;
1772 }
1773 return -1;
1774 }
1775
1776 static int
1777 radv_get_int_debug_option(const char *name, int default_value)
1778 {
1779 const char *str;
1780 int result;
1781
1782 str = getenv(name);
1783 if (!str) {
1784 result = default_value;
1785 } else {
1786 char *endptr;
1787
1788 result = strtol(str, &endptr, 0);
1789 if (str == endptr) {
1790 /* No digits founs. */
1791 result = default_value;
1792 }
1793 }
1794
1795 return result;
1796 }
1797
1798 VkResult radv_CreateDevice(
1799 VkPhysicalDevice physicalDevice,
1800 const VkDeviceCreateInfo* pCreateInfo,
1801 const VkAllocationCallbacks* pAllocator,
1802 VkDevice* pDevice)
1803 {
1804 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1805 VkResult result;
1806 struct radv_device *device;
1807
1808 bool keep_shader_info = false;
1809
1810 /* Check enabled features */
1811 if (pCreateInfo->pEnabledFeatures) {
1812 VkPhysicalDeviceFeatures supported_features;
1813 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1814 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1815 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1816 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1817 for (uint32_t i = 0; i < num_features; i++) {
1818 if (enabled_feature[i] && !supported_feature[i])
1819 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1820 }
1821 }
1822
1823 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1824 sizeof(*device), 8,
1825 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1826 if (!device)
1827 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1828
1829 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1830 device->instance = physical_device->instance;
1831 device->physical_device = physical_device;
1832
1833 device->ws = physical_device->ws;
1834 if (pAllocator)
1835 device->alloc = *pAllocator;
1836 else
1837 device->alloc = physical_device->instance->alloc;
1838
1839 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1840 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1841 int index = radv_get_device_extension_index(ext_name);
1842 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1843 vk_free(&device->alloc, device);
1844 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1845 }
1846
1847 device->enabled_extensions.extensions[index] = true;
1848 }
1849
1850 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1851
1852 /* With update after bind we can't attach bo's to the command buffer
1853 * from the descriptor set anymore, so we have to use a global BO list.
1854 */
1855 device->use_global_bo_list =
1856 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1857 device->enabled_extensions.EXT_descriptor_indexing ||
1858 device->enabled_extensions.EXT_buffer_device_address;
1859
1860 mtx_init(&device->shader_slab_mutex, mtx_plain);
1861 list_inithead(&device->shader_slabs);
1862
1863 radv_bo_list_init(&device->bo_list);
1864
1865 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1866 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1867 uint32_t qfi = queue_create->queueFamilyIndex;
1868 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1869 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1870
1871 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1872
1873 device->queues[qfi] = vk_alloc(&device->alloc,
1874 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1875 if (!device->queues[qfi]) {
1876 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1877 goto fail;
1878 }
1879
1880 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1881
1882 device->queue_count[qfi] = queue_create->queueCount;
1883
1884 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1885 result = radv_queue_init(device, &device->queues[qfi][q],
1886 qfi, q, queue_create->flags,
1887 global_priority);
1888 if (result != VK_SUCCESS)
1889 goto fail;
1890 }
1891 }
1892
1893 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1894 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1895
1896 /* Disabled and not implemented for now. */
1897 device->dfsm_allowed = device->pbb_allowed &&
1898 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1899 device->physical_device->rad_info.family == CHIP_RAVEN2);
1900
1901 #ifdef ANDROID
1902 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1903 #endif
1904
1905 /* The maximum number of scratch waves. Scratch space isn't divided
1906 * evenly between CUs. The number is only a function of the number of CUs.
1907 * We can decrease the constant to decrease the scratch buffer size.
1908 *
1909 * sctx->scratch_waves must be >= the maximum possible size of
1910 * 1 threadgroup, so that the hw doesn't hang from being unable
1911 * to start any.
1912 *
1913 * The recommended value is 4 per CU at most. Higher numbers don't
1914 * bring much benefit, but they still occupy chip resources (think
1915 * async compute). I've seen ~2% performance difference between 4 and 32.
1916 */
1917 uint32_t max_threads_per_block = 2048;
1918 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1919 max_threads_per_block / 64);
1920
1921 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1922
1923 if (device->physical_device->rad_info.chip_class >= GFX7) {
1924 /* If the KMD allows it (there is a KMD hw register for it),
1925 * allow launching waves out-of-order.
1926 */
1927 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1928 }
1929
1930 radv_device_init_gs_info(device);
1931
1932 device->tess_offchip_block_dw_size =
1933 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1934 device->has_distributed_tess =
1935 device->physical_device->rad_info.chip_class >= GFX8 &&
1936 device->physical_device->rad_info.max_se >= 2;
1937
1938 if (getenv("RADV_TRACE_FILE")) {
1939 const char *filename = getenv("RADV_TRACE_FILE");
1940
1941 keep_shader_info = true;
1942
1943 if (!radv_init_trace(device))
1944 goto fail;
1945
1946 fprintf(stderr, "*****************************************************************************\n");
1947 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1948 fprintf(stderr, "*****************************************************************************\n");
1949
1950 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1951 radv_dump_enabled_options(device, stderr);
1952 }
1953
1954 device->keep_shader_info = keep_shader_info;
1955
1956 result = radv_device_init_meta(device);
1957 if (result != VK_SUCCESS)
1958 goto fail;
1959
1960 radv_device_init_msaa(device);
1961
1962 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1963 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1964 switch (family) {
1965 case RADV_QUEUE_GENERAL:
1966 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1967 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1968 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1969 break;
1970 case RADV_QUEUE_COMPUTE:
1971 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1972 radeon_emit(device->empty_cs[family], 0);
1973 break;
1974 }
1975 device->ws->cs_finalize(device->empty_cs[family]);
1976 }
1977
1978 if (device->physical_device->rad_info.chip_class >= GFX7)
1979 cik_create_gfx_config(device);
1980
1981 VkPipelineCacheCreateInfo ci;
1982 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1983 ci.pNext = NULL;
1984 ci.flags = 0;
1985 ci.pInitialData = NULL;
1986 ci.initialDataSize = 0;
1987 VkPipelineCache pc;
1988 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1989 &ci, NULL, &pc);
1990 if (result != VK_SUCCESS)
1991 goto fail_meta;
1992
1993 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1994
1995 device->force_aniso =
1996 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1997 if (device->force_aniso >= 0) {
1998 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1999 1 << util_logbase2(device->force_aniso));
2000 }
2001
2002 *pDevice = radv_device_to_handle(device);
2003 return VK_SUCCESS;
2004
2005 fail_meta:
2006 radv_device_finish_meta(device);
2007 fail:
2008 radv_bo_list_finish(&device->bo_list);
2009
2010 if (device->trace_bo)
2011 device->ws->buffer_destroy(device->trace_bo);
2012
2013 if (device->gfx_init)
2014 device->ws->buffer_destroy(device->gfx_init);
2015
2016 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2017 for (unsigned q = 0; q < device->queue_count[i]; q++)
2018 radv_queue_finish(&device->queues[i][q]);
2019 if (device->queue_count[i])
2020 vk_free(&device->alloc, device->queues[i]);
2021 }
2022
2023 vk_free(&device->alloc, device);
2024 return result;
2025 }
2026
2027 void radv_DestroyDevice(
2028 VkDevice _device,
2029 const VkAllocationCallbacks* pAllocator)
2030 {
2031 RADV_FROM_HANDLE(radv_device, device, _device);
2032
2033 if (!device)
2034 return;
2035
2036 if (device->trace_bo)
2037 device->ws->buffer_destroy(device->trace_bo);
2038
2039 if (device->gfx_init)
2040 device->ws->buffer_destroy(device->gfx_init);
2041
2042 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2043 for (unsigned q = 0; q < device->queue_count[i]; q++)
2044 radv_queue_finish(&device->queues[i][q]);
2045 if (device->queue_count[i])
2046 vk_free(&device->alloc, device->queues[i]);
2047 if (device->empty_cs[i])
2048 device->ws->cs_destroy(device->empty_cs[i]);
2049 }
2050 radv_device_finish_meta(device);
2051
2052 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2053 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2054
2055 radv_destroy_shader_slabs(device);
2056
2057 radv_bo_list_finish(&device->bo_list);
2058 vk_free(&device->alloc, device);
2059 }
2060
2061 VkResult radv_EnumerateInstanceLayerProperties(
2062 uint32_t* pPropertyCount,
2063 VkLayerProperties* pProperties)
2064 {
2065 if (pProperties == NULL) {
2066 *pPropertyCount = 0;
2067 return VK_SUCCESS;
2068 }
2069
2070 /* None supported at this time */
2071 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2072 }
2073
2074 VkResult radv_EnumerateDeviceLayerProperties(
2075 VkPhysicalDevice physicalDevice,
2076 uint32_t* pPropertyCount,
2077 VkLayerProperties* pProperties)
2078 {
2079 if (pProperties == NULL) {
2080 *pPropertyCount = 0;
2081 return VK_SUCCESS;
2082 }
2083
2084 /* None supported at this time */
2085 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2086 }
2087
2088 void radv_GetDeviceQueue2(
2089 VkDevice _device,
2090 const VkDeviceQueueInfo2* pQueueInfo,
2091 VkQueue* pQueue)
2092 {
2093 RADV_FROM_HANDLE(radv_device, device, _device);
2094 struct radv_queue *queue;
2095
2096 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2097 if (pQueueInfo->flags != queue->flags) {
2098 /* From the Vulkan 1.1.70 spec:
2099 *
2100 * "The queue returned by vkGetDeviceQueue2 must have the same
2101 * flags value from this structure as that used at device
2102 * creation time in a VkDeviceQueueCreateInfo instance. If no
2103 * matching flags were specified at device creation time then
2104 * pQueue will return VK_NULL_HANDLE."
2105 */
2106 *pQueue = VK_NULL_HANDLE;
2107 return;
2108 }
2109
2110 *pQueue = radv_queue_to_handle(queue);
2111 }
2112
2113 void radv_GetDeviceQueue(
2114 VkDevice _device,
2115 uint32_t queueFamilyIndex,
2116 uint32_t queueIndex,
2117 VkQueue* pQueue)
2118 {
2119 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2120 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2121 .queueFamilyIndex = queueFamilyIndex,
2122 .queueIndex = queueIndex
2123 };
2124
2125 radv_GetDeviceQueue2(_device, &info, pQueue);
2126 }
2127
2128 static void
2129 fill_geom_tess_rings(struct radv_queue *queue,
2130 uint32_t *map,
2131 bool add_sample_positions,
2132 uint32_t esgs_ring_size,
2133 struct radeon_winsys_bo *esgs_ring_bo,
2134 uint32_t gsvs_ring_size,
2135 struct radeon_winsys_bo *gsvs_ring_bo,
2136 uint32_t tess_factor_ring_size,
2137 uint32_t tess_offchip_ring_offset,
2138 uint32_t tess_offchip_ring_size,
2139 struct radeon_winsys_bo *tess_rings_bo)
2140 {
2141 uint32_t *desc = &map[4];
2142
2143 if (esgs_ring_bo) {
2144 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2145
2146 /* stride 0, num records - size, add tid, swizzle, elsize4,
2147 index stride 64 */
2148 desc[0] = esgs_va;
2149 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2150 S_008F04_STRIDE(0) |
2151 S_008F04_SWIZZLE_ENABLE(true);
2152 desc[2] = esgs_ring_size;
2153 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2154 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2155 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2156 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2157 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2158 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2159 S_008F0C_ELEMENT_SIZE(1) |
2160 S_008F0C_INDEX_STRIDE(3) |
2161 S_008F0C_ADD_TID_ENABLE(true);
2162
2163 /* GS entry for ES->GS ring */
2164 /* stride 0, num records - size, elsize0,
2165 index stride 0 */
2166 desc[4] = esgs_va;
2167 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2168 S_008F04_STRIDE(0) |
2169 S_008F04_SWIZZLE_ENABLE(false);
2170 desc[6] = esgs_ring_size;
2171 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2175 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2176 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2177 S_008F0C_ELEMENT_SIZE(0) |
2178 S_008F0C_INDEX_STRIDE(0) |
2179 S_008F0C_ADD_TID_ENABLE(false);
2180 }
2181
2182 desc += 8;
2183
2184 if (gsvs_ring_bo) {
2185 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2186
2187 /* VS entry for GS->VS ring */
2188 /* stride 0, num records - size, elsize0,
2189 index stride 0 */
2190 desc[0] = gsvs_va;
2191 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2192 S_008F04_STRIDE(0) |
2193 S_008F04_SWIZZLE_ENABLE(false);
2194 desc[2] = gsvs_ring_size;
2195 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2196 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2197 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2198 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2199 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2201 S_008F0C_ELEMENT_SIZE(0) |
2202 S_008F0C_INDEX_STRIDE(0) |
2203 S_008F0C_ADD_TID_ENABLE(false);
2204
2205 /* stride gsvs_itemsize, num records 64
2206 elsize 4, index stride 16 */
2207 /* shader will patch stride and desc[2] */
2208 desc[4] = gsvs_va;
2209 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2210 S_008F04_STRIDE(0) |
2211 S_008F04_SWIZZLE_ENABLE(true);
2212 desc[6] = 0;
2213 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2217 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2218 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2219 S_008F0C_ELEMENT_SIZE(1) |
2220 S_008F0C_INDEX_STRIDE(1) |
2221 S_008F0C_ADD_TID_ENABLE(true);
2222 }
2223
2224 desc += 8;
2225
2226 if (tess_rings_bo) {
2227 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2228 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2229
2230 desc[0] = tess_va;
2231 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2232 S_008F04_STRIDE(0) |
2233 S_008F04_SWIZZLE_ENABLE(false);
2234 desc[2] = tess_factor_ring_size;
2235 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2236 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2237 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2238 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2239 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2241 S_008F0C_ELEMENT_SIZE(0) |
2242 S_008F0C_INDEX_STRIDE(0) |
2243 S_008F0C_ADD_TID_ENABLE(false);
2244
2245 desc[4] = tess_offchip_va;
2246 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2247 S_008F04_STRIDE(0) |
2248 S_008F04_SWIZZLE_ENABLE(false);
2249 desc[6] = tess_offchip_ring_size;
2250 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2254 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2256 S_008F0C_ELEMENT_SIZE(0) |
2257 S_008F0C_INDEX_STRIDE(0) |
2258 S_008F0C_ADD_TID_ENABLE(false);
2259 }
2260
2261 desc += 8;
2262
2263 if (add_sample_positions) {
2264 /* add sample positions after all rings */
2265 memcpy(desc, queue->device->sample_locations_1x, 8);
2266 desc += 2;
2267 memcpy(desc, queue->device->sample_locations_2x, 16);
2268 desc += 4;
2269 memcpy(desc, queue->device->sample_locations_4x, 32);
2270 desc += 8;
2271 memcpy(desc, queue->device->sample_locations_8x, 64);
2272 }
2273 }
2274
2275 static unsigned
2276 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2277 {
2278 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2279 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2280 device->physical_device->rad_info.family != CHIP_STONEY;
2281 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2282 unsigned max_offchip_buffers;
2283 unsigned offchip_granularity;
2284 unsigned hs_offchip_param;
2285
2286 /*
2287 * Per RadeonSI:
2288 * This must be one less than the maximum number due to a hw limitation.
2289 * Various hardware bugs need thGFX7
2290 *
2291 * Per AMDVLK:
2292 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2293 * Gfx7 should limit max_offchip_buffers to 508
2294 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2295 *
2296 * Follow AMDVLK here.
2297 */
2298 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2299 device->physical_device->rad_info.chip_class == GFX7 ||
2300 device->physical_device->rad_info.chip_class == GFX6)
2301 --max_offchip_buffers_per_se;
2302
2303 max_offchip_buffers = max_offchip_buffers_per_se *
2304 device->physical_device->rad_info.max_se;
2305
2306 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2307 * around by setting 4K granularity.
2308 */
2309 if (device->tess_offchip_block_dw_size == 4096) {
2310 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2311 offchip_granularity = V_03093C_X_4K_DWORDS;
2312 } else {
2313 assert(device->tess_offchip_block_dw_size == 8192);
2314 offchip_granularity = V_03093C_X_8K_DWORDS;
2315 }
2316
2317 switch (device->physical_device->rad_info.chip_class) {
2318 case GFX6:
2319 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2320 break;
2321 case GFX7:
2322 case GFX8:
2323 case GFX9:
2324 default:
2325 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2326 break;
2327 }
2328
2329 *max_offchip_buffers_p = max_offchip_buffers;
2330 if (device->physical_device->rad_info.chip_class >= GFX7) {
2331 if (device->physical_device->rad_info.chip_class >= GFX8)
2332 --max_offchip_buffers;
2333 hs_offchip_param =
2334 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2335 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2336 } else {
2337 hs_offchip_param =
2338 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2339 }
2340 return hs_offchip_param;
2341 }
2342
2343 static void
2344 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2345 struct radeon_winsys_bo *esgs_ring_bo,
2346 uint32_t esgs_ring_size,
2347 struct radeon_winsys_bo *gsvs_ring_bo,
2348 uint32_t gsvs_ring_size)
2349 {
2350 if (!esgs_ring_bo && !gsvs_ring_bo)
2351 return;
2352
2353 if (esgs_ring_bo)
2354 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2355
2356 if (gsvs_ring_bo)
2357 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2358
2359 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2360 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2361 radeon_emit(cs, esgs_ring_size >> 8);
2362 radeon_emit(cs, gsvs_ring_size >> 8);
2363 } else {
2364 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2365 radeon_emit(cs, esgs_ring_size >> 8);
2366 radeon_emit(cs, gsvs_ring_size >> 8);
2367 }
2368 }
2369
2370 static void
2371 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2372 unsigned hs_offchip_param, unsigned tf_ring_size,
2373 struct radeon_winsys_bo *tess_rings_bo)
2374 {
2375 uint64_t tf_va;
2376
2377 if (!tess_rings_bo)
2378 return;
2379
2380 tf_va = radv_buffer_get_va(tess_rings_bo);
2381
2382 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2383
2384 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2385 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2386 S_030938_SIZE(tf_ring_size / 4));
2387 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2388 tf_va >> 8);
2389 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2390 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2391 S_030944_BASE_HI(tf_va >> 40));
2392 }
2393 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2394 hs_offchip_param);
2395 } else {
2396 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2397 S_008988_SIZE(tf_ring_size / 4));
2398 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2399 tf_va >> 8);
2400 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2401 hs_offchip_param);
2402 }
2403 }
2404
2405 static void
2406 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2407 struct radeon_winsys_bo *compute_scratch_bo)
2408 {
2409 uint64_t scratch_va;
2410
2411 if (!compute_scratch_bo)
2412 return;
2413
2414 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2415
2416 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2417
2418 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2419 radeon_emit(cs, scratch_va);
2420 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2421 S_008F04_SWIZZLE_ENABLE(1));
2422 }
2423
2424 static void
2425 radv_emit_global_shader_pointers(struct radv_queue *queue,
2426 struct radeon_cmdbuf *cs,
2427 struct radeon_winsys_bo *descriptor_bo)
2428 {
2429 uint64_t va;
2430
2431 if (!descriptor_bo)
2432 return;
2433
2434 va = radv_buffer_get_va(descriptor_bo);
2435
2436 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2437
2438 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2439 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2440 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2441 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2442 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2443
2444 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2445 radv_emit_shader_pointer(queue->device, cs, regs[i],
2446 va, true);
2447 }
2448 } else {
2449 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2450 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2451 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2452 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2453 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2454 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2455
2456 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2457 radv_emit_shader_pointer(queue->device, cs, regs[i],
2458 va, true);
2459 }
2460 }
2461 }
2462
2463 static void
2464 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2465 {
2466 struct radv_device *device = queue->device;
2467
2468 if (device->gfx_init) {
2469 uint64_t va = radv_buffer_get_va(device->gfx_init);
2470
2471 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2472 radeon_emit(cs, va);
2473 radeon_emit(cs, va >> 32);
2474 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2475
2476 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2477 } else {
2478 struct radv_physical_device *physical_device = device->physical_device;
2479 si_emit_graphics(physical_device, cs);
2480 }
2481 }
2482
2483 static void
2484 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2485 {
2486 struct radv_physical_device *physical_device = queue->device->physical_device;
2487 si_emit_compute(physical_device, cs);
2488 }
2489
2490 static VkResult
2491 radv_get_preamble_cs(struct radv_queue *queue,
2492 uint32_t scratch_size,
2493 uint32_t compute_scratch_size,
2494 uint32_t esgs_ring_size,
2495 uint32_t gsvs_ring_size,
2496 bool needs_tess_rings,
2497 bool needs_sample_positions,
2498 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2499 struct radeon_cmdbuf **initial_preamble_cs,
2500 struct radeon_cmdbuf **continue_preamble_cs)
2501 {
2502 struct radeon_winsys_bo *scratch_bo = NULL;
2503 struct radeon_winsys_bo *descriptor_bo = NULL;
2504 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2505 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2506 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2507 struct radeon_winsys_bo *tess_rings_bo = NULL;
2508 struct radeon_cmdbuf *dest_cs[3] = {0};
2509 bool add_tess_rings = false, add_sample_positions = false;
2510 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2511 unsigned max_offchip_buffers;
2512 unsigned hs_offchip_param = 0;
2513 unsigned tess_offchip_ring_offset;
2514 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2515 if (!queue->has_tess_rings) {
2516 if (needs_tess_rings)
2517 add_tess_rings = true;
2518 }
2519 if (!queue->has_sample_positions) {
2520 if (needs_sample_positions)
2521 add_sample_positions = true;
2522 }
2523 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2524 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2525 &max_offchip_buffers);
2526 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2527 tess_offchip_ring_size = max_offchip_buffers *
2528 queue->device->tess_offchip_block_dw_size * 4;
2529
2530 if (scratch_size <= queue->scratch_size &&
2531 compute_scratch_size <= queue->compute_scratch_size &&
2532 esgs_ring_size <= queue->esgs_ring_size &&
2533 gsvs_ring_size <= queue->gsvs_ring_size &&
2534 !add_tess_rings && !add_sample_positions &&
2535 queue->initial_preamble_cs) {
2536 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2537 *initial_preamble_cs = queue->initial_preamble_cs;
2538 *continue_preamble_cs = queue->continue_preamble_cs;
2539 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2540 *continue_preamble_cs = NULL;
2541 return VK_SUCCESS;
2542 }
2543
2544 if (scratch_size > queue->scratch_size) {
2545 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2546 scratch_size,
2547 4096,
2548 RADEON_DOMAIN_VRAM,
2549 ring_bo_flags,
2550 RADV_BO_PRIORITY_SCRATCH);
2551 if (!scratch_bo)
2552 goto fail;
2553 } else
2554 scratch_bo = queue->scratch_bo;
2555
2556 if (compute_scratch_size > queue->compute_scratch_size) {
2557 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2558 compute_scratch_size,
2559 4096,
2560 RADEON_DOMAIN_VRAM,
2561 ring_bo_flags,
2562 RADV_BO_PRIORITY_SCRATCH);
2563 if (!compute_scratch_bo)
2564 goto fail;
2565
2566 } else
2567 compute_scratch_bo = queue->compute_scratch_bo;
2568
2569 if (esgs_ring_size > queue->esgs_ring_size) {
2570 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2571 esgs_ring_size,
2572 4096,
2573 RADEON_DOMAIN_VRAM,
2574 ring_bo_flags,
2575 RADV_BO_PRIORITY_SCRATCH);
2576 if (!esgs_ring_bo)
2577 goto fail;
2578 } else {
2579 esgs_ring_bo = queue->esgs_ring_bo;
2580 esgs_ring_size = queue->esgs_ring_size;
2581 }
2582
2583 if (gsvs_ring_size > queue->gsvs_ring_size) {
2584 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2585 gsvs_ring_size,
2586 4096,
2587 RADEON_DOMAIN_VRAM,
2588 ring_bo_flags,
2589 RADV_BO_PRIORITY_SCRATCH);
2590 if (!gsvs_ring_bo)
2591 goto fail;
2592 } else {
2593 gsvs_ring_bo = queue->gsvs_ring_bo;
2594 gsvs_ring_size = queue->gsvs_ring_size;
2595 }
2596
2597 if (add_tess_rings) {
2598 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2599 tess_offchip_ring_offset + tess_offchip_ring_size,
2600 256,
2601 RADEON_DOMAIN_VRAM,
2602 ring_bo_flags,
2603 RADV_BO_PRIORITY_SCRATCH);
2604 if (!tess_rings_bo)
2605 goto fail;
2606 } else {
2607 tess_rings_bo = queue->tess_rings_bo;
2608 }
2609
2610 if (scratch_bo != queue->scratch_bo ||
2611 esgs_ring_bo != queue->esgs_ring_bo ||
2612 gsvs_ring_bo != queue->gsvs_ring_bo ||
2613 tess_rings_bo != queue->tess_rings_bo ||
2614 add_sample_positions) {
2615 uint32_t size = 0;
2616 if (gsvs_ring_bo || esgs_ring_bo ||
2617 tess_rings_bo || add_sample_positions) {
2618 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2619 if (add_sample_positions)
2620 size += 128; /* 64+32+16+8 = 120 bytes */
2621 }
2622 else if (scratch_bo)
2623 size = 8; /* 2 dword */
2624
2625 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2626 size,
2627 4096,
2628 RADEON_DOMAIN_VRAM,
2629 RADEON_FLAG_CPU_ACCESS |
2630 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2631 RADEON_FLAG_READ_ONLY,
2632 RADV_BO_PRIORITY_DESCRIPTOR);
2633 if (!descriptor_bo)
2634 goto fail;
2635 } else
2636 descriptor_bo = queue->descriptor_bo;
2637
2638 if (descriptor_bo != queue->descriptor_bo) {
2639 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2640
2641 if (scratch_bo) {
2642 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2643 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2644 S_008F04_SWIZZLE_ENABLE(1);
2645 map[0] = scratch_va;
2646 map[1] = rsrc1;
2647 }
2648
2649 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2650 fill_geom_tess_rings(queue, map, add_sample_positions,
2651 esgs_ring_size, esgs_ring_bo,
2652 gsvs_ring_size, gsvs_ring_bo,
2653 tess_factor_ring_size,
2654 tess_offchip_ring_offset,
2655 tess_offchip_ring_size,
2656 tess_rings_bo);
2657
2658 queue->device->ws->buffer_unmap(descriptor_bo);
2659 }
2660
2661 for(int i = 0; i < 3; ++i) {
2662 struct radeon_cmdbuf *cs = NULL;
2663 cs = queue->device->ws->cs_create(queue->device->ws,
2664 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2665 if (!cs)
2666 goto fail;
2667
2668 dest_cs[i] = cs;
2669
2670 if (scratch_bo)
2671 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2672
2673 /* Emit initial configuration. */
2674 switch (queue->queue_family_index) {
2675 case RADV_QUEUE_GENERAL:
2676 radv_init_graphics_state(cs, queue);
2677 break;
2678 case RADV_QUEUE_COMPUTE:
2679 radv_init_compute_state(cs, queue);
2680 break;
2681 case RADV_QUEUE_TRANSFER:
2682 break;
2683 }
2684
2685 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2686 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2687 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2688 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2689 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2690 }
2691
2692 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2693 gsvs_ring_bo, gsvs_ring_size);
2694 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2695 tess_factor_ring_size, tess_rings_bo);
2696 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2697 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2698
2699 if (i == 0) {
2700 si_cs_emit_cache_flush(cs,
2701 queue->device->physical_device->rad_info.chip_class,
2702 NULL, 0,
2703 queue->queue_family_index == RING_COMPUTE &&
2704 queue->device->physical_device->rad_info.chip_class >= GFX7,
2705 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2706 RADV_CMD_FLAG_INV_ICACHE |
2707 RADV_CMD_FLAG_INV_SCACHE |
2708 RADV_CMD_FLAG_INV_VCACHE |
2709 RADV_CMD_FLAG_INV_L2 |
2710 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2711 } else if (i == 1) {
2712 si_cs_emit_cache_flush(cs,
2713 queue->device->physical_device->rad_info.chip_class,
2714 NULL, 0,
2715 queue->queue_family_index == RING_COMPUTE &&
2716 queue->device->physical_device->rad_info.chip_class >= GFX7,
2717 RADV_CMD_FLAG_INV_ICACHE |
2718 RADV_CMD_FLAG_INV_SCACHE |
2719 RADV_CMD_FLAG_INV_VCACHE |
2720 RADV_CMD_FLAG_INV_L2 |
2721 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2722 }
2723
2724 if (!queue->device->ws->cs_finalize(cs))
2725 goto fail;
2726 }
2727
2728 if (queue->initial_full_flush_preamble_cs)
2729 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2730
2731 if (queue->initial_preamble_cs)
2732 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2733
2734 if (queue->continue_preamble_cs)
2735 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2736
2737 queue->initial_full_flush_preamble_cs = dest_cs[0];
2738 queue->initial_preamble_cs = dest_cs[1];
2739 queue->continue_preamble_cs = dest_cs[2];
2740
2741 if (scratch_bo != queue->scratch_bo) {
2742 if (queue->scratch_bo)
2743 queue->device->ws->buffer_destroy(queue->scratch_bo);
2744 queue->scratch_bo = scratch_bo;
2745 queue->scratch_size = scratch_size;
2746 }
2747
2748 if (compute_scratch_bo != queue->compute_scratch_bo) {
2749 if (queue->compute_scratch_bo)
2750 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2751 queue->compute_scratch_bo = compute_scratch_bo;
2752 queue->compute_scratch_size = compute_scratch_size;
2753 }
2754
2755 if (esgs_ring_bo != queue->esgs_ring_bo) {
2756 if (queue->esgs_ring_bo)
2757 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2758 queue->esgs_ring_bo = esgs_ring_bo;
2759 queue->esgs_ring_size = esgs_ring_size;
2760 }
2761
2762 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2763 if (queue->gsvs_ring_bo)
2764 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2765 queue->gsvs_ring_bo = gsvs_ring_bo;
2766 queue->gsvs_ring_size = gsvs_ring_size;
2767 }
2768
2769 if (tess_rings_bo != queue->tess_rings_bo) {
2770 queue->tess_rings_bo = tess_rings_bo;
2771 queue->has_tess_rings = true;
2772 }
2773
2774 if (descriptor_bo != queue->descriptor_bo) {
2775 if (queue->descriptor_bo)
2776 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2777
2778 queue->descriptor_bo = descriptor_bo;
2779 }
2780
2781 if (add_sample_positions)
2782 queue->has_sample_positions = true;
2783
2784 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2785 *initial_preamble_cs = queue->initial_preamble_cs;
2786 *continue_preamble_cs = queue->continue_preamble_cs;
2787 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2788 *continue_preamble_cs = NULL;
2789 return VK_SUCCESS;
2790 fail:
2791 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2792 if (dest_cs[i])
2793 queue->device->ws->cs_destroy(dest_cs[i]);
2794 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2795 queue->device->ws->buffer_destroy(descriptor_bo);
2796 if (scratch_bo && scratch_bo != queue->scratch_bo)
2797 queue->device->ws->buffer_destroy(scratch_bo);
2798 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2799 queue->device->ws->buffer_destroy(compute_scratch_bo);
2800 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2801 queue->device->ws->buffer_destroy(esgs_ring_bo);
2802 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2803 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2804 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2805 queue->device->ws->buffer_destroy(tess_rings_bo);
2806 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2807 }
2808
2809 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2810 struct radv_winsys_sem_counts *counts,
2811 int num_sems,
2812 const VkSemaphore *sems,
2813 VkFence _fence,
2814 bool reset_temp)
2815 {
2816 int syncobj_idx = 0, sem_idx = 0;
2817
2818 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2819 return VK_SUCCESS;
2820
2821 for (uint32_t i = 0; i < num_sems; i++) {
2822 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2823
2824 if (sem->temp_syncobj || sem->syncobj)
2825 counts->syncobj_count++;
2826 else
2827 counts->sem_count++;
2828 }
2829
2830 if (_fence != VK_NULL_HANDLE) {
2831 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2832 if (fence->temp_syncobj || fence->syncobj)
2833 counts->syncobj_count++;
2834 }
2835
2836 if (counts->syncobj_count) {
2837 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2838 if (!counts->syncobj)
2839 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2840 }
2841
2842 if (counts->sem_count) {
2843 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2844 if (!counts->sem) {
2845 free(counts->syncobj);
2846 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2847 }
2848 }
2849
2850 for (uint32_t i = 0; i < num_sems; i++) {
2851 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2852
2853 if (sem->temp_syncobj) {
2854 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2855 }
2856 else if (sem->syncobj)
2857 counts->syncobj[syncobj_idx++] = sem->syncobj;
2858 else {
2859 assert(sem->sem);
2860 counts->sem[sem_idx++] = sem->sem;
2861 }
2862 }
2863
2864 if (_fence != VK_NULL_HANDLE) {
2865 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2866 if (fence->temp_syncobj)
2867 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2868 else if (fence->syncobj)
2869 counts->syncobj[syncobj_idx++] = fence->syncobj;
2870 }
2871
2872 return VK_SUCCESS;
2873 }
2874
2875 static void
2876 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2877 {
2878 free(sem_info->wait.syncobj);
2879 free(sem_info->wait.sem);
2880 free(sem_info->signal.syncobj);
2881 free(sem_info->signal.sem);
2882 }
2883
2884
2885 static void radv_free_temp_syncobjs(struct radv_device *device,
2886 int num_sems,
2887 const VkSemaphore *sems)
2888 {
2889 for (uint32_t i = 0; i < num_sems; i++) {
2890 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2891
2892 if (sem->temp_syncobj) {
2893 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2894 sem->temp_syncobj = 0;
2895 }
2896 }
2897 }
2898
2899 static VkResult
2900 radv_alloc_sem_info(struct radv_instance *instance,
2901 struct radv_winsys_sem_info *sem_info,
2902 int num_wait_sems,
2903 const VkSemaphore *wait_sems,
2904 int num_signal_sems,
2905 const VkSemaphore *signal_sems,
2906 VkFence fence)
2907 {
2908 VkResult ret;
2909 memset(sem_info, 0, sizeof(*sem_info));
2910
2911 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2912 if (ret)
2913 return ret;
2914 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2915 if (ret)
2916 radv_free_sem_info(sem_info);
2917
2918 /* caller can override these */
2919 sem_info->cs_emit_wait = true;
2920 sem_info->cs_emit_signal = true;
2921 return ret;
2922 }
2923
2924 /* Signals fence as soon as all the work currently put on queue is done. */
2925 static VkResult radv_signal_fence(struct radv_queue *queue,
2926 struct radv_fence *fence)
2927 {
2928 int ret;
2929 VkResult result;
2930 struct radv_winsys_sem_info sem_info;
2931
2932 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2933 radv_fence_to_handle(fence));
2934 if (result != VK_SUCCESS)
2935 return result;
2936
2937 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2938 &queue->device->empty_cs[queue->queue_family_index],
2939 1, NULL, NULL, &sem_info, NULL,
2940 false, fence->fence);
2941 radv_free_sem_info(&sem_info);
2942
2943 if (ret)
2944 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2945
2946 return VK_SUCCESS;
2947 }
2948
2949 VkResult radv_QueueSubmit(
2950 VkQueue _queue,
2951 uint32_t submitCount,
2952 const VkSubmitInfo* pSubmits,
2953 VkFence _fence)
2954 {
2955 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2956 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2957 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2958 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2959 int ret;
2960 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2961 uint32_t scratch_size = 0;
2962 uint32_t compute_scratch_size = 0;
2963 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2964 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2965 VkResult result;
2966 bool fence_emitted = false;
2967 bool tess_rings_needed = false;
2968 bool sample_positions_needed = false;
2969
2970 /* Do this first so failing to allocate scratch buffers can't result in
2971 * partially executed submissions. */
2972 for (uint32_t i = 0; i < submitCount; i++) {
2973 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2975 pSubmits[i].pCommandBuffers[j]);
2976
2977 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2978 compute_scratch_size = MAX2(compute_scratch_size,
2979 cmd_buffer->compute_scratch_size_needed);
2980 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2981 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2982 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2983 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2984 }
2985 }
2986
2987 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2988 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2989 sample_positions_needed, &initial_flush_preamble_cs,
2990 &initial_preamble_cs, &continue_preamble_cs);
2991 if (result != VK_SUCCESS)
2992 return result;
2993
2994 for (uint32_t i = 0; i < submitCount; i++) {
2995 struct radeon_cmdbuf **cs_array;
2996 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2997 bool can_patch = true;
2998 uint32_t advance;
2999 struct radv_winsys_sem_info sem_info;
3000
3001 result = radv_alloc_sem_info(queue->device->instance,
3002 &sem_info,
3003 pSubmits[i].waitSemaphoreCount,
3004 pSubmits[i].pWaitSemaphores,
3005 pSubmits[i].signalSemaphoreCount,
3006 pSubmits[i].pSignalSemaphores,
3007 _fence);
3008 if (result != VK_SUCCESS)
3009 return result;
3010
3011 if (!pSubmits[i].commandBufferCount) {
3012 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3013 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3014 &queue->device->empty_cs[queue->queue_family_index],
3015 1, NULL, NULL,
3016 &sem_info, NULL,
3017 false, base_fence);
3018 if (ret) {
3019 radv_loge("failed to submit CS %d\n", i);
3020 abort();
3021 }
3022 fence_emitted = true;
3023 }
3024 radv_free_sem_info(&sem_info);
3025 continue;
3026 }
3027
3028 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3029 (pSubmits[i].commandBufferCount));
3030
3031 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3033 pSubmits[i].pCommandBuffers[j]);
3034 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3035
3036 cs_array[j] = cmd_buffer->cs;
3037 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3038 can_patch = false;
3039
3040 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3041 }
3042
3043 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3044 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3045 const struct radv_winsys_bo_list *bo_list = NULL;
3046
3047 advance = MIN2(max_cs_submission,
3048 pSubmits[i].commandBufferCount - j);
3049
3050 if (queue->device->trace_bo)
3051 *queue->device->trace_id_ptr = 0;
3052
3053 sem_info.cs_emit_wait = j == 0;
3054 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3055
3056 if (unlikely(queue->device->use_global_bo_list)) {
3057 pthread_mutex_lock(&queue->device->bo_list.mutex);
3058 bo_list = &queue->device->bo_list.list;
3059 }
3060
3061 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3062 advance, initial_preamble, continue_preamble_cs,
3063 &sem_info, bo_list,
3064 can_patch, base_fence);
3065
3066 if (unlikely(queue->device->use_global_bo_list))
3067 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3068
3069 if (ret) {
3070 radv_loge("failed to submit CS %d\n", i);
3071 abort();
3072 }
3073 fence_emitted = true;
3074 if (queue->device->trace_bo) {
3075 radv_check_gpu_hangs(queue, cs_array[j]);
3076 }
3077 }
3078
3079 radv_free_temp_syncobjs(queue->device,
3080 pSubmits[i].waitSemaphoreCount,
3081 pSubmits[i].pWaitSemaphores);
3082 radv_free_sem_info(&sem_info);
3083 free(cs_array);
3084 }
3085
3086 if (fence) {
3087 if (!fence_emitted) {
3088 result = radv_signal_fence(queue, fence);
3089 if (result != VK_SUCCESS)
3090 return result;
3091 }
3092 }
3093
3094 return VK_SUCCESS;
3095 }
3096
3097 VkResult radv_QueueWaitIdle(
3098 VkQueue _queue)
3099 {
3100 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3101
3102 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3103 radv_queue_family_to_ring(queue->queue_family_index),
3104 queue->queue_idx);
3105 return VK_SUCCESS;
3106 }
3107
3108 VkResult radv_DeviceWaitIdle(
3109 VkDevice _device)
3110 {
3111 RADV_FROM_HANDLE(radv_device, device, _device);
3112
3113 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3114 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3115 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3116 }
3117 }
3118 return VK_SUCCESS;
3119 }
3120
3121 VkResult radv_EnumerateInstanceExtensionProperties(
3122 const char* pLayerName,
3123 uint32_t* pPropertyCount,
3124 VkExtensionProperties* pProperties)
3125 {
3126 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3127
3128 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3129 if (radv_supported_instance_extensions.extensions[i]) {
3130 vk_outarray_append(&out, prop) {
3131 *prop = radv_instance_extensions[i];
3132 }
3133 }
3134 }
3135
3136 return vk_outarray_status(&out);
3137 }
3138
3139 VkResult radv_EnumerateDeviceExtensionProperties(
3140 VkPhysicalDevice physicalDevice,
3141 const char* pLayerName,
3142 uint32_t* pPropertyCount,
3143 VkExtensionProperties* pProperties)
3144 {
3145 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3146 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3147
3148 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3149 if (device->supported_extensions.extensions[i]) {
3150 vk_outarray_append(&out, prop) {
3151 *prop = radv_device_extensions[i];
3152 }
3153 }
3154 }
3155
3156 return vk_outarray_status(&out);
3157 }
3158
3159 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3160 VkInstance _instance,
3161 const char* pName)
3162 {
3163 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3164
3165 return radv_lookup_entrypoint_checked(pName,
3166 instance ? instance->apiVersion : 0,
3167 instance ? &instance->enabled_extensions : NULL,
3168 NULL);
3169 }
3170
3171 /* The loader wants us to expose a second GetInstanceProcAddr function
3172 * to work around certain LD_PRELOAD issues seen in apps.
3173 */
3174 PUBLIC
3175 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3176 VkInstance instance,
3177 const char* pName);
3178
3179 PUBLIC
3180 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3181 VkInstance instance,
3182 const char* pName)
3183 {
3184 return radv_GetInstanceProcAddr(instance, pName);
3185 }
3186
3187 PUBLIC
3188 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3189 VkInstance _instance,
3190 const char* pName);
3191
3192 PUBLIC
3193 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3194 VkInstance _instance,
3195 const char* pName)
3196 {
3197 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3198
3199 return radv_lookup_physical_device_entrypoint_checked(pName,
3200 instance ? instance->apiVersion : 0,
3201 instance ? &instance->enabled_extensions : NULL);
3202 }
3203
3204 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3205 VkDevice _device,
3206 const char* pName)
3207 {
3208 RADV_FROM_HANDLE(radv_device, device, _device);
3209
3210 return radv_lookup_entrypoint_checked(pName,
3211 device->instance->apiVersion,
3212 &device->instance->enabled_extensions,
3213 &device->enabled_extensions);
3214 }
3215
3216 bool radv_get_memory_fd(struct radv_device *device,
3217 struct radv_device_memory *memory,
3218 int *pFD)
3219 {
3220 struct radeon_bo_metadata metadata;
3221
3222 if (memory->image) {
3223 radv_init_metadata(device, memory->image, &metadata);
3224 device->ws->buffer_set_metadata(memory->bo, &metadata);
3225 }
3226
3227 return device->ws->buffer_get_fd(device->ws, memory->bo,
3228 pFD);
3229 }
3230
3231 static VkResult radv_alloc_memory(struct radv_device *device,
3232 const VkMemoryAllocateInfo* pAllocateInfo,
3233 const VkAllocationCallbacks* pAllocator,
3234 VkDeviceMemory* pMem)
3235 {
3236 struct radv_device_memory *mem;
3237 VkResult result;
3238 enum radeon_bo_domain domain;
3239 uint32_t flags = 0;
3240 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3241
3242 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3243
3244 if (pAllocateInfo->allocationSize == 0) {
3245 /* Apparently, this is allowed */
3246 *pMem = VK_NULL_HANDLE;
3247 return VK_SUCCESS;
3248 }
3249
3250 const VkImportMemoryFdInfoKHR *import_info =
3251 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3252 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3253 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3254 const VkExportMemoryAllocateInfo *export_info =
3255 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3256 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3257 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3258
3259 const struct wsi_memory_allocate_info *wsi_info =
3260 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3261
3262 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3264 if (mem == NULL)
3265 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3266
3267 if (wsi_info && wsi_info->implicit_sync)
3268 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3269
3270 if (dedicate_info) {
3271 mem->image = radv_image_from_handle(dedicate_info->image);
3272 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3273 } else {
3274 mem->image = NULL;
3275 mem->buffer = NULL;
3276 }
3277
3278 float priority_float = 0.5;
3279 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3280 vk_find_struct_const(pAllocateInfo->pNext,
3281 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3282 if (priority_ext)
3283 priority_float = priority_ext->priority;
3284
3285 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3286 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3287
3288 mem->user_ptr = NULL;
3289
3290 if (import_info) {
3291 assert(import_info->handleType ==
3292 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3293 import_info->handleType ==
3294 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3295 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3296 priority, NULL, NULL);
3297 if (!mem->bo) {
3298 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3299 goto fail;
3300 } else {
3301 close(import_info->fd);
3302 }
3303 } else if (host_ptr_info) {
3304 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3305 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3306 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3307 pAllocateInfo->allocationSize,
3308 priority);
3309 if (!mem->bo) {
3310 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3311 goto fail;
3312 } else {
3313 mem->user_ptr = host_ptr_info->pHostPointer;
3314 }
3315 } else {
3316 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3317 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3318 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3319 domain = RADEON_DOMAIN_GTT;
3320 else
3321 domain = RADEON_DOMAIN_VRAM;
3322
3323 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3324 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3325 else
3326 flags |= RADEON_FLAG_CPU_ACCESS;
3327
3328 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3329 flags |= RADEON_FLAG_GTT_WC;
3330
3331 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3332 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3333 if (device->use_global_bo_list) {
3334 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3335 }
3336 }
3337
3338 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3339 domain, flags, priority);
3340
3341 if (!mem->bo) {
3342 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3343 goto fail;
3344 }
3345 mem->type_index = mem_type_index;
3346 }
3347
3348 result = radv_bo_list_add(device, mem->bo);
3349 if (result != VK_SUCCESS)
3350 goto fail_bo;
3351
3352 *pMem = radv_device_memory_to_handle(mem);
3353
3354 return VK_SUCCESS;
3355
3356 fail_bo:
3357 device->ws->buffer_destroy(mem->bo);
3358 fail:
3359 vk_free2(&device->alloc, pAllocator, mem);
3360
3361 return result;
3362 }
3363
3364 VkResult radv_AllocateMemory(
3365 VkDevice _device,
3366 const VkMemoryAllocateInfo* pAllocateInfo,
3367 const VkAllocationCallbacks* pAllocator,
3368 VkDeviceMemory* pMem)
3369 {
3370 RADV_FROM_HANDLE(radv_device, device, _device);
3371 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3372 }
3373
3374 void radv_FreeMemory(
3375 VkDevice _device,
3376 VkDeviceMemory _mem,
3377 const VkAllocationCallbacks* pAllocator)
3378 {
3379 RADV_FROM_HANDLE(radv_device, device, _device);
3380 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3381
3382 if (mem == NULL)
3383 return;
3384
3385 radv_bo_list_remove(device, mem->bo);
3386 device->ws->buffer_destroy(mem->bo);
3387 mem->bo = NULL;
3388
3389 vk_free2(&device->alloc, pAllocator, mem);
3390 }
3391
3392 VkResult radv_MapMemory(
3393 VkDevice _device,
3394 VkDeviceMemory _memory,
3395 VkDeviceSize offset,
3396 VkDeviceSize size,
3397 VkMemoryMapFlags flags,
3398 void** ppData)
3399 {
3400 RADV_FROM_HANDLE(radv_device, device, _device);
3401 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3402
3403 if (mem == NULL) {
3404 *ppData = NULL;
3405 return VK_SUCCESS;
3406 }
3407
3408 if (mem->user_ptr)
3409 *ppData = mem->user_ptr;
3410 else
3411 *ppData = device->ws->buffer_map(mem->bo);
3412
3413 if (*ppData) {
3414 *ppData += offset;
3415 return VK_SUCCESS;
3416 }
3417
3418 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3419 }
3420
3421 void radv_UnmapMemory(
3422 VkDevice _device,
3423 VkDeviceMemory _memory)
3424 {
3425 RADV_FROM_HANDLE(radv_device, device, _device);
3426 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3427
3428 if (mem == NULL)
3429 return;
3430
3431 if (mem->user_ptr == NULL)
3432 device->ws->buffer_unmap(mem->bo);
3433 }
3434
3435 VkResult radv_FlushMappedMemoryRanges(
3436 VkDevice _device,
3437 uint32_t memoryRangeCount,
3438 const VkMappedMemoryRange* pMemoryRanges)
3439 {
3440 return VK_SUCCESS;
3441 }
3442
3443 VkResult radv_InvalidateMappedMemoryRanges(
3444 VkDevice _device,
3445 uint32_t memoryRangeCount,
3446 const VkMappedMemoryRange* pMemoryRanges)
3447 {
3448 return VK_SUCCESS;
3449 }
3450
3451 void radv_GetBufferMemoryRequirements(
3452 VkDevice _device,
3453 VkBuffer _buffer,
3454 VkMemoryRequirements* pMemoryRequirements)
3455 {
3456 RADV_FROM_HANDLE(radv_device, device, _device);
3457 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3458
3459 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3460
3461 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3462 pMemoryRequirements->alignment = 4096;
3463 else
3464 pMemoryRequirements->alignment = 16;
3465
3466 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3467 }
3468
3469 void radv_GetBufferMemoryRequirements2(
3470 VkDevice device,
3471 const VkBufferMemoryRequirementsInfo2 *pInfo,
3472 VkMemoryRequirements2 *pMemoryRequirements)
3473 {
3474 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3475 &pMemoryRequirements->memoryRequirements);
3476 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3477 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3478 switch (ext->sType) {
3479 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3480 VkMemoryDedicatedRequirements *req =
3481 (VkMemoryDedicatedRequirements *) ext;
3482 req->requiresDedicatedAllocation = buffer->shareable;
3483 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3484 break;
3485 }
3486 default:
3487 break;
3488 }
3489 }
3490 }
3491
3492 void radv_GetImageMemoryRequirements(
3493 VkDevice _device,
3494 VkImage _image,
3495 VkMemoryRequirements* pMemoryRequirements)
3496 {
3497 RADV_FROM_HANDLE(radv_device, device, _device);
3498 RADV_FROM_HANDLE(radv_image, image, _image);
3499
3500 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3501
3502 pMemoryRequirements->size = image->size;
3503 pMemoryRequirements->alignment = image->alignment;
3504 }
3505
3506 void radv_GetImageMemoryRequirements2(
3507 VkDevice device,
3508 const VkImageMemoryRequirementsInfo2 *pInfo,
3509 VkMemoryRequirements2 *pMemoryRequirements)
3510 {
3511 radv_GetImageMemoryRequirements(device, pInfo->image,
3512 &pMemoryRequirements->memoryRequirements);
3513
3514 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3515
3516 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3517 switch (ext->sType) {
3518 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3519 VkMemoryDedicatedRequirements *req =
3520 (VkMemoryDedicatedRequirements *) ext;
3521 req->requiresDedicatedAllocation = image->shareable;
3522 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3523 break;
3524 }
3525 default:
3526 break;
3527 }
3528 }
3529 }
3530
3531 void radv_GetImageSparseMemoryRequirements(
3532 VkDevice device,
3533 VkImage image,
3534 uint32_t* pSparseMemoryRequirementCount,
3535 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3536 {
3537 stub();
3538 }
3539
3540 void radv_GetImageSparseMemoryRequirements2(
3541 VkDevice device,
3542 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3543 uint32_t* pSparseMemoryRequirementCount,
3544 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3545 {
3546 stub();
3547 }
3548
3549 void radv_GetDeviceMemoryCommitment(
3550 VkDevice device,
3551 VkDeviceMemory memory,
3552 VkDeviceSize* pCommittedMemoryInBytes)
3553 {
3554 *pCommittedMemoryInBytes = 0;
3555 }
3556
3557 VkResult radv_BindBufferMemory2(VkDevice device,
3558 uint32_t bindInfoCount,
3559 const VkBindBufferMemoryInfo *pBindInfos)
3560 {
3561 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3562 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3563 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3564
3565 if (mem) {
3566 buffer->bo = mem->bo;
3567 buffer->offset = pBindInfos[i].memoryOffset;
3568 } else {
3569 buffer->bo = NULL;
3570 }
3571 }
3572 return VK_SUCCESS;
3573 }
3574
3575 VkResult radv_BindBufferMemory(
3576 VkDevice device,
3577 VkBuffer buffer,
3578 VkDeviceMemory memory,
3579 VkDeviceSize memoryOffset)
3580 {
3581 const VkBindBufferMemoryInfo info = {
3582 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3583 .buffer = buffer,
3584 .memory = memory,
3585 .memoryOffset = memoryOffset
3586 };
3587
3588 return radv_BindBufferMemory2(device, 1, &info);
3589 }
3590
3591 VkResult radv_BindImageMemory2(VkDevice device,
3592 uint32_t bindInfoCount,
3593 const VkBindImageMemoryInfo *pBindInfos)
3594 {
3595 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3596 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3597 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3598
3599 if (mem) {
3600 image->bo = mem->bo;
3601 image->offset = pBindInfos[i].memoryOffset;
3602 } else {
3603 image->bo = NULL;
3604 image->offset = 0;
3605 }
3606 }
3607 return VK_SUCCESS;
3608 }
3609
3610
3611 VkResult radv_BindImageMemory(
3612 VkDevice device,
3613 VkImage image,
3614 VkDeviceMemory memory,
3615 VkDeviceSize memoryOffset)
3616 {
3617 const VkBindImageMemoryInfo info = {
3618 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3619 .image = image,
3620 .memory = memory,
3621 .memoryOffset = memoryOffset
3622 };
3623
3624 return radv_BindImageMemory2(device, 1, &info);
3625 }
3626
3627
3628 static void
3629 radv_sparse_buffer_bind_memory(struct radv_device *device,
3630 const VkSparseBufferMemoryBindInfo *bind)
3631 {
3632 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3633
3634 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3635 struct radv_device_memory *mem = NULL;
3636
3637 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3638 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3639
3640 device->ws->buffer_virtual_bind(buffer->bo,
3641 bind->pBinds[i].resourceOffset,
3642 bind->pBinds[i].size,
3643 mem ? mem->bo : NULL,
3644 bind->pBinds[i].memoryOffset);
3645 }
3646 }
3647
3648 static void
3649 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3650 const VkSparseImageOpaqueMemoryBindInfo *bind)
3651 {
3652 RADV_FROM_HANDLE(radv_image, image, bind->image);
3653
3654 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3655 struct radv_device_memory *mem = NULL;
3656
3657 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3658 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3659
3660 device->ws->buffer_virtual_bind(image->bo,
3661 bind->pBinds[i].resourceOffset,
3662 bind->pBinds[i].size,
3663 mem ? mem->bo : NULL,
3664 bind->pBinds[i].memoryOffset);
3665 }
3666 }
3667
3668 VkResult radv_QueueBindSparse(
3669 VkQueue _queue,
3670 uint32_t bindInfoCount,
3671 const VkBindSparseInfo* pBindInfo,
3672 VkFence _fence)
3673 {
3674 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3675 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3676 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3677 bool fence_emitted = false;
3678 VkResult result;
3679 int ret;
3680
3681 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3682 struct radv_winsys_sem_info sem_info;
3683 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3684 radv_sparse_buffer_bind_memory(queue->device,
3685 pBindInfo[i].pBufferBinds + j);
3686 }
3687
3688 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3689 radv_sparse_image_opaque_bind_memory(queue->device,
3690 pBindInfo[i].pImageOpaqueBinds + j);
3691 }
3692
3693 VkResult result;
3694 result = radv_alloc_sem_info(queue->device->instance,
3695 &sem_info,
3696 pBindInfo[i].waitSemaphoreCount,
3697 pBindInfo[i].pWaitSemaphores,
3698 pBindInfo[i].signalSemaphoreCount,
3699 pBindInfo[i].pSignalSemaphores,
3700 _fence);
3701 if (result != VK_SUCCESS)
3702 return result;
3703
3704 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3705 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3706 &queue->device->empty_cs[queue->queue_family_index],
3707 1, NULL, NULL,
3708 &sem_info, NULL,
3709 false, base_fence);
3710 if (ret) {
3711 radv_loge("failed to submit CS %d\n", i);
3712 abort();
3713 }
3714
3715 fence_emitted = true;
3716 }
3717
3718 radv_free_sem_info(&sem_info);
3719
3720 }
3721
3722 if (fence) {
3723 if (!fence_emitted) {
3724 result = radv_signal_fence(queue, fence);
3725 if (result != VK_SUCCESS)
3726 return result;
3727 }
3728 }
3729
3730 return VK_SUCCESS;
3731 }
3732
3733 VkResult radv_CreateFence(
3734 VkDevice _device,
3735 const VkFenceCreateInfo* pCreateInfo,
3736 const VkAllocationCallbacks* pAllocator,
3737 VkFence* pFence)
3738 {
3739 RADV_FROM_HANDLE(radv_device, device, _device);
3740 const VkExportFenceCreateInfo *export =
3741 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3742 VkExternalFenceHandleTypeFlags handleTypes =
3743 export ? export->handleTypes : 0;
3744
3745 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3746 sizeof(*fence), 8,
3747 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3748
3749 if (!fence)
3750 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3751
3752 fence->fence_wsi = NULL;
3753 fence->temp_syncobj = 0;
3754 if (device->always_use_syncobj || handleTypes) {
3755 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3756 if (ret) {
3757 vk_free2(&device->alloc, pAllocator, fence);
3758 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3759 }
3760 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3761 device->ws->signal_syncobj(device->ws, fence->syncobj);
3762 }
3763 fence->fence = NULL;
3764 } else {
3765 fence->fence = device->ws->create_fence();
3766 if (!fence->fence) {
3767 vk_free2(&device->alloc, pAllocator, fence);
3768 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3769 }
3770 fence->syncobj = 0;
3771 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3772 device->ws->signal_fence(fence->fence);
3773 }
3774
3775 *pFence = radv_fence_to_handle(fence);
3776
3777 return VK_SUCCESS;
3778 }
3779
3780 void radv_DestroyFence(
3781 VkDevice _device,
3782 VkFence _fence,
3783 const VkAllocationCallbacks* pAllocator)
3784 {
3785 RADV_FROM_HANDLE(radv_device, device, _device);
3786 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3787
3788 if (!fence)
3789 return;
3790
3791 if (fence->temp_syncobj)
3792 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3793 if (fence->syncobj)
3794 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3795 if (fence->fence)
3796 device->ws->destroy_fence(fence->fence);
3797 if (fence->fence_wsi)
3798 fence->fence_wsi->destroy(fence->fence_wsi);
3799 vk_free2(&device->alloc, pAllocator, fence);
3800 }
3801
3802
3803 uint64_t radv_get_current_time(void)
3804 {
3805 struct timespec tv;
3806 clock_gettime(CLOCK_MONOTONIC, &tv);
3807 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3808 }
3809
3810 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3811 {
3812 uint64_t current_time = radv_get_current_time();
3813
3814 timeout = MIN2(UINT64_MAX - current_time, timeout);
3815
3816 return current_time + timeout;
3817 }
3818
3819
3820 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3821 uint32_t fenceCount, const VkFence *pFences)
3822 {
3823 for (uint32_t i = 0; i < fenceCount; ++i) {
3824 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3825 if (fence->fence == NULL || fence->syncobj ||
3826 fence->temp_syncobj || fence->fence_wsi ||
3827 (!device->ws->is_fence_waitable(fence->fence)))
3828 return false;
3829 }
3830 return true;
3831 }
3832
3833 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3834 {
3835 for (uint32_t i = 0; i < fenceCount; ++i) {
3836 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3837 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3838 return false;
3839 }
3840 return true;
3841 }
3842
3843 VkResult radv_WaitForFences(
3844 VkDevice _device,
3845 uint32_t fenceCount,
3846 const VkFence* pFences,
3847 VkBool32 waitAll,
3848 uint64_t timeout)
3849 {
3850 RADV_FROM_HANDLE(radv_device, device, _device);
3851 timeout = radv_get_absolute_timeout(timeout);
3852
3853 if (device->always_use_syncobj &&
3854 radv_all_fences_syncobj(fenceCount, pFences))
3855 {
3856 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3857 if (!handles)
3858 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3859
3860 for (uint32_t i = 0; i < fenceCount; ++i) {
3861 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3862 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3863 }
3864
3865 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3866
3867 free(handles);
3868 return success ? VK_SUCCESS : VK_TIMEOUT;
3869 }
3870
3871 if (!waitAll && fenceCount > 1) {
3872 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3873 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3874 uint32_t wait_count = 0;
3875 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3876 if (!fences)
3877 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3878
3879 for (uint32_t i = 0; i < fenceCount; ++i) {
3880 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3881
3882 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3883 free(fences);
3884 return VK_SUCCESS;
3885 }
3886
3887 fences[wait_count++] = fence->fence;
3888 }
3889
3890 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3891 waitAll, timeout - radv_get_current_time());
3892
3893 free(fences);
3894 return success ? VK_SUCCESS : VK_TIMEOUT;
3895 }
3896
3897 while(radv_get_current_time() <= timeout) {
3898 for (uint32_t i = 0; i < fenceCount; ++i) {
3899 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3900 return VK_SUCCESS;
3901 }
3902 }
3903 return VK_TIMEOUT;
3904 }
3905
3906 for (uint32_t i = 0; i < fenceCount; ++i) {
3907 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3908 bool expired = false;
3909
3910 if (fence->temp_syncobj) {
3911 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3912 return VK_TIMEOUT;
3913 continue;
3914 }
3915
3916 if (fence->syncobj) {
3917 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3918 return VK_TIMEOUT;
3919 continue;
3920 }
3921
3922 if (fence->fence) {
3923 if (!device->ws->is_fence_waitable(fence->fence)) {
3924 while(!device->ws->is_fence_waitable(fence->fence) &&
3925 radv_get_current_time() <= timeout)
3926 /* Do nothing */;
3927 }
3928
3929 expired = device->ws->fence_wait(device->ws,
3930 fence->fence,
3931 true, timeout);
3932 if (!expired)
3933 return VK_TIMEOUT;
3934 }
3935
3936 if (fence->fence_wsi) {
3937 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3938 if (result != VK_SUCCESS)
3939 return result;
3940 }
3941 }
3942
3943 return VK_SUCCESS;
3944 }
3945
3946 VkResult radv_ResetFences(VkDevice _device,
3947 uint32_t fenceCount,
3948 const VkFence *pFences)
3949 {
3950 RADV_FROM_HANDLE(radv_device, device, _device);
3951
3952 for (unsigned i = 0; i < fenceCount; ++i) {
3953 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3954 if (fence->fence)
3955 device->ws->reset_fence(fence->fence);
3956
3957 /* Per spec, we first restore the permanent payload, and then reset, so
3958 * having a temp syncobj should not skip resetting the permanent syncobj. */
3959 if (fence->temp_syncobj) {
3960 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3961 fence->temp_syncobj = 0;
3962 }
3963
3964 if (fence->syncobj) {
3965 device->ws->reset_syncobj(device->ws, fence->syncobj);
3966 }
3967 }
3968
3969 return VK_SUCCESS;
3970 }
3971
3972 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3973 {
3974 RADV_FROM_HANDLE(radv_device, device, _device);
3975 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3976
3977 if (fence->temp_syncobj) {
3978 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3979 return success ? VK_SUCCESS : VK_NOT_READY;
3980 }
3981
3982 if (fence->syncobj) {
3983 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3984 return success ? VK_SUCCESS : VK_NOT_READY;
3985 }
3986
3987 if (fence->fence) {
3988 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3989 return VK_NOT_READY;
3990 }
3991 if (fence->fence_wsi) {
3992 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3993
3994 if (result != VK_SUCCESS) {
3995 if (result == VK_TIMEOUT)
3996 return VK_NOT_READY;
3997 return result;
3998 }
3999 }
4000 return VK_SUCCESS;
4001 }
4002
4003
4004 // Queue semaphore functions
4005
4006 VkResult radv_CreateSemaphore(
4007 VkDevice _device,
4008 const VkSemaphoreCreateInfo* pCreateInfo,
4009 const VkAllocationCallbacks* pAllocator,
4010 VkSemaphore* pSemaphore)
4011 {
4012 RADV_FROM_HANDLE(radv_device, device, _device);
4013 const VkExportSemaphoreCreateInfo *export =
4014 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4015 VkExternalSemaphoreHandleTypeFlags handleTypes =
4016 export ? export->handleTypes : 0;
4017
4018 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4019 sizeof(*sem), 8,
4020 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4021 if (!sem)
4022 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4023
4024 sem->temp_syncobj = 0;
4025 /* create a syncobject if we are going to export this semaphore */
4026 if (device->always_use_syncobj || handleTypes) {
4027 assert (device->physical_device->rad_info.has_syncobj);
4028 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4029 if (ret) {
4030 vk_free2(&device->alloc, pAllocator, sem);
4031 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4032 }
4033 sem->sem = NULL;
4034 } else {
4035 sem->sem = device->ws->create_sem(device->ws);
4036 if (!sem->sem) {
4037 vk_free2(&device->alloc, pAllocator, sem);
4038 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4039 }
4040 sem->syncobj = 0;
4041 }
4042
4043 *pSemaphore = radv_semaphore_to_handle(sem);
4044 return VK_SUCCESS;
4045 }
4046
4047 void radv_DestroySemaphore(
4048 VkDevice _device,
4049 VkSemaphore _semaphore,
4050 const VkAllocationCallbacks* pAllocator)
4051 {
4052 RADV_FROM_HANDLE(radv_device, device, _device);
4053 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4054 if (!_semaphore)
4055 return;
4056
4057 if (sem->syncobj)
4058 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4059 else
4060 device->ws->destroy_sem(sem->sem);
4061 vk_free2(&device->alloc, pAllocator, sem);
4062 }
4063
4064 VkResult radv_CreateEvent(
4065 VkDevice _device,
4066 const VkEventCreateInfo* pCreateInfo,
4067 const VkAllocationCallbacks* pAllocator,
4068 VkEvent* pEvent)
4069 {
4070 RADV_FROM_HANDLE(radv_device, device, _device);
4071 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4072 sizeof(*event), 8,
4073 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4074
4075 if (!event)
4076 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4077
4078 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4079 RADEON_DOMAIN_GTT,
4080 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4081 RADV_BO_PRIORITY_FENCE);
4082 if (!event->bo) {
4083 vk_free2(&device->alloc, pAllocator, event);
4084 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4085 }
4086
4087 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4088
4089 *pEvent = radv_event_to_handle(event);
4090
4091 return VK_SUCCESS;
4092 }
4093
4094 void radv_DestroyEvent(
4095 VkDevice _device,
4096 VkEvent _event,
4097 const VkAllocationCallbacks* pAllocator)
4098 {
4099 RADV_FROM_HANDLE(radv_device, device, _device);
4100 RADV_FROM_HANDLE(radv_event, event, _event);
4101
4102 if (!event)
4103 return;
4104 device->ws->buffer_destroy(event->bo);
4105 vk_free2(&device->alloc, pAllocator, event);
4106 }
4107
4108 VkResult radv_GetEventStatus(
4109 VkDevice _device,
4110 VkEvent _event)
4111 {
4112 RADV_FROM_HANDLE(radv_event, event, _event);
4113
4114 if (*event->map == 1)
4115 return VK_EVENT_SET;
4116 return VK_EVENT_RESET;
4117 }
4118
4119 VkResult radv_SetEvent(
4120 VkDevice _device,
4121 VkEvent _event)
4122 {
4123 RADV_FROM_HANDLE(radv_event, event, _event);
4124 *event->map = 1;
4125
4126 return VK_SUCCESS;
4127 }
4128
4129 VkResult radv_ResetEvent(
4130 VkDevice _device,
4131 VkEvent _event)
4132 {
4133 RADV_FROM_HANDLE(radv_event, event, _event);
4134 *event->map = 0;
4135
4136 return VK_SUCCESS;
4137 }
4138
4139 VkResult radv_CreateBuffer(
4140 VkDevice _device,
4141 const VkBufferCreateInfo* pCreateInfo,
4142 const VkAllocationCallbacks* pAllocator,
4143 VkBuffer* pBuffer)
4144 {
4145 RADV_FROM_HANDLE(radv_device, device, _device);
4146 struct radv_buffer *buffer;
4147
4148 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4149
4150 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4151 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4152 if (buffer == NULL)
4153 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4154
4155 buffer->size = pCreateInfo->size;
4156 buffer->usage = pCreateInfo->usage;
4157 buffer->bo = NULL;
4158 buffer->offset = 0;
4159 buffer->flags = pCreateInfo->flags;
4160
4161 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4162 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4163
4164 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4165 buffer->bo = device->ws->buffer_create(device->ws,
4166 align64(buffer->size, 4096),
4167 4096, 0, RADEON_FLAG_VIRTUAL,
4168 RADV_BO_PRIORITY_VIRTUAL);
4169 if (!buffer->bo) {
4170 vk_free2(&device->alloc, pAllocator, buffer);
4171 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4172 }
4173 }
4174
4175 *pBuffer = radv_buffer_to_handle(buffer);
4176
4177 return VK_SUCCESS;
4178 }
4179
4180 void radv_DestroyBuffer(
4181 VkDevice _device,
4182 VkBuffer _buffer,
4183 const VkAllocationCallbacks* pAllocator)
4184 {
4185 RADV_FROM_HANDLE(radv_device, device, _device);
4186 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4187
4188 if (!buffer)
4189 return;
4190
4191 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4192 device->ws->buffer_destroy(buffer->bo);
4193
4194 vk_free2(&device->alloc, pAllocator, buffer);
4195 }
4196
4197 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4198 VkDevice device,
4199 const VkBufferDeviceAddressInfoEXT* pInfo)
4200 {
4201 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4202 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4203 }
4204
4205
4206 static inline unsigned
4207 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4208 {
4209 if (stencil)
4210 return plane->surface.u.legacy.stencil_tiling_index[level];
4211 else
4212 return plane->surface.u.legacy.tiling_index[level];
4213 }
4214
4215 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4216 {
4217 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4218 }
4219
4220 static uint32_t
4221 radv_init_dcc_control_reg(struct radv_device *device,
4222 struct radv_image_view *iview)
4223 {
4224 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4225 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4226 unsigned max_compressed_block_size;
4227 unsigned independent_128b_blocks;
4228 unsigned independent_64b_blocks;
4229
4230 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4231 return 0;
4232
4233 if (!device->physical_device->rad_info.has_dedicated_vram) {
4234 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4235 * dGPU and 64 for APU because all of our APUs to date use
4236 * DIMMs which have a request granularity size of 64B while all
4237 * other chips have a 32B request size.
4238 */
4239 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4240 }
4241
4242 if (device->physical_device->rad_info.chip_class >= GFX10) {
4243 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4244 independent_64b_blocks = 0;
4245 independent_128b_blocks = 1;
4246 } else {
4247 independent_128b_blocks = 0;
4248
4249 if (iview->image->info.samples > 1) {
4250 if (iview->image->planes[0].surface.bpe == 1)
4251 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4252 else if (iview->image->planes[0].surface.bpe == 2)
4253 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4254 }
4255
4256 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4257 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4258 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4259 /* If this DCC image is potentially going to be used in texture
4260 * fetches, we need some special settings.
4261 */
4262 independent_64b_blocks = 1;
4263 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4264 } else {
4265 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4266 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4267 * big as possible for better compression state.
4268 */
4269 independent_64b_blocks = 0;
4270 max_compressed_block_size = max_uncompressed_block_size;
4271 }
4272 }
4273
4274 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4275 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4276 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4277 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4278 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4279 }
4280
4281 static void
4282 radv_initialise_color_surface(struct radv_device *device,
4283 struct radv_color_buffer_info *cb,
4284 struct radv_image_view *iview)
4285 {
4286 const struct vk_format_description *desc;
4287 unsigned ntype, format, swap, endian;
4288 unsigned blend_clamp = 0, blend_bypass = 0;
4289 uint64_t va;
4290 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4291 const struct radeon_surf *surf = &plane->surface;
4292
4293 desc = vk_format_description(iview->vk_format);
4294
4295 memset(cb, 0, sizeof(*cb));
4296
4297 /* Intensity is implemented as Red, so treat it that way. */
4298 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4299
4300 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4301
4302 cb->cb_color_base = va >> 8;
4303
4304 if (device->physical_device->rad_info.chip_class >= GFX9) {
4305 struct gfx9_surf_meta_flags meta;
4306 if (iview->image->dcc_offset)
4307 meta = surf->u.gfx9.dcc;
4308 else
4309 meta = surf->u.gfx9.cmask;
4310
4311 if (device->physical_device->rad_info.chip_class >= GFX10) {
4312 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4313 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4314 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4315 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4316 } else {
4317 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4318 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4319 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4320 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4321 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4322 }
4323
4324 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4325 cb->cb_color_base |= surf->tile_swizzle;
4326 } else {
4327 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4328 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4329
4330 cb->cb_color_base += level_info->offset >> 8;
4331 if (level_info->mode == RADEON_SURF_MODE_2D)
4332 cb->cb_color_base |= surf->tile_swizzle;
4333
4334 pitch_tile_max = level_info->nblk_x / 8 - 1;
4335 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4336 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4337
4338 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4339 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4340 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4341
4342 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4343
4344 if (radv_image_has_fmask(iview->image)) {
4345 if (device->physical_device->rad_info.chip_class >= GFX7)
4346 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4347 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4348 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4349 } else {
4350 /* This must be set for fast clear to work without FMASK. */
4351 if (device->physical_device->rad_info.chip_class >= GFX7)
4352 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4353 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4354 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4355 }
4356 }
4357
4358 /* CMASK variables */
4359 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4360 va += iview->image->cmask.offset;
4361 cb->cb_color_cmask = va >> 8;
4362
4363 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4364 va += iview->image->dcc_offset;
4365
4366 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4367 device->physical_device->rad_info.chip_class <= GFX8)
4368 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4369
4370 cb->cb_dcc_base = va >> 8;
4371 cb->cb_dcc_base |= surf->tile_swizzle;
4372
4373 /* GFX10 field has the same base shift as the GFX6 field. */
4374 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4375 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4376 S_028C6C_SLICE_MAX_GFX10(max_slice);
4377
4378 if (iview->image->info.samples > 1) {
4379 unsigned log_samples = util_logbase2(iview->image->info.samples);
4380
4381 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4382 S_028C74_NUM_FRAGMENTS(log_samples);
4383 }
4384
4385 if (radv_image_has_fmask(iview->image)) {
4386 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4387 cb->cb_color_fmask = va >> 8;
4388 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4389 } else {
4390 cb->cb_color_fmask = cb->cb_color_base;
4391 }
4392
4393 ntype = radv_translate_color_numformat(iview->vk_format,
4394 desc,
4395 vk_format_get_first_non_void_channel(iview->vk_format));
4396 format = radv_translate_colorformat(iview->vk_format);
4397 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4398 radv_finishme("Illegal color\n");
4399 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4400 endian = radv_colorformat_endian_swap(format);
4401
4402 /* blend clamp should be set for all NORM/SRGB types */
4403 if (ntype == V_028C70_NUMBER_UNORM ||
4404 ntype == V_028C70_NUMBER_SNORM ||
4405 ntype == V_028C70_NUMBER_SRGB)
4406 blend_clamp = 1;
4407
4408 /* set blend bypass according to docs if SINT/UINT or
4409 8/24 COLOR variants */
4410 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4411 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4412 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4413 blend_clamp = 0;
4414 blend_bypass = 1;
4415 }
4416 #if 0
4417 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4418 (format == V_028C70_COLOR_8 ||
4419 format == V_028C70_COLOR_8_8 ||
4420 format == V_028C70_COLOR_8_8_8_8))
4421 ->color_is_int8 = true;
4422 #endif
4423 cb->cb_color_info = S_028C70_FORMAT(format) |
4424 S_028C70_COMP_SWAP(swap) |
4425 S_028C70_BLEND_CLAMP(blend_clamp) |
4426 S_028C70_BLEND_BYPASS(blend_bypass) |
4427 S_028C70_SIMPLE_FLOAT(1) |
4428 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4429 ntype != V_028C70_NUMBER_SNORM &&
4430 ntype != V_028C70_NUMBER_SRGB &&
4431 format != V_028C70_COLOR_8_24 &&
4432 format != V_028C70_COLOR_24_8) |
4433 S_028C70_NUMBER_TYPE(ntype) |
4434 S_028C70_ENDIAN(endian);
4435 if (radv_image_has_fmask(iview->image)) {
4436 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4437 if (device->physical_device->rad_info.chip_class == GFX6) {
4438 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4439 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4440 }
4441
4442 if (radv_image_is_tc_compat_cmask(iview->image)) {
4443 /* Allow the texture block to read FMASK directly
4444 * without decompressing it. This bit must be cleared
4445 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4446 * otherwise the operation doesn't happen.
4447 */
4448 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4449
4450 /* Set CMASK into a tiling format that allows the
4451 * texture block to read it.
4452 */
4453 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4454 }
4455 }
4456
4457 if (radv_image_has_cmask(iview->image) &&
4458 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4459 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4460
4461 if (radv_dcc_enabled(iview->image, iview->base_mip))
4462 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4463
4464 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4465
4466 /* This must be set for fast clear to work without FMASK. */
4467 if (!radv_image_has_fmask(iview->image) &&
4468 device->physical_device->rad_info.chip_class == GFX6) {
4469 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4470 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4471 }
4472
4473 if (device->physical_device->rad_info.chip_class >= GFX9) {
4474 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4475
4476 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4477 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4478 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4479 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4480
4481 if (device->physical_device->rad_info.chip_class >= GFX10) {
4482 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4483
4484 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4485 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4486 S_028EE0_RESOURCE_LEVEL(1);
4487 } else {
4488 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4489 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4490 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4491 }
4492
4493 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4494 S_028C68_MIP0_HEIGHT(height - 1) |
4495 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4496 }
4497 }
4498
4499 static unsigned
4500 radv_calc_decompress_on_z_planes(struct radv_device *device,
4501 struct radv_image_view *iview)
4502 {
4503 unsigned max_zplanes = 0;
4504
4505 assert(radv_image_is_tc_compat_htile(iview->image));
4506
4507 if (device->physical_device->rad_info.chip_class >= GFX9) {
4508 /* Default value for 32-bit depth surfaces. */
4509 max_zplanes = 4;
4510
4511 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4512 iview->image->info.samples > 1)
4513 max_zplanes = 2;
4514
4515 max_zplanes = max_zplanes + 1;
4516 } else {
4517 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4518 /* Do not enable Z plane compression for 16-bit depth
4519 * surfaces because isn't supported on GFX8. Only
4520 * 32-bit depth surfaces are supported by the hardware.
4521 * This allows to maintain shader compatibility and to
4522 * reduce the number of depth decompressions.
4523 */
4524 max_zplanes = 1;
4525 } else {
4526 if (iview->image->info.samples <= 1)
4527 max_zplanes = 5;
4528 else if (iview->image->info.samples <= 4)
4529 max_zplanes = 3;
4530 else
4531 max_zplanes = 2;
4532 }
4533 }
4534
4535 return max_zplanes;
4536 }
4537
4538 static void
4539 radv_initialise_ds_surface(struct radv_device *device,
4540 struct radv_ds_buffer_info *ds,
4541 struct radv_image_view *iview)
4542 {
4543 unsigned level = iview->base_mip;
4544 unsigned format, stencil_format;
4545 uint64_t va, s_offs, z_offs;
4546 bool stencil_only = false;
4547 const struct radv_image_plane *plane = &iview->image->planes[0];
4548 const struct radeon_surf *surf = &plane->surface;
4549
4550 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4551
4552 memset(ds, 0, sizeof(*ds));
4553 switch (iview->image->vk_format) {
4554 case VK_FORMAT_D24_UNORM_S8_UINT:
4555 case VK_FORMAT_X8_D24_UNORM_PACK32:
4556 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4557 ds->offset_scale = 2.0f;
4558 break;
4559 case VK_FORMAT_D16_UNORM:
4560 case VK_FORMAT_D16_UNORM_S8_UINT:
4561 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4562 ds->offset_scale = 4.0f;
4563 break;
4564 case VK_FORMAT_D32_SFLOAT:
4565 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4566 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4567 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4568 ds->offset_scale = 1.0f;
4569 break;
4570 case VK_FORMAT_S8_UINT:
4571 stencil_only = true;
4572 break;
4573 default:
4574 break;
4575 }
4576
4577 format = radv_translate_dbformat(iview->image->vk_format);
4578 stencil_format = surf->has_stencil ?
4579 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4580
4581 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4582 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4583 S_028008_SLICE_MAX(max_slice);
4584 if (device->physical_device->rad_info.chip_class >= GFX10) {
4585 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4586 S_028008_SLICE_MAX_HI(max_slice >> 11);
4587 }
4588
4589 ds->db_htile_data_base = 0;
4590 ds->db_htile_surface = 0;
4591
4592 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4593 s_offs = z_offs = va;
4594
4595 if (device->physical_device->rad_info.chip_class >= GFX9) {
4596 assert(surf->u.gfx9.surf_offset == 0);
4597 s_offs += surf->u.gfx9.stencil_offset;
4598
4599 ds->db_z_info = S_028038_FORMAT(format) |
4600 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4601 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4602 S_028038_MAXMIP(iview->image->info.levels - 1) |
4603 S_028038_ZRANGE_PRECISION(1);
4604 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4605 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4606
4607 if (device->physical_device->rad_info.chip_class == GFX9) {
4608 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4609 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4610 }
4611
4612 ds->db_depth_view |= S_028008_MIPID(level);
4613 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4614 S_02801C_Y_MAX(iview->image->info.height - 1);
4615
4616 if (radv_htile_enabled(iview->image, level)) {
4617 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4618
4619 if (radv_image_is_tc_compat_htile(iview->image)) {
4620 unsigned max_zplanes =
4621 radv_calc_decompress_on_z_planes(device, iview);
4622
4623 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4624
4625 if (device->physical_device->rad_info.chip_class >= GFX10) {
4626 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4627 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4628 } else {
4629 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4630 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4631 }
4632 }
4633
4634 if (!surf->has_stencil)
4635 /* Use all of the htile_buffer for depth if there's no stencil. */
4636 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4637 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4638 iview->image->htile_offset;
4639 ds->db_htile_data_base = va >> 8;
4640 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4641 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4642
4643 if (device->physical_device->rad_info.chip_class == GFX9) {
4644 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4645 }
4646 }
4647 } else {
4648 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4649
4650 if (stencil_only)
4651 level_info = &surf->u.legacy.stencil_level[level];
4652
4653 z_offs += surf->u.legacy.level[level].offset;
4654 s_offs += surf->u.legacy.stencil_level[level].offset;
4655
4656 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4657 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4658 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4659
4660 if (iview->image->info.samples > 1)
4661 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4662
4663 if (device->physical_device->rad_info.chip_class >= GFX7) {
4664 struct radeon_info *info = &device->physical_device->rad_info;
4665 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4666 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4667 unsigned macro_index = surf->u.legacy.macro_tile_index;
4668 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4669 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4670 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4671
4672 if (stencil_only)
4673 tile_mode = stencil_tile_mode;
4674
4675 ds->db_depth_info |=
4676 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4677 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4678 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4679 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4680 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4681 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4682 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4683 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4684 } else {
4685 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4686 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4687 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4688 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4689 if (stencil_only)
4690 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4691 }
4692
4693 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4694 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4695 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4696
4697 if (radv_htile_enabled(iview->image, level)) {
4698 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4699
4700 if (!surf->has_stencil &&
4701 !radv_image_is_tc_compat_htile(iview->image))
4702 /* Use all of the htile_buffer for depth if there's no stencil. */
4703 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4704
4705 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4706 iview->image->htile_offset;
4707 ds->db_htile_data_base = va >> 8;
4708 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4709
4710 if (radv_image_is_tc_compat_htile(iview->image)) {
4711 unsigned max_zplanes =
4712 radv_calc_decompress_on_z_planes(device, iview);
4713
4714 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4715 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4716 }
4717 }
4718 }
4719
4720 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4721 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4722 }
4723
4724 VkResult radv_CreateFramebuffer(
4725 VkDevice _device,
4726 const VkFramebufferCreateInfo* pCreateInfo,
4727 const VkAllocationCallbacks* pAllocator,
4728 VkFramebuffer* pFramebuffer)
4729 {
4730 RADV_FROM_HANDLE(radv_device, device, _device);
4731 struct radv_framebuffer *framebuffer;
4732
4733 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4734
4735 size_t size = sizeof(*framebuffer) +
4736 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4737 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4738 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4739 if (framebuffer == NULL)
4740 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4741
4742 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4743 framebuffer->width = pCreateInfo->width;
4744 framebuffer->height = pCreateInfo->height;
4745 framebuffer->layers = pCreateInfo->layers;
4746 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4747 VkImageView _iview = pCreateInfo->pAttachments[i];
4748 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4749 framebuffer->attachments[i].attachment = iview;
4750 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4751 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4752 } else {
4753 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4754 }
4755 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4756 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4757 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4758 }
4759
4760 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4761 return VK_SUCCESS;
4762 }
4763
4764 void radv_DestroyFramebuffer(
4765 VkDevice _device,
4766 VkFramebuffer _fb,
4767 const VkAllocationCallbacks* pAllocator)
4768 {
4769 RADV_FROM_HANDLE(radv_device, device, _device);
4770 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4771
4772 if (!fb)
4773 return;
4774 vk_free2(&device->alloc, pAllocator, fb);
4775 }
4776
4777 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4778 {
4779 switch (address_mode) {
4780 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4781 return V_008F30_SQ_TEX_WRAP;
4782 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4783 return V_008F30_SQ_TEX_MIRROR;
4784 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4785 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4786 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4787 return V_008F30_SQ_TEX_CLAMP_BORDER;
4788 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4789 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4790 default:
4791 unreachable("illegal tex wrap mode");
4792 break;
4793 }
4794 }
4795
4796 static unsigned
4797 radv_tex_compare(VkCompareOp op)
4798 {
4799 switch (op) {
4800 case VK_COMPARE_OP_NEVER:
4801 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4802 case VK_COMPARE_OP_LESS:
4803 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4804 case VK_COMPARE_OP_EQUAL:
4805 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4806 case VK_COMPARE_OP_LESS_OR_EQUAL:
4807 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4808 case VK_COMPARE_OP_GREATER:
4809 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4810 case VK_COMPARE_OP_NOT_EQUAL:
4811 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4812 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4813 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4814 case VK_COMPARE_OP_ALWAYS:
4815 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4816 default:
4817 unreachable("illegal compare mode");
4818 break;
4819 }
4820 }
4821
4822 static unsigned
4823 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4824 {
4825 switch (filter) {
4826 case VK_FILTER_NEAREST:
4827 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4828 V_008F38_SQ_TEX_XY_FILTER_POINT);
4829 case VK_FILTER_LINEAR:
4830 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4831 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4832 case VK_FILTER_CUBIC_IMG:
4833 default:
4834 fprintf(stderr, "illegal texture filter");
4835 return 0;
4836 }
4837 }
4838
4839 static unsigned
4840 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4841 {
4842 switch (mode) {
4843 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4844 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4845 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4846 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4847 default:
4848 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4849 }
4850 }
4851
4852 static unsigned
4853 radv_tex_bordercolor(VkBorderColor bcolor)
4854 {
4855 switch (bcolor) {
4856 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4857 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4858 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4859 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4860 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4861 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4862 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4863 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4864 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4865 default:
4866 break;
4867 }
4868 return 0;
4869 }
4870
4871 static unsigned
4872 radv_tex_aniso_filter(unsigned filter)
4873 {
4874 if (filter < 2)
4875 return 0;
4876 if (filter < 4)
4877 return 1;
4878 if (filter < 8)
4879 return 2;
4880 if (filter < 16)
4881 return 3;
4882 return 4;
4883 }
4884
4885 static unsigned
4886 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4887 {
4888 switch (mode) {
4889 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4890 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4891 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4892 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4893 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4894 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4895 default:
4896 break;
4897 }
4898 return 0;
4899 }
4900
4901 static uint32_t
4902 radv_get_max_anisotropy(struct radv_device *device,
4903 const VkSamplerCreateInfo *pCreateInfo)
4904 {
4905 if (device->force_aniso >= 0)
4906 return device->force_aniso;
4907
4908 if (pCreateInfo->anisotropyEnable &&
4909 pCreateInfo->maxAnisotropy > 1.0f)
4910 return (uint32_t)pCreateInfo->maxAnisotropy;
4911
4912 return 0;
4913 }
4914
4915 static void
4916 radv_init_sampler(struct radv_device *device,
4917 struct radv_sampler *sampler,
4918 const VkSamplerCreateInfo *pCreateInfo)
4919 {
4920 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4921 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4922 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4923 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4924
4925 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4926 vk_find_struct_const(pCreateInfo->pNext,
4927 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4928 if (sampler_reduction)
4929 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4930
4931 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4932 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4933 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4934 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4935 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4936 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4937 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4938 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4939 S_008F30_DISABLE_CUBE_WRAP(0) |
4940 S_008F30_COMPAT_MODE(is_vi) |
4941 S_008F30_FILTER_MODE(filter_mode));
4942 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4943 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4944 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4945 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4946 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4947 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4948 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4949 S_008F38_MIP_POINT_PRECLAMP(0) |
4950 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4951 S_008F38_FILTER_PREC_FIX(1) |
4952 S_008F38_ANISO_OVERRIDE_GFX6(is_vi));
4953 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4954 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4955 }
4956
4957 VkResult radv_CreateSampler(
4958 VkDevice _device,
4959 const VkSamplerCreateInfo* pCreateInfo,
4960 const VkAllocationCallbacks* pAllocator,
4961 VkSampler* pSampler)
4962 {
4963 RADV_FROM_HANDLE(radv_device, device, _device);
4964 struct radv_sampler *sampler;
4965
4966 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4967 vk_find_struct_const(pCreateInfo->pNext,
4968 SAMPLER_YCBCR_CONVERSION_INFO);
4969
4970 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4971
4972 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4973 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4974 if (!sampler)
4975 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4976
4977 radv_init_sampler(device, sampler, pCreateInfo);
4978
4979 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4980 *pSampler = radv_sampler_to_handle(sampler);
4981
4982 return VK_SUCCESS;
4983 }
4984
4985 void radv_DestroySampler(
4986 VkDevice _device,
4987 VkSampler _sampler,
4988 const VkAllocationCallbacks* pAllocator)
4989 {
4990 RADV_FROM_HANDLE(radv_device, device, _device);
4991 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4992
4993 if (!sampler)
4994 return;
4995 vk_free2(&device->alloc, pAllocator, sampler);
4996 }
4997
4998 /* vk_icd.h does not declare this function, so we declare it here to
4999 * suppress Wmissing-prototypes.
5000 */
5001 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5002 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5003
5004 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5005 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5006 {
5007 /* For the full details on loader interface versioning, see
5008 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5009 * What follows is a condensed summary, to help you navigate the large and
5010 * confusing official doc.
5011 *
5012 * - Loader interface v0 is incompatible with later versions. We don't
5013 * support it.
5014 *
5015 * - In loader interface v1:
5016 * - The first ICD entrypoint called by the loader is
5017 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5018 * entrypoint.
5019 * - The ICD must statically expose no other Vulkan symbol unless it is
5020 * linked with -Bsymbolic.
5021 * - Each dispatchable Vulkan handle created by the ICD must be
5022 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5023 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5024 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5025 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5026 * such loader-managed surfaces.
5027 *
5028 * - Loader interface v2 differs from v1 in:
5029 * - The first ICD entrypoint called by the loader is
5030 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5031 * statically expose this entrypoint.
5032 *
5033 * - Loader interface v3 differs from v2 in:
5034 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5035 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5036 * because the loader no longer does so.
5037 */
5038 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5039 return VK_SUCCESS;
5040 }
5041
5042 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5043 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5044 int *pFD)
5045 {
5046 RADV_FROM_HANDLE(radv_device, device, _device);
5047 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5048
5049 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5050
5051 /* At the moment, we support only the below handle types. */
5052 assert(pGetFdInfo->handleType ==
5053 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5054 pGetFdInfo->handleType ==
5055 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5056
5057 bool ret = radv_get_memory_fd(device, memory, pFD);
5058 if (ret == false)
5059 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5060 return VK_SUCCESS;
5061 }
5062
5063 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5064 VkExternalMemoryHandleTypeFlagBits handleType,
5065 int fd,
5066 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5067 {
5068 RADV_FROM_HANDLE(radv_device, device, _device);
5069
5070 switch (handleType) {
5071 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5072 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5073 return VK_SUCCESS;
5074
5075 default:
5076 /* The valid usage section for this function says:
5077 *
5078 * "handleType must not be one of the handle types defined as
5079 * opaque."
5080 *
5081 * So opaque handle types fall into the default "unsupported" case.
5082 */
5083 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5084 }
5085 }
5086
5087 static VkResult radv_import_opaque_fd(struct radv_device *device,
5088 int fd,
5089 uint32_t *syncobj)
5090 {
5091 uint32_t syncobj_handle = 0;
5092 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5093 if (ret != 0)
5094 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5095
5096 if (*syncobj)
5097 device->ws->destroy_syncobj(device->ws, *syncobj);
5098
5099 *syncobj = syncobj_handle;
5100 close(fd);
5101
5102 return VK_SUCCESS;
5103 }
5104
5105 static VkResult radv_import_sync_fd(struct radv_device *device,
5106 int fd,
5107 uint32_t *syncobj)
5108 {
5109 /* If we create a syncobj we do it locally so that if we have an error, we don't
5110 * leave a syncobj in an undetermined state in the fence. */
5111 uint32_t syncobj_handle = *syncobj;
5112 if (!syncobj_handle) {
5113 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5114 if (ret) {
5115 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5116 }
5117 }
5118
5119 if (fd == -1) {
5120 device->ws->signal_syncobj(device->ws, syncobj_handle);
5121 } else {
5122 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5123 if (ret != 0)
5124 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5125 }
5126
5127 *syncobj = syncobj_handle;
5128 if (fd != -1)
5129 close(fd);
5130
5131 return VK_SUCCESS;
5132 }
5133
5134 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5135 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5136 {
5137 RADV_FROM_HANDLE(radv_device, device, _device);
5138 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5139 uint32_t *syncobj_dst = NULL;
5140
5141 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5142 syncobj_dst = &sem->temp_syncobj;
5143 } else {
5144 syncobj_dst = &sem->syncobj;
5145 }
5146
5147 switch(pImportSemaphoreFdInfo->handleType) {
5148 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5149 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5150 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5151 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5152 default:
5153 unreachable("Unhandled semaphore handle type");
5154 }
5155 }
5156
5157 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5158 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5159 int *pFd)
5160 {
5161 RADV_FROM_HANDLE(radv_device, device, _device);
5162 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5163 int ret;
5164 uint32_t syncobj_handle;
5165
5166 if (sem->temp_syncobj)
5167 syncobj_handle = sem->temp_syncobj;
5168 else
5169 syncobj_handle = sem->syncobj;
5170
5171 switch(pGetFdInfo->handleType) {
5172 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5173 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5174 break;
5175 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5176 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5177 if (!ret) {
5178 if (sem->temp_syncobj) {
5179 close (sem->temp_syncobj);
5180 sem->temp_syncobj = 0;
5181 } else {
5182 device->ws->reset_syncobj(device->ws, syncobj_handle);
5183 }
5184 }
5185 break;
5186 default:
5187 unreachable("Unhandled semaphore handle type");
5188 }
5189
5190 if (ret)
5191 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5192 return VK_SUCCESS;
5193 }
5194
5195 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5196 VkPhysicalDevice physicalDevice,
5197 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5198 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5199 {
5200 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5201
5202 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5203 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5204 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5205 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5206 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5207 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5208 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5209 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5210 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5211 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5212 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5213 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5214 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5215 } else {
5216 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5217 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5218 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5219 }
5220 }
5221
5222 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5223 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5224 {
5225 RADV_FROM_HANDLE(radv_device, device, _device);
5226 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5227 uint32_t *syncobj_dst = NULL;
5228
5229
5230 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5231 syncobj_dst = &fence->temp_syncobj;
5232 } else {
5233 syncobj_dst = &fence->syncobj;
5234 }
5235
5236 switch(pImportFenceFdInfo->handleType) {
5237 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5238 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5239 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5240 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5241 default:
5242 unreachable("Unhandled fence handle type");
5243 }
5244 }
5245
5246 VkResult radv_GetFenceFdKHR(VkDevice _device,
5247 const VkFenceGetFdInfoKHR *pGetFdInfo,
5248 int *pFd)
5249 {
5250 RADV_FROM_HANDLE(radv_device, device, _device);
5251 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5252 int ret;
5253 uint32_t syncobj_handle;
5254
5255 if (fence->temp_syncobj)
5256 syncobj_handle = fence->temp_syncobj;
5257 else
5258 syncobj_handle = fence->syncobj;
5259
5260 switch(pGetFdInfo->handleType) {
5261 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5262 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5263 break;
5264 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5265 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5266 if (!ret) {
5267 if (fence->temp_syncobj) {
5268 close (fence->temp_syncobj);
5269 fence->temp_syncobj = 0;
5270 } else {
5271 device->ws->reset_syncobj(device->ws, syncobj_handle);
5272 }
5273 }
5274 break;
5275 default:
5276 unreachable("Unhandled fence handle type");
5277 }
5278
5279 if (ret)
5280 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5281 return VK_SUCCESS;
5282 }
5283
5284 void radv_GetPhysicalDeviceExternalFenceProperties(
5285 VkPhysicalDevice physicalDevice,
5286 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5287 VkExternalFenceProperties *pExternalFenceProperties)
5288 {
5289 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5290
5291 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5292 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5293 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5294 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5295 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5296 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5297 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5298 } else {
5299 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5300 pExternalFenceProperties->compatibleHandleTypes = 0;
5301 pExternalFenceProperties->externalFenceFeatures = 0;
5302 }
5303 }
5304
5305 VkResult
5306 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5307 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5308 const VkAllocationCallbacks* pAllocator,
5309 VkDebugReportCallbackEXT* pCallback)
5310 {
5311 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5312 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5313 pCreateInfo, pAllocator, &instance->alloc,
5314 pCallback);
5315 }
5316
5317 void
5318 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5319 VkDebugReportCallbackEXT _callback,
5320 const VkAllocationCallbacks* pAllocator)
5321 {
5322 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5323 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5324 _callback, pAllocator, &instance->alloc);
5325 }
5326
5327 void
5328 radv_DebugReportMessageEXT(VkInstance _instance,
5329 VkDebugReportFlagsEXT flags,
5330 VkDebugReportObjectTypeEXT objectType,
5331 uint64_t object,
5332 size_t location,
5333 int32_t messageCode,
5334 const char* pLayerPrefix,
5335 const char* pMessage)
5336 {
5337 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5338 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5339 object, location, messageCode, pLayerPrefix, pMessage);
5340 }
5341
5342 void
5343 radv_GetDeviceGroupPeerMemoryFeatures(
5344 VkDevice device,
5345 uint32_t heapIndex,
5346 uint32_t localDeviceIndex,
5347 uint32_t remoteDeviceIndex,
5348 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5349 {
5350 assert(localDeviceIndex == remoteDeviceIndex);
5351
5352 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5353 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5354 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5355 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5356 }
5357
5358 static const VkTimeDomainEXT radv_time_domains[] = {
5359 VK_TIME_DOMAIN_DEVICE_EXT,
5360 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5361 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5362 };
5363
5364 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5365 VkPhysicalDevice physicalDevice,
5366 uint32_t *pTimeDomainCount,
5367 VkTimeDomainEXT *pTimeDomains)
5368 {
5369 int d;
5370 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5371
5372 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5373 vk_outarray_append(&out, i) {
5374 *i = radv_time_domains[d];
5375 }
5376 }
5377
5378 return vk_outarray_status(&out);
5379 }
5380
5381 static uint64_t
5382 radv_clock_gettime(clockid_t clock_id)
5383 {
5384 struct timespec current;
5385 int ret;
5386
5387 ret = clock_gettime(clock_id, &current);
5388 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5389 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5390 if (ret < 0)
5391 return 0;
5392
5393 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5394 }
5395
5396 VkResult radv_GetCalibratedTimestampsEXT(
5397 VkDevice _device,
5398 uint32_t timestampCount,
5399 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5400 uint64_t *pTimestamps,
5401 uint64_t *pMaxDeviation)
5402 {
5403 RADV_FROM_HANDLE(radv_device, device, _device);
5404 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5405 int d;
5406 uint64_t begin, end;
5407 uint64_t max_clock_period = 0;
5408
5409 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5410
5411 for (d = 0; d < timestampCount; d++) {
5412 switch (pTimestampInfos[d].timeDomain) {
5413 case VK_TIME_DOMAIN_DEVICE_EXT:
5414 pTimestamps[d] = device->ws->query_value(device->ws,
5415 RADEON_TIMESTAMP);
5416 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5417 max_clock_period = MAX2(max_clock_period, device_period);
5418 break;
5419 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5420 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5421 max_clock_period = MAX2(max_clock_period, 1);
5422 break;
5423
5424 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5425 pTimestamps[d] = begin;
5426 break;
5427 default:
5428 pTimestamps[d] = 0;
5429 break;
5430 }
5431 }
5432
5433 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5434
5435 /*
5436 * The maximum deviation is the sum of the interval over which we
5437 * perform the sampling and the maximum period of any sampled
5438 * clock. That's because the maximum skew between any two sampled
5439 * clock edges is when the sampled clock with the largest period is
5440 * sampled at the end of that period but right at the beginning of the
5441 * sampling interval and some other clock is sampled right at the
5442 * begining of its sampling period and right at the end of the
5443 * sampling interval. Let's assume the GPU has the longest clock
5444 * period and that the application is sampling GPU and monotonic:
5445 *
5446 * s e
5447 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5448 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5449 *
5450 * g
5451 * 0 1 2 3
5452 * GPU -----_____-----_____-----_____-----_____
5453 *
5454 * m
5455 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5456 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5457 *
5458 * Interval <----------------->
5459 * Deviation <-------------------------->
5460 *
5461 * s = read(raw) 2
5462 * g = read(GPU) 1
5463 * m = read(monotonic) 2
5464 * e = read(raw) b
5465 *
5466 * We round the sample interval up by one tick to cover sampling error
5467 * in the interval clock
5468 */
5469
5470 uint64_t sample_interval = end - begin + 1;
5471
5472 *pMaxDeviation = sample_interval + max_clock_period;
5473
5474 return VK_SUCCESS;
5475 }
5476
5477 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5478 VkPhysicalDevice physicalDevice,
5479 VkSampleCountFlagBits samples,
5480 VkMultisamplePropertiesEXT* pMultisampleProperties)
5481 {
5482 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5483 VK_SAMPLE_COUNT_4_BIT |
5484 VK_SAMPLE_COUNT_8_BIT)) {
5485 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5486 } else {
5487 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5488 }
5489 }