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radv: Fix hang width YCBCR array textures.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
116 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
117 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
118 default: chip_string = "AMD RADV unknown"; break;
119 }
120
121 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
122 }
123
124 static uint64_t
125 radv_get_visible_vram_size(struct radv_physical_device *device)
126 {
127 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
128 }
129
130 static uint64_t
131 radv_get_vram_size(struct radv_physical_device *device)
132 {
133 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
134 }
135
136 static void
137 radv_physical_device_init_mem_types(struct radv_physical_device *device)
138 {
139 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
140 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
141 uint64_t vram_size = radv_get_vram_size(device);
142 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
143 device->memory_properties.memoryHeapCount = 0;
144 if (vram_size > 0) {
145 vram_index = device->memory_properties.memoryHeapCount++;
146 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
147 .size = vram_size,
148 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
149 };
150 }
151 if (visible_vram_size) {
152 visible_vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
154 .size = visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (device->rad_info.gart_size > 0) {
159 gart_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
161 .size = device->rad_info.gart_size,
162 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165
166 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
167 unsigned type_count = 0;
168 if (vram_index >= 0) {
169 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
170 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
171 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
172 .heapIndex = vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
197 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
198 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
199 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
200 .heapIndex = gart_index,
201 };
202 }
203 device->memory_properties.memoryTypeCount = type_count;
204 }
205
206 static void
207 radv_handle_env_var_force_family(struct radv_physical_device *device)
208 {
209 const char *family = getenv("RADV_FORCE_FAMILY");
210 unsigned i;
211
212 if (!family)
213 return;
214
215 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
216 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
217 /* Override family and chip_class. */
218 device->rad_info.family = i;
219
220 if (i >= CHIP_VEGA10)
221 device->rad_info.chip_class = GFX9;
222 else if (i >= CHIP_TONGA)
223 device->rad_info.chip_class = VI;
224 else if (i >= CHIP_BONAIRE)
225 device->rad_info.chip_class = CIK;
226 else
227 device->rad_info.chip_class = SI;
228
229 return;
230 }
231 }
232
233 fprintf(stderr, "radv: Unknown family: %s\n", family);
234 exit(1);
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246 int master_fd = -1;
247
248 fd = open(path, O_RDWR | O_CLOEXEC);
249 if (fd < 0) {
250 if (instance->debug_flags & RADV_DEBUG_STARTUP)
251 radv_logi("Could not open device '%s'", path);
252
253 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
254 }
255
256 version = drmGetVersion(fd);
257 if (!version) {
258 close(fd);
259
260 if (instance->debug_flags & RADV_DEBUG_STARTUP)
261 radv_logi("Could not get the kernel driver version for device '%s'", path);
262
263 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
264 "failed to get version %s: %m", path);
265 }
266
267 if (strcmp(version->name, "amdgpu")) {
268 drmFreeVersion(version);
269 close(fd);
270
271 if (instance->debug_flags & RADV_DEBUG_STARTUP)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
273
274 return VK_ERROR_INCOMPATIBLE_DRIVER;
275 }
276 drmFreeVersion(version);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Found compatible device '%s'.", path);
280
281 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
282 device->instance = instance;
283
284 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
285 instance->perftest_flags);
286 if (!device->ws) {
287 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 goto fail;
289 }
290
291 if (instance->enabled_extensions.KHR_display) {
292 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
293 if (master_fd >= 0) {
294 uint32_t accel_working = 0;
295 struct drm_amdgpu_info request = {
296 .return_pointer = (uintptr_t)&accel_working,
297 .return_size = sizeof(accel_working),
298 .query = AMDGPU_INFO_ACCEL_WORKING
299 };
300
301 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
302 close(master_fd);
303 master_fd = -1;
304 }
305 }
306 }
307
308 device->master_fd = master_fd;
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311
312 radv_handle_env_var_force_family(device);
313
314 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
315
316 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
317 device->ws->destroy(device->ws);
318 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
319 "cannot generate UUID");
320 goto fail;
321 }
322
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags =
325 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
326 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
327
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
330 */
331 char buf[VK_UUID_SIZE * 2 + 1];
332 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
333 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
334
335 if (device->rad_info.chip_class < VI ||
336 device->rad_info.chip_class > GFX9)
337 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338
339 radv_get_driver_uuid(&device->driver_uuid);
340 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
341
342 if (device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.chip_class >= GFX9) {
344 device->has_rbplus = true;
345 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.family == CHIP_VEGA12 ||
347 device->rad_info.family == CHIP_RAVEN ||
348 device->rad_info.family == CHIP_RAVEN2;
349 }
350
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 * on SI.
353 */
354 device->has_clear_state = device->rad_info.chip_class >= CIK;
355
356 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
357
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
360 device->rad_info.family == CHIP_RAVEN;
361
362 /* Out-of-order primitive rasterization. */
363 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
364 device->rad_info.max_se >= 2;
365 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
366 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
367
368 device->dcc_msaa_allowed =
369 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
370
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
372 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
373 (device->rad_info.chip_class >= VI &&
374 device->rad_info.me_fw_feature >= 41);
375
376 radv_physical_device_init_mem_types(device);
377 radv_fill_device_extension_table(device, &device->supported_extensions);
378
379 device->bus_info = *drm_device->businfo.pci;
380
381 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
382 ac_print_gpu_info(&device->rad_info);
383
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
386 * semi-layers).
387 */
388 result = radv_init_wsi(device);
389 if (result != VK_SUCCESS) {
390 device->ws->destroy(device->ws);
391 vk_error(instance, result);
392 goto fail;
393 }
394
395 return VK_SUCCESS;
396
397 fail:
398 close(fd);
399 if (master_fd != -1)
400 close(master_fd);
401 return result;
402 }
403
404 static void
405 radv_physical_device_finish(struct radv_physical_device *device)
406 {
407 radv_finish_wsi(device);
408 device->ws->destroy(device->ws);
409 disk_cache_destroy(device->disk_cache);
410 close(device->local_fd);
411 if (device->master_fd != -1)
412 close(device->master_fd);
413 }
414
415 static void *
416 default_alloc_func(void *pUserData, size_t size, size_t align,
417 VkSystemAllocationScope allocationScope)
418 {
419 return malloc(size);
420 }
421
422 static void *
423 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
424 size_t align, VkSystemAllocationScope allocationScope)
425 {
426 return realloc(pOriginal, size);
427 }
428
429 static void
430 default_free_func(void *pUserData, void *pMemory)
431 {
432 free(pMemory);
433 }
434
435 static const VkAllocationCallbacks default_alloc = {
436 .pUserData = NULL,
437 .pfnAllocation = default_alloc_func,
438 .pfnReallocation = default_realloc_func,
439 .pfnFree = default_free_func,
440 };
441
442 static const struct debug_control radv_debug_options[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
444 {"nodcc", RADV_DEBUG_NO_DCC},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS},
446 {"nocache", RADV_DEBUG_NO_CACHE},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
448 {"nohiz", RADV_DEBUG_NO_HIZ},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
451 {"allbos", RADV_DEBUG_ALL_BOS},
452 {"noibs", RADV_DEBUG_NO_IBS},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
457 {"nosisched", RADV_DEBUG_NO_SISCHED},
458 {"preoptir", RADV_DEBUG_PREOPTIR},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
461 {"info", RADV_DEBUG_INFO},
462 {"errors", RADV_DEBUG_ERRORS},
463 {"startup", RADV_DEBUG_STARTUP},
464 {"checkir", RADV_DEBUG_CHECKIR},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
466 {"nobinning", RADV_DEBUG_NOBINNING},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
482 {"bolist", RADV_PERFTEST_BO_LIST},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525 static const char radv_dri_options_xml[] =
526 DRI_CONF_BEGIN
527 DRI_CONF_SECTION_QUALITY
528 DRI_CONF_ADAPTIVE_SYNC("true")
529 DRI_CONF_SECTION_END
530 DRI_CONF_END;
531
532 static void radv_init_dri_options(struct radv_instance *instance)
533 {
534 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
535 driParseConfigFiles(&instance->dri_options,
536 &instance->available_dri_options,
537 0, "radv", NULL);
538 }
539
540 VkResult radv_CreateInstance(
541 const VkInstanceCreateInfo* pCreateInfo,
542 const VkAllocationCallbacks* pAllocator,
543 VkInstance* pInstance)
544 {
545 struct radv_instance *instance;
546 VkResult result;
547
548 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
549
550 uint32_t client_version;
551 if (pCreateInfo->pApplicationInfo &&
552 pCreateInfo->pApplicationInfo->apiVersion != 0) {
553 client_version = pCreateInfo->pApplicationInfo->apiVersion;
554 } else {
555 client_version = VK_API_VERSION_1_0;
556 }
557
558 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
559 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
560 if (!instance)
561 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
562
563 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
564
565 if (pAllocator)
566 instance->alloc = *pAllocator;
567 else
568 instance->alloc = default_alloc;
569
570 instance->apiVersion = client_version;
571 instance->physicalDeviceCount = -1;
572
573 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
574 radv_debug_options);
575
576 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
577 radv_perftest_options);
578
579
580 if (instance->debug_flags & RADV_DEBUG_STARTUP)
581 radv_logi("Created an instance");
582
583 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
584 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
585 int index = radv_get_instance_extension_index(ext_name);
586
587 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
588 vk_free2(&default_alloc, pAllocator, instance);
589 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
590 }
591
592 instance->enabled_extensions.extensions[index] = true;
593 }
594
595 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
596 if (result != VK_SUCCESS) {
597 vk_free2(&default_alloc, pAllocator, instance);
598 return vk_error(instance, result);
599 }
600
601 _mesa_locale_init();
602 glsl_type_singleton_init_or_ref();
603
604 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
605
606 radv_init_dri_options(instance);
607 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
608
609 *pInstance = radv_instance_to_handle(instance);
610
611 return VK_SUCCESS;
612 }
613
614 void radv_DestroyInstance(
615 VkInstance _instance,
616 const VkAllocationCallbacks* pAllocator)
617 {
618 RADV_FROM_HANDLE(radv_instance, instance, _instance);
619
620 if (!instance)
621 return;
622
623 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
624 radv_physical_device_finish(instance->physicalDevices + i);
625 }
626
627 VG(VALGRIND_DESTROY_MEMPOOL(instance));
628
629 glsl_type_singleton_decref();
630 _mesa_locale_fini();
631
632 driDestroyOptionCache(&instance->dri_options);
633 driDestroyOptionInfo(&instance->available_dri_options);
634
635 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
636
637 vk_free(&instance->alloc, instance);
638 }
639
640 static VkResult
641 radv_enumerate_devices(struct radv_instance *instance)
642 {
643 /* TODO: Check for more devices ? */
644 drmDevicePtr devices[8];
645 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
646 int max_devices;
647
648 instance->physicalDeviceCount = 0;
649
650 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
651
652 if (instance->debug_flags & RADV_DEBUG_STARTUP)
653 radv_logi("Found %d drm nodes", max_devices);
654
655 if (max_devices < 1)
656 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
657
658 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
659 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
660 devices[i]->bustype == DRM_BUS_PCI &&
661 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
662
663 result = radv_physical_device_init(instance->physicalDevices +
664 instance->physicalDeviceCount,
665 instance,
666 devices[i]);
667 if (result == VK_SUCCESS)
668 ++instance->physicalDeviceCount;
669 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 break;
671 }
672 }
673 drmFreeDevices(devices, max_devices);
674
675 return result;
676 }
677
678 VkResult radv_EnumeratePhysicalDevices(
679 VkInstance _instance,
680 uint32_t* pPhysicalDeviceCount,
681 VkPhysicalDevice* pPhysicalDevices)
682 {
683 RADV_FROM_HANDLE(radv_instance, instance, _instance);
684 VkResult result;
685
686 if (instance->physicalDeviceCount < 0) {
687 result = radv_enumerate_devices(instance);
688 if (result != VK_SUCCESS &&
689 result != VK_ERROR_INCOMPATIBLE_DRIVER)
690 return result;
691 }
692
693 if (!pPhysicalDevices) {
694 *pPhysicalDeviceCount = instance->physicalDeviceCount;
695 } else {
696 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
697 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
698 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
699 }
700
701 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
702 : VK_SUCCESS;
703 }
704
705 VkResult radv_EnumeratePhysicalDeviceGroups(
706 VkInstance _instance,
707 uint32_t* pPhysicalDeviceGroupCount,
708 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
709 {
710 RADV_FROM_HANDLE(radv_instance, instance, _instance);
711 VkResult result;
712
713 if (instance->physicalDeviceCount < 0) {
714 result = radv_enumerate_devices(instance);
715 if (result != VK_SUCCESS &&
716 result != VK_ERROR_INCOMPATIBLE_DRIVER)
717 return result;
718 }
719
720 if (!pPhysicalDeviceGroupProperties) {
721 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
722 } else {
723 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
724 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
725 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
726 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
727 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
728 }
729 }
730 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
731 : VK_SUCCESS;
732 }
733
734 void radv_GetPhysicalDeviceFeatures(
735 VkPhysicalDevice physicalDevice,
736 VkPhysicalDeviceFeatures* pFeatures)
737 {
738 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
739 memset(pFeatures, 0, sizeof(*pFeatures));
740
741 *pFeatures = (VkPhysicalDeviceFeatures) {
742 .robustBufferAccess = true,
743 .fullDrawIndexUint32 = true,
744 .imageCubeArray = true,
745 .independentBlend = true,
746 .geometryShader = true,
747 .tessellationShader = true,
748 .sampleRateShading = true,
749 .dualSrcBlend = true,
750 .logicOp = true,
751 .multiDrawIndirect = true,
752 .drawIndirectFirstInstance = true,
753 .depthClamp = true,
754 .depthBiasClamp = true,
755 .fillModeNonSolid = true,
756 .depthBounds = true,
757 .wideLines = true,
758 .largePoints = true,
759 .alphaToOne = true,
760 .multiViewport = true,
761 .samplerAnisotropy = true,
762 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
763 .textureCompressionASTC_LDR = false,
764 .textureCompressionBC = true,
765 .occlusionQueryPrecise = true,
766 .pipelineStatisticsQuery = true,
767 .vertexPipelineStoresAndAtomics = true,
768 .fragmentStoresAndAtomics = true,
769 .shaderTessellationAndGeometryPointSize = true,
770 .shaderImageGatherExtended = true,
771 .shaderStorageImageExtendedFormats = true,
772 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
773 .shaderUniformBufferArrayDynamicIndexing = true,
774 .shaderSampledImageArrayDynamicIndexing = true,
775 .shaderStorageBufferArrayDynamicIndexing = true,
776 .shaderStorageImageArrayDynamicIndexing = true,
777 .shaderStorageImageReadWithoutFormat = true,
778 .shaderStorageImageWriteWithoutFormat = true,
779 .shaderClipDistance = true,
780 .shaderCullDistance = true,
781 .shaderFloat64 = true,
782 .shaderInt64 = true,
783 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
784 .sparseBinding = true,
785 .variableMultisampleRate = true,
786 .inheritedQueries = true,
787 };
788 }
789
790 void radv_GetPhysicalDeviceFeatures2(
791 VkPhysicalDevice physicalDevice,
792 VkPhysicalDeviceFeatures2 *pFeatures)
793 {
794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
795 vk_foreach_struct(ext, pFeatures->pNext) {
796 switch (ext->sType) {
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
798 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
799 features->variablePointersStorageBuffer = true;
800 features->variablePointers = true;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
804 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
805 features->multiview = true;
806 features->multiviewGeometryShader = true;
807 features->multiviewTessellationShader = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
811 VkPhysicalDeviceShaderDrawParametersFeatures *features =
812 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
813 features->shaderDrawParameters = true;
814 break;
815 }
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
817 VkPhysicalDeviceProtectedMemoryFeatures *features =
818 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
819 features->protectedMemory = false;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
823 VkPhysicalDevice16BitStorageFeatures *features =
824 (VkPhysicalDevice16BitStorageFeatures*)ext;
825 bool enabled = pdevice->rad_info.chip_class >= VI;
826 features->storageBuffer16BitAccess = enabled;
827 features->uniformAndStorageBuffer16BitAccess = enabled;
828 features->storagePushConstant16 = enabled;
829 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
833 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
834 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
835 features->samplerYcbcrConversion = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
839 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
840 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
841 features->shaderInputAttachmentArrayDynamicIndexing = true;
842 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
843 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
844 features->shaderUniformBufferArrayNonUniformIndexing = true;
845 features->shaderSampledImageArrayNonUniformIndexing = true;
846 features->shaderStorageBufferArrayNonUniformIndexing = true;
847 features->shaderStorageImageArrayNonUniformIndexing = true;
848 features->shaderInputAttachmentArrayNonUniformIndexing = true;
849 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
850 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
851 features->descriptorBindingUniformBufferUpdateAfterBind = true;
852 features->descriptorBindingSampledImageUpdateAfterBind = true;
853 features->descriptorBindingStorageImageUpdateAfterBind = true;
854 features->descriptorBindingStorageBufferUpdateAfterBind = true;
855 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
856 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
857 features->descriptorBindingUpdateUnusedWhilePending = true;
858 features->descriptorBindingPartiallyBound = true;
859 features->descriptorBindingVariableDescriptorCount = true;
860 features->runtimeDescriptorArray = true;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
864 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
865 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
866 features->conditionalRendering = true;
867 features->inheritedConditionalRendering = false;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
871 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
872 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
873 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
874 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
878 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
879 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
880 features->transformFeedback = true;
881 features->geometryStreams = true;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
885 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
886 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
887 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
891 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
892 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
893 features->memoryPriority = VK_TRUE;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
897 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
898 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
899 features->bufferDeviceAddress = true;
900 features->bufferDeviceAddressCaptureReplay = false;
901 features->bufferDeviceAddressMultiDevice = false;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
905 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
906 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
907 features->depthClipEnable = true;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
911 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
912 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
913 features->hostQueryReset = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
917 VkPhysicalDevice8BitStorageFeaturesKHR *features =
918 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
919 bool enabled = pdevice->rad_info.chip_class >= VI;
920 features->storageBuffer8BitAccess = enabled;
921 features->uniformAndStorageBuffer8BitAccess = enabled;
922 features->storagePushConstant8 = enabled;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
926 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
927 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
928 features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800;
929 features->shaderInt8 = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
933 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
934 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
935 /* TODO: Enable this once the driver supports 64-bit
936 * compare&swap atomic operations.
937 */
938 features->shaderBufferInt64Atomics = false;
939 features->shaderSharedInt64Atomics = false;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
943 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
944 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
945
946 features->inlineUniformBlock = true;
947 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
948 break;
949 }
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
951 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
952 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
953 features->computeDerivativeGroupQuads = false;
954 features->computeDerivativeGroupLinear = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
958 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
959 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
960 features->ycbcrImageArrays = true;
961 break;
962 }
963 default:
964 break;
965 }
966 }
967 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
968 }
969
970 void radv_GetPhysicalDeviceProperties(
971 VkPhysicalDevice physicalDevice,
972 VkPhysicalDeviceProperties* pProperties)
973 {
974 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
975 VkSampleCountFlags sample_counts = 0xf;
976
977 /* make sure that the entire descriptor set is addressable with a signed
978 * 32-bit int. So the sum of all limits scaled by descriptor size has to
979 * be at most 2 GiB. the combined image & samples object count as one of
980 * both. This limit is for the pipeline layout, not for the set layout, but
981 * there is no set limit, so we just set a pipeline limit. I don't think
982 * any app is going to hit this soon. */
983 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
984 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
985 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
986 32 /* sampler, largest when combined with image */ +
987 64 /* sampled image */ +
988 64 /* storage image */);
989
990 VkPhysicalDeviceLimits limits = {
991 .maxImageDimension1D = (1 << 14),
992 .maxImageDimension2D = (1 << 14),
993 .maxImageDimension3D = (1 << 11),
994 .maxImageDimensionCube = (1 << 14),
995 .maxImageArrayLayers = (1 << 11),
996 .maxTexelBufferElements = 128 * 1024 * 1024,
997 .maxUniformBufferRange = UINT32_MAX,
998 .maxStorageBufferRange = UINT32_MAX,
999 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1000 .maxMemoryAllocationCount = UINT32_MAX,
1001 .maxSamplerAllocationCount = 64 * 1024,
1002 .bufferImageGranularity = 64, /* A cache line */
1003 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1004 .maxBoundDescriptorSets = MAX_SETS,
1005 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1006 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1007 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1008 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1009 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1010 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1011 .maxPerStageResources = max_descriptor_set_size,
1012 .maxDescriptorSetSamplers = max_descriptor_set_size,
1013 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1014 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1015 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1016 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1017 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1018 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1019 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1020 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1021 .maxVertexInputBindings = MAX_VBS,
1022 .maxVertexInputAttributeOffset = 2047,
1023 .maxVertexInputBindingStride = 2048,
1024 .maxVertexOutputComponents = 128,
1025 .maxTessellationGenerationLevel = 64,
1026 .maxTessellationPatchSize = 32,
1027 .maxTessellationControlPerVertexInputComponents = 128,
1028 .maxTessellationControlPerVertexOutputComponents = 128,
1029 .maxTessellationControlPerPatchOutputComponents = 120,
1030 .maxTessellationControlTotalOutputComponents = 4096,
1031 .maxTessellationEvaluationInputComponents = 128,
1032 .maxTessellationEvaluationOutputComponents = 128,
1033 .maxGeometryShaderInvocations = 127,
1034 .maxGeometryInputComponents = 64,
1035 .maxGeometryOutputComponents = 128,
1036 .maxGeometryOutputVertices = 256,
1037 .maxGeometryTotalOutputComponents = 1024,
1038 .maxFragmentInputComponents = 128,
1039 .maxFragmentOutputAttachments = 8,
1040 .maxFragmentDualSrcAttachments = 1,
1041 .maxFragmentCombinedOutputResources = 8,
1042 .maxComputeSharedMemorySize = 32768,
1043 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1044 .maxComputeWorkGroupInvocations = 2048,
1045 .maxComputeWorkGroupSize = {
1046 2048,
1047 2048,
1048 2048
1049 },
1050 .subPixelPrecisionBits = 8,
1051 .subTexelPrecisionBits = 8,
1052 .mipmapPrecisionBits = 8,
1053 .maxDrawIndexedIndexValue = UINT32_MAX,
1054 .maxDrawIndirectCount = UINT32_MAX,
1055 .maxSamplerLodBias = 16,
1056 .maxSamplerAnisotropy = 16,
1057 .maxViewports = MAX_VIEWPORTS,
1058 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1059 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1060 .viewportSubPixelBits = 8,
1061 .minMemoryMapAlignment = 4096, /* A page */
1062 .minTexelBufferOffsetAlignment = 1,
1063 .minUniformBufferOffsetAlignment = 4,
1064 .minStorageBufferOffsetAlignment = 4,
1065 .minTexelOffset = -32,
1066 .maxTexelOffset = 31,
1067 .minTexelGatherOffset = -32,
1068 .maxTexelGatherOffset = 31,
1069 .minInterpolationOffset = -2,
1070 .maxInterpolationOffset = 2,
1071 .subPixelInterpolationOffsetBits = 8,
1072 .maxFramebufferWidth = (1 << 14),
1073 .maxFramebufferHeight = (1 << 14),
1074 .maxFramebufferLayers = (1 << 10),
1075 .framebufferColorSampleCounts = sample_counts,
1076 .framebufferDepthSampleCounts = sample_counts,
1077 .framebufferStencilSampleCounts = sample_counts,
1078 .framebufferNoAttachmentsSampleCounts = sample_counts,
1079 .maxColorAttachments = MAX_RTS,
1080 .sampledImageColorSampleCounts = sample_counts,
1081 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1082 .sampledImageDepthSampleCounts = sample_counts,
1083 .sampledImageStencilSampleCounts = sample_counts,
1084 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1085 .maxSampleMaskWords = 1,
1086 .timestampComputeAndGraphics = true,
1087 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1088 .maxClipDistances = 8,
1089 .maxCullDistances = 8,
1090 .maxCombinedClipAndCullDistances = 8,
1091 .discreteQueuePriorities = 2,
1092 .pointSizeRange = { 0.0, 8192.0 },
1093 .lineWidthRange = { 0.0, 7.9921875 },
1094 .pointSizeGranularity = (1.0 / 8.0),
1095 .lineWidthGranularity = (1.0 / 128.0),
1096 .strictLines = false, /* FINISHME */
1097 .standardSampleLocations = true,
1098 .optimalBufferCopyOffsetAlignment = 128,
1099 .optimalBufferCopyRowPitchAlignment = 128,
1100 .nonCoherentAtomSize = 64,
1101 };
1102
1103 *pProperties = (VkPhysicalDeviceProperties) {
1104 .apiVersion = radv_physical_device_api_version(pdevice),
1105 .driverVersion = vk_get_driver_version(),
1106 .vendorID = ATI_VENDOR_ID,
1107 .deviceID = pdevice->rad_info.pci_id,
1108 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1109 .limits = limits,
1110 .sparseProperties = {0},
1111 };
1112
1113 strcpy(pProperties->deviceName, pdevice->name);
1114 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1115 }
1116
1117 void radv_GetPhysicalDeviceProperties2(
1118 VkPhysicalDevice physicalDevice,
1119 VkPhysicalDeviceProperties2 *pProperties)
1120 {
1121 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1122 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1123
1124 vk_foreach_struct(ext, pProperties->pNext) {
1125 switch (ext->sType) {
1126 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1127 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1128 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1129 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1133 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1134 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1135 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1136 properties->deviceLUIDValid = false;
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1140 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1141 properties->maxMultiviewViewCount = MAX_VIEWS;
1142 properties->maxMultiviewInstanceIndex = INT_MAX;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1146 VkPhysicalDevicePointClippingProperties *properties =
1147 (VkPhysicalDevicePointClippingProperties*)ext;
1148 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1152 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1153 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1154 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1158 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1159 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1160 properties->minImportedHostPointerAlignment = 4096;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1164 VkPhysicalDeviceSubgroupProperties *properties =
1165 (VkPhysicalDeviceSubgroupProperties*)ext;
1166 properties->subgroupSize = 64;
1167 properties->supportedStages = VK_SHADER_STAGE_ALL;
1168 properties->supportedOperations =
1169 VK_SUBGROUP_FEATURE_BASIC_BIT |
1170 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1171 VK_SUBGROUP_FEATURE_QUAD_BIT |
1172 VK_SUBGROUP_FEATURE_VOTE_BIT;
1173 if (pdevice->rad_info.chip_class >= VI) {
1174 properties->supportedOperations |=
1175 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1176 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1177 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1178 }
1179 properties->quadOperationsInAllStages = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1183 VkPhysicalDeviceMaintenance3Properties *properties =
1184 (VkPhysicalDeviceMaintenance3Properties*)ext;
1185 /* Make sure everything is addressable by a signed 32-bit int, and
1186 * our largest descriptors are 96 bytes. */
1187 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1188 /* Our buffer size fields allow only this much */
1189 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1190 break;
1191 }
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1193 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1194 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1195 /* GFX6-8 only support single channel min/max filter. */
1196 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1197 properties->filterMinmaxSingleComponentFormats = true;
1198 break;
1199 }
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1201 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1202 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1203
1204 /* Shader engines. */
1205 properties->shaderEngineCount =
1206 pdevice->rad_info.max_se;
1207 properties->shaderArraysPerEngineCount =
1208 pdevice->rad_info.max_sh_per_se;
1209 properties->computeUnitsPerShaderArray =
1210 pdevice->rad_info.num_good_cu_per_sh;
1211 properties->simdPerComputeUnit = 4;
1212 properties->wavefrontsPerSimd =
1213 pdevice->rad_info.family == CHIP_TONGA ||
1214 pdevice->rad_info.family == CHIP_ICELAND ||
1215 pdevice->rad_info.family == CHIP_POLARIS10 ||
1216 pdevice->rad_info.family == CHIP_POLARIS11 ||
1217 pdevice->rad_info.family == CHIP_POLARIS12 ||
1218 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1219 properties->wavefrontSize = 64;
1220
1221 /* SGPR. */
1222 properties->sgprsPerSimd =
1223 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1224 properties->minSgprAllocation =
1225 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1226 properties->maxSgprAllocation =
1227 pdevice->rad_info.family == CHIP_TONGA ||
1228 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1229 properties->sgprAllocationGranularity =
1230 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1231
1232 /* VGPR. */
1233 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1234 properties->minVgprAllocation = 4;
1235 properties->maxVgprAllocation = 256;
1236 properties->vgprAllocationGranularity = 4;
1237 break;
1238 }
1239 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1240 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1241 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1242 properties->maxVertexAttribDivisor = UINT32_MAX;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1246 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1247 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1248 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1249 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1250 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1251 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1252 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1253 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1254 properties->robustBufferAccessUpdateAfterBind = false;
1255 properties->quadDivergentImplicitLod = false;
1256
1257 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1258 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1259 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1260 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1261 32 /* sampler, largest when combined with image */ +
1262 64 /* sampled image */ +
1263 64 /* storage image */);
1264 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1265 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1266 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1267 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1268 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1269 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1270 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1271 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1272 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1273 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1274 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1275 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1276 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1277 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1278 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1279 break;
1280 }
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1282 VkPhysicalDeviceProtectedMemoryProperties *properties =
1283 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1284 properties->protectedNoFault = false;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1288 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1289 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1290 properties->primitiveOverestimationSize = 0;
1291 properties->maxExtraPrimitiveOverestimationSize = 0;
1292 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1293 properties->primitiveUnderestimation = VK_FALSE;
1294 properties->conservativePointAndLineRasterization = VK_FALSE;
1295 properties->degenerateTrianglesRasterized = VK_FALSE;
1296 properties->degenerateLinesRasterized = VK_FALSE;
1297 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1298 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1302 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1303 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1304 properties->pciDomain = pdevice->bus_info.domain;
1305 properties->pciBus = pdevice->bus_info.bus;
1306 properties->pciDevice = pdevice->bus_info.dev;
1307 properties->pciFunction = pdevice->bus_info.func;
1308 break;
1309 }
1310 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1311 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1312 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1313
1314 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1315 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1316 strcpy(driver_props->driverName, "radv");
1317
1318 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1319 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1320 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1321 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1322
1323 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1324 .major = 1,
1325 .minor = 1,
1326 .subminor = 2,
1327 .patch = 0,
1328 };
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1332 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1333 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1334 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1335 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1336 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1337 properties->maxTransformFeedbackStreamDataSize = 512;
1338 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1339 properties->maxTransformFeedbackBufferDataStride = 512;
1340 properties->transformFeedbackQueries = true;
1341 properties->transformFeedbackStreamsLinesTriangles = false;
1342 properties->transformFeedbackRasterizationStreamSelect = false;
1343 properties->transformFeedbackDraw = true;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1347 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1348 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1349
1350 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1351 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1352 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1353 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1354 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1355 break;
1356 }
1357 default:
1358 break;
1359 }
1360 }
1361 }
1362
1363 static void radv_get_physical_device_queue_family_properties(
1364 struct radv_physical_device* pdevice,
1365 uint32_t* pCount,
1366 VkQueueFamilyProperties** pQueueFamilyProperties)
1367 {
1368 int num_queue_families = 1;
1369 int idx;
1370 if (pdevice->rad_info.num_compute_rings > 0 &&
1371 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1372 num_queue_families++;
1373
1374 if (pQueueFamilyProperties == NULL) {
1375 *pCount = num_queue_families;
1376 return;
1377 }
1378
1379 if (!*pCount)
1380 return;
1381
1382 idx = 0;
1383 if (*pCount >= 1) {
1384 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1385 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1386 VK_QUEUE_COMPUTE_BIT |
1387 VK_QUEUE_TRANSFER_BIT |
1388 VK_QUEUE_SPARSE_BINDING_BIT,
1389 .queueCount = 1,
1390 .timestampValidBits = 64,
1391 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1392 };
1393 idx++;
1394 }
1395
1396 if (pdevice->rad_info.num_compute_rings > 0 &&
1397 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1398 if (*pCount > idx) {
1399 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1400 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1401 VK_QUEUE_TRANSFER_BIT |
1402 VK_QUEUE_SPARSE_BINDING_BIT,
1403 .queueCount = pdevice->rad_info.num_compute_rings,
1404 .timestampValidBits = 64,
1405 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1406 };
1407 idx++;
1408 }
1409 }
1410 *pCount = idx;
1411 }
1412
1413 void radv_GetPhysicalDeviceQueueFamilyProperties(
1414 VkPhysicalDevice physicalDevice,
1415 uint32_t* pCount,
1416 VkQueueFamilyProperties* pQueueFamilyProperties)
1417 {
1418 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1419 if (!pQueueFamilyProperties) {
1420 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1421 return;
1422 }
1423 VkQueueFamilyProperties *properties[] = {
1424 pQueueFamilyProperties + 0,
1425 pQueueFamilyProperties + 1,
1426 pQueueFamilyProperties + 2,
1427 };
1428 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1429 assert(*pCount <= 3);
1430 }
1431
1432 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1433 VkPhysicalDevice physicalDevice,
1434 uint32_t* pCount,
1435 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1436 {
1437 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1438 if (!pQueueFamilyProperties) {
1439 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1440 return;
1441 }
1442 VkQueueFamilyProperties *properties[] = {
1443 &pQueueFamilyProperties[0].queueFamilyProperties,
1444 &pQueueFamilyProperties[1].queueFamilyProperties,
1445 &pQueueFamilyProperties[2].queueFamilyProperties,
1446 };
1447 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1448 assert(*pCount <= 3);
1449 }
1450
1451 void radv_GetPhysicalDeviceMemoryProperties(
1452 VkPhysicalDevice physicalDevice,
1453 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1454 {
1455 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1456
1457 *pMemoryProperties = physical_device->memory_properties;
1458 }
1459
1460 static void
1461 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1462 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1463 {
1464 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1465 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1466 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1467 uint64_t vram_size = radv_get_vram_size(device);
1468 uint64_t gtt_size = device->rad_info.gart_size;
1469 uint64_t heap_budget, heap_usage;
1470
1471 /* For all memory heaps, the computation of budget is as follow:
1472 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1473 *
1474 * The Vulkan spec 1.1.97 says that the budget should include any
1475 * currently allocated device memory.
1476 *
1477 * Note that the application heap usages are not really accurate (eg.
1478 * in presence of shared buffers).
1479 */
1480 if (vram_size) {
1481 heap_usage = device->ws->query_value(device->ws,
1482 RADEON_ALLOCATED_VRAM);
1483
1484 heap_budget = vram_size -
1485 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1486 heap_usage;
1487
1488 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1489 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1490 }
1491
1492 if (visible_vram_size) {
1493 heap_usage = device->ws->query_value(device->ws,
1494 RADEON_ALLOCATED_VRAM_VIS);
1495
1496 heap_budget = visible_vram_size -
1497 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1498 heap_usage;
1499
1500 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1501 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1502 }
1503
1504 if (gtt_size) {
1505 heap_usage = device->ws->query_value(device->ws,
1506 RADEON_ALLOCATED_GTT);
1507
1508 heap_budget = gtt_size -
1509 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1510 heap_usage;
1511
1512 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1513 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1514 }
1515
1516 /* The heapBudget and heapUsage values must be zero for array elements
1517 * greater than or equal to
1518 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1519 */
1520 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1521 memoryBudget->heapBudget[i] = 0;
1522 memoryBudget->heapUsage[i] = 0;
1523 }
1524 }
1525
1526 void radv_GetPhysicalDeviceMemoryProperties2(
1527 VkPhysicalDevice physicalDevice,
1528 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1529 {
1530 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1531 &pMemoryProperties->memoryProperties);
1532
1533 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1534 vk_find_struct(pMemoryProperties->pNext,
1535 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1536 if (memory_budget)
1537 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1538 }
1539
1540 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1541 VkDevice _device,
1542 VkExternalMemoryHandleTypeFlagBits handleType,
1543 const void *pHostPointer,
1544 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1545 {
1546 RADV_FROM_HANDLE(radv_device, device, _device);
1547
1548 switch (handleType)
1549 {
1550 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1551 const struct radv_physical_device *physical_device = device->physical_device;
1552 uint32_t memoryTypeBits = 0;
1553 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1554 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1555 memoryTypeBits = (1 << i);
1556 break;
1557 }
1558 }
1559 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1560 return VK_SUCCESS;
1561 }
1562 default:
1563 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1564 }
1565 }
1566
1567 static enum radeon_ctx_priority
1568 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1569 {
1570 /* Default to MEDIUM when a specific global priority isn't requested */
1571 if (!pObj)
1572 return RADEON_CTX_PRIORITY_MEDIUM;
1573
1574 switch(pObj->globalPriority) {
1575 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1576 return RADEON_CTX_PRIORITY_REALTIME;
1577 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1578 return RADEON_CTX_PRIORITY_HIGH;
1579 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1580 return RADEON_CTX_PRIORITY_MEDIUM;
1581 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1582 return RADEON_CTX_PRIORITY_LOW;
1583 default:
1584 unreachable("Illegal global priority value");
1585 return RADEON_CTX_PRIORITY_INVALID;
1586 }
1587 }
1588
1589 static int
1590 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1591 uint32_t queue_family_index, int idx,
1592 VkDeviceQueueCreateFlags flags,
1593 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1594 {
1595 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1596 queue->device = device;
1597 queue->queue_family_index = queue_family_index;
1598 queue->queue_idx = idx;
1599 queue->priority = radv_get_queue_global_priority(global_priority);
1600 queue->flags = flags;
1601
1602 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1603 if (!queue->hw_ctx)
1604 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1605
1606 return VK_SUCCESS;
1607 }
1608
1609 static void
1610 radv_queue_finish(struct radv_queue *queue)
1611 {
1612 if (queue->hw_ctx)
1613 queue->device->ws->ctx_destroy(queue->hw_ctx);
1614
1615 if (queue->initial_full_flush_preamble_cs)
1616 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1617 if (queue->initial_preamble_cs)
1618 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1619 if (queue->continue_preamble_cs)
1620 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1621 if (queue->descriptor_bo)
1622 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1623 if (queue->scratch_bo)
1624 queue->device->ws->buffer_destroy(queue->scratch_bo);
1625 if (queue->esgs_ring_bo)
1626 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1627 if (queue->gsvs_ring_bo)
1628 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1629 if (queue->tess_rings_bo)
1630 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1631 if (queue->compute_scratch_bo)
1632 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1633 }
1634
1635 static void
1636 radv_bo_list_init(struct radv_bo_list *bo_list)
1637 {
1638 pthread_mutex_init(&bo_list->mutex, NULL);
1639 bo_list->list.count = bo_list->capacity = 0;
1640 bo_list->list.bos = NULL;
1641 }
1642
1643 static void
1644 radv_bo_list_finish(struct radv_bo_list *bo_list)
1645 {
1646 free(bo_list->list.bos);
1647 pthread_mutex_destroy(&bo_list->mutex);
1648 }
1649
1650 static VkResult radv_bo_list_add(struct radv_device *device,
1651 struct radeon_winsys_bo *bo)
1652 {
1653 struct radv_bo_list *bo_list = &device->bo_list;
1654
1655 if (bo->is_local)
1656 return VK_SUCCESS;
1657
1658 if (unlikely(!device->use_global_bo_list))
1659 return VK_SUCCESS;
1660
1661 pthread_mutex_lock(&bo_list->mutex);
1662 if (bo_list->list.count == bo_list->capacity) {
1663 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1664 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1665
1666 if (!data) {
1667 pthread_mutex_unlock(&bo_list->mutex);
1668 return VK_ERROR_OUT_OF_HOST_MEMORY;
1669 }
1670
1671 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1672 bo_list->capacity = capacity;
1673 }
1674
1675 bo_list->list.bos[bo_list->list.count++] = bo;
1676 pthread_mutex_unlock(&bo_list->mutex);
1677 return VK_SUCCESS;
1678 }
1679
1680 static void radv_bo_list_remove(struct radv_device *device,
1681 struct radeon_winsys_bo *bo)
1682 {
1683 struct radv_bo_list *bo_list = &device->bo_list;
1684
1685 if (bo->is_local)
1686 return;
1687
1688 if (unlikely(!device->use_global_bo_list))
1689 return;
1690
1691 pthread_mutex_lock(&bo_list->mutex);
1692 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1693 if (bo_list->list.bos[i] == bo) {
1694 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1695 --bo_list->list.count;
1696 break;
1697 }
1698 }
1699 pthread_mutex_unlock(&bo_list->mutex);
1700 }
1701
1702 static void
1703 radv_device_init_gs_info(struct radv_device *device)
1704 {
1705 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1706 device->physical_device->rad_info.family);
1707 }
1708
1709 static int radv_get_device_extension_index(const char *name)
1710 {
1711 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1712 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1713 return i;
1714 }
1715 return -1;
1716 }
1717
1718 static int
1719 radv_get_int_debug_option(const char *name, int default_value)
1720 {
1721 const char *str;
1722 int result;
1723
1724 str = getenv(name);
1725 if (!str) {
1726 result = default_value;
1727 } else {
1728 char *endptr;
1729
1730 result = strtol(str, &endptr, 0);
1731 if (str == endptr) {
1732 /* No digits founs. */
1733 result = default_value;
1734 }
1735 }
1736
1737 return result;
1738 }
1739
1740 VkResult radv_CreateDevice(
1741 VkPhysicalDevice physicalDevice,
1742 const VkDeviceCreateInfo* pCreateInfo,
1743 const VkAllocationCallbacks* pAllocator,
1744 VkDevice* pDevice)
1745 {
1746 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1747 VkResult result;
1748 struct radv_device *device;
1749
1750 bool keep_shader_info = false;
1751
1752 /* Check enabled features */
1753 if (pCreateInfo->pEnabledFeatures) {
1754 VkPhysicalDeviceFeatures supported_features;
1755 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1756 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1757 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1758 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1759 for (uint32_t i = 0; i < num_features; i++) {
1760 if (enabled_feature[i] && !supported_feature[i])
1761 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1762 }
1763 }
1764
1765 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1766 sizeof(*device), 8,
1767 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1768 if (!device)
1769 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1770
1771 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1772 device->instance = physical_device->instance;
1773 device->physical_device = physical_device;
1774
1775 device->ws = physical_device->ws;
1776 if (pAllocator)
1777 device->alloc = *pAllocator;
1778 else
1779 device->alloc = physical_device->instance->alloc;
1780
1781 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1782 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1783 int index = radv_get_device_extension_index(ext_name);
1784 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1785 vk_free(&device->alloc, device);
1786 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1787 }
1788
1789 device->enabled_extensions.extensions[index] = true;
1790 }
1791
1792 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1793
1794 /* With update after bind we can't attach bo's to the command buffer
1795 * from the descriptor set anymore, so we have to use a global BO list.
1796 */
1797 device->use_global_bo_list =
1798 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1799 device->enabled_extensions.EXT_descriptor_indexing ||
1800 device->enabled_extensions.EXT_buffer_device_address;
1801
1802 mtx_init(&device->shader_slab_mutex, mtx_plain);
1803 list_inithead(&device->shader_slabs);
1804
1805 radv_bo_list_init(&device->bo_list);
1806
1807 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1808 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1809 uint32_t qfi = queue_create->queueFamilyIndex;
1810 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1811 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1812
1813 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1814
1815 device->queues[qfi] = vk_alloc(&device->alloc,
1816 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1817 if (!device->queues[qfi]) {
1818 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1819 goto fail;
1820 }
1821
1822 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1823
1824 device->queue_count[qfi] = queue_create->queueCount;
1825
1826 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1827 result = radv_queue_init(device, &device->queues[qfi][q],
1828 qfi, q, queue_create->flags,
1829 global_priority);
1830 if (result != VK_SUCCESS)
1831 goto fail;
1832 }
1833 }
1834
1835 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1836 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1837
1838 /* Disabled and not implemented for now. */
1839 device->dfsm_allowed = device->pbb_allowed &&
1840 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1841 device->physical_device->rad_info.family == CHIP_RAVEN2);
1842
1843 #ifdef ANDROID
1844 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1845 #endif
1846
1847 /* The maximum number of scratch waves. Scratch space isn't divided
1848 * evenly between CUs. The number is only a function of the number of CUs.
1849 * We can decrease the constant to decrease the scratch buffer size.
1850 *
1851 * sctx->scratch_waves must be >= the maximum possible size of
1852 * 1 threadgroup, so that the hw doesn't hang from being unable
1853 * to start any.
1854 *
1855 * The recommended value is 4 per CU at most. Higher numbers don't
1856 * bring much benefit, but they still occupy chip resources (think
1857 * async compute). I've seen ~2% performance difference between 4 and 32.
1858 */
1859 uint32_t max_threads_per_block = 2048;
1860 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1861 max_threads_per_block / 64);
1862
1863 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1864
1865 if (device->physical_device->rad_info.chip_class >= CIK) {
1866 /* If the KMD allows it (there is a KMD hw register for it),
1867 * allow launching waves out-of-order.
1868 */
1869 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1870 }
1871
1872 radv_device_init_gs_info(device);
1873
1874 device->tess_offchip_block_dw_size =
1875 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1876 device->has_distributed_tess =
1877 device->physical_device->rad_info.chip_class >= VI &&
1878 device->physical_device->rad_info.max_se >= 2;
1879
1880 if (getenv("RADV_TRACE_FILE")) {
1881 const char *filename = getenv("RADV_TRACE_FILE");
1882
1883 keep_shader_info = true;
1884
1885 if (!radv_init_trace(device))
1886 goto fail;
1887
1888 fprintf(stderr, "*****************************************************************************\n");
1889 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1890 fprintf(stderr, "*****************************************************************************\n");
1891
1892 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1893 radv_dump_enabled_options(device, stderr);
1894 }
1895
1896 device->keep_shader_info = keep_shader_info;
1897
1898 result = radv_device_init_meta(device);
1899 if (result != VK_SUCCESS)
1900 goto fail;
1901
1902 radv_device_init_msaa(device);
1903
1904 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1905 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1906 switch (family) {
1907 case RADV_QUEUE_GENERAL:
1908 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1909 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1910 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1911 break;
1912 case RADV_QUEUE_COMPUTE:
1913 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1914 radeon_emit(device->empty_cs[family], 0);
1915 break;
1916 }
1917 device->ws->cs_finalize(device->empty_cs[family]);
1918 }
1919
1920 if (device->physical_device->rad_info.chip_class >= CIK)
1921 cik_create_gfx_config(device);
1922
1923 VkPipelineCacheCreateInfo ci;
1924 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1925 ci.pNext = NULL;
1926 ci.flags = 0;
1927 ci.pInitialData = NULL;
1928 ci.initialDataSize = 0;
1929 VkPipelineCache pc;
1930 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1931 &ci, NULL, &pc);
1932 if (result != VK_SUCCESS)
1933 goto fail_meta;
1934
1935 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1936
1937 device->force_aniso =
1938 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1939 if (device->force_aniso >= 0) {
1940 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1941 1 << util_logbase2(device->force_aniso));
1942 }
1943
1944 *pDevice = radv_device_to_handle(device);
1945 return VK_SUCCESS;
1946
1947 fail_meta:
1948 radv_device_finish_meta(device);
1949 fail:
1950 radv_bo_list_finish(&device->bo_list);
1951
1952 if (device->trace_bo)
1953 device->ws->buffer_destroy(device->trace_bo);
1954
1955 if (device->gfx_init)
1956 device->ws->buffer_destroy(device->gfx_init);
1957
1958 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1959 for (unsigned q = 0; q < device->queue_count[i]; q++)
1960 radv_queue_finish(&device->queues[i][q]);
1961 if (device->queue_count[i])
1962 vk_free(&device->alloc, device->queues[i]);
1963 }
1964
1965 vk_free(&device->alloc, device);
1966 return result;
1967 }
1968
1969 void radv_DestroyDevice(
1970 VkDevice _device,
1971 const VkAllocationCallbacks* pAllocator)
1972 {
1973 RADV_FROM_HANDLE(radv_device, device, _device);
1974
1975 if (!device)
1976 return;
1977
1978 if (device->trace_bo)
1979 device->ws->buffer_destroy(device->trace_bo);
1980
1981 if (device->gfx_init)
1982 device->ws->buffer_destroy(device->gfx_init);
1983
1984 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1985 for (unsigned q = 0; q < device->queue_count[i]; q++)
1986 radv_queue_finish(&device->queues[i][q]);
1987 if (device->queue_count[i])
1988 vk_free(&device->alloc, device->queues[i]);
1989 if (device->empty_cs[i])
1990 device->ws->cs_destroy(device->empty_cs[i]);
1991 }
1992 radv_device_finish_meta(device);
1993
1994 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1995 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1996
1997 radv_destroy_shader_slabs(device);
1998
1999 radv_bo_list_finish(&device->bo_list);
2000 vk_free(&device->alloc, device);
2001 }
2002
2003 VkResult radv_EnumerateInstanceLayerProperties(
2004 uint32_t* pPropertyCount,
2005 VkLayerProperties* pProperties)
2006 {
2007 if (pProperties == NULL) {
2008 *pPropertyCount = 0;
2009 return VK_SUCCESS;
2010 }
2011
2012 /* None supported at this time */
2013 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2014 }
2015
2016 VkResult radv_EnumerateDeviceLayerProperties(
2017 VkPhysicalDevice physicalDevice,
2018 uint32_t* pPropertyCount,
2019 VkLayerProperties* pProperties)
2020 {
2021 if (pProperties == NULL) {
2022 *pPropertyCount = 0;
2023 return VK_SUCCESS;
2024 }
2025
2026 /* None supported at this time */
2027 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2028 }
2029
2030 void radv_GetDeviceQueue2(
2031 VkDevice _device,
2032 const VkDeviceQueueInfo2* pQueueInfo,
2033 VkQueue* pQueue)
2034 {
2035 RADV_FROM_HANDLE(radv_device, device, _device);
2036 struct radv_queue *queue;
2037
2038 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2039 if (pQueueInfo->flags != queue->flags) {
2040 /* From the Vulkan 1.1.70 spec:
2041 *
2042 * "The queue returned by vkGetDeviceQueue2 must have the same
2043 * flags value from this structure as that used at device
2044 * creation time in a VkDeviceQueueCreateInfo instance. If no
2045 * matching flags were specified at device creation time then
2046 * pQueue will return VK_NULL_HANDLE."
2047 */
2048 *pQueue = VK_NULL_HANDLE;
2049 return;
2050 }
2051
2052 *pQueue = radv_queue_to_handle(queue);
2053 }
2054
2055 void radv_GetDeviceQueue(
2056 VkDevice _device,
2057 uint32_t queueFamilyIndex,
2058 uint32_t queueIndex,
2059 VkQueue* pQueue)
2060 {
2061 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2062 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2063 .queueFamilyIndex = queueFamilyIndex,
2064 .queueIndex = queueIndex
2065 };
2066
2067 radv_GetDeviceQueue2(_device, &info, pQueue);
2068 }
2069
2070 static void
2071 fill_geom_tess_rings(struct radv_queue *queue,
2072 uint32_t *map,
2073 bool add_sample_positions,
2074 uint32_t esgs_ring_size,
2075 struct radeon_winsys_bo *esgs_ring_bo,
2076 uint32_t gsvs_ring_size,
2077 struct radeon_winsys_bo *gsvs_ring_bo,
2078 uint32_t tess_factor_ring_size,
2079 uint32_t tess_offchip_ring_offset,
2080 uint32_t tess_offchip_ring_size,
2081 struct radeon_winsys_bo *tess_rings_bo)
2082 {
2083 uint32_t *desc = &map[4];
2084
2085 if (esgs_ring_bo) {
2086 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2087
2088 /* stride 0, num records - size, add tid, swizzle, elsize4,
2089 index stride 64 */
2090 desc[0] = esgs_va;
2091 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2092 S_008F04_STRIDE(0) |
2093 S_008F04_SWIZZLE_ENABLE(true);
2094 desc[2] = esgs_ring_size;
2095 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2096 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2097 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2098 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2099 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2100 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2101 S_008F0C_ELEMENT_SIZE(1) |
2102 S_008F0C_INDEX_STRIDE(3) |
2103 S_008F0C_ADD_TID_ENABLE(true);
2104
2105 /* GS entry for ES->GS ring */
2106 /* stride 0, num records - size, elsize0,
2107 index stride 0 */
2108 desc[4] = esgs_va;
2109 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2110 S_008F04_STRIDE(0) |
2111 S_008F04_SWIZZLE_ENABLE(false);
2112 desc[6] = esgs_ring_size;
2113 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2114 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2115 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2116 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2117 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2118 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2119 S_008F0C_ELEMENT_SIZE(0) |
2120 S_008F0C_INDEX_STRIDE(0) |
2121 S_008F0C_ADD_TID_ENABLE(false);
2122 }
2123
2124 desc += 8;
2125
2126 if (gsvs_ring_bo) {
2127 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2128
2129 /* VS entry for GS->VS ring */
2130 /* stride 0, num records - size, elsize0,
2131 index stride 0 */
2132 desc[0] = gsvs_va;
2133 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2134 S_008F04_STRIDE(0) |
2135 S_008F04_SWIZZLE_ENABLE(false);
2136 desc[2] = gsvs_ring_size;
2137 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2138 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2139 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2140 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2141 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2143 S_008F0C_ELEMENT_SIZE(0) |
2144 S_008F0C_INDEX_STRIDE(0) |
2145 S_008F0C_ADD_TID_ENABLE(false);
2146
2147 /* stride gsvs_itemsize, num records 64
2148 elsize 4, index stride 16 */
2149 /* shader will patch stride and desc[2] */
2150 desc[4] = gsvs_va;
2151 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2152 S_008F04_STRIDE(0) |
2153 S_008F04_SWIZZLE_ENABLE(true);
2154 desc[6] = 0;
2155 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2156 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2157 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2158 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2159 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2160 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2161 S_008F0C_ELEMENT_SIZE(1) |
2162 S_008F0C_INDEX_STRIDE(1) |
2163 S_008F0C_ADD_TID_ENABLE(true);
2164 }
2165
2166 desc += 8;
2167
2168 if (tess_rings_bo) {
2169 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2170 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2171
2172 desc[0] = tess_va;
2173 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2174 S_008F04_STRIDE(0) |
2175 S_008F04_SWIZZLE_ENABLE(false);
2176 desc[2] = tess_factor_ring_size;
2177 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2178 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2179 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2180 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2181 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2182 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2183 S_008F0C_ELEMENT_SIZE(0) |
2184 S_008F0C_INDEX_STRIDE(0) |
2185 S_008F0C_ADD_TID_ENABLE(false);
2186
2187 desc[4] = tess_offchip_va;
2188 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2189 S_008F04_STRIDE(0) |
2190 S_008F04_SWIZZLE_ENABLE(false);
2191 desc[6] = tess_offchip_ring_size;
2192 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2193 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2194 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2195 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2196 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2197 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2198 S_008F0C_ELEMENT_SIZE(0) |
2199 S_008F0C_INDEX_STRIDE(0) |
2200 S_008F0C_ADD_TID_ENABLE(false);
2201 }
2202
2203 desc += 8;
2204
2205 if (add_sample_positions) {
2206 /* add sample positions after all rings */
2207 memcpy(desc, queue->device->sample_locations_1x, 8);
2208 desc += 2;
2209 memcpy(desc, queue->device->sample_locations_2x, 16);
2210 desc += 4;
2211 memcpy(desc, queue->device->sample_locations_4x, 32);
2212 desc += 8;
2213 memcpy(desc, queue->device->sample_locations_8x, 64);
2214 }
2215 }
2216
2217 static unsigned
2218 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2219 {
2220 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2221 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2222 device->physical_device->rad_info.family != CHIP_STONEY;
2223 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2224 unsigned max_offchip_buffers;
2225 unsigned offchip_granularity;
2226 unsigned hs_offchip_param;
2227
2228 /*
2229 * Per RadeonSI:
2230 * This must be one less than the maximum number due to a hw limitation.
2231 * Various hardware bugs in SI, CIK, and GFX9 need this.
2232 *
2233 * Per AMDVLK:
2234 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2235 * Gfx7 should limit max_offchip_buffers to 508
2236 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2237 *
2238 * Follow AMDVLK here.
2239 */
2240 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2241 device->physical_device->rad_info.chip_class == CIK ||
2242 device->physical_device->rad_info.chip_class == SI)
2243 --max_offchip_buffers_per_se;
2244
2245 max_offchip_buffers = max_offchip_buffers_per_se *
2246 device->physical_device->rad_info.max_se;
2247
2248 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2249 * around by setting 4K granularity.
2250 */
2251 if (device->tess_offchip_block_dw_size == 4096) {
2252 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2253 offchip_granularity = V_03093C_X_4K_DWORDS;
2254 } else {
2255 assert(device->tess_offchip_block_dw_size == 8192);
2256 offchip_granularity = V_03093C_X_8K_DWORDS;
2257 }
2258
2259 switch (device->physical_device->rad_info.chip_class) {
2260 case SI:
2261 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2262 break;
2263 case CIK:
2264 case VI:
2265 case GFX9:
2266 default:
2267 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2268 break;
2269 }
2270
2271 *max_offchip_buffers_p = max_offchip_buffers;
2272 if (device->physical_device->rad_info.chip_class >= CIK) {
2273 if (device->physical_device->rad_info.chip_class >= VI)
2274 --max_offchip_buffers;
2275 hs_offchip_param =
2276 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2277 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2278 } else {
2279 hs_offchip_param =
2280 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2281 }
2282 return hs_offchip_param;
2283 }
2284
2285 static void
2286 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2287 struct radeon_winsys_bo *esgs_ring_bo,
2288 uint32_t esgs_ring_size,
2289 struct radeon_winsys_bo *gsvs_ring_bo,
2290 uint32_t gsvs_ring_size)
2291 {
2292 if (!esgs_ring_bo && !gsvs_ring_bo)
2293 return;
2294
2295 if (esgs_ring_bo)
2296 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2297
2298 if (gsvs_ring_bo)
2299 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2300
2301 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2302 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2303 radeon_emit(cs, esgs_ring_size >> 8);
2304 radeon_emit(cs, gsvs_ring_size >> 8);
2305 } else {
2306 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2307 radeon_emit(cs, esgs_ring_size >> 8);
2308 radeon_emit(cs, gsvs_ring_size >> 8);
2309 }
2310 }
2311
2312 static void
2313 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2314 unsigned hs_offchip_param, unsigned tf_ring_size,
2315 struct radeon_winsys_bo *tess_rings_bo)
2316 {
2317 uint64_t tf_va;
2318
2319 if (!tess_rings_bo)
2320 return;
2321
2322 tf_va = radv_buffer_get_va(tess_rings_bo);
2323
2324 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2325
2326 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2327 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2328 S_030938_SIZE(tf_ring_size / 4));
2329 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2330 tf_va >> 8);
2331 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2332 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2333 S_030944_BASE_HI(tf_va >> 40));
2334 }
2335 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2336 hs_offchip_param);
2337 } else {
2338 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2339 S_008988_SIZE(tf_ring_size / 4));
2340 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2341 tf_va >> 8);
2342 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2343 hs_offchip_param);
2344 }
2345 }
2346
2347 static void
2348 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2349 struct radeon_winsys_bo *compute_scratch_bo)
2350 {
2351 uint64_t scratch_va;
2352
2353 if (!compute_scratch_bo)
2354 return;
2355
2356 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2357
2358 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2359
2360 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2361 radeon_emit(cs, scratch_va);
2362 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2363 S_008F04_SWIZZLE_ENABLE(1));
2364 }
2365
2366 static void
2367 radv_emit_global_shader_pointers(struct radv_queue *queue,
2368 struct radeon_cmdbuf *cs,
2369 struct radeon_winsys_bo *descriptor_bo)
2370 {
2371 uint64_t va;
2372
2373 if (!descriptor_bo)
2374 return;
2375
2376 va = radv_buffer_get_va(descriptor_bo);
2377
2378 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2379
2380 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2381 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2382 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2383 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2384 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2385
2386 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2387 radv_emit_shader_pointer(queue->device, cs, regs[i],
2388 va, true);
2389 }
2390 } else {
2391 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2392 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2393 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2394 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2395 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2396 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2397
2398 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2399 radv_emit_shader_pointer(queue->device, cs, regs[i],
2400 va, true);
2401 }
2402 }
2403 }
2404
2405 static void
2406 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2407 {
2408 struct radv_device *device = queue->device;
2409
2410 if (device->gfx_init) {
2411 uint64_t va = radv_buffer_get_va(device->gfx_init);
2412
2413 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2414 radeon_emit(cs, va);
2415 radeon_emit(cs, va >> 32);
2416 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2417
2418 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2419 } else {
2420 struct radv_physical_device *physical_device = device->physical_device;
2421 si_emit_graphics(physical_device, cs);
2422 }
2423 }
2424
2425 static void
2426 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2427 {
2428 struct radv_physical_device *physical_device = queue->device->physical_device;
2429 si_emit_compute(physical_device, cs);
2430 }
2431
2432 static VkResult
2433 radv_get_preamble_cs(struct radv_queue *queue,
2434 uint32_t scratch_size,
2435 uint32_t compute_scratch_size,
2436 uint32_t esgs_ring_size,
2437 uint32_t gsvs_ring_size,
2438 bool needs_tess_rings,
2439 bool needs_sample_positions,
2440 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2441 struct radeon_cmdbuf **initial_preamble_cs,
2442 struct radeon_cmdbuf **continue_preamble_cs)
2443 {
2444 struct radeon_winsys_bo *scratch_bo = NULL;
2445 struct radeon_winsys_bo *descriptor_bo = NULL;
2446 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2447 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2448 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2449 struct radeon_winsys_bo *tess_rings_bo = NULL;
2450 struct radeon_cmdbuf *dest_cs[3] = {0};
2451 bool add_tess_rings = false, add_sample_positions = false;
2452 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2453 unsigned max_offchip_buffers;
2454 unsigned hs_offchip_param = 0;
2455 unsigned tess_offchip_ring_offset;
2456 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2457 if (!queue->has_tess_rings) {
2458 if (needs_tess_rings)
2459 add_tess_rings = true;
2460 }
2461 if (!queue->has_sample_positions) {
2462 if (needs_sample_positions)
2463 add_sample_positions = true;
2464 }
2465 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2466 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2467 &max_offchip_buffers);
2468 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2469 tess_offchip_ring_size = max_offchip_buffers *
2470 queue->device->tess_offchip_block_dw_size * 4;
2471
2472 if (scratch_size <= queue->scratch_size &&
2473 compute_scratch_size <= queue->compute_scratch_size &&
2474 esgs_ring_size <= queue->esgs_ring_size &&
2475 gsvs_ring_size <= queue->gsvs_ring_size &&
2476 !add_tess_rings && !add_sample_positions &&
2477 queue->initial_preamble_cs) {
2478 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2479 *initial_preamble_cs = queue->initial_preamble_cs;
2480 *continue_preamble_cs = queue->continue_preamble_cs;
2481 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2482 *continue_preamble_cs = NULL;
2483 return VK_SUCCESS;
2484 }
2485
2486 if (scratch_size > queue->scratch_size) {
2487 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2488 scratch_size,
2489 4096,
2490 RADEON_DOMAIN_VRAM,
2491 ring_bo_flags,
2492 RADV_BO_PRIORITY_SCRATCH);
2493 if (!scratch_bo)
2494 goto fail;
2495 } else
2496 scratch_bo = queue->scratch_bo;
2497
2498 if (compute_scratch_size > queue->compute_scratch_size) {
2499 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2500 compute_scratch_size,
2501 4096,
2502 RADEON_DOMAIN_VRAM,
2503 ring_bo_flags,
2504 RADV_BO_PRIORITY_SCRATCH);
2505 if (!compute_scratch_bo)
2506 goto fail;
2507
2508 } else
2509 compute_scratch_bo = queue->compute_scratch_bo;
2510
2511 if (esgs_ring_size > queue->esgs_ring_size) {
2512 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2513 esgs_ring_size,
2514 4096,
2515 RADEON_DOMAIN_VRAM,
2516 ring_bo_flags,
2517 RADV_BO_PRIORITY_SCRATCH);
2518 if (!esgs_ring_bo)
2519 goto fail;
2520 } else {
2521 esgs_ring_bo = queue->esgs_ring_bo;
2522 esgs_ring_size = queue->esgs_ring_size;
2523 }
2524
2525 if (gsvs_ring_size > queue->gsvs_ring_size) {
2526 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2527 gsvs_ring_size,
2528 4096,
2529 RADEON_DOMAIN_VRAM,
2530 ring_bo_flags,
2531 RADV_BO_PRIORITY_SCRATCH);
2532 if (!gsvs_ring_bo)
2533 goto fail;
2534 } else {
2535 gsvs_ring_bo = queue->gsvs_ring_bo;
2536 gsvs_ring_size = queue->gsvs_ring_size;
2537 }
2538
2539 if (add_tess_rings) {
2540 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2541 tess_offchip_ring_offset + tess_offchip_ring_size,
2542 256,
2543 RADEON_DOMAIN_VRAM,
2544 ring_bo_flags,
2545 RADV_BO_PRIORITY_SCRATCH);
2546 if (!tess_rings_bo)
2547 goto fail;
2548 } else {
2549 tess_rings_bo = queue->tess_rings_bo;
2550 }
2551
2552 if (scratch_bo != queue->scratch_bo ||
2553 esgs_ring_bo != queue->esgs_ring_bo ||
2554 gsvs_ring_bo != queue->gsvs_ring_bo ||
2555 tess_rings_bo != queue->tess_rings_bo ||
2556 add_sample_positions) {
2557 uint32_t size = 0;
2558 if (gsvs_ring_bo || esgs_ring_bo ||
2559 tess_rings_bo || add_sample_positions) {
2560 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2561 if (add_sample_positions)
2562 size += 128; /* 64+32+16+8 = 120 bytes */
2563 }
2564 else if (scratch_bo)
2565 size = 8; /* 2 dword */
2566
2567 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2568 size,
2569 4096,
2570 RADEON_DOMAIN_VRAM,
2571 RADEON_FLAG_CPU_ACCESS |
2572 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2573 RADEON_FLAG_READ_ONLY,
2574 RADV_BO_PRIORITY_DESCRIPTOR);
2575 if (!descriptor_bo)
2576 goto fail;
2577 } else
2578 descriptor_bo = queue->descriptor_bo;
2579
2580 if (descriptor_bo != queue->descriptor_bo) {
2581 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2582
2583 if (scratch_bo) {
2584 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2585 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2586 S_008F04_SWIZZLE_ENABLE(1);
2587 map[0] = scratch_va;
2588 map[1] = rsrc1;
2589 }
2590
2591 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2592 fill_geom_tess_rings(queue, map, add_sample_positions,
2593 esgs_ring_size, esgs_ring_bo,
2594 gsvs_ring_size, gsvs_ring_bo,
2595 tess_factor_ring_size,
2596 tess_offchip_ring_offset,
2597 tess_offchip_ring_size,
2598 tess_rings_bo);
2599
2600 queue->device->ws->buffer_unmap(descriptor_bo);
2601 }
2602
2603 for(int i = 0; i < 3; ++i) {
2604 struct radeon_cmdbuf *cs = NULL;
2605 cs = queue->device->ws->cs_create(queue->device->ws,
2606 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2607 if (!cs)
2608 goto fail;
2609
2610 dest_cs[i] = cs;
2611
2612 if (scratch_bo)
2613 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2614
2615 /* Emit initial configuration. */
2616 switch (queue->queue_family_index) {
2617 case RADV_QUEUE_GENERAL:
2618 radv_init_graphics_state(cs, queue);
2619 break;
2620 case RADV_QUEUE_COMPUTE:
2621 radv_init_compute_state(cs, queue);
2622 break;
2623 case RADV_QUEUE_TRANSFER:
2624 break;
2625 }
2626
2627 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2628 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2629 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2630 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2631 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2632 }
2633
2634 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2635 gsvs_ring_bo, gsvs_ring_size);
2636 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2637 tess_factor_ring_size, tess_rings_bo);
2638 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2639 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2640
2641 if (i == 0) {
2642 si_cs_emit_cache_flush(cs,
2643 queue->device->physical_device->rad_info.chip_class,
2644 NULL, 0,
2645 queue->queue_family_index == RING_COMPUTE &&
2646 queue->device->physical_device->rad_info.chip_class >= CIK,
2647 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2648 RADV_CMD_FLAG_INV_ICACHE |
2649 RADV_CMD_FLAG_INV_SMEM_L1 |
2650 RADV_CMD_FLAG_INV_VMEM_L1 |
2651 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2652 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2653 } else if (i == 1) {
2654 si_cs_emit_cache_flush(cs,
2655 queue->device->physical_device->rad_info.chip_class,
2656 NULL, 0,
2657 queue->queue_family_index == RING_COMPUTE &&
2658 queue->device->physical_device->rad_info.chip_class >= CIK,
2659 RADV_CMD_FLAG_INV_ICACHE |
2660 RADV_CMD_FLAG_INV_SMEM_L1 |
2661 RADV_CMD_FLAG_INV_VMEM_L1 |
2662 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2663 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2664 }
2665
2666 if (!queue->device->ws->cs_finalize(cs))
2667 goto fail;
2668 }
2669
2670 if (queue->initial_full_flush_preamble_cs)
2671 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2672
2673 if (queue->initial_preamble_cs)
2674 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2675
2676 if (queue->continue_preamble_cs)
2677 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2678
2679 queue->initial_full_flush_preamble_cs = dest_cs[0];
2680 queue->initial_preamble_cs = dest_cs[1];
2681 queue->continue_preamble_cs = dest_cs[2];
2682
2683 if (scratch_bo != queue->scratch_bo) {
2684 if (queue->scratch_bo)
2685 queue->device->ws->buffer_destroy(queue->scratch_bo);
2686 queue->scratch_bo = scratch_bo;
2687 queue->scratch_size = scratch_size;
2688 }
2689
2690 if (compute_scratch_bo != queue->compute_scratch_bo) {
2691 if (queue->compute_scratch_bo)
2692 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2693 queue->compute_scratch_bo = compute_scratch_bo;
2694 queue->compute_scratch_size = compute_scratch_size;
2695 }
2696
2697 if (esgs_ring_bo != queue->esgs_ring_bo) {
2698 if (queue->esgs_ring_bo)
2699 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2700 queue->esgs_ring_bo = esgs_ring_bo;
2701 queue->esgs_ring_size = esgs_ring_size;
2702 }
2703
2704 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2705 if (queue->gsvs_ring_bo)
2706 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2707 queue->gsvs_ring_bo = gsvs_ring_bo;
2708 queue->gsvs_ring_size = gsvs_ring_size;
2709 }
2710
2711 if (tess_rings_bo != queue->tess_rings_bo) {
2712 queue->tess_rings_bo = tess_rings_bo;
2713 queue->has_tess_rings = true;
2714 }
2715
2716 if (descriptor_bo != queue->descriptor_bo) {
2717 if (queue->descriptor_bo)
2718 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2719
2720 queue->descriptor_bo = descriptor_bo;
2721 }
2722
2723 if (add_sample_positions)
2724 queue->has_sample_positions = true;
2725
2726 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2727 *initial_preamble_cs = queue->initial_preamble_cs;
2728 *continue_preamble_cs = queue->continue_preamble_cs;
2729 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2730 *continue_preamble_cs = NULL;
2731 return VK_SUCCESS;
2732 fail:
2733 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2734 if (dest_cs[i])
2735 queue->device->ws->cs_destroy(dest_cs[i]);
2736 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2737 queue->device->ws->buffer_destroy(descriptor_bo);
2738 if (scratch_bo && scratch_bo != queue->scratch_bo)
2739 queue->device->ws->buffer_destroy(scratch_bo);
2740 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2741 queue->device->ws->buffer_destroy(compute_scratch_bo);
2742 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2743 queue->device->ws->buffer_destroy(esgs_ring_bo);
2744 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2745 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2746 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2747 queue->device->ws->buffer_destroy(tess_rings_bo);
2748 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2749 }
2750
2751 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2752 struct radv_winsys_sem_counts *counts,
2753 int num_sems,
2754 const VkSemaphore *sems,
2755 VkFence _fence,
2756 bool reset_temp)
2757 {
2758 int syncobj_idx = 0, sem_idx = 0;
2759
2760 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2761 return VK_SUCCESS;
2762
2763 for (uint32_t i = 0; i < num_sems; i++) {
2764 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2765
2766 if (sem->temp_syncobj || sem->syncobj)
2767 counts->syncobj_count++;
2768 else
2769 counts->sem_count++;
2770 }
2771
2772 if (_fence != VK_NULL_HANDLE) {
2773 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2774 if (fence->temp_syncobj || fence->syncobj)
2775 counts->syncobj_count++;
2776 }
2777
2778 if (counts->syncobj_count) {
2779 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2780 if (!counts->syncobj)
2781 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2782 }
2783
2784 if (counts->sem_count) {
2785 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2786 if (!counts->sem) {
2787 free(counts->syncobj);
2788 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2789 }
2790 }
2791
2792 for (uint32_t i = 0; i < num_sems; i++) {
2793 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2794
2795 if (sem->temp_syncobj) {
2796 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2797 }
2798 else if (sem->syncobj)
2799 counts->syncobj[syncobj_idx++] = sem->syncobj;
2800 else {
2801 assert(sem->sem);
2802 counts->sem[sem_idx++] = sem->sem;
2803 }
2804 }
2805
2806 if (_fence != VK_NULL_HANDLE) {
2807 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2808 if (fence->temp_syncobj)
2809 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2810 else if (fence->syncobj)
2811 counts->syncobj[syncobj_idx++] = fence->syncobj;
2812 }
2813
2814 return VK_SUCCESS;
2815 }
2816
2817 static void
2818 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2819 {
2820 free(sem_info->wait.syncobj);
2821 free(sem_info->wait.sem);
2822 free(sem_info->signal.syncobj);
2823 free(sem_info->signal.sem);
2824 }
2825
2826
2827 static void radv_free_temp_syncobjs(struct radv_device *device,
2828 int num_sems,
2829 const VkSemaphore *sems)
2830 {
2831 for (uint32_t i = 0; i < num_sems; i++) {
2832 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2833
2834 if (sem->temp_syncobj) {
2835 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2836 sem->temp_syncobj = 0;
2837 }
2838 }
2839 }
2840
2841 static VkResult
2842 radv_alloc_sem_info(struct radv_instance *instance,
2843 struct radv_winsys_sem_info *sem_info,
2844 int num_wait_sems,
2845 const VkSemaphore *wait_sems,
2846 int num_signal_sems,
2847 const VkSemaphore *signal_sems,
2848 VkFence fence)
2849 {
2850 VkResult ret;
2851 memset(sem_info, 0, sizeof(*sem_info));
2852
2853 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2854 if (ret)
2855 return ret;
2856 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2857 if (ret)
2858 radv_free_sem_info(sem_info);
2859
2860 /* caller can override these */
2861 sem_info->cs_emit_wait = true;
2862 sem_info->cs_emit_signal = true;
2863 return ret;
2864 }
2865
2866 /* Signals fence as soon as all the work currently put on queue is done. */
2867 static VkResult radv_signal_fence(struct radv_queue *queue,
2868 struct radv_fence *fence)
2869 {
2870 int ret;
2871 VkResult result;
2872 struct radv_winsys_sem_info sem_info;
2873
2874 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2875 radv_fence_to_handle(fence));
2876 if (result != VK_SUCCESS)
2877 return result;
2878
2879 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2880 &queue->device->empty_cs[queue->queue_family_index],
2881 1, NULL, NULL, &sem_info, NULL,
2882 false, fence->fence);
2883 radv_free_sem_info(&sem_info);
2884
2885 if (ret)
2886 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2887
2888 return VK_SUCCESS;
2889 }
2890
2891 VkResult radv_QueueSubmit(
2892 VkQueue _queue,
2893 uint32_t submitCount,
2894 const VkSubmitInfo* pSubmits,
2895 VkFence _fence)
2896 {
2897 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2898 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2899 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2900 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2901 int ret;
2902 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2903 uint32_t scratch_size = 0;
2904 uint32_t compute_scratch_size = 0;
2905 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2906 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2907 VkResult result;
2908 bool fence_emitted = false;
2909 bool tess_rings_needed = false;
2910 bool sample_positions_needed = false;
2911
2912 /* Do this first so failing to allocate scratch buffers can't result in
2913 * partially executed submissions. */
2914 for (uint32_t i = 0; i < submitCount; i++) {
2915 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2917 pSubmits[i].pCommandBuffers[j]);
2918
2919 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2920 compute_scratch_size = MAX2(compute_scratch_size,
2921 cmd_buffer->compute_scratch_size_needed);
2922 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2923 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2924 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2925 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2926 }
2927 }
2928
2929 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2930 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2931 sample_positions_needed, &initial_flush_preamble_cs,
2932 &initial_preamble_cs, &continue_preamble_cs);
2933 if (result != VK_SUCCESS)
2934 return result;
2935
2936 for (uint32_t i = 0; i < submitCount; i++) {
2937 struct radeon_cmdbuf **cs_array;
2938 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2939 bool can_patch = true;
2940 uint32_t advance;
2941 struct radv_winsys_sem_info sem_info;
2942
2943 result = radv_alloc_sem_info(queue->device->instance,
2944 &sem_info,
2945 pSubmits[i].waitSemaphoreCount,
2946 pSubmits[i].pWaitSemaphores,
2947 pSubmits[i].signalSemaphoreCount,
2948 pSubmits[i].pSignalSemaphores,
2949 _fence);
2950 if (result != VK_SUCCESS)
2951 return result;
2952
2953 if (!pSubmits[i].commandBufferCount) {
2954 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2955 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2956 &queue->device->empty_cs[queue->queue_family_index],
2957 1, NULL, NULL,
2958 &sem_info, NULL,
2959 false, base_fence);
2960 if (ret) {
2961 radv_loge("failed to submit CS %d\n", i);
2962 abort();
2963 }
2964 fence_emitted = true;
2965 }
2966 radv_free_sem_info(&sem_info);
2967 continue;
2968 }
2969
2970 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2971 (pSubmits[i].commandBufferCount));
2972
2973 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2975 pSubmits[i].pCommandBuffers[j]);
2976 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2977
2978 cs_array[j] = cmd_buffer->cs;
2979 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2980 can_patch = false;
2981
2982 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2983 }
2984
2985 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2986 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2987 const struct radv_winsys_bo_list *bo_list = NULL;
2988
2989 advance = MIN2(max_cs_submission,
2990 pSubmits[i].commandBufferCount - j);
2991
2992 if (queue->device->trace_bo)
2993 *queue->device->trace_id_ptr = 0;
2994
2995 sem_info.cs_emit_wait = j == 0;
2996 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2997
2998 if (unlikely(queue->device->use_global_bo_list)) {
2999 pthread_mutex_lock(&queue->device->bo_list.mutex);
3000 bo_list = &queue->device->bo_list.list;
3001 }
3002
3003 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3004 advance, initial_preamble, continue_preamble_cs,
3005 &sem_info, bo_list,
3006 can_patch, base_fence);
3007
3008 if (unlikely(queue->device->use_global_bo_list))
3009 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3010
3011 if (ret) {
3012 radv_loge("failed to submit CS %d\n", i);
3013 abort();
3014 }
3015 fence_emitted = true;
3016 if (queue->device->trace_bo) {
3017 radv_check_gpu_hangs(queue, cs_array[j]);
3018 }
3019 }
3020
3021 radv_free_temp_syncobjs(queue->device,
3022 pSubmits[i].waitSemaphoreCount,
3023 pSubmits[i].pWaitSemaphores);
3024 radv_free_sem_info(&sem_info);
3025 free(cs_array);
3026 }
3027
3028 if (fence) {
3029 if (!fence_emitted) {
3030 result = radv_signal_fence(queue, fence);
3031 if (result != VK_SUCCESS)
3032 return result;
3033 }
3034 fence->submitted = true;
3035 }
3036
3037 return VK_SUCCESS;
3038 }
3039
3040 VkResult radv_QueueWaitIdle(
3041 VkQueue _queue)
3042 {
3043 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3044
3045 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3046 radv_queue_family_to_ring(queue->queue_family_index),
3047 queue->queue_idx);
3048 return VK_SUCCESS;
3049 }
3050
3051 VkResult radv_DeviceWaitIdle(
3052 VkDevice _device)
3053 {
3054 RADV_FROM_HANDLE(radv_device, device, _device);
3055
3056 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3057 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3058 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3059 }
3060 }
3061 return VK_SUCCESS;
3062 }
3063
3064 VkResult radv_EnumerateInstanceExtensionProperties(
3065 const char* pLayerName,
3066 uint32_t* pPropertyCount,
3067 VkExtensionProperties* pProperties)
3068 {
3069 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3070
3071 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3072 if (radv_supported_instance_extensions.extensions[i]) {
3073 vk_outarray_append(&out, prop) {
3074 *prop = radv_instance_extensions[i];
3075 }
3076 }
3077 }
3078
3079 return vk_outarray_status(&out);
3080 }
3081
3082 VkResult radv_EnumerateDeviceExtensionProperties(
3083 VkPhysicalDevice physicalDevice,
3084 const char* pLayerName,
3085 uint32_t* pPropertyCount,
3086 VkExtensionProperties* pProperties)
3087 {
3088 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3089 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3090
3091 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3092 if (device->supported_extensions.extensions[i]) {
3093 vk_outarray_append(&out, prop) {
3094 *prop = radv_device_extensions[i];
3095 }
3096 }
3097 }
3098
3099 return vk_outarray_status(&out);
3100 }
3101
3102 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3103 VkInstance _instance,
3104 const char* pName)
3105 {
3106 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3107
3108 return radv_lookup_entrypoint_checked(pName,
3109 instance ? instance->apiVersion : 0,
3110 instance ? &instance->enabled_extensions : NULL,
3111 NULL);
3112 }
3113
3114 /* The loader wants us to expose a second GetInstanceProcAddr function
3115 * to work around certain LD_PRELOAD issues seen in apps.
3116 */
3117 PUBLIC
3118 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3119 VkInstance instance,
3120 const char* pName);
3121
3122 PUBLIC
3123 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3124 VkInstance instance,
3125 const char* pName)
3126 {
3127 return radv_GetInstanceProcAddr(instance, pName);
3128 }
3129
3130 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3131 VkDevice _device,
3132 const char* pName)
3133 {
3134 RADV_FROM_HANDLE(radv_device, device, _device);
3135
3136 return radv_lookup_entrypoint_checked(pName,
3137 device->instance->apiVersion,
3138 &device->instance->enabled_extensions,
3139 &device->enabled_extensions);
3140 }
3141
3142 bool radv_get_memory_fd(struct radv_device *device,
3143 struct radv_device_memory *memory,
3144 int *pFD)
3145 {
3146 struct radeon_bo_metadata metadata;
3147
3148 if (memory->image) {
3149 radv_init_metadata(device, memory->image, &metadata);
3150 device->ws->buffer_set_metadata(memory->bo, &metadata);
3151 }
3152
3153 return device->ws->buffer_get_fd(device->ws, memory->bo,
3154 pFD);
3155 }
3156
3157 static VkResult radv_alloc_memory(struct radv_device *device,
3158 const VkMemoryAllocateInfo* pAllocateInfo,
3159 const VkAllocationCallbacks* pAllocator,
3160 VkDeviceMemory* pMem)
3161 {
3162 struct radv_device_memory *mem;
3163 VkResult result;
3164 enum radeon_bo_domain domain;
3165 uint32_t flags = 0;
3166 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3167
3168 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3169
3170 if (pAllocateInfo->allocationSize == 0) {
3171 /* Apparently, this is allowed */
3172 *pMem = VK_NULL_HANDLE;
3173 return VK_SUCCESS;
3174 }
3175
3176 const VkImportMemoryFdInfoKHR *import_info =
3177 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3178 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3179 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3180 const VkExportMemoryAllocateInfo *export_info =
3181 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3182 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3183 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3184
3185 const struct wsi_memory_allocate_info *wsi_info =
3186 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3187
3188 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3189 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3190 if (mem == NULL)
3191 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3192
3193 if (wsi_info && wsi_info->implicit_sync)
3194 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3195
3196 if (dedicate_info) {
3197 mem->image = radv_image_from_handle(dedicate_info->image);
3198 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3199 } else {
3200 mem->image = NULL;
3201 mem->buffer = NULL;
3202 }
3203
3204 float priority_float = 0.5;
3205 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3206 vk_find_struct_const(pAllocateInfo->pNext,
3207 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3208 if (priority_ext)
3209 priority_float = priority_ext->priority;
3210
3211 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3212 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3213
3214 mem->user_ptr = NULL;
3215
3216 if (import_info) {
3217 assert(import_info->handleType ==
3218 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3219 import_info->handleType ==
3220 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3221 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3222 priority, NULL, NULL);
3223 if (!mem->bo) {
3224 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3225 goto fail;
3226 } else {
3227 close(import_info->fd);
3228 }
3229 } else if (host_ptr_info) {
3230 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3231 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3232 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3233 pAllocateInfo->allocationSize,
3234 priority);
3235 if (!mem->bo) {
3236 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3237 goto fail;
3238 } else {
3239 mem->user_ptr = host_ptr_info->pHostPointer;
3240 }
3241 } else {
3242 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3243 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3244 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3245 domain = RADEON_DOMAIN_GTT;
3246 else
3247 domain = RADEON_DOMAIN_VRAM;
3248
3249 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3250 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3251 else
3252 flags |= RADEON_FLAG_CPU_ACCESS;
3253
3254 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3255 flags |= RADEON_FLAG_GTT_WC;
3256
3257 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3258 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3259 if (device->use_global_bo_list) {
3260 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3261 }
3262 }
3263
3264 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3265 domain, flags, priority);
3266
3267 if (!mem->bo) {
3268 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3269 goto fail;
3270 }
3271 mem->type_index = mem_type_index;
3272 }
3273
3274 result = radv_bo_list_add(device, mem->bo);
3275 if (result != VK_SUCCESS)
3276 goto fail_bo;
3277
3278 *pMem = radv_device_memory_to_handle(mem);
3279
3280 return VK_SUCCESS;
3281
3282 fail_bo:
3283 device->ws->buffer_destroy(mem->bo);
3284 fail:
3285 vk_free2(&device->alloc, pAllocator, mem);
3286
3287 return result;
3288 }
3289
3290 VkResult radv_AllocateMemory(
3291 VkDevice _device,
3292 const VkMemoryAllocateInfo* pAllocateInfo,
3293 const VkAllocationCallbacks* pAllocator,
3294 VkDeviceMemory* pMem)
3295 {
3296 RADV_FROM_HANDLE(radv_device, device, _device);
3297 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3298 }
3299
3300 void radv_FreeMemory(
3301 VkDevice _device,
3302 VkDeviceMemory _mem,
3303 const VkAllocationCallbacks* pAllocator)
3304 {
3305 RADV_FROM_HANDLE(radv_device, device, _device);
3306 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3307
3308 if (mem == NULL)
3309 return;
3310
3311 radv_bo_list_remove(device, mem->bo);
3312 device->ws->buffer_destroy(mem->bo);
3313 mem->bo = NULL;
3314
3315 vk_free2(&device->alloc, pAllocator, mem);
3316 }
3317
3318 VkResult radv_MapMemory(
3319 VkDevice _device,
3320 VkDeviceMemory _memory,
3321 VkDeviceSize offset,
3322 VkDeviceSize size,
3323 VkMemoryMapFlags flags,
3324 void** ppData)
3325 {
3326 RADV_FROM_HANDLE(radv_device, device, _device);
3327 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3328
3329 if (mem == NULL) {
3330 *ppData = NULL;
3331 return VK_SUCCESS;
3332 }
3333
3334 if (mem->user_ptr)
3335 *ppData = mem->user_ptr;
3336 else
3337 *ppData = device->ws->buffer_map(mem->bo);
3338
3339 if (*ppData) {
3340 *ppData += offset;
3341 return VK_SUCCESS;
3342 }
3343
3344 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3345 }
3346
3347 void radv_UnmapMemory(
3348 VkDevice _device,
3349 VkDeviceMemory _memory)
3350 {
3351 RADV_FROM_HANDLE(radv_device, device, _device);
3352 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3353
3354 if (mem == NULL)
3355 return;
3356
3357 if (mem->user_ptr == NULL)
3358 device->ws->buffer_unmap(mem->bo);
3359 }
3360
3361 VkResult radv_FlushMappedMemoryRanges(
3362 VkDevice _device,
3363 uint32_t memoryRangeCount,
3364 const VkMappedMemoryRange* pMemoryRanges)
3365 {
3366 return VK_SUCCESS;
3367 }
3368
3369 VkResult radv_InvalidateMappedMemoryRanges(
3370 VkDevice _device,
3371 uint32_t memoryRangeCount,
3372 const VkMappedMemoryRange* pMemoryRanges)
3373 {
3374 return VK_SUCCESS;
3375 }
3376
3377 void radv_GetBufferMemoryRequirements(
3378 VkDevice _device,
3379 VkBuffer _buffer,
3380 VkMemoryRequirements* pMemoryRequirements)
3381 {
3382 RADV_FROM_HANDLE(radv_device, device, _device);
3383 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3384
3385 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3386
3387 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3388 pMemoryRequirements->alignment = 4096;
3389 else
3390 pMemoryRequirements->alignment = 16;
3391
3392 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3393 }
3394
3395 void radv_GetBufferMemoryRequirements2(
3396 VkDevice device,
3397 const VkBufferMemoryRequirementsInfo2 *pInfo,
3398 VkMemoryRequirements2 *pMemoryRequirements)
3399 {
3400 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3401 &pMemoryRequirements->memoryRequirements);
3402 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3403 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3404 switch (ext->sType) {
3405 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3406 VkMemoryDedicatedRequirements *req =
3407 (VkMemoryDedicatedRequirements *) ext;
3408 req->requiresDedicatedAllocation = buffer->shareable;
3409 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3410 break;
3411 }
3412 default:
3413 break;
3414 }
3415 }
3416 }
3417
3418 void radv_GetImageMemoryRequirements(
3419 VkDevice _device,
3420 VkImage _image,
3421 VkMemoryRequirements* pMemoryRequirements)
3422 {
3423 RADV_FROM_HANDLE(radv_device, device, _device);
3424 RADV_FROM_HANDLE(radv_image, image, _image);
3425
3426 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3427
3428 pMemoryRequirements->size = image->size;
3429 pMemoryRequirements->alignment = image->alignment;
3430 }
3431
3432 void radv_GetImageMemoryRequirements2(
3433 VkDevice device,
3434 const VkImageMemoryRequirementsInfo2 *pInfo,
3435 VkMemoryRequirements2 *pMemoryRequirements)
3436 {
3437 radv_GetImageMemoryRequirements(device, pInfo->image,
3438 &pMemoryRequirements->memoryRequirements);
3439
3440 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3441
3442 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3443 switch (ext->sType) {
3444 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3445 VkMemoryDedicatedRequirements *req =
3446 (VkMemoryDedicatedRequirements *) ext;
3447 req->requiresDedicatedAllocation = image->shareable;
3448 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3449 break;
3450 }
3451 default:
3452 break;
3453 }
3454 }
3455 }
3456
3457 void radv_GetImageSparseMemoryRequirements(
3458 VkDevice device,
3459 VkImage image,
3460 uint32_t* pSparseMemoryRequirementCount,
3461 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3462 {
3463 stub();
3464 }
3465
3466 void radv_GetImageSparseMemoryRequirements2(
3467 VkDevice device,
3468 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3469 uint32_t* pSparseMemoryRequirementCount,
3470 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3471 {
3472 stub();
3473 }
3474
3475 void radv_GetDeviceMemoryCommitment(
3476 VkDevice device,
3477 VkDeviceMemory memory,
3478 VkDeviceSize* pCommittedMemoryInBytes)
3479 {
3480 *pCommittedMemoryInBytes = 0;
3481 }
3482
3483 VkResult radv_BindBufferMemory2(VkDevice device,
3484 uint32_t bindInfoCount,
3485 const VkBindBufferMemoryInfo *pBindInfos)
3486 {
3487 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3488 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3489 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3490
3491 if (mem) {
3492 buffer->bo = mem->bo;
3493 buffer->offset = pBindInfos[i].memoryOffset;
3494 } else {
3495 buffer->bo = NULL;
3496 }
3497 }
3498 return VK_SUCCESS;
3499 }
3500
3501 VkResult radv_BindBufferMemory(
3502 VkDevice device,
3503 VkBuffer buffer,
3504 VkDeviceMemory memory,
3505 VkDeviceSize memoryOffset)
3506 {
3507 const VkBindBufferMemoryInfo info = {
3508 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3509 .buffer = buffer,
3510 .memory = memory,
3511 .memoryOffset = memoryOffset
3512 };
3513
3514 return radv_BindBufferMemory2(device, 1, &info);
3515 }
3516
3517 VkResult radv_BindImageMemory2(VkDevice device,
3518 uint32_t bindInfoCount,
3519 const VkBindImageMemoryInfo *pBindInfos)
3520 {
3521 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3522 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3523 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3524
3525 if (mem) {
3526 image->bo = mem->bo;
3527 image->offset = pBindInfos[i].memoryOffset;
3528 } else {
3529 image->bo = NULL;
3530 image->offset = 0;
3531 }
3532 }
3533 return VK_SUCCESS;
3534 }
3535
3536
3537 VkResult radv_BindImageMemory(
3538 VkDevice device,
3539 VkImage image,
3540 VkDeviceMemory memory,
3541 VkDeviceSize memoryOffset)
3542 {
3543 const VkBindImageMemoryInfo info = {
3544 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3545 .image = image,
3546 .memory = memory,
3547 .memoryOffset = memoryOffset
3548 };
3549
3550 return radv_BindImageMemory2(device, 1, &info);
3551 }
3552
3553
3554 static void
3555 radv_sparse_buffer_bind_memory(struct radv_device *device,
3556 const VkSparseBufferMemoryBindInfo *bind)
3557 {
3558 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3559
3560 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3561 struct radv_device_memory *mem = NULL;
3562
3563 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3564 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3565
3566 device->ws->buffer_virtual_bind(buffer->bo,
3567 bind->pBinds[i].resourceOffset,
3568 bind->pBinds[i].size,
3569 mem ? mem->bo : NULL,
3570 bind->pBinds[i].memoryOffset);
3571 }
3572 }
3573
3574 static void
3575 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3576 const VkSparseImageOpaqueMemoryBindInfo *bind)
3577 {
3578 RADV_FROM_HANDLE(radv_image, image, bind->image);
3579
3580 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3581 struct radv_device_memory *mem = NULL;
3582
3583 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3584 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3585
3586 device->ws->buffer_virtual_bind(image->bo,
3587 bind->pBinds[i].resourceOffset,
3588 bind->pBinds[i].size,
3589 mem ? mem->bo : NULL,
3590 bind->pBinds[i].memoryOffset);
3591 }
3592 }
3593
3594 VkResult radv_QueueBindSparse(
3595 VkQueue _queue,
3596 uint32_t bindInfoCount,
3597 const VkBindSparseInfo* pBindInfo,
3598 VkFence _fence)
3599 {
3600 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3601 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3602 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3603 bool fence_emitted = false;
3604 VkResult result;
3605 int ret;
3606
3607 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3608 struct radv_winsys_sem_info sem_info;
3609 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3610 radv_sparse_buffer_bind_memory(queue->device,
3611 pBindInfo[i].pBufferBinds + j);
3612 }
3613
3614 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3615 radv_sparse_image_opaque_bind_memory(queue->device,
3616 pBindInfo[i].pImageOpaqueBinds + j);
3617 }
3618
3619 VkResult result;
3620 result = radv_alloc_sem_info(queue->device->instance,
3621 &sem_info,
3622 pBindInfo[i].waitSemaphoreCount,
3623 pBindInfo[i].pWaitSemaphores,
3624 pBindInfo[i].signalSemaphoreCount,
3625 pBindInfo[i].pSignalSemaphores,
3626 _fence);
3627 if (result != VK_SUCCESS)
3628 return result;
3629
3630 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3631 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3632 &queue->device->empty_cs[queue->queue_family_index],
3633 1, NULL, NULL,
3634 &sem_info, NULL,
3635 false, base_fence);
3636 if (ret) {
3637 radv_loge("failed to submit CS %d\n", i);
3638 abort();
3639 }
3640
3641 fence_emitted = true;
3642 if (fence)
3643 fence->submitted = true;
3644 }
3645
3646 radv_free_sem_info(&sem_info);
3647
3648 }
3649
3650 if (fence) {
3651 if (!fence_emitted) {
3652 result = radv_signal_fence(queue, fence);
3653 if (result != VK_SUCCESS)
3654 return result;
3655 }
3656 fence->submitted = true;
3657 }
3658
3659 return VK_SUCCESS;
3660 }
3661
3662 VkResult radv_CreateFence(
3663 VkDevice _device,
3664 const VkFenceCreateInfo* pCreateInfo,
3665 const VkAllocationCallbacks* pAllocator,
3666 VkFence* pFence)
3667 {
3668 RADV_FROM_HANDLE(radv_device, device, _device);
3669 const VkExportFenceCreateInfo *export =
3670 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3671 VkExternalFenceHandleTypeFlags handleTypes =
3672 export ? export->handleTypes : 0;
3673
3674 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3675 sizeof(*fence), 8,
3676 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3677
3678 if (!fence)
3679 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3680
3681 fence->fence_wsi = NULL;
3682 fence->submitted = false;
3683 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3684 fence->temp_syncobj = 0;
3685 if (device->always_use_syncobj || handleTypes) {
3686 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3687 if (ret) {
3688 vk_free2(&device->alloc, pAllocator, fence);
3689 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3690 }
3691 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3692 device->ws->signal_syncobj(device->ws, fence->syncobj);
3693 }
3694 fence->fence = NULL;
3695 } else {
3696 fence->fence = device->ws->create_fence();
3697 if (!fence->fence) {
3698 vk_free2(&device->alloc, pAllocator, fence);
3699 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3700 }
3701 fence->syncobj = 0;
3702 }
3703
3704 *pFence = radv_fence_to_handle(fence);
3705
3706 return VK_SUCCESS;
3707 }
3708
3709 void radv_DestroyFence(
3710 VkDevice _device,
3711 VkFence _fence,
3712 const VkAllocationCallbacks* pAllocator)
3713 {
3714 RADV_FROM_HANDLE(radv_device, device, _device);
3715 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3716
3717 if (!fence)
3718 return;
3719
3720 if (fence->temp_syncobj)
3721 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3722 if (fence->syncobj)
3723 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3724 if (fence->fence)
3725 device->ws->destroy_fence(fence->fence);
3726 if (fence->fence_wsi)
3727 fence->fence_wsi->destroy(fence->fence_wsi);
3728 vk_free2(&device->alloc, pAllocator, fence);
3729 }
3730
3731
3732 uint64_t radv_get_current_time(void)
3733 {
3734 struct timespec tv;
3735 clock_gettime(CLOCK_MONOTONIC, &tv);
3736 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3737 }
3738
3739 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3740 {
3741 uint64_t current_time = radv_get_current_time();
3742
3743 timeout = MIN2(UINT64_MAX - current_time, timeout);
3744
3745 return current_time + timeout;
3746 }
3747
3748
3749 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3750 {
3751 for (uint32_t i = 0; i < fenceCount; ++i) {
3752 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3753 if (fence->fence == NULL || fence->syncobj ||
3754 fence->temp_syncobj ||
3755 (!fence->signalled && !fence->submitted))
3756 return false;
3757 }
3758 return true;
3759 }
3760
3761 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3762 {
3763 for (uint32_t i = 0; i < fenceCount; ++i) {
3764 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3765 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3766 return false;
3767 }
3768 return true;
3769 }
3770
3771 VkResult radv_WaitForFences(
3772 VkDevice _device,
3773 uint32_t fenceCount,
3774 const VkFence* pFences,
3775 VkBool32 waitAll,
3776 uint64_t timeout)
3777 {
3778 RADV_FROM_HANDLE(radv_device, device, _device);
3779 timeout = radv_get_absolute_timeout(timeout);
3780
3781 if (device->always_use_syncobj &&
3782 radv_all_fences_syncobj(fenceCount, pFences))
3783 {
3784 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3785 if (!handles)
3786 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3787
3788 for (uint32_t i = 0; i < fenceCount; ++i) {
3789 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3790 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3791 }
3792
3793 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3794
3795 free(handles);
3796 return success ? VK_SUCCESS : VK_TIMEOUT;
3797 }
3798
3799 if (!waitAll && fenceCount > 1) {
3800 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3801 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3802 uint32_t wait_count = 0;
3803 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3804 if (!fences)
3805 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3806
3807 for (uint32_t i = 0; i < fenceCount; ++i) {
3808 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3809
3810 if (fence->signalled) {
3811 free(fences);
3812 return VK_SUCCESS;
3813 }
3814
3815 fences[wait_count++] = fence->fence;
3816 }
3817
3818 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3819 waitAll, timeout - radv_get_current_time());
3820
3821 free(fences);
3822 return success ? VK_SUCCESS : VK_TIMEOUT;
3823 }
3824
3825 while(radv_get_current_time() <= timeout) {
3826 for (uint32_t i = 0; i < fenceCount; ++i) {
3827 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3828 return VK_SUCCESS;
3829 }
3830 }
3831 return VK_TIMEOUT;
3832 }
3833
3834 for (uint32_t i = 0; i < fenceCount; ++i) {
3835 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3836 bool expired = false;
3837
3838 if (fence->temp_syncobj) {
3839 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3840 return VK_TIMEOUT;
3841 continue;
3842 }
3843
3844 if (fence->syncobj) {
3845 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3846 return VK_TIMEOUT;
3847 continue;
3848 }
3849
3850 if (fence->signalled)
3851 continue;
3852
3853 if (fence->fence) {
3854 if (!fence->submitted) {
3855 while(radv_get_current_time() <= timeout &&
3856 !fence->submitted)
3857 /* Do nothing */;
3858
3859 if (!fence->submitted)
3860 return VK_TIMEOUT;
3861
3862 /* Recheck as it may have been set by
3863 * submitting operations. */
3864
3865 if (fence->signalled)
3866 continue;
3867 }
3868
3869 expired = device->ws->fence_wait(device->ws,
3870 fence->fence,
3871 true, timeout);
3872 if (!expired)
3873 return VK_TIMEOUT;
3874 }
3875
3876 if (fence->fence_wsi) {
3877 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3878 if (result != VK_SUCCESS)
3879 return result;
3880 }
3881
3882 fence->signalled = true;
3883 }
3884
3885 return VK_SUCCESS;
3886 }
3887
3888 VkResult radv_ResetFences(VkDevice _device,
3889 uint32_t fenceCount,
3890 const VkFence *pFences)
3891 {
3892 RADV_FROM_HANDLE(radv_device, device, _device);
3893
3894 for (unsigned i = 0; i < fenceCount; ++i) {
3895 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3896 fence->submitted = fence->signalled = false;
3897
3898 /* Per spec, we first restore the permanent payload, and then reset, so
3899 * having a temp syncobj should not skip resetting the permanent syncobj. */
3900 if (fence->temp_syncobj) {
3901 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3902 fence->temp_syncobj = 0;
3903 }
3904
3905 if (fence->syncobj) {
3906 device->ws->reset_syncobj(device->ws, fence->syncobj);
3907 }
3908 }
3909
3910 return VK_SUCCESS;
3911 }
3912
3913 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3914 {
3915 RADV_FROM_HANDLE(radv_device, device, _device);
3916 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3917
3918 if (fence->temp_syncobj) {
3919 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3920 return success ? VK_SUCCESS : VK_NOT_READY;
3921 }
3922
3923 if (fence->syncobj) {
3924 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3925 return success ? VK_SUCCESS : VK_NOT_READY;
3926 }
3927
3928 if (fence->signalled)
3929 return VK_SUCCESS;
3930 if (!fence->submitted)
3931 return VK_NOT_READY;
3932 if (fence->fence) {
3933 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3934 return VK_NOT_READY;
3935 }
3936 if (fence->fence_wsi) {
3937 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3938
3939 if (result != VK_SUCCESS) {
3940 if (result == VK_TIMEOUT)
3941 return VK_NOT_READY;
3942 return result;
3943 }
3944 }
3945 return VK_SUCCESS;
3946 }
3947
3948
3949 // Queue semaphore functions
3950
3951 VkResult radv_CreateSemaphore(
3952 VkDevice _device,
3953 const VkSemaphoreCreateInfo* pCreateInfo,
3954 const VkAllocationCallbacks* pAllocator,
3955 VkSemaphore* pSemaphore)
3956 {
3957 RADV_FROM_HANDLE(radv_device, device, _device);
3958 const VkExportSemaphoreCreateInfo *export =
3959 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3960 VkExternalSemaphoreHandleTypeFlags handleTypes =
3961 export ? export->handleTypes : 0;
3962
3963 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3964 sizeof(*sem), 8,
3965 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3966 if (!sem)
3967 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3968
3969 sem->temp_syncobj = 0;
3970 /* create a syncobject if we are going to export this semaphore */
3971 if (device->always_use_syncobj || handleTypes) {
3972 assert (device->physical_device->rad_info.has_syncobj);
3973 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3974 if (ret) {
3975 vk_free2(&device->alloc, pAllocator, sem);
3976 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3977 }
3978 sem->sem = NULL;
3979 } else {
3980 sem->sem = device->ws->create_sem(device->ws);
3981 if (!sem->sem) {
3982 vk_free2(&device->alloc, pAllocator, sem);
3983 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3984 }
3985 sem->syncobj = 0;
3986 }
3987
3988 *pSemaphore = radv_semaphore_to_handle(sem);
3989 return VK_SUCCESS;
3990 }
3991
3992 void radv_DestroySemaphore(
3993 VkDevice _device,
3994 VkSemaphore _semaphore,
3995 const VkAllocationCallbacks* pAllocator)
3996 {
3997 RADV_FROM_HANDLE(radv_device, device, _device);
3998 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3999 if (!_semaphore)
4000 return;
4001
4002 if (sem->syncobj)
4003 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4004 else
4005 device->ws->destroy_sem(sem->sem);
4006 vk_free2(&device->alloc, pAllocator, sem);
4007 }
4008
4009 VkResult radv_CreateEvent(
4010 VkDevice _device,
4011 const VkEventCreateInfo* pCreateInfo,
4012 const VkAllocationCallbacks* pAllocator,
4013 VkEvent* pEvent)
4014 {
4015 RADV_FROM_HANDLE(radv_device, device, _device);
4016 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4017 sizeof(*event), 8,
4018 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4019
4020 if (!event)
4021 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4022
4023 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4024 RADEON_DOMAIN_GTT,
4025 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4026 RADV_BO_PRIORITY_FENCE);
4027 if (!event->bo) {
4028 vk_free2(&device->alloc, pAllocator, event);
4029 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4030 }
4031
4032 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4033
4034 *pEvent = radv_event_to_handle(event);
4035
4036 return VK_SUCCESS;
4037 }
4038
4039 void radv_DestroyEvent(
4040 VkDevice _device,
4041 VkEvent _event,
4042 const VkAllocationCallbacks* pAllocator)
4043 {
4044 RADV_FROM_HANDLE(radv_device, device, _device);
4045 RADV_FROM_HANDLE(radv_event, event, _event);
4046
4047 if (!event)
4048 return;
4049 device->ws->buffer_destroy(event->bo);
4050 vk_free2(&device->alloc, pAllocator, event);
4051 }
4052
4053 VkResult radv_GetEventStatus(
4054 VkDevice _device,
4055 VkEvent _event)
4056 {
4057 RADV_FROM_HANDLE(radv_event, event, _event);
4058
4059 if (*event->map == 1)
4060 return VK_EVENT_SET;
4061 return VK_EVENT_RESET;
4062 }
4063
4064 VkResult radv_SetEvent(
4065 VkDevice _device,
4066 VkEvent _event)
4067 {
4068 RADV_FROM_HANDLE(radv_event, event, _event);
4069 *event->map = 1;
4070
4071 return VK_SUCCESS;
4072 }
4073
4074 VkResult radv_ResetEvent(
4075 VkDevice _device,
4076 VkEvent _event)
4077 {
4078 RADV_FROM_HANDLE(radv_event, event, _event);
4079 *event->map = 0;
4080
4081 return VK_SUCCESS;
4082 }
4083
4084 VkResult radv_CreateBuffer(
4085 VkDevice _device,
4086 const VkBufferCreateInfo* pCreateInfo,
4087 const VkAllocationCallbacks* pAllocator,
4088 VkBuffer* pBuffer)
4089 {
4090 RADV_FROM_HANDLE(radv_device, device, _device);
4091 struct radv_buffer *buffer;
4092
4093 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4094
4095 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4096 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4097 if (buffer == NULL)
4098 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4099
4100 buffer->size = pCreateInfo->size;
4101 buffer->usage = pCreateInfo->usage;
4102 buffer->bo = NULL;
4103 buffer->offset = 0;
4104 buffer->flags = pCreateInfo->flags;
4105
4106 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4107 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4108
4109 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4110 buffer->bo = device->ws->buffer_create(device->ws,
4111 align64(buffer->size, 4096),
4112 4096, 0, RADEON_FLAG_VIRTUAL,
4113 RADV_BO_PRIORITY_VIRTUAL);
4114 if (!buffer->bo) {
4115 vk_free2(&device->alloc, pAllocator, buffer);
4116 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4117 }
4118 }
4119
4120 *pBuffer = radv_buffer_to_handle(buffer);
4121
4122 return VK_SUCCESS;
4123 }
4124
4125 void radv_DestroyBuffer(
4126 VkDevice _device,
4127 VkBuffer _buffer,
4128 const VkAllocationCallbacks* pAllocator)
4129 {
4130 RADV_FROM_HANDLE(radv_device, device, _device);
4131 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4132
4133 if (!buffer)
4134 return;
4135
4136 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4137 device->ws->buffer_destroy(buffer->bo);
4138
4139 vk_free2(&device->alloc, pAllocator, buffer);
4140 }
4141
4142 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4143 VkDevice device,
4144 const VkBufferDeviceAddressInfoEXT* pInfo)
4145 {
4146 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4147 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4148 }
4149
4150
4151 static inline unsigned
4152 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4153 {
4154 if (stencil)
4155 return plane->surface.u.legacy.stencil_tiling_index[level];
4156 else
4157 return plane->surface.u.legacy.tiling_index[level];
4158 }
4159
4160 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4161 {
4162 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4163 }
4164
4165 static uint32_t
4166 radv_init_dcc_control_reg(struct radv_device *device,
4167 struct radv_image_view *iview)
4168 {
4169 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4170 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4171 unsigned max_compressed_block_size;
4172 unsigned independent_64b_blocks;
4173
4174 if (!radv_image_has_dcc(iview->image))
4175 return 0;
4176
4177 if (iview->image->info.samples > 1) {
4178 if (iview->image->planes[0].surface.bpe == 1)
4179 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4180 else if (iview->image->planes[0].surface.bpe == 2)
4181 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4182 }
4183
4184 if (!device->physical_device->rad_info.has_dedicated_vram) {
4185 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4186 * dGPU and 64 for APU because all of our APUs to date use
4187 * DIMMs which have a request granularity size of 64B while all
4188 * other chips have a 32B request size.
4189 */
4190 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4191 }
4192
4193 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4194 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4195 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4196 /* If this DCC image is potentially going to be used in texture
4197 * fetches, we need some special settings.
4198 */
4199 independent_64b_blocks = 1;
4200 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4201 } else {
4202 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4203 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4204 * big as possible for better compression state.
4205 */
4206 independent_64b_blocks = 0;
4207 max_compressed_block_size = max_uncompressed_block_size;
4208 }
4209
4210 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4211 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4212 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4213 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4214 }
4215
4216 static void
4217 radv_initialise_color_surface(struct radv_device *device,
4218 struct radv_color_buffer_info *cb,
4219 struct radv_image_view *iview)
4220 {
4221 const struct vk_format_description *desc;
4222 unsigned ntype, format, swap, endian;
4223 unsigned blend_clamp = 0, blend_bypass = 0;
4224 uint64_t va;
4225 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4226 const struct radeon_surf *surf = &plane->surface;
4227
4228 desc = vk_format_description(iview->vk_format);
4229
4230 memset(cb, 0, sizeof(*cb));
4231
4232 /* Intensity is implemented as Red, so treat it that way. */
4233 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4234
4235 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4236
4237 cb->cb_color_base = va >> 8;
4238
4239 if (device->physical_device->rad_info.chip_class >= GFX9) {
4240 struct gfx9_surf_meta_flags meta;
4241 if (iview->image->dcc_offset)
4242 meta = surf->u.gfx9.dcc;
4243 else
4244 meta = surf->u.gfx9.cmask;
4245
4246 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4247 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4248 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4249 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4250
4251 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4252 cb->cb_color_base |= surf->tile_swizzle;
4253
4254 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4255 } else {
4256 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4257 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4258
4259 cb->cb_color_base += level_info->offset >> 8;
4260 if (level_info->mode == RADEON_SURF_MODE_2D)
4261 cb->cb_color_base |= surf->tile_swizzle;
4262
4263 pitch_tile_max = level_info->nblk_x / 8 - 1;
4264 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4265 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4266
4267 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4268 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4269 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4270
4271 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4272
4273 if (radv_image_has_fmask(iview->image)) {
4274 if (device->physical_device->rad_info.chip_class >= CIK)
4275 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4276 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4277 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4278 } else {
4279 /* This must be set for fast clear to work without FMASK. */
4280 if (device->physical_device->rad_info.chip_class >= CIK)
4281 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4282 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4283 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4284 }
4285 }
4286
4287 /* CMASK variables */
4288 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4289 va += iview->image->cmask.offset;
4290 cb->cb_color_cmask = va >> 8;
4291
4292 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4293 va += iview->image->dcc_offset;
4294 cb->cb_dcc_base = va >> 8;
4295 cb->cb_dcc_base |= surf->tile_swizzle;
4296
4297 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4298 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4299 S_028C6C_SLICE_MAX(max_slice);
4300
4301 if (iview->image->info.samples > 1) {
4302 unsigned log_samples = util_logbase2(iview->image->info.samples);
4303
4304 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4305 S_028C74_NUM_FRAGMENTS(log_samples);
4306 }
4307
4308 if (radv_image_has_fmask(iview->image)) {
4309 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4310 cb->cb_color_fmask = va >> 8;
4311 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4312 } else {
4313 cb->cb_color_fmask = cb->cb_color_base;
4314 }
4315
4316 ntype = radv_translate_color_numformat(iview->vk_format,
4317 desc,
4318 vk_format_get_first_non_void_channel(iview->vk_format));
4319 format = radv_translate_colorformat(iview->vk_format);
4320 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4321 radv_finishme("Illegal color\n");
4322 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4323 endian = radv_colorformat_endian_swap(format);
4324
4325 /* blend clamp should be set for all NORM/SRGB types */
4326 if (ntype == V_028C70_NUMBER_UNORM ||
4327 ntype == V_028C70_NUMBER_SNORM ||
4328 ntype == V_028C70_NUMBER_SRGB)
4329 blend_clamp = 1;
4330
4331 /* set blend bypass according to docs if SINT/UINT or
4332 8/24 COLOR variants */
4333 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4334 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4335 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4336 blend_clamp = 0;
4337 blend_bypass = 1;
4338 }
4339 #if 0
4340 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4341 (format == V_028C70_COLOR_8 ||
4342 format == V_028C70_COLOR_8_8 ||
4343 format == V_028C70_COLOR_8_8_8_8))
4344 ->color_is_int8 = true;
4345 #endif
4346 cb->cb_color_info = S_028C70_FORMAT(format) |
4347 S_028C70_COMP_SWAP(swap) |
4348 S_028C70_BLEND_CLAMP(blend_clamp) |
4349 S_028C70_BLEND_BYPASS(blend_bypass) |
4350 S_028C70_SIMPLE_FLOAT(1) |
4351 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4352 ntype != V_028C70_NUMBER_SNORM &&
4353 ntype != V_028C70_NUMBER_SRGB &&
4354 format != V_028C70_COLOR_8_24 &&
4355 format != V_028C70_COLOR_24_8) |
4356 S_028C70_NUMBER_TYPE(ntype) |
4357 S_028C70_ENDIAN(endian);
4358 if (radv_image_has_fmask(iview->image)) {
4359 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4360 if (device->physical_device->rad_info.chip_class == SI) {
4361 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4362 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4363 }
4364 }
4365
4366 if (radv_image_has_cmask(iview->image) &&
4367 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4368 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4369
4370 if (radv_dcc_enabled(iview->image, iview->base_mip))
4371 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4372
4373 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4374
4375 /* This must be set for fast clear to work without FMASK. */
4376 if (!radv_image_has_fmask(iview->image) &&
4377 device->physical_device->rad_info.chip_class == SI) {
4378 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4379 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4380 }
4381
4382 if (device->physical_device->rad_info.chip_class >= GFX9) {
4383 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4384
4385 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4386 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4387 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4388 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4389
4390 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4391 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4392 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4393 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4394 S_028C68_MIP0_HEIGHT(height - 1) |
4395 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4396 }
4397 }
4398
4399 static unsigned
4400 radv_calc_decompress_on_z_planes(struct radv_device *device,
4401 struct radv_image_view *iview)
4402 {
4403 unsigned max_zplanes = 0;
4404
4405 assert(radv_image_is_tc_compat_htile(iview->image));
4406
4407 if (device->physical_device->rad_info.chip_class >= GFX9) {
4408 /* Default value for 32-bit depth surfaces. */
4409 max_zplanes = 4;
4410
4411 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4412 iview->image->info.samples > 1)
4413 max_zplanes = 2;
4414
4415 max_zplanes = max_zplanes + 1;
4416 } else {
4417 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4418 /* Do not enable Z plane compression for 16-bit depth
4419 * surfaces because isn't supported on GFX8. Only
4420 * 32-bit depth surfaces are supported by the hardware.
4421 * This allows to maintain shader compatibility and to
4422 * reduce the number of depth decompressions.
4423 */
4424 max_zplanes = 1;
4425 } else {
4426 if (iview->image->info.samples <= 1)
4427 max_zplanes = 5;
4428 else if (iview->image->info.samples <= 4)
4429 max_zplanes = 3;
4430 else
4431 max_zplanes = 2;
4432 }
4433 }
4434
4435 return max_zplanes;
4436 }
4437
4438 static void
4439 radv_initialise_ds_surface(struct radv_device *device,
4440 struct radv_ds_buffer_info *ds,
4441 struct radv_image_view *iview)
4442 {
4443 unsigned level = iview->base_mip;
4444 unsigned format, stencil_format;
4445 uint64_t va, s_offs, z_offs;
4446 bool stencil_only = false;
4447 const struct radv_image_plane *plane = &iview->image->planes[0];
4448 const struct radeon_surf *surf = &plane->surface;
4449
4450 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4451
4452 memset(ds, 0, sizeof(*ds));
4453 switch (iview->image->vk_format) {
4454 case VK_FORMAT_D24_UNORM_S8_UINT:
4455 case VK_FORMAT_X8_D24_UNORM_PACK32:
4456 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4457 ds->offset_scale = 2.0f;
4458 break;
4459 case VK_FORMAT_D16_UNORM:
4460 case VK_FORMAT_D16_UNORM_S8_UINT:
4461 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4462 ds->offset_scale = 4.0f;
4463 break;
4464 case VK_FORMAT_D32_SFLOAT:
4465 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4466 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4467 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4468 ds->offset_scale = 1.0f;
4469 break;
4470 case VK_FORMAT_S8_UINT:
4471 stencil_only = true;
4472 break;
4473 default:
4474 break;
4475 }
4476
4477 format = radv_translate_dbformat(iview->image->vk_format);
4478 stencil_format = surf->has_stencil ?
4479 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4480
4481 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4482 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4483 S_028008_SLICE_MAX(max_slice);
4484
4485 ds->db_htile_data_base = 0;
4486 ds->db_htile_surface = 0;
4487
4488 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4489 s_offs = z_offs = va;
4490
4491 if (device->physical_device->rad_info.chip_class >= GFX9) {
4492 assert(surf->u.gfx9.surf_offset == 0);
4493 s_offs += surf->u.gfx9.stencil_offset;
4494
4495 ds->db_z_info = S_028038_FORMAT(format) |
4496 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4497 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4498 S_028038_MAXMIP(iview->image->info.levels - 1) |
4499 S_028038_ZRANGE_PRECISION(1);
4500 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4501 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4502
4503 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4504 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4505 ds->db_depth_view |= S_028008_MIPID(level);
4506
4507 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4508 S_02801C_Y_MAX(iview->image->info.height - 1);
4509
4510 if (radv_htile_enabled(iview->image, level)) {
4511 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4512
4513 if (radv_image_is_tc_compat_htile(iview->image)) {
4514 unsigned max_zplanes =
4515 radv_calc_decompress_on_z_planes(device, iview);
4516
4517 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4518 S_028038_ITERATE_FLUSH(1);
4519 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4520 }
4521
4522 if (!surf->has_stencil)
4523 /* Use all of the htile_buffer for depth if there's no stencil. */
4524 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4525 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4526 iview->image->htile_offset;
4527 ds->db_htile_data_base = va >> 8;
4528 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4529 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4530 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4531 }
4532 } else {
4533 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4534
4535 if (stencil_only)
4536 level_info = &surf->u.legacy.stencil_level[level];
4537
4538 z_offs += surf->u.legacy.level[level].offset;
4539 s_offs += surf->u.legacy.stencil_level[level].offset;
4540
4541 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4542 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4543 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4544
4545 if (iview->image->info.samples > 1)
4546 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4547
4548 if (device->physical_device->rad_info.chip_class >= CIK) {
4549 struct radeon_info *info = &device->physical_device->rad_info;
4550 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4551 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4552 unsigned macro_index = surf->u.legacy.macro_tile_index;
4553 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4554 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4555 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4556
4557 if (stencil_only)
4558 tile_mode = stencil_tile_mode;
4559
4560 ds->db_depth_info |=
4561 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4562 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4563 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4564 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4565 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4566 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4567 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4568 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4569 } else {
4570 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4571 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4572 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4573 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4574 if (stencil_only)
4575 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4576 }
4577
4578 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4579 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4580 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4581
4582 if (radv_htile_enabled(iview->image, level)) {
4583 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4584
4585 if (!surf->has_stencil &&
4586 !radv_image_is_tc_compat_htile(iview->image))
4587 /* Use all of the htile_buffer for depth if there's no stencil. */
4588 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4589
4590 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4591 iview->image->htile_offset;
4592 ds->db_htile_data_base = va >> 8;
4593 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4594
4595 if (radv_image_is_tc_compat_htile(iview->image)) {
4596 unsigned max_zplanes =
4597 radv_calc_decompress_on_z_planes(device, iview);
4598
4599 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4600 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4601 }
4602 }
4603 }
4604
4605 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4606 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4607 }
4608
4609 VkResult radv_CreateFramebuffer(
4610 VkDevice _device,
4611 const VkFramebufferCreateInfo* pCreateInfo,
4612 const VkAllocationCallbacks* pAllocator,
4613 VkFramebuffer* pFramebuffer)
4614 {
4615 RADV_FROM_HANDLE(radv_device, device, _device);
4616 struct radv_framebuffer *framebuffer;
4617
4618 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4619
4620 size_t size = sizeof(*framebuffer) +
4621 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4622 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4623 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4624 if (framebuffer == NULL)
4625 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4626
4627 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4628 framebuffer->width = pCreateInfo->width;
4629 framebuffer->height = pCreateInfo->height;
4630 framebuffer->layers = pCreateInfo->layers;
4631 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4632 VkImageView _iview = pCreateInfo->pAttachments[i];
4633 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4634 framebuffer->attachments[i].attachment = iview;
4635 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4636 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4637 } else {
4638 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4639 }
4640 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4641 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4642 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4643 }
4644
4645 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4646 return VK_SUCCESS;
4647 }
4648
4649 void radv_DestroyFramebuffer(
4650 VkDevice _device,
4651 VkFramebuffer _fb,
4652 const VkAllocationCallbacks* pAllocator)
4653 {
4654 RADV_FROM_HANDLE(radv_device, device, _device);
4655 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4656
4657 if (!fb)
4658 return;
4659 vk_free2(&device->alloc, pAllocator, fb);
4660 }
4661
4662 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4663 {
4664 switch (address_mode) {
4665 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4666 return V_008F30_SQ_TEX_WRAP;
4667 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4668 return V_008F30_SQ_TEX_MIRROR;
4669 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4670 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4671 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4672 return V_008F30_SQ_TEX_CLAMP_BORDER;
4673 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4674 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4675 default:
4676 unreachable("illegal tex wrap mode");
4677 break;
4678 }
4679 }
4680
4681 static unsigned
4682 radv_tex_compare(VkCompareOp op)
4683 {
4684 switch (op) {
4685 case VK_COMPARE_OP_NEVER:
4686 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4687 case VK_COMPARE_OP_LESS:
4688 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4689 case VK_COMPARE_OP_EQUAL:
4690 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4691 case VK_COMPARE_OP_LESS_OR_EQUAL:
4692 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4693 case VK_COMPARE_OP_GREATER:
4694 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4695 case VK_COMPARE_OP_NOT_EQUAL:
4696 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4697 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4698 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4699 case VK_COMPARE_OP_ALWAYS:
4700 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4701 default:
4702 unreachable("illegal compare mode");
4703 break;
4704 }
4705 }
4706
4707 static unsigned
4708 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4709 {
4710 switch (filter) {
4711 case VK_FILTER_NEAREST:
4712 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4713 V_008F38_SQ_TEX_XY_FILTER_POINT);
4714 case VK_FILTER_LINEAR:
4715 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4716 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4717 case VK_FILTER_CUBIC_IMG:
4718 default:
4719 fprintf(stderr, "illegal texture filter");
4720 return 0;
4721 }
4722 }
4723
4724 static unsigned
4725 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4726 {
4727 switch (mode) {
4728 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4729 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4730 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4731 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4732 default:
4733 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4734 }
4735 }
4736
4737 static unsigned
4738 radv_tex_bordercolor(VkBorderColor bcolor)
4739 {
4740 switch (bcolor) {
4741 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4742 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4743 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4744 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4745 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4746 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4747 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4748 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4749 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4750 default:
4751 break;
4752 }
4753 return 0;
4754 }
4755
4756 static unsigned
4757 radv_tex_aniso_filter(unsigned filter)
4758 {
4759 if (filter < 2)
4760 return 0;
4761 if (filter < 4)
4762 return 1;
4763 if (filter < 8)
4764 return 2;
4765 if (filter < 16)
4766 return 3;
4767 return 4;
4768 }
4769
4770 static unsigned
4771 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4772 {
4773 switch (mode) {
4774 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4775 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4776 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4777 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4778 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4779 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4780 default:
4781 break;
4782 }
4783 return 0;
4784 }
4785
4786 static uint32_t
4787 radv_get_max_anisotropy(struct radv_device *device,
4788 const VkSamplerCreateInfo *pCreateInfo)
4789 {
4790 if (device->force_aniso >= 0)
4791 return device->force_aniso;
4792
4793 if (pCreateInfo->anisotropyEnable &&
4794 pCreateInfo->maxAnisotropy > 1.0f)
4795 return (uint32_t)pCreateInfo->maxAnisotropy;
4796
4797 return 0;
4798 }
4799
4800 static void
4801 radv_init_sampler(struct radv_device *device,
4802 struct radv_sampler *sampler,
4803 const VkSamplerCreateInfo *pCreateInfo)
4804 {
4805 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4806 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4807 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4808 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4809
4810 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4811 vk_find_struct_const(pCreateInfo->pNext,
4812 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4813 if (sampler_reduction)
4814 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4815
4816 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4817 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4818 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4819 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4820 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4821 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4822 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4823 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4824 S_008F30_DISABLE_CUBE_WRAP(0) |
4825 S_008F30_COMPAT_MODE(is_vi) |
4826 S_008F30_FILTER_MODE(filter_mode));
4827 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4828 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4829 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4830 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4831 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4832 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4833 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4834 S_008F38_MIP_POINT_PRECLAMP(0) |
4835 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4836 S_008F38_FILTER_PREC_FIX(1) |
4837 S_008F38_ANISO_OVERRIDE(is_vi));
4838 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4839 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4840 }
4841
4842 VkResult radv_CreateSampler(
4843 VkDevice _device,
4844 const VkSamplerCreateInfo* pCreateInfo,
4845 const VkAllocationCallbacks* pAllocator,
4846 VkSampler* pSampler)
4847 {
4848 RADV_FROM_HANDLE(radv_device, device, _device);
4849 struct radv_sampler *sampler;
4850
4851 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4852 vk_find_struct_const(pCreateInfo->pNext,
4853 SAMPLER_YCBCR_CONVERSION_INFO);
4854
4855 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4856
4857 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4858 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4859 if (!sampler)
4860 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4861
4862 radv_init_sampler(device, sampler, pCreateInfo);
4863
4864 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4865 *pSampler = radv_sampler_to_handle(sampler);
4866
4867 return VK_SUCCESS;
4868 }
4869
4870 void radv_DestroySampler(
4871 VkDevice _device,
4872 VkSampler _sampler,
4873 const VkAllocationCallbacks* pAllocator)
4874 {
4875 RADV_FROM_HANDLE(radv_device, device, _device);
4876 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4877
4878 if (!sampler)
4879 return;
4880 vk_free2(&device->alloc, pAllocator, sampler);
4881 }
4882
4883 /* vk_icd.h does not declare this function, so we declare it here to
4884 * suppress Wmissing-prototypes.
4885 */
4886 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4887 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4888
4889 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4890 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4891 {
4892 /* For the full details on loader interface versioning, see
4893 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4894 * What follows is a condensed summary, to help you navigate the large and
4895 * confusing official doc.
4896 *
4897 * - Loader interface v0 is incompatible with later versions. We don't
4898 * support it.
4899 *
4900 * - In loader interface v1:
4901 * - The first ICD entrypoint called by the loader is
4902 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4903 * entrypoint.
4904 * - The ICD must statically expose no other Vulkan symbol unless it is
4905 * linked with -Bsymbolic.
4906 * - Each dispatchable Vulkan handle created by the ICD must be
4907 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4908 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4909 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4910 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4911 * such loader-managed surfaces.
4912 *
4913 * - Loader interface v2 differs from v1 in:
4914 * - The first ICD entrypoint called by the loader is
4915 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4916 * statically expose this entrypoint.
4917 *
4918 * - Loader interface v3 differs from v2 in:
4919 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4920 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4921 * because the loader no longer does so.
4922 */
4923 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4924 return VK_SUCCESS;
4925 }
4926
4927 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4928 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4929 int *pFD)
4930 {
4931 RADV_FROM_HANDLE(radv_device, device, _device);
4932 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4933
4934 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4935
4936 /* At the moment, we support only the below handle types. */
4937 assert(pGetFdInfo->handleType ==
4938 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4939 pGetFdInfo->handleType ==
4940 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4941
4942 bool ret = radv_get_memory_fd(device, memory, pFD);
4943 if (ret == false)
4944 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4945 return VK_SUCCESS;
4946 }
4947
4948 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4949 VkExternalMemoryHandleTypeFlagBits handleType,
4950 int fd,
4951 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4952 {
4953 RADV_FROM_HANDLE(radv_device, device, _device);
4954
4955 switch (handleType) {
4956 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4957 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4958 return VK_SUCCESS;
4959
4960 default:
4961 /* The valid usage section for this function says:
4962 *
4963 * "handleType must not be one of the handle types defined as
4964 * opaque."
4965 *
4966 * So opaque handle types fall into the default "unsupported" case.
4967 */
4968 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4969 }
4970 }
4971
4972 static VkResult radv_import_opaque_fd(struct radv_device *device,
4973 int fd,
4974 uint32_t *syncobj)
4975 {
4976 uint32_t syncobj_handle = 0;
4977 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4978 if (ret != 0)
4979 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4980
4981 if (*syncobj)
4982 device->ws->destroy_syncobj(device->ws, *syncobj);
4983
4984 *syncobj = syncobj_handle;
4985 close(fd);
4986
4987 return VK_SUCCESS;
4988 }
4989
4990 static VkResult radv_import_sync_fd(struct radv_device *device,
4991 int fd,
4992 uint32_t *syncobj)
4993 {
4994 /* If we create a syncobj we do it locally so that if we have an error, we don't
4995 * leave a syncobj in an undetermined state in the fence. */
4996 uint32_t syncobj_handle = *syncobj;
4997 if (!syncobj_handle) {
4998 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4999 if (ret) {
5000 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5001 }
5002 }
5003
5004 if (fd == -1) {
5005 device->ws->signal_syncobj(device->ws, syncobj_handle);
5006 } else {
5007 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5008 if (ret != 0)
5009 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5010 }
5011
5012 *syncobj = syncobj_handle;
5013 if (fd != -1)
5014 close(fd);
5015
5016 return VK_SUCCESS;
5017 }
5018
5019 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5020 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5021 {
5022 RADV_FROM_HANDLE(radv_device, device, _device);
5023 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5024 uint32_t *syncobj_dst = NULL;
5025
5026 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5027 syncobj_dst = &sem->temp_syncobj;
5028 } else {
5029 syncobj_dst = &sem->syncobj;
5030 }
5031
5032 switch(pImportSemaphoreFdInfo->handleType) {
5033 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5034 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5035 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5036 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5037 default:
5038 unreachable("Unhandled semaphore handle type");
5039 }
5040 }
5041
5042 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5043 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5044 int *pFd)
5045 {
5046 RADV_FROM_HANDLE(radv_device, device, _device);
5047 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5048 int ret;
5049 uint32_t syncobj_handle;
5050
5051 if (sem->temp_syncobj)
5052 syncobj_handle = sem->temp_syncobj;
5053 else
5054 syncobj_handle = sem->syncobj;
5055
5056 switch(pGetFdInfo->handleType) {
5057 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5058 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5059 break;
5060 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5061 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5062 if (!ret) {
5063 if (sem->temp_syncobj) {
5064 close (sem->temp_syncobj);
5065 sem->temp_syncobj = 0;
5066 } else {
5067 device->ws->reset_syncobj(device->ws, syncobj_handle);
5068 }
5069 }
5070 break;
5071 default:
5072 unreachable("Unhandled semaphore handle type");
5073 }
5074
5075 if (ret)
5076 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5077 return VK_SUCCESS;
5078 }
5079
5080 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5081 VkPhysicalDevice physicalDevice,
5082 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5083 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5084 {
5085 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5086
5087 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5088 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5089 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5090 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5091 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5092 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5093 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5094 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5095 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5096 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5097 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5098 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5099 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5100 } else {
5101 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5102 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5103 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5104 }
5105 }
5106
5107 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5108 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5109 {
5110 RADV_FROM_HANDLE(radv_device, device, _device);
5111 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5112 uint32_t *syncobj_dst = NULL;
5113
5114
5115 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5116 syncobj_dst = &fence->temp_syncobj;
5117 } else {
5118 syncobj_dst = &fence->syncobj;
5119 }
5120
5121 switch(pImportFenceFdInfo->handleType) {
5122 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5123 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5124 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5125 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5126 default:
5127 unreachable("Unhandled fence handle type");
5128 }
5129 }
5130
5131 VkResult radv_GetFenceFdKHR(VkDevice _device,
5132 const VkFenceGetFdInfoKHR *pGetFdInfo,
5133 int *pFd)
5134 {
5135 RADV_FROM_HANDLE(radv_device, device, _device);
5136 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5137 int ret;
5138 uint32_t syncobj_handle;
5139
5140 if (fence->temp_syncobj)
5141 syncobj_handle = fence->temp_syncobj;
5142 else
5143 syncobj_handle = fence->syncobj;
5144
5145 switch(pGetFdInfo->handleType) {
5146 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5147 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5148 break;
5149 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5150 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5151 if (!ret) {
5152 if (fence->temp_syncobj) {
5153 close (fence->temp_syncobj);
5154 fence->temp_syncobj = 0;
5155 } else {
5156 device->ws->reset_syncobj(device->ws, syncobj_handle);
5157 }
5158 }
5159 break;
5160 default:
5161 unreachable("Unhandled fence handle type");
5162 }
5163
5164 if (ret)
5165 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5166 return VK_SUCCESS;
5167 }
5168
5169 void radv_GetPhysicalDeviceExternalFenceProperties(
5170 VkPhysicalDevice physicalDevice,
5171 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5172 VkExternalFenceProperties *pExternalFenceProperties)
5173 {
5174 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5175
5176 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5177 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5178 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5179 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5180 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5181 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5182 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5183 } else {
5184 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5185 pExternalFenceProperties->compatibleHandleTypes = 0;
5186 pExternalFenceProperties->externalFenceFeatures = 0;
5187 }
5188 }
5189
5190 VkResult
5191 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5192 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5193 const VkAllocationCallbacks* pAllocator,
5194 VkDebugReportCallbackEXT* pCallback)
5195 {
5196 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5197 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5198 pCreateInfo, pAllocator, &instance->alloc,
5199 pCallback);
5200 }
5201
5202 void
5203 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5204 VkDebugReportCallbackEXT _callback,
5205 const VkAllocationCallbacks* pAllocator)
5206 {
5207 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5208 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5209 _callback, pAllocator, &instance->alloc);
5210 }
5211
5212 void
5213 radv_DebugReportMessageEXT(VkInstance _instance,
5214 VkDebugReportFlagsEXT flags,
5215 VkDebugReportObjectTypeEXT objectType,
5216 uint64_t object,
5217 size_t location,
5218 int32_t messageCode,
5219 const char* pLayerPrefix,
5220 const char* pMessage)
5221 {
5222 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5223 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5224 object, location, messageCode, pLayerPrefix, pMessage);
5225 }
5226
5227 void
5228 radv_GetDeviceGroupPeerMemoryFeatures(
5229 VkDevice device,
5230 uint32_t heapIndex,
5231 uint32_t localDeviceIndex,
5232 uint32_t remoteDeviceIndex,
5233 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5234 {
5235 assert(localDeviceIndex == remoteDeviceIndex);
5236
5237 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5238 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5239 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5240 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5241 }
5242
5243 static const VkTimeDomainEXT radv_time_domains[] = {
5244 VK_TIME_DOMAIN_DEVICE_EXT,
5245 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5246 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5247 };
5248
5249 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5250 VkPhysicalDevice physicalDevice,
5251 uint32_t *pTimeDomainCount,
5252 VkTimeDomainEXT *pTimeDomains)
5253 {
5254 int d;
5255 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5256
5257 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5258 vk_outarray_append(&out, i) {
5259 *i = radv_time_domains[d];
5260 }
5261 }
5262
5263 return vk_outarray_status(&out);
5264 }
5265
5266 static uint64_t
5267 radv_clock_gettime(clockid_t clock_id)
5268 {
5269 struct timespec current;
5270 int ret;
5271
5272 ret = clock_gettime(clock_id, &current);
5273 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5274 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5275 if (ret < 0)
5276 return 0;
5277
5278 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5279 }
5280
5281 VkResult radv_GetCalibratedTimestampsEXT(
5282 VkDevice _device,
5283 uint32_t timestampCount,
5284 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5285 uint64_t *pTimestamps,
5286 uint64_t *pMaxDeviation)
5287 {
5288 RADV_FROM_HANDLE(radv_device, device, _device);
5289 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5290 int d;
5291 uint64_t begin, end;
5292 uint64_t max_clock_period = 0;
5293
5294 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5295
5296 for (d = 0; d < timestampCount; d++) {
5297 switch (pTimestampInfos[d].timeDomain) {
5298 case VK_TIME_DOMAIN_DEVICE_EXT:
5299 pTimestamps[d] = device->ws->query_value(device->ws,
5300 RADEON_TIMESTAMP);
5301 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5302 max_clock_period = MAX2(max_clock_period, device_period);
5303 break;
5304 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5305 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5306 max_clock_period = MAX2(max_clock_period, 1);
5307 break;
5308
5309 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5310 pTimestamps[d] = begin;
5311 break;
5312 default:
5313 pTimestamps[d] = 0;
5314 break;
5315 }
5316 }
5317
5318 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5319
5320 /*
5321 * The maximum deviation is the sum of the interval over which we
5322 * perform the sampling and the maximum period of any sampled
5323 * clock. That's because the maximum skew between any two sampled
5324 * clock edges is when the sampled clock with the largest period is
5325 * sampled at the end of that period but right at the beginning of the
5326 * sampling interval and some other clock is sampled right at the
5327 * begining of its sampling period and right at the end of the
5328 * sampling interval. Let's assume the GPU has the longest clock
5329 * period and that the application is sampling GPU and monotonic:
5330 *
5331 * s e
5332 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5333 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5334 *
5335 * g
5336 * 0 1 2 3
5337 * GPU -----_____-----_____-----_____-----_____
5338 *
5339 * m
5340 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5341 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5342 *
5343 * Interval <----------------->
5344 * Deviation <-------------------------->
5345 *
5346 * s = read(raw) 2
5347 * g = read(GPU) 1
5348 * m = read(monotonic) 2
5349 * e = read(raw) b
5350 *
5351 * We round the sample interval up by one tick to cover sampling error
5352 * in the interval clock
5353 */
5354
5355 uint64_t sample_interval = end - begin + 1;
5356
5357 *pMaxDeviation = sample_interval + max_clock_period;
5358
5359 return VK_SUCCESS;
5360 }