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radv: Expose VK_KHR_imageless_framebuffer.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 /* Determine the number of threads per wave for all stages. */
387 device->cs_wave_size = 64;
388 device->ps_wave_size = 64;
389 device->ge_wave_size = 64;
390
391 if (device->rad_info.chip_class >= GFX10) {
392 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
393 device->cs_wave_size = 32;
394
395 /* For pixel shaders, wave64 is recommanded. */
396 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
397 device->ps_wave_size = 32;
398
399 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
400 device->ge_wave_size = 32;
401 }
402
403 radv_physical_device_init_mem_types(device);
404 radv_fill_device_extension_table(device, &device->supported_extensions);
405
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 device->ws->destroy(device->ws);
418 vk_error(instance, result);
419 goto fail;
420 }
421
422 return VK_SUCCESS;
423
424 fail:
425 close(fd);
426 if (master_fd != -1)
427 close(master_fd);
428 return result;
429 }
430
431 static void
432 radv_physical_device_finish(struct radv_physical_device *device)
433 {
434 radv_finish_wsi(device);
435 device->ws->destroy(device->ws);
436 disk_cache_destroy(device->disk_cache);
437 close(device->local_fd);
438 if (device->master_fd != -1)
439 close(device->master_fd);
440 }
441
442 static void *
443 default_alloc_func(void *pUserData, size_t size, size_t align,
444 VkSystemAllocationScope allocationScope)
445 {
446 return malloc(size);
447 }
448
449 static void *
450 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
451 size_t align, VkSystemAllocationScope allocationScope)
452 {
453 return realloc(pOriginal, size);
454 }
455
456 static void
457 default_free_func(void *pUserData, void *pMemory)
458 {
459 free(pMemory);
460 }
461
462 static const VkAllocationCallbacks default_alloc = {
463 .pUserData = NULL,
464 .pfnAllocation = default_alloc_func,
465 .pfnReallocation = default_realloc_func,
466 .pfnFree = default_free_func,
467 };
468
469 static const struct debug_control radv_debug_options[] = {
470 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
471 {"nodcc", RADV_DEBUG_NO_DCC},
472 {"shaders", RADV_DEBUG_DUMP_SHADERS},
473 {"nocache", RADV_DEBUG_NO_CACHE},
474 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
475 {"nohiz", RADV_DEBUG_NO_HIZ},
476 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
477 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
478 {"allbos", RADV_DEBUG_ALL_BOS},
479 {"noibs", RADV_DEBUG_NO_IBS},
480 {"spirv", RADV_DEBUG_DUMP_SPIRV},
481 {"vmfaults", RADV_DEBUG_VM_FAULTS},
482 {"zerovram", RADV_DEBUG_ZERO_VRAM},
483 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
484 {"nosisched", RADV_DEBUG_NO_SISCHED},
485 {"preoptir", RADV_DEBUG_PREOPTIR},
486 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
487 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
488 {"info", RADV_DEBUG_INFO},
489 {"errors", RADV_DEBUG_ERRORS},
490 {"startup", RADV_DEBUG_STARTUP},
491 {"checkir", RADV_DEBUG_CHECKIR},
492 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
493 {"nobinning", RADV_DEBUG_NOBINNING},
494 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
495 {"nongg", RADV_DEBUG_NO_NGG},
496 {NULL, 0}
497 };
498
499 const char *
500 radv_get_debug_option_name(int id)
501 {
502 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
503 return radv_debug_options[id].string;
504 }
505
506 static const struct debug_control radv_perftest_options[] = {
507 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
508 {"sisched", RADV_PERFTEST_SISCHED},
509 {"localbos", RADV_PERFTEST_LOCAL_BOS},
510 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
511 {"bolist", RADV_PERFTEST_BO_LIST},
512 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
513 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
514 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
515 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
516 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_perftest_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
524 return radv_perftest_options[id].string;
525 }
526
527 static void
528 radv_handle_per_app_options(struct radv_instance *instance,
529 const VkApplicationInfo *info)
530 {
531 const char *name = info ? info->pApplicationName : NULL;
532
533 if (!name)
534 return;
535
536 if (!strcmp(name, "Talos - Linux - 32bit") ||
537 !strcmp(name, "Talos - Linux - 64bit")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
539 /* Force enable LLVM sisched for Talos because it looks
540 * safe and it gives few more FPS.
541 */
542 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
543 }
544 } else if (!strcmp(name, "DOOM_VFR")) {
545 /* Work around a Doom VFR game bug */
546 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
547 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
548 /* Workaround for a WaW hazard when LLVM moves/merges
549 * load/store memory operations.
550 * See https://reviews.llvm.org/D61313
551 */
552 if (HAVE_LLVM < 0x900)
553 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
554 }
555 }
556
557 static int radv_get_instance_extension_index(const char *name)
558 {
559 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
560 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
561 return i;
562 }
563 return -1;
564 }
565
566 static const char radv_dri_options_xml[] =
567 DRI_CONF_BEGIN
568 DRI_CONF_SECTION_QUALITY
569 DRI_CONF_ADAPTIVE_SYNC("true")
570 DRI_CONF_SECTION_END
571 DRI_CONF_END;
572
573 static void radv_init_dri_options(struct radv_instance *instance)
574 {
575 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
576 driParseConfigFiles(&instance->dri_options,
577 &instance->available_dri_options,
578 0, "radv", NULL);
579 }
580
581 VkResult radv_CreateInstance(
582 const VkInstanceCreateInfo* pCreateInfo,
583 const VkAllocationCallbacks* pAllocator,
584 VkInstance* pInstance)
585 {
586 struct radv_instance *instance;
587 VkResult result;
588
589 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
590
591 uint32_t client_version;
592 if (pCreateInfo->pApplicationInfo &&
593 pCreateInfo->pApplicationInfo->apiVersion != 0) {
594 client_version = pCreateInfo->pApplicationInfo->apiVersion;
595 } else {
596 client_version = VK_API_VERSION_1_0;
597 }
598
599 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
600 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
601 if (!instance)
602 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
603
604 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
605
606 if (pAllocator)
607 instance->alloc = *pAllocator;
608 else
609 instance->alloc = default_alloc;
610
611 instance->apiVersion = client_version;
612 instance->physicalDeviceCount = -1;
613
614 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
615 radv_debug_options);
616
617 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
618 radv_perftest_options);
619
620
621 if (instance->debug_flags & RADV_DEBUG_STARTUP)
622 radv_logi("Created an instance");
623
624 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
625 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
626 int index = radv_get_instance_extension_index(ext_name);
627
628 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
629 vk_free2(&default_alloc, pAllocator, instance);
630 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
631 }
632
633 instance->enabled_extensions.extensions[index] = true;
634 }
635
636 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
637 if (result != VK_SUCCESS) {
638 vk_free2(&default_alloc, pAllocator, instance);
639 return vk_error(instance, result);
640 }
641
642 _mesa_locale_init();
643 glsl_type_singleton_init_or_ref();
644
645 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
646
647 radv_init_dri_options(instance);
648 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
649
650 *pInstance = radv_instance_to_handle(instance);
651
652 return VK_SUCCESS;
653 }
654
655 void radv_DestroyInstance(
656 VkInstance _instance,
657 const VkAllocationCallbacks* pAllocator)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660
661 if (!instance)
662 return;
663
664 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
665 radv_physical_device_finish(instance->physicalDevices + i);
666 }
667
668 VG(VALGRIND_DESTROY_MEMPOOL(instance));
669
670 glsl_type_singleton_decref();
671 _mesa_locale_fini();
672
673 driDestroyOptionCache(&instance->dri_options);
674 driDestroyOptionInfo(&instance->available_dri_options);
675
676 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
677
678 vk_free(&instance->alloc, instance);
679 }
680
681 static VkResult
682 radv_enumerate_devices(struct radv_instance *instance)
683 {
684 /* TODO: Check for more devices ? */
685 drmDevicePtr devices[8];
686 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
687 int max_devices;
688
689 instance->physicalDeviceCount = 0;
690
691 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
692
693 if (instance->debug_flags & RADV_DEBUG_STARTUP)
694 radv_logi("Found %d drm nodes", max_devices);
695
696 if (max_devices < 1)
697 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
698
699 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
700 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
701 devices[i]->bustype == DRM_BUS_PCI &&
702 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
703
704 result = radv_physical_device_init(instance->physicalDevices +
705 instance->physicalDeviceCount,
706 instance,
707 devices[i]);
708 if (result == VK_SUCCESS)
709 ++instance->physicalDeviceCount;
710 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 break;
712 }
713 }
714 drmFreeDevices(devices, max_devices);
715
716 return result;
717 }
718
719 VkResult radv_EnumeratePhysicalDevices(
720 VkInstance _instance,
721 uint32_t* pPhysicalDeviceCount,
722 VkPhysicalDevice* pPhysicalDevices)
723 {
724 RADV_FROM_HANDLE(radv_instance, instance, _instance);
725 VkResult result;
726
727 if (instance->physicalDeviceCount < 0) {
728 result = radv_enumerate_devices(instance);
729 if (result != VK_SUCCESS &&
730 result != VK_ERROR_INCOMPATIBLE_DRIVER)
731 return result;
732 }
733
734 if (!pPhysicalDevices) {
735 *pPhysicalDeviceCount = instance->physicalDeviceCount;
736 } else {
737 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
738 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
739 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
740 }
741
742 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
743 : VK_SUCCESS;
744 }
745
746 VkResult radv_EnumeratePhysicalDeviceGroups(
747 VkInstance _instance,
748 uint32_t* pPhysicalDeviceGroupCount,
749 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
750 {
751 RADV_FROM_HANDLE(radv_instance, instance, _instance);
752 VkResult result;
753
754 if (instance->physicalDeviceCount < 0) {
755 result = radv_enumerate_devices(instance);
756 if (result != VK_SUCCESS &&
757 result != VK_ERROR_INCOMPATIBLE_DRIVER)
758 return result;
759 }
760
761 if (!pPhysicalDeviceGroupProperties) {
762 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
763 } else {
764 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
765 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
766 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
767 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
768 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
769 }
770 }
771 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
772 : VK_SUCCESS;
773 }
774
775 void radv_GetPhysicalDeviceFeatures(
776 VkPhysicalDevice physicalDevice,
777 VkPhysicalDeviceFeatures* pFeatures)
778 {
779 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
780 memset(pFeatures, 0, sizeof(*pFeatures));
781
782 *pFeatures = (VkPhysicalDeviceFeatures) {
783 .robustBufferAccess = true,
784 .fullDrawIndexUint32 = true,
785 .imageCubeArray = true,
786 .independentBlend = true,
787 .geometryShader = true,
788 .tessellationShader = true,
789 .sampleRateShading = true,
790 .dualSrcBlend = true,
791 .logicOp = true,
792 .multiDrawIndirect = true,
793 .drawIndirectFirstInstance = true,
794 .depthClamp = true,
795 .depthBiasClamp = true,
796 .fillModeNonSolid = true,
797 .depthBounds = true,
798 .wideLines = true,
799 .largePoints = true,
800 .alphaToOne = true,
801 .multiViewport = true,
802 .samplerAnisotropy = true,
803 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
804 .textureCompressionASTC_LDR = false,
805 .textureCompressionBC = true,
806 .occlusionQueryPrecise = true,
807 .pipelineStatisticsQuery = true,
808 .vertexPipelineStoresAndAtomics = true,
809 .fragmentStoresAndAtomics = true,
810 .shaderTessellationAndGeometryPointSize = true,
811 .shaderImageGatherExtended = true,
812 .shaderStorageImageExtendedFormats = true,
813 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
814 .shaderUniformBufferArrayDynamicIndexing = true,
815 .shaderSampledImageArrayDynamicIndexing = true,
816 .shaderStorageBufferArrayDynamicIndexing = true,
817 .shaderStorageImageArrayDynamicIndexing = true,
818 .shaderStorageImageReadWithoutFormat = true,
819 .shaderStorageImageWriteWithoutFormat = true,
820 .shaderClipDistance = true,
821 .shaderCullDistance = true,
822 .shaderFloat64 = true,
823 .shaderInt64 = true,
824 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
825 .sparseBinding = true,
826 .variableMultisampleRate = true,
827 .inheritedQueries = true,
828 };
829 }
830
831 void radv_GetPhysicalDeviceFeatures2(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceFeatures2 *pFeatures)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 vk_foreach_struct(ext, pFeatures->pNext) {
837 switch (ext->sType) {
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
839 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
840 features->variablePointersStorageBuffer = true;
841 features->variablePointers = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
845 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
846 features->multiview = true;
847 features->multiviewGeometryShader = true;
848 features->multiviewTessellationShader = true;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
852 VkPhysicalDeviceShaderDrawParametersFeatures *features =
853 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
854 features->shaderDrawParameters = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
858 VkPhysicalDeviceProtectedMemoryFeatures *features =
859 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
860 features->protectedMemory = false;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
864 VkPhysicalDevice16BitStorageFeatures *features =
865 (VkPhysicalDevice16BitStorageFeatures*)ext;
866 bool enabled = pdevice->rad_info.chip_class >= GFX8;
867 features->storageBuffer16BitAccess = enabled;
868 features->uniformAndStorageBuffer16BitAccess = enabled;
869 features->storagePushConstant16 = enabled;
870 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
874 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
875 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
876 features->samplerYcbcrConversion = true;
877 break;
878 }
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
880 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
881 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
882 features->shaderInputAttachmentArrayDynamicIndexing = true;
883 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
884 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
885 features->shaderUniformBufferArrayNonUniformIndexing = true;
886 features->shaderSampledImageArrayNonUniformIndexing = true;
887 features->shaderStorageBufferArrayNonUniformIndexing = true;
888 features->shaderStorageImageArrayNonUniformIndexing = true;
889 features->shaderInputAttachmentArrayNonUniformIndexing = true;
890 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
891 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
892 features->descriptorBindingUniformBufferUpdateAfterBind = true;
893 features->descriptorBindingSampledImageUpdateAfterBind = true;
894 features->descriptorBindingStorageImageUpdateAfterBind = true;
895 features->descriptorBindingStorageBufferUpdateAfterBind = true;
896 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
897 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
898 features->descriptorBindingUpdateUnusedWhilePending = true;
899 features->descriptorBindingPartiallyBound = true;
900 features->descriptorBindingVariableDescriptorCount = true;
901 features->runtimeDescriptorArray = true;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
905 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
906 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
907 features->conditionalRendering = true;
908 features->inheritedConditionalRendering = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
912 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
913 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
914 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
915 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
919 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
920 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
921 features->transformFeedback = true;
922 features->geometryStreams = true;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
926 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
927 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
928 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
932 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
933 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
934 features->memoryPriority = VK_TRUE;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
938 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
939 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
940 features->bufferDeviceAddress = true;
941 features->bufferDeviceAddressCaptureReplay = false;
942 features->bufferDeviceAddressMultiDevice = false;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
946 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
947 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
948 features->depthClipEnable = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
952 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
953 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
954 features->hostQueryReset = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
958 VkPhysicalDevice8BitStorageFeaturesKHR *features =
959 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
960 bool enabled = pdevice->rad_info.chip_class >= GFX8;
961 features->storageBuffer8BitAccess = enabled;
962 features->uniformAndStorageBuffer8BitAccess = enabled;
963 features->storagePushConstant8 = enabled;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
967 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
968 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
969 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
970 features->shaderInt8 = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
974 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
975 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
976 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
977 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
981 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
982 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
983
984 features->inlineUniformBlock = true;
985 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
989 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
990 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
991 features->computeDerivativeGroupQuads = false;
992 features->computeDerivativeGroupLinear = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
996 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
997 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
998 features->ycbcrImageArrays = true;
999 break;
1000 }
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1002 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1003 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1004 features->uniformBufferStandardLayout = true;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1008 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1009 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1010 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1011 break;
1012 }
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1014 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1015 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1016 features->imagelessFramebuffer = true;
1017 break;
1018 }
1019 default:
1020 break;
1021 }
1022 }
1023 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1024 }
1025
1026 void radv_GetPhysicalDeviceProperties(
1027 VkPhysicalDevice physicalDevice,
1028 VkPhysicalDeviceProperties* pProperties)
1029 {
1030 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1031 VkSampleCountFlags sample_counts = 0xf;
1032
1033 /* make sure that the entire descriptor set is addressable with a signed
1034 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1035 * be at most 2 GiB. the combined image & samples object count as one of
1036 * both. This limit is for the pipeline layout, not for the set layout, but
1037 * there is no set limit, so we just set a pipeline limit. I don't think
1038 * any app is going to hit this soon. */
1039 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1040 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1041 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1042 32 /* sampler, largest when combined with image */ +
1043 64 /* sampled image */ +
1044 64 /* storage image */);
1045
1046 VkPhysicalDeviceLimits limits = {
1047 .maxImageDimension1D = (1 << 14),
1048 .maxImageDimension2D = (1 << 14),
1049 .maxImageDimension3D = (1 << 11),
1050 .maxImageDimensionCube = (1 << 14),
1051 .maxImageArrayLayers = (1 << 11),
1052 .maxTexelBufferElements = 128 * 1024 * 1024,
1053 .maxUniformBufferRange = UINT32_MAX,
1054 .maxStorageBufferRange = UINT32_MAX,
1055 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1056 .maxMemoryAllocationCount = UINT32_MAX,
1057 .maxSamplerAllocationCount = 64 * 1024,
1058 .bufferImageGranularity = 64, /* A cache line */
1059 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1060 .maxBoundDescriptorSets = MAX_SETS,
1061 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1062 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1063 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1064 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1065 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1066 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1067 .maxPerStageResources = max_descriptor_set_size,
1068 .maxDescriptorSetSamplers = max_descriptor_set_size,
1069 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1070 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1071 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1072 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1073 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1074 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1075 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1076 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1077 .maxVertexInputBindings = MAX_VBS,
1078 .maxVertexInputAttributeOffset = 2047,
1079 .maxVertexInputBindingStride = 2048,
1080 .maxVertexOutputComponents = 128,
1081 .maxTessellationGenerationLevel = 64,
1082 .maxTessellationPatchSize = 32,
1083 .maxTessellationControlPerVertexInputComponents = 128,
1084 .maxTessellationControlPerVertexOutputComponents = 128,
1085 .maxTessellationControlPerPatchOutputComponents = 120,
1086 .maxTessellationControlTotalOutputComponents = 4096,
1087 .maxTessellationEvaluationInputComponents = 128,
1088 .maxTessellationEvaluationOutputComponents = 128,
1089 .maxGeometryShaderInvocations = 127,
1090 .maxGeometryInputComponents = 64,
1091 .maxGeometryOutputComponents = 128,
1092 .maxGeometryOutputVertices = 256,
1093 .maxGeometryTotalOutputComponents = 1024,
1094 .maxFragmentInputComponents = 128,
1095 .maxFragmentOutputAttachments = 8,
1096 .maxFragmentDualSrcAttachments = 1,
1097 .maxFragmentCombinedOutputResources = 8,
1098 .maxComputeSharedMemorySize = 32768,
1099 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1100 .maxComputeWorkGroupInvocations = 2048,
1101 .maxComputeWorkGroupSize = {
1102 2048,
1103 2048,
1104 2048
1105 },
1106 .subPixelPrecisionBits = 8,
1107 .subTexelPrecisionBits = 8,
1108 .mipmapPrecisionBits = 8,
1109 .maxDrawIndexedIndexValue = UINT32_MAX,
1110 .maxDrawIndirectCount = UINT32_MAX,
1111 .maxSamplerLodBias = 16,
1112 .maxSamplerAnisotropy = 16,
1113 .maxViewports = MAX_VIEWPORTS,
1114 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1115 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1116 .viewportSubPixelBits = 8,
1117 .minMemoryMapAlignment = 4096, /* A page */
1118 .minTexelBufferOffsetAlignment = 1,
1119 .minUniformBufferOffsetAlignment = 4,
1120 .minStorageBufferOffsetAlignment = 4,
1121 .minTexelOffset = -32,
1122 .maxTexelOffset = 31,
1123 .minTexelGatherOffset = -32,
1124 .maxTexelGatherOffset = 31,
1125 .minInterpolationOffset = -2,
1126 .maxInterpolationOffset = 2,
1127 .subPixelInterpolationOffsetBits = 8,
1128 .maxFramebufferWidth = (1 << 14),
1129 .maxFramebufferHeight = (1 << 14),
1130 .maxFramebufferLayers = (1 << 10),
1131 .framebufferColorSampleCounts = sample_counts,
1132 .framebufferDepthSampleCounts = sample_counts,
1133 .framebufferStencilSampleCounts = sample_counts,
1134 .framebufferNoAttachmentsSampleCounts = sample_counts,
1135 .maxColorAttachments = MAX_RTS,
1136 .sampledImageColorSampleCounts = sample_counts,
1137 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1138 .sampledImageDepthSampleCounts = sample_counts,
1139 .sampledImageStencilSampleCounts = sample_counts,
1140 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1141 .maxSampleMaskWords = 1,
1142 .timestampComputeAndGraphics = true,
1143 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1144 .maxClipDistances = 8,
1145 .maxCullDistances = 8,
1146 .maxCombinedClipAndCullDistances = 8,
1147 .discreteQueuePriorities = 2,
1148 .pointSizeRange = { 0.0, 8192.0 },
1149 .lineWidthRange = { 0.0, 7.9921875 },
1150 .pointSizeGranularity = (1.0 / 8.0),
1151 .lineWidthGranularity = (1.0 / 128.0),
1152 .strictLines = false, /* FINISHME */
1153 .standardSampleLocations = true,
1154 .optimalBufferCopyOffsetAlignment = 128,
1155 .optimalBufferCopyRowPitchAlignment = 128,
1156 .nonCoherentAtomSize = 64,
1157 };
1158
1159 *pProperties = (VkPhysicalDeviceProperties) {
1160 .apiVersion = radv_physical_device_api_version(pdevice),
1161 .driverVersion = vk_get_driver_version(),
1162 .vendorID = ATI_VENDOR_ID,
1163 .deviceID = pdevice->rad_info.pci_id,
1164 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1165 .limits = limits,
1166 .sparseProperties = {0},
1167 };
1168
1169 strcpy(pProperties->deviceName, pdevice->name);
1170 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1171 }
1172
1173 void radv_GetPhysicalDeviceProperties2(
1174 VkPhysicalDevice physicalDevice,
1175 VkPhysicalDeviceProperties2 *pProperties)
1176 {
1177 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1178 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1179
1180 vk_foreach_struct(ext, pProperties->pNext) {
1181 switch (ext->sType) {
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1183 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1184 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1185 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1189 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1190 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1191 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1192 properties->deviceLUIDValid = false;
1193 break;
1194 }
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1196 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1197 properties->maxMultiviewViewCount = MAX_VIEWS;
1198 properties->maxMultiviewInstanceIndex = INT_MAX;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1202 VkPhysicalDevicePointClippingProperties *properties =
1203 (VkPhysicalDevicePointClippingProperties*)ext;
1204 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1208 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1209 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1210 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1214 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1215 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1216 properties->minImportedHostPointerAlignment = 4096;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1220 VkPhysicalDeviceSubgroupProperties *properties =
1221 (VkPhysicalDeviceSubgroupProperties*)ext;
1222 properties->subgroupSize = 64;
1223 properties->supportedStages = VK_SHADER_STAGE_ALL;
1224 properties->supportedOperations =
1225 VK_SUBGROUP_FEATURE_BASIC_BIT |
1226 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1227 VK_SUBGROUP_FEATURE_QUAD_BIT |
1228 VK_SUBGROUP_FEATURE_VOTE_BIT;
1229 if (pdevice->rad_info.chip_class >= GFX8) {
1230 properties->supportedOperations |=
1231 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1232 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1233 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1234 }
1235 properties->quadOperationsInAllStages = true;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1239 VkPhysicalDeviceMaintenance3Properties *properties =
1240 (VkPhysicalDeviceMaintenance3Properties*)ext;
1241 /* Make sure everything is addressable by a signed 32-bit int, and
1242 * our largest descriptors are 96 bytes. */
1243 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1244 /* Our buffer size fields allow only this much */
1245 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1246 break;
1247 }
1248 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1249 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1250 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1251 /* GFX6-8 only support single channel min/max filter. */
1252 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1253 properties->filterMinmaxSingleComponentFormats = true;
1254 break;
1255 }
1256 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1257 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1258 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1259
1260 /* Shader engines. */
1261 properties->shaderEngineCount =
1262 pdevice->rad_info.max_se;
1263 properties->shaderArraysPerEngineCount =
1264 pdevice->rad_info.max_sh_per_se;
1265 properties->computeUnitsPerShaderArray =
1266 pdevice->rad_info.num_good_cu_per_sh;
1267 properties->simdPerComputeUnit = 4;
1268 properties->wavefrontsPerSimd =
1269 pdevice->rad_info.family == CHIP_TONGA ||
1270 pdevice->rad_info.family == CHIP_ICELAND ||
1271 pdevice->rad_info.family == CHIP_POLARIS10 ||
1272 pdevice->rad_info.family == CHIP_POLARIS11 ||
1273 pdevice->rad_info.family == CHIP_POLARIS12 ||
1274 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1275 properties->wavefrontSize = 64;
1276
1277 /* SGPR. */
1278 properties->sgprsPerSimd =
1279 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1280 properties->minSgprAllocation =
1281 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1282 properties->maxSgprAllocation =
1283 pdevice->rad_info.family == CHIP_TONGA ||
1284 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1285 properties->sgprAllocationGranularity =
1286 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1287
1288 /* VGPR. */
1289 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1290 properties->minVgprAllocation = 4;
1291 properties->maxVgprAllocation = 256;
1292 properties->vgprAllocationGranularity = 4;
1293 break;
1294 }
1295 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1296 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1297 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1298 properties->maxVertexAttribDivisor = UINT32_MAX;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1302 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1303 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1304 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1305 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1306 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1307 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1308 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1309 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1310 properties->robustBufferAccessUpdateAfterBind = false;
1311 properties->quadDivergentImplicitLod = false;
1312
1313 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1314 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1315 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1316 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1317 32 /* sampler, largest when combined with image */ +
1318 64 /* sampled image */ +
1319 64 /* storage image */);
1320 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1321 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1322 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1323 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1324 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1325 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1326 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1327 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1328 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1329 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1330 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1331 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1332 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1333 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1334 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1338 VkPhysicalDeviceProtectedMemoryProperties *properties =
1339 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1340 properties->protectedNoFault = false;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1344 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1345 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1346 properties->primitiveOverestimationSize = 0;
1347 properties->maxExtraPrimitiveOverestimationSize = 0;
1348 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1349 properties->primitiveUnderestimation = VK_FALSE;
1350 properties->conservativePointAndLineRasterization = VK_FALSE;
1351 properties->degenerateTrianglesRasterized = VK_FALSE;
1352 properties->degenerateLinesRasterized = VK_FALSE;
1353 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1354 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1355 break;
1356 }
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1358 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1359 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1360 properties->pciDomain = pdevice->bus_info.domain;
1361 properties->pciBus = pdevice->bus_info.bus;
1362 properties->pciDevice = pdevice->bus_info.dev;
1363 properties->pciFunction = pdevice->bus_info.func;
1364 break;
1365 }
1366 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1367 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1368 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1369
1370 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1371 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1372 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1373 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1374 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1375
1376 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1377 .major = 1,
1378 .minor = 1,
1379 .subminor = 2,
1380 .patch = 0,
1381 };
1382 break;
1383 }
1384 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1385 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1386 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1387 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1388 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1389 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1390 properties->maxTransformFeedbackStreamDataSize = 512;
1391 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1392 properties->maxTransformFeedbackBufferDataStride = 512;
1393 properties->transformFeedbackQueries = true;
1394 properties->transformFeedbackStreamsLinesTriangles = true;
1395 properties->transformFeedbackRasterizationStreamSelect = false;
1396 properties->transformFeedbackDraw = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1400 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1401 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1402
1403 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1404 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1405 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1406 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1407 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1408 break;
1409 }
1410 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1411 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1412 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1413 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1414 VK_SAMPLE_COUNT_4_BIT |
1415 VK_SAMPLE_COUNT_8_BIT;
1416 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1417 properties->sampleLocationCoordinateRange[0] = 0.0f;
1418 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1419 properties->sampleLocationSubPixelBits = 4;
1420 properties->variableSampleLocations = VK_FALSE;
1421 break;
1422 }
1423 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1424 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1425 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1426
1427 /* We support all of the depth resolve modes */
1428 properties->supportedDepthResolveModes =
1429 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1430 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1431 VK_RESOLVE_MODE_MIN_BIT_KHR |
1432 VK_RESOLVE_MODE_MAX_BIT_KHR;
1433
1434 /* Average doesn't make sense for stencil so we don't support that */
1435 properties->supportedStencilResolveModes =
1436 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1437 VK_RESOLVE_MODE_MIN_BIT_KHR |
1438 VK_RESOLVE_MODE_MAX_BIT_KHR;
1439
1440 properties->independentResolveNone = VK_TRUE;
1441 properties->independentResolve = VK_TRUE;
1442 break;
1443 }
1444 default:
1445 break;
1446 }
1447 }
1448 }
1449
1450 static void radv_get_physical_device_queue_family_properties(
1451 struct radv_physical_device* pdevice,
1452 uint32_t* pCount,
1453 VkQueueFamilyProperties** pQueueFamilyProperties)
1454 {
1455 int num_queue_families = 1;
1456 int idx;
1457 if (pdevice->rad_info.num_compute_rings > 0 &&
1458 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1459 num_queue_families++;
1460
1461 if (pQueueFamilyProperties == NULL) {
1462 *pCount = num_queue_families;
1463 return;
1464 }
1465
1466 if (!*pCount)
1467 return;
1468
1469 idx = 0;
1470 if (*pCount >= 1) {
1471 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1472 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1473 VK_QUEUE_COMPUTE_BIT |
1474 VK_QUEUE_TRANSFER_BIT |
1475 VK_QUEUE_SPARSE_BINDING_BIT,
1476 .queueCount = 1,
1477 .timestampValidBits = 64,
1478 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1479 };
1480 idx++;
1481 }
1482
1483 if (pdevice->rad_info.num_compute_rings > 0 &&
1484 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1485 if (*pCount > idx) {
1486 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1487 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1488 VK_QUEUE_TRANSFER_BIT |
1489 VK_QUEUE_SPARSE_BINDING_BIT,
1490 .queueCount = pdevice->rad_info.num_compute_rings,
1491 .timestampValidBits = 64,
1492 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1493 };
1494 idx++;
1495 }
1496 }
1497 *pCount = idx;
1498 }
1499
1500 void radv_GetPhysicalDeviceQueueFamilyProperties(
1501 VkPhysicalDevice physicalDevice,
1502 uint32_t* pCount,
1503 VkQueueFamilyProperties* pQueueFamilyProperties)
1504 {
1505 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1506 if (!pQueueFamilyProperties) {
1507 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1508 return;
1509 }
1510 VkQueueFamilyProperties *properties[] = {
1511 pQueueFamilyProperties + 0,
1512 pQueueFamilyProperties + 1,
1513 pQueueFamilyProperties + 2,
1514 };
1515 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1516 assert(*pCount <= 3);
1517 }
1518
1519 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1520 VkPhysicalDevice physicalDevice,
1521 uint32_t* pCount,
1522 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1523 {
1524 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1525 if (!pQueueFamilyProperties) {
1526 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1527 return;
1528 }
1529 VkQueueFamilyProperties *properties[] = {
1530 &pQueueFamilyProperties[0].queueFamilyProperties,
1531 &pQueueFamilyProperties[1].queueFamilyProperties,
1532 &pQueueFamilyProperties[2].queueFamilyProperties,
1533 };
1534 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1535 assert(*pCount <= 3);
1536 }
1537
1538 void radv_GetPhysicalDeviceMemoryProperties(
1539 VkPhysicalDevice physicalDevice,
1540 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1541 {
1542 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1543
1544 *pMemoryProperties = physical_device->memory_properties;
1545 }
1546
1547 static void
1548 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1549 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1550 {
1551 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1552 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1553 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1554 uint64_t vram_size = radv_get_vram_size(device);
1555 uint64_t gtt_size = device->rad_info.gart_size;
1556 uint64_t heap_budget, heap_usage;
1557
1558 /* For all memory heaps, the computation of budget is as follow:
1559 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1560 *
1561 * The Vulkan spec 1.1.97 says that the budget should include any
1562 * currently allocated device memory.
1563 *
1564 * Note that the application heap usages are not really accurate (eg.
1565 * in presence of shared buffers).
1566 */
1567 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1568 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1569
1570 switch (device->mem_type_indices[i]) {
1571 case RADV_MEM_TYPE_VRAM:
1572 heap_usage = device->ws->query_value(device->ws,
1573 RADEON_ALLOCATED_VRAM);
1574
1575 heap_budget = vram_size -
1576 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1577 heap_usage;
1578
1579 memoryBudget->heapBudget[heap_index] = heap_budget;
1580 memoryBudget->heapUsage[heap_index] = heap_usage;
1581 break;
1582 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1583 heap_usage = device->ws->query_value(device->ws,
1584 RADEON_ALLOCATED_VRAM_VIS);
1585
1586 heap_budget = visible_vram_size -
1587 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1588 heap_usage;
1589
1590 memoryBudget->heapBudget[heap_index] = heap_budget;
1591 memoryBudget->heapUsage[heap_index] = heap_usage;
1592 break;
1593 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1594 heap_usage = device->ws->query_value(device->ws,
1595 RADEON_ALLOCATED_GTT);
1596
1597 heap_budget = gtt_size -
1598 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1599 heap_usage;
1600
1601 memoryBudget->heapBudget[heap_index] = heap_budget;
1602 memoryBudget->heapUsage[heap_index] = heap_usage;
1603 break;
1604 default:
1605 break;
1606 }
1607 }
1608
1609 /* The heapBudget and heapUsage values must be zero for array elements
1610 * greater than or equal to
1611 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1612 */
1613 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1614 memoryBudget->heapBudget[i] = 0;
1615 memoryBudget->heapUsage[i] = 0;
1616 }
1617 }
1618
1619 void radv_GetPhysicalDeviceMemoryProperties2(
1620 VkPhysicalDevice physicalDevice,
1621 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1622 {
1623 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1624 &pMemoryProperties->memoryProperties);
1625
1626 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1627 vk_find_struct(pMemoryProperties->pNext,
1628 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1629 if (memory_budget)
1630 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1631 }
1632
1633 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1634 VkDevice _device,
1635 VkExternalMemoryHandleTypeFlagBits handleType,
1636 const void *pHostPointer,
1637 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1638 {
1639 RADV_FROM_HANDLE(radv_device, device, _device);
1640
1641 switch (handleType)
1642 {
1643 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1644 const struct radv_physical_device *physical_device = device->physical_device;
1645 uint32_t memoryTypeBits = 0;
1646 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1647 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1648 memoryTypeBits = (1 << i);
1649 break;
1650 }
1651 }
1652 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1653 return VK_SUCCESS;
1654 }
1655 default:
1656 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1657 }
1658 }
1659
1660 static enum radeon_ctx_priority
1661 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1662 {
1663 /* Default to MEDIUM when a specific global priority isn't requested */
1664 if (!pObj)
1665 return RADEON_CTX_PRIORITY_MEDIUM;
1666
1667 switch(pObj->globalPriority) {
1668 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1669 return RADEON_CTX_PRIORITY_REALTIME;
1670 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1671 return RADEON_CTX_PRIORITY_HIGH;
1672 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1673 return RADEON_CTX_PRIORITY_MEDIUM;
1674 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1675 return RADEON_CTX_PRIORITY_LOW;
1676 default:
1677 unreachable("Illegal global priority value");
1678 return RADEON_CTX_PRIORITY_INVALID;
1679 }
1680 }
1681
1682 static int
1683 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1684 uint32_t queue_family_index, int idx,
1685 VkDeviceQueueCreateFlags flags,
1686 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1687 {
1688 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1689 queue->device = device;
1690 queue->queue_family_index = queue_family_index;
1691 queue->queue_idx = idx;
1692 queue->priority = radv_get_queue_global_priority(global_priority);
1693 queue->flags = flags;
1694
1695 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1696 if (!queue->hw_ctx)
1697 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1698
1699 return VK_SUCCESS;
1700 }
1701
1702 static void
1703 radv_queue_finish(struct radv_queue *queue)
1704 {
1705 if (queue->hw_ctx)
1706 queue->device->ws->ctx_destroy(queue->hw_ctx);
1707
1708 if (queue->initial_full_flush_preamble_cs)
1709 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1710 if (queue->initial_preamble_cs)
1711 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1712 if (queue->continue_preamble_cs)
1713 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1714 if (queue->descriptor_bo)
1715 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1716 if (queue->scratch_bo)
1717 queue->device->ws->buffer_destroy(queue->scratch_bo);
1718 if (queue->esgs_ring_bo)
1719 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1720 if (queue->gsvs_ring_bo)
1721 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1722 if (queue->tess_rings_bo)
1723 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1724 if (queue->compute_scratch_bo)
1725 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1726 }
1727
1728 static void
1729 radv_bo_list_init(struct radv_bo_list *bo_list)
1730 {
1731 pthread_mutex_init(&bo_list->mutex, NULL);
1732 bo_list->list.count = bo_list->capacity = 0;
1733 bo_list->list.bos = NULL;
1734 }
1735
1736 static void
1737 radv_bo_list_finish(struct radv_bo_list *bo_list)
1738 {
1739 free(bo_list->list.bos);
1740 pthread_mutex_destroy(&bo_list->mutex);
1741 }
1742
1743 static VkResult radv_bo_list_add(struct radv_device *device,
1744 struct radeon_winsys_bo *bo)
1745 {
1746 struct radv_bo_list *bo_list = &device->bo_list;
1747
1748 if (bo->is_local)
1749 return VK_SUCCESS;
1750
1751 if (unlikely(!device->use_global_bo_list))
1752 return VK_SUCCESS;
1753
1754 pthread_mutex_lock(&bo_list->mutex);
1755 if (bo_list->list.count == bo_list->capacity) {
1756 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1757 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1758
1759 if (!data) {
1760 pthread_mutex_unlock(&bo_list->mutex);
1761 return VK_ERROR_OUT_OF_HOST_MEMORY;
1762 }
1763
1764 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1765 bo_list->capacity = capacity;
1766 }
1767
1768 bo_list->list.bos[bo_list->list.count++] = bo;
1769 pthread_mutex_unlock(&bo_list->mutex);
1770 return VK_SUCCESS;
1771 }
1772
1773 static void radv_bo_list_remove(struct radv_device *device,
1774 struct radeon_winsys_bo *bo)
1775 {
1776 struct radv_bo_list *bo_list = &device->bo_list;
1777
1778 if (bo->is_local)
1779 return;
1780
1781 if (unlikely(!device->use_global_bo_list))
1782 return;
1783
1784 pthread_mutex_lock(&bo_list->mutex);
1785 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1786 if (bo_list->list.bos[i] == bo) {
1787 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1788 --bo_list->list.count;
1789 break;
1790 }
1791 }
1792 pthread_mutex_unlock(&bo_list->mutex);
1793 }
1794
1795 static void
1796 radv_device_init_gs_info(struct radv_device *device)
1797 {
1798 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1799 device->physical_device->rad_info.family);
1800 }
1801
1802 static int radv_get_device_extension_index(const char *name)
1803 {
1804 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1805 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1806 return i;
1807 }
1808 return -1;
1809 }
1810
1811 static int
1812 radv_get_int_debug_option(const char *name, int default_value)
1813 {
1814 const char *str;
1815 int result;
1816
1817 str = getenv(name);
1818 if (!str) {
1819 result = default_value;
1820 } else {
1821 char *endptr;
1822
1823 result = strtol(str, &endptr, 0);
1824 if (str == endptr) {
1825 /* No digits founs. */
1826 result = default_value;
1827 }
1828 }
1829
1830 return result;
1831 }
1832
1833 VkResult radv_CreateDevice(
1834 VkPhysicalDevice physicalDevice,
1835 const VkDeviceCreateInfo* pCreateInfo,
1836 const VkAllocationCallbacks* pAllocator,
1837 VkDevice* pDevice)
1838 {
1839 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1840 VkResult result;
1841 struct radv_device *device;
1842
1843 bool keep_shader_info = false;
1844
1845 /* Check enabled features */
1846 if (pCreateInfo->pEnabledFeatures) {
1847 VkPhysicalDeviceFeatures supported_features;
1848 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1849 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1850 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1851 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1852 for (uint32_t i = 0; i < num_features; i++) {
1853 if (enabled_feature[i] && !supported_feature[i])
1854 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1855 }
1856 }
1857
1858 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1859 sizeof(*device), 8,
1860 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1861 if (!device)
1862 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1863
1864 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1865 device->instance = physical_device->instance;
1866 device->physical_device = physical_device;
1867
1868 device->ws = physical_device->ws;
1869 if (pAllocator)
1870 device->alloc = *pAllocator;
1871 else
1872 device->alloc = physical_device->instance->alloc;
1873
1874 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1875 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1876 int index = radv_get_device_extension_index(ext_name);
1877 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1878 vk_free(&device->alloc, device);
1879 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1880 }
1881
1882 device->enabled_extensions.extensions[index] = true;
1883 }
1884
1885 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1886
1887 /* With update after bind we can't attach bo's to the command buffer
1888 * from the descriptor set anymore, so we have to use a global BO list.
1889 */
1890 device->use_global_bo_list =
1891 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1892 device->enabled_extensions.EXT_descriptor_indexing ||
1893 device->enabled_extensions.EXT_buffer_device_address;
1894
1895 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1896 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1897
1898 mtx_init(&device->shader_slab_mutex, mtx_plain);
1899 list_inithead(&device->shader_slabs);
1900
1901 radv_bo_list_init(&device->bo_list);
1902
1903 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1904 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1905 uint32_t qfi = queue_create->queueFamilyIndex;
1906 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1907 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1908
1909 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1910
1911 device->queues[qfi] = vk_alloc(&device->alloc,
1912 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1913 if (!device->queues[qfi]) {
1914 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1915 goto fail;
1916 }
1917
1918 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1919
1920 device->queue_count[qfi] = queue_create->queueCount;
1921
1922 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1923 result = radv_queue_init(device, &device->queues[qfi][q],
1924 qfi, q, queue_create->flags,
1925 global_priority);
1926 if (result != VK_SUCCESS)
1927 goto fail;
1928 }
1929 }
1930
1931 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1932 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1933
1934 /* Disabled and not implemented for now. */
1935 device->dfsm_allowed = device->pbb_allowed &&
1936 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1937 device->physical_device->rad_info.family == CHIP_RAVEN2);
1938
1939 #ifdef ANDROID
1940 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1941 #endif
1942
1943 /* The maximum number of scratch waves. Scratch space isn't divided
1944 * evenly between CUs. The number is only a function of the number of CUs.
1945 * We can decrease the constant to decrease the scratch buffer size.
1946 *
1947 * sctx->scratch_waves must be >= the maximum possible size of
1948 * 1 threadgroup, so that the hw doesn't hang from being unable
1949 * to start any.
1950 *
1951 * The recommended value is 4 per CU at most. Higher numbers don't
1952 * bring much benefit, but they still occupy chip resources (think
1953 * async compute). I've seen ~2% performance difference between 4 and 32.
1954 */
1955 uint32_t max_threads_per_block = 2048;
1956 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1957 max_threads_per_block / 64);
1958
1959 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1960 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1961
1962 if (device->physical_device->rad_info.chip_class >= GFX7) {
1963 /* If the KMD allows it (there is a KMD hw register for it),
1964 * allow launching waves out-of-order.
1965 */
1966 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1967 }
1968
1969 radv_device_init_gs_info(device);
1970
1971 device->tess_offchip_block_dw_size =
1972 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1973 device->has_distributed_tess =
1974 device->physical_device->rad_info.chip_class >= GFX8 &&
1975 device->physical_device->rad_info.max_se >= 2;
1976
1977 if (getenv("RADV_TRACE_FILE")) {
1978 const char *filename = getenv("RADV_TRACE_FILE");
1979
1980 keep_shader_info = true;
1981
1982 if (!radv_init_trace(device))
1983 goto fail;
1984
1985 fprintf(stderr, "*****************************************************************************\n");
1986 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1987 fprintf(stderr, "*****************************************************************************\n");
1988
1989 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1990 radv_dump_enabled_options(device, stderr);
1991 }
1992
1993 device->keep_shader_info = keep_shader_info;
1994
1995 result = radv_device_init_meta(device);
1996 if (result != VK_SUCCESS)
1997 goto fail;
1998
1999 radv_device_init_msaa(device);
2000
2001 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2002 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2003 switch (family) {
2004 case RADV_QUEUE_GENERAL:
2005 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2006 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2007 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2008 break;
2009 case RADV_QUEUE_COMPUTE:
2010 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2011 radeon_emit(device->empty_cs[family], 0);
2012 break;
2013 }
2014 device->ws->cs_finalize(device->empty_cs[family]);
2015 }
2016
2017 if (device->physical_device->rad_info.chip_class >= GFX7)
2018 cik_create_gfx_config(device);
2019
2020 VkPipelineCacheCreateInfo ci;
2021 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2022 ci.pNext = NULL;
2023 ci.flags = 0;
2024 ci.pInitialData = NULL;
2025 ci.initialDataSize = 0;
2026 VkPipelineCache pc;
2027 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2028 &ci, NULL, &pc);
2029 if (result != VK_SUCCESS)
2030 goto fail_meta;
2031
2032 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2033
2034 device->force_aniso =
2035 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2036 if (device->force_aniso >= 0) {
2037 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2038 1 << util_logbase2(device->force_aniso));
2039 }
2040
2041 *pDevice = radv_device_to_handle(device);
2042 return VK_SUCCESS;
2043
2044 fail_meta:
2045 radv_device_finish_meta(device);
2046 fail:
2047 radv_bo_list_finish(&device->bo_list);
2048
2049 if (device->trace_bo)
2050 device->ws->buffer_destroy(device->trace_bo);
2051
2052 if (device->gfx_init)
2053 device->ws->buffer_destroy(device->gfx_init);
2054
2055 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2056 for (unsigned q = 0; q < device->queue_count[i]; q++)
2057 radv_queue_finish(&device->queues[i][q]);
2058 if (device->queue_count[i])
2059 vk_free(&device->alloc, device->queues[i]);
2060 }
2061
2062 vk_free(&device->alloc, device);
2063 return result;
2064 }
2065
2066 void radv_DestroyDevice(
2067 VkDevice _device,
2068 const VkAllocationCallbacks* pAllocator)
2069 {
2070 RADV_FROM_HANDLE(radv_device, device, _device);
2071
2072 if (!device)
2073 return;
2074
2075 if (device->trace_bo)
2076 device->ws->buffer_destroy(device->trace_bo);
2077
2078 if (device->gfx_init)
2079 device->ws->buffer_destroy(device->gfx_init);
2080
2081 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2082 for (unsigned q = 0; q < device->queue_count[i]; q++)
2083 radv_queue_finish(&device->queues[i][q]);
2084 if (device->queue_count[i])
2085 vk_free(&device->alloc, device->queues[i]);
2086 if (device->empty_cs[i])
2087 device->ws->cs_destroy(device->empty_cs[i]);
2088 }
2089 radv_device_finish_meta(device);
2090
2091 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2092 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2093
2094 radv_destroy_shader_slabs(device);
2095
2096 radv_bo_list_finish(&device->bo_list);
2097 vk_free(&device->alloc, device);
2098 }
2099
2100 VkResult radv_EnumerateInstanceLayerProperties(
2101 uint32_t* pPropertyCount,
2102 VkLayerProperties* pProperties)
2103 {
2104 if (pProperties == NULL) {
2105 *pPropertyCount = 0;
2106 return VK_SUCCESS;
2107 }
2108
2109 /* None supported at this time */
2110 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2111 }
2112
2113 VkResult radv_EnumerateDeviceLayerProperties(
2114 VkPhysicalDevice physicalDevice,
2115 uint32_t* pPropertyCount,
2116 VkLayerProperties* pProperties)
2117 {
2118 if (pProperties == NULL) {
2119 *pPropertyCount = 0;
2120 return VK_SUCCESS;
2121 }
2122
2123 /* None supported at this time */
2124 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2125 }
2126
2127 void radv_GetDeviceQueue2(
2128 VkDevice _device,
2129 const VkDeviceQueueInfo2* pQueueInfo,
2130 VkQueue* pQueue)
2131 {
2132 RADV_FROM_HANDLE(radv_device, device, _device);
2133 struct radv_queue *queue;
2134
2135 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2136 if (pQueueInfo->flags != queue->flags) {
2137 /* From the Vulkan 1.1.70 spec:
2138 *
2139 * "The queue returned by vkGetDeviceQueue2 must have the same
2140 * flags value from this structure as that used at device
2141 * creation time in a VkDeviceQueueCreateInfo instance. If no
2142 * matching flags were specified at device creation time then
2143 * pQueue will return VK_NULL_HANDLE."
2144 */
2145 *pQueue = VK_NULL_HANDLE;
2146 return;
2147 }
2148
2149 *pQueue = radv_queue_to_handle(queue);
2150 }
2151
2152 void radv_GetDeviceQueue(
2153 VkDevice _device,
2154 uint32_t queueFamilyIndex,
2155 uint32_t queueIndex,
2156 VkQueue* pQueue)
2157 {
2158 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2159 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2160 .queueFamilyIndex = queueFamilyIndex,
2161 .queueIndex = queueIndex
2162 };
2163
2164 radv_GetDeviceQueue2(_device, &info, pQueue);
2165 }
2166
2167 static void
2168 fill_geom_tess_rings(struct radv_queue *queue,
2169 uint32_t *map,
2170 bool add_sample_positions,
2171 uint32_t esgs_ring_size,
2172 struct radeon_winsys_bo *esgs_ring_bo,
2173 uint32_t gsvs_ring_size,
2174 struct radeon_winsys_bo *gsvs_ring_bo,
2175 uint32_t tess_factor_ring_size,
2176 uint32_t tess_offchip_ring_offset,
2177 uint32_t tess_offchip_ring_size,
2178 struct radeon_winsys_bo *tess_rings_bo)
2179 {
2180 uint32_t *desc = &map[4];
2181
2182 if (esgs_ring_bo) {
2183 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2184
2185 /* stride 0, num records - size, add tid, swizzle, elsize4,
2186 index stride 64 */
2187 desc[0] = esgs_va;
2188 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2189 S_008F04_SWIZZLE_ENABLE(true);
2190 desc[2] = esgs_ring_size;
2191 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2192 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2193 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2194 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2195 S_008F0C_INDEX_STRIDE(3) |
2196 S_008F0C_ADD_TID_ENABLE(1);
2197
2198 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2199 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2200 S_008F0C_OOB_SELECT(2) |
2201 S_008F0C_RESOURCE_LEVEL(1);
2202 } else {
2203 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2204 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2205 S_008F0C_ELEMENT_SIZE(1);
2206 }
2207
2208 /* GS entry for ES->GS ring */
2209 /* stride 0, num records - size, elsize0,
2210 index stride 0 */
2211 desc[4] = esgs_va;
2212 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2213 desc[6] = esgs_ring_size;
2214 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2215 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2216 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2217 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2218
2219 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2220 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2221 S_008F0C_OOB_SELECT(2) |
2222 S_008F0C_RESOURCE_LEVEL(1);
2223 } else {
2224 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2225 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2226 }
2227 }
2228
2229 desc += 8;
2230
2231 if (gsvs_ring_bo) {
2232 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2233
2234 /* VS entry for GS->VS ring */
2235 /* stride 0, num records - size, elsize0,
2236 index stride 0 */
2237 desc[0] = gsvs_va;
2238 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2239 desc[2] = gsvs_ring_size;
2240 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2241 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2242 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2243 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2244
2245 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2246 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2247 S_008F0C_OOB_SELECT(2) |
2248 S_008F0C_RESOURCE_LEVEL(1);
2249 } else {
2250 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2251 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2252 }
2253
2254 /* stride gsvs_itemsize, num records 64
2255 elsize 4, index stride 16 */
2256 /* shader will patch stride and desc[2] */
2257 desc[4] = gsvs_va;
2258 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2259 S_008F04_SWIZZLE_ENABLE(1);
2260 desc[6] = 0;
2261 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2262 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2263 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2264 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2265 S_008F0C_INDEX_STRIDE(1) |
2266 S_008F0C_ADD_TID_ENABLE(true);
2267
2268 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2269 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2270 S_008F0C_OOB_SELECT(2) |
2271 S_008F0C_RESOURCE_LEVEL(1);
2272 } else {
2273 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2274 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2275 S_008F0C_ELEMENT_SIZE(1);
2276 }
2277
2278 }
2279
2280 desc += 8;
2281
2282 if (tess_rings_bo) {
2283 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2284 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2285
2286 desc[0] = tess_va;
2287 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2288 desc[2] = tess_factor_ring_size;
2289 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2290 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2291 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2292 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2293
2294 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2295 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2296 S_008F0C_OOB_SELECT(3) |
2297 S_008F0C_RESOURCE_LEVEL(1);
2298 } else {
2299 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2300 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2301 }
2302
2303 desc[4] = tess_offchip_va;
2304 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2305 desc[6] = tess_offchip_ring_size;
2306 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2307 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2308 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2309 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2310
2311 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2312 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2313 S_008F0C_OOB_SELECT(3) |
2314 S_008F0C_RESOURCE_LEVEL(1);
2315 } else {
2316 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2317 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2318 }
2319 }
2320
2321 desc += 8;
2322
2323 if (add_sample_positions) {
2324 /* add sample positions after all rings */
2325 memcpy(desc, queue->device->sample_locations_1x, 8);
2326 desc += 2;
2327 memcpy(desc, queue->device->sample_locations_2x, 16);
2328 desc += 4;
2329 memcpy(desc, queue->device->sample_locations_4x, 32);
2330 desc += 8;
2331 memcpy(desc, queue->device->sample_locations_8x, 64);
2332 }
2333 }
2334
2335 static unsigned
2336 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2337 {
2338 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2339 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2340 device->physical_device->rad_info.family != CHIP_STONEY;
2341 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2342 unsigned max_offchip_buffers;
2343 unsigned offchip_granularity;
2344 unsigned hs_offchip_param;
2345
2346 /*
2347 * Per RadeonSI:
2348 * This must be one less than the maximum number due to a hw limitation.
2349 * Various hardware bugs need thGFX7
2350 *
2351 * Per AMDVLK:
2352 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2353 * Gfx7 should limit max_offchip_buffers to 508
2354 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2355 *
2356 * Follow AMDVLK here.
2357 */
2358 if (device->physical_device->rad_info.chip_class >= GFX10) {
2359 max_offchip_buffers_per_se = 256;
2360 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2361 device->physical_device->rad_info.chip_class == GFX7 ||
2362 device->physical_device->rad_info.chip_class == GFX6)
2363 --max_offchip_buffers_per_se;
2364
2365 max_offchip_buffers = max_offchip_buffers_per_se *
2366 device->physical_device->rad_info.max_se;
2367
2368 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2369 * around by setting 4K granularity.
2370 */
2371 if (device->tess_offchip_block_dw_size == 4096) {
2372 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2373 offchip_granularity = V_03093C_X_4K_DWORDS;
2374 } else {
2375 assert(device->tess_offchip_block_dw_size == 8192);
2376 offchip_granularity = V_03093C_X_8K_DWORDS;
2377 }
2378
2379 switch (device->physical_device->rad_info.chip_class) {
2380 case GFX6:
2381 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2382 break;
2383 case GFX7:
2384 case GFX8:
2385 case GFX9:
2386 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2387 break;
2388 case GFX10:
2389 break;
2390 default:
2391 break;
2392 }
2393
2394 *max_offchip_buffers_p = max_offchip_buffers;
2395 if (device->physical_device->rad_info.chip_class >= GFX7) {
2396 if (device->physical_device->rad_info.chip_class >= GFX8)
2397 --max_offchip_buffers;
2398 hs_offchip_param =
2399 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2400 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2401 } else {
2402 hs_offchip_param =
2403 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2404 }
2405 return hs_offchip_param;
2406 }
2407
2408 static void
2409 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2410 struct radeon_winsys_bo *esgs_ring_bo,
2411 uint32_t esgs_ring_size,
2412 struct radeon_winsys_bo *gsvs_ring_bo,
2413 uint32_t gsvs_ring_size)
2414 {
2415 if (!esgs_ring_bo && !gsvs_ring_bo)
2416 return;
2417
2418 if (esgs_ring_bo)
2419 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2420
2421 if (gsvs_ring_bo)
2422 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2423
2424 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2425 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2426 radeon_emit(cs, esgs_ring_size >> 8);
2427 radeon_emit(cs, gsvs_ring_size >> 8);
2428 } else {
2429 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2430 radeon_emit(cs, esgs_ring_size >> 8);
2431 radeon_emit(cs, gsvs_ring_size >> 8);
2432 }
2433 }
2434
2435 static void
2436 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2437 unsigned hs_offchip_param, unsigned tf_ring_size,
2438 struct radeon_winsys_bo *tess_rings_bo)
2439 {
2440 uint64_t tf_va;
2441
2442 if (!tess_rings_bo)
2443 return;
2444
2445 tf_va = radv_buffer_get_va(tess_rings_bo);
2446
2447 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2448
2449 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2450 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2451 S_030938_SIZE(tf_ring_size / 4));
2452 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2453 tf_va >> 8);
2454
2455 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2456 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2457 S_030984_BASE_HI(tf_va >> 40));
2458 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2459 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2460 S_030944_BASE_HI(tf_va >> 40));
2461 }
2462 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2463 hs_offchip_param);
2464 } else {
2465 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2466 S_008988_SIZE(tf_ring_size / 4));
2467 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2468 tf_va >> 8);
2469 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2470 hs_offchip_param);
2471 }
2472 }
2473
2474 static void
2475 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2476 struct radeon_winsys_bo *compute_scratch_bo)
2477 {
2478 uint64_t scratch_va;
2479
2480 if (!compute_scratch_bo)
2481 return;
2482
2483 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2484
2485 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2486
2487 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2488 radeon_emit(cs, scratch_va);
2489 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2490 S_008F04_SWIZZLE_ENABLE(1));
2491 }
2492
2493 static void
2494 radv_emit_global_shader_pointers(struct radv_queue *queue,
2495 struct radeon_cmdbuf *cs,
2496 struct radeon_winsys_bo *descriptor_bo)
2497 {
2498 uint64_t va;
2499
2500 if (!descriptor_bo)
2501 return;
2502
2503 va = radv_buffer_get_va(descriptor_bo);
2504
2505 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2506
2507 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2508 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2509 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2510 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2511 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2512
2513 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2514 radv_emit_shader_pointer(queue->device, cs, regs[i],
2515 va, true);
2516 }
2517 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2518 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2519 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2520 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2521 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2522
2523 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2524 radv_emit_shader_pointer(queue->device, cs, regs[i],
2525 va, true);
2526 }
2527 } else {
2528 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2529 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2530 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2531 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2532 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2533 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2534
2535 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2536 radv_emit_shader_pointer(queue->device, cs, regs[i],
2537 va, true);
2538 }
2539 }
2540 }
2541
2542 static void
2543 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2544 {
2545 struct radv_device *device = queue->device;
2546
2547 if (device->gfx_init) {
2548 uint64_t va = radv_buffer_get_va(device->gfx_init);
2549
2550 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2551 radeon_emit(cs, va);
2552 radeon_emit(cs, va >> 32);
2553 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2554
2555 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2556 } else {
2557 struct radv_physical_device *physical_device = device->physical_device;
2558 si_emit_graphics(physical_device, cs);
2559 }
2560 }
2561
2562 static void
2563 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2564 {
2565 struct radv_physical_device *physical_device = queue->device->physical_device;
2566 si_emit_compute(physical_device, cs);
2567 }
2568
2569 static VkResult
2570 radv_get_preamble_cs(struct radv_queue *queue,
2571 uint32_t scratch_size,
2572 uint32_t compute_scratch_size,
2573 uint32_t esgs_ring_size,
2574 uint32_t gsvs_ring_size,
2575 bool needs_tess_rings,
2576 bool needs_sample_positions,
2577 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2578 struct radeon_cmdbuf **initial_preamble_cs,
2579 struct radeon_cmdbuf **continue_preamble_cs)
2580 {
2581 struct radeon_winsys_bo *scratch_bo = NULL;
2582 struct radeon_winsys_bo *descriptor_bo = NULL;
2583 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2584 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2585 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2586 struct radeon_winsys_bo *tess_rings_bo = NULL;
2587 struct radeon_cmdbuf *dest_cs[3] = {0};
2588 bool add_tess_rings = false, add_sample_positions = false;
2589 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2590 unsigned max_offchip_buffers;
2591 unsigned hs_offchip_param = 0;
2592 unsigned tess_offchip_ring_offset;
2593 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2594 if (!queue->has_tess_rings) {
2595 if (needs_tess_rings)
2596 add_tess_rings = true;
2597 }
2598 if (!queue->has_sample_positions) {
2599 if (needs_sample_positions)
2600 add_sample_positions = true;
2601 }
2602 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2603 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2604 &max_offchip_buffers);
2605 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2606 tess_offchip_ring_size = max_offchip_buffers *
2607 queue->device->tess_offchip_block_dw_size * 4;
2608
2609 if (scratch_size <= queue->scratch_size &&
2610 compute_scratch_size <= queue->compute_scratch_size &&
2611 esgs_ring_size <= queue->esgs_ring_size &&
2612 gsvs_ring_size <= queue->gsvs_ring_size &&
2613 !add_tess_rings && !add_sample_positions &&
2614 queue->initial_preamble_cs) {
2615 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2616 *initial_preamble_cs = queue->initial_preamble_cs;
2617 *continue_preamble_cs = queue->continue_preamble_cs;
2618 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2619 *continue_preamble_cs = NULL;
2620 return VK_SUCCESS;
2621 }
2622
2623 if (scratch_size > queue->scratch_size) {
2624 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2625 scratch_size,
2626 4096,
2627 RADEON_DOMAIN_VRAM,
2628 ring_bo_flags,
2629 RADV_BO_PRIORITY_SCRATCH);
2630 if (!scratch_bo)
2631 goto fail;
2632 } else
2633 scratch_bo = queue->scratch_bo;
2634
2635 if (compute_scratch_size > queue->compute_scratch_size) {
2636 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2637 compute_scratch_size,
2638 4096,
2639 RADEON_DOMAIN_VRAM,
2640 ring_bo_flags,
2641 RADV_BO_PRIORITY_SCRATCH);
2642 if (!compute_scratch_bo)
2643 goto fail;
2644
2645 } else
2646 compute_scratch_bo = queue->compute_scratch_bo;
2647
2648 if (esgs_ring_size > queue->esgs_ring_size) {
2649 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2650 esgs_ring_size,
2651 4096,
2652 RADEON_DOMAIN_VRAM,
2653 ring_bo_flags,
2654 RADV_BO_PRIORITY_SCRATCH);
2655 if (!esgs_ring_bo)
2656 goto fail;
2657 } else {
2658 esgs_ring_bo = queue->esgs_ring_bo;
2659 esgs_ring_size = queue->esgs_ring_size;
2660 }
2661
2662 if (gsvs_ring_size > queue->gsvs_ring_size) {
2663 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2664 gsvs_ring_size,
2665 4096,
2666 RADEON_DOMAIN_VRAM,
2667 ring_bo_flags,
2668 RADV_BO_PRIORITY_SCRATCH);
2669 if (!gsvs_ring_bo)
2670 goto fail;
2671 } else {
2672 gsvs_ring_bo = queue->gsvs_ring_bo;
2673 gsvs_ring_size = queue->gsvs_ring_size;
2674 }
2675
2676 if (add_tess_rings) {
2677 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2678 tess_offchip_ring_offset + tess_offchip_ring_size,
2679 256,
2680 RADEON_DOMAIN_VRAM,
2681 ring_bo_flags,
2682 RADV_BO_PRIORITY_SCRATCH);
2683 if (!tess_rings_bo)
2684 goto fail;
2685 } else {
2686 tess_rings_bo = queue->tess_rings_bo;
2687 }
2688
2689 if (scratch_bo != queue->scratch_bo ||
2690 esgs_ring_bo != queue->esgs_ring_bo ||
2691 gsvs_ring_bo != queue->gsvs_ring_bo ||
2692 tess_rings_bo != queue->tess_rings_bo ||
2693 add_sample_positions) {
2694 uint32_t size = 0;
2695 if (gsvs_ring_bo || esgs_ring_bo ||
2696 tess_rings_bo || add_sample_positions) {
2697 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2698 if (add_sample_positions)
2699 size += 128; /* 64+32+16+8 = 120 bytes */
2700 }
2701 else if (scratch_bo)
2702 size = 8; /* 2 dword */
2703
2704 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2705 size,
2706 4096,
2707 RADEON_DOMAIN_VRAM,
2708 RADEON_FLAG_CPU_ACCESS |
2709 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2710 RADEON_FLAG_READ_ONLY,
2711 RADV_BO_PRIORITY_DESCRIPTOR);
2712 if (!descriptor_bo)
2713 goto fail;
2714 } else
2715 descriptor_bo = queue->descriptor_bo;
2716
2717 if (descriptor_bo != queue->descriptor_bo) {
2718 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2719
2720 if (scratch_bo) {
2721 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2722 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2723 S_008F04_SWIZZLE_ENABLE(1);
2724 map[0] = scratch_va;
2725 map[1] = rsrc1;
2726 }
2727
2728 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2729 fill_geom_tess_rings(queue, map, add_sample_positions,
2730 esgs_ring_size, esgs_ring_bo,
2731 gsvs_ring_size, gsvs_ring_bo,
2732 tess_factor_ring_size,
2733 tess_offchip_ring_offset,
2734 tess_offchip_ring_size,
2735 tess_rings_bo);
2736
2737 queue->device->ws->buffer_unmap(descriptor_bo);
2738 }
2739
2740 for(int i = 0; i < 3; ++i) {
2741 struct radeon_cmdbuf *cs = NULL;
2742 cs = queue->device->ws->cs_create(queue->device->ws,
2743 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2744 if (!cs)
2745 goto fail;
2746
2747 dest_cs[i] = cs;
2748
2749 if (scratch_bo)
2750 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2751
2752 /* Emit initial configuration. */
2753 switch (queue->queue_family_index) {
2754 case RADV_QUEUE_GENERAL:
2755 radv_init_graphics_state(cs, queue);
2756 break;
2757 case RADV_QUEUE_COMPUTE:
2758 radv_init_compute_state(cs, queue);
2759 break;
2760 case RADV_QUEUE_TRANSFER:
2761 break;
2762 }
2763
2764 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2765 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2766 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2767
2768 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2769 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2770 }
2771
2772 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2773 gsvs_ring_bo, gsvs_ring_size);
2774 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2775 tess_factor_ring_size, tess_rings_bo);
2776 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2777 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2778
2779 if (i == 0) {
2780 si_cs_emit_cache_flush(cs,
2781 queue->device->physical_device->rad_info.chip_class,
2782 NULL, 0,
2783 queue->queue_family_index == RING_COMPUTE &&
2784 queue->device->physical_device->rad_info.chip_class >= GFX7,
2785 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2786 RADV_CMD_FLAG_INV_ICACHE |
2787 RADV_CMD_FLAG_INV_SCACHE |
2788 RADV_CMD_FLAG_INV_VCACHE |
2789 RADV_CMD_FLAG_INV_L2 |
2790 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2791 } else if (i == 1) {
2792 si_cs_emit_cache_flush(cs,
2793 queue->device->physical_device->rad_info.chip_class,
2794 NULL, 0,
2795 queue->queue_family_index == RING_COMPUTE &&
2796 queue->device->physical_device->rad_info.chip_class >= GFX7,
2797 RADV_CMD_FLAG_INV_ICACHE |
2798 RADV_CMD_FLAG_INV_SCACHE |
2799 RADV_CMD_FLAG_INV_VCACHE |
2800 RADV_CMD_FLAG_INV_L2 |
2801 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2802 }
2803
2804 if (!queue->device->ws->cs_finalize(cs))
2805 goto fail;
2806 }
2807
2808 if (queue->initial_full_flush_preamble_cs)
2809 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2810
2811 if (queue->initial_preamble_cs)
2812 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2813
2814 if (queue->continue_preamble_cs)
2815 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2816
2817 queue->initial_full_flush_preamble_cs = dest_cs[0];
2818 queue->initial_preamble_cs = dest_cs[1];
2819 queue->continue_preamble_cs = dest_cs[2];
2820
2821 if (scratch_bo != queue->scratch_bo) {
2822 if (queue->scratch_bo)
2823 queue->device->ws->buffer_destroy(queue->scratch_bo);
2824 queue->scratch_bo = scratch_bo;
2825 queue->scratch_size = scratch_size;
2826 }
2827
2828 if (compute_scratch_bo != queue->compute_scratch_bo) {
2829 if (queue->compute_scratch_bo)
2830 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2831 queue->compute_scratch_bo = compute_scratch_bo;
2832 queue->compute_scratch_size = compute_scratch_size;
2833 }
2834
2835 if (esgs_ring_bo != queue->esgs_ring_bo) {
2836 if (queue->esgs_ring_bo)
2837 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2838 queue->esgs_ring_bo = esgs_ring_bo;
2839 queue->esgs_ring_size = esgs_ring_size;
2840 }
2841
2842 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2843 if (queue->gsvs_ring_bo)
2844 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2845 queue->gsvs_ring_bo = gsvs_ring_bo;
2846 queue->gsvs_ring_size = gsvs_ring_size;
2847 }
2848
2849 if (tess_rings_bo != queue->tess_rings_bo) {
2850 queue->tess_rings_bo = tess_rings_bo;
2851 queue->has_tess_rings = true;
2852 }
2853
2854 if (descriptor_bo != queue->descriptor_bo) {
2855 if (queue->descriptor_bo)
2856 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2857
2858 queue->descriptor_bo = descriptor_bo;
2859 }
2860
2861 if (add_sample_positions)
2862 queue->has_sample_positions = true;
2863
2864 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2865 *initial_preamble_cs = queue->initial_preamble_cs;
2866 *continue_preamble_cs = queue->continue_preamble_cs;
2867 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2868 *continue_preamble_cs = NULL;
2869 return VK_SUCCESS;
2870 fail:
2871 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2872 if (dest_cs[i])
2873 queue->device->ws->cs_destroy(dest_cs[i]);
2874 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2875 queue->device->ws->buffer_destroy(descriptor_bo);
2876 if (scratch_bo && scratch_bo != queue->scratch_bo)
2877 queue->device->ws->buffer_destroy(scratch_bo);
2878 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2879 queue->device->ws->buffer_destroy(compute_scratch_bo);
2880 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2881 queue->device->ws->buffer_destroy(esgs_ring_bo);
2882 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2883 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2884 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2885 queue->device->ws->buffer_destroy(tess_rings_bo);
2886 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2887 }
2888
2889 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2890 struct radv_winsys_sem_counts *counts,
2891 int num_sems,
2892 const VkSemaphore *sems,
2893 VkFence _fence,
2894 bool reset_temp)
2895 {
2896 int syncobj_idx = 0, sem_idx = 0;
2897
2898 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2899 return VK_SUCCESS;
2900
2901 for (uint32_t i = 0; i < num_sems; i++) {
2902 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2903
2904 if (sem->temp_syncobj || sem->syncobj)
2905 counts->syncobj_count++;
2906 else
2907 counts->sem_count++;
2908 }
2909
2910 if (_fence != VK_NULL_HANDLE) {
2911 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2912 if (fence->temp_syncobj || fence->syncobj)
2913 counts->syncobj_count++;
2914 }
2915
2916 if (counts->syncobj_count) {
2917 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2918 if (!counts->syncobj)
2919 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2920 }
2921
2922 if (counts->sem_count) {
2923 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2924 if (!counts->sem) {
2925 free(counts->syncobj);
2926 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2927 }
2928 }
2929
2930 for (uint32_t i = 0; i < num_sems; i++) {
2931 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2932
2933 if (sem->temp_syncobj) {
2934 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2935 }
2936 else if (sem->syncobj)
2937 counts->syncobj[syncobj_idx++] = sem->syncobj;
2938 else {
2939 assert(sem->sem);
2940 counts->sem[sem_idx++] = sem->sem;
2941 }
2942 }
2943
2944 if (_fence != VK_NULL_HANDLE) {
2945 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2946 if (fence->temp_syncobj)
2947 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2948 else if (fence->syncobj)
2949 counts->syncobj[syncobj_idx++] = fence->syncobj;
2950 }
2951
2952 return VK_SUCCESS;
2953 }
2954
2955 static void
2956 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2957 {
2958 free(sem_info->wait.syncobj);
2959 free(sem_info->wait.sem);
2960 free(sem_info->signal.syncobj);
2961 free(sem_info->signal.sem);
2962 }
2963
2964
2965 static void radv_free_temp_syncobjs(struct radv_device *device,
2966 int num_sems,
2967 const VkSemaphore *sems)
2968 {
2969 for (uint32_t i = 0; i < num_sems; i++) {
2970 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2971
2972 if (sem->temp_syncobj) {
2973 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2974 sem->temp_syncobj = 0;
2975 }
2976 }
2977 }
2978
2979 static VkResult
2980 radv_alloc_sem_info(struct radv_instance *instance,
2981 struct radv_winsys_sem_info *sem_info,
2982 int num_wait_sems,
2983 const VkSemaphore *wait_sems,
2984 int num_signal_sems,
2985 const VkSemaphore *signal_sems,
2986 VkFence fence)
2987 {
2988 VkResult ret;
2989 memset(sem_info, 0, sizeof(*sem_info));
2990
2991 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2992 if (ret)
2993 return ret;
2994 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2995 if (ret)
2996 radv_free_sem_info(sem_info);
2997
2998 /* caller can override these */
2999 sem_info->cs_emit_wait = true;
3000 sem_info->cs_emit_signal = true;
3001 return ret;
3002 }
3003
3004 /* Signals fence as soon as all the work currently put on queue is done. */
3005 static VkResult radv_signal_fence(struct radv_queue *queue,
3006 struct radv_fence *fence)
3007 {
3008 int ret;
3009 VkResult result;
3010 struct radv_winsys_sem_info sem_info;
3011
3012 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3013 radv_fence_to_handle(fence));
3014 if (result != VK_SUCCESS)
3015 return result;
3016
3017 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3018 &queue->device->empty_cs[queue->queue_family_index],
3019 1, NULL, NULL, &sem_info, NULL,
3020 false, fence->fence);
3021 radv_free_sem_info(&sem_info);
3022
3023 if (ret)
3024 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3025
3026 return VK_SUCCESS;
3027 }
3028
3029 VkResult radv_QueueSubmit(
3030 VkQueue _queue,
3031 uint32_t submitCount,
3032 const VkSubmitInfo* pSubmits,
3033 VkFence _fence)
3034 {
3035 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3036 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3037 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3038 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3039 int ret;
3040 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3041 uint32_t scratch_size = 0;
3042 uint32_t compute_scratch_size = 0;
3043 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3044 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3045 VkResult result;
3046 bool fence_emitted = false;
3047 bool tess_rings_needed = false;
3048 bool sample_positions_needed = false;
3049
3050 /* Do this first so failing to allocate scratch buffers can't result in
3051 * partially executed submissions. */
3052 for (uint32_t i = 0; i < submitCount; i++) {
3053 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3054 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3055 pSubmits[i].pCommandBuffers[j]);
3056
3057 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3058 compute_scratch_size = MAX2(compute_scratch_size,
3059 cmd_buffer->compute_scratch_size_needed);
3060 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3061 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3062 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3063 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3064 }
3065 }
3066
3067 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3068 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3069 sample_positions_needed, &initial_flush_preamble_cs,
3070 &initial_preamble_cs, &continue_preamble_cs);
3071 if (result != VK_SUCCESS)
3072 return result;
3073
3074 for (uint32_t i = 0; i < submitCount; i++) {
3075 struct radeon_cmdbuf **cs_array;
3076 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3077 bool can_patch = true;
3078 uint32_t advance;
3079 struct radv_winsys_sem_info sem_info;
3080
3081 result = radv_alloc_sem_info(queue->device->instance,
3082 &sem_info,
3083 pSubmits[i].waitSemaphoreCount,
3084 pSubmits[i].pWaitSemaphores,
3085 pSubmits[i].signalSemaphoreCount,
3086 pSubmits[i].pSignalSemaphores,
3087 _fence);
3088 if (result != VK_SUCCESS)
3089 return result;
3090
3091 if (!pSubmits[i].commandBufferCount) {
3092 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3093 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3094 &queue->device->empty_cs[queue->queue_family_index],
3095 1, NULL, NULL,
3096 &sem_info, NULL,
3097 false, base_fence);
3098 if (ret) {
3099 radv_loge("failed to submit CS %d\n", i);
3100 abort();
3101 }
3102 fence_emitted = true;
3103 }
3104 radv_free_sem_info(&sem_info);
3105 continue;
3106 }
3107
3108 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3109 (pSubmits[i].commandBufferCount));
3110
3111 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3112 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3113 pSubmits[i].pCommandBuffers[j]);
3114 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3115
3116 cs_array[j] = cmd_buffer->cs;
3117 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3118 can_patch = false;
3119
3120 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3121 }
3122
3123 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3124 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3125 const struct radv_winsys_bo_list *bo_list = NULL;
3126
3127 advance = MIN2(max_cs_submission,
3128 pSubmits[i].commandBufferCount - j);
3129
3130 if (queue->device->trace_bo)
3131 *queue->device->trace_id_ptr = 0;
3132
3133 sem_info.cs_emit_wait = j == 0;
3134 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3135
3136 if (unlikely(queue->device->use_global_bo_list)) {
3137 pthread_mutex_lock(&queue->device->bo_list.mutex);
3138 bo_list = &queue->device->bo_list.list;
3139 }
3140
3141 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3142 advance, initial_preamble, continue_preamble_cs,
3143 &sem_info, bo_list,
3144 can_patch, base_fence);
3145
3146 if (unlikely(queue->device->use_global_bo_list))
3147 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3148
3149 if (ret) {
3150 radv_loge("failed to submit CS %d\n", i);
3151 abort();
3152 }
3153 fence_emitted = true;
3154 if (queue->device->trace_bo) {
3155 radv_check_gpu_hangs(queue, cs_array[j]);
3156 }
3157 }
3158
3159 radv_free_temp_syncobjs(queue->device,
3160 pSubmits[i].waitSemaphoreCount,
3161 pSubmits[i].pWaitSemaphores);
3162 radv_free_sem_info(&sem_info);
3163 free(cs_array);
3164 }
3165
3166 if (fence) {
3167 if (!fence_emitted) {
3168 result = radv_signal_fence(queue, fence);
3169 if (result != VK_SUCCESS)
3170 return result;
3171 }
3172 }
3173
3174 return VK_SUCCESS;
3175 }
3176
3177 VkResult radv_QueueWaitIdle(
3178 VkQueue _queue)
3179 {
3180 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3181
3182 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3183 radv_queue_family_to_ring(queue->queue_family_index),
3184 queue->queue_idx);
3185 return VK_SUCCESS;
3186 }
3187
3188 VkResult radv_DeviceWaitIdle(
3189 VkDevice _device)
3190 {
3191 RADV_FROM_HANDLE(radv_device, device, _device);
3192
3193 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3194 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3195 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3196 }
3197 }
3198 return VK_SUCCESS;
3199 }
3200
3201 VkResult radv_EnumerateInstanceExtensionProperties(
3202 const char* pLayerName,
3203 uint32_t* pPropertyCount,
3204 VkExtensionProperties* pProperties)
3205 {
3206 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3207
3208 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3209 if (radv_supported_instance_extensions.extensions[i]) {
3210 vk_outarray_append(&out, prop) {
3211 *prop = radv_instance_extensions[i];
3212 }
3213 }
3214 }
3215
3216 return vk_outarray_status(&out);
3217 }
3218
3219 VkResult radv_EnumerateDeviceExtensionProperties(
3220 VkPhysicalDevice physicalDevice,
3221 const char* pLayerName,
3222 uint32_t* pPropertyCount,
3223 VkExtensionProperties* pProperties)
3224 {
3225 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3226 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3227
3228 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3229 if (device->supported_extensions.extensions[i]) {
3230 vk_outarray_append(&out, prop) {
3231 *prop = radv_device_extensions[i];
3232 }
3233 }
3234 }
3235
3236 return vk_outarray_status(&out);
3237 }
3238
3239 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3240 VkInstance _instance,
3241 const char* pName)
3242 {
3243 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3244
3245 return radv_lookup_entrypoint_checked(pName,
3246 instance ? instance->apiVersion : 0,
3247 instance ? &instance->enabled_extensions : NULL,
3248 NULL);
3249 }
3250
3251 /* The loader wants us to expose a second GetInstanceProcAddr function
3252 * to work around certain LD_PRELOAD issues seen in apps.
3253 */
3254 PUBLIC
3255 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3256 VkInstance instance,
3257 const char* pName);
3258
3259 PUBLIC
3260 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3261 VkInstance instance,
3262 const char* pName)
3263 {
3264 return radv_GetInstanceProcAddr(instance, pName);
3265 }
3266
3267 PUBLIC
3268 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3269 VkInstance _instance,
3270 const char* pName);
3271
3272 PUBLIC
3273 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3274 VkInstance _instance,
3275 const char* pName)
3276 {
3277 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3278
3279 return radv_lookup_physical_device_entrypoint_checked(pName,
3280 instance ? instance->apiVersion : 0,
3281 instance ? &instance->enabled_extensions : NULL);
3282 }
3283
3284 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3285 VkDevice _device,
3286 const char* pName)
3287 {
3288 RADV_FROM_HANDLE(radv_device, device, _device);
3289
3290 return radv_lookup_entrypoint_checked(pName,
3291 device->instance->apiVersion,
3292 &device->instance->enabled_extensions,
3293 &device->enabled_extensions);
3294 }
3295
3296 bool radv_get_memory_fd(struct radv_device *device,
3297 struct radv_device_memory *memory,
3298 int *pFD)
3299 {
3300 struct radeon_bo_metadata metadata;
3301
3302 if (memory->image) {
3303 radv_init_metadata(device, memory->image, &metadata);
3304 device->ws->buffer_set_metadata(memory->bo, &metadata);
3305 }
3306
3307 return device->ws->buffer_get_fd(device->ws, memory->bo,
3308 pFD);
3309 }
3310
3311 static VkResult radv_alloc_memory(struct radv_device *device,
3312 const VkMemoryAllocateInfo* pAllocateInfo,
3313 const VkAllocationCallbacks* pAllocator,
3314 VkDeviceMemory* pMem)
3315 {
3316 struct radv_device_memory *mem;
3317 VkResult result;
3318 enum radeon_bo_domain domain;
3319 uint32_t flags = 0;
3320 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3321
3322 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3323
3324 if (pAllocateInfo->allocationSize == 0) {
3325 /* Apparently, this is allowed */
3326 *pMem = VK_NULL_HANDLE;
3327 return VK_SUCCESS;
3328 }
3329
3330 const VkImportMemoryFdInfoKHR *import_info =
3331 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3332 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3333 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3334 const VkExportMemoryAllocateInfo *export_info =
3335 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3336 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3337 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3338
3339 const struct wsi_memory_allocate_info *wsi_info =
3340 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3341
3342 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3343 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3344 if (mem == NULL)
3345 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3346
3347 if (wsi_info && wsi_info->implicit_sync)
3348 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3349
3350 if (dedicate_info) {
3351 mem->image = radv_image_from_handle(dedicate_info->image);
3352 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3353 } else {
3354 mem->image = NULL;
3355 mem->buffer = NULL;
3356 }
3357
3358 float priority_float = 0.5;
3359 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3360 vk_find_struct_const(pAllocateInfo->pNext,
3361 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3362 if (priority_ext)
3363 priority_float = priority_ext->priority;
3364
3365 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3366 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3367
3368 mem->user_ptr = NULL;
3369
3370 if (import_info) {
3371 assert(import_info->handleType ==
3372 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3373 import_info->handleType ==
3374 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3375 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3376 priority, NULL, NULL);
3377 if (!mem->bo) {
3378 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3379 goto fail;
3380 } else {
3381 close(import_info->fd);
3382 }
3383 } else if (host_ptr_info) {
3384 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3385 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3386 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3387 pAllocateInfo->allocationSize,
3388 priority);
3389 if (!mem->bo) {
3390 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3391 goto fail;
3392 } else {
3393 mem->user_ptr = host_ptr_info->pHostPointer;
3394 }
3395 } else {
3396 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3397 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3398 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3399 domain = RADEON_DOMAIN_GTT;
3400 else
3401 domain = RADEON_DOMAIN_VRAM;
3402
3403 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3404 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3405 else
3406 flags |= RADEON_FLAG_CPU_ACCESS;
3407
3408 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3409 flags |= RADEON_FLAG_GTT_WC;
3410
3411 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3412 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3413 if (device->use_global_bo_list) {
3414 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3415 }
3416 }
3417
3418 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3419 domain, flags, priority);
3420
3421 if (!mem->bo) {
3422 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3423 goto fail;
3424 }
3425 mem->type_index = mem_type_index;
3426 }
3427
3428 result = radv_bo_list_add(device, mem->bo);
3429 if (result != VK_SUCCESS)
3430 goto fail_bo;
3431
3432 *pMem = radv_device_memory_to_handle(mem);
3433
3434 return VK_SUCCESS;
3435
3436 fail_bo:
3437 device->ws->buffer_destroy(mem->bo);
3438 fail:
3439 vk_free2(&device->alloc, pAllocator, mem);
3440
3441 return result;
3442 }
3443
3444 VkResult radv_AllocateMemory(
3445 VkDevice _device,
3446 const VkMemoryAllocateInfo* pAllocateInfo,
3447 const VkAllocationCallbacks* pAllocator,
3448 VkDeviceMemory* pMem)
3449 {
3450 RADV_FROM_HANDLE(radv_device, device, _device);
3451 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3452 }
3453
3454 void radv_FreeMemory(
3455 VkDevice _device,
3456 VkDeviceMemory _mem,
3457 const VkAllocationCallbacks* pAllocator)
3458 {
3459 RADV_FROM_HANDLE(radv_device, device, _device);
3460 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3461
3462 if (mem == NULL)
3463 return;
3464
3465 radv_bo_list_remove(device, mem->bo);
3466 device->ws->buffer_destroy(mem->bo);
3467 mem->bo = NULL;
3468
3469 vk_free2(&device->alloc, pAllocator, mem);
3470 }
3471
3472 VkResult radv_MapMemory(
3473 VkDevice _device,
3474 VkDeviceMemory _memory,
3475 VkDeviceSize offset,
3476 VkDeviceSize size,
3477 VkMemoryMapFlags flags,
3478 void** ppData)
3479 {
3480 RADV_FROM_HANDLE(radv_device, device, _device);
3481 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3482
3483 if (mem == NULL) {
3484 *ppData = NULL;
3485 return VK_SUCCESS;
3486 }
3487
3488 if (mem->user_ptr)
3489 *ppData = mem->user_ptr;
3490 else
3491 *ppData = device->ws->buffer_map(mem->bo);
3492
3493 if (*ppData) {
3494 *ppData += offset;
3495 return VK_SUCCESS;
3496 }
3497
3498 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3499 }
3500
3501 void radv_UnmapMemory(
3502 VkDevice _device,
3503 VkDeviceMemory _memory)
3504 {
3505 RADV_FROM_HANDLE(radv_device, device, _device);
3506 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3507
3508 if (mem == NULL)
3509 return;
3510
3511 if (mem->user_ptr == NULL)
3512 device->ws->buffer_unmap(mem->bo);
3513 }
3514
3515 VkResult radv_FlushMappedMemoryRanges(
3516 VkDevice _device,
3517 uint32_t memoryRangeCount,
3518 const VkMappedMemoryRange* pMemoryRanges)
3519 {
3520 return VK_SUCCESS;
3521 }
3522
3523 VkResult radv_InvalidateMappedMemoryRanges(
3524 VkDevice _device,
3525 uint32_t memoryRangeCount,
3526 const VkMappedMemoryRange* pMemoryRanges)
3527 {
3528 return VK_SUCCESS;
3529 }
3530
3531 void radv_GetBufferMemoryRequirements(
3532 VkDevice _device,
3533 VkBuffer _buffer,
3534 VkMemoryRequirements* pMemoryRequirements)
3535 {
3536 RADV_FROM_HANDLE(radv_device, device, _device);
3537 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3538
3539 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3540
3541 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3542 pMemoryRequirements->alignment = 4096;
3543 else
3544 pMemoryRequirements->alignment = 16;
3545
3546 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3547 }
3548
3549 void radv_GetBufferMemoryRequirements2(
3550 VkDevice device,
3551 const VkBufferMemoryRequirementsInfo2 *pInfo,
3552 VkMemoryRequirements2 *pMemoryRequirements)
3553 {
3554 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3555 &pMemoryRequirements->memoryRequirements);
3556 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3557 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3558 switch (ext->sType) {
3559 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3560 VkMemoryDedicatedRequirements *req =
3561 (VkMemoryDedicatedRequirements *) ext;
3562 req->requiresDedicatedAllocation = buffer->shareable;
3563 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3564 break;
3565 }
3566 default:
3567 break;
3568 }
3569 }
3570 }
3571
3572 void radv_GetImageMemoryRequirements(
3573 VkDevice _device,
3574 VkImage _image,
3575 VkMemoryRequirements* pMemoryRequirements)
3576 {
3577 RADV_FROM_HANDLE(radv_device, device, _device);
3578 RADV_FROM_HANDLE(radv_image, image, _image);
3579
3580 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3581
3582 pMemoryRequirements->size = image->size;
3583 pMemoryRequirements->alignment = image->alignment;
3584 }
3585
3586 void radv_GetImageMemoryRequirements2(
3587 VkDevice device,
3588 const VkImageMemoryRequirementsInfo2 *pInfo,
3589 VkMemoryRequirements2 *pMemoryRequirements)
3590 {
3591 radv_GetImageMemoryRequirements(device, pInfo->image,
3592 &pMemoryRequirements->memoryRequirements);
3593
3594 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3595
3596 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3597 switch (ext->sType) {
3598 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3599 VkMemoryDedicatedRequirements *req =
3600 (VkMemoryDedicatedRequirements *) ext;
3601 req->requiresDedicatedAllocation = image->shareable;
3602 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3603 break;
3604 }
3605 default:
3606 break;
3607 }
3608 }
3609 }
3610
3611 void radv_GetImageSparseMemoryRequirements(
3612 VkDevice device,
3613 VkImage image,
3614 uint32_t* pSparseMemoryRequirementCount,
3615 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3616 {
3617 stub();
3618 }
3619
3620 void radv_GetImageSparseMemoryRequirements2(
3621 VkDevice device,
3622 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3623 uint32_t* pSparseMemoryRequirementCount,
3624 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3625 {
3626 stub();
3627 }
3628
3629 void radv_GetDeviceMemoryCommitment(
3630 VkDevice device,
3631 VkDeviceMemory memory,
3632 VkDeviceSize* pCommittedMemoryInBytes)
3633 {
3634 *pCommittedMemoryInBytes = 0;
3635 }
3636
3637 VkResult radv_BindBufferMemory2(VkDevice device,
3638 uint32_t bindInfoCount,
3639 const VkBindBufferMemoryInfo *pBindInfos)
3640 {
3641 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3642 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3643 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3644
3645 if (mem) {
3646 buffer->bo = mem->bo;
3647 buffer->offset = pBindInfos[i].memoryOffset;
3648 } else {
3649 buffer->bo = NULL;
3650 }
3651 }
3652 return VK_SUCCESS;
3653 }
3654
3655 VkResult radv_BindBufferMemory(
3656 VkDevice device,
3657 VkBuffer buffer,
3658 VkDeviceMemory memory,
3659 VkDeviceSize memoryOffset)
3660 {
3661 const VkBindBufferMemoryInfo info = {
3662 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3663 .buffer = buffer,
3664 .memory = memory,
3665 .memoryOffset = memoryOffset
3666 };
3667
3668 return radv_BindBufferMemory2(device, 1, &info);
3669 }
3670
3671 VkResult radv_BindImageMemory2(VkDevice device,
3672 uint32_t bindInfoCount,
3673 const VkBindImageMemoryInfo *pBindInfos)
3674 {
3675 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3676 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3677 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3678
3679 if (mem) {
3680 image->bo = mem->bo;
3681 image->offset = pBindInfos[i].memoryOffset;
3682 } else {
3683 image->bo = NULL;
3684 image->offset = 0;
3685 }
3686 }
3687 return VK_SUCCESS;
3688 }
3689
3690
3691 VkResult radv_BindImageMemory(
3692 VkDevice device,
3693 VkImage image,
3694 VkDeviceMemory memory,
3695 VkDeviceSize memoryOffset)
3696 {
3697 const VkBindImageMemoryInfo info = {
3698 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3699 .image = image,
3700 .memory = memory,
3701 .memoryOffset = memoryOffset
3702 };
3703
3704 return radv_BindImageMemory2(device, 1, &info);
3705 }
3706
3707
3708 static void
3709 radv_sparse_buffer_bind_memory(struct radv_device *device,
3710 const VkSparseBufferMemoryBindInfo *bind)
3711 {
3712 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3713
3714 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3715 struct radv_device_memory *mem = NULL;
3716
3717 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3718 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3719
3720 device->ws->buffer_virtual_bind(buffer->bo,
3721 bind->pBinds[i].resourceOffset,
3722 bind->pBinds[i].size,
3723 mem ? mem->bo : NULL,
3724 bind->pBinds[i].memoryOffset);
3725 }
3726 }
3727
3728 static void
3729 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3730 const VkSparseImageOpaqueMemoryBindInfo *bind)
3731 {
3732 RADV_FROM_HANDLE(radv_image, image, bind->image);
3733
3734 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3735 struct radv_device_memory *mem = NULL;
3736
3737 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3738 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3739
3740 device->ws->buffer_virtual_bind(image->bo,
3741 bind->pBinds[i].resourceOffset,
3742 bind->pBinds[i].size,
3743 mem ? mem->bo : NULL,
3744 bind->pBinds[i].memoryOffset);
3745 }
3746 }
3747
3748 VkResult radv_QueueBindSparse(
3749 VkQueue _queue,
3750 uint32_t bindInfoCount,
3751 const VkBindSparseInfo* pBindInfo,
3752 VkFence _fence)
3753 {
3754 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3755 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3756 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3757 bool fence_emitted = false;
3758 VkResult result;
3759 int ret;
3760
3761 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3762 struct radv_winsys_sem_info sem_info;
3763 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3764 radv_sparse_buffer_bind_memory(queue->device,
3765 pBindInfo[i].pBufferBinds + j);
3766 }
3767
3768 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3769 radv_sparse_image_opaque_bind_memory(queue->device,
3770 pBindInfo[i].pImageOpaqueBinds + j);
3771 }
3772
3773 VkResult result;
3774 result = radv_alloc_sem_info(queue->device->instance,
3775 &sem_info,
3776 pBindInfo[i].waitSemaphoreCount,
3777 pBindInfo[i].pWaitSemaphores,
3778 pBindInfo[i].signalSemaphoreCount,
3779 pBindInfo[i].pSignalSemaphores,
3780 _fence);
3781 if (result != VK_SUCCESS)
3782 return result;
3783
3784 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3785 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3786 &queue->device->empty_cs[queue->queue_family_index],
3787 1, NULL, NULL,
3788 &sem_info, NULL,
3789 false, base_fence);
3790 if (ret) {
3791 radv_loge("failed to submit CS %d\n", i);
3792 abort();
3793 }
3794
3795 fence_emitted = true;
3796 }
3797
3798 radv_free_sem_info(&sem_info);
3799
3800 }
3801
3802 if (fence) {
3803 if (!fence_emitted) {
3804 result = radv_signal_fence(queue, fence);
3805 if (result != VK_SUCCESS)
3806 return result;
3807 }
3808 }
3809
3810 return VK_SUCCESS;
3811 }
3812
3813 VkResult radv_CreateFence(
3814 VkDevice _device,
3815 const VkFenceCreateInfo* pCreateInfo,
3816 const VkAllocationCallbacks* pAllocator,
3817 VkFence* pFence)
3818 {
3819 RADV_FROM_HANDLE(radv_device, device, _device);
3820 const VkExportFenceCreateInfo *export =
3821 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3822 VkExternalFenceHandleTypeFlags handleTypes =
3823 export ? export->handleTypes : 0;
3824
3825 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3826 sizeof(*fence), 8,
3827 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3828
3829 if (!fence)
3830 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3831
3832 fence->fence_wsi = NULL;
3833 fence->temp_syncobj = 0;
3834 if (device->always_use_syncobj || handleTypes) {
3835 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3836 if (ret) {
3837 vk_free2(&device->alloc, pAllocator, fence);
3838 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3839 }
3840 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3841 device->ws->signal_syncobj(device->ws, fence->syncobj);
3842 }
3843 fence->fence = NULL;
3844 } else {
3845 fence->fence = device->ws->create_fence();
3846 if (!fence->fence) {
3847 vk_free2(&device->alloc, pAllocator, fence);
3848 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3849 }
3850 fence->syncobj = 0;
3851 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3852 device->ws->signal_fence(fence->fence);
3853 }
3854
3855 *pFence = radv_fence_to_handle(fence);
3856
3857 return VK_SUCCESS;
3858 }
3859
3860 void radv_DestroyFence(
3861 VkDevice _device,
3862 VkFence _fence,
3863 const VkAllocationCallbacks* pAllocator)
3864 {
3865 RADV_FROM_HANDLE(radv_device, device, _device);
3866 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3867
3868 if (!fence)
3869 return;
3870
3871 if (fence->temp_syncobj)
3872 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3873 if (fence->syncobj)
3874 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3875 if (fence->fence)
3876 device->ws->destroy_fence(fence->fence);
3877 if (fence->fence_wsi)
3878 fence->fence_wsi->destroy(fence->fence_wsi);
3879 vk_free2(&device->alloc, pAllocator, fence);
3880 }
3881
3882
3883 uint64_t radv_get_current_time(void)
3884 {
3885 struct timespec tv;
3886 clock_gettime(CLOCK_MONOTONIC, &tv);
3887 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3888 }
3889
3890 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3891 {
3892 uint64_t current_time = radv_get_current_time();
3893
3894 timeout = MIN2(UINT64_MAX - current_time, timeout);
3895
3896 return current_time + timeout;
3897 }
3898
3899
3900 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3901 uint32_t fenceCount, const VkFence *pFences)
3902 {
3903 for (uint32_t i = 0; i < fenceCount; ++i) {
3904 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3905 if (fence->fence == NULL || fence->syncobj ||
3906 fence->temp_syncobj || fence->fence_wsi ||
3907 (!device->ws->is_fence_waitable(fence->fence)))
3908 return false;
3909 }
3910 return true;
3911 }
3912
3913 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3914 {
3915 for (uint32_t i = 0; i < fenceCount; ++i) {
3916 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3917 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3918 return false;
3919 }
3920 return true;
3921 }
3922
3923 VkResult radv_WaitForFences(
3924 VkDevice _device,
3925 uint32_t fenceCount,
3926 const VkFence* pFences,
3927 VkBool32 waitAll,
3928 uint64_t timeout)
3929 {
3930 RADV_FROM_HANDLE(radv_device, device, _device);
3931 timeout = radv_get_absolute_timeout(timeout);
3932
3933 if (device->always_use_syncobj &&
3934 radv_all_fences_syncobj(fenceCount, pFences))
3935 {
3936 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3937 if (!handles)
3938 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3939
3940 for (uint32_t i = 0; i < fenceCount; ++i) {
3941 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3942 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3943 }
3944
3945 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3946
3947 free(handles);
3948 return success ? VK_SUCCESS : VK_TIMEOUT;
3949 }
3950
3951 if (!waitAll && fenceCount > 1) {
3952 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3953 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3954 uint32_t wait_count = 0;
3955 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3956 if (!fences)
3957 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3958
3959 for (uint32_t i = 0; i < fenceCount; ++i) {
3960 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3961
3962 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3963 free(fences);
3964 return VK_SUCCESS;
3965 }
3966
3967 fences[wait_count++] = fence->fence;
3968 }
3969
3970 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3971 waitAll, timeout - radv_get_current_time());
3972
3973 free(fences);
3974 return success ? VK_SUCCESS : VK_TIMEOUT;
3975 }
3976
3977 while(radv_get_current_time() <= timeout) {
3978 for (uint32_t i = 0; i < fenceCount; ++i) {
3979 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3980 return VK_SUCCESS;
3981 }
3982 }
3983 return VK_TIMEOUT;
3984 }
3985
3986 for (uint32_t i = 0; i < fenceCount; ++i) {
3987 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3988 bool expired = false;
3989
3990 if (fence->temp_syncobj) {
3991 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3992 return VK_TIMEOUT;
3993 continue;
3994 }
3995
3996 if (fence->syncobj) {
3997 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3998 return VK_TIMEOUT;
3999 continue;
4000 }
4001
4002 if (fence->fence) {
4003 if (!device->ws->is_fence_waitable(fence->fence)) {
4004 while(!device->ws->is_fence_waitable(fence->fence) &&
4005 radv_get_current_time() <= timeout)
4006 /* Do nothing */;
4007 }
4008
4009 expired = device->ws->fence_wait(device->ws,
4010 fence->fence,
4011 true, timeout);
4012 if (!expired)
4013 return VK_TIMEOUT;
4014 }
4015
4016 if (fence->fence_wsi) {
4017 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4018 if (result != VK_SUCCESS)
4019 return result;
4020 }
4021 }
4022
4023 return VK_SUCCESS;
4024 }
4025
4026 VkResult radv_ResetFences(VkDevice _device,
4027 uint32_t fenceCount,
4028 const VkFence *pFences)
4029 {
4030 RADV_FROM_HANDLE(radv_device, device, _device);
4031
4032 for (unsigned i = 0; i < fenceCount; ++i) {
4033 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4034 if (fence->fence)
4035 device->ws->reset_fence(fence->fence);
4036
4037 /* Per spec, we first restore the permanent payload, and then reset, so
4038 * having a temp syncobj should not skip resetting the permanent syncobj. */
4039 if (fence->temp_syncobj) {
4040 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4041 fence->temp_syncobj = 0;
4042 }
4043
4044 if (fence->syncobj) {
4045 device->ws->reset_syncobj(device->ws, fence->syncobj);
4046 }
4047 }
4048
4049 return VK_SUCCESS;
4050 }
4051
4052 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4053 {
4054 RADV_FROM_HANDLE(radv_device, device, _device);
4055 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4056
4057 if (fence->temp_syncobj) {
4058 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4059 return success ? VK_SUCCESS : VK_NOT_READY;
4060 }
4061
4062 if (fence->syncobj) {
4063 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4064 return success ? VK_SUCCESS : VK_NOT_READY;
4065 }
4066
4067 if (fence->fence) {
4068 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4069 return VK_NOT_READY;
4070 }
4071 if (fence->fence_wsi) {
4072 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4073
4074 if (result != VK_SUCCESS) {
4075 if (result == VK_TIMEOUT)
4076 return VK_NOT_READY;
4077 return result;
4078 }
4079 }
4080 return VK_SUCCESS;
4081 }
4082
4083
4084 // Queue semaphore functions
4085
4086 VkResult radv_CreateSemaphore(
4087 VkDevice _device,
4088 const VkSemaphoreCreateInfo* pCreateInfo,
4089 const VkAllocationCallbacks* pAllocator,
4090 VkSemaphore* pSemaphore)
4091 {
4092 RADV_FROM_HANDLE(radv_device, device, _device);
4093 const VkExportSemaphoreCreateInfo *export =
4094 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4095 VkExternalSemaphoreHandleTypeFlags handleTypes =
4096 export ? export->handleTypes : 0;
4097
4098 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4099 sizeof(*sem), 8,
4100 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4101 if (!sem)
4102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4103
4104 sem->temp_syncobj = 0;
4105 /* create a syncobject if we are going to export this semaphore */
4106 if (device->always_use_syncobj || handleTypes) {
4107 assert (device->physical_device->rad_info.has_syncobj);
4108 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4109 if (ret) {
4110 vk_free2(&device->alloc, pAllocator, sem);
4111 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4112 }
4113 sem->sem = NULL;
4114 } else {
4115 sem->sem = device->ws->create_sem(device->ws);
4116 if (!sem->sem) {
4117 vk_free2(&device->alloc, pAllocator, sem);
4118 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4119 }
4120 sem->syncobj = 0;
4121 }
4122
4123 *pSemaphore = radv_semaphore_to_handle(sem);
4124 return VK_SUCCESS;
4125 }
4126
4127 void radv_DestroySemaphore(
4128 VkDevice _device,
4129 VkSemaphore _semaphore,
4130 const VkAllocationCallbacks* pAllocator)
4131 {
4132 RADV_FROM_HANDLE(radv_device, device, _device);
4133 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4134 if (!_semaphore)
4135 return;
4136
4137 if (sem->syncobj)
4138 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4139 else
4140 device->ws->destroy_sem(sem->sem);
4141 vk_free2(&device->alloc, pAllocator, sem);
4142 }
4143
4144 VkResult radv_CreateEvent(
4145 VkDevice _device,
4146 const VkEventCreateInfo* pCreateInfo,
4147 const VkAllocationCallbacks* pAllocator,
4148 VkEvent* pEvent)
4149 {
4150 RADV_FROM_HANDLE(radv_device, device, _device);
4151 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4152 sizeof(*event), 8,
4153 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4154
4155 if (!event)
4156 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4157
4158 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4159 RADEON_DOMAIN_GTT,
4160 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4161 RADV_BO_PRIORITY_FENCE);
4162 if (!event->bo) {
4163 vk_free2(&device->alloc, pAllocator, event);
4164 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4165 }
4166
4167 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4168
4169 *pEvent = radv_event_to_handle(event);
4170
4171 return VK_SUCCESS;
4172 }
4173
4174 void radv_DestroyEvent(
4175 VkDevice _device,
4176 VkEvent _event,
4177 const VkAllocationCallbacks* pAllocator)
4178 {
4179 RADV_FROM_HANDLE(radv_device, device, _device);
4180 RADV_FROM_HANDLE(radv_event, event, _event);
4181
4182 if (!event)
4183 return;
4184 device->ws->buffer_destroy(event->bo);
4185 vk_free2(&device->alloc, pAllocator, event);
4186 }
4187
4188 VkResult radv_GetEventStatus(
4189 VkDevice _device,
4190 VkEvent _event)
4191 {
4192 RADV_FROM_HANDLE(radv_event, event, _event);
4193
4194 if (*event->map == 1)
4195 return VK_EVENT_SET;
4196 return VK_EVENT_RESET;
4197 }
4198
4199 VkResult radv_SetEvent(
4200 VkDevice _device,
4201 VkEvent _event)
4202 {
4203 RADV_FROM_HANDLE(radv_event, event, _event);
4204 *event->map = 1;
4205
4206 return VK_SUCCESS;
4207 }
4208
4209 VkResult radv_ResetEvent(
4210 VkDevice _device,
4211 VkEvent _event)
4212 {
4213 RADV_FROM_HANDLE(radv_event, event, _event);
4214 *event->map = 0;
4215
4216 return VK_SUCCESS;
4217 }
4218
4219 VkResult radv_CreateBuffer(
4220 VkDevice _device,
4221 const VkBufferCreateInfo* pCreateInfo,
4222 const VkAllocationCallbacks* pAllocator,
4223 VkBuffer* pBuffer)
4224 {
4225 RADV_FROM_HANDLE(radv_device, device, _device);
4226 struct radv_buffer *buffer;
4227
4228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4229
4230 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4231 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4232 if (buffer == NULL)
4233 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4234
4235 buffer->size = pCreateInfo->size;
4236 buffer->usage = pCreateInfo->usage;
4237 buffer->bo = NULL;
4238 buffer->offset = 0;
4239 buffer->flags = pCreateInfo->flags;
4240
4241 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4242 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4243
4244 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4245 buffer->bo = device->ws->buffer_create(device->ws,
4246 align64(buffer->size, 4096),
4247 4096, 0, RADEON_FLAG_VIRTUAL,
4248 RADV_BO_PRIORITY_VIRTUAL);
4249 if (!buffer->bo) {
4250 vk_free2(&device->alloc, pAllocator, buffer);
4251 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4252 }
4253 }
4254
4255 *pBuffer = radv_buffer_to_handle(buffer);
4256
4257 return VK_SUCCESS;
4258 }
4259
4260 void radv_DestroyBuffer(
4261 VkDevice _device,
4262 VkBuffer _buffer,
4263 const VkAllocationCallbacks* pAllocator)
4264 {
4265 RADV_FROM_HANDLE(radv_device, device, _device);
4266 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4267
4268 if (!buffer)
4269 return;
4270
4271 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4272 device->ws->buffer_destroy(buffer->bo);
4273
4274 vk_free2(&device->alloc, pAllocator, buffer);
4275 }
4276
4277 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4278 VkDevice device,
4279 const VkBufferDeviceAddressInfoEXT* pInfo)
4280 {
4281 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4282 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4283 }
4284
4285
4286 static inline unsigned
4287 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4288 {
4289 if (stencil)
4290 return plane->surface.u.legacy.stencil_tiling_index[level];
4291 else
4292 return plane->surface.u.legacy.tiling_index[level];
4293 }
4294
4295 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4296 {
4297 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4298 }
4299
4300 static uint32_t
4301 radv_init_dcc_control_reg(struct radv_device *device,
4302 struct radv_image_view *iview)
4303 {
4304 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4305 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4306 unsigned max_compressed_block_size;
4307 unsigned independent_128b_blocks;
4308 unsigned independent_64b_blocks;
4309
4310 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4311 return 0;
4312
4313 if (!device->physical_device->rad_info.has_dedicated_vram) {
4314 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4315 * dGPU and 64 for APU because all of our APUs to date use
4316 * DIMMs which have a request granularity size of 64B while all
4317 * other chips have a 32B request size.
4318 */
4319 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4320 }
4321
4322 if (device->physical_device->rad_info.chip_class >= GFX10) {
4323 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4324 independent_64b_blocks = 0;
4325 independent_128b_blocks = 1;
4326 } else {
4327 independent_128b_blocks = 0;
4328
4329 if (iview->image->info.samples > 1) {
4330 if (iview->image->planes[0].surface.bpe == 1)
4331 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4332 else if (iview->image->planes[0].surface.bpe == 2)
4333 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4334 }
4335
4336 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4337 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4338 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4339 /* If this DCC image is potentially going to be used in texture
4340 * fetches, we need some special settings.
4341 */
4342 independent_64b_blocks = 1;
4343 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4344 } else {
4345 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4346 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4347 * big as possible for better compression state.
4348 */
4349 independent_64b_blocks = 0;
4350 max_compressed_block_size = max_uncompressed_block_size;
4351 }
4352 }
4353
4354 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4355 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4356 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4357 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4358 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4359 }
4360
4361 void
4362 radv_initialise_color_surface(struct radv_device *device,
4363 struct radv_color_buffer_info *cb,
4364 struct radv_image_view *iview)
4365 {
4366 const struct vk_format_description *desc;
4367 unsigned ntype, format, swap, endian;
4368 unsigned blend_clamp = 0, blend_bypass = 0;
4369 uint64_t va;
4370 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4371 const struct radeon_surf *surf = &plane->surface;
4372
4373 desc = vk_format_description(iview->vk_format);
4374
4375 memset(cb, 0, sizeof(*cb));
4376
4377 /* Intensity is implemented as Red, so treat it that way. */
4378 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4379
4380 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4381
4382 cb->cb_color_base = va >> 8;
4383
4384 if (device->physical_device->rad_info.chip_class >= GFX9) {
4385 struct gfx9_surf_meta_flags meta;
4386 if (iview->image->dcc_offset)
4387 meta = surf->u.gfx9.dcc;
4388 else
4389 meta = surf->u.gfx9.cmask;
4390
4391 if (device->physical_device->rad_info.chip_class >= GFX10) {
4392 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4393 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4394 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4395 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4396 } else {
4397 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4398 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4399 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4400 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4401 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4402 }
4403
4404 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4405 cb->cb_color_base |= surf->tile_swizzle;
4406 } else {
4407 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4408 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4409
4410 cb->cb_color_base += level_info->offset >> 8;
4411 if (level_info->mode == RADEON_SURF_MODE_2D)
4412 cb->cb_color_base |= surf->tile_swizzle;
4413
4414 pitch_tile_max = level_info->nblk_x / 8 - 1;
4415 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4416 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4417
4418 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4419 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4420 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4421
4422 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4423
4424 if (radv_image_has_fmask(iview->image)) {
4425 if (device->physical_device->rad_info.chip_class >= GFX7)
4426 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4427 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4428 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4429 } else {
4430 /* This must be set for fast clear to work without FMASK. */
4431 if (device->physical_device->rad_info.chip_class >= GFX7)
4432 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4433 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4434 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4435 }
4436 }
4437
4438 /* CMASK variables */
4439 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4440 va += iview->image->cmask_offset;
4441 cb->cb_color_cmask = va >> 8;
4442
4443 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4444 va += iview->image->dcc_offset;
4445
4446 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4447 device->physical_device->rad_info.chip_class <= GFX8)
4448 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4449
4450 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4451 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4452
4453 cb->cb_dcc_base = va >> 8;
4454 cb->cb_dcc_base |= dcc_tile_swizzle;
4455
4456 /* GFX10 field has the same base shift as the GFX6 field. */
4457 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4458 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4459 S_028C6C_SLICE_MAX_GFX10(max_slice);
4460
4461 if (iview->image->info.samples > 1) {
4462 unsigned log_samples = util_logbase2(iview->image->info.samples);
4463
4464 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4465 S_028C74_NUM_FRAGMENTS(log_samples);
4466 }
4467
4468 if (radv_image_has_fmask(iview->image)) {
4469 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4470 cb->cb_color_fmask = va >> 8;
4471 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4472 } else {
4473 cb->cb_color_fmask = cb->cb_color_base;
4474 }
4475
4476 ntype = radv_translate_color_numformat(iview->vk_format,
4477 desc,
4478 vk_format_get_first_non_void_channel(iview->vk_format));
4479 format = radv_translate_colorformat(iview->vk_format);
4480 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4481 radv_finishme("Illegal color\n");
4482 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4483 endian = radv_colorformat_endian_swap(format);
4484
4485 /* blend clamp should be set for all NORM/SRGB types */
4486 if (ntype == V_028C70_NUMBER_UNORM ||
4487 ntype == V_028C70_NUMBER_SNORM ||
4488 ntype == V_028C70_NUMBER_SRGB)
4489 blend_clamp = 1;
4490
4491 /* set blend bypass according to docs if SINT/UINT or
4492 8/24 COLOR variants */
4493 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4494 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4495 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4496 blend_clamp = 0;
4497 blend_bypass = 1;
4498 }
4499 #if 0
4500 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4501 (format == V_028C70_COLOR_8 ||
4502 format == V_028C70_COLOR_8_8 ||
4503 format == V_028C70_COLOR_8_8_8_8))
4504 ->color_is_int8 = true;
4505 #endif
4506 cb->cb_color_info = S_028C70_FORMAT(format) |
4507 S_028C70_COMP_SWAP(swap) |
4508 S_028C70_BLEND_CLAMP(blend_clamp) |
4509 S_028C70_BLEND_BYPASS(blend_bypass) |
4510 S_028C70_SIMPLE_FLOAT(1) |
4511 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4512 ntype != V_028C70_NUMBER_SNORM &&
4513 ntype != V_028C70_NUMBER_SRGB &&
4514 format != V_028C70_COLOR_8_24 &&
4515 format != V_028C70_COLOR_24_8) |
4516 S_028C70_NUMBER_TYPE(ntype) |
4517 S_028C70_ENDIAN(endian);
4518 if (radv_image_has_fmask(iview->image)) {
4519 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4520 if (device->physical_device->rad_info.chip_class == GFX6) {
4521 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4522 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4523 }
4524
4525 if (radv_image_is_tc_compat_cmask(iview->image)) {
4526 /* Allow the texture block to read FMASK directly
4527 * without decompressing it. This bit must be cleared
4528 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4529 * otherwise the operation doesn't happen.
4530 */
4531 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4532
4533 /* Set CMASK into a tiling format that allows the
4534 * texture block to read it.
4535 */
4536 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4537 }
4538 }
4539
4540 if (radv_image_has_cmask(iview->image) &&
4541 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4542 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4543
4544 if (radv_dcc_enabled(iview->image, iview->base_mip))
4545 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4546
4547 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4548
4549 /* This must be set for fast clear to work without FMASK. */
4550 if (!radv_image_has_fmask(iview->image) &&
4551 device->physical_device->rad_info.chip_class == GFX6) {
4552 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4553 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4554 }
4555
4556 if (device->physical_device->rad_info.chip_class >= GFX9) {
4557 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4558
4559 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4560 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4561 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4562 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4563
4564 if (device->physical_device->rad_info.chip_class >= GFX10) {
4565 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4566
4567 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4568 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4569 S_028EE0_RESOURCE_LEVEL(1);
4570 } else {
4571 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4572 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4573 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4574 }
4575
4576 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4577 S_028C68_MIP0_HEIGHT(height - 1) |
4578 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4579 }
4580 }
4581
4582 static unsigned
4583 radv_calc_decompress_on_z_planes(struct radv_device *device,
4584 struct radv_image_view *iview)
4585 {
4586 unsigned max_zplanes = 0;
4587
4588 assert(radv_image_is_tc_compat_htile(iview->image));
4589
4590 if (device->physical_device->rad_info.chip_class >= GFX9) {
4591 /* Default value for 32-bit depth surfaces. */
4592 max_zplanes = 4;
4593
4594 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4595 iview->image->info.samples > 1)
4596 max_zplanes = 2;
4597
4598 max_zplanes = max_zplanes + 1;
4599 } else {
4600 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4601 /* Do not enable Z plane compression for 16-bit depth
4602 * surfaces because isn't supported on GFX8. Only
4603 * 32-bit depth surfaces are supported by the hardware.
4604 * This allows to maintain shader compatibility and to
4605 * reduce the number of depth decompressions.
4606 */
4607 max_zplanes = 1;
4608 } else {
4609 if (iview->image->info.samples <= 1)
4610 max_zplanes = 5;
4611 else if (iview->image->info.samples <= 4)
4612 max_zplanes = 3;
4613 else
4614 max_zplanes = 2;
4615 }
4616 }
4617
4618 return max_zplanes;
4619 }
4620
4621 void
4622 radv_initialise_ds_surface(struct radv_device *device,
4623 struct radv_ds_buffer_info *ds,
4624 struct radv_image_view *iview)
4625 {
4626 unsigned level = iview->base_mip;
4627 unsigned format, stencil_format;
4628 uint64_t va, s_offs, z_offs;
4629 bool stencil_only = false;
4630 const struct radv_image_plane *plane = &iview->image->planes[0];
4631 const struct radeon_surf *surf = &plane->surface;
4632
4633 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4634
4635 memset(ds, 0, sizeof(*ds));
4636 switch (iview->image->vk_format) {
4637 case VK_FORMAT_D24_UNORM_S8_UINT:
4638 case VK_FORMAT_X8_D24_UNORM_PACK32:
4639 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4640 ds->offset_scale = 2.0f;
4641 break;
4642 case VK_FORMAT_D16_UNORM:
4643 case VK_FORMAT_D16_UNORM_S8_UINT:
4644 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4645 ds->offset_scale = 4.0f;
4646 break;
4647 case VK_FORMAT_D32_SFLOAT:
4648 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4649 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4650 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4651 ds->offset_scale = 1.0f;
4652 break;
4653 case VK_FORMAT_S8_UINT:
4654 stencil_only = true;
4655 break;
4656 default:
4657 break;
4658 }
4659
4660 format = radv_translate_dbformat(iview->image->vk_format);
4661 stencil_format = surf->has_stencil ?
4662 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4663
4664 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4665 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4666 S_028008_SLICE_MAX(max_slice);
4667 if (device->physical_device->rad_info.chip_class >= GFX10) {
4668 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4669 S_028008_SLICE_MAX_HI(max_slice >> 11);
4670 }
4671
4672 ds->db_htile_data_base = 0;
4673 ds->db_htile_surface = 0;
4674
4675 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4676 s_offs = z_offs = va;
4677
4678 if (device->physical_device->rad_info.chip_class >= GFX9) {
4679 assert(surf->u.gfx9.surf_offset == 0);
4680 s_offs += surf->u.gfx9.stencil_offset;
4681
4682 ds->db_z_info = S_028038_FORMAT(format) |
4683 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4684 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4685 S_028038_MAXMIP(iview->image->info.levels - 1) |
4686 S_028038_ZRANGE_PRECISION(1);
4687 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4688 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4689
4690 if (device->physical_device->rad_info.chip_class == GFX9) {
4691 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4692 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4693 }
4694
4695 ds->db_depth_view |= S_028008_MIPID(level);
4696 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4697 S_02801C_Y_MAX(iview->image->info.height - 1);
4698
4699 if (radv_htile_enabled(iview->image, level)) {
4700 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4701
4702 if (radv_image_is_tc_compat_htile(iview->image)) {
4703 unsigned max_zplanes =
4704 radv_calc_decompress_on_z_planes(device, iview);
4705
4706 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4707
4708 if (device->physical_device->rad_info.chip_class >= GFX10) {
4709 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4710 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4711 } else {
4712 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4713 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4714 }
4715 }
4716
4717 if (!surf->has_stencil)
4718 /* Use all of the htile_buffer for depth if there's no stencil. */
4719 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4720 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4721 iview->image->htile_offset;
4722 ds->db_htile_data_base = va >> 8;
4723 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4724 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4725
4726 if (device->physical_device->rad_info.chip_class == GFX9) {
4727 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4728 }
4729 }
4730 } else {
4731 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4732
4733 if (stencil_only)
4734 level_info = &surf->u.legacy.stencil_level[level];
4735
4736 z_offs += surf->u.legacy.level[level].offset;
4737 s_offs += surf->u.legacy.stencil_level[level].offset;
4738
4739 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4740 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4741 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4742
4743 if (iview->image->info.samples > 1)
4744 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4745
4746 if (device->physical_device->rad_info.chip_class >= GFX7) {
4747 struct radeon_info *info = &device->physical_device->rad_info;
4748 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4749 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4750 unsigned macro_index = surf->u.legacy.macro_tile_index;
4751 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4752 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4753 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4754
4755 if (stencil_only)
4756 tile_mode = stencil_tile_mode;
4757
4758 ds->db_depth_info |=
4759 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4760 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4761 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4762 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4763 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4764 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4765 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4766 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4767 } else {
4768 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4769 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4770 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4771 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4772 if (stencil_only)
4773 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4774 }
4775
4776 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4777 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4778 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4779
4780 if (radv_htile_enabled(iview->image, level)) {
4781 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4782
4783 if (!surf->has_stencil &&
4784 !radv_image_is_tc_compat_htile(iview->image))
4785 /* Use all of the htile_buffer for depth if there's no stencil. */
4786 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4787
4788 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4789 iview->image->htile_offset;
4790 ds->db_htile_data_base = va >> 8;
4791 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4792
4793 if (radv_image_is_tc_compat_htile(iview->image)) {
4794 unsigned max_zplanes =
4795 radv_calc_decompress_on_z_planes(device, iview);
4796
4797 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4798 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4799 }
4800 }
4801 }
4802
4803 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4804 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4805 }
4806
4807 VkResult radv_CreateFramebuffer(
4808 VkDevice _device,
4809 const VkFramebufferCreateInfo* pCreateInfo,
4810 const VkAllocationCallbacks* pAllocator,
4811 VkFramebuffer* pFramebuffer)
4812 {
4813 RADV_FROM_HANDLE(radv_device, device, _device);
4814 struct radv_framebuffer *framebuffer;
4815 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4816 vk_find_struct_const(pCreateInfo->pNext,
4817 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4818
4819 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4820
4821 size_t size = sizeof(*framebuffer);
4822 if (!imageless_create_info)
4823 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4824 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4825 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4826 if (framebuffer == NULL)
4827 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4828
4829 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4830 framebuffer->width = pCreateInfo->width;
4831 framebuffer->height = pCreateInfo->height;
4832 framebuffer->layers = pCreateInfo->layers;
4833 if (imageless_create_info) {
4834 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4835 const VkFramebufferAttachmentImageInfoKHR *attachment =
4836 imageless_create_info->pAttachmentImageInfos + i;
4837 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4838 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4839 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4840 }
4841 } else {
4842 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4843 VkImageView _iview = pCreateInfo->pAttachments[i];
4844 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4845 framebuffer->attachments[i] = iview;
4846 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4847 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4848 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4849 }
4850 }
4851
4852 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4853 return VK_SUCCESS;
4854 }
4855
4856 void radv_DestroyFramebuffer(
4857 VkDevice _device,
4858 VkFramebuffer _fb,
4859 const VkAllocationCallbacks* pAllocator)
4860 {
4861 RADV_FROM_HANDLE(radv_device, device, _device);
4862 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4863
4864 if (!fb)
4865 return;
4866 vk_free2(&device->alloc, pAllocator, fb);
4867 }
4868
4869 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4870 {
4871 switch (address_mode) {
4872 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4873 return V_008F30_SQ_TEX_WRAP;
4874 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4875 return V_008F30_SQ_TEX_MIRROR;
4876 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4877 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4878 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4879 return V_008F30_SQ_TEX_CLAMP_BORDER;
4880 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4881 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4882 default:
4883 unreachable("illegal tex wrap mode");
4884 break;
4885 }
4886 }
4887
4888 static unsigned
4889 radv_tex_compare(VkCompareOp op)
4890 {
4891 switch (op) {
4892 case VK_COMPARE_OP_NEVER:
4893 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4894 case VK_COMPARE_OP_LESS:
4895 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4896 case VK_COMPARE_OP_EQUAL:
4897 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4898 case VK_COMPARE_OP_LESS_OR_EQUAL:
4899 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4900 case VK_COMPARE_OP_GREATER:
4901 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4902 case VK_COMPARE_OP_NOT_EQUAL:
4903 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4904 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4905 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4906 case VK_COMPARE_OP_ALWAYS:
4907 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4908 default:
4909 unreachable("illegal compare mode");
4910 break;
4911 }
4912 }
4913
4914 static unsigned
4915 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4916 {
4917 switch (filter) {
4918 case VK_FILTER_NEAREST:
4919 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4920 V_008F38_SQ_TEX_XY_FILTER_POINT);
4921 case VK_FILTER_LINEAR:
4922 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4923 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4924 case VK_FILTER_CUBIC_IMG:
4925 default:
4926 fprintf(stderr, "illegal texture filter");
4927 return 0;
4928 }
4929 }
4930
4931 static unsigned
4932 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4933 {
4934 switch (mode) {
4935 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4936 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4937 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4938 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4939 default:
4940 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4941 }
4942 }
4943
4944 static unsigned
4945 radv_tex_bordercolor(VkBorderColor bcolor)
4946 {
4947 switch (bcolor) {
4948 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4949 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4950 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4951 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4952 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4953 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4954 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4955 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4956 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4957 default:
4958 break;
4959 }
4960 return 0;
4961 }
4962
4963 static unsigned
4964 radv_tex_aniso_filter(unsigned filter)
4965 {
4966 if (filter < 2)
4967 return 0;
4968 if (filter < 4)
4969 return 1;
4970 if (filter < 8)
4971 return 2;
4972 if (filter < 16)
4973 return 3;
4974 return 4;
4975 }
4976
4977 static unsigned
4978 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4979 {
4980 switch (mode) {
4981 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4982 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4983 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4984 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4985 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4986 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4987 default:
4988 break;
4989 }
4990 return 0;
4991 }
4992
4993 static uint32_t
4994 radv_get_max_anisotropy(struct radv_device *device,
4995 const VkSamplerCreateInfo *pCreateInfo)
4996 {
4997 if (device->force_aniso >= 0)
4998 return device->force_aniso;
4999
5000 if (pCreateInfo->anisotropyEnable &&
5001 pCreateInfo->maxAnisotropy > 1.0f)
5002 return (uint32_t)pCreateInfo->maxAnisotropy;
5003
5004 return 0;
5005 }
5006
5007 static void
5008 radv_init_sampler(struct radv_device *device,
5009 struct radv_sampler *sampler,
5010 const VkSamplerCreateInfo *pCreateInfo)
5011 {
5012 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5013 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5014 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5015 device->physical_device->rad_info.chip_class == GFX9;
5016 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5017
5018 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5019 vk_find_struct_const(pCreateInfo->pNext,
5020 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5021 if (sampler_reduction)
5022 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5023
5024 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5025 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5026 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5027 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5028 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5029 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5030 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5031 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5032 S_008F30_DISABLE_CUBE_WRAP(0) |
5033 S_008F30_COMPAT_MODE(compat_mode) |
5034 S_008F30_FILTER_MODE(filter_mode));
5035 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5036 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5037 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5038 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5039 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5040 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5041 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5042 S_008F38_MIP_POINT_PRECLAMP(0));
5043 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5044 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5045
5046 if (device->physical_device->rad_info.chip_class >= GFX10) {
5047 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5048 } else {
5049 sampler->state[2] |=
5050 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5051 S_008F38_FILTER_PREC_FIX(1) |
5052 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5053 }
5054 }
5055
5056 VkResult radv_CreateSampler(
5057 VkDevice _device,
5058 const VkSamplerCreateInfo* pCreateInfo,
5059 const VkAllocationCallbacks* pAllocator,
5060 VkSampler* pSampler)
5061 {
5062 RADV_FROM_HANDLE(radv_device, device, _device);
5063 struct radv_sampler *sampler;
5064
5065 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5066 vk_find_struct_const(pCreateInfo->pNext,
5067 SAMPLER_YCBCR_CONVERSION_INFO);
5068
5069 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5070
5071 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5072 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5073 if (!sampler)
5074 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5075
5076 radv_init_sampler(device, sampler, pCreateInfo);
5077
5078 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5079 *pSampler = radv_sampler_to_handle(sampler);
5080
5081 return VK_SUCCESS;
5082 }
5083
5084 void radv_DestroySampler(
5085 VkDevice _device,
5086 VkSampler _sampler,
5087 const VkAllocationCallbacks* pAllocator)
5088 {
5089 RADV_FROM_HANDLE(radv_device, device, _device);
5090 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5091
5092 if (!sampler)
5093 return;
5094 vk_free2(&device->alloc, pAllocator, sampler);
5095 }
5096
5097 /* vk_icd.h does not declare this function, so we declare it here to
5098 * suppress Wmissing-prototypes.
5099 */
5100 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5101 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5102
5103 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5104 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5105 {
5106 /* For the full details on loader interface versioning, see
5107 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5108 * What follows is a condensed summary, to help you navigate the large and
5109 * confusing official doc.
5110 *
5111 * - Loader interface v0 is incompatible with later versions. We don't
5112 * support it.
5113 *
5114 * - In loader interface v1:
5115 * - The first ICD entrypoint called by the loader is
5116 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5117 * entrypoint.
5118 * - The ICD must statically expose no other Vulkan symbol unless it is
5119 * linked with -Bsymbolic.
5120 * - Each dispatchable Vulkan handle created by the ICD must be
5121 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5122 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5123 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5124 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5125 * such loader-managed surfaces.
5126 *
5127 * - Loader interface v2 differs from v1 in:
5128 * - The first ICD entrypoint called by the loader is
5129 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5130 * statically expose this entrypoint.
5131 *
5132 * - Loader interface v3 differs from v2 in:
5133 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5134 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5135 * because the loader no longer does so.
5136 */
5137 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5138 return VK_SUCCESS;
5139 }
5140
5141 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5142 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5143 int *pFD)
5144 {
5145 RADV_FROM_HANDLE(radv_device, device, _device);
5146 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5147
5148 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5149
5150 /* At the moment, we support only the below handle types. */
5151 assert(pGetFdInfo->handleType ==
5152 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5153 pGetFdInfo->handleType ==
5154 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5155
5156 bool ret = radv_get_memory_fd(device, memory, pFD);
5157 if (ret == false)
5158 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5159 return VK_SUCCESS;
5160 }
5161
5162 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5163 VkExternalMemoryHandleTypeFlagBits handleType,
5164 int fd,
5165 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5166 {
5167 RADV_FROM_HANDLE(radv_device, device, _device);
5168
5169 switch (handleType) {
5170 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5171 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5172 return VK_SUCCESS;
5173
5174 default:
5175 /* The valid usage section for this function says:
5176 *
5177 * "handleType must not be one of the handle types defined as
5178 * opaque."
5179 *
5180 * So opaque handle types fall into the default "unsupported" case.
5181 */
5182 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5183 }
5184 }
5185
5186 static VkResult radv_import_opaque_fd(struct radv_device *device,
5187 int fd,
5188 uint32_t *syncobj)
5189 {
5190 uint32_t syncobj_handle = 0;
5191 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5192 if (ret != 0)
5193 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5194
5195 if (*syncobj)
5196 device->ws->destroy_syncobj(device->ws, *syncobj);
5197
5198 *syncobj = syncobj_handle;
5199 close(fd);
5200
5201 return VK_SUCCESS;
5202 }
5203
5204 static VkResult radv_import_sync_fd(struct radv_device *device,
5205 int fd,
5206 uint32_t *syncobj)
5207 {
5208 /* If we create a syncobj we do it locally so that if we have an error, we don't
5209 * leave a syncobj in an undetermined state in the fence. */
5210 uint32_t syncobj_handle = *syncobj;
5211 if (!syncobj_handle) {
5212 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5213 if (ret) {
5214 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5215 }
5216 }
5217
5218 if (fd == -1) {
5219 device->ws->signal_syncobj(device->ws, syncobj_handle);
5220 } else {
5221 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5222 if (ret != 0)
5223 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5224 }
5225
5226 *syncobj = syncobj_handle;
5227 if (fd != -1)
5228 close(fd);
5229
5230 return VK_SUCCESS;
5231 }
5232
5233 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5234 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5235 {
5236 RADV_FROM_HANDLE(radv_device, device, _device);
5237 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5238 uint32_t *syncobj_dst = NULL;
5239
5240 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5241 syncobj_dst = &sem->temp_syncobj;
5242 } else {
5243 syncobj_dst = &sem->syncobj;
5244 }
5245
5246 switch(pImportSemaphoreFdInfo->handleType) {
5247 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5248 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5249 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5250 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5251 default:
5252 unreachable("Unhandled semaphore handle type");
5253 }
5254 }
5255
5256 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5257 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5258 int *pFd)
5259 {
5260 RADV_FROM_HANDLE(radv_device, device, _device);
5261 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5262 int ret;
5263 uint32_t syncobj_handle;
5264
5265 if (sem->temp_syncobj)
5266 syncobj_handle = sem->temp_syncobj;
5267 else
5268 syncobj_handle = sem->syncobj;
5269
5270 switch(pGetFdInfo->handleType) {
5271 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5272 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5273 break;
5274 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5275 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5276 if (!ret) {
5277 if (sem->temp_syncobj) {
5278 close (sem->temp_syncobj);
5279 sem->temp_syncobj = 0;
5280 } else {
5281 device->ws->reset_syncobj(device->ws, syncobj_handle);
5282 }
5283 }
5284 break;
5285 default:
5286 unreachable("Unhandled semaphore handle type");
5287 }
5288
5289 if (ret)
5290 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5291 return VK_SUCCESS;
5292 }
5293
5294 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5295 VkPhysicalDevice physicalDevice,
5296 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5297 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5298 {
5299 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5300
5301 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5302 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5303 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5304 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5305 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5306 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5307 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5308 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5309 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5310 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5311 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5312 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5313 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5314 } else {
5315 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5316 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5317 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5318 }
5319 }
5320
5321 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5322 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5323 {
5324 RADV_FROM_HANDLE(radv_device, device, _device);
5325 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5326 uint32_t *syncobj_dst = NULL;
5327
5328
5329 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5330 syncobj_dst = &fence->temp_syncobj;
5331 } else {
5332 syncobj_dst = &fence->syncobj;
5333 }
5334
5335 switch(pImportFenceFdInfo->handleType) {
5336 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5337 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5338 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5339 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5340 default:
5341 unreachable("Unhandled fence handle type");
5342 }
5343 }
5344
5345 VkResult radv_GetFenceFdKHR(VkDevice _device,
5346 const VkFenceGetFdInfoKHR *pGetFdInfo,
5347 int *pFd)
5348 {
5349 RADV_FROM_HANDLE(radv_device, device, _device);
5350 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5351 int ret;
5352 uint32_t syncobj_handle;
5353
5354 if (fence->temp_syncobj)
5355 syncobj_handle = fence->temp_syncobj;
5356 else
5357 syncobj_handle = fence->syncobj;
5358
5359 switch(pGetFdInfo->handleType) {
5360 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5361 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5362 break;
5363 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5364 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5365 if (!ret) {
5366 if (fence->temp_syncobj) {
5367 close (fence->temp_syncobj);
5368 fence->temp_syncobj = 0;
5369 } else {
5370 device->ws->reset_syncobj(device->ws, syncobj_handle);
5371 }
5372 }
5373 break;
5374 default:
5375 unreachable("Unhandled fence handle type");
5376 }
5377
5378 if (ret)
5379 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5380 return VK_SUCCESS;
5381 }
5382
5383 void radv_GetPhysicalDeviceExternalFenceProperties(
5384 VkPhysicalDevice physicalDevice,
5385 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5386 VkExternalFenceProperties *pExternalFenceProperties)
5387 {
5388 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5389
5390 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5391 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5392 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5393 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5394 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5395 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5396 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5397 } else {
5398 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5399 pExternalFenceProperties->compatibleHandleTypes = 0;
5400 pExternalFenceProperties->externalFenceFeatures = 0;
5401 }
5402 }
5403
5404 VkResult
5405 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5406 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5407 const VkAllocationCallbacks* pAllocator,
5408 VkDebugReportCallbackEXT* pCallback)
5409 {
5410 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5411 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5412 pCreateInfo, pAllocator, &instance->alloc,
5413 pCallback);
5414 }
5415
5416 void
5417 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5418 VkDebugReportCallbackEXT _callback,
5419 const VkAllocationCallbacks* pAllocator)
5420 {
5421 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5422 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5423 _callback, pAllocator, &instance->alloc);
5424 }
5425
5426 void
5427 radv_DebugReportMessageEXT(VkInstance _instance,
5428 VkDebugReportFlagsEXT flags,
5429 VkDebugReportObjectTypeEXT objectType,
5430 uint64_t object,
5431 size_t location,
5432 int32_t messageCode,
5433 const char* pLayerPrefix,
5434 const char* pMessage)
5435 {
5436 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5437 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5438 object, location, messageCode, pLayerPrefix, pMessage);
5439 }
5440
5441 void
5442 radv_GetDeviceGroupPeerMemoryFeatures(
5443 VkDevice device,
5444 uint32_t heapIndex,
5445 uint32_t localDeviceIndex,
5446 uint32_t remoteDeviceIndex,
5447 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5448 {
5449 assert(localDeviceIndex == remoteDeviceIndex);
5450
5451 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5452 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5453 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5454 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5455 }
5456
5457 static const VkTimeDomainEXT radv_time_domains[] = {
5458 VK_TIME_DOMAIN_DEVICE_EXT,
5459 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5460 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5461 };
5462
5463 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5464 VkPhysicalDevice physicalDevice,
5465 uint32_t *pTimeDomainCount,
5466 VkTimeDomainEXT *pTimeDomains)
5467 {
5468 int d;
5469 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5470
5471 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5472 vk_outarray_append(&out, i) {
5473 *i = radv_time_domains[d];
5474 }
5475 }
5476
5477 return vk_outarray_status(&out);
5478 }
5479
5480 static uint64_t
5481 radv_clock_gettime(clockid_t clock_id)
5482 {
5483 struct timespec current;
5484 int ret;
5485
5486 ret = clock_gettime(clock_id, &current);
5487 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5488 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5489 if (ret < 0)
5490 return 0;
5491
5492 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5493 }
5494
5495 VkResult radv_GetCalibratedTimestampsEXT(
5496 VkDevice _device,
5497 uint32_t timestampCount,
5498 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5499 uint64_t *pTimestamps,
5500 uint64_t *pMaxDeviation)
5501 {
5502 RADV_FROM_HANDLE(radv_device, device, _device);
5503 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5504 int d;
5505 uint64_t begin, end;
5506 uint64_t max_clock_period = 0;
5507
5508 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5509
5510 for (d = 0; d < timestampCount; d++) {
5511 switch (pTimestampInfos[d].timeDomain) {
5512 case VK_TIME_DOMAIN_DEVICE_EXT:
5513 pTimestamps[d] = device->ws->query_value(device->ws,
5514 RADEON_TIMESTAMP);
5515 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5516 max_clock_period = MAX2(max_clock_period, device_period);
5517 break;
5518 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5519 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5520 max_clock_period = MAX2(max_clock_period, 1);
5521 break;
5522
5523 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5524 pTimestamps[d] = begin;
5525 break;
5526 default:
5527 pTimestamps[d] = 0;
5528 break;
5529 }
5530 }
5531
5532 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5533
5534 /*
5535 * The maximum deviation is the sum of the interval over which we
5536 * perform the sampling and the maximum period of any sampled
5537 * clock. That's because the maximum skew between any two sampled
5538 * clock edges is when the sampled clock with the largest period is
5539 * sampled at the end of that period but right at the beginning of the
5540 * sampling interval and some other clock is sampled right at the
5541 * begining of its sampling period and right at the end of the
5542 * sampling interval. Let's assume the GPU has the longest clock
5543 * period and that the application is sampling GPU and monotonic:
5544 *
5545 * s e
5546 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5547 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5548 *
5549 * g
5550 * 0 1 2 3
5551 * GPU -----_____-----_____-----_____-----_____
5552 *
5553 * m
5554 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5555 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5556 *
5557 * Interval <----------------->
5558 * Deviation <-------------------------->
5559 *
5560 * s = read(raw) 2
5561 * g = read(GPU) 1
5562 * m = read(monotonic) 2
5563 * e = read(raw) b
5564 *
5565 * We round the sample interval up by one tick to cover sampling error
5566 * in the interval clock
5567 */
5568
5569 uint64_t sample_interval = end - begin + 1;
5570
5571 *pMaxDeviation = sample_interval + max_clock_period;
5572
5573 return VK_SUCCESS;
5574 }
5575
5576 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5577 VkPhysicalDevice physicalDevice,
5578 VkSampleCountFlagBits samples,
5579 VkMultisamplePropertiesEXT* pMultisampleProperties)
5580 {
5581 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5582 VK_SAMPLE_COUNT_4_BIT |
5583 VK_SAMPLE_COUNT_8_BIT)) {
5584 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5585 } else {
5586 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5587 }
5588 }