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radv: Add VK_KHR_storage_buffer_storage_class support.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 {
102 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 };
106
107 static const VkExtensionProperties common_device_extensions[] = {
108 {
109 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
110 .specVersion = 1,
111 },
112 {
113 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
130 .specVersion = 68,
131 },
132 {
133 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
134 .specVersion = 1,
135 },
136 {
137 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 };
161
162 static VkResult
163 radv_extensions_register(struct radv_instance *instance,
164 struct radv_extensions *extensions,
165 const VkExtensionProperties *new_ext,
166 uint32_t num_ext)
167 {
168 size_t new_size;
169 VkExtensionProperties *new_ptr;
170
171 assert(new_ext && num_ext > 0);
172
173 if (!new_ext)
174 return VK_ERROR_INITIALIZATION_FAILED;
175
176 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
177 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
178 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
179
180 /* Old array continues to be valid, update nothing */
181 if (!new_ptr)
182 return VK_ERROR_OUT_OF_HOST_MEMORY;
183
184 memcpy(&new_ptr[extensions->num_ext], new_ext,
185 num_ext * sizeof(VkExtensionProperties));
186 extensions->ext_array = new_ptr;
187 extensions->num_ext += num_ext;
188
189 return VK_SUCCESS;
190 }
191
192 static void
193 radv_extensions_finish(struct radv_instance *instance,
194 struct radv_extensions *extensions)
195 {
196 assert(extensions);
197
198 if (!extensions)
199 radv_loge("Attemted to free invalid extension struct\n");
200
201 if (extensions->ext_array)
202 vk_free(&instance->alloc, extensions->ext_array);
203 }
204
205 static bool
206 is_extension_enabled(const VkExtensionProperties *extensions,
207 size_t num_ext,
208 const char *name)
209 {
210 assert(extensions && name);
211
212 for (uint32_t i = 0; i < num_ext; i++) {
213 if (strcmp(name, extensions[i].extensionName) == 0)
214 return true;
215 }
216
217 return false;
218 }
219
220 static const char *
221 get_chip_name(enum radeon_family family)
222 {
223 switch (family) {
224 case CHIP_TAHITI: return "AMD RADV TAHITI";
225 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
226 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
227 case CHIP_OLAND: return "AMD RADV OLAND";
228 case CHIP_HAINAN: return "AMD RADV HAINAN";
229 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
230 case CHIP_KAVERI: return "AMD RADV KAVERI";
231 case CHIP_KABINI: return "AMD RADV KABINI";
232 case CHIP_HAWAII: return "AMD RADV HAWAII";
233 case CHIP_MULLINS: return "AMD RADV MULLINS";
234 case CHIP_TONGA: return "AMD RADV TONGA";
235 case CHIP_ICELAND: return "AMD RADV ICELAND";
236 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
237 case CHIP_FIJI: return "AMD RADV FIJI";
238 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
239 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
240 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
241 case CHIP_STONEY: return "AMD RADV STONEY";
242 case CHIP_VEGA10: return "AMD RADV VEGA";
243 case CHIP_RAVEN: return "AMD RADV RAVEN";
244 default: return "AMD RADV unknown";
245 }
246 }
247
248 static VkResult
249 radv_physical_device_init(struct radv_physical_device *device,
250 struct radv_instance *instance,
251 drmDevicePtr drm_device)
252 {
253 const char *path = drm_device->nodes[DRM_NODE_RENDER];
254 VkResult result;
255 drmVersionPtr version;
256 int fd;
257
258 fd = open(path, O_RDWR | O_CLOEXEC);
259 if (fd < 0)
260 return VK_ERROR_INCOMPATIBLE_DRIVER;
261
262 version = drmGetVersion(fd);
263 if (!version) {
264 close(fd);
265 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
266 "failed to get version %s: %m", path);
267 }
268
269 if (strcmp(version->name, "amdgpu")) {
270 drmFreeVersion(version);
271 close(fd);
272 return VK_ERROR_INCOMPATIBLE_DRIVER;
273 }
274 drmFreeVersion(version);
275
276 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
277 device->instance = instance;
278 assert(strlen(path) < ARRAY_SIZE(device->path));
279 strncpy(device->path, path, ARRAY_SIZE(device->path));
280
281 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
282 instance->perftest_flags);
283 if (!device->ws) {
284 result = VK_ERROR_INCOMPATIBLE_DRIVER;
285 goto fail;
286 }
287
288 device->local_fd = fd;
289 device->ws->query_info(device->ws, &device->rad_info);
290 result = radv_init_wsi(device);
291 if (result != VK_SUCCESS) {
292 device->ws->destroy(device->ws);
293 goto fail;
294 }
295
296 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
297 radv_finish_wsi(device);
298 device->ws->destroy(device->ws);
299 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
300 "cannot generate UUID");
301 goto fail;
302 }
303
304 result = radv_extensions_register(instance,
305 &device->extensions,
306 common_device_extensions,
307 ARRAY_SIZE(common_device_extensions));
308 if (result != VK_SUCCESS)
309 goto fail;
310
311 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
312 device->name = get_chip_name(device->rad_info.family);
313
314 radv_get_device_uuid(drm_device, device->device_uuid);
315
316 if (device->rad_info.family == CHIP_STONEY ||
317 device->rad_info.chip_class >= GFX9) {
318 device->has_rbplus = true;
319 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
320 }
321
322 return VK_SUCCESS;
323
324 fail:
325 close(fd);
326 return result;
327 }
328
329 static void
330 radv_physical_device_finish(struct radv_physical_device *device)
331 {
332 radv_extensions_finish(device->instance, &device->extensions);
333 radv_finish_wsi(device);
334 device->ws->destroy(device->ws);
335 close(device->local_fd);
336 }
337
338 static void *
339 default_alloc_func(void *pUserData, size_t size, size_t align,
340 VkSystemAllocationScope allocationScope)
341 {
342 return malloc(size);
343 }
344
345 static void *
346 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
347 size_t align, VkSystemAllocationScope allocationScope)
348 {
349 return realloc(pOriginal, size);
350 }
351
352 static void
353 default_free_func(void *pUserData, void *pMemory)
354 {
355 free(pMemory);
356 }
357
358 static const VkAllocationCallbacks default_alloc = {
359 .pUserData = NULL,
360 .pfnAllocation = default_alloc_func,
361 .pfnReallocation = default_realloc_func,
362 .pfnFree = default_free_func,
363 };
364
365 static const struct debug_control radv_debug_options[] = {
366 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
367 {"nodcc", RADV_DEBUG_NO_DCC},
368 {"shaders", RADV_DEBUG_DUMP_SHADERS},
369 {"nocache", RADV_DEBUG_NO_CACHE},
370 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
371 {"nohiz", RADV_DEBUG_NO_HIZ},
372 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
373 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
374 {"allbos", RADV_DEBUG_ALL_BOS},
375 {"noibs", RADV_DEBUG_NO_IBS},
376 {NULL, 0}
377 };
378
379 static const struct debug_control radv_perftest_options[] = {
380 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
381 {"sisched", RADV_PERFTEST_SISCHED},
382 {NULL, 0}
383 };
384
385 VkResult radv_CreateInstance(
386 const VkInstanceCreateInfo* pCreateInfo,
387 const VkAllocationCallbacks* pAllocator,
388 VkInstance* pInstance)
389 {
390 struct radv_instance *instance;
391
392 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
393
394 uint32_t client_version;
395 if (pCreateInfo->pApplicationInfo &&
396 pCreateInfo->pApplicationInfo->apiVersion != 0) {
397 client_version = pCreateInfo->pApplicationInfo->apiVersion;
398 } else {
399 client_version = VK_MAKE_VERSION(1, 0, 0);
400 }
401
402 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
403 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
404 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
405 "Client requested version %d.%d.%d",
406 VK_VERSION_MAJOR(client_version),
407 VK_VERSION_MINOR(client_version),
408 VK_VERSION_PATCH(client_version));
409 }
410
411 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
412 if (!is_extension_enabled(instance_extensions,
413 ARRAY_SIZE(instance_extensions),
414 pCreateInfo->ppEnabledExtensionNames[i]))
415 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
416 }
417
418 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
419 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
420 if (!instance)
421 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
422
423 memset(instance, 0, sizeof(*instance));
424
425 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
426
427 if (pAllocator)
428 instance->alloc = *pAllocator;
429 else
430 instance->alloc = default_alloc;
431
432 instance->apiVersion = client_version;
433 instance->physicalDeviceCount = -1;
434
435 _mesa_locale_init();
436
437 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
438
439 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
440 radv_debug_options);
441
442 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
443 radv_perftest_options);
444
445 *pInstance = radv_instance_to_handle(instance);
446
447 return VK_SUCCESS;
448 }
449
450 void radv_DestroyInstance(
451 VkInstance _instance,
452 const VkAllocationCallbacks* pAllocator)
453 {
454 RADV_FROM_HANDLE(radv_instance, instance, _instance);
455
456 if (!instance)
457 return;
458
459 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
460 radv_physical_device_finish(instance->physicalDevices + i);
461 }
462
463 VG(VALGRIND_DESTROY_MEMPOOL(instance));
464
465 _mesa_locale_fini();
466
467 vk_free(&instance->alloc, instance);
468 }
469
470 static VkResult
471 radv_enumerate_devices(struct radv_instance *instance)
472 {
473 /* TODO: Check for more devices ? */
474 drmDevicePtr devices[8];
475 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
476 int max_devices;
477
478 instance->physicalDeviceCount = 0;
479
480 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
481 if (max_devices < 1)
482 return VK_ERROR_INCOMPATIBLE_DRIVER;
483
484 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
485 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
486 devices[i]->bustype == DRM_BUS_PCI &&
487 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
488
489 result = radv_physical_device_init(instance->physicalDevices +
490 instance->physicalDeviceCount,
491 instance,
492 devices[i]);
493 if (result == VK_SUCCESS)
494 ++instance->physicalDeviceCount;
495 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
496 break;
497 }
498 }
499 drmFreeDevices(devices, max_devices);
500
501 return result;
502 }
503
504 VkResult radv_EnumeratePhysicalDevices(
505 VkInstance _instance,
506 uint32_t* pPhysicalDeviceCount,
507 VkPhysicalDevice* pPhysicalDevices)
508 {
509 RADV_FROM_HANDLE(radv_instance, instance, _instance);
510 VkResult result;
511
512 if (instance->physicalDeviceCount < 0) {
513 result = radv_enumerate_devices(instance);
514 if (result != VK_SUCCESS &&
515 result != VK_ERROR_INCOMPATIBLE_DRIVER)
516 return result;
517 }
518
519 if (!pPhysicalDevices) {
520 *pPhysicalDeviceCount = instance->physicalDeviceCount;
521 } else {
522 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
523 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
524 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
525 }
526
527 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
528 : VK_SUCCESS;
529 }
530
531 void radv_GetPhysicalDeviceFeatures(
532 VkPhysicalDevice physicalDevice,
533 VkPhysicalDeviceFeatures* pFeatures)
534 {
535 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
536 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
537 memset(pFeatures, 0, sizeof(*pFeatures));
538
539 *pFeatures = (VkPhysicalDeviceFeatures) {
540 .robustBufferAccess = true,
541 .fullDrawIndexUint32 = true,
542 .imageCubeArray = true,
543 .independentBlend = true,
544 .geometryShader = !is_gfx9,
545 .tessellationShader = !is_gfx9,
546 .sampleRateShading = false,
547 .dualSrcBlend = true,
548 .logicOp = true,
549 .multiDrawIndirect = true,
550 .drawIndirectFirstInstance = true,
551 .depthClamp = true,
552 .depthBiasClamp = true,
553 .fillModeNonSolid = true,
554 .depthBounds = true,
555 .wideLines = true,
556 .largePoints = true,
557 .alphaToOne = true,
558 .multiViewport = true,
559 .samplerAnisotropy = true,
560 .textureCompressionETC2 = false,
561 .textureCompressionASTC_LDR = false,
562 .textureCompressionBC = true,
563 .occlusionQueryPrecise = true,
564 .pipelineStatisticsQuery = true,
565 .vertexPipelineStoresAndAtomics = true,
566 .fragmentStoresAndAtomics = true,
567 .shaderTessellationAndGeometryPointSize = true,
568 .shaderImageGatherExtended = true,
569 .shaderStorageImageExtendedFormats = true,
570 .shaderStorageImageMultisample = false,
571 .shaderUniformBufferArrayDynamicIndexing = true,
572 .shaderSampledImageArrayDynamicIndexing = true,
573 .shaderStorageBufferArrayDynamicIndexing = true,
574 .shaderStorageImageArrayDynamicIndexing = true,
575 .shaderStorageImageReadWithoutFormat = true,
576 .shaderStorageImageWriteWithoutFormat = true,
577 .shaderClipDistance = true,
578 .shaderCullDistance = true,
579 .shaderFloat64 = true,
580 .shaderInt64 = true,
581 .shaderInt16 = false,
582 .sparseBinding = true,
583 .variableMultisampleRate = true,
584 .inheritedQueries = true,
585 };
586 }
587
588 void radv_GetPhysicalDeviceFeatures2KHR(
589 VkPhysicalDevice physicalDevice,
590 VkPhysicalDeviceFeatures2KHR *pFeatures)
591 {
592 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
593 }
594
595 void radv_GetPhysicalDeviceProperties(
596 VkPhysicalDevice physicalDevice,
597 VkPhysicalDeviceProperties* pProperties)
598 {
599 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
600 VkSampleCountFlags sample_counts = 0xf;
601
602 /* make sure that the entire descriptor set is addressable with a signed
603 * 32-bit int. So the sum of all limits scaled by descriptor size has to
604 * be at most 2 GiB. the combined image & samples object count as one of
605 * both. This limit is for the pipeline layout, not for the set layout, but
606 * there is no set limit, so we just set a pipeline limit. I don't think
607 * any app is going to hit this soon. */
608 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
609 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
610 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
611 32 /* sampler, largest when combined with image */ +
612 64 /* sampled image */ +
613 64 /* storage image */);
614
615 VkPhysicalDeviceLimits limits = {
616 .maxImageDimension1D = (1 << 14),
617 .maxImageDimension2D = (1 << 14),
618 .maxImageDimension3D = (1 << 11),
619 .maxImageDimensionCube = (1 << 14),
620 .maxImageArrayLayers = (1 << 11),
621 .maxTexelBufferElements = 128 * 1024 * 1024,
622 .maxUniformBufferRange = UINT32_MAX,
623 .maxStorageBufferRange = UINT32_MAX,
624 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
625 .maxMemoryAllocationCount = UINT32_MAX,
626 .maxSamplerAllocationCount = 64 * 1024,
627 .bufferImageGranularity = 64, /* A cache line */
628 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
629 .maxBoundDescriptorSets = MAX_SETS,
630 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
631 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
632 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
633 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
634 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
635 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
636 .maxPerStageResources = max_descriptor_set_size,
637 .maxDescriptorSetSamplers = max_descriptor_set_size,
638 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
639 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
640 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
641 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
642 .maxDescriptorSetSampledImages = max_descriptor_set_size,
643 .maxDescriptorSetStorageImages = max_descriptor_set_size,
644 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
645 .maxVertexInputAttributes = 32,
646 .maxVertexInputBindings = 32,
647 .maxVertexInputAttributeOffset = 2047,
648 .maxVertexInputBindingStride = 2048,
649 .maxVertexOutputComponents = 128,
650 .maxTessellationGenerationLevel = 64,
651 .maxTessellationPatchSize = 32,
652 .maxTessellationControlPerVertexInputComponents = 128,
653 .maxTessellationControlPerVertexOutputComponents = 128,
654 .maxTessellationControlPerPatchOutputComponents = 120,
655 .maxTessellationControlTotalOutputComponents = 4096,
656 .maxTessellationEvaluationInputComponents = 128,
657 .maxTessellationEvaluationOutputComponents = 128,
658 .maxGeometryShaderInvocations = 127,
659 .maxGeometryInputComponents = 64,
660 .maxGeometryOutputComponents = 128,
661 .maxGeometryOutputVertices = 256,
662 .maxGeometryTotalOutputComponents = 1024,
663 .maxFragmentInputComponents = 128,
664 .maxFragmentOutputAttachments = 8,
665 .maxFragmentDualSrcAttachments = 1,
666 .maxFragmentCombinedOutputResources = 8,
667 .maxComputeSharedMemorySize = 32768,
668 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
669 .maxComputeWorkGroupInvocations = 2048,
670 .maxComputeWorkGroupSize = {
671 2048,
672 2048,
673 2048
674 },
675 .subPixelPrecisionBits = 4 /* FIXME */,
676 .subTexelPrecisionBits = 4 /* FIXME */,
677 .mipmapPrecisionBits = 4 /* FIXME */,
678 .maxDrawIndexedIndexValue = UINT32_MAX,
679 .maxDrawIndirectCount = UINT32_MAX,
680 .maxSamplerLodBias = 16,
681 .maxSamplerAnisotropy = 16,
682 .maxViewports = MAX_VIEWPORTS,
683 .maxViewportDimensions = { (1 << 14), (1 << 14) },
684 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
685 .viewportSubPixelBits = 13, /* We take a float? */
686 .minMemoryMapAlignment = 4096, /* A page */
687 .minTexelBufferOffsetAlignment = 1,
688 .minUniformBufferOffsetAlignment = 4,
689 .minStorageBufferOffsetAlignment = 4,
690 .minTexelOffset = -32,
691 .maxTexelOffset = 31,
692 .minTexelGatherOffset = -32,
693 .maxTexelGatherOffset = 31,
694 .minInterpolationOffset = -2,
695 .maxInterpolationOffset = 2,
696 .subPixelInterpolationOffsetBits = 8,
697 .maxFramebufferWidth = (1 << 14),
698 .maxFramebufferHeight = (1 << 14),
699 .maxFramebufferLayers = (1 << 10),
700 .framebufferColorSampleCounts = sample_counts,
701 .framebufferDepthSampleCounts = sample_counts,
702 .framebufferStencilSampleCounts = sample_counts,
703 .framebufferNoAttachmentsSampleCounts = sample_counts,
704 .maxColorAttachments = MAX_RTS,
705 .sampledImageColorSampleCounts = sample_counts,
706 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
707 .sampledImageDepthSampleCounts = sample_counts,
708 .sampledImageStencilSampleCounts = sample_counts,
709 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
710 .maxSampleMaskWords = 1,
711 .timestampComputeAndGraphics = true,
712 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
713 .maxClipDistances = 8,
714 .maxCullDistances = 8,
715 .maxCombinedClipAndCullDistances = 8,
716 .discreteQueuePriorities = 1,
717 .pointSizeRange = { 0.125, 255.875 },
718 .lineWidthRange = { 0.0, 7.9921875 },
719 .pointSizeGranularity = (1.0 / 8.0),
720 .lineWidthGranularity = (1.0 / 128.0),
721 .strictLines = false, /* FINISHME */
722 .standardSampleLocations = true,
723 .optimalBufferCopyOffsetAlignment = 128,
724 .optimalBufferCopyRowPitchAlignment = 128,
725 .nonCoherentAtomSize = 64,
726 };
727
728 *pProperties = (VkPhysicalDeviceProperties) {
729 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
730 .driverVersion = vk_get_driver_version(),
731 .vendorID = 0x1002,
732 .deviceID = pdevice->rad_info.pci_id,
733 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
734 .limits = limits,
735 .sparseProperties = {0},
736 };
737
738 strcpy(pProperties->deviceName, pdevice->name);
739 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
740 }
741
742 void radv_GetPhysicalDeviceProperties2KHR(
743 VkPhysicalDevice physicalDevice,
744 VkPhysicalDeviceProperties2KHR *pProperties)
745 {
746 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
747 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
748
749 vk_foreach_struct(ext, pProperties->pNext) {
750 switch (ext->sType) {
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
752 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
753 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
754 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
755 break;
756 }
757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
758 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
759 radv_device_get_cache_uuid(0, properties->driverUUID);
760 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
761 properties->deviceLUIDValid = false;
762 break;
763 }
764 default:
765 break;
766 }
767 }
768 }
769
770 static void radv_get_physical_device_queue_family_properties(
771 struct radv_physical_device* pdevice,
772 uint32_t* pCount,
773 VkQueueFamilyProperties** pQueueFamilyProperties)
774 {
775 int num_queue_families = 1;
776 int idx;
777 if (pdevice->rad_info.num_compute_rings > 0 &&
778 pdevice->rad_info.chip_class >= CIK &&
779 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
780 num_queue_families++;
781
782 if (pQueueFamilyProperties == NULL) {
783 *pCount = num_queue_families;
784 return;
785 }
786
787 if (!*pCount)
788 return;
789
790 idx = 0;
791 if (*pCount >= 1) {
792 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
793 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
794 VK_QUEUE_COMPUTE_BIT |
795 VK_QUEUE_TRANSFER_BIT |
796 VK_QUEUE_SPARSE_BINDING_BIT,
797 .queueCount = 1,
798 .timestampValidBits = 64,
799 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
800 };
801 idx++;
802 }
803
804 if (pdevice->rad_info.num_compute_rings > 0 &&
805 pdevice->rad_info.chip_class >= CIK &&
806 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
807 if (*pCount > idx) {
808 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
809 .queueFlags = VK_QUEUE_COMPUTE_BIT |
810 VK_QUEUE_TRANSFER_BIT |
811 VK_QUEUE_SPARSE_BINDING_BIT,
812 .queueCount = pdevice->rad_info.num_compute_rings,
813 .timestampValidBits = 64,
814 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
815 };
816 idx++;
817 }
818 }
819 *pCount = idx;
820 }
821
822 void radv_GetPhysicalDeviceQueueFamilyProperties(
823 VkPhysicalDevice physicalDevice,
824 uint32_t* pCount,
825 VkQueueFamilyProperties* pQueueFamilyProperties)
826 {
827 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
828 if (!pQueueFamilyProperties) {
829 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
830 return;
831 }
832 VkQueueFamilyProperties *properties[] = {
833 pQueueFamilyProperties + 0,
834 pQueueFamilyProperties + 1,
835 pQueueFamilyProperties + 2,
836 };
837 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
838 assert(*pCount <= 3);
839 }
840
841 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
842 VkPhysicalDevice physicalDevice,
843 uint32_t* pCount,
844 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
845 {
846 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
847 if (!pQueueFamilyProperties) {
848 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
849 return;
850 }
851 VkQueueFamilyProperties *properties[] = {
852 &pQueueFamilyProperties[0].queueFamilyProperties,
853 &pQueueFamilyProperties[1].queueFamilyProperties,
854 &pQueueFamilyProperties[2].queueFamilyProperties,
855 };
856 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
857 assert(*pCount <= 3);
858 }
859
860 void radv_GetPhysicalDeviceMemoryProperties(
861 VkPhysicalDevice physicalDevice,
862 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
863 {
864 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
865
866 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
867
868 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
869 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
870 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
871 .heapIndex = RADV_MEM_HEAP_VRAM,
872 };
873 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
874 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
875 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
876 .heapIndex = RADV_MEM_HEAP_GTT,
877 };
878 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
879 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
880 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
881 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
882 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
883 };
884 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
885 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
886 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
887 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
888 .heapIndex = RADV_MEM_HEAP_GTT,
889 };
890
891 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
892
893 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
894 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
895 .size = physical_device->rad_info.vram_size -
896 physical_device->rad_info.vram_vis_size,
897 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
898 };
899 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
900 .size = physical_device->rad_info.vram_vis_size,
901 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
902 };
903 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
904 .size = physical_device->rad_info.gart_size,
905 .flags = 0,
906 };
907 }
908
909 void radv_GetPhysicalDeviceMemoryProperties2KHR(
910 VkPhysicalDevice physicalDevice,
911 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
912 {
913 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
914 &pMemoryProperties->memoryProperties);
915 }
916
917 static int
918 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
919 int queue_family_index, int idx)
920 {
921 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
922 queue->device = device;
923 queue->queue_family_index = queue_family_index;
924 queue->queue_idx = idx;
925
926 queue->hw_ctx = device->ws->ctx_create(device->ws);
927 if (!queue->hw_ctx)
928 return VK_ERROR_OUT_OF_HOST_MEMORY;
929
930 return VK_SUCCESS;
931 }
932
933 static void
934 radv_queue_finish(struct radv_queue *queue)
935 {
936 if (queue->hw_ctx)
937 queue->device->ws->ctx_destroy(queue->hw_ctx);
938
939 if (queue->initial_preamble_cs)
940 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
941 if (queue->continue_preamble_cs)
942 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
943 if (queue->descriptor_bo)
944 queue->device->ws->buffer_destroy(queue->descriptor_bo);
945 if (queue->scratch_bo)
946 queue->device->ws->buffer_destroy(queue->scratch_bo);
947 if (queue->esgs_ring_bo)
948 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
949 if (queue->gsvs_ring_bo)
950 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
951 if (queue->tess_factor_ring_bo)
952 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
953 if (queue->tess_offchip_ring_bo)
954 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
955 if (queue->compute_scratch_bo)
956 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
957 }
958
959 static void
960 radv_device_init_gs_info(struct radv_device *device)
961 {
962 switch (device->physical_device->rad_info.family) {
963 case CHIP_OLAND:
964 case CHIP_HAINAN:
965 case CHIP_KAVERI:
966 case CHIP_KABINI:
967 case CHIP_MULLINS:
968 case CHIP_ICELAND:
969 case CHIP_CARRIZO:
970 case CHIP_STONEY:
971 device->gs_table_depth = 16;
972 return;
973 case CHIP_TAHITI:
974 case CHIP_PITCAIRN:
975 case CHIP_VERDE:
976 case CHIP_BONAIRE:
977 case CHIP_HAWAII:
978 case CHIP_TONGA:
979 case CHIP_FIJI:
980 case CHIP_POLARIS10:
981 case CHIP_POLARIS11:
982 case CHIP_POLARIS12:
983 case CHIP_VEGA10:
984 case CHIP_RAVEN:
985 device->gs_table_depth = 32;
986 return;
987 default:
988 unreachable("unknown GPU");
989 }
990 }
991
992 VkResult radv_CreateDevice(
993 VkPhysicalDevice physicalDevice,
994 const VkDeviceCreateInfo* pCreateInfo,
995 const VkAllocationCallbacks* pAllocator,
996 VkDevice* pDevice)
997 {
998 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
999 VkResult result;
1000 struct radv_device *device;
1001
1002 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1003 if (!is_extension_enabled(physical_device->extensions.ext_array,
1004 physical_device->extensions.num_ext,
1005 pCreateInfo->ppEnabledExtensionNames[i]))
1006 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1007 }
1008
1009 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1010 sizeof(*device), 8,
1011 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1012 if (!device)
1013 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1014
1015 memset(device, 0, sizeof(*device));
1016
1017 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1018 device->instance = physical_device->instance;
1019 device->physical_device = physical_device;
1020
1021 device->debug_flags = device->instance->debug_flags;
1022
1023 device->ws = physical_device->ws;
1024 if (pAllocator)
1025 device->alloc = *pAllocator;
1026 else
1027 device->alloc = physical_device->instance->alloc;
1028
1029 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1030 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1031 uint32_t qfi = queue_create->queueFamilyIndex;
1032
1033 device->queues[qfi] = vk_alloc(&device->alloc,
1034 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1035 if (!device->queues[qfi]) {
1036 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1037 goto fail;
1038 }
1039
1040 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1041
1042 device->queue_count[qfi] = queue_create->queueCount;
1043
1044 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1045 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1046 if (result != VK_SUCCESS)
1047 goto fail;
1048 }
1049 }
1050
1051 #if HAVE_LLVM < 0x0400
1052 device->llvm_supports_spill = false;
1053 #else
1054 device->llvm_supports_spill = true;
1055 #endif
1056
1057 /* The maximum number of scratch waves. Scratch space isn't divided
1058 * evenly between CUs. The number is only a function of the number of CUs.
1059 * We can decrease the constant to decrease the scratch buffer size.
1060 *
1061 * sctx->scratch_waves must be >= the maximum posible size of
1062 * 1 threadgroup, so that the hw doesn't hang from being unable
1063 * to start any.
1064 *
1065 * The recommended value is 4 per CU at most. Higher numbers don't
1066 * bring much benefit, but they still occupy chip resources (think
1067 * async compute). I've seen ~2% performance difference between 4 and 32.
1068 */
1069 uint32_t max_threads_per_block = 2048;
1070 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1071 max_threads_per_block / 64);
1072
1073 radv_device_init_gs_info(device);
1074
1075 device->tess_offchip_block_dw_size =
1076 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1077 device->has_distributed_tess =
1078 device->physical_device->rad_info.chip_class >= VI &&
1079 device->physical_device->rad_info.max_se >= 2;
1080
1081 result = radv_device_init_meta(device);
1082 if (result != VK_SUCCESS)
1083 goto fail;
1084
1085 radv_device_init_msaa(device);
1086
1087 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1088 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1089 switch (family) {
1090 case RADV_QUEUE_GENERAL:
1091 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1092 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1093 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1094 break;
1095 case RADV_QUEUE_COMPUTE:
1096 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1097 radeon_emit(device->empty_cs[family], 0);
1098 break;
1099 }
1100 device->ws->cs_finalize(device->empty_cs[family]);
1101
1102 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1103 switch (family) {
1104 case RADV_QUEUE_GENERAL:
1105 case RADV_QUEUE_COMPUTE:
1106 si_cs_emit_cache_flush(device->flush_cs[family],
1107 false,
1108 device->physical_device->rad_info.chip_class,
1109 NULL, 0,
1110 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1111 RADV_CMD_FLAG_INV_ICACHE |
1112 RADV_CMD_FLAG_INV_SMEM_L1 |
1113 RADV_CMD_FLAG_INV_VMEM_L1 |
1114 RADV_CMD_FLAG_INV_GLOBAL_L2);
1115 break;
1116 }
1117 device->ws->cs_finalize(device->flush_cs[family]);
1118
1119 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1120 switch (family) {
1121 case RADV_QUEUE_GENERAL:
1122 case RADV_QUEUE_COMPUTE:
1123 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1124 false,
1125 device->physical_device->rad_info.chip_class,
1126 NULL, 0,
1127 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1128 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1129 RADV_CMD_FLAG_INV_ICACHE |
1130 RADV_CMD_FLAG_INV_SMEM_L1 |
1131 RADV_CMD_FLAG_INV_VMEM_L1 |
1132 RADV_CMD_FLAG_INV_GLOBAL_L2);
1133 break;
1134 }
1135 device->ws->cs_finalize(device->flush_shader_cs[family]);
1136 }
1137
1138 if (getenv("RADV_TRACE_FILE")) {
1139 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1140 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1141 if (!device->trace_bo)
1142 goto fail;
1143
1144 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1145 if (!device->trace_id_ptr)
1146 goto fail;
1147 }
1148
1149 if (device->physical_device->rad_info.chip_class >= CIK)
1150 cik_create_gfx_config(device);
1151
1152 VkPipelineCacheCreateInfo ci;
1153 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1154 ci.pNext = NULL;
1155 ci.flags = 0;
1156 ci.pInitialData = NULL;
1157 ci.initialDataSize = 0;
1158 VkPipelineCache pc;
1159 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1160 &ci, NULL, &pc);
1161 if (result != VK_SUCCESS)
1162 goto fail;
1163
1164 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1165
1166 *pDevice = radv_device_to_handle(device);
1167 return VK_SUCCESS;
1168
1169 fail:
1170 if (device->trace_bo)
1171 device->ws->buffer_destroy(device->trace_bo);
1172
1173 if (device->gfx_init)
1174 device->ws->buffer_destroy(device->gfx_init);
1175
1176 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1177 for (unsigned q = 0; q < device->queue_count[i]; q++)
1178 radv_queue_finish(&device->queues[i][q]);
1179 if (device->queue_count[i])
1180 vk_free(&device->alloc, device->queues[i]);
1181 }
1182
1183 vk_free(&device->alloc, device);
1184 return result;
1185 }
1186
1187 void radv_DestroyDevice(
1188 VkDevice _device,
1189 const VkAllocationCallbacks* pAllocator)
1190 {
1191 RADV_FROM_HANDLE(radv_device, device, _device);
1192
1193 if (!device)
1194 return;
1195
1196 if (device->trace_bo)
1197 device->ws->buffer_destroy(device->trace_bo);
1198
1199 if (device->gfx_init)
1200 device->ws->buffer_destroy(device->gfx_init);
1201
1202 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1203 for (unsigned q = 0; q < device->queue_count[i]; q++)
1204 radv_queue_finish(&device->queues[i][q]);
1205 if (device->queue_count[i])
1206 vk_free(&device->alloc, device->queues[i]);
1207 if (device->empty_cs[i])
1208 device->ws->cs_destroy(device->empty_cs[i]);
1209 if (device->flush_cs[i])
1210 device->ws->cs_destroy(device->flush_cs[i]);
1211 if (device->flush_shader_cs[i])
1212 device->ws->cs_destroy(device->flush_shader_cs[i]);
1213 }
1214 radv_device_finish_meta(device);
1215
1216 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1217 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1218
1219 vk_free(&device->alloc, device);
1220 }
1221
1222 VkResult radv_EnumerateInstanceExtensionProperties(
1223 const char* pLayerName,
1224 uint32_t* pPropertyCount,
1225 VkExtensionProperties* pProperties)
1226 {
1227 if (pProperties == NULL) {
1228 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1229 return VK_SUCCESS;
1230 }
1231
1232 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1233 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1234
1235 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1236 return VK_INCOMPLETE;
1237
1238 return VK_SUCCESS;
1239 }
1240
1241 VkResult radv_EnumerateDeviceExtensionProperties(
1242 VkPhysicalDevice physicalDevice,
1243 const char* pLayerName,
1244 uint32_t* pPropertyCount,
1245 VkExtensionProperties* pProperties)
1246 {
1247 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1248
1249 if (pProperties == NULL) {
1250 *pPropertyCount = pdevice->extensions.num_ext;
1251 return VK_SUCCESS;
1252 }
1253
1254 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1255 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1256
1257 if (*pPropertyCount < pdevice->extensions.num_ext)
1258 return VK_INCOMPLETE;
1259
1260 return VK_SUCCESS;
1261 }
1262
1263 VkResult radv_EnumerateInstanceLayerProperties(
1264 uint32_t* pPropertyCount,
1265 VkLayerProperties* pProperties)
1266 {
1267 if (pProperties == NULL) {
1268 *pPropertyCount = 0;
1269 return VK_SUCCESS;
1270 }
1271
1272 /* None supported at this time */
1273 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1274 }
1275
1276 VkResult radv_EnumerateDeviceLayerProperties(
1277 VkPhysicalDevice physicalDevice,
1278 uint32_t* pPropertyCount,
1279 VkLayerProperties* pProperties)
1280 {
1281 if (pProperties == NULL) {
1282 *pPropertyCount = 0;
1283 return VK_SUCCESS;
1284 }
1285
1286 /* None supported at this time */
1287 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1288 }
1289
1290 void radv_GetDeviceQueue(
1291 VkDevice _device,
1292 uint32_t queueFamilyIndex,
1293 uint32_t queueIndex,
1294 VkQueue* pQueue)
1295 {
1296 RADV_FROM_HANDLE(radv_device, device, _device);
1297
1298 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1299 }
1300
1301 static void radv_dump_trace(struct radv_device *device,
1302 struct radeon_winsys_cs *cs)
1303 {
1304 const char *filename = getenv("RADV_TRACE_FILE");
1305 FILE *f = fopen(filename, "w");
1306 if (!f) {
1307 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1308 return;
1309 }
1310
1311 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1312 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1313 fclose(f);
1314 }
1315
1316 static void
1317 fill_geom_tess_rings(struct radv_queue *queue,
1318 uint32_t *map,
1319 bool add_sample_positions,
1320 uint32_t esgs_ring_size,
1321 struct radeon_winsys_bo *esgs_ring_bo,
1322 uint32_t gsvs_ring_size,
1323 struct radeon_winsys_bo *gsvs_ring_bo,
1324 uint32_t tess_factor_ring_size,
1325 struct radeon_winsys_bo *tess_factor_ring_bo,
1326 uint32_t tess_offchip_ring_size,
1327 struct radeon_winsys_bo *tess_offchip_ring_bo)
1328 {
1329 uint64_t esgs_va = 0, gsvs_va = 0;
1330 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1331 uint32_t *desc = &map[4];
1332
1333 if (esgs_ring_bo)
1334 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1335 if (gsvs_ring_bo)
1336 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1337 if (tess_factor_ring_bo)
1338 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1339 if (tess_offchip_ring_bo)
1340 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1341
1342 /* stride 0, num records - size, add tid, swizzle, elsize4,
1343 index stride 64 */
1344 desc[0] = esgs_va;
1345 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1346 S_008F04_STRIDE(0) |
1347 S_008F04_SWIZZLE_ENABLE(true);
1348 desc[2] = esgs_ring_size;
1349 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1350 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1351 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1352 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1353 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1354 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1355 S_008F0C_ELEMENT_SIZE(1) |
1356 S_008F0C_INDEX_STRIDE(3) |
1357 S_008F0C_ADD_TID_ENABLE(true);
1358
1359 desc += 4;
1360 /* GS entry for ES->GS ring */
1361 /* stride 0, num records - size, elsize0,
1362 index stride 0 */
1363 desc[0] = esgs_va;
1364 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1365 S_008F04_STRIDE(0) |
1366 S_008F04_SWIZZLE_ENABLE(false);
1367 desc[2] = esgs_ring_size;
1368 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1369 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1370 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1371 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1372 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1373 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1374 S_008F0C_ELEMENT_SIZE(0) |
1375 S_008F0C_INDEX_STRIDE(0) |
1376 S_008F0C_ADD_TID_ENABLE(false);
1377
1378 desc += 4;
1379 /* VS entry for GS->VS ring */
1380 /* stride 0, num records - size, elsize0,
1381 index stride 0 */
1382 desc[0] = gsvs_va;
1383 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1384 S_008F04_STRIDE(0) |
1385 S_008F04_SWIZZLE_ENABLE(false);
1386 desc[2] = gsvs_ring_size;
1387 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1388 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1389 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1390 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1391 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1392 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1393 S_008F0C_ELEMENT_SIZE(0) |
1394 S_008F0C_INDEX_STRIDE(0) |
1395 S_008F0C_ADD_TID_ENABLE(false);
1396 desc += 4;
1397
1398 /* stride gsvs_itemsize, num records 64
1399 elsize 4, index stride 16 */
1400 /* shader will patch stride and desc[2] */
1401 desc[0] = gsvs_va;
1402 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1403 S_008F04_STRIDE(0) |
1404 S_008F04_SWIZZLE_ENABLE(true);
1405 desc[2] = 0;
1406 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1407 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1408 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1409 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1410 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1411 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1412 S_008F0C_ELEMENT_SIZE(1) |
1413 S_008F0C_INDEX_STRIDE(1) |
1414 S_008F0C_ADD_TID_ENABLE(true);
1415 desc += 4;
1416
1417 desc[0] = tess_factor_va;
1418 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1419 S_008F04_STRIDE(0) |
1420 S_008F04_SWIZZLE_ENABLE(false);
1421 desc[2] = tess_factor_ring_size;
1422 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1423 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1424 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1425 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1426 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1427 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1428 S_008F0C_ELEMENT_SIZE(0) |
1429 S_008F0C_INDEX_STRIDE(0) |
1430 S_008F0C_ADD_TID_ENABLE(false);
1431 desc += 4;
1432
1433 desc[0] = tess_offchip_va;
1434 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1435 S_008F04_STRIDE(0) |
1436 S_008F04_SWIZZLE_ENABLE(false);
1437 desc[2] = tess_offchip_ring_size;
1438 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1439 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1440 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1441 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1442 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1443 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1444 S_008F0C_ELEMENT_SIZE(0) |
1445 S_008F0C_INDEX_STRIDE(0) |
1446 S_008F0C_ADD_TID_ENABLE(false);
1447 desc += 4;
1448
1449 /* add sample positions after all rings */
1450 memcpy(desc, queue->device->sample_locations_1x, 8);
1451 desc += 2;
1452 memcpy(desc, queue->device->sample_locations_2x, 16);
1453 desc += 4;
1454 memcpy(desc, queue->device->sample_locations_4x, 32);
1455 desc += 8;
1456 memcpy(desc, queue->device->sample_locations_8x, 64);
1457 desc += 16;
1458 memcpy(desc, queue->device->sample_locations_16x, 128);
1459 }
1460
1461 static unsigned
1462 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1463 {
1464 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1465 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1466 device->physical_device->rad_info.family != CHIP_STONEY;
1467 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1468 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1469 device->physical_device->rad_info.max_se;
1470 unsigned offchip_granularity;
1471 unsigned hs_offchip_param;
1472 switch (device->tess_offchip_block_dw_size) {
1473 default:
1474 assert(0);
1475 /* fall through */
1476 case 8192:
1477 offchip_granularity = V_03093C_X_8K_DWORDS;
1478 break;
1479 case 4096:
1480 offchip_granularity = V_03093C_X_4K_DWORDS;
1481 break;
1482 }
1483
1484 switch (device->physical_device->rad_info.chip_class) {
1485 case SI:
1486 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1487 break;
1488 case CIK:
1489 case VI:
1490 case GFX9:
1491 default:
1492 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1493 break;
1494 }
1495
1496 *max_offchip_buffers_p = max_offchip_buffers;
1497 if (device->physical_device->rad_info.chip_class >= CIK) {
1498 if (device->physical_device->rad_info.chip_class >= VI)
1499 --max_offchip_buffers;
1500 hs_offchip_param =
1501 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1502 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1503 } else {
1504 hs_offchip_param =
1505 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1506 }
1507 return hs_offchip_param;
1508 }
1509
1510 static VkResult
1511 radv_get_preamble_cs(struct radv_queue *queue,
1512 uint32_t scratch_size,
1513 uint32_t compute_scratch_size,
1514 uint32_t esgs_ring_size,
1515 uint32_t gsvs_ring_size,
1516 bool needs_tess_rings,
1517 bool needs_sample_positions,
1518 struct radeon_winsys_cs **initial_preamble_cs,
1519 struct radeon_winsys_cs **continue_preamble_cs)
1520 {
1521 struct radeon_winsys_bo *scratch_bo = NULL;
1522 struct radeon_winsys_bo *descriptor_bo = NULL;
1523 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1524 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1525 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1526 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1527 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1528 struct radeon_winsys_cs *dest_cs[2] = {0};
1529 bool add_tess_rings = false, add_sample_positions = false;
1530 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1531 unsigned max_offchip_buffers;
1532 unsigned hs_offchip_param = 0;
1533 if (!queue->has_tess_rings) {
1534 if (needs_tess_rings)
1535 add_tess_rings = true;
1536 }
1537 if (!queue->has_sample_positions) {
1538 if (needs_sample_positions)
1539 add_sample_positions = true;
1540 }
1541 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1542 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1543 &max_offchip_buffers);
1544 tess_offchip_ring_size = max_offchip_buffers *
1545 queue->device->tess_offchip_block_dw_size * 4;
1546
1547 if (scratch_size <= queue->scratch_size &&
1548 compute_scratch_size <= queue->compute_scratch_size &&
1549 esgs_ring_size <= queue->esgs_ring_size &&
1550 gsvs_ring_size <= queue->gsvs_ring_size &&
1551 !add_tess_rings && !add_sample_positions &&
1552 queue->initial_preamble_cs) {
1553 *initial_preamble_cs = queue->initial_preamble_cs;
1554 *continue_preamble_cs = queue->continue_preamble_cs;
1555 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1556 *continue_preamble_cs = NULL;
1557 return VK_SUCCESS;
1558 }
1559
1560 if (scratch_size > queue->scratch_size) {
1561 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1562 scratch_size,
1563 4096,
1564 RADEON_DOMAIN_VRAM,
1565 RADEON_FLAG_NO_CPU_ACCESS);
1566 if (!scratch_bo)
1567 goto fail;
1568 } else
1569 scratch_bo = queue->scratch_bo;
1570
1571 if (compute_scratch_size > queue->compute_scratch_size) {
1572 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1573 compute_scratch_size,
1574 4096,
1575 RADEON_DOMAIN_VRAM,
1576 RADEON_FLAG_NO_CPU_ACCESS);
1577 if (!compute_scratch_bo)
1578 goto fail;
1579
1580 } else
1581 compute_scratch_bo = queue->compute_scratch_bo;
1582
1583 if (esgs_ring_size > queue->esgs_ring_size) {
1584 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1585 esgs_ring_size,
1586 4096,
1587 RADEON_DOMAIN_VRAM,
1588 RADEON_FLAG_NO_CPU_ACCESS);
1589 if (!esgs_ring_bo)
1590 goto fail;
1591 } else {
1592 esgs_ring_bo = queue->esgs_ring_bo;
1593 esgs_ring_size = queue->esgs_ring_size;
1594 }
1595
1596 if (gsvs_ring_size > queue->gsvs_ring_size) {
1597 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1598 gsvs_ring_size,
1599 4096,
1600 RADEON_DOMAIN_VRAM,
1601 RADEON_FLAG_NO_CPU_ACCESS);
1602 if (!gsvs_ring_bo)
1603 goto fail;
1604 } else {
1605 gsvs_ring_bo = queue->gsvs_ring_bo;
1606 gsvs_ring_size = queue->gsvs_ring_size;
1607 }
1608
1609 if (add_tess_rings) {
1610 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1611 tess_factor_ring_size,
1612 256,
1613 RADEON_DOMAIN_VRAM,
1614 RADEON_FLAG_NO_CPU_ACCESS);
1615 if (!tess_factor_ring_bo)
1616 goto fail;
1617 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1618 tess_offchip_ring_size,
1619 256,
1620 RADEON_DOMAIN_VRAM,
1621 RADEON_FLAG_NO_CPU_ACCESS);
1622 if (!tess_offchip_ring_bo)
1623 goto fail;
1624 } else {
1625 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1626 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1627 }
1628
1629 if (scratch_bo != queue->scratch_bo ||
1630 esgs_ring_bo != queue->esgs_ring_bo ||
1631 gsvs_ring_bo != queue->gsvs_ring_bo ||
1632 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1633 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1634 uint32_t size = 0;
1635 if (gsvs_ring_bo || esgs_ring_bo ||
1636 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1637 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1638 if (add_sample_positions)
1639 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1640 }
1641 else if (scratch_bo)
1642 size = 8; /* 2 dword */
1643
1644 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1645 size,
1646 4096,
1647 RADEON_DOMAIN_VRAM,
1648 RADEON_FLAG_CPU_ACCESS);
1649 if (!descriptor_bo)
1650 goto fail;
1651 } else
1652 descriptor_bo = queue->descriptor_bo;
1653
1654 for(int i = 0; i < 2; ++i) {
1655 struct radeon_winsys_cs *cs = NULL;
1656 cs = queue->device->ws->cs_create(queue->device->ws,
1657 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1658 if (!cs)
1659 goto fail;
1660
1661 dest_cs[i] = cs;
1662
1663 if (scratch_bo)
1664 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1665
1666 if (esgs_ring_bo)
1667 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1668
1669 if (gsvs_ring_bo)
1670 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1671
1672 if (tess_factor_ring_bo)
1673 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1674
1675 if (tess_offchip_ring_bo)
1676 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1677
1678 if (descriptor_bo)
1679 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1680
1681 if (descriptor_bo != queue->descriptor_bo) {
1682 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1683
1684 if (scratch_bo) {
1685 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1686 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1687 S_008F04_SWIZZLE_ENABLE(1);
1688 map[0] = scratch_va;
1689 map[1] = rsrc1;
1690 }
1691
1692 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1693 add_sample_positions)
1694 fill_geom_tess_rings(queue, map, add_sample_positions,
1695 esgs_ring_size, esgs_ring_bo,
1696 gsvs_ring_size, gsvs_ring_bo,
1697 tess_factor_ring_size, tess_factor_ring_bo,
1698 tess_offchip_ring_size, tess_offchip_ring_bo);
1699
1700 queue->device->ws->buffer_unmap(descriptor_bo);
1701 }
1702
1703 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1704 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1705 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1706 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1707 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1708 }
1709
1710 if (esgs_ring_bo || gsvs_ring_bo) {
1711 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1712 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1713 radeon_emit(cs, esgs_ring_size >> 8);
1714 radeon_emit(cs, gsvs_ring_size >> 8);
1715 } else {
1716 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1717 radeon_emit(cs, esgs_ring_size >> 8);
1718 radeon_emit(cs, gsvs_ring_size >> 8);
1719 }
1720 }
1721
1722 if (tess_factor_ring_bo) {
1723 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1724 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1725 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1726 S_030938_SIZE(tess_factor_ring_size / 4));
1727 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1728 tf_va >> 8);
1729 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1730 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1731 tf_va >> 40);
1732 }
1733 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1734 } else {
1735 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1736 S_008988_SIZE(tess_factor_ring_size / 4));
1737 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1738 tf_va >> 8);
1739 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1740 hs_offchip_param);
1741 }
1742 }
1743
1744 if (descriptor_bo) {
1745 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1746 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1747 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1748 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1749 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1750 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1751
1752 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1753
1754 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1755 radeon_set_sh_reg_seq(cs, regs[i], 2);
1756 radeon_emit(cs, va);
1757 radeon_emit(cs, va >> 32);
1758 }
1759 }
1760
1761 if (compute_scratch_bo) {
1762 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1763 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1764 S_008F04_SWIZZLE_ENABLE(1);
1765
1766 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1767
1768 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1769 radeon_emit(cs, scratch_va);
1770 radeon_emit(cs, rsrc1);
1771 }
1772
1773 if (!i) {
1774 si_cs_emit_cache_flush(cs,
1775 false,
1776 queue->device->physical_device->rad_info.chip_class,
1777 NULL, 0,
1778 queue->queue_family_index == RING_COMPUTE &&
1779 queue->device->physical_device->rad_info.chip_class >= CIK,
1780 RADV_CMD_FLAG_INV_ICACHE |
1781 RADV_CMD_FLAG_INV_SMEM_L1 |
1782 RADV_CMD_FLAG_INV_VMEM_L1 |
1783 RADV_CMD_FLAG_INV_GLOBAL_L2);
1784 }
1785
1786 if (!queue->device->ws->cs_finalize(cs))
1787 goto fail;
1788 }
1789
1790 if (queue->initial_preamble_cs)
1791 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1792
1793 if (queue->continue_preamble_cs)
1794 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1795
1796 queue->initial_preamble_cs = dest_cs[0];
1797 queue->continue_preamble_cs = dest_cs[1];
1798
1799 if (scratch_bo != queue->scratch_bo) {
1800 if (queue->scratch_bo)
1801 queue->device->ws->buffer_destroy(queue->scratch_bo);
1802 queue->scratch_bo = scratch_bo;
1803 queue->scratch_size = scratch_size;
1804 }
1805
1806 if (compute_scratch_bo != queue->compute_scratch_bo) {
1807 if (queue->compute_scratch_bo)
1808 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1809 queue->compute_scratch_bo = compute_scratch_bo;
1810 queue->compute_scratch_size = compute_scratch_size;
1811 }
1812
1813 if (esgs_ring_bo != queue->esgs_ring_bo) {
1814 if (queue->esgs_ring_bo)
1815 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1816 queue->esgs_ring_bo = esgs_ring_bo;
1817 queue->esgs_ring_size = esgs_ring_size;
1818 }
1819
1820 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1821 if (queue->gsvs_ring_bo)
1822 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1823 queue->gsvs_ring_bo = gsvs_ring_bo;
1824 queue->gsvs_ring_size = gsvs_ring_size;
1825 }
1826
1827 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1828 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1829 }
1830
1831 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1832 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1833 queue->has_tess_rings = true;
1834 }
1835
1836 if (descriptor_bo != queue->descriptor_bo) {
1837 if (queue->descriptor_bo)
1838 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1839
1840 queue->descriptor_bo = descriptor_bo;
1841 }
1842
1843 if (add_sample_positions)
1844 queue->has_sample_positions = true;
1845
1846 *initial_preamble_cs = queue->initial_preamble_cs;
1847 *continue_preamble_cs = queue->continue_preamble_cs;
1848 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1849 *continue_preamble_cs = NULL;
1850 return VK_SUCCESS;
1851 fail:
1852 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1853 if (dest_cs[i])
1854 queue->device->ws->cs_destroy(dest_cs[i]);
1855 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1856 queue->device->ws->buffer_destroy(descriptor_bo);
1857 if (scratch_bo && scratch_bo != queue->scratch_bo)
1858 queue->device->ws->buffer_destroy(scratch_bo);
1859 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1860 queue->device->ws->buffer_destroy(compute_scratch_bo);
1861 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1862 queue->device->ws->buffer_destroy(esgs_ring_bo);
1863 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1864 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1865 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1866 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1867 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1868 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1869 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1870 }
1871
1872 VkResult radv_QueueSubmit(
1873 VkQueue _queue,
1874 uint32_t submitCount,
1875 const VkSubmitInfo* pSubmits,
1876 VkFence _fence)
1877 {
1878 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1879 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1880 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1881 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1882 int ret;
1883 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1884 uint32_t scratch_size = 0;
1885 uint32_t compute_scratch_size = 0;
1886 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1887 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1888 VkResult result;
1889 bool fence_emitted = false;
1890 bool tess_rings_needed = false;
1891 bool sample_positions_needed = false;
1892
1893 /* Do this first so failing to allocate scratch buffers can't result in
1894 * partially executed submissions. */
1895 for (uint32_t i = 0; i < submitCount; i++) {
1896 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1898 pSubmits[i].pCommandBuffers[j]);
1899
1900 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1901 compute_scratch_size = MAX2(compute_scratch_size,
1902 cmd_buffer->compute_scratch_size_needed);
1903 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1904 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1905 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1906 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1907 }
1908 }
1909
1910 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1911 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1912 sample_positions_needed,
1913 &initial_preamble_cs, &continue_preamble_cs);
1914 if (result != VK_SUCCESS)
1915 return result;
1916
1917 for (uint32_t i = 0; i < submitCount; i++) {
1918 struct radeon_winsys_cs **cs_array;
1919 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1920 bool can_patch = !do_flush;
1921 uint32_t advance;
1922
1923 if (!pSubmits[i].commandBufferCount) {
1924 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1925 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1926 &queue->device->empty_cs[queue->queue_family_index],
1927 1, NULL, NULL,
1928 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1929 pSubmits[i].waitSemaphoreCount,
1930 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1931 pSubmits[i].signalSemaphoreCount,
1932 false, base_fence);
1933 if (ret) {
1934 radv_loge("failed to submit CS %d\n", i);
1935 abort();
1936 }
1937 fence_emitted = true;
1938 }
1939 continue;
1940 }
1941
1942 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1943 (pSubmits[i].commandBufferCount + do_flush));
1944
1945 if(do_flush)
1946 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
1947 queue->device->flush_shader_cs[queue->queue_family_index] :
1948 queue->device->flush_cs[queue->queue_family_index];
1949
1950 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1952 pSubmits[i].pCommandBuffers[j]);
1953 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1954
1955 cs_array[j + do_flush] = cmd_buffer->cs;
1956 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1957 can_patch = false;
1958 }
1959
1960 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1961 advance = MIN2(max_cs_submission,
1962 pSubmits[i].commandBufferCount + do_flush - j);
1963 bool b = j == 0;
1964 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1965
1966 if (queue->device->trace_bo)
1967 *queue->device->trace_id_ptr = 0;
1968
1969 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1970 advance, initial_preamble_cs, continue_preamble_cs,
1971 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1972 b ? pSubmits[i].waitSemaphoreCount : 0,
1973 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1974 e ? pSubmits[i].signalSemaphoreCount : 0,
1975 can_patch, base_fence);
1976
1977 if (ret) {
1978 radv_loge("failed to submit CS %d\n", i);
1979 abort();
1980 }
1981 fence_emitted = true;
1982 if (queue->device->trace_bo) {
1983 bool success = queue->device->ws->ctx_wait_idle(
1984 queue->hw_ctx,
1985 radv_queue_family_to_ring(
1986 queue->queue_family_index),
1987 queue->queue_idx);
1988
1989 if (!success) { /* Hang */
1990 radv_dump_trace(queue->device, cs_array[j]);
1991 abort();
1992 }
1993 }
1994 }
1995 free(cs_array);
1996 }
1997
1998 if (fence) {
1999 if (!fence_emitted)
2000 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2001 &queue->device->empty_cs[queue->queue_family_index],
2002 1, NULL, NULL, NULL, 0, NULL, 0,
2003 false, base_fence);
2004
2005 fence->submitted = true;
2006 }
2007
2008 return VK_SUCCESS;
2009 }
2010
2011 VkResult radv_QueueWaitIdle(
2012 VkQueue _queue)
2013 {
2014 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2015
2016 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2017 radv_queue_family_to_ring(queue->queue_family_index),
2018 queue->queue_idx);
2019 return VK_SUCCESS;
2020 }
2021
2022 VkResult radv_DeviceWaitIdle(
2023 VkDevice _device)
2024 {
2025 RADV_FROM_HANDLE(radv_device, device, _device);
2026
2027 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2028 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2029 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2030 }
2031 }
2032 return VK_SUCCESS;
2033 }
2034
2035 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2036 VkInstance instance,
2037 const char* pName)
2038 {
2039 return radv_lookup_entrypoint(pName);
2040 }
2041
2042 /* The loader wants us to expose a second GetInstanceProcAddr function
2043 * to work around certain LD_PRELOAD issues seen in apps.
2044 */
2045 PUBLIC
2046 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2047 VkInstance instance,
2048 const char* pName);
2049
2050 PUBLIC
2051 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2052 VkInstance instance,
2053 const char* pName)
2054 {
2055 return radv_GetInstanceProcAddr(instance, pName);
2056 }
2057
2058 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2059 VkDevice device,
2060 const char* pName)
2061 {
2062 return radv_lookup_entrypoint(pName);
2063 }
2064
2065 bool radv_get_memory_fd(struct radv_device *device,
2066 struct radv_device_memory *memory,
2067 int *pFD)
2068 {
2069 struct radeon_bo_metadata metadata;
2070
2071 if (memory->image) {
2072 radv_init_metadata(device, memory->image, &metadata);
2073 device->ws->buffer_set_metadata(memory->bo, &metadata);
2074 }
2075
2076 return device->ws->buffer_get_fd(device->ws, memory->bo,
2077 pFD);
2078 }
2079
2080 VkResult radv_AllocateMemory(
2081 VkDevice _device,
2082 const VkMemoryAllocateInfo* pAllocateInfo,
2083 const VkAllocationCallbacks* pAllocator,
2084 VkDeviceMemory* pMem)
2085 {
2086 RADV_FROM_HANDLE(radv_device, device, _device);
2087 struct radv_device_memory *mem;
2088 VkResult result;
2089 enum radeon_bo_domain domain;
2090 uint32_t flags = 0;
2091
2092 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2093
2094 if (pAllocateInfo->allocationSize == 0) {
2095 /* Apparently, this is allowed */
2096 *pMem = VK_NULL_HANDLE;
2097 return VK_SUCCESS;
2098 }
2099
2100 const VkImportMemoryFdInfoKHR *import_info =
2101 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2102 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2103 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2104
2105 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2106 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2107 if (mem == NULL)
2108 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2109
2110 if (dedicate_info) {
2111 mem->image = radv_image_from_handle(dedicate_info->image);
2112 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2113 } else {
2114 mem->image = NULL;
2115 mem->buffer = NULL;
2116 }
2117
2118 if (import_info) {
2119 assert(import_info->handleType ==
2120 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2121 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2122 NULL, NULL);
2123 if (!mem->bo) {
2124 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2125 goto fail;
2126 } else
2127 goto out_success;
2128 }
2129
2130 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2131 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2132 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2133 domain = RADEON_DOMAIN_GTT;
2134 else
2135 domain = RADEON_DOMAIN_VRAM;
2136
2137 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2138 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2139 else
2140 flags |= RADEON_FLAG_CPU_ACCESS;
2141
2142 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2143 flags |= RADEON_FLAG_GTT_WC;
2144
2145 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2146 domain, flags);
2147
2148 if (!mem->bo) {
2149 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2150 goto fail;
2151 }
2152 mem->type_index = pAllocateInfo->memoryTypeIndex;
2153 out_success:
2154 *pMem = radv_device_memory_to_handle(mem);
2155
2156 return VK_SUCCESS;
2157
2158 fail:
2159 vk_free2(&device->alloc, pAllocator, mem);
2160
2161 return result;
2162 }
2163
2164 void radv_FreeMemory(
2165 VkDevice _device,
2166 VkDeviceMemory _mem,
2167 const VkAllocationCallbacks* pAllocator)
2168 {
2169 RADV_FROM_HANDLE(radv_device, device, _device);
2170 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2171
2172 if (mem == NULL)
2173 return;
2174
2175 device->ws->buffer_destroy(mem->bo);
2176 mem->bo = NULL;
2177
2178 vk_free2(&device->alloc, pAllocator, mem);
2179 }
2180
2181 VkResult radv_MapMemory(
2182 VkDevice _device,
2183 VkDeviceMemory _memory,
2184 VkDeviceSize offset,
2185 VkDeviceSize size,
2186 VkMemoryMapFlags flags,
2187 void** ppData)
2188 {
2189 RADV_FROM_HANDLE(radv_device, device, _device);
2190 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2191
2192 if (mem == NULL) {
2193 *ppData = NULL;
2194 return VK_SUCCESS;
2195 }
2196
2197 *ppData = device->ws->buffer_map(mem->bo);
2198 if (*ppData) {
2199 *ppData += offset;
2200 return VK_SUCCESS;
2201 }
2202
2203 return VK_ERROR_MEMORY_MAP_FAILED;
2204 }
2205
2206 void radv_UnmapMemory(
2207 VkDevice _device,
2208 VkDeviceMemory _memory)
2209 {
2210 RADV_FROM_HANDLE(radv_device, device, _device);
2211 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2212
2213 if (mem == NULL)
2214 return;
2215
2216 device->ws->buffer_unmap(mem->bo);
2217 }
2218
2219 VkResult radv_FlushMappedMemoryRanges(
2220 VkDevice _device,
2221 uint32_t memoryRangeCount,
2222 const VkMappedMemoryRange* pMemoryRanges)
2223 {
2224 return VK_SUCCESS;
2225 }
2226
2227 VkResult radv_InvalidateMappedMemoryRanges(
2228 VkDevice _device,
2229 uint32_t memoryRangeCount,
2230 const VkMappedMemoryRange* pMemoryRanges)
2231 {
2232 return VK_SUCCESS;
2233 }
2234
2235 void radv_GetBufferMemoryRequirements(
2236 VkDevice device,
2237 VkBuffer _buffer,
2238 VkMemoryRequirements* pMemoryRequirements)
2239 {
2240 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2241
2242 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2243
2244 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2245 pMemoryRequirements->alignment = 4096;
2246 else
2247 pMemoryRequirements->alignment = 16;
2248
2249 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2250 }
2251
2252 void radv_GetBufferMemoryRequirements2KHR(
2253 VkDevice device,
2254 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2255 VkMemoryRequirements2KHR* pMemoryRequirements)
2256 {
2257 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2258 &pMemoryRequirements->memoryRequirements);
2259
2260 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2261 switch (ext->sType) {
2262 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2263 VkMemoryDedicatedRequirementsKHR *req =
2264 (VkMemoryDedicatedRequirementsKHR *) ext;
2265 req->requiresDedicatedAllocation = false;
2266 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2267 break;
2268 }
2269 default:
2270 break;
2271 }
2272 }
2273 }
2274
2275 void radv_GetImageMemoryRequirements(
2276 VkDevice device,
2277 VkImage _image,
2278 VkMemoryRequirements* pMemoryRequirements)
2279 {
2280 RADV_FROM_HANDLE(radv_image, image, _image);
2281
2282 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2283
2284 pMemoryRequirements->size = image->size;
2285 pMemoryRequirements->alignment = image->alignment;
2286 }
2287
2288 void radv_GetImageMemoryRequirements2KHR(
2289 VkDevice device,
2290 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2291 VkMemoryRequirements2KHR* pMemoryRequirements)
2292 {
2293 radv_GetImageMemoryRequirements(device, pInfo->image,
2294 &pMemoryRequirements->memoryRequirements);
2295
2296 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2297
2298 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2299 switch (ext->sType) {
2300 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2301 VkMemoryDedicatedRequirementsKHR *req =
2302 (VkMemoryDedicatedRequirementsKHR *) ext;
2303 req->requiresDedicatedAllocation = image->shareable;
2304 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2305 break;
2306 }
2307 default:
2308 break;
2309 }
2310 }
2311 }
2312
2313 void radv_GetImageSparseMemoryRequirements(
2314 VkDevice device,
2315 VkImage image,
2316 uint32_t* pSparseMemoryRequirementCount,
2317 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2318 {
2319 stub();
2320 }
2321
2322 void radv_GetImageSparseMemoryRequirements2KHR(
2323 VkDevice device,
2324 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2325 uint32_t* pSparseMemoryRequirementCount,
2326 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2327 {
2328 stub();
2329 }
2330
2331 void radv_GetDeviceMemoryCommitment(
2332 VkDevice device,
2333 VkDeviceMemory memory,
2334 VkDeviceSize* pCommittedMemoryInBytes)
2335 {
2336 *pCommittedMemoryInBytes = 0;
2337 }
2338
2339 VkResult radv_BindBufferMemory(
2340 VkDevice device,
2341 VkBuffer _buffer,
2342 VkDeviceMemory _memory,
2343 VkDeviceSize memoryOffset)
2344 {
2345 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2346 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2347
2348 if (mem) {
2349 buffer->bo = mem->bo;
2350 buffer->offset = memoryOffset;
2351 } else {
2352 buffer->bo = NULL;
2353 buffer->offset = 0;
2354 }
2355
2356 return VK_SUCCESS;
2357 }
2358
2359 VkResult radv_BindImageMemory(
2360 VkDevice device,
2361 VkImage _image,
2362 VkDeviceMemory _memory,
2363 VkDeviceSize memoryOffset)
2364 {
2365 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2366 RADV_FROM_HANDLE(radv_image, image, _image);
2367
2368 if (mem) {
2369 image->bo = mem->bo;
2370 image->offset = memoryOffset;
2371 } else {
2372 image->bo = NULL;
2373 image->offset = 0;
2374 }
2375
2376 return VK_SUCCESS;
2377 }
2378
2379
2380 static void
2381 radv_sparse_buffer_bind_memory(struct radv_device *device,
2382 const VkSparseBufferMemoryBindInfo *bind)
2383 {
2384 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2385
2386 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2387 struct radv_device_memory *mem = NULL;
2388
2389 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2390 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2391
2392 device->ws->buffer_virtual_bind(buffer->bo,
2393 bind->pBinds[i].resourceOffset,
2394 bind->pBinds[i].size,
2395 mem ? mem->bo : NULL,
2396 bind->pBinds[i].memoryOffset);
2397 }
2398 }
2399
2400 static void
2401 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2402 const VkSparseImageOpaqueMemoryBindInfo *bind)
2403 {
2404 RADV_FROM_HANDLE(radv_image, image, bind->image);
2405
2406 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2407 struct radv_device_memory *mem = NULL;
2408
2409 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2410 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2411
2412 device->ws->buffer_virtual_bind(image->bo,
2413 bind->pBinds[i].resourceOffset,
2414 bind->pBinds[i].size,
2415 mem ? mem->bo : NULL,
2416 bind->pBinds[i].memoryOffset);
2417 }
2418 }
2419
2420 VkResult radv_QueueBindSparse(
2421 VkQueue _queue,
2422 uint32_t bindInfoCount,
2423 const VkBindSparseInfo* pBindInfo,
2424 VkFence _fence)
2425 {
2426 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2427 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2428 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2429 bool fence_emitted = false;
2430
2431 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2432 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2433 radv_sparse_buffer_bind_memory(queue->device,
2434 pBindInfo[i].pBufferBinds + j);
2435 }
2436
2437 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2438 radv_sparse_image_opaque_bind_memory(queue->device,
2439 pBindInfo[i].pImageOpaqueBinds + j);
2440 }
2441
2442 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2443 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2444 &queue->device->empty_cs[queue->queue_family_index],
2445 1, NULL, NULL,
2446 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2447 pBindInfo[i].waitSemaphoreCount,
2448 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2449 pBindInfo[i].signalSemaphoreCount,
2450 false, base_fence);
2451 fence_emitted = true;
2452 if (fence)
2453 fence->submitted = true;
2454 }
2455 }
2456
2457 if (fence && !fence_emitted) {
2458 fence->signalled = true;
2459 }
2460
2461 return VK_SUCCESS;
2462 }
2463
2464 VkResult radv_CreateFence(
2465 VkDevice _device,
2466 const VkFenceCreateInfo* pCreateInfo,
2467 const VkAllocationCallbacks* pAllocator,
2468 VkFence* pFence)
2469 {
2470 RADV_FROM_HANDLE(radv_device, device, _device);
2471 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2472 sizeof(*fence), 8,
2473 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2474
2475 if (!fence)
2476 return VK_ERROR_OUT_OF_HOST_MEMORY;
2477
2478 memset(fence, 0, sizeof(*fence));
2479 fence->submitted = false;
2480 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2481 fence->fence = device->ws->create_fence();
2482 if (!fence->fence) {
2483 vk_free2(&device->alloc, pAllocator, fence);
2484 return VK_ERROR_OUT_OF_HOST_MEMORY;
2485 }
2486
2487 *pFence = radv_fence_to_handle(fence);
2488
2489 return VK_SUCCESS;
2490 }
2491
2492 void radv_DestroyFence(
2493 VkDevice _device,
2494 VkFence _fence,
2495 const VkAllocationCallbacks* pAllocator)
2496 {
2497 RADV_FROM_HANDLE(radv_device, device, _device);
2498 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2499
2500 if (!fence)
2501 return;
2502 device->ws->destroy_fence(fence->fence);
2503 vk_free2(&device->alloc, pAllocator, fence);
2504 }
2505
2506 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2507 {
2508 uint64_t current_time;
2509 struct timespec tv;
2510
2511 clock_gettime(CLOCK_MONOTONIC, &tv);
2512 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2513
2514 timeout = MIN2(UINT64_MAX - current_time, timeout);
2515
2516 return current_time + timeout;
2517 }
2518
2519 VkResult radv_WaitForFences(
2520 VkDevice _device,
2521 uint32_t fenceCount,
2522 const VkFence* pFences,
2523 VkBool32 waitAll,
2524 uint64_t timeout)
2525 {
2526 RADV_FROM_HANDLE(radv_device, device, _device);
2527 timeout = radv_get_absolute_timeout(timeout);
2528
2529 if (!waitAll && fenceCount > 1) {
2530 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2531 }
2532
2533 for (uint32_t i = 0; i < fenceCount; ++i) {
2534 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2535 bool expired = false;
2536
2537 if (fence->signalled)
2538 continue;
2539
2540 if (!fence->submitted)
2541 return VK_TIMEOUT;
2542
2543 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2544 if (!expired)
2545 return VK_TIMEOUT;
2546
2547 fence->signalled = true;
2548 }
2549
2550 return VK_SUCCESS;
2551 }
2552
2553 VkResult radv_ResetFences(VkDevice device,
2554 uint32_t fenceCount,
2555 const VkFence *pFences)
2556 {
2557 for (unsigned i = 0; i < fenceCount; ++i) {
2558 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2559 fence->submitted = fence->signalled = false;
2560 }
2561
2562 return VK_SUCCESS;
2563 }
2564
2565 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2566 {
2567 RADV_FROM_HANDLE(radv_device, device, _device);
2568 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2569
2570 if (fence->signalled)
2571 return VK_SUCCESS;
2572 if (!fence->submitted)
2573 return VK_NOT_READY;
2574
2575 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2576 return VK_NOT_READY;
2577
2578 return VK_SUCCESS;
2579 }
2580
2581
2582 // Queue semaphore functions
2583
2584 VkResult radv_CreateSemaphore(
2585 VkDevice _device,
2586 const VkSemaphoreCreateInfo* pCreateInfo,
2587 const VkAllocationCallbacks* pAllocator,
2588 VkSemaphore* pSemaphore)
2589 {
2590 RADV_FROM_HANDLE(radv_device, device, _device);
2591 struct radeon_winsys_sem *sem;
2592
2593 sem = device->ws->create_sem(device->ws);
2594 if (!sem)
2595 return VK_ERROR_OUT_OF_HOST_MEMORY;
2596
2597 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2598 return VK_SUCCESS;
2599 }
2600
2601 void radv_DestroySemaphore(
2602 VkDevice _device,
2603 VkSemaphore _semaphore,
2604 const VkAllocationCallbacks* pAllocator)
2605 {
2606 RADV_FROM_HANDLE(radv_device, device, _device);
2607 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2608 if (!_semaphore)
2609 return;
2610
2611 device->ws->destroy_sem(sem);
2612 }
2613
2614 VkResult radv_CreateEvent(
2615 VkDevice _device,
2616 const VkEventCreateInfo* pCreateInfo,
2617 const VkAllocationCallbacks* pAllocator,
2618 VkEvent* pEvent)
2619 {
2620 RADV_FROM_HANDLE(radv_device, device, _device);
2621 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2622 sizeof(*event), 8,
2623 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2624
2625 if (!event)
2626 return VK_ERROR_OUT_OF_HOST_MEMORY;
2627
2628 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2629 RADEON_DOMAIN_GTT,
2630 RADEON_FLAG_CPU_ACCESS);
2631 if (!event->bo) {
2632 vk_free2(&device->alloc, pAllocator, event);
2633 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2634 }
2635
2636 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2637
2638 *pEvent = radv_event_to_handle(event);
2639
2640 return VK_SUCCESS;
2641 }
2642
2643 void radv_DestroyEvent(
2644 VkDevice _device,
2645 VkEvent _event,
2646 const VkAllocationCallbacks* pAllocator)
2647 {
2648 RADV_FROM_HANDLE(radv_device, device, _device);
2649 RADV_FROM_HANDLE(radv_event, event, _event);
2650
2651 if (!event)
2652 return;
2653 device->ws->buffer_destroy(event->bo);
2654 vk_free2(&device->alloc, pAllocator, event);
2655 }
2656
2657 VkResult radv_GetEventStatus(
2658 VkDevice _device,
2659 VkEvent _event)
2660 {
2661 RADV_FROM_HANDLE(radv_event, event, _event);
2662
2663 if (*event->map == 1)
2664 return VK_EVENT_SET;
2665 return VK_EVENT_RESET;
2666 }
2667
2668 VkResult radv_SetEvent(
2669 VkDevice _device,
2670 VkEvent _event)
2671 {
2672 RADV_FROM_HANDLE(radv_event, event, _event);
2673 *event->map = 1;
2674
2675 return VK_SUCCESS;
2676 }
2677
2678 VkResult radv_ResetEvent(
2679 VkDevice _device,
2680 VkEvent _event)
2681 {
2682 RADV_FROM_HANDLE(radv_event, event, _event);
2683 *event->map = 0;
2684
2685 return VK_SUCCESS;
2686 }
2687
2688 VkResult radv_CreateBuffer(
2689 VkDevice _device,
2690 const VkBufferCreateInfo* pCreateInfo,
2691 const VkAllocationCallbacks* pAllocator,
2692 VkBuffer* pBuffer)
2693 {
2694 RADV_FROM_HANDLE(radv_device, device, _device);
2695 struct radv_buffer *buffer;
2696
2697 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2698
2699 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2700 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2701 if (buffer == NULL)
2702 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2703
2704 buffer->size = pCreateInfo->size;
2705 buffer->usage = pCreateInfo->usage;
2706 buffer->bo = NULL;
2707 buffer->offset = 0;
2708 buffer->flags = pCreateInfo->flags;
2709
2710 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2711 buffer->bo = device->ws->buffer_create(device->ws,
2712 align64(buffer->size, 4096),
2713 4096, 0, RADEON_FLAG_VIRTUAL);
2714 if (!buffer->bo) {
2715 vk_free2(&device->alloc, pAllocator, buffer);
2716 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2717 }
2718 }
2719
2720 *pBuffer = radv_buffer_to_handle(buffer);
2721
2722 return VK_SUCCESS;
2723 }
2724
2725 void radv_DestroyBuffer(
2726 VkDevice _device,
2727 VkBuffer _buffer,
2728 const VkAllocationCallbacks* pAllocator)
2729 {
2730 RADV_FROM_HANDLE(radv_device, device, _device);
2731 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2732
2733 if (!buffer)
2734 return;
2735
2736 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2737 device->ws->buffer_destroy(buffer->bo);
2738
2739 vk_free2(&device->alloc, pAllocator, buffer);
2740 }
2741
2742 static inline unsigned
2743 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2744 {
2745 if (stencil)
2746 return image->surface.u.legacy.stencil_tiling_index[level];
2747 else
2748 return image->surface.u.legacy.tiling_index[level];
2749 }
2750
2751 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2752 {
2753 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2754 }
2755
2756 static void
2757 radv_initialise_color_surface(struct radv_device *device,
2758 struct radv_color_buffer_info *cb,
2759 struct radv_image_view *iview)
2760 {
2761 const struct vk_format_description *desc;
2762 unsigned ntype, format, swap, endian;
2763 unsigned blend_clamp = 0, blend_bypass = 0;
2764 uint64_t va;
2765 const struct radeon_surf *surf = &iview->image->surface;
2766
2767 desc = vk_format_description(iview->vk_format);
2768
2769 memset(cb, 0, sizeof(*cb));
2770
2771 /* Intensity is implemented as Red, so treat it that way. */
2772 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2773
2774 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2775
2776 if (device->physical_device->rad_info.chip_class >= GFX9) {
2777 struct gfx9_surf_meta_flags meta;
2778 if (iview->image->dcc_offset)
2779 meta = iview->image->surface.u.gfx9.dcc;
2780 else
2781 meta = iview->image->surface.u.gfx9.cmask;
2782
2783 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2784 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2785 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2786 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2787
2788 va += iview->image->surface.u.gfx9.surf_offset >> 8;
2789 } else {
2790 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2791 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2792
2793 va += level_info->offset;
2794
2795 pitch_tile_max = level_info->nblk_x / 8 - 1;
2796 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2797 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2798
2799 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2800 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2801 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2802
2803 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2804 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2805
2806 if (iview->image->fmask.size) {
2807 if (device->physical_device->rad_info.chip_class >= CIK)
2808 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2809 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2810 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2811 } else {
2812 /* This must be set for fast clear to work without FMASK. */
2813 if (device->physical_device->rad_info.chip_class >= CIK)
2814 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2815 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2816 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2817 }
2818 }
2819
2820 cb->cb_color_base = va >> 8;
2821 if (device->physical_device->rad_info.chip_class < GFX9)
2822 cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
2823 /* CMASK variables */
2824 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2825 va += iview->image->cmask.offset;
2826 cb->cb_color_cmask = va >> 8;
2827
2828 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2829 va += iview->image->dcc_offset;
2830 cb->cb_dcc_base = va >> 8;
2831 if (device->physical_device->rad_info.chip_class < GFX9)
2832 cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
2833
2834 uint32_t max_slice = radv_surface_layer_count(iview);
2835 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2836 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2837
2838 if (iview->image->info.samples > 1) {
2839 unsigned log_samples = util_logbase2(iview->image->info.samples);
2840
2841 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2842 S_028C74_NUM_FRAGMENTS(log_samples);
2843 }
2844
2845 if (iview->image->fmask.size) {
2846 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2847 cb->cb_color_fmask = va >> 8;
2848 if (device->physical_device->rad_info.chip_class < GFX9)
2849 cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
2850 } else {
2851 cb->cb_color_fmask = cb->cb_color_base;
2852 }
2853
2854 ntype = radv_translate_color_numformat(iview->vk_format,
2855 desc,
2856 vk_format_get_first_non_void_channel(iview->vk_format));
2857 format = radv_translate_colorformat(iview->vk_format);
2858 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2859 radv_finishme("Illegal color\n");
2860 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2861 endian = radv_colorformat_endian_swap(format);
2862
2863 /* blend clamp should be set for all NORM/SRGB types */
2864 if (ntype == V_028C70_NUMBER_UNORM ||
2865 ntype == V_028C70_NUMBER_SNORM ||
2866 ntype == V_028C70_NUMBER_SRGB)
2867 blend_clamp = 1;
2868
2869 /* set blend bypass according to docs if SINT/UINT or
2870 8/24 COLOR variants */
2871 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2872 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2873 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2874 blend_clamp = 0;
2875 blend_bypass = 1;
2876 }
2877 #if 0
2878 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2879 (format == V_028C70_COLOR_8 ||
2880 format == V_028C70_COLOR_8_8 ||
2881 format == V_028C70_COLOR_8_8_8_8))
2882 ->color_is_int8 = true;
2883 #endif
2884 cb->cb_color_info = S_028C70_FORMAT(format) |
2885 S_028C70_COMP_SWAP(swap) |
2886 S_028C70_BLEND_CLAMP(blend_clamp) |
2887 S_028C70_BLEND_BYPASS(blend_bypass) |
2888 S_028C70_SIMPLE_FLOAT(1) |
2889 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2890 ntype != V_028C70_NUMBER_SNORM &&
2891 ntype != V_028C70_NUMBER_SRGB &&
2892 format != V_028C70_COLOR_8_24 &&
2893 format != V_028C70_COLOR_24_8) |
2894 S_028C70_NUMBER_TYPE(ntype) |
2895 S_028C70_ENDIAN(endian);
2896 if (iview->image->info.samples > 1)
2897 if (iview->image->fmask.size)
2898 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2899
2900 if (iview->image->cmask.size &&
2901 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2902 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2903
2904 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
2905 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2906
2907 if (device->physical_device->rad_info.chip_class >= VI) {
2908 unsigned max_uncompressed_block_size = 2;
2909 if (iview->image->info.samples > 1) {
2910 if (iview->image->surface.bpe == 1)
2911 max_uncompressed_block_size = 0;
2912 else if (iview->image->surface.bpe == 2)
2913 max_uncompressed_block_size = 1;
2914 }
2915
2916 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2917 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2918 }
2919
2920 /* This must be set for fast clear to work without FMASK. */
2921 if (!iview->image->fmask.size &&
2922 device->physical_device->rad_info.chip_class == SI) {
2923 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
2924 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2925 }
2926
2927 if (device->physical_device->rad_info.chip_class >= GFX9) {
2928 uint32_t max_slice = radv_surface_layer_count(iview);
2929 unsigned mip0_depth = iview->base_layer + max_slice - 1;
2930
2931 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
2932 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2933 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
2934 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
2935 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
2936 S_028C68_MAX_MIP(iview->image->info.levels);
2937
2938 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
2939
2940 }
2941 }
2942
2943 static void
2944 radv_initialise_ds_surface(struct radv_device *device,
2945 struct radv_ds_buffer_info *ds,
2946 struct radv_image_view *iview)
2947 {
2948 unsigned level = iview->base_mip;
2949 unsigned format, stencil_format;
2950 uint64_t va, s_offs, z_offs;
2951 bool stencil_only = false;
2952 memset(ds, 0, sizeof(*ds));
2953 switch (iview->image->vk_format) {
2954 case VK_FORMAT_D24_UNORM_S8_UINT:
2955 case VK_FORMAT_X8_D24_UNORM_PACK32:
2956 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2957 ds->offset_scale = 2.0f;
2958 break;
2959 case VK_FORMAT_D16_UNORM:
2960 case VK_FORMAT_D16_UNORM_S8_UINT:
2961 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2962 ds->offset_scale = 4.0f;
2963 break;
2964 case VK_FORMAT_D32_SFLOAT:
2965 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2966 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2967 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2968 ds->offset_scale = 1.0f;
2969 break;
2970 case VK_FORMAT_S8_UINT:
2971 stencil_only = true;
2972 break;
2973 default:
2974 break;
2975 }
2976
2977 format = radv_translate_dbformat(iview->image->vk_format);
2978 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
2979 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2980
2981 uint32_t max_slice = radv_surface_layer_count(iview);
2982 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2983 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2984
2985 ds->db_htile_data_base = 0;
2986 ds->db_htile_surface = 0;
2987
2988 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2989 s_offs = z_offs = va;
2990
2991 if (device->physical_device->rad_info.chip_class >= GFX9) {
2992 assert(iview->image->surface.u.gfx9.surf_offset == 0);
2993 s_offs += iview->image->surface.u.gfx9.stencil_offset;
2994
2995 ds->db_z_info = S_028038_FORMAT(format) |
2996 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
2997 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2998 S_028038_MAXMIP(iview->image->info.levels - 1);
2999 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3000 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3001
3002 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3003 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3004 ds->db_depth_view |= S_028008_MIPID(level);
3005
3006 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3007 S_02801C_Y_MAX(iview->image->info.height - 1);
3008
3009 /* Only use HTILE for the first level. */
3010 if (iview->image->surface.htile_size && !level) {
3011 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3012
3013 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3014 /* Use all of the htile_buffer for depth if there's no stencil. */
3015 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3016 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3017 iview->image->htile_offset;
3018 ds->db_htile_data_base = va >> 8;
3019 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3020 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3021 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3022 }
3023 } else {
3024 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3025
3026 if (stencil_only)
3027 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3028
3029 z_offs += iview->image->surface.u.legacy.level[level].offset;
3030 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3031
3032 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3033 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3034 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3035
3036 if (iview->image->info.samples > 1)
3037 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3038
3039 if (device->physical_device->rad_info.chip_class >= CIK) {
3040 struct radeon_info *info = &device->physical_device->rad_info;
3041 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3042 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3043 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3044 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3045 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3046 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3047
3048 if (stencil_only)
3049 tile_mode = stencil_tile_mode;
3050
3051 ds->db_depth_info |=
3052 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3053 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3054 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3055 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3056 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3057 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3058 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3059 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3060 } else {
3061 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3062 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3063 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3064 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3065 }
3066
3067 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3068 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3069 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3070
3071 if (iview->image->surface.htile_size && !level) {
3072 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3073
3074 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3075 /* Use all of the htile_buffer for depth if there's no stencil. */
3076 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3077
3078 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3079 iview->image->htile_offset;
3080 ds->db_htile_data_base = va >> 8;
3081 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3082 }
3083 }
3084
3085 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3086 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3087 }
3088
3089 VkResult radv_CreateFramebuffer(
3090 VkDevice _device,
3091 const VkFramebufferCreateInfo* pCreateInfo,
3092 const VkAllocationCallbacks* pAllocator,
3093 VkFramebuffer* pFramebuffer)
3094 {
3095 RADV_FROM_HANDLE(radv_device, device, _device);
3096 struct radv_framebuffer *framebuffer;
3097
3098 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3099
3100 size_t size = sizeof(*framebuffer) +
3101 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3102 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3103 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3104 if (framebuffer == NULL)
3105 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3106
3107 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3108 framebuffer->width = pCreateInfo->width;
3109 framebuffer->height = pCreateInfo->height;
3110 framebuffer->layers = pCreateInfo->layers;
3111 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3112 VkImageView _iview = pCreateInfo->pAttachments[i];
3113 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3114 framebuffer->attachments[i].attachment = iview;
3115 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3116 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3117 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3118 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3119 }
3120 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3121 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3122 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3123 }
3124
3125 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3126 return VK_SUCCESS;
3127 }
3128
3129 void radv_DestroyFramebuffer(
3130 VkDevice _device,
3131 VkFramebuffer _fb,
3132 const VkAllocationCallbacks* pAllocator)
3133 {
3134 RADV_FROM_HANDLE(radv_device, device, _device);
3135 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3136
3137 if (!fb)
3138 return;
3139 vk_free2(&device->alloc, pAllocator, fb);
3140 }
3141
3142 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3143 {
3144 switch (address_mode) {
3145 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3146 return V_008F30_SQ_TEX_WRAP;
3147 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3148 return V_008F30_SQ_TEX_MIRROR;
3149 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3150 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3151 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3152 return V_008F30_SQ_TEX_CLAMP_BORDER;
3153 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3154 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3155 default:
3156 unreachable("illegal tex wrap mode");
3157 break;
3158 }
3159 }
3160
3161 static unsigned
3162 radv_tex_compare(VkCompareOp op)
3163 {
3164 switch (op) {
3165 case VK_COMPARE_OP_NEVER:
3166 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3167 case VK_COMPARE_OP_LESS:
3168 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3169 case VK_COMPARE_OP_EQUAL:
3170 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3171 case VK_COMPARE_OP_LESS_OR_EQUAL:
3172 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3173 case VK_COMPARE_OP_GREATER:
3174 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3175 case VK_COMPARE_OP_NOT_EQUAL:
3176 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3177 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3178 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3179 case VK_COMPARE_OP_ALWAYS:
3180 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3181 default:
3182 unreachable("illegal compare mode");
3183 break;
3184 }
3185 }
3186
3187 static unsigned
3188 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3189 {
3190 switch (filter) {
3191 case VK_FILTER_NEAREST:
3192 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3193 V_008F38_SQ_TEX_XY_FILTER_POINT);
3194 case VK_FILTER_LINEAR:
3195 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3196 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3197 case VK_FILTER_CUBIC_IMG:
3198 default:
3199 fprintf(stderr, "illegal texture filter");
3200 return 0;
3201 }
3202 }
3203
3204 static unsigned
3205 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3206 {
3207 switch (mode) {
3208 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3209 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3210 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3211 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3212 default:
3213 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3214 }
3215 }
3216
3217 static unsigned
3218 radv_tex_bordercolor(VkBorderColor bcolor)
3219 {
3220 switch (bcolor) {
3221 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3222 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3223 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3224 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3225 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3226 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3227 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3228 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3229 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3230 default:
3231 break;
3232 }
3233 return 0;
3234 }
3235
3236 static unsigned
3237 radv_tex_aniso_filter(unsigned filter)
3238 {
3239 if (filter < 2)
3240 return 0;
3241 if (filter < 4)
3242 return 1;
3243 if (filter < 8)
3244 return 2;
3245 if (filter < 16)
3246 return 3;
3247 return 4;
3248 }
3249
3250 static void
3251 radv_init_sampler(struct radv_device *device,
3252 struct radv_sampler *sampler,
3253 const VkSamplerCreateInfo *pCreateInfo)
3254 {
3255 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3256 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3257 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3258 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3259
3260 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3261 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3262 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3263 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3264 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3265 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3266 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3267 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3268 S_008F30_DISABLE_CUBE_WRAP(0) |
3269 S_008F30_COMPAT_MODE(is_vi));
3270 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3271 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3272 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3273 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3274 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3275 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3276 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3277 S_008F38_MIP_POINT_PRECLAMP(0) |
3278 S_008F38_DISABLE_LSB_CEIL(1) |
3279 S_008F38_FILTER_PREC_FIX(1) |
3280 S_008F38_ANISO_OVERRIDE(is_vi));
3281 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3282 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3283 }
3284
3285 VkResult radv_CreateSampler(
3286 VkDevice _device,
3287 const VkSamplerCreateInfo* pCreateInfo,
3288 const VkAllocationCallbacks* pAllocator,
3289 VkSampler* pSampler)
3290 {
3291 RADV_FROM_HANDLE(radv_device, device, _device);
3292 struct radv_sampler *sampler;
3293
3294 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3295
3296 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3297 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3298 if (!sampler)
3299 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3300
3301 radv_init_sampler(device, sampler, pCreateInfo);
3302 *pSampler = radv_sampler_to_handle(sampler);
3303
3304 return VK_SUCCESS;
3305 }
3306
3307 void radv_DestroySampler(
3308 VkDevice _device,
3309 VkSampler _sampler,
3310 const VkAllocationCallbacks* pAllocator)
3311 {
3312 RADV_FROM_HANDLE(radv_device, device, _device);
3313 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3314
3315 if (!sampler)
3316 return;
3317 vk_free2(&device->alloc, pAllocator, sampler);
3318 }
3319
3320 /* vk_icd.h does not declare this function, so we declare it here to
3321 * suppress Wmissing-prototypes.
3322 */
3323 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3324 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3325
3326 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3327 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3328 {
3329 /* For the full details on loader interface versioning, see
3330 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3331 * What follows is a condensed summary, to help you navigate the large and
3332 * confusing official doc.
3333 *
3334 * - Loader interface v0 is incompatible with later versions. We don't
3335 * support it.
3336 *
3337 * - In loader interface v1:
3338 * - The first ICD entrypoint called by the loader is
3339 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3340 * entrypoint.
3341 * - The ICD must statically expose no other Vulkan symbol unless it is
3342 * linked with -Bsymbolic.
3343 * - Each dispatchable Vulkan handle created by the ICD must be
3344 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3345 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3346 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3347 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3348 * such loader-managed surfaces.
3349 *
3350 * - Loader interface v2 differs from v1 in:
3351 * - The first ICD entrypoint called by the loader is
3352 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3353 * statically expose this entrypoint.
3354 *
3355 * - Loader interface v3 differs from v2 in:
3356 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3357 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3358 * because the loader no longer does so.
3359 */
3360 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3361 return VK_SUCCESS;
3362 }
3363
3364 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3365 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3366 int *pFD)
3367 {
3368 RADV_FROM_HANDLE(radv_device, device, _device);
3369 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3370
3371 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3372
3373 /* We support only one handle type. */
3374 assert(pGetFdInfo->handleType ==
3375 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3376
3377 bool ret = radv_get_memory_fd(device, memory, pFD);
3378 if (ret == false)
3379 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3380 return VK_SUCCESS;
3381 }
3382
3383 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3384 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3385 int fd,
3386 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3387 {
3388 /* The valid usage section for this function says:
3389 *
3390 * "handleType must not be one of the handle types defined as opaque."
3391 *
3392 * Since we only handle opaque handles for now, there are no FD properties.
3393 */
3394 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3395 }