2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
55 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
58 unsigned char sha1
[20];
59 unsigned ptr_size
= sizeof(void*);
61 memset(uuid
, 0, VK_UUID_SIZE
);
62 _mesa_sha1_init(&ctx
);
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
68 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
69 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
70 _mesa_sha1_final(&ctx
, sha1
);
72 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
77 radv_get_driver_uuid(void *uuid
)
79 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
83 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
85 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
89 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
91 const char *chip_string
;
94 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
98 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
101 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
102 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS
: chip_string
= "AMD RADV MULLINS"; break;
104 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
105 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
112 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
115 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
117 default: chip_string
= "AMD RADV unknown"; break;
120 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
124 radv_get_visible_vram_size(struct radv_physical_device
*device
)
126 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
130 radv_get_vram_size(struct radv_physical_device
*device
)
132 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
136 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
139 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
140 uint64_t vram_size
= radv_get_vram_size(device
);
141 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
142 device
->memory_properties
.memoryHeapCount
= 0;
144 vram_index
= device
->memory_properties
.memoryHeapCount
++;
145 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
147 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
150 if (visible_vram_size
) {
151 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
152 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
153 .size
= visible_vram_size
,
154 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
157 if (device
->rad_info
.gart_size
> 0) {
158 gart_index
= device
->memory_properties
.memoryHeapCount
++;
159 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
160 .size
= device
->rad_info
.gart_size
,
161 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
166 unsigned type_count
= 0;
167 if (vram_index
>= 0) {
168 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
169 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
170 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
171 .heapIndex
= vram_index
,
174 if (gart_index
>= 0) {
175 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
176 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
177 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
179 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
180 .heapIndex
= gart_index
,
183 if (visible_vram_index
>= 0) {
184 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
185 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
186 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
189 .heapIndex
= visible_vram_index
,
192 if (gart_index
>= 0) {
193 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
194 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
195 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
198 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
199 .heapIndex
= gart_index
,
202 device
->memory_properties
.memoryTypeCount
= type_count
;
206 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
208 const char *family
= getenv("RADV_FORCE_FAMILY");
214 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
215 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
216 /* Override family and chip_class. */
217 device
->rad_info
.family
= i
;
219 if (i
>= CHIP_VEGA10
)
220 device
->rad_info
.chip_class
= GFX9
;
221 else if (i
>= CHIP_TONGA
)
222 device
->rad_info
.chip_class
= VI
;
223 else if (i
>= CHIP_BONAIRE
)
224 device
->rad_info
.chip_class
= CIK
;
226 device
->rad_info
.chip_class
= SI
;
232 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
237 radv_physical_device_init(struct radv_physical_device
*device
,
238 struct radv_instance
*instance
,
239 drmDevicePtr drm_device
)
241 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
243 drmVersionPtr version
;
247 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
249 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
250 radv_logi("Could not open device '%s'", path
);
252 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
255 version
= drmGetVersion(fd
);
259 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
260 radv_logi("Could not get the kernel driver version for device '%s'", path
);
262 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
263 "failed to get version %s: %m", path
);
266 if (strcmp(version
->name
, "amdgpu")) {
267 drmFreeVersion(version
);
270 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
273 return VK_ERROR_INCOMPATIBLE_DRIVER
;
275 drmFreeVersion(version
);
277 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
278 radv_logi("Found compatible device '%s'.", path
);
280 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
281 device
->instance
= instance
;
283 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
284 instance
->perftest_flags
);
286 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
290 if (instance
->enabled_extensions
.KHR_display
) {
291 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
292 if (master_fd
>= 0) {
293 uint32_t accel_working
= 0;
294 struct drm_amdgpu_info request
= {
295 .return_pointer
= (uintptr_t)&accel_working
,
296 .return_size
= sizeof(accel_working
),
297 .query
= AMDGPU_INFO_ACCEL_WORKING
300 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
307 device
->master_fd
= master_fd
;
308 device
->local_fd
= fd
;
309 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
311 radv_handle_env_var_force_family(device
);
313 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
315 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
316 device
->ws
->destroy(device
->ws
);
317 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
318 "cannot generate UUID");
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags
=
324 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
325 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
330 char buf
[VK_UUID_SIZE
* 2 + 1];
331 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
332 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
334 if (device
->rad_info
.chip_class
< VI
||
335 device
->rad_info
.chip_class
> GFX9
)
336 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338 radv_get_driver_uuid(&device
->driver_uuid
);
339 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
341 if (device
->rad_info
.family
== CHIP_STONEY
||
342 device
->rad_info
.chip_class
>= GFX9
) {
343 device
->has_rbplus
= true;
344 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
345 device
->rad_info
.family
== CHIP_VEGA12
||
346 device
->rad_info
.family
== CHIP_RAVEN
||
347 device
->rad_info
.family
== CHIP_RAVEN2
;
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 device
->has_clear_state
= device
->rad_info
.chip_class
>= CIK
;
355 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= VI
;
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
359 device
->rad_info
.family
== CHIP_RAVEN
;
361 /* Out-of-order primitive rasterization. */
362 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= VI
&&
363 device
->rad_info
.max_se
>= 2;
364 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
365 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
367 device
->dcc_msaa_allowed
=
368 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
371 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
372 (device
->rad_info
.chip_class
>= VI
&&
373 device
->rad_info
.me_fw_feature
>= 41);
375 radv_physical_device_init_mem_types(device
);
376 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
378 device
->bus_info
= *drm_device
->businfo
.pci
;
380 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
381 ac_print_gpu_info(&device
->rad_info
);
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
387 result
= radv_init_wsi(device
);
388 if (result
!= VK_SUCCESS
) {
389 device
->ws
->destroy(device
->ws
);
390 vk_error(instance
, result
);
404 radv_physical_device_finish(struct radv_physical_device
*device
)
406 radv_finish_wsi(device
);
407 device
->ws
->destroy(device
->ws
);
408 disk_cache_destroy(device
->disk_cache
);
409 close(device
->local_fd
);
410 if (device
->master_fd
!= -1)
411 close(device
->master_fd
);
415 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
416 VkSystemAllocationScope allocationScope
)
422 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
423 size_t align
, VkSystemAllocationScope allocationScope
)
425 return realloc(pOriginal
, size
);
429 default_free_func(void *pUserData
, void *pMemory
)
434 static const VkAllocationCallbacks default_alloc
= {
436 .pfnAllocation
= default_alloc_func
,
437 .pfnReallocation
= default_realloc_func
,
438 .pfnFree
= default_free_func
,
441 static const struct debug_control radv_debug_options
[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
443 {"nodcc", RADV_DEBUG_NO_DCC
},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
445 {"nocache", RADV_DEBUG_NO_CACHE
},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
447 {"nohiz", RADV_DEBUG_NO_HIZ
},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
450 {"allbos", RADV_DEBUG_ALL_BOS
},
451 {"noibs", RADV_DEBUG_NO_IBS
},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
456 {"nosisched", RADV_DEBUG_NO_SISCHED
},
457 {"preoptir", RADV_DEBUG_PREOPTIR
},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
460 {"info", RADV_DEBUG_INFO
},
461 {"errors", RADV_DEBUG_ERRORS
},
462 {"startup", RADV_DEBUG_STARTUP
},
463 {"checkir", RADV_DEBUG_CHECKIR
},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
465 {"nobinning", RADV_DEBUG_NOBINNING
},
470 radv_get_debug_option_name(int id
)
472 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
473 return radv_debug_options
[id
].string
;
476 static const struct debug_control radv_perftest_options
[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
478 {"sisched", RADV_PERFTEST_SISCHED
},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
481 {"bolist", RADV_PERFTEST_BO_LIST
},
486 radv_get_perftest_option_name(int id
)
488 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
489 return radv_perftest_options
[id
].string
;
493 radv_handle_per_app_options(struct radv_instance
*instance
,
494 const VkApplicationInfo
*info
)
496 const char *name
= info
? info
->pApplicationName
: NULL
;
501 if (!strcmp(name
, "Talos - Linux - 32bit") ||
502 !strcmp(name
, "Talos - Linux - 64bit")) {
503 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
507 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
509 } else if (!strcmp(name
, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
515 static int radv_get_instance_extension_index(const char *name
)
517 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
518 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
524 static const char radv_dri_options_xml
[] =
528 static void radv_init_dri_options(struct radv_instance
*instance
)
530 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
531 driParseConfigFiles(&instance
->dri_options
,
532 &instance
->available_dri_options
,
536 VkResult
radv_CreateInstance(
537 const VkInstanceCreateInfo
* pCreateInfo
,
538 const VkAllocationCallbacks
* pAllocator
,
539 VkInstance
* pInstance
)
541 struct radv_instance
*instance
;
544 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
546 uint32_t client_version
;
547 if (pCreateInfo
->pApplicationInfo
&&
548 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
549 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
551 client_version
= VK_API_VERSION_1_0
;
554 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
555 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
557 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
559 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
562 instance
->alloc
= *pAllocator
;
564 instance
->alloc
= default_alloc
;
566 instance
->apiVersion
= client_version
;
567 instance
->physicalDeviceCount
= -1;
569 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
572 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
573 radv_perftest_options
);
576 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
577 radv_logi("Created an instance");
579 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
580 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
581 int index
= radv_get_instance_extension_index(ext_name
);
583 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
584 vk_free2(&default_alloc
, pAllocator
, instance
);
585 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
588 instance
->enabled_extensions
.extensions
[index
] = true;
591 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
592 if (result
!= VK_SUCCESS
) {
593 vk_free2(&default_alloc
, pAllocator
, instance
);
594 return vk_error(instance
, result
);
598 glsl_type_singleton_init_or_ref();
600 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
602 radv_init_dri_options(instance
);
603 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
605 *pInstance
= radv_instance_to_handle(instance
);
610 void radv_DestroyInstance(
611 VkInstance _instance
,
612 const VkAllocationCallbacks
* pAllocator
)
614 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
619 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
620 radv_physical_device_finish(instance
->physicalDevices
+ i
);
623 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
625 glsl_type_singleton_decref();
628 driDestroyOptionCache(&instance
->dri_options
);
629 driDestroyOptionInfo(&instance
->available_dri_options
);
631 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
633 vk_free(&instance
->alloc
, instance
);
637 radv_enumerate_devices(struct radv_instance
*instance
)
639 /* TODO: Check for more devices ? */
640 drmDevicePtr devices
[8];
641 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
644 instance
->physicalDeviceCount
= 0;
646 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
648 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
649 radv_logi("Found %d drm nodes", max_devices
);
652 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
654 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
655 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
656 devices
[i
]->bustype
== DRM_BUS_PCI
&&
657 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
659 result
= radv_physical_device_init(instance
->physicalDevices
+
660 instance
->physicalDeviceCount
,
663 if (result
== VK_SUCCESS
)
664 ++instance
->physicalDeviceCount
;
665 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
669 drmFreeDevices(devices
, max_devices
);
674 VkResult
radv_EnumeratePhysicalDevices(
675 VkInstance _instance
,
676 uint32_t* pPhysicalDeviceCount
,
677 VkPhysicalDevice
* pPhysicalDevices
)
679 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
682 if (instance
->physicalDeviceCount
< 0) {
683 result
= radv_enumerate_devices(instance
);
684 if (result
!= VK_SUCCESS
&&
685 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
689 if (!pPhysicalDevices
) {
690 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
692 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
693 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
694 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
697 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
701 VkResult
radv_EnumeratePhysicalDeviceGroups(
702 VkInstance _instance
,
703 uint32_t* pPhysicalDeviceGroupCount
,
704 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
706 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
709 if (instance
->physicalDeviceCount
< 0) {
710 result
= radv_enumerate_devices(instance
);
711 if (result
!= VK_SUCCESS
&&
712 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
716 if (!pPhysicalDeviceGroupProperties
) {
717 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
719 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
720 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
721 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
722 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
723 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
726 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
730 void radv_GetPhysicalDeviceFeatures(
731 VkPhysicalDevice physicalDevice
,
732 VkPhysicalDeviceFeatures
* pFeatures
)
734 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
735 memset(pFeatures
, 0, sizeof(*pFeatures
));
737 *pFeatures
= (VkPhysicalDeviceFeatures
) {
738 .robustBufferAccess
= true,
739 .fullDrawIndexUint32
= true,
740 .imageCubeArray
= true,
741 .independentBlend
= true,
742 .geometryShader
= true,
743 .tessellationShader
= true,
744 .sampleRateShading
= true,
745 .dualSrcBlend
= true,
747 .multiDrawIndirect
= true,
748 .drawIndirectFirstInstance
= true,
750 .depthBiasClamp
= true,
751 .fillModeNonSolid
= true,
756 .multiViewport
= true,
757 .samplerAnisotropy
= true,
758 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
759 .textureCompressionASTC_LDR
= false,
760 .textureCompressionBC
= true,
761 .occlusionQueryPrecise
= true,
762 .pipelineStatisticsQuery
= true,
763 .vertexPipelineStoresAndAtomics
= true,
764 .fragmentStoresAndAtomics
= true,
765 .shaderTessellationAndGeometryPointSize
= true,
766 .shaderImageGatherExtended
= true,
767 .shaderStorageImageExtendedFormats
= true,
768 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= VI
,
769 .shaderUniformBufferArrayDynamicIndexing
= true,
770 .shaderSampledImageArrayDynamicIndexing
= true,
771 .shaderStorageBufferArrayDynamicIndexing
= true,
772 .shaderStorageImageArrayDynamicIndexing
= true,
773 .shaderStorageImageReadWithoutFormat
= true,
774 .shaderStorageImageWriteWithoutFormat
= true,
775 .shaderClipDistance
= true,
776 .shaderCullDistance
= true,
777 .shaderFloat64
= true,
779 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
780 .sparseBinding
= true,
781 .variableMultisampleRate
= true,
782 .inheritedQueries
= true,
786 void radv_GetPhysicalDeviceFeatures2(
787 VkPhysicalDevice physicalDevice
,
788 VkPhysicalDeviceFeatures2
*pFeatures
)
790 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
791 vk_foreach_struct(ext
, pFeatures
->pNext
) {
792 switch (ext
->sType
) {
793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES
: {
794 VkPhysicalDeviceVariablePointerFeatures
*features
= (void *)ext
;
795 features
->variablePointersStorageBuffer
= true;
796 features
->variablePointers
= true;
799 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
800 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
801 features
->multiview
= true;
802 features
->multiviewGeometryShader
= true;
803 features
->multiviewTessellationShader
= true;
806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES
: {
807 VkPhysicalDeviceShaderDrawParameterFeatures
*features
=
808 (VkPhysicalDeviceShaderDrawParameterFeatures
*)ext
;
809 features
->shaderDrawParameters
= true;
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
813 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
814 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
815 features
->protectedMemory
= false;
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
819 VkPhysicalDevice16BitStorageFeatures
*features
=
820 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
821 bool enabled
= pdevice
->rad_info
.chip_class
>= VI
;
822 features
->storageBuffer16BitAccess
= enabled
;
823 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
824 features
->storagePushConstant16
= enabled
;
825 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
829 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
830 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
831 features
->samplerYcbcrConversion
= false;
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
835 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
836 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
837 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
838 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
839 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
840 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
841 features
->shaderSampledImageArrayNonUniformIndexing
= true;
842 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
843 features
->shaderStorageImageArrayNonUniformIndexing
= true;
844 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
845 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
846 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
847 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
848 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
849 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
850 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
851 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
852 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
853 features
->descriptorBindingUpdateUnusedWhilePending
= true;
854 features
->descriptorBindingPartiallyBound
= true;
855 features
->descriptorBindingVariableDescriptorCount
= true;
856 features
->runtimeDescriptorArray
= true;
859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
860 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
861 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
862 features
->conditionalRendering
= true;
863 features
->inheritedConditionalRendering
= false;
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
867 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
868 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
869 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
870 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
874 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
875 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
876 features
->transformFeedback
= true;
877 features
->geometryStreams
= true;
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
881 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
882 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
883 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= CIK
;
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
887 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
888 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
889 features
->memoryPriority
= VK_TRUE
;
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT
: {
893 VkPhysicalDeviceBufferAddressFeaturesEXT
*features
=
894 (VkPhysicalDeviceBufferAddressFeaturesEXT
*)ext
;
895 features
->bufferDeviceAddress
= true;
896 features
->bufferDeviceAddressCaptureReplay
= false;
897 features
->bufferDeviceAddressMultiDevice
= false;
900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
901 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
902 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
903 features
->depthClipEnable
= true;
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
907 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
908 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
909 features
->hostQueryReset
= true;
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
913 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
914 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
915 bool enabled
= pdevice
->rad_info
.chip_class
>= VI
;
916 features
->storageBuffer8BitAccess
= enabled
;
917 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
918 features
->storagePushConstant8
= enabled
;
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
922 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
923 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
924 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= VI
&& HAVE_LLVM
>= 0x0800;
925 features
->shaderInt8
= true;
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
929 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
930 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
931 /* TODO: Enable this once the driver supports 64-bit
932 * compare&swap atomic operations.
934 features
->shaderBufferInt64Atomics
= false;
935 features
->shaderSharedInt64Atomics
= false;
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
939 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
940 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
942 features
->inlineUniformBlock
= true;
943 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
947 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
948 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
949 features
->computeDerivativeGroupQuads
= false;
950 features
->computeDerivativeGroupLinear
= true;
957 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
960 void radv_GetPhysicalDeviceProperties(
961 VkPhysicalDevice physicalDevice
,
962 VkPhysicalDeviceProperties
* pProperties
)
964 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
965 VkSampleCountFlags sample_counts
= 0xf;
967 /* make sure that the entire descriptor set is addressable with a signed
968 * 32-bit int. So the sum of all limits scaled by descriptor size has to
969 * be at most 2 GiB. the combined image & samples object count as one of
970 * both. This limit is for the pipeline layout, not for the set layout, but
971 * there is no set limit, so we just set a pipeline limit. I don't think
972 * any app is going to hit this soon. */
973 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
974 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
975 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
976 32 /* sampler, largest when combined with image */ +
977 64 /* sampled image */ +
978 64 /* storage image */);
980 VkPhysicalDeviceLimits limits
= {
981 .maxImageDimension1D
= (1 << 14),
982 .maxImageDimension2D
= (1 << 14),
983 .maxImageDimension3D
= (1 << 11),
984 .maxImageDimensionCube
= (1 << 14),
985 .maxImageArrayLayers
= (1 << 11),
986 .maxTexelBufferElements
= 128 * 1024 * 1024,
987 .maxUniformBufferRange
= UINT32_MAX
,
988 .maxStorageBufferRange
= UINT32_MAX
,
989 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
990 .maxMemoryAllocationCount
= UINT32_MAX
,
991 .maxSamplerAllocationCount
= 64 * 1024,
992 .bufferImageGranularity
= 64, /* A cache line */
993 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
994 .maxBoundDescriptorSets
= MAX_SETS
,
995 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
996 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
997 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
998 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
999 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1000 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1001 .maxPerStageResources
= max_descriptor_set_size
,
1002 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1003 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1004 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1005 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1006 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1007 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1008 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1009 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1010 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1011 .maxVertexInputBindings
= MAX_VBS
,
1012 .maxVertexInputAttributeOffset
= 2047,
1013 .maxVertexInputBindingStride
= 2048,
1014 .maxVertexOutputComponents
= 128,
1015 .maxTessellationGenerationLevel
= 64,
1016 .maxTessellationPatchSize
= 32,
1017 .maxTessellationControlPerVertexInputComponents
= 128,
1018 .maxTessellationControlPerVertexOutputComponents
= 128,
1019 .maxTessellationControlPerPatchOutputComponents
= 120,
1020 .maxTessellationControlTotalOutputComponents
= 4096,
1021 .maxTessellationEvaluationInputComponents
= 128,
1022 .maxTessellationEvaluationOutputComponents
= 128,
1023 .maxGeometryShaderInvocations
= 127,
1024 .maxGeometryInputComponents
= 64,
1025 .maxGeometryOutputComponents
= 128,
1026 .maxGeometryOutputVertices
= 256,
1027 .maxGeometryTotalOutputComponents
= 1024,
1028 .maxFragmentInputComponents
= 128,
1029 .maxFragmentOutputAttachments
= 8,
1030 .maxFragmentDualSrcAttachments
= 1,
1031 .maxFragmentCombinedOutputResources
= 8,
1032 .maxComputeSharedMemorySize
= 32768,
1033 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1034 .maxComputeWorkGroupInvocations
= 2048,
1035 .maxComputeWorkGroupSize
= {
1040 .subPixelPrecisionBits
= 8,
1041 .subTexelPrecisionBits
= 8,
1042 .mipmapPrecisionBits
= 8,
1043 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1044 .maxDrawIndirectCount
= UINT32_MAX
,
1045 .maxSamplerLodBias
= 16,
1046 .maxSamplerAnisotropy
= 16,
1047 .maxViewports
= MAX_VIEWPORTS
,
1048 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1049 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1050 .viewportSubPixelBits
= 8,
1051 .minMemoryMapAlignment
= 4096, /* A page */
1052 .minTexelBufferOffsetAlignment
= 1,
1053 .minUniformBufferOffsetAlignment
= 4,
1054 .minStorageBufferOffsetAlignment
= 4,
1055 .minTexelOffset
= -32,
1056 .maxTexelOffset
= 31,
1057 .minTexelGatherOffset
= -32,
1058 .maxTexelGatherOffset
= 31,
1059 .minInterpolationOffset
= -2,
1060 .maxInterpolationOffset
= 2,
1061 .subPixelInterpolationOffsetBits
= 8,
1062 .maxFramebufferWidth
= (1 << 14),
1063 .maxFramebufferHeight
= (1 << 14),
1064 .maxFramebufferLayers
= (1 << 10),
1065 .framebufferColorSampleCounts
= sample_counts
,
1066 .framebufferDepthSampleCounts
= sample_counts
,
1067 .framebufferStencilSampleCounts
= sample_counts
,
1068 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1069 .maxColorAttachments
= MAX_RTS
,
1070 .sampledImageColorSampleCounts
= sample_counts
,
1071 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1072 .sampledImageDepthSampleCounts
= sample_counts
,
1073 .sampledImageStencilSampleCounts
= sample_counts
,
1074 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= VI
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1075 .maxSampleMaskWords
= 1,
1076 .timestampComputeAndGraphics
= true,
1077 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1078 .maxClipDistances
= 8,
1079 .maxCullDistances
= 8,
1080 .maxCombinedClipAndCullDistances
= 8,
1081 .discreteQueuePriorities
= 2,
1082 .pointSizeRange
= { 0.0, 8192.0 },
1083 .lineWidthRange
= { 0.0, 7.9921875 },
1084 .pointSizeGranularity
= (1.0 / 8.0),
1085 .lineWidthGranularity
= (1.0 / 128.0),
1086 .strictLines
= false, /* FINISHME */
1087 .standardSampleLocations
= true,
1088 .optimalBufferCopyOffsetAlignment
= 128,
1089 .optimalBufferCopyRowPitchAlignment
= 128,
1090 .nonCoherentAtomSize
= 64,
1093 *pProperties
= (VkPhysicalDeviceProperties
) {
1094 .apiVersion
= radv_physical_device_api_version(pdevice
),
1095 .driverVersion
= vk_get_driver_version(),
1096 .vendorID
= ATI_VENDOR_ID
,
1097 .deviceID
= pdevice
->rad_info
.pci_id
,
1098 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1100 .sparseProperties
= {0},
1103 strcpy(pProperties
->deviceName
, pdevice
->name
);
1104 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1107 void radv_GetPhysicalDeviceProperties2(
1108 VkPhysicalDevice physicalDevice
,
1109 VkPhysicalDeviceProperties2
*pProperties
)
1111 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1112 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1114 vk_foreach_struct(ext
, pProperties
->pNext
) {
1115 switch (ext
->sType
) {
1116 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1117 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1118 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1119 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1123 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1124 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1125 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1126 properties
->deviceLUIDValid
= false;
1129 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1130 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1131 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1132 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1136 VkPhysicalDevicePointClippingProperties
*properties
=
1137 (VkPhysicalDevicePointClippingProperties
*)ext
;
1138 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1142 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1143 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1144 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1147 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1148 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1149 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1150 properties
->minImportedHostPointerAlignment
= 4096;
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1154 VkPhysicalDeviceSubgroupProperties
*properties
=
1155 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1156 properties
->subgroupSize
= 64;
1157 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1158 properties
->supportedOperations
=
1159 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1160 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1161 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1162 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1163 if (pdevice
->rad_info
.chip_class
>= VI
) {
1164 properties
->supportedOperations
|=
1165 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1166 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1167 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1169 properties
->quadOperationsInAllStages
= true;
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1173 VkPhysicalDeviceMaintenance3Properties
*properties
=
1174 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1175 /* Make sure everything is addressable by a signed 32-bit int, and
1176 * our largest descriptors are 96 bytes. */
1177 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1178 /* Our buffer size fields allow only this much */
1179 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1183 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1184 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1185 /* GFX6-8 only support single channel min/max filter. */
1186 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1187 properties
->filterMinmaxSingleComponentFormats
= true;
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1191 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1192 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1194 /* Shader engines. */
1195 properties
->shaderEngineCount
=
1196 pdevice
->rad_info
.max_se
;
1197 properties
->shaderArraysPerEngineCount
=
1198 pdevice
->rad_info
.max_sh_per_se
;
1199 properties
->computeUnitsPerShaderArray
=
1200 pdevice
->rad_info
.num_good_cu_per_sh
;
1201 properties
->simdPerComputeUnit
= 4;
1202 properties
->wavefrontsPerSimd
=
1203 pdevice
->rad_info
.family
== CHIP_TONGA
||
1204 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1205 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1206 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1207 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1208 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1209 properties
->wavefrontSize
= 64;
1212 properties
->sgprsPerSimd
=
1213 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1214 properties
->minSgprAllocation
=
1215 pdevice
->rad_info
.chip_class
>= VI
? 16 : 8;
1216 properties
->maxSgprAllocation
=
1217 pdevice
->rad_info
.family
== CHIP_TONGA
||
1218 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1219 properties
->sgprAllocationGranularity
=
1220 pdevice
->rad_info
.chip_class
>= VI
? 16 : 8;
1223 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1224 properties
->minVgprAllocation
= 4;
1225 properties
->maxVgprAllocation
= 256;
1226 properties
->vgprAllocationGranularity
= 4;
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1230 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1231 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1232 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1236 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1237 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1238 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1239 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1240 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1241 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1242 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1243 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1244 properties
->robustBufferAccessUpdateAfterBind
= false;
1245 properties
->quadDivergentImplicitLod
= false;
1247 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1248 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1249 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1250 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1251 32 /* sampler, largest when combined with image */ +
1252 64 /* sampled image */ +
1253 64 /* storage image */);
1254 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1255 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1256 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1257 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1258 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1259 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1260 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1261 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1262 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1263 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1264 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1265 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1266 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1267 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1268 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1272 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1273 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1274 properties
->protectedNoFault
= false;
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1278 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1279 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1280 properties
->primitiveOverestimationSize
= 0;
1281 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1282 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1283 properties
->primitiveUnderestimation
= VK_FALSE
;
1284 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1285 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1286 properties
->degenerateLinesRasterized
= VK_FALSE
;
1287 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1288 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1291 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1292 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1293 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1294 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1295 properties
->pciBus
= pdevice
->bus_info
.bus
;
1296 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1297 properties
->pciFunction
= pdevice
->bus_info
.func
;
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1301 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1302 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1304 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1305 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1306 strcpy(driver_props
->driverName
, "radv");
1308 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1309 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1310 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1311 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1313 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1322 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1323 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1324 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1325 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1326 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1327 properties
->maxTransformFeedbackStreamDataSize
= 512;
1328 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1329 properties
->maxTransformFeedbackBufferDataStride
= 512;
1330 properties
->transformFeedbackQueries
= true;
1331 properties
->transformFeedbackStreamsLinesTriangles
= false;
1332 properties
->transformFeedbackRasterizationStreamSelect
= false;
1333 properties
->transformFeedbackDraw
= true;
1336 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1337 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1338 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1340 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1341 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1342 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1343 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1344 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1353 static void radv_get_physical_device_queue_family_properties(
1354 struct radv_physical_device
* pdevice
,
1356 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1358 int num_queue_families
= 1;
1360 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1361 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1362 num_queue_families
++;
1364 if (pQueueFamilyProperties
== NULL
) {
1365 *pCount
= num_queue_families
;
1374 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1375 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1376 VK_QUEUE_COMPUTE_BIT
|
1377 VK_QUEUE_TRANSFER_BIT
|
1378 VK_QUEUE_SPARSE_BINDING_BIT
,
1380 .timestampValidBits
= 64,
1381 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1386 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1387 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1388 if (*pCount
> idx
) {
1389 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1390 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1391 VK_QUEUE_TRANSFER_BIT
|
1392 VK_QUEUE_SPARSE_BINDING_BIT
,
1393 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1394 .timestampValidBits
= 64,
1395 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1403 void radv_GetPhysicalDeviceQueueFamilyProperties(
1404 VkPhysicalDevice physicalDevice
,
1406 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1408 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1409 if (!pQueueFamilyProperties
) {
1410 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1413 VkQueueFamilyProperties
*properties
[] = {
1414 pQueueFamilyProperties
+ 0,
1415 pQueueFamilyProperties
+ 1,
1416 pQueueFamilyProperties
+ 2,
1418 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1419 assert(*pCount
<= 3);
1422 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1423 VkPhysicalDevice physicalDevice
,
1425 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1427 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1428 if (!pQueueFamilyProperties
) {
1429 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1432 VkQueueFamilyProperties
*properties
[] = {
1433 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1434 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1435 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1437 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1438 assert(*pCount
<= 3);
1441 void radv_GetPhysicalDeviceMemoryProperties(
1442 VkPhysicalDevice physicalDevice
,
1443 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1445 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1447 *pMemoryProperties
= physical_device
->memory_properties
;
1451 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1452 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1454 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1455 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1456 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1457 uint64_t vram_size
= radv_get_vram_size(device
);
1458 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1459 uint64_t heap_budget
, heap_usage
;
1461 /* For all memory heaps, the computation of budget is as follow:
1462 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1464 * The Vulkan spec 1.1.97 says that the budget should include any
1465 * currently allocated device memory.
1467 * Note that the application heap usages are not really accurate (eg.
1468 * in presence of shared buffers).
1471 heap_usage
= device
->ws
->query_value(device
->ws
,
1472 RADEON_ALLOCATED_VRAM
);
1474 heap_budget
= vram_size
-
1475 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1478 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM
] = heap_budget
;
1479 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM
] = heap_usage
;
1482 if (visible_vram_size
) {
1483 heap_usage
= device
->ws
->query_value(device
->ws
,
1484 RADEON_ALLOCATED_VRAM_VIS
);
1486 heap_budget
= visible_vram_size
-
1487 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1490 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_budget
;
1491 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_usage
;
1495 heap_usage
= device
->ws
->query_value(device
->ws
,
1496 RADEON_ALLOCATED_GTT
);
1498 heap_budget
= gtt_size
-
1499 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1502 memoryBudget
->heapBudget
[RADV_MEM_HEAP_GTT
] = heap_budget
;
1503 memoryBudget
->heapUsage
[RADV_MEM_HEAP_GTT
] = heap_usage
;
1506 /* The heapBudget and heapUsage values must be zero for array elements
1507 * greater than or equal to
1508 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1510 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1511 memoryBudget
->heapBudget
[i
] = 0;
1512 memoryBudget
->heapUsage
[i
] = 0;
1516 void radv_GetPhysicalDeviceMemoryProperties2(
1517 VkPhysicalDevice physicalDevice
,
1518 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1520 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1521 &pMemoryProperties
->memoryProperties
);
1523 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1524 vk_find_struct(pMemoryProperties
->pNext
,
1525 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1527 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1530 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1532 VkExternalMemoryHandleTypeFlagBits handleType
,
1533 const void *pHostPointer
,
1534 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1536 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1540 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1541 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1542 uint32_t memoryTypeBits
= 0;
1543 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1544 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1545 memoryTypeBits
= (1 << i
);
1549 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1553 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1557 static enum radeon_ctx_priority
1558 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1560 /* Default to MEDIUM when a specific global priority isn't requested */
1562 return RADEON_CTX_PRIORITY_MEDIUM
;
1564 switch(pObj
->globalPriority
) {
1565 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1566 return RADEON_CTX_PRIORITY_REALTIME
;
1567 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1568 return RADEON_CTX_PRIORITY_HIGH
;
1569 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1570 return RADEON_CTX_PRIORITY_MEDIUM
;
1571 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1572 return RADEON_CTX_PRIORITY_LOW
;
1574 unreachable("Illegal global priority value");
1575 return RADEON_CTX_PRIORITY_INVALID
;
1580 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1581 uint32_t queue_family_index
, int idx
,
1582 VkDeviceQueueCreateFlags flags
,
1583 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1585 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1586 queue
->device
= device
;
1587 queue
->queue_family_index
= queue_family_index
;
1588 queue
->queue_idx
= idx
;
1589 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1590 queue
->flags
= flags
;
1592 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1594 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1600 radv_queue_finish(struct radv_queue
*queue
)
1603 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1605 if (queue
->initial_full_flush_preamble_cs
)
1606 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1607 if (queue
->initial_preamble_cs
)
1608 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1609 if (queue
->continue_preamble_cs
)
1610 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1611 if (queue
->descriptor_bo
)
1612 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1613 if (queue
->scratch_bo
)
1614 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1615 if (queue
->esgs_ring_bo
)
1616 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1617 if (queue
->gsvs_ring_bo
)
1618 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1619 if (queue
->tess_rings_bo
)
1620 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1621 if (queue
->compute_scratch_bo
)
1622 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1626 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1628 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1629 bo_list
->list
.count
= bo_list
->capacity
= 0;
1630 bo_list
->list
.bos
= NULL
;
1634 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1636 free(bo_list
->list
.bos
);
1637 pthread_mutex_destroy(&bo_list
->mutex
);
1640 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1641 struct radeon_winsys_bo
*bo
)
1643 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1648 if (unlikely(!device
->use_global_bo_list
))
1651 pthread_mutex_lock(&bo_list
->mutex
);
1652 if (bo_list
->list
.count
== bo_list
->capacity
) {
1653 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1654 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1657 pthread_mutex_unlock(&bo_list
->mutex
);
1658 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1661 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1662 bo_list
->capacity
= capacity
;
1665 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1666 pthread_mutex_unlock(&bo_list
->mutex
);
1670 static void radv_bo_list_remove(struct radv_device
*device
,
1671 struct radeon_winsys_bo
*bo
)
1673 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1678 if (unlikely(!device
->use_global_bo_list
))
1681 pthread_mutex_lock(&bo_list
->mutex
);
1682 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1683 if (bo_list
->list
.bos
[i
] == bo
) {
1684 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1685 --bo_list
->list
.count
;
1689 pthread_mutex_unlock(&bo_list
->mutex
);
1693 radv_device_init_gs_info(struct radv_device
*device
)
1695 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1696 device
->physical_device
->rad_info
.family
);
1699 static int radv_get_device_extension_index(const char *name
)
1701 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1702 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1709 radv_get_int_debug_option(const char *name
, int default_value
)
1716 result
= default_value
;
1720 result
= strtol(str
, &endptr
, 0);
1721 if (str
== endptr
) {
1722 /* No digits founs. */
1723 result
= default_value
;
1730 VkResult
radv_CreateDevice(
1731 VkPhysicalDevice physicalDevice
,
1732 const VkDeviceCreateInfo
* pCreateInfo
,
1733 const VkAllocationCallbacks
* pAllocator
,
1736 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1738 struct radv_device
*device
;
1740 bool keep_shader_info
= false;
1742 /* Check enabled features */
1743 if (pCreateInfo
->pEnabledFeatures
) {
1744 VkPhysicalDeviceFeatures supported_features
;
1745 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1746 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1747 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1748 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1749 for (uint32_t i
= 0; i
< num_features
; i
++) {
1750 if (enabled_feature
[i
] && !supported_feature
[i
])
1751 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1755 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1757 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1759 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1761 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1762 device
->instance
= physical_device
->instance
;
1763 device
->physical_device
= physical_device
;
1765 device
->ws
= physical_device
->ws
;
1767 device
->alloc
= *pAllocator
;
1769 device
->alloc
= physical_device
->instance
->alloc
;
1771 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1772 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1773 int index
= radv_get_device_extension_index(ext_name
);
1774 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1775 vk_free(&device
->alloc
, device
);
1776 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1779 device
->enabled_extensions
.extensions
[index
] = true;
1782 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1784 /* With update after bind we can't attach bo's to the command buffer
1785 * from the descriptor set anymore, so we have to use a global BO list.
1787 device
->use_global_bo_list
=
1788 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1789 device
->enabled_extensions
.EXT_descriptor_indexing
||
1790 device
->enabled_extensions
.EXT_buffer_device_address
;
1792 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1793 list_inithead(&device
->shader_slabs
);
1795 radv_bo_list_init(&device
->bo_list
);
1797 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1798 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1799 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1800 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1801 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1803 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1805 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1806 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1807 if (!device
->queues
[qfi
]) {
1808 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1812 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1814 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1816 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1817 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1818 qfi
, q
, queue_create
->flags
,
1820 if (result
!= VK_SUCCESS
)
1825 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1826 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1828 /* Disabled and not implemented for now. */
1829 device
->dfsm_allowed
= device
->pbb_allowed
&&
1830 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1831 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1834 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1837 /* The maximum number of scratch waves. Scratch space isn't divided
1838 * evenly between CUs. The number is only a function of the number of CUs.
1839 * We can decrease the constant to decrease the scratch buffer size.
1841 * sctx->scratch_waves must be >= the maximum possible size of
1842 * 1 threadgroup, so that the hw doesn't hang from being unable
1845 * The recommended value is 4 per CU at most. Higher numbers don't
1846 * bring much benefit, but they still occupy chip resources (think
1847 * async compute). I've seen ~2% performance difference between 4 and 32.
1849 uint32_t max_threads_per_block
= 2048;
1850 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1851 max_threads_per_block
/ 64);
1853 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1855 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1856 /* If the KMD allows it (there is a KMD hw register for it),
1857 * allow launching waves out-of-order.
1859 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1862 radv_device_init_gs_info(device
);
1864 device
->tess_offchip_block_dw_size
=
1865 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1866 device
->has_distributed_tess
=
1867 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1868 device
->physical_device
->rad_info
.max_se
>= 2;
1870 if (getenv("RADV_TRACE_FILE")) {
1871 const char *filename
= getenv("RADV_TRACE_FILE");
1873 keep_shader_info
= true;
1875 if (!radv_init_trace(device
))
1878 fprintf(stderr
, "*****************************************************************************\n");
1879 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1880 fprintf(stderr
, "*****************************************************************************\n");
1882 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1883 radv_dump_enabled_options(device
, stderr
);
1886 device
->keep_shader_info
= keep_shader_info
;
1888 result
= radv_device_init_meta(device
);
1889 if (result
!= VK_SUCCESS
)
1892 radv_device_init_msaa(device
);
1894 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1895 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1897 case RADV_QUEUE_GENERAL
:
1898 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1899 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1900 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1902 case RADV_QUEUE_COMPUTE
:
1903 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1904 radeon_emit(device
->empty_cs
[family
], 0);
1907 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1910 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1911 cik_create_gfx_config(device
);
1913 VkPipelineCacheCreateInfo ci
;
1914 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1917 ci
.pInitialData
= NULL
;
1918 ci
.initialDataSize
= 0;
1920 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1922 if (result
!= VK_SUCCESS
)
1925 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1927 device
->force_aniso
=
1928 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1929 if (device
->force_aniso
>= 0) {
1930 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1931 1 << util_logbase2(device
->force_aniso
));
1934 *pDevice
= radv_device_to_handle(device
);
1938 radv_device_finish_meta(device
);
1940 radv_bo_list_finish(&device
->bo_list
);
1942 if (device
->trace_bo
)
1943 device
->ws
->buffer_destroy(device
->trace_bo
);
1945 if (device
->gfx_init
)
1946 device
->ws
->buffer_destroy(device
->gfx_init
);
1948 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1949 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1950 radv_queue_finish(&device
->queues
[i
][q
]);
1951 if (device
->queue_count
[i
])
1952 vk_free(&device
->alloc
, device
->queues
[i
]);
1955 vk_free(&device
->alloc
, device
);
1959 void radv_DestroyDevice(
1961 const VkAllocationCallbacks
* pAllocator
)
1963 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1968 if (device
->trace_bo
)
1969 device
->ws
->buffer_destroy(device
->trace_bo
);
1971 if (device
->gfx_init
)
1972 device
->ws
->buffer_destroy(device
->gfx_init
);
1974 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1975 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1976 radv_queue_finish(&device
->queues
[i
][q
]);
1977 if (device
->queue_count
[i
])
1978 vk_free(&device
->alloc
, device
->queues
[i
]);
1979 if (device
->empty_cs
[i
])
1980 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1982 radv_device_finish_meta(device
);
1984 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1985 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1987 radv_destroy_shader_slabs(device
);
1989 radv_bo_list_finish(&device
->bo_list
);
1990 vk_free(&device
->alloc
, device
);
1993 VkResult
radv_EnumerateInstanceLayerProperties(
1994 uint32_t* pPropertyCount
,
1995 VkLayerProperties
* pProperties
)
1997 if (pProperties
== NULL
) {
1998 *pPropertyCount
= 0;
2002 /* None supported at this time */
2003 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2006 VkResult
radv_EnumerateDeviceLayerProperties(
2007 VkPhysicalDevice physicalDevice
,
2008 uint32_t* pPropertyCount
,
2009 VkLayerProperties
* pProperties
)
2011 if (pProperties
== NULL
) {
2012 *pPropertyCount
= 0;
2016 /* None supported at this time */
2017 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2020 void radv_GetDeviceQueue2(
2022 const VkDeviceQueueInfo2
* pQueueInfo
,
2025 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2026 struct radv_queue
*queue
;
2028 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2029 if (pQueueInfo
->flags
!= queue
->flags
) {
2030 /* From the Vulkan 1.1.70 spec:
2032 * "The queue returned by vkGetDeviceQueue2 must have the same
2033 * flags value from this structure as that used at device
2034 * creation time in a VkDeviceQueueCreateInfo instance. If no
2035 * matching flags were specified at device creation time then
2036 * pQueue will return VK_NULL_HANDLE."
2038 *pQueue
= VK_NULL_HANDLE
;
2042 *pQueue
= radv_queue_to_handle(queue
);
2045 void radv_GetDeviceQueue(
2047 uint32_t queueFamilyIndex
,
2048 uint32_t queueIndex
,
2051 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2052 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2053 .queueFamilyIndex
= queueFamilyIndex
,
2054 .queueIndex
= queueIndex
2057 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2061 fill_geom_tess_rings(struct radv_queue
*queue
,
2063 bool add_sample_positions
,
2064 uint32_t esgs_ring_size
,
2065 struct radeon_winsys_bo
*esgs_ring_bo
,
2066 uint32_t gsvs_ring_size
,
2067 struct radeon_winsys_bo
*gsvs_ring_bo
,
2068 uint32_t tess_factor_ring_size
,
2069 uint32_t tess_offchip_ring_offset
,
2070 uint32_t tess_offchip_ring_size
,
2071 struct radeon_winsys_bo
*tess_rings_bo
)
2073 uint32_t *desc
= &map
[4];
2076 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2078 /* stride 0, num records - size, add tid, swizzle, elsize4,
2081 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2082 S_008F04_STRIDE(0) |
2083 S_008F04_SWIZZLE_ENABLE(true);
2084 desc
[2] = esgs_ring_size
;
2085 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2086 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2087 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2088 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2089 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2090 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2091 S_008F0C_ELEMENT_SIZE(1) |
2092 S_008F0C_INDEX_STRIDE(3) |
2093 S_008F0C_ADD_TID_ENABLE(true);
2095 /* GS entry for ES->GS ring */
2096 /* stride 0, num records - size, elsize0,
2099 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2100 S_008F04_STRIDE(0) |
2101 S_008F04_SWIZZLE_ENABLE(false);
2102 desc
[6] = esgs_ring_size
;
2103 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2104 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2105 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2106 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2107 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2108 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2109 S_008F0C_ELEMENT_SIZE(0) |
2110 S_008F0C_INDEX_STRIDE(0) |
2111 S_008F0C_ADD_TID_ENABLE(false);
2117 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2119 /* VS entry for GS->VS ring */
2120 /* stride 0, num records - size, elsize0,
2123 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2124 S_008F04_STRIDE(0) |
2125 S_008F04_SWIZZLE_ENABLE(false);
2126 desc
[2] = gsvs_ring_size
;
2127 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2128 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2129 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2130 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2131 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2132 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2133 S_008F0C_ELEMENT_SIZE(0) |
2134 S_008F0C_INDEX_STRIDE(0) |
2135 S_008F0C_ADD_TID_ENABLE(false);
2137 /* stride gsvs_itemsize, num records 64
2138 elsize 4, index stride 16 */
2139 /* shader will patch stride and desc[2] */
2141 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2142 S_008F04_STRIDE(0) |
2143 S_008F04_SWIZZLE_ENABLE(true);
2145 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2146 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2147 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2148 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2149 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2150 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2151 S_008F0C_ELEMENT_SIZE(1) |
2152 S_008F0C_INDEX_STRIDE(1) |
2153 S_008F0C_ADD_TID_ENABLE(true);
2158 if (tess_rings_bo
) {
2159 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2160 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2163 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2164 S_008F04_STRIDE(0) |
2165 S_008F04_SWIZZLE_ENABLE(false);
2166 desc
[2] = tess_factor_ring_size
;
2167 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2168 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2169 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2170 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2171 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2173 S_008F0C_ELEMENT_SIZE(0) |
2174 S_008F0C_INDEX_STRIDE(0) |
2175 S_008F0C_ADD_TID_ENABLE(false);
2177 desc
[4] = tess_offchip_va
;
2178 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2179 S_008F04_STRIDE(0) |
2180 S_008F04_SWIZZLE_ENABLE(false);
2181 desc
[6] = tess_offchip_ring_size
;
2182 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2186 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2187 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2188 S_008F0C_ELEMENT_SIZE(0) |
2189 S_008F0C_INDEX_STRIDE(0) |
2190 S_008F0C_ADD_TID_ENABLE(false);
2195 if (add_sample_positions
) {
2196 /* add sample positions after all rings */
2197 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2199 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2201 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2203 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2208 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2210 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
2211 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2212 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2213 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2214 unsigned max_offchip_buffers
;
2215 unsigned offchip_granularity
;
2216 unsigned hs_offchip_param
;
2220 * This must be one less than the maximum number due to a hw limitation.
2221 * Various hardware bugs in SI, CIK, and GFX9 need this.
2224 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2225 * Gfx7 should limit max_offchip_buffers to 508
2226 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2228 * Follow AMDVLK here.
2230 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2231 device
->physical_device
->rad_info
.chip_class
== CIK
||
2232 device
->physical_device
->rad_info
.chip_class
== SI
)
2233 --max_offchip_buffers_per_se
;
2235 max_offchip_buffers
= max_offchip_buffers_per_se
*
2236 device
->physical_device
->rad_info
.max_se
;
2238 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2239 * around by setting 4K granularity.
2241 if (device
->tess_offchip_block_dw_size
== 4096) {
2242 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2243 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2245 assert(device
->tess_offchip_block_dw_size
== 8192);
2246 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2249 switch (device
->physical_device
->rad_info
.chip_class
) {
2251 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2257 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2261 *max_offchip_buffers_p
= max_offchip_buffers
;
2262 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2263 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
2264 --max_offchip_buffers
;
2266 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2267 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2270 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2272 return hs_offchip_param
;
2276 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2277 struct radeon_winsys_bo
*esgs_ring_bo
,
2278 uint32_t esgs_ring_size
,
2279 struct radeon_winsys_bo
*gsvs_ring_bo
,
2280 uint32_t gsvs_ring_size
)
2282 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2286 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2289 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2291 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2292 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2293 radeon_emit(cs
, esgs_ring_size
>> 8);
2294 radeon_emit(cs
, gsvs_ring_size
>> 8);
2296 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2297 radeon_emit(cs
, esgs_ring_size
>> 8);
2298 radeon_emit(cs
, gsvs_ring_size
>> 8);
2303 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2304 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2305 struct radeon_winsys_bo
*tess_rings_bo
)
2312 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2314 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2316 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2317 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2318 S_030938_SIZE(tf_ring_size
/ 4));
2319 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2321 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2322 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2323 S_030944_BASE_HI(tf_va
>> 40));
2325 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2328 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2329 S_008988_SIZE(tf_ring_size
/ 4));
2330 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2332 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2338 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2339 struct radeon_winsys_bo
*compute_scratch_bo
)
2341 uint64_t scratch_va
;
2343 if (!compute_scratch_bo
)
2346 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2348 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2350 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2351 radeon_emit(cs
, scratch_va
);
2352 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2353 S_008F04_SWIZZLE_ENABLE(1));
2357 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2358 struct radeon_cmdbuf
*cs
,
2359 struct radeon_winsys_bo
*descriptor_bo
)
2366 va
= radv_buffer_get_va(descriptor_bo
);
2368 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2370 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2371 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2372 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2373 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2374 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2376 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2377 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2381 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2382 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2383 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2384 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2385 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2386 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2388 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2389 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2396 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2398 struct radv_device
*device
= queue
->device
;
2400 if (device
->gfx_init
) {
2401 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2403 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2404 radeon_emit(cs
, va
);
2405 radeon_emit(cs
, va
>> 32);
2406 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2408 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2410 struct radv_physical_device
*physical_device
= device
->physical_device
;
2411 si_emit_graphics(physical_device
, cs
);
2416 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2418 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2419 si_emit_compute(physical_device
, cs
);
2423 radv_get_preamble_cs(struct radv_queue
*queue
,
2424 uint32_t scratch_size
,
2425 uint32_t compute_scratch_size
,
2426 uint32_t esgs_ring_size
,
2427 uint32_t gsvs_ring_size
,
2428 bool needs_tess_rings
,
2429 bool needs_sample_positions
,
2430 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2431 struct radeon_cmdbuf
**initial_preamble_cs
,
2432 struct radeon_cmdbuf
**continue_preamble_cs
)
2434 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2435 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2436 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2437 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2438 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2439 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2440 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2441 bool add_tess_rings
= false, add_sample_positions
= false;
2442 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2443 unsigned max_offchip_buffers
;
2444 unsigned hs_offchip_param
= 0;
2445 unsigned tess_offchip_ring_offset
;
2446 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2447 if (!queue
->has_tess_rings
) {
2448 if (needs_tess_rings
)
2449 add_tess_rings
= true;
2451 if (!queue
->has_sample_positions
) {
2452 if (needs_sample_positions
)
2453 add_sample_positions
= true;
2455 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2456 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2457 &max_offchip_buffers
);
2458 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2459 tess_offchip_ring_size
= max_offchip_buffers
*
2460 queue
->device
->tess_offchip_block_dw_size
* 4;
2462 if (scratch_size
<= queue
->scratch_size
&&
2463 compute_scratch_size
<= queue
->compute_scratch_size
&&
2464 esgs_ring_size
<= queue
->esgs_ring_size
&&
2465 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2466 !add_tess_rings
&& !add_sample_positions
&&
2467 queue
->initial_preamble_cs
) {
2468 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2469 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2470 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2471 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2472 *continue_preamble_cs
= NULL
;
2476 if (scratch_size
> queue
->scratch_size
) {
2477 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2482 RADV_BO_PRIORITY_SCRATCH
);
2486 scratch_bo
= queue
->scratch_bo
;
2488 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2489 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2490 compute_scratch_size
,
2494 RADV_BO_PRIORITY_SCRATCH
);
2495 if (!compute_scratch_bo
)
2499 compute_scratch_bo
= queue
->compute_scratch_bo
;
2501 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2502 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2507 RADV_BO_PRIORITY_SCRATCH
);
2511 esgs_ring_bo
= queue
->esgs_ring_bo
;
2512 esgs_ring_size
= queue
->esgs_ring_size
;
2515 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2516 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2521 RADV_BO_PRIORITY_SCRATCH
);
2525 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2526 gsvs_ring_size
= queue
->gsvs_ring_size
;
2529 if (add_tess_rings
) {
2530 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2531 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2535 RADV_BO_PRIORITY_SCRATCH
);
2539 tess_rings_bo
= queue
->tess_rings_bo
;
2542 if (scratch_bo
!= queue
->scratch_bo
||
2543 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2544 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2545 tess_rings_bo
!= queue
->tess_rings_bo
||
2546 add_sample_positions
) {
2548 if (gsvs_ring_bo
|| esgs_ring_bo
||
2549 tess_rings_bo
|| add_sample_positions
) {
2550 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2551 if (add_sample_positions
)
2552 size
+= 128; /* 64+32+16+8 = 120 bytes */
2554 else if (scratch_bo
)
2555 size
= 8; /* 2 dword */
2557 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2561 RADEON_FLAG_CPU_ACCESS
|
2562 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2563 RADEON_FLAG_READ_ONLY
,
2564 RADV_BO_PRIORITY_DESCRIPTOR
);
2568 descriptor_bo
= queue
->descriptor_bo
;
2570 if (descriptor_bo
!= queue
->descriptor_bo
) {
2571 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2574 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2575 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2576 S_008F04_SWIZZLE_ENABLE(1);
2577 map
[0] = scratch_va
;
2581 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2582 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2583 esgs_ring_size
, esgs_ring_bo
,
2584 gsvs_ring_size
, gsvs_ring_bo
,
2585 tess_factor_ring_size
,
2586 tess_offchip_ring_offset
,
2587 tess_offchip_ring_size
,
2590 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2593 for(int i
= 0; i
< 3; ++i
) {
2594 struct radeon_cmdbuf
*cs
= NULL
;
2595 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2596 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2603 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2605 /* Emit initial configuration. */
2606 switch (queue
->queue_family_index
) {
2607 case RADV_QUEUE_GENERAL
:
2608 radv_init_graphics_state(cs
, queue
);
2610 case RADV_QUEUE_COMPUTE
:
2611 radv_init_compute_state(cs
, queue
);
2613 case RADV_QUEUE_TRANSFER
:
2617 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2618 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2619 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2620 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2621 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2624 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2625 gsvs_ring_bo
, gsvs_ring_size
);
2626 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2627 tess_factor_ring_size
, tess_rings_bo
);
2628 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2629 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2632 si_cs_emit_cache_flush(cs
,
2633 queue
->device
->physical_device
->rad_info
.chip_class
,
2635 queue
->queue_family_index
== RING_COMPUTE
&&
2636 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
2637 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2638 RADV_CMD_FLAG_INV_ICACHE
|
2639 RADV_CMD_FLAG_INV_SMEM_L1
|
2640 RADV_CMD_FLAG_INV_VMEM_L1
|
2641 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2642 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2643 } else if (i
== 1) {
2644 si_cs_emit_cache_flush(cs
,
2645 queue
->device
->physical_device
->rad_info
.chip_class
,
2647 queue
->queue_family_index
== RING_COMPUTE
&&
2648 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
2649 RADV_CMD_FLAG_INV_ICACHE
|
2650 RADV_CMD_FLAG_INV_SMEM_L1
|
2651 RADV_CMD_FLAG_INV_VMEM_L1
|
2652 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2653 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2656 if (!queue
->device
->ws
->cs_finalize(cs
))
2660 if (queue
->initial_full_flush_preamble_cs
)
2661 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2663 if (queue
->initial_preamble_cs
)
2664 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2666 if (queue
->continue_preamble_cs
)
2667 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2669 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2670 queue
->initial_preamble_cs
= dest_cs
[1];
2671 queue
->continue_preamble_cs
= dest_cs
[2];
2673 if (scratch_bo
!= queue
->scratch_bo
) {
2674 if (queue
->scratch_bo
)
2675 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2676 queue
->scratch_bo
= scratch_bo
;
2677 queue
->scratch_size
= scratch_size
;
2680 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2681 if (queue
->compute_scratch_bo
)
2682 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2683 queue
->compute_scratch_bo
= compute_scratch_bo
;
2684 queue
->compute_scratch_size
= compute_scratch_size
;
2687 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2688 if (queue
->esgs_ring_bo
)
2689 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2690 queue
->esgs_ring_bo
= esgs_ring_bo
;
2691 queue
->esgs_ring_size
= esgs_ring_size
;
2694 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2695 if (queue
->gsvs_ring_bo
)
2696 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2697 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2698 queue
->gsvs_ring_size
= gsvs_ring_size
;
2701 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2702 queue
->tess_rings_bo
= tess_rings_bo
;
2703 queue
->has_tess_rings
= true;
2706 if (descriptor_bo
!= queue
->descriptor_bo
) {
2707 if (queue
->descriptor_bo
)
2708 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2710 queue
->descriptor_bo
= descriptor_bo
;
2713 if (add_sample_positions
)
2714 queue
->has_sample_positions
= true;
2716 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2717 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2718 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2719 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2720 *continue_preamble_cs
= NULL
;
2723 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2725 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2726 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2727 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2728 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2729 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2730 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2731 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2732 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2733 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2734 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2735 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2736 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2737 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2738 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2741 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2742 struct radv_winsys_sem_counts
*counts
,
2744 const VkSemaphore
*sems
,
2748 int syncobj_idx
= 0, sem_idx
= 0;
2750 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2753 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2754 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2756 if (sem
->temp_syncobj
|| sem
->syncobj
)
2757 counts
->syncobj_count
++;
2759 counts
->sem_count
++;
2762 if (_fence
!= VK_NULL_HANDLE
) {
2763 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2764 if (fence
->temp_syncobj
|| fence
->syncobj
)
2765 counts
->syncobj_count
++;
2768 if (counts
->syncobj_count
) {
2769 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2770 if (!counts
->syncobj
)
2771 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2774 if (counts
->sem_count
) {
2775 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2777 free(counts
->syncobj
);
2778 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2782 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2783 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2785 if (sem
->temp_syncobj
) {
2786 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2788 else if (sem
->syncobj
)
2789 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2792 counts
->sem
[sem_idx
++] = sem
->sem
;
2796 if (_fence
!= VK_NULL_HANDLE
) {
2797 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2798 if (fence
->temp_syncobj
)
2799 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2800 else if (fence
->syncobj
)
2801 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2808 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2810 free(sem_info
->wait
.syncobj
);
2811 free(sem_info
->wait
.sem
);
2812 free(sem_info
->signal
.syncobj
);
2813 free(sem_info
->signal
.sem
);
2817 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2819 const VkSemaphore
*sems
)
2821 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2822 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2824 if (sem
->temp_syncobj
) {
2825 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2826 sem
->temp_syncobj
= 0;
2832 radv_alloc_sem_info(struct radv_instance
*instance
,
2833 struct radv_winsys_sem_info
*sem_info
,
2835 const VkSemaphore
*wait_sems
,
2836 int num_signal_sems
,
2837 const VkSemaphore
*signal_sems
,
2841 memset(sem_info
, 0, sizeof(*sem_info
));
2843 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2846 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2848 radv_free_sem_info(sem_info
);
2850 /* caller can override these */
2851 sem_info
->cs_emit_wait
= true;
2852 sem_info
->cs_emit_signal
= true;
2856 /* Signals fence as soon as all the work currently put on queue is done. */
2857 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2858 struct radv_fence
*fence
)
2862 struct radv_winsys_sem_info sem_info
;
2864 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2865 radv_fence_to_handle(fence
));
2866 if (result
!= VK_SUCCESS
)
2869 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2870 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2871 1, NULL
, NULL
, &sem_info
, NULL
,
2872 false, fence
->fence
);
2873 radv_free_sem_info(&sem_info
);
2876 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2881 VkResult
radv_QueueSubmit(
2883 uint32_t submitCount
,
2884 const VkSubmitInfo
* pSubmits
,
2887 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2888 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2889 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2890 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2892 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
2893 uint32_t scratch_size
= 0;
2894 uint32_t compute_scratch_size
= 0;
2895 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2896 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2898 bool fence_emitted
= false;
2899 bool tess_rings_needed
= false;
2900 bool sample_positions_needed
= false;
2902 /* Do this first so failing to allocate scratch buffers can't result in
2903 * partially executed submissions. */
2904 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2905 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2906 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2907 pSubmits
[i
].pCommandBuffers
[j
]);
2909 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2910 compute_scratch_size
= MAX2(compute_scratch_size
,
2911 cmd_buffer
->compute_scratch_size_needed
);
2912 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2913 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2914 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2915 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2919 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2920 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2921 sample_positions_needed
, &initial_flush_preamble_cs
,
2922 &initial_preamble_cs
, &continue_preamble_cs
);
2923 if (result
!= VK_SUCCESS
)
2926 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2927 struct radeon_cmdbuf
**cs_array
;
2928 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2929 bool can_patch
= true;
2931 struct radv_winsys_sem_info sem_info
;
2933 result
= radv_alloc_sem_info(queue
->device
->instance
,
2935 pSubmits
[i
].waitSemaphoreCount
,
2936 pSubmits
[i
].pWaitSemaphores
,
2937 pSubmits
[i
].signalSemaphoreCount
,
2938 pSubmits
[i
].pSignalSemaphores
,
2940 if (result
!= VK_SUCCESS
)
2943 if (!pSubmits
[i
].commandBufferCount
) {
2944 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2945 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2946 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2951 radv_loge("failed to submit CS %d\n", i
);
2954 fence_emitted
= true;
2956 radv_free_sem_info(&sem_info
);
2960 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
2961 (pSubmits
[i
].commandBufferCount
));
2963 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2964 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2965 pSubmits
[i
].pCommandBuffers
[j
]);
2966 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2968 cs_array
[j
] = cmd_buffer
->cs
;
2969 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
2972 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
2975 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
2976 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
2977 const struct radv_winsys_bo_list
*bo_list
= NULL
;
2979 advance
= MIN2(max_cs_submission
,
2980 pSubmits
[i
].commandBufferCount
- j
);
2982 if (queue
->device
->trace_bo
)
2983 *queue
->device
->trace_id_ptr
= 0;
2985 sem_info
.cs_emit_wait
= j
== 0;
2986 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
2988 if (unlikely(queue
->device
->use_global_bo_list
)) {
2989 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
2990 bo_list
= &queue
->device
->bo_list
.list
;
2993 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
2994 advance
, initial_preamble
, continue_preamble_cs
,
2996 can_patch
, base_fence
);
2998 if (unlikely(queue
->device
->use_global_bo_list
))
2999 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3002 radv_loge("failed to submit CS %d\n", i
);
3005 fence_emitted
= true;
3006 if (queue
->device
->trace_bo
) {
3007 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3011 radv_free_temp_syncobjs(queue
->device
,
3012 pSubmits
[i
].waitSemaphoreCount
,
3013 pSubmits
[i
].pWaitSemaphores
);
3014 radv_free_sem_info(&sem_info
);
3019 if (!fence_emitted
) {
3020 result
= radv_signal_fence(queue
, fence
);
3021 if (result
!= VK_SUCCESS
)
3024 fence
->submitted
= true;
3030 VkResult
radv_QueueWaitIdle(
3033 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3035 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3036 radv_queue_family_to_ring(queue
->queue_family_index
),
3041 VkResult
radv_DeviceWaitIdle(
3044 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3046 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3047 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3048 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3054 VkResult
radv_EnumerateInstanceExtensionProperties(
3055 const char* pLayerName
,
3056 uint32_t* pPropertyCount
,
3057 VkExtensionProperties
* pProperties
)
3059 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3061 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3062 if (radv_supported_instance_extensions
.extensions
[i
]) {
3063 vk_outarray_append(&out
, prop
) {
3064 *prop
= radv_instance_extensions
[i
];
3069 return vk_outarray_status(&out
);
3072 VkResult
radv_EnumerateDeviceExtensionProperties(
3073 VkPhysicalDevice physicalDevice
,
3074 const char* pLayerName
,
3075 uint32_t* pPropertyCount
,
3076 VkExtensionProperties
* pProperties
)
3078 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3079 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3081 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3082 if (device
->supported_extensions
.extensions
[i
]) {
3083 vk_outarray_append(&out
, prop
) {
3084 *prop
= radv_device_extensions
[i
];
3089 return vk_outarray_status(&out
);
3092 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3093 VkInstance _instance
,
3096 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3098 return radv_lookup_entrypoint_checked(pName
,
3099 instance
? instance
->apiVersion
: 0,
3100 instance
? &instance
->enabled_extensions
: NULL
,
3104 /* The loader wants us to expose a second GetInstanceProcAddr function
3105 * to work around certain LD_PRELOAD issues seen in apps.
3108 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3109 VkInstance instance
,
3113 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3114 VkInstance instance
,
3117 return radv_GetInstanceProcAddr(instance
, pName
);
3120 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3124 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3126 return radv_lookup_entrypoint_checked(pName
,
3127 device
->instance
->apiVersion
,
3128 &device
->instance
->enabled_extensions
,
3129 &device
->enabled_extensions
);
3132 bool radv_get_memory_fd(struct radv_device
*device
,
3133 struct radv_device_memory
*memory
,
3136 struct radeon_bo_metadata metadata
;
3138 if (memory
->image
) {
3139 radv_init_metadata(device
, memory
->image
, &metadata
);
3140 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3143 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3147 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3148 const VkMemoryAllocateInfo
* pAllocateInfo
,
3149 const VkAllocationCallbacks
* pAllocator
,
3150 VkDeviceMemory
* pMem
)
3152 struct radv_device_memory
*mem
;
3154 enum radeon_bo_domain domain
;
3156 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3158 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3160 if (pAllocateInfo
->allocationSize
== 0) {
3161 /* Apparently, this is allowed */
3162 *pMem
= VK_NULL_HANDLE
;
3166 const VkImportMemoryFdInfoKHR
*import_info
=
3167 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3168 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3169 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3170 const VkExportMemoryAllocateInfo
*export_info
=
3171 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3172 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3173 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3175 const struct wsi_memory_allocate_info
*wsi_info
=
3176 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3178 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3179 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3181 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3183 if (wsi_info
&& wsi_info
->implicit_sync
)
3184 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3186 if (dedicate_info
) {
3187 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3188 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3194 float priority_float
= 0.5;
3195 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3196 vk_find_struct_const(pAllocateInfo
->pNext
,
3197 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3199 priority_float
= priority_ext
->priority
;
3201 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3202 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3204 mem
->user_ptr
= NULL
;
3207 assert(import_info
->handleType
==
3208 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3209 import_info
->handleType
==
3210 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3211 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3212 priority
, NULL
, NULL
);
3214 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3217 close(import_info
->fd
);
3219 } else if (host_ptr_info
) {
3220 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3221 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3222 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3223 pAllocateInfo
->allocationSize
,
3226 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3229 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3232 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3233 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3234 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3235 domain
= RADEON_DOMAIN_GTT
;
3237 domain
= RADEON_DOMAIN_VRAM
;
3239 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3240 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3242 flags
|= RADEON_FLAG_CPU_ACCESS
;
3244 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3245 flags
|= RADEON_FLAG_GTT_WC
;
3247 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3248 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3249 if (device
->use_global_bo_list
) {
3250 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3254 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3255 domain
, flags
, priority
);
3258 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3261 mem
->type_index
= mem_type_index
;
3264 result
= radv_bo_list_add(device
, mem
->bo
);
3265 if (result
!= VK_SUCCESS
)
3268 *pMem
= radv_device_memory_to_handle(mem
);
3273 device
->ws
->buffer_destroy(mem
->bo
);
3275 vk_free2(&device
->alloc
, pAllocator
, mem
);
3280 VkResult
radv_AllocateMemory(
3282 const VkMemoryAllocateInfo
* pAllocateInfo
,
3283 const VkAllocationCallbacks
* pAllocator
,
3284 VkDeviceMemory
* pMem
)
3286 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3287 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3290 void radv_FreeMemory(
3292 VkDeviceMemory _mem
,
3293 const VkAllocationCallbacks
* pAllocator
)
3295 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3296 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3301 radv_bo_list_remove(device
, mem
->bo
);
3302 device
->ws
->buffer_destroy(mem
->bo
);
3305 vk_free2(&device
->alloc
, pAllocator
, mem
);
3308 VkResult
radv_MapMemory(
3310 VkDeviceMemory _memory
,
3311 VkDeviceSize offset
,
3313 VkMemoryMapFlags flags
,
3316 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3317 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3325 *ppData
= mem
->user_ptr
;
3327 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3334 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3337 void radv_UnmapMemory(
3339 VkDeviceMemory _memory
)
3341 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3342 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3347 if (mem
->user_ptr
== NULL
)
3348 device
->ws
->buffer_unmap(mem
->bo
);
3351 VkResult
radv_FlushMappedMemoryRanges(
3353 uint32_t memoryRangeCount
,
3354 const VkMappedMemoryRange
* pMemoryRanges
)
3359 VkResult
radv_InvalidateMappedMemoryRanges(
3361 uint32_t memoryRangeCount
,
3362 const VkMappedMemoryRange
* pMemoryRanges
)
3367 void radv_GetBufferMemoryRequirements(
3370 VkMemoryRequirements
* pMemoryRequirements
)
3372 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3373 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3375 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3377 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3378 pMemoryRequirements
->alignment
= 4096;
3380 pMemoryRequirements
->alignment
= 16;
3382 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3385 void radv_GetBufferMemoryRequirements2(
3387 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3388 VkMemoryRequirements2
*pMemoryRequirements
)
3390 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3391 &pMemoryRequirements
->memoryRequirements
);
3392 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3393 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3394 switch (ext
->sType
) {
3395 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3396 VkMemoryDedicatedRequirements
*req
=
3397 (VkMemoryDedicatedRequirements
*) ext
;
3398 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3399 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3408 void radv_GetImageMemoryRequirements(
3411 VkMemoryRequirements
* pMemoryRequirements
)
3413 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3414 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3416 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3418 pMemoryRequirements
->size
= image
->size
;
3419 pMemoryRequirements
->alignment
= image
->alignment
;
3422 void radv_GetImageMemoryRequirements2(
3424 const VkImageMemoryRequirementsInfo2
*pInfo
,
3425 VkMemoryRequirements2
*pMemoryRequirements
)
3427 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3428 &pMemoryRequirements
->memoryRequirements
);
3430 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3432 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3433 switch (ext
->sType
) {
3434 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3435 VkMemoryDedicatedRequirements
*req
=
3436 (VkMemoryDedicatedRequirements
*) ext
;
3437 req
->requiresDedicatedAllocation
= image
->shareable
;
3438 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3447 void radv_GetImageSparseMemoryRequirements(
3450 uint32_t* pSparseMemoryRequirementCount
,
3451 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3456 void radv_GetImageSparseMemoryRequirements2(
3458 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3459 uint32_t* pSparseMemoryRequirementCount
,
3460 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3465 void radv_GetDeviceMemoryCommitment(
3467 VkDeviceMemory memory
,
3468 VkDeviceSize
* pCommittedMemoryInBytes
)
3470 *pCommittedMemoryInBytes
= 0;
3473 VkResult
radv_BindBufferMemory2(VkDevice device
,
3474 uint32_t bindInfoCount
,
3475 const VkBindBufferMemoryInfo
*pBindInfos
)
3477 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3478 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3479 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3482 buffer
->bo
= mem
->bo
;
3483 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3491 VkResult
radv_BindBufferMemory(
3494 VkDeviceMemory memory
,
3495 VkDeviceSize memoryOffset
)
3497 const VkBindBufferMemoryInfo info
= {
3498 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3501 .memoryOffset
= memoryOffset
3504 return radv_BindBufferMemory2(device
, 1, &info
);
3507 VkResult
radv_BindImageMemory2(VkDevice device
,
3508 uint32_t bindInfoCount
,
3509 const VkBindImageMemoryInfo
*pBindInfos
)
3511 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3512 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3513 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3516 image
->bo
= mem
->bo
;
3517 image
->offset
= pBindInfos
[i
].memoryOffset
;
3527 VkResult
radv_BindImageMemory(
3530 VkDeviceMemory memory
,
3531 VkDeviceSize memoryOffset
)
3533 const VkBindImageMemoryInfo info
= {
3534 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3537 .memoryOffset
= memoryOffset
3540 return radv_BindImageMemory2(device
, 1, &info
);
3545 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3546 const VkSparseBufferMemoryBindInfo
*bind
)
3548 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3550 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3551 struct radv_device_memory
*mem
= NULL
;
3553 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3554 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3556 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3557 bind
->pBinds
[i
].resourceOffset
,
3558 bind
->pBinds
[i
].size
,
3559 mem
? mem
->bo
: NULL
,
3560 bind
->pBinds
[i
].memoryOffset
);
3565 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3566 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3568 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3570 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3571 struct radv_device_memory
*mem
= NULL
;
3573 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3574 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3576 device
->ws
->buffer_virtual_bind(image
->bo
,
3577 bind
->pBinds
[i
].resourceOffset
,
3578 bind
->pBinds
[i
].size
,
3579 mem
? mem
->bo
: NULL
,
3580 bind
->pBinds
[i
].memoryOffset
);
3584 VkResult
radv_QueueBindSparse(
3586 uint32_t bindInfoCount
,
3587 const VkBindSparseInfo
* pBindInfo
,
3590 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3591 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3592 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3593 bool fence_emitted
= false;
3597 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3598 struct radv_winsys_sem_info sem_info
;
3599 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3600 radv_sparse_buffer_bind_memory(queue
->device
,
3601 pBindInfo
[i
].pBufferBinds
+ j
);
3604 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3605 radv_sparse_image_opaque_bind_memory(queue
->device
,
3606 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3610 result
= radv_alloc_sem_info(queue
->device
->instance
,
3612 pBindInfo
[i
].waitSemaphoreCount
,
3613 pBindInfo
[i
].pWaitSemaphores
,
3614 pBindInfo
[i
].signalSemaphoreCount
,
3615 pBindInfo
[i
].pSignalSemaphores
,
3617 if (result
!= VK_SUCCESS
)
3620 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3621 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3622 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3627 radv_loge("failed to submit CS %d\n", i
);
3631 fence_emitted
= true;
3633 fence
->submitted
= true;
3636 radv_free_sem_info(&sem_info
);
3641 if (!fence_emitted
) {
3642 result
= radv_signal_fence(queue
, fence
);
3643 if (result
!= VK_SUCCESS
)
3646 fence
->submitted
= true;
3652 VkResult
radv_CreateFence(
3654 const VkFenceCreateInfo
* pCreateInfo
,
3655 const VkAllocationCallbacks
* pAllocator
,
3658 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3659 const VkExportFenceCreateInfo
*export
=
3660 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3661 VkExternalFenceHandleTypeFlags handleTypes
=
3662 export
? export
->handleTypes
: 0;
3664 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3666 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3669 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3671 fence
->fence_wsi
= NULL
;
3672 fence
->submitted
= false;
3673 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
3674 fence
->temp_syncobj
= 0;
3675 if (device
->always_use_syncobj
|| handleTypes
) {
3676 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3678 vk_free2(&device
->alloc
, pAllocator
, fence
);
3679 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3681 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3682 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3684 fence
->fence
= NULL
;
3686 fence
->fence
= device
->ws
->create_fence();
3687 if (!fence
->fence
) {
3688 vk_free2(&device
->alloc
, pAllocator
, fence
);
3689 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3694 *pFence
= radv_fence_to_handle(fence
);
3699 void radv_DestroyFence(
3702 const VkAllocationCallbacks
* pAllocator
)
3704 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3705 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3710 if (fence
->temp_syncobj
)
3711 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3713 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3715 device
->ws
->destroy_fence(fence
->fence
);
3716 if (fence
->fence_wsi
)
3717 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3718 vk_free2(&device
->alloc
, pAllocator
, fence
);
3722 uint64_t radv_get_current_time(void)
3725 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3726 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3729 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3731 uint64_t current_time
= radv_get_current_time();
3733 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3735 return current_time
+ timeout
;
3739 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount
, const VkFence
*pFences
)
3741 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3742 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3743 if (fence
->fence
== NULL
|| fence
->syncobj
||
3744 fence
->temp_syncobj
||
3745 (!fence
->signalled
&& !fence
->submitted
))
3751 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3753 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3754 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3755 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3761 VkResult
radv_WaitForFences(
3763 uint32_t fenceCount
,
3764 const VkFence
* pFences
,
3768 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3769 timeout
= radv_get_absolute_timeout(timeout
);
3771 if (device
->always_use_syncobj
&&
3772 radv_all_fences_syncobj(fenceCount
, pFences
))
3774 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3776 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3778 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3779 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3780 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3783 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3786 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3789 if (!waitAll
&& fenceCount
> 1) {
3790 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3791 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(fenceCount
, pFences
)) {
3792 uint32_t wait_count
= 0;
3793 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3795 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3797 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3798 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3800 if (fence
->signalled
) {
3805 fences
[wait_count
++] = fence
->fence
;
3808 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3809 waitAll
, timeout
- radv_get_current_time());
3812 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3815 while(radv_get_current_time() <= timeout
) {
3816 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3817 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3824 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3825 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3826 bool expired
= false;
3828 if (fence
->temp_syncobj
) {
3829 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3834 if (fence
->syncobj
) {
3835 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3840 if (fence
->signalled
)
3844 if (!fence
->submitted
) {
3845 while(radv_get_current_time() <= timeout
&&
3849 if (!fence
->submitted
)
3852 /* Recheck as it may have been set by
3853 * submitting operations. */
3855 if (fence
->signalled
)
3859 expired
= device
->ws
->fence_wait(device
->ws
,
3866 if (fence
->fence_wsi
) {
3867 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3868 if (result
!= VK_SUCCESS
)
3872 fence
->signalled
= true;
3878 VkResult
radv_ResetFences(VkDevice _device
,
3879 uint32_t fenceCount
,
3880 const VkFence
*pFences
)
3882 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3884 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3885 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3886 fence
->submitted
= fence
->signalled
= false;
3888 /* Per spec, we first restore the permanent payload, and then reset, so
3889 * having a temp syncobj should not skip resetting the permanent syncobj. */
3890 if (fence
->temp_syncobj
) {
3891 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3892 fence
->temp_syncobj
= 0;
3895 if (fence
->syncobj
) {
3896 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3903 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3905 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3906 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3908 if (fence
->temp_syncobj
) {
3909 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3910 return success
? VK_SUCCESS
: VK_NOT_READY
;
3913 if (fence
->syncobj
) {
3914 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3915 return success
? VK_SUCCESS
: VK_NOT_READY
;
3918 if (fence
->signalled
)
3920 if (!fence
->submitted
)
3921 return VK_NOT_READY
;
3923 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3924 return VK_NOT_READY
;
3926 if (fence
->fence_wsi
) {
3927 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3929 if (result
!= VK_SUCCESS
) {
3930 if (result
== VK_TIMEOUT
)
3931 return VK_NOT_READY
;
3939 // Queue semaphore functions
3941 VkResult
radv_CreateSemaphore(
3943 const VkSemaphoreCreateInfo
* pCreateInfo
,
3944 const VkAllocationCallbacks
* pAllocator
,
3945 VkSemaphore
* pSemaphore
)
3947 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3948 const VkExportSemaphoreCreateInfo
*export
=
3949 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
3950 VkExternalSemaphoreHandleTypeFlags handleTypes
=
3951 export
? export
->handleTypes
: 0;
3953 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
3955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3957 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3959 sem
->temp_syncobj
= 0;
3960 /* create a syncobject if we are going to export this semaphore */
3961 if (device
->always_use_syncobj
|| handleTypes
) {
3962 assert (device
->physical_device
->rad_info
.has_syncobj
);
3963 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
3965 vk_free2(&device
->alloc
, pAllocator
, sem
);
3966 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3970 sem
->sem
= device
->ws
->create_sem(device
->ws
);
3972 vk_free2(&device
->alloc
, pAllocator
, sem
);
3973 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3978 *pSemaphore
= radv_semaphore_to_handle(sem
);
3982 void radv_DestroySemaphore(
3984 VkSemaphore _semaphore
,
3985 const VkAllocationCallbacks
* pAllocator
)
3987 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3988 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
3993 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
3995 device
->ws
->destroy_sem(sem
->sem
);
3996 vk_free2(&device
->alloc
, pAllocator
, sem
);
3999 VkResult
radv_CreateEvent(
4001 const VkEventCreateInfo
* pCreateInfo
,
4002 const VkAllocationCallbacks
* pAllocator
,
4005 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4006 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4011 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4013 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4015 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4016 RADV_BO_PRIORITY_FENCE
);
4018 vk_free2(&device
->alloc
, pAllocator
, event
);
4019 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4022 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4024 *pEvent
= radv_event_to_handle(event
);
4029 void radv_DestroyEvent(
4032 const VkAllocationCallbacks
* pAllocator
)
4034 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4035 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4039 device
->ws
->buffer_destroy(event
->bo
);
4040 vk_free2(&device
->alloc
, pAllocator
, event
);
4043 VkResult
radv_GetEventStatus(
4047 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4049 if (*event
->map
== 1)
4050 return VK_EVENT_SET
;
4051 return VK_EVENT_RESET
;
4054 VkResult
radv_SetEvent(
4058 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4064 VkResult
radv_ResetEvent(
4068 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4074 VkResult
radv_CreateBuffer(
4076 const VkBufferCreateInfo
* pCreateInfo
,
4077 const VkAllocationCallbacks
* pAllocator
,
4080 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4081 struct radv_buffer
*buffer
;
4083 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4085 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4086 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4088 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4090 buffer
->size
= pCreateInfo
->size
;
4091 buffer
->usage
= pCreateInfo
->usage
;
4094 buffer
->flags
= pCreateInfo
->flags
;
4096 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4097 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4099 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4100 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4101 align64(buffer
->size
, 4096),
4102 4096, 0, RADEON_FLAG_VIRTUAL
,
4103 RADV_BO_PRIORITY_VIRTUAL
);
4105 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4106 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4110 *pBuffer
= radv_buffer_to_handle(buffer
);
4115 void radv_DestroyBuffer(
4118 const VkAllocationCallbacks
* pAllocator
)
4120 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4121 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4126 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4127 device
->ws
->buffer_destroy(buffer
->bo
);
4129 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4132 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4134 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4136 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4137 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4141 static inline unsigned
4142 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
4145 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4147 return image
->surface
.u
.legacy
.tiling_index
[level
];
4150 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4152 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4156 radv_init_dcc_control_reg(struct radv_device
*device
,
4157 struct radv_image_view
*iview
)
4159 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4160 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4161 unsigned max_compressed_block_size
;
4162 unsigned independent_64b_blocks
;
4164 if (!radv_image_has_dcc(iview
->image
))
4167 if (iview
->image
->info
.samples
> 1) {
4168 if (iview
->image
->surface
.bpe
== 1)
4169 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4170 else if (iview
->image
->surface
.bpe
== 2)
4171 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4174 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4175 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4176 * dGPU and 64 for APU because all of our APUs to date use
4177 * DIMMs which have a request granularity size of 64B while all
4178 * other chips have a 32B request size.
4180 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4183 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4184 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4185 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4186 /* If this DCC image is potentially going to be used in texture
4187 * fetches, we need some special settings.
4189 independent_64b_blocks
= 1;
4190 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4192 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4193 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4194 * big as possible for better compression state.
4196 independent_64b_blocks
= 0;
4197 max_compressed_block_size
= max_uncompressed_block_size
;
4200 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4201 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4202 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4203 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
4207 radv_initialise_color_surface(struct radv_device
*device
,
4208 struct radv_color_buffer_info
*cb
,
4209 struct radv_image_view
*iview
)
4211 const struct vk_format_description
*desc
;
4212 unsigned ntype
, format
, swap
, endian
;
4213 unsigned blend_clamp
= 0, blend_bypass
= 0;
4215 const struct radeon_surf
*surf
= &iview
->image
->surface
;
4217 desc
= vk_format_description(iview
->vk_format
);
4219 memset(cb
, 0, sizeof(*cb
));
4221 /* Intensity is implemented as Red, so treat it that way. */
4222 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4224 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4226 cb
->cb_color_base
= va
>> 8;
4228 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4229 struct gfx9_surf_meta_flags meta
;
4230 if (iview
->image
->dcc_offset
)
4231 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
4233 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
4235 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
4236 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4237 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4238 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4240 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
4241 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
4243 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4244 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4246 cb
->cb_color_base
+= level_info
->offset
>> 8;
4247 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4248 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
4250 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4251 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4252 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
4254 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4255 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4256 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4258 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4260 if (radv_image_has_fmask(iview
->image
)) {
4261 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
4262 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4263 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4264 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4266 /* This must be set for fast clear to work without FMASK. */
4267 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
4268 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4269 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4270 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4274 /* CMASK variables */
4275 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4276 va
+= iview
->image
->cmask
.offset
;
4277 cb
->cb_color_cmask
= va
>> 8;
4279 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4280 va
+= iview
->image
->dcc_offset
;
4281 cb
->cb_dcc_base
= va
>> 8;
4282 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
4284 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4285 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4286 S_028C6C_SLICE_MAX(max_slice
);
4288 if (iview
->image
->info
.samples
> 1) {
4289 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4291 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4292 S_028C74_NUM_FRAGMENTS(log_samples
);
4295 if (radv_image_has_fmask(iview
->image
)) {
4296 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4297 cb
->cb_color_fmask
= va
>> 8;
4298 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4300 cb
->cb_color_fmask
= cb
->cb_color_base
;
4303 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4305 vk_format_get_first_non_void_channel(iview
->vk_format
));
4306 format
= radv_translate_colorformat(iview
->vk_format
);
4307 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4308 radv_finishme("Illegal color\n");
4309 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4310 endian
= radv_colorformat_endian_swap(format
);
4312 /* blend clamp should be set for all NORM/SRGB types */
4313 if (ntype
== V_028C70_NUMBER_UNORM
||
4314 ntype
== V_028C70_NUMBER_SNORM
||
4315 ntype
== V_028C70_NUMBER_SRGB
)
4318 /* set blend bypass according to docs if SINT/UINT or
4319 8/24 COLOR variants */
4320 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4321 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4322 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4327 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4328 (format
== V_028C70_COLOR_8
||
4329 format
== V_028C70_COLOR_8_8
||
4330 format
== V_028C70_COLOR_8_8_8_8
))
4331 ->color_is_int8
= true;
4333 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4334 S_028C70_COMP_SWAP(swap
) |
4335 S_028C70_BLEND_CLAMP(blend_clamp
) |
4336 S_028C70_BLEND_BYPASS(blend_bypass
) |
4337 S_028C70_SIMPLE_FLOAT(1) |
4338 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4339 ntype
!= V_028C70_NUMBER_SNORM
&&
4340 ntype
!= V_028C70_NUMBER_SRGB
&&
4341 format
!= V_028C70_COLOR_8_24
&&
4342 format
!= V_028C70_COLOR_24_8
) |
4343 S_028C70_NUMBER_TYPE(ntype
) |
4344 S_028C70_ENDIAN(endian
);
4345 if (radv_image_has_fmask(iview
->image
)) {
4346 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4347 if (device
->physical_device
->rad_info
.chip_class
== SI
) {
4348 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4349 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4353 if (radv_image_has_cmask(iview
->image
) &&
4354 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4355 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4357 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4358 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4360 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4362 /* This must be set for fast clear to work without FMASK. */
4363 if (!radv_image_has_fmask(iview
->image
) &&
4364 device
->physical_device
->rad_info
.chip_class
== SI
) {
4365 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
4366 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4369 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4370 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4371 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4373 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
4374 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4375 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
4376 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->extent
.width
- 1) |
4377 S_028C68_MIP0_HEIGHT(iview
->extent
.height
- 1) |
4378 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4383 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4384 struct radv_image_view
*iview
)
4386 unsigned max_zplanes
= 0;
4388 assert(radv_image_is_tc_compat_htile(iview
->image
));
4390 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4391 /* Default value for 32-bit depth surfaces. */
4394 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4395 iview
->image
->info
.samples
> 1)
4398 max_zplanes
= max_zplanes
+ 1;
4400 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4401 /* Do not enable Z plane compression for 16-bit depth
4402 * surfaces because isn't supported on GFX8. Only
4403 * 32-bit depth surfaces are supported by the hardware.
4404 * This allows to maintain shader compatibility and to
4405 * reduce the number of depth decompressions.
4409 if (iview
->image
->info
.samples
<= 1)
4411 else if (iview
->image
->info
.samples
<= 4)
4422 radv_initialise_ds_surface(struct radv_device
*device
,
4423 struct radv_ds_buffer_info
*ds
,
4424 struct radv_image_view
*iview
)
4426 unsigned level
= iview
->base_mip
;
4427 unsigned format
, stencil_format
;
4428 uint64_t va
, s_offs
, z_offs
;
4429 bool stencil_only
= false;
4430 memset(ds
, 0, sizeof(*ds
));
4431 switch (iview
->image
->vk_format
) {
4432 case VK_FORMAT_D24_UNORM_S8_UINT
:
4433 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4434 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4435 ds
->offset_scale
= 2.0f
;
4437 case VK_FORMAT_D16_UNORM
:
4438 case VK_FORMAT_D16_UNORM_S8_UINT
:
4439 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4440 ds
->offset_scale
= 4.0f
;
4442 case VK_FORMAT_D32_SFLOAT
:
4443 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4444 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4445 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4446 ds
->offset_scale
= 1.0f
;
4448 case VK_FORMAT_S8_UINT
:
4449 stencil_only
= true;
4455 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4456 stencil_format
= iview
->image
->surface
.has_stencil
?
4457 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4459 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4460 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4461 S_028008_SLICE_MAX(max_slice
);
4463 ds
->db_htile_data_base
= 0;
4464 ds
->db_htile_surface
= 0;
4466 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4467 s_offs
= z_offs
= va
;
4469 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4470 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
4471 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
4473 ds
->db_z_info
= S_028038_FORMAT(format
) |
4474 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4475 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
4476 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4477 S_028038_ZRANGE_PRECISION(1);
4478 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4479 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
4481 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
4482 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
4483 ds
->db_depth_view
|= S_028008_MIPID(level
);
4485 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4486 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4488 if (radv_htile_enabled(iview
->image
, level
)) {
4489 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4491 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4492 unsigned max_zplanes
=
4493 radv_calc_decompress_on_z_planes(device
, iview
);
4495 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4496 S_028038_ITERATE_FLUSH(1);
4497 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4500 if (!iview
->image
->surface
.has_stencil
)
4501 /* Use all of the htile_buffer for depth if there's no stencil. */
4502 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4503 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4504 iview
->image
->htile_offset
;
4505 ds
->db_htile_data_base
= va
>> 8;
4506 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4507 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
4508 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
4511 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
4514 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
4516 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
4517 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
4519 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4520 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4521 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4523 if (iview
->image
->info
.samples
> 1)
4524 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4526 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4527 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4528 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
4529 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4530 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
4531 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4532 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4533 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4536 tile_mode
= stencil_tile_mode
;
4538 ds
->db_depth_info
|=
4539 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4540 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4541 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4542 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4543 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4544 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4545 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4546 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4548 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
4549 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4550 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
4551 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4553 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4556 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4557 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4558 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4560 if (radv_htile_enabled(iview
->image
, level
)) {
4561 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4563 if (!iview
->image
->surface
.has_stencil
&&
4564 !radv_image_is_tc_compat_htile(iview
->image
))
4565 /* Use all of the htile_buffer for depth if there's no stencil. */
4566 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4568 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4569 iview
->image
->htile_offset
;
4570 ds
->db_htile_data_base
= va
>> 8;
4571 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4573 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4574 unsigned max_zplanes
=
4575 radv_calc_decompress_on_z_planes(device
, iview
);
4577 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4578 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4583 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4584 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4587 VkResult
radv_CreateFramebuffer(
4589 const VkFramebufferCreateInfo
* pCreateInfo
,
4590 const VkAllocationCallbacks
* pAllocator
,
4591 VkFramebuffer
* pFramebuffer
)
4593 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4594 struct radv_framebuffer
*framebuffer
;
4596 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4598 size_t size
= sizeof(*framebuffer
) +
4599 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4600 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4601 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4602 if (framebuffer
== NULL
)
4603 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4605 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4606 framebuffer
->width
= pCreateInfo
->width
;
4607 framebuffer
->height
= pCreateInfo
->height
;
4608 framebuffer
->layers
= pCreateInfo
->layers
;
4609 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4610 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4611 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4612 framebuffer
->attachments
[i
].attachment
= iview
;
4613 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4614 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4615 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4616 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4618 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4619 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4620 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4623 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4627 void radv_DestroyFramebuffer(
4630 const VkAllocationCallbacks
* pAllocator
)
4632 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4633 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4637 vk_free2(&device
->alloc
, pAllocator
, fb
);
4640 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4642 switch (address_mode
) {
4643 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4644 return V_008F30_SQ_TEX_WRAP
;
4645 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4646 return V_008F30_SQ_TEX_MIRROR
;
4647 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4648 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4649 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4650 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4651 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4652 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4654 unreachable("illegal tex wrap mode");
4660 radv_tex_compare(VkCompareOp op
)
4663 case VK_COMPARE_OP_NEVER
:
4664 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4665 case VK_COMPARE_OP_LESS
:
4666 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4667 case VK_COMPARE_OP_EQUAL
:
4668 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4669 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4670 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4671 case VK_COMPARE_OP_GREATER
:
4672 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4673 case VK_COMPARE_OP_NOT_EQUAL
:
4674 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4675 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4676 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4677 case VK_COMPARE_OP_ALWAYS
:
4678 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4680 unreachable("illegal compare mode");
4686 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4689 case VK_FILTER_NEAREST
:
4690 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4691 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4692 case VK_FILTER_LINEAR
:
4693 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4694 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4695 case VK_FILTER_CUBIC_IMG
:
4697 fprintf(stderr
, "illegal texture filter");
4703 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4706 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4707 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4708 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4709 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4711 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4716 radv_tex_bordercolor(VkBorderColor bcolor
)
4719 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4720 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4721 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4722 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4723 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4724 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4725 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4726 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4727 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4735 radv_tex_aniso_filter(unsigned filter
)
4749 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4752 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4753 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4754 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4755 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4756 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4757 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4765 radv_get_max_anisotropy(struct radv_device
*device
,
4766 const VkSamplerCreateInfo
*pCreateInfo
)
4768 if (device
->force_aniso
>= 0)
4769 return device
->force_aniso
;
4771 if (pCreateInfo
->anisotropyEnable
&&
4772 pCreateInfo
->maxAnisotropy
> 1.0f
)
4773 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4779 radv_init_sampler(struct radv_device
*device
,
4780 struct radv_sampler
*sampler
,
4781 const VkSamplerCreateInfo
*pCreateInfo
)
4783 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4784 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4785 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
4786 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4788 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4789 vk_find_struct_const(pCreateInfo
->pNext
,
4790 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4791 if (sampler_reduction
)
4792 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4794 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4795 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4796 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4797 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4798 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4799 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4800 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4801 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4802 S_008F30_DISABLE_CUBE_WRAP(0) |
4803 S_008F30_COMPAT_MODE(is_vi
) |
4804 S_008F30_FILTER_MODE(filter_mode
));
4805 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4806 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4807 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4808 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4809 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4810 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4811 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4812 S_008F38_MIP_POINT_PRECLAMP(0) |
4813 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= VI
) |
4814 S_008F38_FILTER_PREC_FIX(1) |
4815 S_008F38_ANISO_OVERRIDE(is_vi
));
4816 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4817 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4820 VkResult
radv_CreateSampler(
4822 const VkSamplerCreateInfo
* pCreateInfo
,
4823 const VkAllocationCallbacks
* pAllocator
,
4824 VkSampler
* pSampler
)
4826 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4827 struct radv_sampler
*sampler
;
4829 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4831 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4832 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4834 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4836 radv_init_sampler(device
, sampler
, pCreateInfo
);
4837 *pSampler
= radv_sampler_to_handle(sampler
);
4842 void radv_DestroySampler(
4845 const VkAllocationCallbacks
* pAllocator
)
4847 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4848 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4852 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4855 /* vk_icd.h does not declare this function, so we declare it here to
4856 * suppress Wmissing-prototypes.
4858 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4859 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4861 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4862 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4864 /* For the full details on loader interface versioning, see
4865 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4866 * What follows is a condensed summary, to help you navigate the large and
4867 * confusing official doc.
4869 * - Loader interface v0 is incompatible with later versions. We don't
4872 * - In loader interface v1:
4873 * - The first ICD entrypoint called by the loader is
4874 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4876 * - The ICD must statically expose no other Vulkan symbol unless it is
4877 * linked with -Bsymbolic.
4878 * - Each dispatchable Vulkan handle created by the ICD must be
4879 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4880 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4881 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4882 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4883 * such loader-managed surfaces.
4885 * - Loader interface v2 differs from v1 in:
4886 * - The first ICD entrypoint called by the loader is
4887 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4888 * statically expose this entrypoint.
4890 * - Loader interface v3 differs from v2 in:
4891 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4892 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4893 * because the loader no longer does so.
4895 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
4899 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
4900 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
4903 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4904 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
4906 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
4908 /* At the moment, we support only the below handle types. */
4909 assert(pGetFdInfo
->handleType
==
4910 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4911 pGetFdInfo
->handleType
==
4912 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4914 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
4916 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4920 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
4921 VkExternalMemoryHandleTypeFlagBits handleType
,
4923 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
4925 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4927 switch (handleType
) {
4928 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
4929 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
4933 /* The valid usage section for this function says:
4935 * "handleType must not be one of the handle types defined as
4938 * So opaque handle types fall into the default "unsupported" case.
4940 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4944 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
4948 uint32_t syncobj_handle
= 0;
4949 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
4951 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4954 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
4956 *syncobj
= syncobj_handle
;
4962 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
4966 /* If we create a syncobj we do it locally so that if we have an error, we don't
4967 * leave a syncobj in an undetermined state in the fence. */
4968 uint32_t syncobj_handle
= *syncobj
;
4969 if (!syncobj_handle
) {
4970 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
4972 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4977 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
4979 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
4981 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4984 *syncobj
= syncobj_handle
;
4991 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
4992 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
4994 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4995 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
4996 uint32_t *syncobj_dst
= NULL
;
4998 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
4999 syncobj_dst
= &sem
->temp_syncobj
;
5001 syncobj_dst
= &sem
->syncobj
;
5004 switch(pImportSemaphoreFdInfo
->handleType
) {
5005 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5006 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5007 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5008 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5010 unreachable("Unhandled semaphore handle type");
5014 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5015 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5018 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5019 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5021 uint32_t syncobj_handle
;
5023 if (sem
->temp_syncobj
)
5024 syncobj_handle
= sem
->temp_syncobj
;
5026 syncobj_handle
= sem
->syncobj
;
5028 switch(pGetFdInfo
->handleType
) {
5029 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5030 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5032 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5033 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5035 if (sem
->temp_syncobj
) {
5036 close (sem
->temp_syncobj
);
5037 sem
->temp_syncobj
= 0;
5039 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5044 unreachable("Unhandled semaphore handle type");
5048 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5052 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5053 VkPhysicalDevice physicalDevice
,
5054 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5055 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5057 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5059 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5060 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5061 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5062 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5063 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5064 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5065 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5066 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5067 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5068 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5069 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5070 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5071 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5073 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5074 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5075 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5079 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5080 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5082 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5083 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5084 uint32_t *syncobj_dst
= NULL
;
5087 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5088 syncobj_dst
= &fence
->temp_syncobj
;
5090 syncobj_dst
= &fence
->syncobj
;
5093 switch(pImportFenceFdInfo
->handleType
) {
5094 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5095 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5096 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5097 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5099 unreachable("Unhandled fence handle type");
5103 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5104 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5107 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5108 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5110 uint32_t syncobj_handle
;
5112 if (fence
->temp_syncobj
)
5113 syncobj_handle
= fence
->temp_syncobj
;
5115 syncobj_handle
= fence
->syncobj
;
5117 switch(pGetFdInfo
->handleType
) {
5118 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5119 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5121 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5122 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5124 if (fence
->temp_syncobj
) {
5125 close (fence
->temp_syncobj
);
5126 fence
->temp_syncobj
= 0;
5128 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5133 unreachable("Unhandled fence handle type");
5137 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5141 void radv_GetPhysicalDeviceExternalFenceProperties(
5142 VkPhysicalDevice physicalDevice
,
5143 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5144 VkExternalFenceProperties
*pExternalFenceProperties
)
5146 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5148 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5149 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5150 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5151 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5152 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5153 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5154 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5156 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5157 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5158 pExternalFenceProperties
->externalFenceFeatures
= 0;
5163 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5164 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5165 const VkAllocationCallbacks
* pAllocator
,
5166 VkDebugReportCallbackEXT
* pCallback
)
5168 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5169 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5170 pCreateInfo
, pAllocator
, &instance
->alloc
,
5175 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5176 VkDebugReportCallbackEXT _callback
,
5177 const VkAllocationCallbacks
* pAllocator
)
5179 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5180 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5181 _callback
, pAllocator
, &instance
->alloc
);
5185 radv_DebugReportMessageEXT(VkInstance _instance
,
5186 VkDebugReportFlagsEXT flags
,
5187 VkDebugReportObjectTypeEXT objectType
,
5190 int32_t messageCode
,
5191 const char* pLayerPrefix
,
5192 const char* pMessage
)
5194 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5195 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5196 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5200 radv_GetDeviceGroupPeerMemoryFeatures(
5203 uint32_t localDeviceIndex
,
5204 uint32_t remoteDeviceIndex
,
5205 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5207 assert(localDeviceIndex
== remoteDeviceIndex
);
5209 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5210 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5211 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5212 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5215 static const VkTimeDomainEXT radv_time_domains
[] = {
5216 VK_TIME_DOMAIN_DEVICE_EXT
,
5217 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5218 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5221 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5222 VkPhysicalDevice physicalDevice
,
5223 uint32_t *pTimeDomainCount
,
5224 VkTimeDomainEXT
*pTimeDomains
)
5227 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5229 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5230 vk_outarray_append(&out
, i
) {
5231 *i
= radv_time_domains
[d
];
5235 return vk_outarray_status(&out
);
5239 radv_clock_gettime(clockid_t clock_id
)
5241 struct timespec current
;
5244 ret
= clock_gettime(clock_id
, ¤t
);
5245 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5246 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5250 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5253 VkResult
radv_GetCalibratedTimestampsEXT(
5255 uint32_t timestampCount
,
5256 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5257 uint64_t *pTimestamps
,
5258 uint64_t *pMaxDeviation
)
5260 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5261 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5263 uint64_t begin
, end
;
5264 uint64_t max_clock_period
= 0;
5266 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5268 for (d
= 0; d
< timestampCount
; d
++) {
5269 switch (pTimestampInfos
[d
].timeDomain
) {
5270 case VK_TIME_DOMAIN_DEVICE_EXT
:
5271 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5273 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5274 max_clock_period
= MAX2(max_clock_period
, device_period
);
5276 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5277 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5278 max_clock_period
= MAX2(max_clock_period
, 1);
5281 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5282 pTimestamps
[d
] = begin
;
5290 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5293 * The maximum deviation is the sum of the interval over which we
5294 * perform the sampling and the maximum period of any sampled
5295 * clock. That's because the maximum skew between any two sampled
5296 * clock edges is when the sampled clock with the largest period is
5297 * sampled at the end of that period but right at the beginning of the
5298 * sampling interval and some other clock is sampled right at the
5299 * begining of its sampling period and right at the end of the
5300 * sampling interval. Let's assume the GPU has the longest clock
5301 * period and that the application is sampling GPU and monotonic:
5304 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5305 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5309 * GPU -----_____-----_____-----_____-----_____
5312 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5313 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5315 * Interval <----------------->
5316 * Deviation <-------------------------->
5320 * m = read(monotonic) 2
5323 * We round the sample interval up by one tick to cover sampling error
5324 * in the interval clock
5327 uint64_t sample_interval
= end
- begin
+ 1;
5329 *pMaxDeviation
= sample_interval
+ max_clock_period
;