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vulkan: make VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT conditional
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29
30 #include <stdatomic.h>
31 #include <stdbool.h>
32 #include <string.h>
33 #include <unistd.h>
34 #include <fcntl.h>
35
36 #include "radv_debug.h"
37 #include "radv_private.h"
38 #include "radv_shader.h"
39 #include "radv_cs.h"
40 #include "util/disk_cache.h"
41 #include "vk_util.h"
42 #include <xf86drm.h>
43 #include <amdgpu.h>
44 #include "drm-uapi/amdgpu_drm.h"
45 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
46 #include "winsys/null/radv_null_winsys_public.h"
47 #include "ac_llvm_util.h"
48 #include "vk_format.h"
49 #include "sid.h"
50 #include "git_sha1.h"
51 #include "util/build_id.h"
52 #include "util/debug.h"
53 #include "util/mesa-sha1.h"
54 #include "util/timespec.h"
55 #include "util/u_atomic.h"
56 #include "compiler/glsl_types.h"
57 #include "util/driconf.h"
58
59 static struct radv_timeline_point *
60 radv_timeline_find_point_at_least_locked(struct radv_device *device,
61 struct radv_timeline *timeline,
62 uint64_t p);
63
64 static struct radv_timeline_point *
65 radv_timeline_add_point_locked(struct radv_device *device,
66 struct radv_timeline *timeline,
67 uint64_t p);
68
69 static void
70 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
71 struct list_head *processing_list);
72
73 static
74 void radv_destroy_semaphore_part(struct radv_device *device,
75 struct radv_semaphore_part *part);
76
77 static VkResult
78 radv_create_pthread_cond(pthread_cond_t *cond);
79
80 uint64_t radv_get_current_time(void)
81 {
82 struct timespec tv;
83 clock_gettime(CLOCK_MONOTONIC, &tv);
84 return tv.tv_nsec + tv.tv_sec*1000000000ull;
85 }
86
87 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
88 {
89 uint64_t current_time = radv_get_current_time();
90
91 timeout = MIN2(UINT64_MAX - current_time, timeout);
92
93 return current_time + timeout;
94 }
95
96 static int
97 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
98 {
99 struct mesa_sha1 ctx;
100 unsigned char sha1[20];
101 unsigned ptr_size = sizeof(void*);
102
103 memset(uuid, 0, VK_UUID_SIZE);
104 _mesa_sha1_init(&ctx);
105
106 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
107 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
108 return -1;
109
110 _mesa_sha1_update(&ctx, &family, sizeof(family));
111 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
112 _mesa_sha1_final(&ctx, sha1);
113
114 memcpy(uuid, sha1, VK_UUID_SIZE);
115 return 0;
116 }
117
118 static void
119 radv_get_driver_uuid(void *uuid)
120 {
121 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
122 }
123
124 static void
125 radv_get_device_uuid(struct radeon_info *info, void *uuid)
126 {
127 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
128 }
129
130 static uint64_t
131 radv_get_visible_vram_size(struct radv_physical_device *device)
132 {
133 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
134 }
135
136 static uint64_t
137 radv_get_vram_size(struct radv_physical_device *device)
138 {
139 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
140 }
141
142 static void
143 radv_physical_device_init_mem_types(struct radv_physical_device *device)
144 {
145 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
146 uint64_t vram_size = radv_get_vram_size(device);
147 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
148 device->memory_properties.memoryHeapCount = 0;
149 if (vram_size > 0) {
150 vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
152 .size = vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = 0,
162 };
163 }
164
165 if (visible_vram_size) {
166 visible_vram_index = device->memory_properties.memoryHeapCount++;
167 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
168 .size = visible_vram_size,
169 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
170 };
171 }
172
173 unsigned type_count = 0;
174
175 if (vram_index >= 0 || visible_vram_index >= 0) {
176 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
177 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
180 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
181 };
182 }
183
184 if (gart_index >= 0) {
185 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
186 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = gart_index,
191 };
192 }
193 if (visible_vram_index >= 0) {
194 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
195 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
198 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = visible_vram_index,
201 };
202 }
203
204 if (gart_index >= 0) {
205 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
206 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
207 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
208 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
210 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
211 .heapIndex = gart_index,
212 };
213 }
214 device->memory_properties.memoryTypeCount = type_count;
215
216 if (device->rad_info.has_l2_uncached) {
217 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
218 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
219
220 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
221 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
222 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
223
224 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
225 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
226 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
227
228 device->memory_domains[type_count] = device->memory_domains[i];
229 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = property_flags,
232 .heapIndex = mem_type.heapIndex,
233 };
234 }
235 }
236 device->memory_properties.memoryTypeCount = type_count;
237 }
238 }
239
240 static const char *
241 radv_get_compiler_string(struct radv_physical_device *pdevice)
242 {
243 if (!pdevice->use_llvm) {
244 /* Some games like SotTR apply shader workarounds if the LLVM
245 * version is too old or if the LLVM version string is
246 * missing. This gives 2-5% performance with SotTR and ACO.
247 */
248 if (driQueryOptionb(&pdevice->instance->dri_options,
249 "radv_report_llvm9_version_string")) {
250 return "ACO/LLVM 9.0.1";
251 }
252
253 return "ACO";
254 }
255
256 return "LLVM " MESA_LLVM_VERSION_STRING;
257 }
258
259 static VkResult
260 radv_physical_device_try_create(struct radv_instance *instance,
261 drmDevicePtr drm_device,
262 struct radv_physical_device **device_out)
263 {
264 VkResult result;
265 int fd = -1;
266 int master_fd = -1;
267
268 if (drm_device) {
269 const char *path = drm_device->nodes[DRM_NODE_RENDER];
270 drmVersionPtr version;
271
272 fd = open(path, O_RDWR | O_CLOEXEC);
273 if (fd < 0) {
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Could not open device '%s'", path);
276
277 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
278 }
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not get the kernel driver version for device '%s'", path);
286
287 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
288 "failed to get version %s: %m", path);
289 }
290
291 if (strcmp(version->name, "amdgpu")) {
292 drmFreeVersion(version);
293 close(fd);
294
295 if (instance->debug_flags & RADV_DEBUG_STARTUP)
296 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
297
298 return VK_ERROR_INCOMPATIBLE_DRIVER;
299 }
300 drmFreeVersion(version);
301
302 if (instance->debug_flags & RADV_DEBUG_STARTUP)
303 radv_logi("Found compatible device '%s'.", path);
304 }
305
306 struct radv_physical_device *device =
307 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
308 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
309 if (!device) {
310 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
311 goto fail_fd;
312 }
313
314 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
315 device->instance = instance;
316
317 if (drm_device) {
318 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
319 instance->perftest_flags);
320 } else {
321 device->ws = radv_null_winsys_create();
322 }
323
324 if (!device->ws) {
325 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
326 "failed to initialize winsys");
327 goto fail_alloc;
328 }
329
330 if (drm_device && instance->enabled_extensions.KHR_display) {
331 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
332 if (master_fd >= 0) {
333 uint32_t accel_working = 0;
334 struct drm_amdgpu_info request = {
335 .return_pointer = (uintptr_t)&accel_working,
336 .return_size = sizeof(accel_working),
337 .query = AMDGPU_INFO_ACCEL_WORKING
338 };
339
340 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
341 close(master_fd);
342 master_fd = -1;
343 }
344 }
345 }
346
347 device->master_fd = master_fd;
348 device->local_fd = fd;
349 device->ws->query_info(device->ws, &device->rad_info);
350
351 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
352
353 snprintf(device->name, sizeof(device->name),
354 "AMD RADV %s (%s)",
355 device->rad_info.name, radv_get_compiler_string(device));
356
357 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
358 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
359 "cannot generate UUID");
360 goto fail_wsi;
361 }
362
363 /* These flags affect shader compilation. */
364 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
365
366 /* The gpu id is already embedded in the uuid so we just pass "radv"
367 * when creating the cache.
368 */
369 char buf[VK_UUID_SIZE * 2 + 1];
370 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
371 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
372
373 if (device->rad_info.chip_class < GFX8)
374 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
375
376 radv_get_driver_uuid(&device->driver_uuid);
377 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
378
379 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
380 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
381
382 device->dcc_msaa_allowed =
383 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
384
385 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
386 device->rad_info.family != CHIP_NAVI14 &&
387 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
388
389 /* TODO: Implement NGG GS with ACO. */
390 device->use_ngg_gs = device->use_ngg && device->use_llvm;
391 device->use_ngg_streamout = false;
392
393 /* Determine the number of threads per wave for all stages. */
394 device->cs_wave_size = 64;
395 device->ps_wave_size = 64;
396 device->ge_wave_size = 64;
397
398 if (device->rad_info.chip_class >= GFX10) {
399 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
400 device->cs_wave_size = 32;
401
402 /* For pixel shaders, wave64 is recommanded. */
403 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
404 device->ps_wave_size = 32;
405
406 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
407 device->ge_wave_size = 32;
408 }
409
410 radv_physical_device_init_mem_types(device);
411
412 radv_physical_device_get_supported_extensions(device,
413 &device->supported_extensions);
414
415 if (drm_device)
416 device->bus_info = *drm_device->businfo.pci;
417
418 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
419 ac_print_gpu_info(&device->rad_info);
420
421 /* The WSI is structured as a layer on top of the driver, so this has
422 * to be the last part of initialization (at least until we get other
423 * semi-layers).
424 */
425 result = radv_init_wsi(device);
426 if (result != VK_SUCCESS) {
427 vk_error(instance, result);
428 goto fail_disk_cache;
429 }
430
431 *device_out = device;
432
433 return VK_SUCCESS;
434
435 fail_disk_cache:
436 disk_cache_destroy(device->disk_cache);
437 fail_wsi:
438 device->ws->destroy(device->ws);
439 fail_alloc:
440 vk_free(&instance->alloc, device);
441 fail_fd:
442 if (fd != -1)
443 close(fd);
444 if (master_fd != -1)
445 close(master_fd);
446 return result;
447 }
448
449 static void
450 radv_physical_device_destroy(struct radv_physical_device *device)
451 {
452 radv_finish_wsi(device);
453 device->ws->destroy(device->ws);
454 disk_cache_destroy(device->disk_cache);
455 close(device->local_fd);
456 if (device->master_fd != -1)
457 close(device->master_fd);
458 vk_free(&device->instance->alloc, device);
459 }
460
461 static void *
462 default_alloc_func(void *pUserData, size_t size, size_t align,
463 VkSystemAllocationScope allocationScope)
464 {
465 return malloc(size);
466 }
467
468 static void *
469 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
470 size_t align, VkSystemAllocationScope allocationScope)
471 {
472 return realloc(pOriginal, size);
473 }
474
475 static void
476 default_free_func(void *pUserData, void *pMemory)
477 {
478 free(pMemory);
479 }
480
481 static const VkAllocationCallbacks default_alloc = {
482 .pUserData = NULL,
483 .pfnAllocation = default_alloc_func,
484 .pfnReallocation = default_realloc_func,
485 .pfnFree = default_free_func,
486 };
487
488 static const struct debug_control radv_debug_options[] = {
489 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
490 {"nodcc", RADV_DEBUG_NO_DCC},
491 {"shaders", RADV_DEBUG_DUMP_SHADERS},
492 {"nocache", RADV_DEBUG_NO_CACHE},
493 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
494 {"nohiz", RADV_DEBUG_NO_HIZ},
495 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
496 {"allbos", RADV_DEBUG_ALL_BOS},
497 {"noibs", RADV_DEBUG_NO_IBS},
498 {"spirv", RADV_DEBUG_DUMP_SPIRV},
499 {"vmfaults", RADV_DEBUG_VM_FAULTS},
500 {"zerovram", RADV_DEBUG_ZERO_VRAM},
501 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
502 {"preoptir", RADV_DEBUG_PREOPTIR},
503 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
504 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
505 {"info", RADV_DEBUG_INFO},
506 {"errors", RADV_DEBUG_ERRORS},
507 {"startup", RADV_DEBUG_STARTUP},
508 {"checkir", RADV_DEBUG_CHECKIR},
509 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
510 {"nobinning", RADV_DEBUG_NOBINNING},
511 {"nongg", RADV_DEBUG_NO_NGG},
512 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
513 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
514 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
515 {"llvm", RADV_DEBUG_LLVM},
516 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_debug_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
524 return radv_debug_options[id].string;
525 }
526
527 static const struct debug_control radv_perftest_options[] = {
528 {"localbos", RADV_PERFTEST_LOCAL_BOS},
529 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
530 {"bolist", RADV_PERFTEST_BO_LIST},
531 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
532 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
533 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
534 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
535 {"dfsm", RADV_PERFTEST_DFSM},
536 {NULL, 0}
537 };
538
539 const char *
540 radv_get_perftest_option_name(int id)
541 {
542 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
543 return radv_perftest_options[id].string;
544 }
545
546 static void
547 radv_handle_per_app_options(struct radv_instance *instance,
548 const VkApplicationInfo *info)
549 {
550 const char *name = info ? info->pApplicationName : NULL;
551 const char *engine_name = info ? info->pEngineName : NULL;
552
553 if (name) {
554 if (!strcmp(name, "DOOM_VFR")) {
555 /* Work around a Doom VFR game bug */
556 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
557 } else if (!strcmp(name, "Fledge")) {
558 /*
559 * Zero VRAM for "The Surge 2"
560 *
561 * This avoid a hang when when rendering any level. Likely
562 * uninitialized data in an indirect draw.
563 */
564 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
565 } else if (!strcmp(name, "No Man's Sky")) {
566 /* Work around a NMS game bug */
567 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
568 } else if (!strcmp(name, "DOOMEternal")) {
569 /* Zero VRAM for Doom Eternal to fix rendering issues. */
570 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
571 } else if (!strcmp(name, "Red Dead Redemption 2")) {
572 /* Work around a RDR2 game bug */
573 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
574 }
575 }
576
577 if (engine_name) {
578 if (!strcmp(engine_name, "vkd3d")) {
579 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
580 * rendering issues.
581 */
582 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
583 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
584 /* Fix various artifacts in Detroit: Become Human */
585 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
586 RADV_DEBUG_DISCARD_TO_DEMOTE;
587 }
588 }
589
590 instance->enable_mrt_output_nan_fixup =
591 driQueryOptionb(&instance->dri_options,
592 "radv_enable_mrt_output_nan_fixup");
593
594 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
595 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
596 }
597
598 static const char radv_dri_options_xml[] =
599 DRI_CONF_BEGIN
600 DRI_CONF_SECTION_PERFORMANCE
601 DRI_CONF_ADAPTIVE_SYNC("true")
602 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
603 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
604 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
605 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
606 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
607 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
608 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
609 DRI_CONF_SECTION_END
610
611 DRI_CONF_SECTION_DEBUG
612 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
613 DRI_CONF_SECTION_END
614 DRI_CONF_END;
615
616 static void radv_init_dri_options(struct radv_instance *instance)
617 {
618 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
619 driParseConfigFiles(&instance->dri_options,
620 &instance->available_dri_options,
621 0, "radv", NULL,
622 instance->applicationName,
623 instance->applicationVersion,
624 instance->engineName,
625 instance->engineVersion);
626 }
627
628 VkResult radv_CreateInstance(
629 const VkInstanceCreateInfo* pCreateInfo,
630 const VkAllocationCallbacks* pAllocator,
631 VkInstance* pInstance)
632 {
633 struct radv_instance *instance;
634 VkResult result;
635
636 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
637 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
638 if (!instance)
639 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
640
641 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
642
643 if (pAllocator)
644 instance->alloc = *pAllocator;
645 else
646 instance->alloc = default_alloc;
647
648 if (pCreateInfo->pApplicationInfo) {
649 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
650
651 instance->applicationName =
652 vk_strdup(&instance->alloc, app->pApplicationName,
653 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
654 instance->applicationVersion = app->applicationVersion;
655
656 instance->engineName =
657 vk_strdup(&instance->alloc, app->pEngineName,
658 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
659 instance->engineVersion = app->engineVersion;
660 instance->apiVersion = app->apiVersion;
661 }
662
663 if (instance->apiVersion == 0)
664 instance->apiVersion = VK_API_VERSION_1_0;
665
666 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
667 radv_debug_options);
668
669 const char *radv_perftest_str = getenv("RADV_PERFTEST");
670 instance->perftest_flags = parse_debug_string(radv_perftest_str,
671 radv_perftest_options);
672
673 if (radv_perftest_str) {
674 /* Output warnings for famous RADV_PERFTEST options that no
675 * longer exist or are deprecated.
676 */
677 if (strstr(radv_perftest_str, "aco")) {
678 fprintf(stderr, "*******************************************************************************\n");
679 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
680 fprintf(stderr, "*******************************************************************************\n");
681 }
682 if (strstr(radv_perftest_str, "llvm")) {
683 fprintf(stderr, "*********************************************************************************\n");
684 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
685 fprintf(stderr, "*********************************************************************************\n");
686 abort();
687 }
688 }
689
690 if (instance->debug_flags & RADV_DEBUG_STARTUP)
691 radv_logi("Created an instance");
692
693 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
694 int idx;
695 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
696 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
697 radv_instance_extensions[idx].extensionName))
698 break;
699 }
700
701 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
702 !radv_instance_extensions_supported.extensions[idx]) {
703 vk_object_base_finish(&instance->base);
704 vk_free2(&default_alloc, pAllocator, instance);
705 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
706 }
707
708 instance->enabled_extensions.extensions[idx] = true;
709 }
710
711 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
712
713 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
714 /* Vulkan requires that entrypoints for extensions which have
715 * not been enabled must not be advertised.
716 */
717 if (!unchecked &&
718 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
719 &instance->enabled_extensions)) {
720 instance->dispatch.entrypoints[i] = NULL;
721 } else {
722 instance->dispatch.entrypoints[i] =
723 radv_instance_dispatch_table.entrypoints[i];
724 }
725 }
726
727 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
728 /* Vulkan requires that entrypoints for extensions which have
729 * not been enabled must not be advertised.
730 */
731 if (!unchecked &&
732 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
733 &instance->enabled_extensions)) {
734 instance->physical_device_dispatch.entrypoints[i] = NULL;
735 } else {
736 instance->physical_device_dispatch.entrypoints[i] =
737 radv_physical_device_dispatch_table.entrypoints[i];
738 }
739 }
740
741 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
742 /* Vulkan requires that entrypoints for extensions which have
743 * not been enabled must not be advertised.
744 */
745 if (!unchecked &&
746 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
747 &instance->enabled_extensions, NULL)) {
748 instance->device_dispatch.entrypoints[i] = NULL;
749 } else {
750 instance->device_dispatch.entrypoints[i] =
751 radv_device_dispatch_table.entrypoints[i];
752 }
753 }
754
755 instance->physical_devices_enumerated = false;
756 list_inithead(&instance->physical_devices);
757
758 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
759 if (result != VK_SUCCESS) {
760 vk_object_base_finish(&instance->base);
761 vk_free2(&default_alloc, pAllocator, instance);
762 return vk_error(instance, result);
763 }
764
765 glsl_type_singleton_init_or_ref();
766
767 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
768
769 radv_init_dri_options(instance);
770 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
771
772 *pInstance = radv_instance_to_handle(instance);
773
774 return VK_SUCCESS;
775 }
776
777 void radv_DestroyInstance(
778 VkInstance _instance,
779 const VkAllocationCallbacks* pAllocator)
780 {
781 RADV_FROM_HANDLE(radv_instance, instance, _instance);
782
783 if (!instance)
784 return;
785
786 list_for_each_entry_safe(struct radv_physical_device, pdevice,
787 &instance->physical_devices, link) {
788 radv_physical_device_destroy(pdevice);
789 }
790
791 vk_free(&instance->alloc, instance->engineName);
792 vk_free(&instance->alloc, instance->applicationName);
793
794 VG(VALGRIND_DESTROY_MEMPOOL(instance));
795
796 glsl_type_singleton_decref();
797
798 driDestroyOptionCache(&instance->dri_options);
799 driDestroyOptionInfo(&instance->available_dri_options);
800
801 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
802
803 vk_object_base_finish(&instance->base);
804 vk_free(&instance->alloc, instance);
805 }
806
807 static VkResult
808 radv_enumerate_physical_devices(struct radv_instance *instance)
809 {
810 if (instance->physical_devices_enumerated)
811 return VK_SUCCESS;
812
813 instance->physical_devices_enumerated = true;
814
815 /* TODO: Check for more devices ? */
816 drmDevicePtr devices[8];
817 VkResult result = VK_SUCCESS;
818 int max_devices;
819
820 if (getenv("RADV_FORCE_FAMILY")) {
821 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
822 * device that allows to test the compiler without having an
823 * AMDGPU instance.
824 */
825 struct radv_physical_device *pdevice;
826
827 result = radv_physical_device_try_create(instance, NULL, &pdevice);
828 if (result != VK_SUCCESS)
829 return result;
830
831 list_addtail(&pdevice->link, &instance->physical_devices);
832 return VK_SUCCESS;
833 }
834
835 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
836
837 if (instance->debug_flags & RADV_DEBUG_STARTUP)
838 radv_logi("Found %d drm nodes", max_devices);
839
840 if (max_devices < 1)
841 return vk_error(instance, VK_SUCCESS);
842
843 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
844 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
845 devices[i]->bustype == DRM_BUS_PCI &&
846 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
847
848 struct radv_physical_device *pdevice;
849 result = radv_physical_device_try_create(instance, devices[i],
850 &pdevice);
851 /* Incompatible DRM device, skip. */
852 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
853 result = VK_SUCCESS;
854 continue;
855 }
856
857 /* Error creating the physical device, report the error. */
858 if (result != VK_SUCCESS)
859 break;
860
861 list_addtail(&pdevice->link, &instance->physical_devices);
862 }
863 }
864 drmFreeDevices(devices, max_devices);
865
866 /* If we successfully enumerated any devices, call it success */
867 return result;
868 }
869
870 VkResult radv_EnumeratePhysicalDevices(
871 VkInstance _instance,
872 uint32_t* pPhysicalDeviceCount,
873 VkPhysicalDevice* pPhysicalDevices)
874 {
875 RADV_FROM_HANDLE(radv_instance, instance, _instance);
876 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
877
878 VkResult result = radv_enumerate_physical_devices(instance);
879 if (result != VK_SUCCESS)
880 return result;
881
882 list_for_each_entry(struct radv_physical_device, pdevice,
883 &instance->physical_devices, link) {
884 vk_outarray_append(&out, i) {
885 *i = radv_physical_device_to_handle(pdevice);
886 }
887 }
888
889 return vk_outarray_status(&out);
890 }
891
892 VkResult radv_EnumeratePhysicalDeviceGroups(
893 VkInstance _instance,
894 uint32_t* pPhysicalDeviceGroupCount,
895 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
896 {
897 RADV_FROM_HANDLE(radv_instance, instance, _instance);
898 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
899 pPhysicalDeviceGroupCount);
900
901 VkResult result = radv_enumerate_physical_devices(instance);
902 if (result != VK_SUCCESS)
903 return result;
904
905 list_for_each_entry(struct radv_physical_device, pdevice,
906 &instance->physical_devices, link) {
907 vk_outarray_append(&out, p) {
908 p->physicalDeviceCount = 1;
909 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
910 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
911 p->subsetAllocation = false;
912 }
913 }
914
915 return vk_outarray_status(&out);
916 }
917
918 void radv_GetPhysicalDeviceFeatures(
919 VkPhysicalDevice physicalDevice,
920 VkPhysicalDeviceFeatures* pFeatures)
921 {
922 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
923 memset(pFeatures, 0, sizeof(*pFeatures));
924
925 *pFeatures = (VkPhysicalDeviceFeatures) {
926 .robustBufferAccess = true,
927 .fullDrawIndexUint32 = true,
928 .imageCubeArray = true,
929 .independentBlend = true,
930 .geometryShader = true,
931 .tessellationShader = true,
932 .sampleRateShading = true,
933 .dualSrcBlend = true,
934 .logicOp = true,
935 .multiDrawIndirect = true,
936 .drawIndirectFirstInstance = true,
937 .depthClamp = true,
938 .depthBiasClamp = true,
939 .fillModeNonSolid = true,
940 .depthBounds = true,
941 .wideLines = true,
942 .largePoints = true,
943 .alphaToOne = true,
944 .multiViewport = true,
945 .samplerAnisotropy = true,
946 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
947 .textureCompressionASTC_LDR = false,
948 .textureCompressionBC = true,
949 .occlusionQueryPrecise = true,
950 .pipelineStatisticsQuery = true,
951 .vertexPipelineStoresAndAtomics = true,
952 .fragmentStoresAndAtomics = true,
953 .shaderTessellationAndGeometryPointSize = true,
954 .shaderImageGatherExtended = true,
955 .shaderStorageImageExtendedFormats = true,
956 .shaderStorageImageMultisample = true,
957 .shaderUniformBufferArrayDynamicIndexing = true,
958 .shaderSampledImageArrayDynamicIndexing = true,
959 .shaderStorageBufferArrayDynamicIndexing = true,
960 .shaderStorageImageArrayDynamicIndexing = true,
961 .shaderStorageImageReadWithoutFormat = true,
962 .shaderStorageImageWriteWithoutFormat = true,
963 .shaderClipDistance = true,
964 .shaderCullDistance = true,
965 .shaderFloat64 = true,
966 .shaderInt64 = true,
967 .shaderInt16 = true,
968 .sparseBinding = true,
969 .variableMultisampleRate = true,
970 .shaderResourceMinLod = true,
971 .inheritedQueries = true,
972 };
973 }
974
975 static void
976 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
977 VkPhysicalDeviceVulkan11Features *f)
978 {
979 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
980
981 f->storageBuffer16BitAccess = true;
982 f->uniformAndStorageBuffer16BitAccess = true;
983 f->storagePushConstant16 = true;
984 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
985 f->multiview = true;
986 f->multiviewGeometryShader = true;
987 f->multiviewTessellationShader = true;
988 f->variablePointersStorageBuffer = true;
989 f->variablePointers = true;
990 f->protectedMemory = false;
991 f->samplerYcbcrConversion = true;
992 f->shaderDrawParameters = true;
993 }
994
995 static void
996 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
997 VkPhysicalDeviceVulkan12Features *f)
998 {
999 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1000
1001 f->samplerMirrorClampToEdge = true;
1002 f->drawIndirectCount = true;
1003 f->storageBuffer8BitAccess = true;
1004 f->uniformAndStorageBuffer8BitAccess = true;
1005 f->storagePushConstant8 = true;
1006 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1007 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1008 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1009 f->shaderInt8 = true;
1010
1011 f->descriptorIndexing = true;
1012 f->shaderInputAttachmentArrayDynamicIndexing = true;
1013 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1014 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1015 f->shaderUniformBufferArrayNonUniformIndexing = true;
1016 f->shaderSampledImageArrayNonUniformIndexing = true;
1017 f->shaderStorageBufferArrayNonUniformIndexing = true;
1018 f->shaderStorageImageArrayNonUniformIndexing = true;
1019 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1020 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1021 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1022 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1023 f->descriptorBindingSampledImageUpdateAfterBind = true;
1024 f->descriptorBindingStorageImageUpdateAfterBind = true;
1025 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1026 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1027 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1028 f->descriptorBindingUpdateUnusedWhilePending = true;
1029 f->descriptorBindingPartiallyBound = true;
1030 f->descriptorBindingVariableDescriptorCount = true;
1031 f->runtimeDescriptorArray = true;
1032
1033 f->samplerFilterMinmax = true;
1034 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1035 f->imagelessFramebuffer = true;
1036 f->uniformBufferStandardLayout = true;
1037 f->shaderSubgroupExtendedTypes = true;
1038 f->separateDepthStencilLayouts = true;
1039 f->hostQueryReset = true;
1040 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1041 f->bufferDeviceAddress = true;
1042 f->bufferDeviceAddressCaptureReplay = false;
1043 f->bufferDeviceAddressMultiDevice = false;
1044 f->vulkanMemoryModel = true;
1045 f->vulkanMemoryModelDeviceScope = true;
1046 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1047 f->shaderOutputViewportIndex = true;
1048 f->shaderOutputLayer = true;
1049 f->subgroupBroadcastDynamicId = true;
1050 }
1051
1052 void radv_GetPhysicalDeviceFeatures2(
1053 VkPhysicalDevice physicalDevice,
1054 VkPhysicalDeviceFeatures2 *pFeatures)
1055 {
1056 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1057 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1058
1059 VkPhysicalDeviceVulkan11Features core_1_1 = {
1060 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1061 };
1062 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1063
1064 VkPhysicalDeviceVulkan12Features core_1_2 = {
1065 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1066 };
1067 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1068
1069 #define CORE_FEATURE(major, minor, feature) \
1070 features->feature = core_##major##_##minor.feature
1071
1072 vk_foreach_struct(ext, pFeatures->pNext) {
1073 switch (ext->sType) {
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1075 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1076 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1077 CORE_FEATURE(1, 1, variablePointers);
1078 break;
1079 }
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1081 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1082 CORE_FEATURE(1, 1, multiview);
1083 CORE_FEATURE(1, 1, multiviewGeometryShader);
1084 CORE_FEATURE(1, 1, multiviewTessellationShader);
1085 break;
1086 }
1087 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1088 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1089 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1090 CORE_FEATURE(1, 1, shaderDrawParameters);
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1094 VkPhysicalDeviceProtectedMemoryFeatures *features =
1095 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1096 CORE_FEATURE(1, 1, protectedMemory);
1097 break;
1098 }
1099 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1100 VkPhysicalDevice16BitStorageFeatures *features =
1101 (VkPhysicalDevice16BitStorageFeatures*)ext;
1102 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1103 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1104 CORE_FEATURE(1, 1, storagePushConstant16);
1105 CORE_FEATURE(1, 1, storageInputOutput16);
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1109 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1110 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1111 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1112 break;
1113 }
1114 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1115 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1116 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1117 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1118 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1119 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1120 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1121 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1122 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1123 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1124 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1125 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1126 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1127 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1128 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1129 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1130 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1131 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1132 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1133 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1134 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1135 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1136 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1140 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1141 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1142 features->conditionalRendering = true;
1143 features->inheritedConditionalRendering = false;
1144 break;
1145 }
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1147 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1148 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1149 features->vertexAttributeInstanceRateDivisor = true;
1150 features->vertexAttributeInstanceRateZeroDivisor = true;
1151 break;
1152 }
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1154 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1155 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1156 features->transformFeedback = true;
1157 features->geometryStreams = !pdevice->use_ngg_streamout;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1161 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1162 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1163 CORE_FEATURE(1, 2, scalarBlockLayout);
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1167 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1168 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1169 features->memoryPriority = true;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1173 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1174 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1175 features->bufferDeviceAddress = true;
1176 features->bufferDeviceAddressCaptureReplay = false;
1177 features->bufferDeviceAddressMultiDevice = false;
1178 break;
1179 }
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1181 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1182 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1183 CORE_FEATURE(1, 2, bufferDeviceAddress);
1184 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1185 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1189 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1190 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1191 features->depthClipEnable = true;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1195 VkPhysicalDeviceHostQueryResetFeatures *features =
1196 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1197 CORE_FEATURE(1, 2, hostQueryReset);
1198 break;
1199 }
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1201 VkPhysicalDevice8BitStorageFeatures *features =
1202 (VkPhysicalDevice8BitStorageFeatures *)ext;
1203 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1204 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1205 CORE_FEATURE(1, 2, storagePushConstant8);
1206 break;
1207 }
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1209 VkPhysicalDeviceShaderFloat16Int8Features *features =
1210 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1211 CORE_FEATURE(1, 2, shaderFloat16);
1212 CORE_FEATURE(1, 2, shaderInt8);
1213 break;
1214 }
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1216 VkPhysicalDeviceShaderAtomicInt64Features *features =
1217 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1218 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1219 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1220 break;
1221 }
1222 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1223 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1224 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1225 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1229 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1230 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1231
1232 features->inlineUniformBlock = true;
1233 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1234 break;
1235 }
1236 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1237 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1238 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1239 features->computeDerivativeGroupQuads = false;
1240 features->computeDerivativeGroupLinear = true;
1241 break;
1242 }
1243 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1244 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1245 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1246 features->ycbcrImageArrays = true;
1247 break;
1248 }
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1250 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1251 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1252 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1256 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1257 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1258 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1262 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1263 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1264 CORE_FEATURE(1, 2, imagelessFramebuffer);
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1268 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1269 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1270 features->pipelineExecutableInfo = true;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1274 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1275 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1276 features->shaderSubgroupClock = true;
1277 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1278 break;
1279 }
1280 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1281 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1282 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1283 features->texelBufferAlignment = true;
1284 break;
1285 }
1286 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1287 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1288 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1289 CORE_FEATURE(1, 2, timelineSemaphore);
1290 break;
1291 }
1292 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1293 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1294 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1295 features->subgroupSizeControl = true;
1296 features->computeFullSubgroups = true;
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1300 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1301 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1302 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1303 break;
1304 }
1305 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1306 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1307 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1308 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1309 break;
1310 }
1311 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1312 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1313 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1314 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1315 break;
1316 }
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1318 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1322 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1326 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1327 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1328 features->rectangularLines = false;
1329 features->bresenhamLines = true;
1330 features->smoothLines = false;
1331 features->stippledRectangularLines = false;
1332 features->stippledBresenhamLines = true;
1333 features->stippledSmoothLines = false;
1334 break;
1335 }
1336 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1337 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1338 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1339 features->overallocationBehavior = true;
1340 break;
1341 }
1342 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1343 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1344 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1345 features->robustBufferAccess2 = true;
1346 features->robustImageAccess2 = true;
1347 features->nullDescriptor = true;
1348 break;
1349 }
1350 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1351 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1352 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1353 features->customBorderColors = true;
1354 features->customBorderColorWithoutFormat = true;
1355 break;
1356 }
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1358 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1359 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1360 features->privateData = true;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1364 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1365 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1366 features-> pipelineCreationCacheControl = true;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1370 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1371 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1372 CORE_FEATURE(1, 2, vulkanMemoryModel);
1373 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1374 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1375 break;
1376 }
1377 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1378 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1379 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1380 features->extendedDynamicState = true;
1381 break;
1382 }
1383 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1384 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1385 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1386 features->robustImageAccess = true;
1387 break;
1388 }
1389 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1390 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1391 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1392 features->shaderBufferFloat32Atomics = true;
1393 features->shaderBufferFloat32AtomicAdd = false;
1394 features->shaderBufferFloat64Atomics = true;
1395 features->shaderBufferFloat64AtomicAdd = false;
1396 features->shaderSharedFloat32Atomics = true;
1397 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1398 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1399 features->shaderSharedFloat64Atomics = true;
1400 features->shaderSharedFloat64AtomicAdd = false;
1401 features->shaderImageFloat32Atomics = true;
1402 features->shaderImageFloat32AtomicAdd = false;
1403 features->sparseImageFloat32Atomics = false;
1404 features->sparseImageFloat32AtomicAdd = false;
1405 break;
1406 }
1407 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1408 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1409 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1410 features->formatA4R4G4B4 = true;
1411 features->formatA4B4G4R4 = true;
1412 break;
1413 }
1414 default:
1415 break;
1416 }
1417 }
1418 #undef CORE_FEATURE
1419 }
1420
1421 static size_t
1422 radv_max_descriptor_set_size()
1423 {
1424 /* make sure that the entire descriptor set is addressable with a signed
1425 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1426 * be at most 2 GiB. the combined image & samples object count as one of
1427 * both. This limit is for the pipeline layout, not for the set layout, but
1428 * there is no set limit, so we just set a pipeline limit. I don't think
1429 * any app is going to hit this soon. */
1430 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1431 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1432 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1433 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1434 32 /* sampler, largest when combined with image */ +
1435 64 /* sampled image */ +
1436 64 /* storage image */);
1437 }
1438
1439 static uint32_t
1440 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1441 {
1442 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1443 "radv_override_uniform_offset_alignment");
1444 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1445 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1446 "not a power of two\n", uniform_offset_alignment);
1447 uniform_offset_alignment = 0;
1448 }
1449
1450 /* Take at least the hardware limit. */
1451 return MAX2(uniform_offset_alignment, 4);
1452 }
1453
1454 void radv_GetPhysicalDeviceProperties(
1455 VkPhysicalDevice physicalDevice,
1456 VkPhysicalDeviceProperties* pProperties)
1457 {
1458 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1459 VkSampleCountFlags sample_counts = 0xf;
1460
1461 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1462
1463 VkPhysicalDeviceLimits limits = {
1464 .maxImageDimension1D = (1 << 14),
1465 .maxImageDimension2D = (1 << 14),
1466 .maxImageDimension3D = (1 << 11),
1467 .maxImageDimensionCube = (1 << 14),
1468 .maxImageArrayLayers = (1 << 11),
1469 .maxTexelBufferElements = UINT32_MAX,
1470 .maxUniformBufferRange = UINT32_MAX,
1471 .maxStorageBufferRange = UINT32_MAX,
1472 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1473 .maxMemoryAllocationCount = UINT32_MAX,
1474 .maxSamplerAllocationCount = 64 * 1024,
1475 .bufferImageGranularity = 64, /* A cache line */
1476 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1477 .maxBoundDescriptorSets = MAX_SETS,
1478 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1479 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1480 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1481 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1482 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1483 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1484 .maxPerStageResources = max_descriptor_set_size,
1485 .maxDescriptorSetSamplers = max_descriptor_set_size,
1486 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1487 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1488 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1489 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1490 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1491 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1492 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1493 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1494 .maxVertexInputBindings = MAX_VBS,
1495 .maxVertexInputAttributeOffset = 2047,
1496 .maxVertexInputBindingStride = 2048,
1497 .maxVertexOutputComponents = 128,
1498 .maxTessellationGenerationLevel = 64,
1499 .maxTessellationPatchSize = 32,
1500 .maxTessellationControlPerVertexInputComponents = 128,
1501 .maxTessellationControlPerVertexOutputComponents = 128,
1502 .maxTessellationControlPerPatchOutputComponents = 120,
1503 .maxTessellationControlTotalOutputComponents = 4096,
1504 .maxTessellationEvaluationInputComponents = 128,
1505 .maxTessellationEvaluationOutputComponents = 128,
1506 .maxGeometryShaderInvocations = 127,
1507 .maxGeometryInputComponents = 64,
1508 .maxGeometryOutputComponents = 128,
1509 .maxGeometryOutputVertices = 256,
1510 .maxGeometryTotalOutputComponents = 1024,
1511 .maxFragmentInputComponents = 128,
1512 .maxFragmentOutputAttachments = 8,
1513 .maxFragmentDualSrcAttachments = 1,
1514 .maxFragmentCombinedOutputResources = 8,
1515 .maxComputeSharedMemorySize = 32768,
1516 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1517 .maxComputeWorkGroupInvocations = 1024,
1518 .maxComputeWorkGroupSize = {
1519 1024,
1520 1024,
1521 1024
1522 },
1523 .subPixelPrecisionBits = 8,
1524 .subTexelPrecisionBits = 8,
1525 .mipmapPrecisionBits = 8,
1526 .maxDrawIndexedIndexValue = UINT32_MAX,
1527 .maxDrawIndirectCount = UINT32_MAX,
1528 .maxSamplerLodBias = 16,
1529 .maxSamplerAnisotropy = 16,
1530 .maxViewports = MAX_VIEWPORTS,
1531 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1532 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1533 .viewportSubPixelBits = 8,
1534 .minMemoryMapAlignment = 4096, /* A page */
1535 .minTexelBufferOffsetAlignment = 4,
1536 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1537 .minStorageBufferOffsetAlignment = 4,
1538 .minTexelOffset = -32,
1539 .maxTexelOffset = 31,
1540 .minTexelGatherOffset = -32,
1541 .maxTexelGatherOffset = 31,
1542 .minInterpolationOffset = -2,
1543 .maxInterpolationOffset = 2,
1544 .subPixelInterpolationOffsetBits = 8,
1545 .maxFramebufferWidth = (1 << 14),
1546 .maxFramebufferHeight = (1 << 14),
1547 .maxFramebufferLayers = (1 << 10),
1548 .framebufferColorSampleCounts = sample_counts,
1549 .framebufferDepthSampleCounts = sample_counts,
1550 .framebufferStencilSampleCounts = sample_counts,
1551 .framebufferNoAttachmentsSampleCounts = sample_counts,
1552 .maxColorAttachments = MAX_RTS,
1553 .sampledImageColorSampleCounts = sample_counts,
1554 .sampledImageIntegerSampleCounts = sample_counts,
1555 .sampledImageDepthSampleCounts = sample_counts,
1556 .sampledImageStencilSampleCounts = sample_counts,
1557 .storageImageSampleCounts = sample_counts,
1558 .maxSampleMaskWords = 1,
1559 .timestampComputeAndGraphics = true,
1560 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1561 .maxClipDistances = 8,
1562 .maxCullDistances = 8,
1563 .maxCombinedClipAndCullDistances = 8,
1564 .discreteQueuePriorities = 2,
1565 .pointSizeRange = { 0.0, 8191.875 },
1566 .lineWidthRange = { 0.0, 8191.875 },
1567 .pointSizeGranularity = (1.0 / 8.0),
1568 .lineWidthGranularity = (1.0 / 8.0),
1569 .strictLines = false, /* FINISHME */
1570 .standardSampleLocations = true,
1571 .optimalBufferCopyOffsetAlignment = 128,
1572 .optimalBufferCopyRowPitchAlignment = 128,
1573 .nonCoherentAtomSize = 64,
1574 };
1575
1576 *pProperties = (VkPhysicalDeviceProperties) {
1577 .apiVersion = radv_physical_device_api_version(pdevice),
1578 .driverVersion = vk_get_driver_version(),
1579 .vendorID = ATI_VENDOR_ID,
1580 .deviceID = pdevice->rad_info.pci_id,
1581 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1582 .limits = limits,
1583 .sparseProperties = {0},
1584 };
1585
1586 strcpy(pProperties->deviceName, pdevice->name);
1587 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1588 }
1589
1590 static void
1591 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1592 VkPhysicalDeviceVulkan11Properties *p)
1593 {
1594 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1595
1596 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1597 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1598 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1599 /* The LUID is for Windows. */
1600 p->deviceLUIDValid = false;
1601 p->deviceNodeMask = 0;
1602
1603 p->subgroupSize = RADV_SUBGROUP_SIZE;
1604 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1605 VK_SHADER_STAGE_COMPUTE_BIT;
1606 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1607 VK_SUBGROUP_FEATURE_VOTE_BIT |
1608 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1609 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1610 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1611 VK_SUBGROUP_FEATURE_QUAD_BIT |
1612 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1613 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1614 p->subgroupQuadOperationsInAllStages = true;
1615
1616 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1617 p->maxMultiviewViewCount = MAX_VIEWS;
1618 p->maxMultiviewInstanceIndex = INT_MAX;
1619 p->protectedNoFault = false;
1620 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1621 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1622 }
1623
1624 static void
1625 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1626 VkPhysicalDeviceVulkan12Properties *p)
1627 {
1628 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1629
1630 p->driverID = VK_DRIVER_ID_MESA_RADV;
1631 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1632 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1633 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1634 radv_get_compiler_string(pdevice));
1635 p->conformanceVersion = (VkConformanceVersion) {
1636 .major = 1,
1637 .minor = 2,
1638 .subminor = 3,
1639 .patch = 0,
1640 };
1641
1642 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1643 * controlled by the same config register.
1644 */
1645 if (pdevice->rad_info.has_packed_math_16bit) {
1646 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1647 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1648 } else {
1649 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1650 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1651 }
1652
1653 /* With LLVM, do not allow both preserving and flushing denorms because
1654 * different shaders in the same pipeline can have different settings and
1655 * this won't work for merged shaders. To make it work, this requires LLVM
1656 * support for changing the register. The same logic applies for the
1657 * rounding modes because they are configured with the same config
1658 * register.
1659 */
1660 p->shaderDenormFlushToZeroFloat32 = true;
1661 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1662 p->shaderRoundingModeRTEFloat32 = true;
1663 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1664 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1665
1666 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1667 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1668 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1669 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1670 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1671
1672 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1673 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1674 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1675 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1676 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1677
1678 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1679 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1680 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1681 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1682 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1683 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1684 p->robustBufferAccessUpdateAfterBind = false;
1685 p->quadDivergentImplicitLod = false;
1686
1687 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1688 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1689 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1690 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1691 32 /* sampler, largest when combined with image */ +
1692 64 /* sampled image */ +
1693 64 /* storage image */);
1694 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1695 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1696 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1697 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1698 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1699 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1700 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1701 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1702 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1703 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1704 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1705 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1706 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1707 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1708 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1709
1710 /* We support all of the depth resolve modes */
1711 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1712 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1713 VK_RESOLVE_MODE_MIN_BIT_KHR |
1714 VK_RESOLVE_MODE_MAX_BIT_KHR;
1715
1716 /* Average doesn't make sense for stencil so we don't support that */
1717 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1718 VK_RESOLVE_MODE_MIN_BIT_KHR |
1719 VK_RESOLVE_MODE_MAX_BIT_KHR;
1720
1721 p->independentResolveNone = true;
1722 p->independentResolve = true;
1723
1724 /* GFX6-8 only support single channel min/max filter. */
1725 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1726 p->filterMinmaxSingleComponentFormats = true;
1727
1728 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1729
1730 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1731 }
1732
1733 void radv_GetPhysicalDeviceProperties2(
1734 VkPhysicalDevice physicalDevice,
1735 VkPhysicalDeviceProperties2 *pProperties)
1736 {
1737 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1738 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1739
1740 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1741 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1742 };
1743 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1744
1745 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1746 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1747 };
1748 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1749
1750 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1751 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1752 sizeof(core_##major##_##minor.core_property))
1753
1754 #define CORE_PROPERTY(major, minor, property) \
1755 CORE_RENAMED_PROPERTY(major, minor, property, property)
1756
1757 vk_foreach_struct(ext, pProperties->pNext) {
1758 switch (ext->sType) {
1759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1760 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1761 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1762 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1763 break;
1764 }
1765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1766 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1767 CORE_PROPERTY(1, 1, deviceUUID);
1768 CORE_PROPERTY(1, 1, driverUUID);
1769 CORE_PROPERTY(1, 1, deviceLUID);
1770 CORE_PROPERTY(1, 1, deviceLUIDValid);
1771 break;
1772 }
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1774 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1775 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1776 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1777 break;
1778 }
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1780 VkPhysicalDevicePointClippingProperties *properties =
1781 (VkPhysicalDevicePointClippingProperties*)ext;
1782 CORE_PROPERTY(1, 1, pointClippingBehavior);
1783 break;
1784 }
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1786 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1787 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1788 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1789 break;
1790 }
1791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1792 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1793 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1794 properties->minImportedHostPointerAlignment = 4096;
1795 break;
1796 }
1797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1798 VkPhysicalDeviceSubgroupProperties *properties =
1799 (VkPhysicalDeviceSubgroupProperties*)ext;
1800 CORE_PROPERTY(1, 1, subgroupSize);
1801 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1802 subgroupSupportedStages);
1803 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1804 subgroupSupportedOperations);
1805 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1806 subgroupQuadOperationsInAllStages);
1807 break;
1808 }
1809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1810 VkPhysicalDeviceMaintenance3Properties *properties =
1811 (VkPhysicalDeviceMaintenance3Properties*)ext;
1812 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1813 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1814 break;
1815 }
1816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1817 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1818 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1819 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1820 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1821 break;
1822 }
1823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1824 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1825 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1826
1827 /* Shader engines. */
1828 properties->shaderEngineCount =
1829 pdevice->rad_info.max_se;
1830 properties->shaderArraysPerEngineCount =
1831 pdevice->rad_info.max_sh_per_se;
1832 properties->computeUnitsPerShaderArray =
1833 pdevice->rad_info.min_good_cu_per_sa;
1834 properties->simdPerComputeUnit =
1835 pdevice->rad_info.num_simd_per_compute_unit;
1836 properties->wavefrontsPerSimd =
1837 pdevice->rad_info.max_wave64_per_simd;
1838 properties->wavefrontSize = 64;
1839
1840 /* SGPR. */
1841 properties->sgprsPerSimd =
1842 pdevice->rad_info.num_physical_sgprs_per_simd;
1843 properties->minSgprAllocation =
1844 pdevice->rad_info.min_sgpr_alloc;
1845 properties->maxSgprAllocation =
1846 pdevice->rad_info.max_sgpr_alloc;
1847 properties->sgprAllocationGranularity =
1848 pdevice->rad_info.sgpr_alloc_granularity;
1849
1850 /* VGPR. */
1851 properties->vgprsPerSimd =
1852 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1853 properties->minVgprAllocation =
1854 pdevice->rad_info.min_wave64_vgpr_alloc;
1855 properties->maxVgprAllocation =
1856 pdevice->rad_info.max_vgpr_alloc;
1857 properties->vgprAllocationGranularity =
1858 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1859 break;
1860 }
1861 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1862 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1863 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1864
1865 properties->shaderCoreFeatures = 0;
1866 properties->activeComputeUnitCount =
1867 pdevice->rad_info.num_good_compute_units;
1868 break;
1869 }
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1871 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1872 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1873 properties->maxVertexAttribDivisor = UINT32_MAX;
1874 break;
1875 }
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1877 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1878 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1879 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1880 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1881 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1882 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1883 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1884 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1885 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1886 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1887 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1888 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1889 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1890 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1891 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1892 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1893 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1894 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1895 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1896 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1897 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1898 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1899 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1900 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1901 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1902 break;
1903 }
1904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1905 VkPhysicalDeviceProtectedMemoryProperties *properties =
1906 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1907 CORE_PROPERTY(1, 1, protectedNoFault);
1908 break;
1909 }
1910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1911 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1912 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1913 properties->primitiveOverestimationSize = 0;
1914 properties->maxExtraPrimitiveOverestimationSize = 0;
1915 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1916 properties->primitiveUnderestimation = false;
1917 properties->conservativePointAndLineRasterization = false;
1918 properties->degenerateTrianglesRasterized = false;
1919 properties->degenerateLinesRasterized = false;
1920 properties->fullyCoveredFragmentShaderInputVariable = false;
1921 properties->conservativeRasterizationPostDepthCoverage = false;
1922 break;
1923 }
1924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1925 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1926 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1927 properties->pciDomain = pdevice->bus_info.domain;
1928 properties->pciBus = pdevice->bus_info.bus;
1929 properties->pciDevice = pdevice->bus_info.dev;
1930 properties->pciFunction = pdevice->bus_info.func;
1931 break;
1932 }
1933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1934 VkPhysicalDeviceDriverProperties *properties =
1935 (VkPhysicalDeviceDriverProperties *) ext;
1936 CORE_PROPERTY(1, 2, driverID);
1937 CORE_PROPERTY(1, 2, driverName);
1938 CORE_PROPERTY(1, 2, driverInfo);
1939 CORE_PROPERTY(1, 2, conformanceVersion);
1940 break;
1941 }
1942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1943 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1944 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1945 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1946 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1947 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1948 properties->maxTransformFeedbackStreamDataSize = 512;
1949 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1950 properties->maxTransformFeedbackBufferDataStride = 512;
1951 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1952 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1953 properties->transformFeedbackRasterizationStreamSelect = false;
1954 properties->transformFeedbackDraw = true;
1955 break;
1956 }
1957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1958 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1959 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1960
1961 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1962 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1963 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1964 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1965 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1966 break;
1967 }
1968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1969 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1970 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1971 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1972 VK_SAMPLE_COUNT_4_BIT |
1973 VK_SAMPLE_COUNT_8_BIT;
1974 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1975 properties->sampleLocationCoordinateRange[0] = 0.0f;
1976 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1977 properties->sampleLocationSubPixelBits = 4;
1978 properties->variableSampleLocations = false;
1979 break;
1980 }
1981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1982 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1983 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1984 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1985 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1986 CORE_PROPERTY(1, 2, independentResolveNone);
1987 CORE_PROPERTY(1, 2, independentResolve);
1988 break;
1989 }
1990 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1991 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1992 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1993 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1994 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1995 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1996 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1997 break;
1998 }
1999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2000 VkPhysicalDeviceFloatControlsProperties *properties =
2001 (VkPhysicalDeviceFloatControlsProperties *)ext;
2002 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2003 CORE_PROPERTY(1, 2, roundingModeIndependence);
2004 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2005 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2006 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2007 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2008 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2009 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2010 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2011 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2012 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2013 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2019 break;
2020 }
2021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2022 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2023 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2024 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2025 break;
2026 }
2027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2028 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2029 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2030 props->minSubgroupSize = 64;
2031 props->maxSubgroupSize = 64;
2032 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2033 props->requiredSubgroupSizeStages = 0;
2034
2035 if (pdevice->rad_info.chip_class >= GFX10) {
2036 /* Only GFX10+ supports wave32. */
2037 props->minSubgroupSize = 32;
2038 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2039 }
2040 break;
2041 }
2042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2043 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2044 break;
2045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2046 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2047 break;
2048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2049 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2050 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2051 props->lineSubPixelPrecisionBits = 4;
2052 break;
2053 }
2054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2055 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2056 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2057 properties->robustStorageBufferAccessSizeAlignment = 4;
2058 properties->robustUniformBufferAccessSizeAlignment = 4;
2059 break;
2060 }
2061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2062 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2063 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2064 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2065 break;
2066 }
2067 default:
2068 break;
2069 }
2070 }
2071 }
2072
2073 static void radv_get_physical_device_queue_family_properties(
2074 struct radv_physical_device* pdevice,
2075 uint32_t* pCount,
2076 VkQueueFamilyProperties** pQueueFamilyProperties)
2077 {
2078 int num_queue_families = 1;
2079 int idx;
2080 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2081 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2082 num_queue_families++;
2083
2084 if (pQueueFamilyProperties == NULL) {
2085 *pCount = num_queue_families;
2086 return;
2087 }
2088
2089 if (!*pCount)
2090 return;
2091
2092 idx = 0;
2093 if (*pCount >= 1) {
2094 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2095 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2096 VK_QUEUE_COMPUTE_BIT |
2097 VK_QUEUE_TRANSFER_BIT |
2098 VK_QUEUE_SPARSE_BINDING_BIT,
2099 .queueCount = 1,
2100 .timestampValidBits = 64,
2101 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2102 };
2103 idx++;
2104 }
2105
2106 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2107 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2108 if (*pCount > idx) {
2109 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2110 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2111 VK_QUEUE_TRANSFER_BIT |
2112 VK_QUEUE_SPARSE_BINDING_BIT,
2113 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2114 .timestampValidBits = 64,
2115 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2116 };
2117 idx++;
2118 }
2119 }
2120 *pCount = idx;
2121 }
2122
2123 void radv_GetPhysicalDeviceQueueFamilyProperties(
2124 VkPhysicalDevice physicalDevice,
2125 uint32_t* pCount,
2126 VkQueueFamilyProperties* pQueueFamilyProperties)
2127 {
2128 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2129 if (!pQueueFamilyProperties) {
2130 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2131 return;
2132 }
2133 VkQueueFamilyProperties *properties[] = {
2134 pQueueFamilyProperties + 0,
2135 pQueueFamilyProperties + 1,
2136 pQueueFamilyProperties + 2,
2137 };
2138 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2139 assert(*pCount <= 3);
2140 }
2141
2142 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2143 VkPhysicalDevice physicalDevice,
2144 uint32_t* pCount,
2145 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2146 {
2147 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2148 if (!pQueueFamilyProperties) {
2149 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2150 return;
2151 }
2152 VkQueueFamilyProperties *properties[] = {
2153 &pQueueFamilyProperties[0].queueFamilyProperties,
2154 &pQueueFamilyProperties[1].queueFamilyProperties,
2155 &pQueueFamilyProperties[2].queueFamilyProperties,
2156 };
2157 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2158 assert(*pCount <= 3);
2159 }
2160
2161 void radv_GetPhysicalDeviceMemoryProperties(
2162 VkPhysicalDevice physicalDevice,
2163 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2164 {
2165 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2166
2167 *pMemoryProperties = physical_device->memory_properties;
2168 }
2169
2170 static void
2171 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2172 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2173 {
2174 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2175 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2176 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2177 uint64_t vram_size = radv_get_vram_size(device);
2178 uint64_t gtt_size = device->rad_info.gart_size;
2179 uint64_t heap_budget, heap_usage;
2180
2181 /* For all memory heaps, the computation of budget is as follow:
2182 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2183 *
2184 * The Vulkan spec 1.1.97 says that the budget should include any
2185 * currently allocated device memory.
2186 *
2187 * Note that the application heap usages are not really accurate (eg.
2188 * in presence of shared buffers).
2189 */
2190 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2191 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2192
2193 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2194 heap_usage = device->ws->query_value(device->ws,
2195 RADEON_ALLOCATED_VRAM);
2196
2197 heap_budget = vram_size -
2198 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2199 heap_usage;
2200
2201 memoryBudget->heapBudget[heap_index] = heap_budget;
2202 memoryBudget->heapUsage[heap_index] = heap_usage;
2203 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM_VIS);
2206
2207 heap_budget = visible_vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else {
2214 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2215
2216 heap_usage = device->ws->query_value(device->ws,
2217 RADEON_ALLOCATED_GTT);
2218
2219 heap_budget = gtt_size -
2220 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2221 heap_usage;
2222
2223 memoryBudget->heapBudget[heap_index] = heap_budget;
2224 memoryBudget->heapUsage[heap_index] = heap_usage;
2225 }
2226 }
2227
2228 /* The heapBudget and heapUsage values must be zero for array elements
2229 * greater than or equal to
2230 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2231 */
2232 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2233 memoryBudget->heapBudget[i] = 0;
2234 memoryBudget->heapUsage[i] = 0;
2235 }
2236 }
2237
2238 void radv_GetPhysicalDeviceMemoryProperties2(
2239 VkPhysicalDevice physicalDevice,
2240 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2241 {
2242 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2243 &pMemoryProperties->memoryProperties);
2244
2245 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2246 vk_find_struct(pMemoryProperties->pNext,
2247 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2248 if (memory_budget)
2249 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2250 }
2251
2252 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2253 VkDevice _device,
2254 VkExternalMemoryHandleTypeFlagBits handleType,
2255 const void *pHostPointer,
2256 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2257 {
2258 RADV_FROM_HANDLE(radv_device, device, _device);
2259
2260 switch (handleType)
2261 {
2262 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2263 const struct radv_physical_device *physical_device = device->physical_device;
2264 uint32_t memoryTypeBits = 0;
2265 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2266 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2267 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2268 memoryTypeBits = (1 << i);
2269 break;
2270 }
2271 }
2272 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2273 return VK_SUCCESS;
2274 }
2275 default:
2276 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2277 }
2278 }
2279
2280 static enum radeon_ctx_priority
2281 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2282 {
2283 /* Default to MEDIUM when a specific global priority isn't requested */
2284 if (!pObj)
2285 return RADEON_CTX_PRIORITY_MEDIUM;
2286
2287 switch(pObj->globalPriority) {
2288 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2289 return RADEON_CTX_PRIORITY_REALTIME;
2290 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2291 return RADEON_CTX_PRIORITY_HIGH;
2292 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2293 return RADEON_CTX_PRIORITY_MEDIUM;
2294 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2295 return RADEON_CTX_PRIORITY_LOW;
2296 default:
2297 unreachable("Illegal global priority value");
2298 return RADEON_CTX_PRIORITY_INVALID;
2299 }
2300 }
2301
2302 static int
2303 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2304 uint32_t queue_family_index, int idx,
2305 VkDeviceQueueCreateFlags flags,
2306 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2307 {
2308 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2309 queue->device = device;
2310 queue->queue_family_index = queue_family_index;
2311 queue->queue_idx = idx;
2312 queue->priority = radv_get_queue_global_priority(global_priority);
2313 queue->flags = flags;
2314 queue->hw_ctx = NULL;
2315
2316 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2317 if (result != VK_SUCCESS)
2318 return vk_error(device->instance, result);
2319
2320 list_inithead(&queue->pending_submissions);
2321 pthread_mutex_init(&queue->pending_mutex, NULL);
2322
2323 pthread_mutex_init(&queue->thread_mutex, NULL);
2324 queue->thread_submission = NULL;
2325 queue->thread_running = queue->thread_exit = false;
2326 result = radv_create_pthread_cond(&queue->thread_cond);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 return VK_SUCCESS;
2331 }
2332
2333 static void
2334 radv_queue_finish(struct radv_queue *queue)
2335 {
2336 if (queue->thread_running) {
2337 p_atomic_set(&queue->thread_exit, true);
2338 pthread_cond_broadcast(&queue->thread_cond);
2339 pthread_join(queue->submission_thread, NULL);
2340 }
2341 pthread_cond_destroy(&queue->thread_cond);
2342 pthread_mutex_destroy(&queue->pending_mutex);
2343 pthread_mutex_destroy(&queue->thread_mutex);
2344
2345 if (queue->hw_ctx)
2346 queue->device->ws->ctx_destroy(queue->hw_ctx);
2347
2348 if (queue->initial_full_flush_preamble_cs)
2349 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2350 if (queue->initial_preamble_cs)
2351 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2352 if (queue->continue_preamble_cs)
2353 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2354 if (queue->descriptor_bo)
2355 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2356 if (queue->scratch_bo)
2357 queue->device->ws->buffer_destroy(queue->scratch_bo);
2358 if (queue->esgs_ring_bo)
2359 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2360 if (queue->gsvs_ring_bo)
2361 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2362 if (queue->tess_rings_bo)
2363 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2364 if (queue->gds_bo)
2365 queue->device->ws->buffer_destroy(queue->gds_bo);
2366 if (queue->gds_oa_bo)
2367 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2368 if (queue->compute_scratch_bo)
2369 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2370 }
2371
2372 static void
2373 radv_bo_list_init(struct radv_bo_list *bo_list)
2374 {
2375 pthread_mutex_init(&bo_list->mutex, NULL);
2376 bo_list->list.count = bo_list->capacity = 0;
2377 bo_list->list.bos = NULL;
2378 }
2379
2380 static void
2381 radv_bo_list_finish(struct radv_bo_list *bo_list)
2382 {
2383 free(bo_list->list.bos);
2384 pthread_mutex_destroy(&bo_list->mutex);
2385 }
2386
2387 VkResult radv_bo_list_add(struct radv_device *device,
2388 struct radeon_winsys_bo *bo)
2389 {
2390 struct radv_bo_list *bo_list = &device->bo_list;
2391
2392 if (bo->is_local)
2393 return VK_SUCCESS;
2394
2395 if (unlikely(!device->use_global_bo_list))
2396 return VK_SUCCESS;
2397
2398 pthread_mutex_lock(&bo_list->mutex);
2399 if (bo_list->list.count == bo_list->capacity) {
2400 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2401 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2402
2403 if (!data) {
2404 pthread_mutex_unlock(&bo_list->mutex);
2405 return VK_ERROR_OUT_OF_HOST_MEMORY;
2406 }
2407
2408 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2409 bo_list->capacity = capacity;
2410 }
2411
2412 bo_list->list.bos[bo_list->list.count++] = bo;
2413 pthread_mutex_unlock(&bo_list->mutex);
2414 return VK_SUCCESS;
2415 }
2416
2417 void radv_bo_list_remove(struct radv_device *device,
2418 struct radeon_winsys_bo *bo)
2419 {
2420 struct radv_bo_list *bo_list = &device->bo_list;
2421
2422 if (bo->is_local)
2423 return;
2424
2425 if (unlikely(!device->use_global_bo_list))
2426 return;
2427
2428 pthread_mutex_lock(&bo_list->mutex);
2429 /* Loop the list backwards so we find the most recently added
2430 * memory first. */
2431 for(unsigned i = bo_list->list.count; i-- > 0;) {
2432 if (bo_list->list.bos[i] == bo) {
2433 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2434 --bo_list->list.count;
2435 break;
2436 }
2437 }
2438 pthread_mutex_unlock(&bo_list->mutex);
2439 }
2440
2441 static void
2442 radv_device_init_gs_info(struct radv_device *device)
2443 {
2444 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2445 device->physical_device->rad_info.family);
2446 }
2447
2448 static int radv_get_device_extension_index(const char *name)
2449 {
2450 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2451 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2452 return i;
2453 }
2454 return -1;
2455 }
2456
2457 static int
2458 radv_get_int_debug_option(const char *name, int default_value)
2459 {
2460 const char *str;
2461 int result;
2462
2463 str = getenv(name);
2464 if (!str) {
2465 result = default_value;
2466 } else {
2467 char *endptr;
2468
2469 result = strtol(str, &endptr, 0);
2470 if (str == endptr) {
2471 /* No digits founs. */
2472 result = default_value;
2473 }
2474 }
2475
2476 return result;
2477 }
2478
2479 static bool radv_thread_trace_enabled()
2480 {
2481 return radv_get_int_debug_option("RADV_THREAD_TRACE", -1) >= 0 ||
2482 getenv("RADV_THREAD_TRACE_TRIGGER");
2483 }
2484
2485 static void
2486 radv_device_init_dispatch(struct radv_device *device)
2487 {
2488 const struct radv_instance *instance = device->physical_device->instance;
2489 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2490 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2491
2492 if (radv_thread_trace_enabled()) {
2493 /* Use device entrypoints from the SQTT layer if enabled. */
2494 dispatch_table_layer = &sqtt_device_dispatch_table;
2495 }
2496
2497 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2498 /* Vulkan requires that entrypoints for extensions which have not been
2499 * enabled must not be advertised.
2500 */
2501 if (!unchecked &&
2502 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2503 &instance->enabled_extensions,
2504 &device->enabled_extensions)) {
2505 device->dispatch.entrypoints[i] = NULL;
2506 } else if (dispatch_table_layer &&
2507 dispatch_table_layer->entrypoints[i]) {
2508 device->dispatch.entrypoints[i] =
2509 dispatch_table_layer->entrypoints[i];
2510 } else {
2511 device->dispatch.entrypoints[i] =
2512 radv_device_dispatch_table.entrypoints[i];
2513 }
2514 }
2515 }
2516
2517 static VkResult
2518 radv_create_pthread_cond(pthread_cond_t *cond)
2519 {
2520 pthread_condattr_t condattr;
2521 if (pthread_condattr_init(&condattr)) {
2522 return VK_ERROR_INITIALIZATION_FAILED;
2523 }
2524
2525 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2526 pthread_condattr_destroy(&condattr);
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529 if (pthread_cond_init(cond, &condattr)) {
2530 pthread_condattr_destroy(&condattr);
2531 return VK_ERROR_INITIALIZATION_FAILED;
2532 }
2533 pthread_condattr_destroy(&condattr);
2534 return VK_SUCCESS;
2535 }
2536
2537 static VkResult
2538 check_physical_device_features(VkPhysicalDevice physicalDevice,
2539 const VkPhysicalDeviceFeatures *features)
2540 {
2541 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2542 VkPhysicalDeviceFeatures supported_features;
2543 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2544 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2545 VkBool32 *enabled_feature = (VkBool32 *)features;
2546 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2547 for (uint32_t i = 0; i < num_features; i++) {
2548 if (enabled_feature[i] && !supported_feature[i])
2549 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2550 }
2551
2552 return VK_SUCCESS;
2553 }
2554
2555 static VkResult radv_device_init_border_color(struct radv_device *device)
2556 {
2557 device->border_color_data.bo =
2558 device->ws->buffer_create(device->ws,
2559 RADV_BORDER_COLOR_BUFFER_SIZE,
2560 4096,
2561 RADEON_DOMAIN_VRAM,
2562 RADEON_FLAG_CPU_ACCESS |
2563 RADEON_FLAG_READ_ONLY |
2564 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2565 RADV_BO_PRIORITY_SHADER);
2566
2567 if (device->border_color_data.bo == NULL)
2568 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2569
2570 device->border_color_data.colors_gpu_ptr =
2571 device->ws->buffer_map(device->border_color_data.bo);
2572 if (!device->border_color_data.colors_gpu_ptr)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2575
2576 return VK_SUCCESS;
2577 }
2578
2579 static void radv_device_finish_border_color(struct radv_device *device)
2580 {
2581 if (device->border_color_data.bo) {
2582 device->ws->buffer_destroy(device->border_color_data.bo);
2583
2584 pthread_mutex_destroy(&device->border_color_data.mutex);
2585 }
2586 }
2587
2588 VkResult
2589 _radv_device_set_lost(struct radv_device *device,
2590 const char *file, int line,
2591 const char *msg, ...)
2592 {
2593 VkResult err;
2594 va_list ap;
2595
2596 p_atomic_inc(&device->lost);
2597
2598 va_start(ap, msg);
2599 err = __vk_errorv(device->physical_device->instance, device,
2600 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2601 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2602 va_end(ap);
2603
2604 return err;
2605 }
2606
2607 VkResult radv_CreateDevice(
2608 VkPhysicalDevice physicalDevice,
2609 const VkDeviceCreateInfo* pCreateInfo,
2610 const VkAllocationCallbacks* pAllocator,
2611 VkDevice* pDevice)
2612 {
2613 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2614 VkResult result;
2615 struct radv_device *device;
2616
2617 bool keep_shader_info = false;
2618 bool robust_buffer_access = false;
2619 bool overallocation_disallowed = false;
2620 bool custom_border_colors = false;
2621
2622 /* Check enabled features */
2623 if (pCreateInfo->pEnabledFeatures) {
2624 result = check_physical_device_features(physicalDevice,
2625 pCreateInfo->pEnabledFeatures);
2626 if (result != VK_SUCCESS)
2627 return result;
2628
2629 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2630 robust_buffer_access = true;
2631 }
2632
2633 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2634 switch (ext->sType) {
2635 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2636 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2637 result = check_physical_device_features(physicalDevice,
2638 &features->features);
2639 if (result != VK_SUCCESS)
2640 return result;
2641
2642 if (features->features.robustBufferAccess)
2643 robust_buffer_access = true;
2644 break;
2645 }
2646 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2647 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2648 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2649 overallocation_disallowed = true;
2650 break;
2651 }
2652 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2653 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2654 custom_border_colors = border_color_features->customBorderColors;
2655 break;
2656 }
2657 default:
2658 break;
2659 }
2660 }
2661
2662 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2663 sizeof(*device), 8,
2664 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2665 if (!device)
2666 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2667
2668 vk_device_init(&device->vk, pCreateInfo,
2669 &physical_device->instance->alloc, pAllocator);
2670
2671 device->instance = physical_device->instance;
2672 device->physical_device = physical_device;
2673
2674 device->ws = physical_device->ws;
2675
2676 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2677 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2678 int index = radv_get_device_extension_index(ext_name);
2679 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2680 vk_free(&device->vk.alloc, device);
2681 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2682 }
2683
2684 device->enabled_extensions.extensions[index] = true;
2685 }
2686
2687 radv_device_init_dispatch(device);
2688
2689 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2690
2691 /* With update after bind we can't attach bo's to the command buffer
2692 * from the descriptor set anymore, so we have to use a global BO list.
2693 */
2694 device->use_global_bo_list =
2695 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2696 device->enabled_extensions.EXT_descriptor_indexing ||
2697 device->enabled_extensions.EXT_buffer_device_address ||
2698 device->enabled_extensions.KHR_buffer_device_address;
2699
2700 device->robust_buffer_access = robust_buffer_access;
2701
2702 mtx_init(&device->shader_slab_mutex, mtx_plain);
2703 list_inithead(&device->shader_slabs);
2704
2705 device->overallocation_disallowed = overallocation_disallowed;
2706 mtx_init(&device->overallocation_mutex, mtx_plain);
2707
2708 radv_bo_list_init(&device->bo_list);
2709
2710 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2711 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2712 uint32_t qfi = queue_create->queueFamilyIndex;
2713 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2714 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2715
2716 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2717
2718 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2719 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2720 if (!device->queues[qfi]) {
2721 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2722 goto fail;
2723 }
2724
2725 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2726
2727 device->queue_count[qfi] = queue_create->queueCount;
2728
2729 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2730 result = radv_queue_init(device, &device->queues[qfi][q],
2731 qfi, q, queue_create->flags,
2732 global_priority);
2733 if (result != VK_SUCCESS)
2734 goto fail;
2735 }
2736 }
2737
2738 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2739 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2740
2741 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2742 device->dfsm_allowed = device->pbb_allowed &&
2743 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2744
2745 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2746
2747 /* The maximum number of scratch waves. Scratch space isn't divided
2748 * evenly between CUs. The number is only a function of the number of CUs.
2749 * We can decrease the constant to decrease the scratch buffer size.
2750 *
2751 * sctx->scratch_waves must be >= the maximum possible size of
2752 * 1 threadgroup, so that the hw doesn't hang from being unable
2753 * to start any.
2754 *
2755 * The recommended value is 4 per CU at most. Higher numbers don't
2756 * bring much benefit, but they still occupy chip resources (think
2757 * async compute). I've seen ~2% performance difference between 4 and 32.
2758 */
2759 uint32_t max_threads_per_block = 2048;
2760 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2761 max_threads_per_block / 64);
2762
2763 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2764
2765 if (device->physical_device->rad_info.chip_class >= GFX7) {
2766 /* If the KMD allows it (there is a KMD hw register for it),
2767 * allow launching waves out-of-order.
2768 */
2769 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2770 }
2771
2772 radv_device_init_gs_info(device);
2773
2774 device->tess_offchip_block_dw_size =
2775 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2776
2777 if (getenv("RADV_TRACE_FILE")) {
2778 const char *filename = getenv("RADV_TRACE_FILE");
2779
2780 keep_shader_info = true;
2781
2782 if (!radv_init_trace(device))
2783 goto fail;
2784
2785 fprintf(stderr, "*****************************************************************************\n");
2786 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2787 fprintf(stderr, "*****************************************************************************\n");
2788
2789 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2790
2791 /* Wait for idle after every draw/dispatch to identify the
2792 * first bad call.
2793 */
2794 device->instance->debug_flags |= RADV_DEBUG_SYNC_SHADERS;
2795
2796 radv_dump_enabled_options(device, stderr);
2797 }
2798
2799 if (radv_thread_trace_enabled()) {
2800 fprintf(stderr, "*************************************************\n");
2801 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2802 fprintf(stderr, "*************************************************\n");
2803
2804 if (device->physical_device->rad_info.chip_class < GFX8) {
2805 fprintf(stderr, "GPU hardware not supported: refer to "
2806 "the RGP documentation for the list of "
2807 "supported GPUs!\n");
2808 abort();
2809 }
2810
2811 /* Default buffer size set to 1MB per SE. */
2812 device->thread_trace_buffer_size =
2813 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2814 device->thread_trace_start_frame = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2815
2816 const char *trigger_file = getenv("RADV_THREAD_TRACE_TRIGGER");
2817 if (trigger_file)
2818 device->thread_trace_trigger_file = strdup(trigger_file);
2819
2820 if (!radv_thread_trace_init(device))
2821 goto fail;
2822 }
2823
2824 if (getenv("RADV_TRAP_HANDLER")) {
2825 /* TODO: Add support for more hardware. */
2826 assert(device->physical_device->rad_info.chip_class == GFX8);
2827
2828 fprintf(stderr, "**********************************************************************\n");
2829 fprintf(stderr, "* WARNING: RADV_TRAP_HANDLER is experimental and only for debugging! *\n");
2830 fprintf(stderr, "**********************************************************************\n");
2831
2832 /* To get the disassembly of the faulty shaders, we have to
2833 * keep some shader info around.
2834 */
2835 keep_shader_info = true;
2836
2837 if (!radv_trap_handler_init(device))
2838 goto fail;
2839 }
2840
2841 device->keep_shader_info = keep_shader_info;
2842 result = radv_device_init_meta(device);
2843 if (result != VK_SUCCESS)
2844 goto fail;
2845
2846 radv_device_init_msaa(device);
2847
2848 /* If the border color extension is enabled, let's create the buffer we need. */
2849 if (custom_border_colors) {
2850 result = radv_device_init_border_color(device);
2851 if (result != VK_SUCCESS)
2852 goto fail;
2853 }
2854
2855 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2856 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2857 if (!device->empty_cs[family])
2858 goto fail;
2859
2860 switch (family) {
2861 case RADV_QUEUE_GENERAL:
2862 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2863 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2864 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2865 break;
2866 case RADV_QUEUE_COMPUTE:
2867 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2868 radeon_emit(device->empty_cs[family], 0);
2869 break;
2870 }
2871
2872 result = device->ws->cs_finalize(device->empty_cs[family]);
2873 if (result != VK_SUCCESS)
2874 goto fail;
2875 }
2876
2877 if (device->physical_device->rad_info.chip_class >= GFX7)
2878 cik_create_gfx_config(device);
2879
2880 VkPipelineCacheCreateInfo ci;
2881 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2882 ci.pNext = NULL;
2883 ci.flags = 0;
2884 ci.pInitialData = NULL;
2885 ci.initialDataSize = 0;
2886 VkPipelineCache pc;
2887 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2888 &ci, NULL, &pc);
2889 if (result != VK_SUCCESS)
2890 goto fail_meta;
2891
2892 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2893
2894 result = radv_create_pthread_cond(&device->timeline_cond);
2895 if (result != VK_SUCCESS)
2896 goto fail_mem_cache;
2897
2898 device->force_aniso =
2899 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2900 if (device->force_aniso >= 0) {
2901 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2902 1 << util_logbase2(device->force_aniso));
2903 }
2904
2905 *pDevice = radv_device_to_handle(device);
2906 return VK_SUCCESS;
2907
2908 fail_mem_cache:
2909 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2910 fail_meta:
2911 radv_device_finish_meta(device);
2912 fail:
2913 radv_bo_list_finish(&device->bo_list);
2914
2915 radv_thread_trace_finish(device);
2916 free(device->thread_trace_trigger_file);
2917
2918 radv_trap_handler_finish(device);
2919
2920 if (device->trace_bo)
2921 device->ws->buffer_destroy(device->trace_bo);
2922
2923 if (device->gfx_init)
2924 device->ws->buffer_destroy(device->gfx_init);
2925
2926 radv_device_finish_border_color(device);
2927
2928 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2929 for (unsigned q = 0; q < device->queue_count[i]; q++)
2930 radv_queue_finish(&device->queues[i][q]);
2931 if (device->queue_count[i])
2932 vk_free(&device->vk.alloc, device->queues[i]);
2933 }
2934
2935 vk_free(&device->vk.alloc, device);
2936 return result;
2937 }
2938
2939 void radv_DestroyDevice(
2940 VkDevice _device,
2941 const VkAllocationCallbacks* pAllocator)
2942 {
2943 RADV_FROM_HANDLE(radv_device, device, _device);
2944
2945 if (!device)
2946 return;
2947
2948 if (device->trace_bo)
2949 device->ws->buffer_destroy(device->trace_bo);
2950
2951 if (device->gfx_init)
2952 device->ws->buffer_destroy(device->gfx_init);
2953
2954 radv_device_finish_border_color(device);
2955
2956 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2957 for (unsigned q = 0; q < device->queue_count[i]; q++)
2958 radv_queue_finish(&device->queues[i][q]);
2959 if (device->queue_count[i])
2960 vk_free(&device->vk.alloc, device->queues[i]);
2961 if (device->empty_cs[i])
2962 device->ws->cs_destroy(device->empty_cs[i]);
2963 }
2964 radv_device_finish_meta(device);
2965
2966 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2967 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2968
2969 radv_trap_handler_finish(device);
2970
2971 radv_destroy_shader_slabs(device);
2972
2973 pthread_cond_destroy(&device->timeline_cond);
2974 radv_bo_list_finish(&device->bo_list);
2975
2976 free(device->thread_trace_trigger_file);
2977 radv_thread_trace_finish(device);
2978
2979 vk_free(&device->vk.alloc, device);
2980 }
2981
2982 VkResult radv_EnumerateInstanceLayerProperties(
2983 uint32_t* pPropertyCount,
2984 VkLayerProperties* pProperties)
2985 {
2986 if (pProperties == NULL) {
2987 *pPropertyCount = 0;
2988 return VK_SUCCESS;
2989 }
2990
2991 /* None supported at this time */
2992 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2993 }
2994
2995 VkResult radv_EnumerateDeviceLayerProperties(
2996 VkPhysicalDevice physicalDevice,
2997 uint32_t* pPropertyCount,
2998 VkLayerProperties* pProperties)
2999 {
3000 if (pProperties == NULL) {
3001 *pPropertyCount = 0;
3002 return VK_SUCCESS;
3003 }
3004
3005 /* None supported at this time */
3006 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3007 }
3008
3009 void radv_GetDeviceQueue2(
3010 VkDevice _device,
3011 const VkDeviceQueueInfo2* pQueueInfo,
3012 VkQueue* pQueue)
3013 {
3014 RADV_FROM_HANDLE(radv_device, device, _device);
3015 struct radv_queue *queue;
3016
3017 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3018 if (pQueueInfo->flags != queue->flags) {
3019 /* From the Vulkan 1.1.70 spec:
3020 *
3021 * "The queue returned by vkGetDeviceQueue2 must have the same
3022 * flags value from this structure as that used at device
3023 * creation time in a VkDeviceQueueCreateInfo instance. If no
3024 * matching flags were specified at device creation time then
3025 * pQueue will return VK_NULL_HANDLE."
3026 */
3027 *pQueue = VK_NULL_HANDLE;
3028 return;
3029 }
3030
3031 *pQueue = radv_queue_to_handle(queue);
3032 }
3033
3034 void radv_GetDeviceQueue(
3035 VkDevice _device,
3036 uint32_t queueFamilyIndex,
3037 uint32_t queueIndex,
3038 VkQueue* pQueue)
3039 {
3040 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3041 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3042 .queueFamilyIndex = queueFamilyIndex,
3043 .queueIndex = queueIndex
3044 };
3045
3046 radv_GetDeviceQueue2(_device, &info, pQueue);
3047 }
3048
3049 static void
3050 fill_geom_tess_rings(struct radv_queue *queue,
3051 uint32_t *map,
3052 bool add_sample_positions,
3053 uint32_t esgs_ring_size,
3054 struct radeon_winsys_bo *esgs_ring_bo,
3055 uint32_t gsvs_ring_size,
3056 struct radeon_winsys_bo *gsvs_ring_bo,
3057 uint32_t tess_factor_ring_size,
3058 uint32_t tess_offchip_ring_offset,
3059 uint32_t tess_offchip_ring_size,
3060 struct radeon_winsys_bo *tess_rings_bo)
3061 {
3062 uint32_t *desc = &map[4];
3063
3064 if (esgs_ring_bo) {
3065 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3066
3067 /* stride 0, num records - size, add tid, swizzle, elsize4,
3068 index stride 64 */
3069 desc[0] = esgs_va;
3070 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3071 S_008F04_SWIZZLE_ENABLE(true);
3072 desc[2] = esgs_ring_size;
3073 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3074 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3075 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3076 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3077 S_008F0C_INDEX_STRIDE(3) |
3078 S_008F0C_ADD_TID_ENABLE(1);
3079
3080 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3081 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3082 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3083 S_008F0C_RESOURCE_LEVEL(1);
3084 } else {
3085 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3087 S_008F0C_ELEMENT_SIZE(1);
3088 }
3089
3090 /* GS entry for ES->GS ring */
3091 /* stride 0, num records - size, elsize0,
3092 index stride 0 */
3093 desc[4] = esgs_va;
3094 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3095 desc[6] = esgs_ring_size;
3096 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3097 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3098 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3099 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3100
3101 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3102 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3103 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3104 S_008F0C_RESOURCE_LEVEL(1);
3105 } else {
3106 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3107 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3108 }
3109 }
3110
3111 desc += 8;
3112
3113 if (gsvs_ring_bo) {
3114 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3115
3116 /* VS entry for GS->VS ring */
3117 /* stride 0, num records - size, elsize0,
3118 index stride 0 */
3119 desc[0] = gsvs_va;
3120 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3121 desc[2] = gsvs_ring_size;
3122 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3123 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3124 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3125 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3126
3127 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3128 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3129 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3130 S_008F0C_RESOURCE_LEVEL(1);
3131 } else {
3132 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3133 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3134 }
3135
3136 /* stride gsvs_itemsize, num records 64
3137 elsize 4, index stride 16 */
3138 /* shader will patch stride and desc[2] */
3139 desc[4] = gsvs_va;
3140 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3141 S_008F04_SWIZZLE_ENABLE(1);
3142 desc[6] = 0;
3143 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3144 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3145 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3146 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3147 S_008F0C_INDEX_STRIDE(1) |
3148 S_008F0C_ADD_TID_ENABLE(true);
3149
3150 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3151 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3152 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3153 S_008F0C_RESOURCE_LEVEL(1);
3154 } else {
3155 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3156 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3157 S_008F0C_ELEMENT_SIZE(1);
3158 }
3159
3160 }
3161
3162 desc += 8;
3163
3164 if (tess_rings_bo) {
3165 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3166 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3167
3168 desc[0] = tess_va;
3169 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3170 desc[2] = tess_factor_ring_size;
3171 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3175
3176 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3177 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3178 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3179 S_008F0C_RESOURCE_LEVEL(1);
3180 } else {
3181 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3182 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3183 }
3184
3185 desc[4] = tess_offchip_va;
3186 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3187 desc[6] = tess_offchip_ring_size;
3188 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3192
3193 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3194 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3195 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3196 S_008F0C_RESOURCE_LEVEL(1);
3197 } else {
3198 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3199 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3200 }
3201 }
3202
3203 desc += 8;
3204
3205 if (add_sample_positions) {
3206 /* add sample positions after all rings */
3207 memcpy(desc, queue->device->sample_locations_1x, 8);
3208 desc += 2;
3209 memcpy(desc, queue->device->sample_locations_2x, 16);
3210 desc += 4;
3211 memcpy(desc, queue->device->sample_locations_4x, 32);
3212 desc += 8;
3213 memcpy(desc, queue->device->sample_locations_8x, 64);
3214 }
3215 }
3216
3217 static unsigned
3218 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3219 {
3220 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3221 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3222 device->physical_device->rad_info.family != CHIP_STONEY;
3223 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3224 unsigned max_offchip_buffers;
3225 unsigned offchip_granularity;
3226 unsigned hs_offchip_param;
3227
3228 /*
3229 * Per RadeonSI:
3230 * This must be one less than the maximum number due to a hw limitation.
3231 * Various hardware bugs need thGFX7
3232 *
3233 * Per AMDVLK:
3234 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3235 * Gfx7 should limit max_offchip_buffers to 508
3236 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3237 *
3238 * Follow AMDVLK here.
3239 */
3240 if (device->physical_device->rad_info.chip_class >= GFX10) {
3241 max_offchip_buffers_per_se = 256;
3242 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3243 device->physical_device->rad_info.chip_class == GFX7 ||
3244 device->physical_device->rad_info.chip_class == GFX6)
3245 --max_offchip_buffers_per_se;
3246
3247 max_offchip_buffers = max_offchip_buffers_per_se *
3248 device->physical_device->rad_info.max_se;
3249
3250 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3251 * around by setting 4K granularity.
3252 */
3253 if (device->tess_offchip_block_dw_size == 4096) {
3254 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3255 offchip_granularity = V_03093C_X_4K_DWORDS;
3256 } else {
3257 assert(device->tess_offchip_block_dw_size == 8192);
3258 offchip_granularity = V_03093C_X_8K_DWORDS;
3259 }
3260
3261 switch (device->physical_device->rad_info.chip_class) {
3262 case GFX6:
3263 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3264 break;
3265 case GFX7:
3266 case GFX8:
3267 case GFX9:
3268 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3269 break;
3270 case GFX10:
3271 break;
3272 default:
3273 break;
3274 }
3275
3276 *max_offchip_buffers_p = max_offchip_buffers;
3277 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3278 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3279 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3280 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3281 if (device->physical_device->rad_info.chip_class >= GFX8)
3282 --max_offchip_buffers;
3283 hs_offchip_param =
3284 S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
3285 S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
3286 } else {
3287 hs_offchip_param =
3288 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3289 }
3290 return hs_offchip_param;
3291 }
3292
3293 static void
3294 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3295 struct radeon_winsys_bo *esgs_ring_bo,
3296 uint32_t esgs_ring_size,
3297 struct radeon_winsys_bo *gsvs_ring_bo,
3298 uint32_t gsvs_ring_size)
3299 {
3300 if (!esgs_ring_bo && !gsvs_ring_bo)
3301 return;
3302
3303 if (esgs_ring_bo)
3304 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3305
3306 if (gsvs_ring_bo)
3307 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3308
3309 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3310 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3311 radeon_emit(cs, esgs_ring_size >> 8);
3312 radeon_emit(cs, gsvs_ring_size >> 8);
3313 } else {
3314 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3315 radeon_emit(cs, esgs_ring_size >> 8);
3316 radeon_emit(cs, gsvs_ring_size >> 8);
3317 }
3318 }
3319
3320 static void
3321 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3322 unsigned hs_offchip_param, unsigned tf_ring_size,
3323 struct radeon_winsys_bo *tess_rings_bo)
3324 {
3325 uint64_t tf_va;
3326
3327 if (!tess_rings_bo)
3328 return;
3329
3330 tf_va = radv_buffer_get_va(tess_rings_bo);
3331
3332 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3333
3334 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3335 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3336 S_030938_SIZE(tf_ring_size / 4));
3337 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3338 tf_va >> 8);
3339
3340 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3341 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3342 S_030984_BASE_HI(tf_va >> 40));
3343 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3344 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3345 S_030944_BASE_HI(tf_va >> 40));
3346 }
3347 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3348 hs_offchip_param);
3349 } else {
3350 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3351 S_008988_SIZE(tf_ring_size / 4));
3352 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3353 tf_va >> 8);
3354 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3355 hs_offchip_param);
3356 }
3357 }
3358
3359 static void
3360 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3361 uint32_t size_per_wave, uint32_t waves,
3362 struct radeon_winsys_bo *scratch_bo)
3363 {
3364 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3365 return;
3366
3367 if (!scratch_bo)
3368 return;
3369
3370 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3371
3372 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3373 S_0286E8_WAVES(waves) |
3374 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3375 }
3376
3377 static void
3378 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3379 uint32_t size_per_wave, uint32_t waves,
3380 struct radeon_winsys_bo *compute_scratch_bo)
3381 {
3382 uint64_t scratch_va;
3383
3384 if (!compute_scratch_bo)
3385 return;
3386
3387 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3388
3389 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3390
3391 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3392 radeon_emit(cs, scratch_va);
3393 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3394 S_008F04_SWIZZLE_ENABLE(1));
3395
3396 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3397 S_00B860_WAVES(waves) |
3398 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3399 }
3400
3401 static void
3402 radv_emit_global_shader_pointers(struct radv_queue *queue,
3403 struct radeon_cmdbuf *cs,
3404 struct radeon_winsys_bo *descriptor_bo)
3405 {
3406 uint64_t va;
3407
3408 if (!descriptor_bo)
3409 return;
3410
3411 va = radv_buffer_get_va(descriptor_bo);
3412
3413 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3414
3415 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3416 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3417 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3418 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3419 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3420
3421 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3422 radv_emit_shader_pointer(queue->device, cs, regs[i],
3423 va, true);
3424 }
3425 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3426 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3427 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3428 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3429 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3430
3431 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3432 radv_emit_shader_pointer(queue->device, cs, regs[i],
3433 va, true);
3434 }
3435 } else {
3436 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3437 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3438 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3439 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3440 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3441 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3442
3443 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3444 radv_emit_shader_pointer(queue->device, cs, regs[i],
3445 va, true);
3446 }
3447 }
3448 }
3449
3450 static void
3451 radv_emit_trap_handler(struct radv_queue *queue,
3452 struct radeon_cmdbuf *cs,
3453 struct radeon_winsys_bo *tma_bo)
3454 {
3455 struct radv_device *device = queue->device;
3456 struct radeon_winsys_bo *tba_bo;
3457 uint64_t tba_va, tma_va;
3458
3459 if (!device->trap_handler_shader || !tma_bo)
3460 return;
3461
3462 tba_bo = device->trap_handler_shader->bo;
3463
3464 tba_va = radv_buffer_get_va(tba_bo) + device->trap_handler_shader->bo_offset;
3465 tma_va = radv_buffer_get_va(tma_bo);
3466
3467 radv_cs_add_buffer(queue->device->ws, cs, tba_bo);
3468 radv_cs_add_buffer(queue->device->ws, cs, tma_bo);
3469
3470 if (queue->queue_family_index == RADV_QUEUE_GENERAL) {
3471 uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS,
3472 R_00B100_SPI_SHADER_TBA_LO_VS,
3473 R_00B200_SPI_SHADER_TBA_LO_GS,
3474 R_00B300_SPI_SHADER_TBA_LO_ES,
3475 R_00B400_SPI_SHADER_TBA_LO_HS,
3476 R_00B500_SPI_SHADER_TBA_LO_LS};
3477
3478 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3479 radeon_set_sh_reg_seq(cs, regs[i], 4);
3480 radeon_emit(cs, tba_va >> 8);
3481 radeon_emit(cs, tba_va >> 40);
3482 radeon_emit(cs, tma_va >> 8);
3483 radeon_emit(cs, tma_va >> 40);
3484 }
3485 } else {
3486 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
3487 radeon_emit(cs, tba_va >> 8);
3488 radeon_emit(cs, tba_va >> 40);
3489 radeon_emit(cs, tma_va >> 8);
3490 radeon_emit(cs, tma_va >> 40);
3491 }
3492 }
3493
3494 static void
3495 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3496 {
3497 struct radv_device *device = queue->device;
3498
3499 if (device->gfx_init) {
3500 uint64_t va = radv_buffer_get_va(device->gfx_init);
3501
3502 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3503 radeon_emit(cs, va);
3504 radeon_emit(cs, va >> 32);
3505 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3506
3507 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3508 } else {
3509 si_emit_graphics(device, cs);
3510 }
3511 }
3512
3513 static void
3514 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3515 {
3516 si_emit_compute(queue->device, cs);
3517 }
3518
3519 static VkResult
3520 radv_get_preamble_cs(struct radv_queue *queue,
3521 uint32_t scratch_size_per_wave,
3522 uint32_t scratch_waves,
3523 uint32_t compute_scratch_size_per_wave,
3524 uint32_t compute_scratch_waves,
3525 uint32_t esgs_ring_size,
3526 uint32_t gsvs_ring_size,
3527 bool needs_tess_rings,
3528 bool needs_gds,
3529 bool needs_gds_oa,
3530 bool needs_sample_positions,
3531 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3532 struct radeon_cmdbuf **initial_preamble_cs,
3533 struct radeon_cmdbuf **continue_preamble_cs)
3534 {
3535 struct radeon_winsys_bo *scratch_bo = NULL;
3536 struct radeon_winsys_bo *descriptor_bo = NULL;
3537 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3538 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3539 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3540 struct radeon_winsys_bo *tess_rings_bo = NULL;
3541 struct radeon_winsys_bo *gds_bo = NULL;
3542 struct radeon_winsys_bo *gds_oa_bo = NULL;
3543 struct radeon_cmdbuf *dest_cs[3] = {0};
3544 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3545 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3546 unsigned max_offchip_buffers;
3547 unsigned hs_offchip_param = 0;
3548 unsigned tess_offchip_ring_offset;
3549 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3550 if (!queue->has_tess_rings) {
3551 if (needs_tess_rings)
3552 add_tess_rings = true;
3553 }
3554 if (!queue->has_gds) {
3555 if (needs_gds)
3556 add_gds = true;
3557 }
3558 if (!queue->has_gds_oa) {
3559 if (needs_gds_oa)
3560 add_gds_oa = true;
3561 }
3562 if (!queue->has_sample_positions) {
3563 if (needs_sample_positions)
3564 add_sample_positions = true;
3565 }
3566 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3567 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3568 &max_offchip_buffers);
3569 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3570 tess_offchip_ring_size = max_offchip_buffers *
3571 queue->device->tess_offchip_block_dw_size * 4;
3572
3573 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3574 if (scratch_size_per_wave)
3575 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3576 else
3577 scratch_waves = 0;
3578
3579 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3580 if (compute_scratch_size_per_wave)
3581 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3582 else
3583 compute_scratch_waves = 0;
3584
3585 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3586 scratch_waves <= queue->scratch_waves &&
3587 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3588 compute_scratch_waves <= queue->compute_scratch_waves &&
3589 esgs_ring_size <= queue->esgs_ring_size &&
3590 gsvs_ring_size <= queue->gsvs_ring_size &&
3591 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3592 queue->initial_preamble_cs) {
3593 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3594 *initial_preamble_cs = queue->initial_preamble_cs;
3595 *continue_preamble_cs = queue->continue_preamble_cs;
3596 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3597 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3598 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3599 *continue_preamble_cs = NULL;
3600 return VK_SUCCESS;
3601 }
3602
3603 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3604 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3605 if (scratch_size > queue_scratch_size) {
3606 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3607 scratch_size,
3608 4096,
3609 RADEON_DOMAIN_VRAM,
3610 ring_bo_flags,
3611 RADV_BO_PRIORITY_SCRATCH);
3612 if (!scratch_bo)
3613 goto fail;
3614 } else
3615 scratch_bo = queue->scratch_bo;
3616
3617 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3618 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3619 if (compute_scratch_size > compute_queue_scratch_size) {
3620 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3621 compute_scratch_size,
3622 4096,
3623 RADEON_DOMAIN_VRAM,
3624 ring_bo_flags,
3625 RADV_BO_PRIORITY_SCRATCH);
3626 if (!compute_scratch_bo)
3627 goto fail;
3628
3629 } else
3630 compute_scratch_bo = queue->compute_scratch_bo;
3631
3632 if (esgs_ring_size > queue->esgs_ring_size) {
3633 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3634 esgs_ring_size,
3635 4096,
3636 RADEON_DOMAIN_VRAM,
3637 ring_bo_flags,
3638 RADV_BO_PRIORITY_SCRATCH);
3639 if (!esgs_ring_bo)
3640 goto fail;
3641 } else {
3642 esgs_ring_bo = queue->esgs_ring_bo;
3643 esgs_ring_size = queue->esgs_ring_size;
3644 }
3645
3646 if (gsvs_ring_size > queue->gsvs_ring_size) {
3647 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3648 gsvs_ring_size,
3649 4096,
3650 RADEON_DOMAIN_VRAM,
3651 ring_bo_flags,
3652 RADV_BO_PRIORITY_SCRATCH);
3653 if (!gsvs_ring_bo)
3654 goto fail;
3655 } else {
3656 gsvs_ring_bo = queue->gsvs_ring_bo;
3657 gsvs_ring_size = queue->gsvs_ring_size;
3658 }
3659
3660 if (add_tess_rings) {
3661 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3662 tess_offchip_ring_offset + tess_offchip_ring_size,
3663 256,
3664 RADEON_DOMAIN_VRAM,
3665 ring_bo_flags,
3666 RADV_BO_PRIORITY_SCRATCH);
3667 if (!tess_rings_bo)
3668 goto fail;
3669 } else {
3670 tess_rings_bo = queue->tess_rings_bo;
3671 }
3672
3673 if (add_gds) {
3674 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3675
3676 /* 4 streamout GDS counters.
3677 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3678 */
3679 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3680 256, 4,
3681 RADEON_DOMAIN_GDS,
3682 ring_bo_flags,
3683 RADV_BO_PRIORITY_SCRATCH);
3684 if (!gds_bo)
3685 goto fail;
3686 } else {
3687 gds_bo = queue->gds_bo;
3688 }
3689
3690 if (add_gds_oa) {
3691 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3692
3693 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3694 4, 1,
3695 RADEON_DOMAIN_OA,
3696 ring_bo_flags,
3697 RADV_BO_PRIORITY_SCRATCH);
3698 if (!gds_oa_bo)
3699 goto fail;
3700 } else {
3701 gds_oa_bo = queue->gds_oa_bo;
3702 }
3703
3704 if (scratch_bo != queue->scratch_bo ||
3705 esgs_ring_bo != queue->esgs_ring_bo ||
3706 gsvs_ring_bo != queue->gsvs_ring_bo ||
3707 tess_rings_bo != queue->tess_rings_bo ||
3708 add_sample_positions) {
3709 uint32_t size = 0;
3710 if (gsvs_ring_bo || esgs_ring_bo ||
3711 tess_rings_bo || add_sample_positions) {
3712 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3713 if (add_sample_positions)
3714 size += 128; /* 64+32+16+8 = 120 bytes */
3715 }
3716 else if (scratch_bo)
3717 size = 8; /* 2 dword */
3718
3719 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3720 size,
3721 4096,
3722 RADEON_DOMAIN_VRAM,
3723 RADEON_FLAG_CPU_ACCESS |
3724 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3725 RADEON_FLAG_READ_ONLY,
3726 RADV_BO_PRIORITY_DESCRIPTOR);
3727 if (!descriptor_bo)
3728 goto fail;
3729 } else
3730 descriptor_bo = queue->descriptor_bo;
3731
3732 if (descriptor_bo != queue->descriptor_bo) {
3733 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3734 if (!map)
3735 goto fail;
3736
3737 if (scratch_bo) {
3738 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3739 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3740 S_008F04_SWIZZLE_ENABLE(1);
3741 map[0] = scratch_va;
3742 map[1] = rsrc1;
3743 }
3744
3745 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3746 fill_geom_tess_rings(queue, map, add_sample_positions,
3747 esgs_ring_size, esgs_ring_bo,
3748 gsvs_ring_size, gsvs_ring_bo,
3749 tess_factor_ring_size,
3750 tess_offchip_ring_offset,
3751 tess_offchip_ring_size,
3752 tess_rings_bo);
3753
3754 queue->device->ws->buffer_unmap(descriptor_bo);
3755 }
3756
3757 for(int i = 0; i < 3; ++i) {
3758 struct radeon_cmdbuf *cs = NULL;
3759 cs = queue->device->ws->cs_create(queue->device->ws,
3760 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3761 if (!cs)
3762 goto fail;
3763
3764 dest_cs[i] = cs;
3765
3766 if (scratch_bo)
3767 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3768
3769 /* Emit initial configuration. */
3770 switch (queue->queue_family_index) {
3771 case RADV_QUEUE_GENERAL:
3772 radv_init_graphics_state(cs, queue);
3773 break;
3774 case RADV_QUEUE_COMPUTE:
3775 radv_init_compute_state(cs, queue);
3776 break;
3777 case RADV_QUEUE_TRANSFER:
3778 break;
3779 }
3780
3781 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3782 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3783 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3784
3785 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3786 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3787 }
3788
3789 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3790 gsvs_ring_bo, gsvs_ring_size);
3791 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3792 tess_factor_ring_size, tess_rings_bo);
3793 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3794 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3795 compute_scratch_waves, compute_scratch_bo);
3796 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3797 scratch_waves, scratch_bo);
3798 radv_emit_trap_handler(queue, cs, queue->device->tma_bo);
3799
3800 if (gds_bo)
3801 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3802 if (gds_oa_bo)
3803 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3804
3805 if (queue->device->trace_bo)
3806 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3807
3808 if (queue->device->border_color_data.bo)
3809 radv_cs_add_buffer(queue->device->ws, cs,
3810 queue->device->border_color_data.bo);
3811
3812 if (i == 0) {
3813 si_cs_emit_cache_flush(cs,
3814 queue->device->physical_device->rad_info.chip_class,
3815 NULL, 0,
3816 queue->queue_family_index == RING_COMPUTE &&
3817 queue->device->physical_device->rad_info.chip_class >= GFX7,
3818 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3819 RADV_CMD_FLAG_INV_ICACHE |
3820 RADV_CMD_FLAG_INV_SCACHE |
3821 RADV_CMD_FLAG_INV_VCACHE |
3822 RADV_CMD_FLAG_INV_L2 |
3823 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3824 } else if (i == 1) {
3825 si_cs_emit_cache_flush(cs,
3826 queue->device->physical_device->rad_info.chip_class,
3827 NULL, 0,
3828 queue->queue_family_index == RING_COMPUTE &&
3829 queue->device->physical_device->rad_info.chip_class >= GFX7,
3830 RADV_CMD_FLAG_INV_ICACHE |
3831 RADV_CMD_FLAG_INV_SCACHE |
3832 RADV_CMD_FLAG_INV_VCACHE |
3833 RADV_CMD_FLAG_INV_L2 |
3834 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3835 }
3836
3837 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3838 goto fail;
3839 }
3840
3841 if (queue->initial_full_flush_preamble_cs)
3842 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3843
3844 if (queue->initial_preamble_cs)
3845 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3846
3847 if (queue->continue_preamble_cs)
3848 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3849
3850 queue->initial_full_flush_preamble_cs = dest_cs[0];
3851 queue->initial_preamble_cs = dest_cs[1];
3852 queue->continue_preamble_cs = dest_cs[2];
3853
3854 if (scratch_bo != queue->scratch_bo) {
3855 if (queue->scratch_bo)
3856 queue->device->ws->buffer_destroy(queue->scratch_bo);
3857 queue->scratch_bo = scratch_bo;
3858 }
3859 queue->scratch_size_per_wave = scratch_size_per_wave;
3860 queue->scratch_waves = scratch_waves;
3861
3862 if (compute_scratch_bo != queue->compute_scratch_bo) {
3863 if (queue->compute_scratch_bo)
3864 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3865 queue->compute_scratch_bo = compute_scratch_bo;
3866 }
3867 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3868 queue->compute_scratch_waves = compute_scratch_waves;
3869
3870 if (esgs_ring_bo != queue->esgs_ring_bo) {
3871 if (queue->esgs_ring_bo)
3872 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3873 queue->esgs_ring_bo = esgs_ring_bo;
3874 queue->esgs_ring_size = esgs_ring_size;
3875 }
3876
3877 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3878 if (queue->gsvs_ring_bo)
3879 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3880 queue->gsvs_ring_bo = gsvs_ring_bo;
3881 queue->gsvs_ring_size = gsvs_ring_size;
3882 }
3883
3884 if (tess_rings_bo != queue->tess_rings_bo) {
3885 queue->tess_rings_bo = tess_rings_bo;
3886 queue->has_tess_rings = true;
3887 }
3888
3889 if (gds_bo != queue->gds_bo) {
3890 queue->gds_bo = gds_bo;
3891 queue->has_gds = true;
3892 }
3893
3894 if (gds_oa_bo != queue->gds_oa_bo) {
3895 queue->gds_oa_bo = gds_oa_bo;
3896 queue->has_gds_oa = true;
3897 }
3898
3899 if (descriptor_bo != queue->descriptor_bo) {
3900 if (queue->descriptor_bo)
3901 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3902
3903 queue->descriptor_bo = descriptor_bo;
3904 }
3905
3906 if (add_sample_positions)
3907 queue->has_sample_positions = true;
3908
3909 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3910 *initial_preamble_cs = queue->initial_preamble_cs;
3911 *continue_preamble_cs = queue->continue_preamble_cs;
3912 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3913 *continue_preamble_cs = NULL;
3914 return VK_SUCCESS;
3915 fail:
3916 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3917 if (dest_cs[i])
3918 queue->device->ws->cs_destroy(dest_cs[i]);
3919 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3920 queue->device->ws->buffer_destroy(descriptor_bo);
3921 if (scratch_bo && scratch_bo != queue->scratch_bo)
3922 queue->device->ws->buffer_destroy(scratch_bo);
3923 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3924 queue->device->ws->buffer_destroy(compute_scratch_bo);
3925 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3926 queue->device->ws->buffer_destroy(esgs_ring_bo);
3927 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3928 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3929 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3930 queue->device->ws->buffer_destroy(tess_rings_bo);
3931 if (gds_bo && gds_bo != queue->gds_bo)
3932 queue->device->ws->buffer_destroy(gds_bo);
3933 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3934 queue->device->ws->buffer_destroy(gds_oa_bo);
3935
3936 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3937 }
3938
3939 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3940 struct radv_winsys_sem_counts *counts,
3941 int num_sems,
3942 struct radv_semaphore_part **sems,
3943 const uint64_t *timeline_values,
3944 VkFence _fence,
3945 bool is_signal)
3946 {
3947 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0, timeline_idx = 0;
3948
3949 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3950 return VK_SUCCESS;
3951
3952 for (uint32_t i = 0; i < num_sems; i++) {
3953 switch(sems[i]->kind) {
3954 case RADV_SEMAPHORE_SYNCOBJ:
3955 counts->syncobj_count++;
3956 counts->syncobj_reset_count++;
3957 break;
3958 case RADV_SEMAPHORE_WINSYS:
3959 counts->sem_count++;
3960 break;
3961 case RADV_SEMAPHORE_NONE:
3962 break;
3963 case RADV_SEMAPHORE_TIMELINE:
3964 counts->syncobj_count++;
3965 break;
3966 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3967 counts->timeline_syncobj_count++;
3968 break;
3969 }
3970 }
3971
3972 if (_fence != VK_NULL_HANDLE) {
3973 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3974
3975 struct radv_fence_part *part =
3976 fence->temporary.kind != RADV_FENCE_NONE ?
3977 &fence->temporary : &fence->permanent;
3978 if (part->kind == RADV_FENCE_SYNCOBJ)
3979 counts->syncobj_count++;
3980 }
3981
3982 if (counts->syncobj_count || counts->timeline_syncobj_count) {
3983 counts->points = (uint64_t *)malloc(
3984 sizeof(*counts->syncobj) * counts->syncobj_count +
3985 (sizeof(*counts->syncobj) + sizeof(*counts->points)) * counts->timeline_syncobj_count);
3986 if (!counts->points)
3987 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3988 counts->syncobj = (uint32_t*)(counts->points + counts->timeline_syncobj_count);
3989 }
3990
3991 if (counts->sem_count) {
3992 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3993 if (!counts->sem) {
3994 free(counts->syncobj);
3995 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3996 }
3997 }
3998
3999 non_reset_idx = counts->syncobj_reset_count;
4000
4001 for (uint32_t i = 0; i < num_sems; i++) {
4002 switch(sems[i]->kind) {
4003 case RADV_SEMAPHORE_NONE:
4004 unreachable("Empty semaphore");
4005 break;
4006 case RADV_SEMAPHORE_SYNCOBJ:
4007 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
4008 break;
4009 case RADV_SEMAPHORE_WINSYS:
4010 counts->sem[sem_idx++] = sems[i]->ws_sem;
4011 break;
4012 case RADV_SEMAPHORE_TIMELINE: {
4013 pthread_mutex_lock(&sems[i]->timeline.mutex);
4014 struct radv_timeline_point *point = NULL;
4015 if (is_signal) {
4016 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4017 } else {
4018 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4019 }
4020
4021 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4022
4023 if (point) {
4024 counts->syncobj[non_reset_idx++] = point->syncobj;
4025 } else {
4026 /* Explicitly remove the semaphore so we might not find
4027 * a point later post-submit. */
4028 sems[i] = NULL;
4029 }
4030 break;
4031 }
4032 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
4033 counts->syncobj[counts->syncobj_count + timeline_idx] = sems[i]->syncobj;
4034 counts->points[timeline_idx] = timeline_values[i];
4035 ++timeline_idx;
4036 break;
4037 }
4038 }
4039
4040 if (_fence != VK_NULL_HANDLE) {
4041 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4042
4043 struct radv_fence_part *part =
4044 fence->temporary.kind != RADV_FENCE_NONE ?
4045 &fence->temporary : &fence->permanent;
4046 if (part->kind == RADV_FENCE_SYNCOBJ)
4047 counts->syncobj[non_reset_idx++] = part->syncobj;
4048 }
4049
4050 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
4051 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
4052
4053 return VK_SUCCESS;
4054 }
4055
4056 static void
4057 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4058 {
4059 free(sem_info->wait.points);
4060 free(sem_info->wait.sem);
4061 free(sem_info->signal.points);
4062 free(sem_info->signal.sem);
4063 }
4064
4065
4066 static void radv_free_temp_syncobjs(struct radv_device *device,
4067 int num_sems,
4068 struct radv_semaphore_part *sems)
4069 {
4070 for (uint32_t i = 0; i < num_sems; i++) {
4071 radv_destroy_semaphore_part(device, sems + i);
4072 }
4073 }
4074
4075 static VkResult
4076 radv_alloc_sem_info(struct radv_device *device,
4077 struct radv_winsys_sem_info *sem_info,
4078 int num_wait_sems,
4079 struct radv_semaphore_part **wait_sems,
4080 const uint64_t *wait_values,
4081 int num_signal_sems,
4082 struct radv_semaphore_part **signal_sems,
4083 const uint64_t *signal_values,
4084 VkFence fence)
4085 {
4086 VkResult ret;
4087 memset(sem_info, 0, sizeof(*sem_info));
4088
4089 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4090 if (ret)
4091 return ret;
4092 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4093 if (ret)
4094 radv_free_sem_info(sem_info);
4095
4096 /* caller can override these */
4097 sem_info->cs_emit_wait = true;
4098 sem_info->cs_emit_signal = true;
4099 return ret;
4100 }
4101
4102 static void
4103 radv_finalize_timelines(struct radv_device *device,
4104 uint32_t num_wait_sems,
4105 struct radv_semaphore_part **wait_sems,
4106 const uint64_t *wait_values,
4107 uint32_t num_signal_sems,
4108 struct radv_semaphore_part **signal_sems,
4109 const uint64_t *signal_values,
4110 struct list_head *processing_list)
4111 {
4112 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4113 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4114 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4115 struct radv_timeline_point *point =
4116 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4117 point->wait_count -= 2;
4118 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4119 }
4120 }
4121 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4122 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4123 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4124 struct radv_timeline_point *point =
4125 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4126 signal_sems[i]->timeline.highest_submitted =
4127 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4128 point->wait_count -= 2;
4129 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4130 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4131 } else if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) {
4132 signal_sems[i]->timeline_syncobj.max_point =
4133 MAX2(signal_sems[i]->timeline_syncobj.max_point, signal_values[i]);
4134 }
4135 }
4136 }
4137
4138 static VkResult
4139 radv_sparse_buffer_bind_memory(struct radv_device *device,
4140 const VkSparseBufferMemoryBindInfo *bind)
4141 {
4142 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4143 VkResult result;
4144
4145 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4146 struct radv_device_memory *mem = NULL;
4147
4148 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4149 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4150
4151 result = device->ws->buffer_virtual_bind(buffer->bo,
4152 bind->pBinds[i].resourceOffset,
4153 bind->pBinds[i].size,
4154 mem ? mem->bo : NULL,
4155 bind->pBinds[i].memoryOffset);
4156 if (result != VK_SUCCESS)
4157 return result;
4158 }
4159
4160 return VK_SUCCESS;
4161 }
4162
4163 static VkResult
4164 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4165 const VkSparseImageOpaqueMemoryBindInfo *bind)
4166 {
4167 RADV_FROM_HANDLE(radv_image, image, bind->image);
4168 VkResult result;
4169
4170 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4171 struct radv_device_memory *mem = NULL;
4172
4173 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4174 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4175
4176 result = device->ws->buffer_virtual_bind(image->bo,
4177 bind->pBinds[i].resourceOffset,
4178 bind->pBinds[i].size,
4179 mem ? mem->bo : NULL,
4180 bind->pBinds[i].memoryOffset);
4181 if (result != VK_SUCCESS)
4182 return result;
4183 }
4184
4185 return VK_SUCCESS;
4186 }
4187
4188 static VkResult
4189 radv_get_preambles(struct radv_queue *queue,
4190 const VkCommandBuffer *cmd_buffers,
4191 uint32_t cmd_buffer_count,
4192 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4193 struct radeon_cmdbuf **initial_preamble_cs,
4194 struct radeon_cmdbuf **continue_preamble_cs)
4195 {
4196 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4197 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4198 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4199 bool tess_rings_needed = false;
4200 bool gds_needed = false;
4201 bool gds_oa_needed = false;
4202 bool sample_positions_needed = false;
4203
4204 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4206 cmd_buffers[j]);
4207
4208 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4209 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4210 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4211 cmd_buffer->compute_scratch_size_per_wave_needed);
4212 compute_waves_wanted = MAX2(compute_waves_wanted,
4213 cmd_buffer->compute_scratch_waves_wanted);
4214 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4215 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4216 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4217 gds_needed |= cmd_buffer->gds_needed;
4218 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4219 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4220 }
4221
4222 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4223 compute_scratch_size_per_wave, compute_waves_wanted,
4224 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4225 gds_needed, gds_oa_needed, sample_positions_needed,
4226 initial_full_flush_preamble_cs,
4227 initial_preamble_cs, continue_preamble_cs);
4228 }
4229
4230 struct radv_deferred_queue_submission {
4231 struct radv_queue *queue;
4232 VkCommandBuffer *cmd_buffers;
4233 uint32_t cmd_buffer_count;
4234
4235 /* Sparse bindings that happen on a queue. */
4236 VkSparseBufferMemoryBindInfo *buffer_binds;
4237 uint32_t buffer_bind_count;
4238 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4239 uint32_t image_opaque_bind_count;
4240
4241 bool flush_caches;
4242 VkShaderStageFlags wait_dst_stage_mask;
4243 struct radv_semaphore_part **wait_semaphores;
4244 uint32_t wait_semaphore_count;
4245 struct radv_semaphore_part **signal_semaphores;
4246 uint32_t signal_semaphore_count;
4247 VkFence fence;
4248
4249 uint64_t *wait_values;
4250 uint64_t *signal_values;
4251
4252 struct radv_semaphore_part *temporary_semaphore_parts;
4253 uint32_t temporary_semaphore_part_count;
4254
4255 struct list_head queue_pending_list;
4256 uint32_t submission_wait_count;
4257 struct radv_timeline_waiter *wait_nodes;
4258
4259 struct list_head processing_list;
4260 };
4261
4262 struct radv_queue_submission {
4263 const VkCommandBuffer *cmd_buffers;
4264 uint32_t cmd_buffer_count;
4265
4266 /* Sparse bindings that happen on a queue. */
4267 const VkSparseBufferMemoryBindInfo *buffer_binds;
4268 uint32_t buffer_bind_count;
4269 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4270 uint32_t image_opaque_bind_count;
4271
4272 bool flush_caches;
4273 VkPipelineStageFlags wait_dst_stage_mask;
4274 const VkSemaphore *wait_semaphores;
4275 uint32_t wait_semaphore_count;
4276 const VkSemaphore *signal_semaphores;
4277 uint32_t signal_semaphore_count;
4278 VkFence fence;
4279
4280 const uint64_t *wait_values;
4281 uint32_t wait_value_count;
4282 const uint64_t *signal_values;
4283 uint32_t signal_value_count;
4284 };
4285
4286 static VkResult
4287 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4288 uint32_t decrement,
4289 struct list_head *processing_list);
4290
4291 static VkResult
4292 radv_create_deferred_submission(struct radv_queue *queue,
4293 const struct radv_queue_submission *submission,
4294 struct radv_deferred_queue_submission **out)
4295 {
4296 struct radv_deferred_queue_submission *deferred = NULL;
4297 size_t size = sizeof(struct radv_deferred_queue_submission);
4298
4299 uint32_t temporary_count = 0;
4300 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4301 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4302 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4303 ++temporary_count;
4304 }
4305
4306 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4307 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4308 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4309 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4310 size += temporary_count * sizeof(struct radv_semaphore_part);
4311 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4312 size += submission->wait_value_count * sizeof(uint64_t);
4313 size += submission->signal_value_count * sizeof(uint64_t);
4314 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4315
4316 deferred = calloc(1, size);
4317 if (!deferred)
4318 return VK_ERROR_OUT_OF_HOST_MEMORY;
4319
4320 deferred->queue = queue;
4321
4322 deferred->cmd_buffers = (void*)(deferred + 1);
4323 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4324 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4325 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4326
4327 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4328 deferred->buffer_bind_count = submission->buffer_bind_count;
4329 memcpy(deferred->buffer_binds, submission->buffer_binds,
4330 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4331
4332 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4333 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4334 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4335 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4336
4337 deferred->flush_caches = submission->flush_caches;
4338 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4339
4340 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4341 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4342
4343 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4344 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4345
4346 deferred->fence = submission->fence;
4347
4348 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4349 deferred->temporary_semaphore_part_count = temporary_count;
4350
4351 uint32_t temporary_idx = 0;
4352 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4353 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4354 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4355 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4356 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4357 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4358 ++temporary_idx;
4359 } else
4360 deferred->wait_semaphores[i] = &semaphore->permanent;
4361 }
4362
4363 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4364 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4365 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4366 deferred->signal_semaphores[i] = &semaphore->temporary;
4367 } else {
4368 deferred->signal_semaphores[i] = &semaphore->permanent;
4369 }
4370 }
4371
4372 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4373 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4374 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4375 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4376
4377 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4378 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4379 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4380 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4381
4382 *out = deferred;
4383 return VK_SUCCESS;
4384 }
4385
4386 static VkResult
4387 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4388 struct list_head *processing_list)
4389 {
4390 uint32_t wait_cnt = 0;
4391 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4392 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4393 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4394 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4395 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4396 ++wait_cnt;
4397 waiter->value = submission->wait_values[i];
4398 waiter->submission = submission;
4399 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4400 ++waiter;
4401 }
4402 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4403 }
4404 }
4405
4406 pthread_mutex_lock(&submission->queue->pending_mutex);
4407
4408 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4409 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4410
4411 pthread_mutex_unlock(&submission->queue->pending_mutex);
4412
4413 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4414 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4415 * submission. */
4416 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4417 return radv_queue_trigger_submission(submission, decrement, processing_list);
4418 }
4419
4420 static void
4421 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4422 struct list_head *processing_list)
4423 {
4424 pthread_mutex_lock(&submission->queue->pending_mutex);
4425 list_del(&submission->queue_pending_list);
4426
4427 /* trigger the next submission in the queue. */
4428 if (!list_is_empty(&submission->queue->pending_submissions)) {
4429 struct radv_deferred_queue_submission *next_submission =
4430 list_first_entry(&submission->queue->pending_submissions,
4431 struct radv_deferred_queue_submission,
4432 queue_pending_list);
4433 radv_queue_trigger_submission(next_submission, 1, processing_list);
4434 }
4435 pthread_mutex_unlock(&submission->queue->pending_mutex);
4436
4437 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4438 }
4439
4440 static VkResult
4441 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4442 struct list_head *processing_list)
4443 {
4444 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4445 struct radv_queue *queue = submission->queue;
4446 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4447 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4448 struct radeon_winsys_fence *base_fence = NULL;
4449 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4450 bool can_patch = true;
4451 uint32_t advance;
4452 struct radv_winsys_sem_info sem_info;
4453 VkResult result;
4454 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4455 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4456 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4457
4458 if (fence) {
4459 /* Under most circumstances, out fences won't be temporary.
4460 * However, the spec does allow it for opaque_fd.
4461 *
4462 * From the Vulkan 1.0.53 spec:
4463 *
4464 * "If the import is temporary, the implementation must
4465 * restore the semaphore to its prior permanent state after
4466 * submitting the next semaphore wait operation."
4467 */
4468 struct radv_fence_part *part =
4469 fence->temporary.kind != RADV_FENCE_NONE ?
4470 &fence->temporary : &fence->permanent;
4471 if (part->kind == RADV_FENCE_WINSYS)
4472 base_fence = part->fence;
4473 }
4474
4475 result = radv_get_preambles(queue, submission->cmd_buffers,
4476 submission->cmd_buffer_count,
4477 &initial_preamble_cs,
4478 &initial_flush_preamble_cs,
4479 &continue_preamble_cs);
4480 if (result != VK_SUCCESS)
4481 goto fail;
4482
4483 result = radv_alloc_sem_info(queue->device,
4484 &sem_info,
4485 submission->wait_semaphore_count,
4486 submission->wait_semaphores,
4487 submission->wait_values,
4488 submission->signal_semaphore_count,
4489 submission->signal_semaphores,
4490 submission->signal_values,
4491 submission->fence);
4492 if (result != VK_SUCCESS)
4493 goto fail;
4494
4495 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4496 result = radv_sparse_buffer_bind_memory(queue->device,
4497 submission->buffer_binds + i);
4498 if (result != VK_SUCCESS)
4499 goto fail;
4500 }
4501
4502 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4503 result = radv_sparse_image_opaque_bind_memory(queue->device,
4504 submission->image_opaque_binds + i);
4505 if (result != VK_SUCCESS)
4506 goto fail;
4507 }
4508
4509 if (!submission->cmd_buffer_count) {
4510 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4511 &queue->device->empty_cs[queue->queue_family_index],
4512 1, NULL, NULL,
4513 &sem_info, NULL,
4514 false, base_fence);
4515 if (result != VK_SUCCESS)
4516 goto fail;
4517 } else {
4518 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4519 (submission->cmd_buffer_count));
4520
4521 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4523 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4524
4525 cs_array[j] = cmd_buffer->cs;
4526 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4527 can_patch = false;
4528
4529 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4530 }
4531
4532 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4533 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4534 const struct radv_winsys_bo_list *bo_list = NULL;
4535
4536 advance = MIN2(max_cs_submission,
4537 submission->cmd_buffer_count - j);
4538
4539 if (queue->device->trace_bo)
4540 *queue->device->trace_id_ptr = 0;
4541
4542 sem_info.cs_emit_wait = j == 0;
4543 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4544
4545 if (unlikely(queue->device->use_global_bo_list)) {
4546 pthread_mutex_lock(&queue->device->bo_list.mutex);
4547 bo_list = &queue->device->bo_list.list;
4548 }
4549
4550 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4551 advance, initial_preamble, continue_preamble_cs,
4552 &sem_info, bo_list,
4553 can_patch, base_fence);
4554
4555 if (unlikely(queue->device->use_global_bo_list))
4556 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4557
4558 if (result != VK_SUCCESS)
4559 goto fail;
4560
4561 if (queue->device->trace_bo) {
4562 radv_check_gpu_hangs(queue, cs_array[j]);
4563 }
4564
4565 if (queue->device->tma_bo) {
4566 radv_check_trap_handler(queue);
4567 }
4568 }
4569
4570 free(cs_array);
4571 }
4572
4573 radv_free_temp_syncobjs(queue->device,
4574 submission->temporary_semaphore_part_count,
4575 submission->temporary_semaphore_parts);
4576 radv_finalize_timelines(queue->device,
4577 submission->wait_semaphore_count,
4578 submission->wait_semaphores,
4579 submission->wait_values,
4580 submission->signal_semaphore_count,
4581 submission->signal_semaphores,
4582 submission->signal_values,
4583 processing_list);
4584 /* Has to happen after timeline finalization to make sure the
4585 * condition variable is only triggered when timelines and queue have
4586 * been updated. */
4587 radv_queue_submission_update_queue(submission, processing_list);
4588 radv_free_sem_info(&sem_info);
4589 free(submission);
4590 return VK_SUCCESS;
4591
4592 fail:
4593 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4594 /* When something bad happened during the submission, such as
4595 * an out of memory issue, it might be hard to recover from
4596 * this inconsistent state. To avoid this sort of problem, we
4597 * assume that we are in a really bad situation and return
4598 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4599 * to submit the same job again to this device.
4600 */
4601 result = radv_device_set_lost(queue->device, "vkQueueSubmit() failed");
4602 }
4603
4604 radv_free_temp_syncobjs(queue->device,
4605 submission->temporary_semaphore_part_count,
4606 submission->temporary_semaphore_parts);
4607 free(submission);
4608 return result;
4609 }
4610
4611 static VkResult
4612 radv_process_submissions(struct list_head *processing_list)
4613 {
4614 while(!list_is_empty(processing_list)) {
4615 struct radv_deferred_queue_submission *submission =
4616 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4617 list_del(&submission->processing_list);
4618
4619 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4620 if (result != VK_SUCCESS)
4621 return result;
4622 }
4623 return VK_SUCCESS;
4624 }
4625
4626 static VkResult
4627 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4628 uint64_t timeout)
4629 {
4630 struct radv_device *device = submission->queue->device;
4631 uint32_t syncobj_count = 0;
4632 uint32_t syncobj_idx = 0;
4633
4634 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4635 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4636 continue;
4637
4638 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4639 continue;
4640 ++syncobj_count;
4641 }
4642
4643 if (!syncobj_count)
4644 return VK_SUCCESS;
4645
4646 uint64_t *points = malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count);
4647 if (!points)
4648 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4649
4650 uint32_t *syncobj = (uint32_t*)(points + syncobj_count);
4651
4652 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4653 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4654 continue;
4655
4656 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4657 continue;
4658
4659 syncobj[syncobj_idx] = submission->wait_semaphores[i]->syncobj;
4660 points[syncobj_idx] = submission->wait_values[i];
4661 ++syncobj_idx;
4662 }
4663 bool success = device->ws->wait_timeline_syncobj(device->ws, syncobj, points, syncobj_idx, true, true, timeout);
4664
4665 free(points);
4666 return success ? VK_SUCCESS : VK_TIMEOUT;
4667 }
4668
4669 static void* radv_queue_submission_thread_run(void *q)
4670 {
4671 struct radv_queue *queue = q;
4672
4673 pthread_mutex_lock(&queue->thread_mutex);
4674 while (!p_atomic_read(&queue->thread_exit)) {
4675 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4676 struct list_head processing_list;
4677 VkResult result = VK_SUCCESS;
4678 if (!submission) {
4679 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4680 continue;
4681 }
4682 pthread_mutex_unlock(&queue->thread_mutex);
4683
4684 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4685 * a semaphore never gets signaled. If it takes longer we just retry
4686 * the wait next iteration. */
4687 result = wait_for_submission_timelines_available(submission,
4688 radv_get_absolute_timeout(5000000000));
4689 if (result != VK_SUCCESS) {
4690 pthread_mutex_lock(&queue->thread_mutex);
4691 continue;
4692 }
4693
4694 /* The lock isn't held but nobody will add one until we finish
4695 * the current submission. */
4696 p_atomic_set(&queue->thread_submission, NULL);
4697
4698 list_inithead(&processing_list);
4699 list_addtail(&submission->processing_list, &processing_list);
4700 result = radv_process_submissions(&processing_list);
4701
4702 pthread_mutex_lock(&queue->thread_mutex);
4703 }
4704 pthread_mutex_unlock(&queue->thread_mutex);
4705 return NULL;
4706 }
4707
4708 static VkResult
4709 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4710 uint32_t decrement,
4711 struct list_head *processing_list)
4712 {
4713 struct radv_queue *queue = submission->queue;
4714 int ret;
4715 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4716 return VK_SUCCESS;
4717
4718 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4719 list_addtail(&submission->processing_list, processing_list);
4720 return VK_SUCCESS;
4721 }
4722
4723 pthread_mutex_lock(&queue->thread_mutex);
4724
4725 /* A submission can only be ready for the thread if it doesn't have
4726 * any predecessors in the same queue, so there can only be one such
4727 * submission at a time. */
4728 assert(queue->thread_submission == NULL);
4729
4730 /* Only start the thread on demand to save resources for the many games
4731 * which only use binary semaphores. */
4732 if (!queue->thread_running) {
4733 ret = pthread_create(&queue->submission_thread, NULL,
4734 radv_queue_submission_thread_run, queue);
4735 if (ret) {
4736 pthread_mutex_unlock(&queue->thread_mutex);
4737 return vk_errorf(queue->device->instance,
4738 VK_ERROR_DEVICE_LOST,
4739 "Failed to start submission thread");
4740 }
4741 queue->thread_running = true;
4742 }
4743
4744 queue->thread_submission = submission;
4745 pthread_mutex_unlock(&queue->thread_mutex);
4746
4747 pthread_cond_signal(&queue->thread_cond);
4748 return VK_SUCCESS;
4749 }
4750
4751 static VkResult radv_queue_submit(struct radv_queue *queue,
4752 const struct radv_queue_submission *submission)
4753 {
4754 struct radv_deferred_queue_submission *deferred = NULL;
4755
4756 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4757 if (result != VK_SUCCESS)
4758 return result;
4759
4760 struct list_head processing_list;
4761 list_inithead(&processing_list);
4762
4763 result = radv_queue_enqueue_submission(deferred, &processing_list);
4764 if (result != VK_SUCCESS) {
4765 /* If anything is in the list we leak. */
4766 assert(list_is_empty(&processing_list));
4767 return result;
4768 }
4769 return radv_process_submissions(&processing_list);
4770 }
4771
4772 bool
4773 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4774 {
4775 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4776 struct radv_winsys_sem_info sem_info;
4777 VkResult result;
4778
4779 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4780 0, NULL, VK_NULL_HANDLE);
4781 if (result != VK_SUCCESS)
4782 return false;
4783
4784 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4785 NULL, NULL, &sem_info, NULL,
4786 false, NULL);
4787 radv_free_sem_info(&sem_info);
4788 if (result != VK_SUCCESS)
4789 return false;
4790
4791 return true;
4792
4793 }
4794
4795 /* Signals fence as soon as all the work currently put on queue is done. */
4796 static VkResult radv_signal_fence(struct radv_queue *queue,
4797 VkFence fence)
4798 {
4799 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4800 .fence = fence
4801 });
4802 }
4803
4804 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4805 {
4806 return info->commandBufferCount ||
4807 info->waitSemaphoreCount ||
4808 info->signalSemaphoreCount;
4809 }
4810
4811 VkResult radv_QueueSubmit(
4812 VkQueue _queue,
4813 uint32_t submitCount,
4814 const VkSubmitInfo* pSubmits,
4815 VkFence fence)
4816 {
4817 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4818 VkResult result;
4819 uint32_t fence_idx = 0;
4820 bool flushed_caches = false;
4821
4822 if (radv_device_is_lost(queue->device))
4823 return VK_ERROR_DEVICE_LOST;
4824
4825 if (fence != VK_NULL_HANDLE) {
4826 for (uint32_t i = 0; i < submitCount; ++i)
4827 if (radv_submit_has_effects(pSubmits + i))
4828 fence_idx = i;
4829 } else
4830 fence_idx = UINT32_MAX;
4831
4832 for (uint32_t i = 0; i < submitCount; i++) {
4833 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4834 continue;
4835
4836 VkPipelineStageFlags wait_dst_stage_mask = 0;
4837 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4838 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4839 }
4840
4841 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4842 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4843
4844 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4845 .cmd_buffers = pSubmits[i].pCommandBuffers,
4846 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4847 .wait_dst_stage_mask = wait_dst_stage_mask,
4848 .flush_caches = !flushed_caches,
4849 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4850 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4851 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4852 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4853 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4854 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4855 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4856 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4857 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4858 });
4859 if (result != VK_SUCCESS)
4860 return result;
4861
4862 flushed_caches = true;
4863 }
4864
4865 if (fence != VK_NULL_HANDLE && !submitCount) {
4866 result = radv_signal_fence(queue, fence);
4867 if (result != VK_SUCCESS)
4868 return result;
4869 }
4870
4871 return VK_SUCCESS;
4872 }
4873
4874 static const char *
4875 radv_get_queue_family_name(struct radv_queue *queue)
4876 {
4877 switch (queue->queue_family_index) {
4878 case RADV_QUEUE_GENERAL:
4879 return "graphics";
4880 case RADV_QUEUE_COMPUTE:
4881 return "compute";
4882 case RADV_QUEUE_TRANSFER:
4883 return "transfer";
4884 default:
4885 unreachable("Unknown queue family");
4886 }
4887 }
4888
4889 VkResult radv_QueueWaitIdle(
4890 VkQueue _queue)
4891 {
4892 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4893
4894 if (radv_device_is_lost(queue->device))
4895 return VK_ERROR_DEVICE_LOST;
4896
4897 pthread_mutex_lock(&queue->pending_mutex);
4898 while (!list_is_empty(&queue->pending_submissions)) {
4899 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4900 }
4901 pthread_mutex_unlock(&queue->pending_mutex);
4902
4903 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4904 radv_queue_family_to_ring(queue->queue_family_index),
4905 queue->queue_idx)) {
4906 return radv_device_set_lost(queue->device,
4907 "Failed to wait for a '%s' queue "
4908 "to be idle. GPU hang ?",
4909 radv_get_queue_family_name(queue));
4910 }
4911
4912 return VK_SUCCESS;
4913 }
4914
4915 VkResult radv_DeviceWaitIdle(
4916 VkDevice _device)
4917 {
4918 RADV_FROM_HANDLE(radv_device, device, _device);
4919
4920 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4921 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4922 VkResult result =
4923 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4924
4925 if (result != VK_SUCCESS)
4926 return result;
4927 }
4928 }
4929 return VK_SUCCESS;
4930 }
4931
4932 VkResult radv_EnumerateInstanceExtensionProperties(
4933 const char* pLayerName,
4934 uint32_t* pPropertyCount,
4935 VkExtensionProperties* pProperties)
4936 {
4937 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4938
4939 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4940 if (radv_instance_extensions_supported.extensions[i]) {
4941 vk_outarray_append(&out, prop) {
4942 *prop = radv_instance_extensions[i];
4943 }
4944 }
4945 }
4946
4947 return vk_outarray_status(&out);
4948 }
4949
4950 VkResult radv_EnumerateDeviceExtensionProperties(
4951 VkPhysicalDevice physicalDevice,
4952 const char* pLayerName,
4953 uint32_t* pPropertyCount,
4954 VkExtensionProperties* pProperties)
4955 {
4956 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4957 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4958
4959 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4960 if (device->supported_extensions.extensions[i]) {
4961 vk_outarray_append(&out, prop) {
4962 *prop = radv_device_extensions[i];
4963 }
4964 }
4965 }
4966
4967 return vk_outarray_status(&out);
4968 }
4969
4970 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4971 VkInstance _instance,
4972 const char* pName)
4973 {
4974 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4975
4976 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4977 * when we have to return valid function pointers, NULL, or it's left
4978 * undefined. See the table for exact details.
4979 */
4980 if (pName == NULL)
4981 return NULL;
4982
4983 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4984 if (strcmp(pName, "vk" #entrypoint) == 0) \
4985 return (PFN_vkVoidFunction)radv_##entrypoint
4986
4987 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4988 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4989 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4990 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4991
4992 /* GetInstanceProcAddr() can also be called with a NULL instance.
4993 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4994 */
4995 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4996
4997 #undef LOOKUP_RADV_ENTRYPOINT
4998
4999 if (instance == NULL)
5000 return NULL;
5001
5002 int idx = radv_get_instance_entrypoint_index(pName);
5003 if (idx >= 0)
5004 return instance->dispatch.entrypoints[idx];
5005
5006 idx = radv_get_physical_device_entrypoint_index(pName);
5007 if (idx >= 0)
5008 return instance->physical_device_dispatch.entrypoints[idx];
5009
5010 idx = radv_get_device_entrypoint_index(pName);
5011 if (idx >= 0)
5012 return instance->device_dispatch.entrypoints[idx];
5013
5014 return NULL;
5015 }
5016
5017 /* The loader wants us to expose a second GetInstanceProcAddr function
5018 * to work around certain LD_PRELOAD issues seen in apps.
5019 */
5020 PUBLIC
5021 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5022 VkInstance instance,
5023 const char* pName);
5024
5025 PUBLIC
5026 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5027 VkInstance instance,
5028 const char* pName)
5029 {
5030 return radv_GetInstanceProcAddr(instance, pName);
5031 }
5032
5033 PUBLIC
5034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5035 VkInstance _instance,
5036 const char* pName);
5037
5038 PUBLIC
5039 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5040 VkInstance _instance,
5041 const char* pName)
5042 {
5043 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5044
5045 if (!pName || !instance)
5046 return NULL;
5047
5048 int idx = radv_get_physical_device_entrypoint_index(pName);
5049 if (idx < 0)
5050 return NULL;
5051
5052 return instance->physical_device_dispatch.entrypoints[idx];
5053 }
5054
5055 PFN_vkVoidFunction radv_GetDeviceProcAddr(
5056 VkDevice _device,
5057 const char* pName)
5058 {
5059 RADV_FROM_HANDLE(radv_device, device, _device);
5060
5061 if (!device || !pName)
5062 return NULL;
5063
5064 int idx = radv_get_device_entrypoint_index(pName);
5065 if (idx < 0)
5066 return NULL;
5067
5068 return device->dispatch.entrypoints[idx];
5069 }
5070
5071 bool radv_get_memory_fd(struct radv_device *device,
5072 struct radv_device_memory *memory,
5073 int *pFD)
5074 {
5075 struct radeon_bo_metadata metadata;
5076
5077 if (memory->image) {
5078 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5079 radv_init_metadata(device, memory->image, &metadata);
5080 device->ws->buffer_set_metadata(memory->bo, &metadata);
5081 }
5082
5083 return device->ws->buffer_get_fd(device->ws, memory->bo,
5084 pFD);
5085 }
5086
5087
5088 void
5089 radv_free_memory(struct radv_device *device,
5090 const VkAllocationCallbacks* pAllocator,
5091 struct radv_device_memory *mem)
5092 {
5093 if (mem == NULL)
5094 return;
5095
5096 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5097 if (mem->android_hardware_buffer)
5098 AHardwareBuffer_release(mem->android_hardware_buffer);
5099 #endif
5100
5101 if (mem->bo) {
5102 if (device->overallocation_disallowed) {
5103 mtx_lock(&device->overallocation_mutex);
5104 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5105 mtx_unlock(&device->overallocation_mutex);
5106 }
5107
5108 radv_bo_list_remove(device, mem->bo);
5109 device->ws->buffer_destroy(mem->bo);
5110 mem->bo = NULL;
5111 }
5112
5113 vk_object_base_finish(&mem->base);
5114 vk_free2(&device->vk.alloc, pAllocator, mem);
5115 }
5116
5117 static VkResult radv_alloc_memory(struct radv_device *device,
5118 const VkMemoryAllocateInfo* pAllocateInfo,
5119 const VkAllocationCallbacks* pAllocator,
5120 VkDeviceMemory* pMem)
5121 {
5122 struct radv_device_memory *mem;
5123 VkResult result;
5124 enum radeon_bo_domain domain;
5125 uint32_t flags = 0;
5126
5127 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5128
5129 const VkImportMemoryFdInfoKHR *import_info =
5130 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5131 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5132 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5133 const VkExportMemoryAllocateInfo *export_info =
5134 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5135 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5136 vk_find_struct_const(pAllocateInfo->pNext,
5137 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5138 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5139 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5140
5141 const struct wsi_memory_allocate_info *wsi_info =
5142 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5143
5144 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5145 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5146 /* Apparently, this is allowed */
5147 *pMem = VK_NULL_HANDLE;
5148 return VK_SUCCESS;
5149 }
5150
5151 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
5152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5153 if (mem == NULL)
5154 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5155
5156 vk_object_base_init(&device->vk, &mem->base,
5157 VK_OBJECT_TYPE_DEVICE_MEMORY);
5158
5159 if (wsi_info && wsi_info->implicit_sync)
5160 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5161
5162 if (dedicate_info) {
5163 mem->image = radv_image_from_handle(dedicate_info->image);
5164 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5165 } else {
5166 mem->image = NULL;
5167 mem->buffer = NULL;
5168 }
5169
5170 float priority_float = 0.5;
5171 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5172 vk_find_struct_const(pAllocateInfo->pNext,
5173 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5174 if (priority_ext)
5175 priority_float = priority_ext->priority;
5176
5177 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5178 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5179
5180 mem->user_ptr = NULL;
5181 mem->bo = NULL;
5182
5183 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5184 mem->android_hardware_buffer = NULL;
5185 #endif
5186
5187 if (ahb_import_info) {
5188 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5189 if (result != VK_SUCCESS)
5190 goto fail;
5191 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5192 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5193 if (result != VK_SUCCESS)
5194 goto fail;
5195 } else if (import_info) {
5196 assert(import_info->handleType ==
5197 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5198 import_info->handleType ==
5199 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5200 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5201 priority, NULL);
5202 if (!mem->bo) {
5203 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5204 goto fail;
5205 } else {
5206 close(import_info->fd);
5207 }
5208
5209 if (mem->image && mem->image->plane_count == 1 &&
5210 !vk_format_is_depth_or_stencil(mem->image->vk_format)) {
5211 struct radeon_bo_metadata metadata;
5212 device->ws->buffer_get_metadata(mem->bo, &metadata);
5213
5214 struct radv_image_create_info create_info = {
5215 .no_metadata_planes = true,
5216 .bo_metadata = &metadata
5217 };
5218
5219 /* This gives a basic ability to import radeonsi images
5220 * that don't have DCC. This is not guaranteed by any
5221 * spec and can be removed after we support modifiers. */
5222 result = radv_image_create_layout(device, create_info, mem->image);
5223 if (result != VK_SUCCESS) {
5224 device->ws->buffer_destroy(mem->bo);
5225 goto fail;
5226 }
5227 }
5228 } else if (host_ptr_info) {
5229 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5230 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5231 pAllocateInfo->allocationSize,
5232 priority);
5233 if (!mem->bo) {
5234 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5235 goto fail;
5236 } else {
5237 mem->user_ptr = host_ptr_info->pHostPointer;
5238 }
5239 } else {
5240 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5241 uint32_t heap_index;
5242
5243 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5244 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5245 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5246
5247 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5248 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5249 if (device->use_global_bo_list) {
5250 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5251 }
5252 }
5253
5254 if (device->overallocation_disallowed) {
5255 uint64_t total_size =
5256 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5257
5258 mtx_lock(&device->overallocation_mutex);
5259 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5260 mtx_unlock(&device->overallocation_mutex);
5261 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5262 goto fail;
5263 }
5264 device->allocated_memory_size[heap_index] += alloc_size;
5265 mtx_unlock(&device->overallocation_mutex);
5266 }
5267
5268 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5269 domain, flags, priority);
5270
5271 if (!mem->bo) {
5272 if (device->overallocation_disallowed) {
5273 mtx_lock(&device->overallocation_mutex);
5274 device->allocated_memory_size[heap_index] -= alloc_size;
5275 mtx_unlock(&device->overallocation_mutex);
5276 }
5277 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5278 goto fail;
5279 }
5280
5281 mem->heap_index = heap_index;
5282 mem->alloc_size = alloc_size;
5283 }
5284
5285 if (!wsi_info) {
5286 result = radv_bo_list_add(device, mem->bo);
5287 if (result != VK_SUCCESS)
5288 goto fail;
5289 }
5290
5291 *pMem = radv_device_memory_to_handle(mem);
5292
5293 return VK_SUCCESS;
5294
5295 fail:
5296 radv_free_memory(device, pAllocator,mem);
5297
5298 return result;
5299 }
5300
5301 VkResult radv_AllocateMemory(
5302 VkDevice _device,
5303 const VkMemoryAllocateInfo* pAllocateInfo,
5304 const VkAllocationCallbacks* pAllocator,
5305 VkDeviceMemory* pMem)
5306 {
5307 RADV_FROM_HANDLE(radv_device, device, _device);
5308 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5309 }
5310
5311 void radv_FreeMemory(
5312 VkDevice _device,
5313 VkDeviceMemory _mem,
5314 const VkAllocationCallbacks* pAllocator)
5315 {
5316 RADV_FROM_HANDLE(radv_device, device, _device);
5317 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5318
5319 radv_free_memory(device, pAllocator, mem);
5320 }
5321
5322 VkResult radv_MapMemory(
5323 VkDevice _device,
5324 VkDeviceMemory _memory,
5325 VkDeviceSize offset,
5326 VkDeviceSize size,
5327 VkMemoryMapFlags flags,
5328 void** ppData)
5329 {
5330 RADV_FROM_HANDLE(radv_device, device, _device);
5331 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5332
5333 if (mem == NULL) {
5334 *ppData = NULL;
5335 return VK_SUCCESS;
5336 }
5337
5338 if (mem->user_ptr)
5339 *ppData = mem->user_ptr;
5340 else
5341 *ppData = device->ws->buffer_map(mem->bo);
5342
5343 if (*ppData) {
5344 *ppData += offset;
5345 return VK_SUCCESS;
5346 }
5347
5348 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5349 }
5350
5351 void radv_UnmapMemory(
5352 VkDevice _device,
5353 VkDeviceMemory _memory)
5354 {
5355 RADV_FROM_HANDLE(radv_device, device, _device);
5356 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5357
5358 if (mem == NULL)
5359 return;
5360
5361 if (mem->user_ptr == NULL)
5362 device->ws->buffer_unmap(mem->bo);
5363 }
5364
5365 VkResult radv_FlushMappedMemoryRanges(
5366 VkDevice _device,
5367 uint32_t memoryRangeCount,
5368 const VkMappedMemoryRange* pMemoryRanges)
5369 {
5370 return VK_SUCCESS;
5371 }
5372
5373 VkResult radv_InvalidateMappedMemoryRanges(
5374 VkDevice _device,
5375 uint32_t memoryRangeCount,
5376 const VkMappedMemoryRange* pMemoryRanges)
5377 {
5378 return VK_SUCCESS;
5379 }
5380
5381 void radv_GetBufferMemoryRequirements(
5382 VkDevice _device,
5383 VkBuffer _buffer,
5384 VkMemoryRequirements* pMemoryRequirements)
5385 {
5386 RADV_FROM_HANDLE(radv_device, device, _device);
5387 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5388
5389 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5390
5391 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5392 pMemoryRequirements->alignment = 4096;
5393 else
5394 pMemoryRequirements->alignment = 16;
5395
5396 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5397 }
5398
5399 void radv_GetBufferMemoryRequirements2(
5400 VkDevice device,
5401 const VkBufferMemoryRequirementsInfo2 *pInfo,
5402 VkMemoryRequirements2 *pMemoryRequirements)
5403 {
5404 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5405 &pMemoryRequirements->memoryRequirements);
5406 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5407 switch (ext->sType) {
5408 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5409 VkMemoryDedicatedRequirements *req =
5410 (VkMemoryDedicatedRequirements *) ext;
5411 req->requiresDedicatedAllocation = false;
5412 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5413 break;
5414 }
5415 default:
5416 break;
5417 }
5418 }
5419 }
5420
5421 void radv_GetImageMemoryRequirements(
5422 VkDevice _device,
5423 VkImage _image,
5424 VkMemoryRequirements* pMemoryRequirements)
5425 {
5426 RADV_FROM_HANDLE(radv_device, device, _device);
5427 RADV_FROM_HANDLE(radv_image, image, _image);
5428
5429 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5430
5431 pMemoryRequirements->size = image->size;
5432 pMemoryRequirements->alignment = image->alignment;
5433 }
5434
5435 void radv_GetImageMemoryRequirements2(
5436 VkDevice device,
5437 const VkImageMemoryRequirementsInfo2 *pInfo,
5438 VkMemoryRequirements2 *pMemoryRequirements)
5439 {
5440 radv_GetImageMemoryRequirements(device, pInfo->image,
5441 &pMemoryRequirements->memoryRequirements);
5442
5443 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5444
5445 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5446 switch (ext->sType) {
5447 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5448 VkMemoryDedicatedRequirements *req =
5449 (VkMemoryDedicatedRequirements *) ext;
5450 req->requiresDedicatedAllocation = image->shareable &&
5451 image->tiling != VK_IMAGE_TILING_LINEAR;
5452 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5453 break;
5454 }
5455 default:
5456 break;
5457 }
5458 }
5459 }
5460
5461 void radv_GetImageSparseMemoryRequirements(
5462 VkDevice device,
5463 VkImage image,
5464 uint32_t* pSparseMemoryRequirementCount,
5465 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5466 {
5467 stub();
5468 }
5469
5470 void radv_GetImageSparseMemoryRequirements2(
5471 VkDevice device,
5472 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5473 uint32_t* pSparseMemoryRequirementCount,
5474 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5475 {
5476 stub();
5477 }
5478
5479 void radv_GetDeviceMemoryCommitment(
5480 VkDevice device,
5481 VkDeviceMemory memory,
5482 VkDeviceSize* pCommittedMemoryInBytes)
5483 {
5484 *pCommittedMemoryInBytes = 0;
5485 }
5486
5487 VkResult radv_BindBufferMemory2(VkDevice device,
5488 uint32_t bindInfoCount,
5489 const VkBindBufferMemoryInfo *pBindInfos)
5490 {
5491 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5492 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5493 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5494
5495 if (mem) {
5496 buffer->bo = mem->bo;
5497 buffer->offset = pBindInfos[i].memoryOffset;
5498 } else {
5499 buffer->bo = NULL;
5500 }
5501 }
5502 return VK_SUCCESS;
5503 }
5504
5505 VkResult radv_BindBufferMemory(
5506 VkDevice device,
5507 VkBuffer buffer,
5508 VkDeviceMemory memory,
5509 VkDeviceSize memoryOffset)
5510 {
5511 const VkBindBufferMemoryInfo info = {
5512 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5513 .buffer = buffer,
5514 .memory = memory,
5515 .memoryOffset = memoryOffset
5516 };
5517
5518 return radv_BindBufferMemory2(device, 1, &info);
5519 }
5520
5521 VkResult radv_BindImageMemory2(VkDevice device,
5522 uint32_t bindInfoCount,
5523 const VkBindImageMemoryInfo *pBindInfos)
5524 {
5525 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5526 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5527 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5528
5529 if (mem) {
5530 image->bo = mem->bo;
5531 image->offset = pBindInfos[i].memoryOffset;
5532 } else {
5533 image->bo = NULL;
5534 image->offset = 0;
5535 }
5536 }
5537 return VK_SUCCESS;
5538 }
5539
5540
5541 VkResult radv_BindImageMemory(
5542 VkDevice device,
5543 VkImage image,
5544 VkDeviceMemory memory,
5545 VkDeviceSize memoryOffset)
5546 {
5547 const VkBindImageMemoryInfo info = {
5548 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5549 .image = image,
5550 .memory = memory,
5551 .memoryOffset = memoryOffset
5552 };
5553
5554 return radv_BindImageMemory2(device, 1, &info);
5555 }
5556
5557 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5558 {
5559 return info->bufferBindCount ||
5560 info->imageOpaqueBindCount ||
5561 info->imageBindCount ||
5562 info->waitSemaphoreCount ||
5563 info->signalSemaphoreCount;
5564 }
5565
5566 VkResult radv_QueueBindSparse(
5567 VkQueue _queue,
5568 uint32_t bindInfoCount,
5569 const VkBindSparseInfo* pBindInfo,
5570 VkFence fence)
5571 {
5572 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5573 VkResult result;
5574 uint32_t fence_idx = 0;
5575
5576 if (radv_device_is_lost(queue->device))
5577 return VK_ERROR_DEVICE_LOST;
5578
5579 if (fence != VK_NULL_HANDLE) {
5580 for (uint32_t i = 0; i < bindInfoCount; ++i)
5581 if (radv_sparse_bind_has_effects(pBindInfo + i))
5582 fence_idx = i;
5583 } else
5584 fence_idx = UINT32_MAX;
5585
5586 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5587 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5588 continue;
5589
5590 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5591 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5592
5593 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5594 .buffer_binds = pBindInfo[i].pBufferBinds,
5595 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5596 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5597 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5598 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5599 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5600 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5601 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5602 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5603 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5604 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5605 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5606 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5607 });
5608
5609 if (result != VK_SUCCESS)
5610 return result;
5611 }
5612
5613 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5614 result = radv_signal_fence(queue, fence);
5615 if (result != VK_SUCCESS)
5616 return result;
5617 }
5618
5619 return VK_SUCCESS;
5620 }
5621
5622 static void
5623 radv_destroy_fence_part(struct radv_device *device,
5624 struct radv_fence_part *part)
5625 {
5626 switch (part->kind) {
5627 case RADV_FENCE_NONE:
5628 break;
5629 case RADV_FENCE_WINSYS:
5630 device->ws->destroy_fence(part->fence);
5631 break;
5632 case RADV_FENCE_SYNCOBJ:
5633 device->ws->destroy_syncobj(device->ws, part->syncobj);
5634 break;
5635 case RADV_FENCE_WSI:
5636 part->fence_wsi->destroy(part->fence_wsi);
5637 break;
5638 default:
5639 unreachable("Invalid fence type");
5640 }
5641
5642 part->kind = RADV_FENCE_NONE;
5643 }
5644
5645 static void
5646 radv_destroy_fence(struct radv_device *device,
5647 const VkAllocationCallbacks *pAllocator,
5648 struct radv_fence *fence)
5649 {
5650 radv_destroy_fence_part(device, &fence->temporary);
5651 radv_destroy_fence_part(device, &fence->permanent);
5652
5653 vk_object_base_finish(&fence->base);
5654 vk_free2(&device->vk.alloc, pAllocator, fence);
5655 }
5656
5657 VkResult radv_CreateFence(
5658 VkDevice _device,
5659 const VkFenceCreateInfo* pCreateInfo,
5660 const VkAllocationCallbacks* pAllocator,
5661 VkFence* pFence)
5662 {
5663 RADV_FROM_HANDLE(radv_device, device, _device);
5664 const VkExportFenceCreateInfo *export =
5665 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5666 VkExternalFenceHandleTypeFlags handleTypes =
5667 export ? export->handleTypes : 0;
5668 struct radv_fence *fence;
5669
5670 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5671 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5672 if (!fence)
5673 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5674
5675 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5676
5677 if (device->always_use_syncobj || handleTypes) {
5678 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5679
5680 bool create_signaled = false;
5681 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5682 create_signaled = true;
5683
5684 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5685 &fence->permanent.syncobj);
5686 if (ret) {
5687 radv_destroy_fence(device, pAllocator, fence);
5688 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5689 }
5690 } else {
5691 fence->permanent.kind = RADV_FENCE_WINSYS;
5692
5693 fence->permanent.fence = device->ws->create_fence();
5694 if (!fence->permanent.fence) {
5695 vk_free2(&device->vk.alloc, pAllocator, fence);
5696 radv_destroy_fence(device, pAllocator, fence);
5697 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5698 }
5699 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5700 device->ws->signal_fence(fence->permanent.fence);
5701 }
5702
5703 *pFence = radv_fence_to_handle(fence);
5704
5705 return VK_SUCCESS;
5706 }
5707
5708
5709 void radv_DestroyFence(
5710 VkDevice _device,
5711 VkFence _fence,
5712 const VkAllocationCallbacks* pAllocator)
5713 {
5714 RADV_FROM_HANDLE(radv_device, device, _device);
5715 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5716
5717 if (!fence)
5718 return;
5719
5720 radv_destroy_fence(device, pAllocator, fence);
5721 }
5722
5723 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5724 uint32_t fenceCount, const VkFence *pFences)
5725 {
5726 for (uint32_t i = 0; i < fenceCount; ++i) {
5727 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5728
5729 struct radv_fence_part *part =
5730 fence->temporary.kind != RADV_FENCE_NONE ?
5731 &fence->temporary : &fence->permanent;
5732 if (part->kind != RADV_FENCE_WINSYS ||
5733 !device->ws->is_fence_waitable(part->fence))
5734 return false;
5735 }
5736 return true;
5737 }
5738
5739 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5740 {
5741 for (uint32_t i = 0; i < fenceCount; ++i) {
5742 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5743
5744 struct radv_fence_part *part =
5745 fence->temporary.kind != RADV_FENCE_NONE ?
5746 &fence->temporary : &fence->permanent;
5747 if (part->kind != RADV_FENCE_SYNCOBJ)
5748 return false;
5749 }
5750 return true;
5751 }
5752
5753 VkResult radv_WaitForFences(
5754 VkDevice _device,
5755 uint32_t fenceCount,
5756 const VkFence* pFences,
5757 VkBool32 waitAll,
5758 uint64_t timeout)
5759 {
5760 RADV_FROM_HANDLE(radv_device, device, _device);
5761
5762 if (radv_device_is_lost(device))
5763 return VK_ERROR_DEVICE_LOST;
5764
5765 timeout = radv_get_absolute_timeout(timeout);
5766
5767 if (device->always_use_syncobj &&
5768 radv_all_fences_syncobj(fenceCount, pFences))
5769 {
5770 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5771 if (!handles)
5772 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5773
5774 for (uint32_t i = 0; i < fenceCount; ++i) {
5775 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5776
5777 struct radv_fence_part *part =
5778 fence->temporary.kind != RADV_FENCE_NONE ?
5779 &fence->temporary : &fence->permanent;
5780
5781 assert(part->kind == RADV_FENCE_SYNCOBJ);
5782 handles[i] = part->syncobj;
5783 }
5784
5785 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5786
5787 free(handles);
5788 return success ? VK_SUCCESS : VK_TIMEOUT;
5789 }
5790
5791 if (!waitAll && fenceCount > 1) {
5792 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5793 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5794 uint32_t wait_count = 0;
5795 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5796 if (!fences)
5797 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5798
5799 for (uint32_t i = 0; i < fenceCount; ++i) {
5800 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5801
5802 struct radv_fence_part *part =
5803 fence->temporary.kind != RADV_FENCE_NONE ?
5804 &fence->temporary : &fence->permanent;
5805 assert(part->kind == RADV_FENCE_WINSYS);
5806
5807 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5808 free(fences);
5809 return VK_SUCCESS;
5810 }
5811
5812 fences[wait_count++] = part->fence;
5813 }
5814
5815 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5816 waitAll, timeout - radv_get_current_time());
5817
5818 free(fences);
5819 return success ? VK_SUCCESS : VK_TIMEOUT;
5820 }
5821
5822 while(radv_get_current_time() <= timeout) {
5823 for (uint32_t i = 0; i < fenceCount; ++i) {
5824 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5825 return VK_SUCCESS;
5826 }
5827 }
5828 return VK_TIMEOUT;
5829 }
5830
5831 for (uint32_t i = 0; i < fenceCount; ++i) {
5832 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5833 bool expired = false;
5834
5835 struct radv_fence_part *part =
5836 fence->temporary.kind != RADV_FENCE_NONE ?
5837 &fence->temporary : &fence->permanent;
5838
5839 switch (part->kind) {
5840 case RADV_FENCE_NONE:
5841 break;
5842 case RADV_FENCE_WINSYS:
5843 if (!device->ws->is_fence_waitable(part->fence)) {
5844 while (!device->ws->is_fence_waitable(part->fence) &&
5845 radv_get_current_time() <= timeout)
5846 /* Do nothing */;
5847 }
5848
5849 expired = device->ws->fence_wait(device->ws,
5850 part->fence,
5851 true, timeout);
5852 if (!expired)
5853 return VK_TIMEOUT;
5854 break;
5855 case RADV_FENCE_SYNCOBJ:
5856 if (!device->ws->wait_syncobj(device->ws,
5857 &part->syncobj, 1, true,
5858 timeout))
5859 return VK_TIMEOUT;
5860 break;
5861 case RADV_FENCE_WSI: {
5862 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5863 if (result != VK_SUCCESS)
5864 return result;
5865 break;
5866 }
5867 default:
5868 unreachable("Invalid fence type");
5869 }
5870 }
5871
5872 return VK_SUCCESS;
5873 }
5874
5875 VkResult radv_ResetFences(VkDevice _device,
5876 uint32_t fenceCount,
5877 const VkFence *pFences)
5878 {
5879 RADV_FROM_HANDLE(radv_device, device, _device);
5880
5881 for (unsigned i = 0; i < fenceCount; ++i) {
5882 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5883
5884 /* From the Vulkan 1.0.53 spec:
5885 *
5886 * "If any member of pFences currently has its payload
5887 * imported with temporary permanence, that fence’s prior
5888 * permanent payload is irst restored. The remaining
5889 * operations described therefore operate on the restored
5890 * payload."
5891 */
5892 if (fence->temporary.kind != RADV_FENCE_NONE)
5893 radv_destroy_fence_part(device, &fence->temporary);
5894
5895 struct radv_fence_part *part = &fence->permanent;
5896
5897 switch (part->kind) {
5898 case RADV_FENCE_WSI:
5899 device->ws->reset_fence(part->fence);
5900 break;
5901 case RADV_FENCE_SYNCOBJ:
5902 device->ws->reset_syncobj(device->ws, part->syncobj);
5903 break;
5904 default:
5905 unreachable("Invalid fence type");
5906 }
5907 }
5908
5909 return VK_SUCCESS;
5910 }
5911
5912 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5913 {
5914 RADV_FROM_HANDLE(radv_device, device, _device);
5915 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5916
5917 struct radv_fence_part *part =
5918 fence->temporary.kind != RADV_FENCE_NONE ?
5919 &fence->temporary : &fence->permanent;
5920
5921 if (radv_device_is_lost(device))
5922 return VK_ERROR_DEVICE_LOST;
5923
5924 switch (part->kind) {
5925 case RADV_FENCE_NONE:
5926 break;
5927 case RADV_FENCE_WINSYS:
5928 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5929 return VK_NOT_READY;
5930 break;
5931 case RADV_FENCE_SYNCOBJ: {
5932 bool success = device->ws->wait_syncobj(device->ws,
5933 &part->syncobj, 1, true, 0);
5934 if (!success)
5935 return VK_NOT_READY;
5936 break;
5937 }
5938 case RADV_FENCE_WSI: {
5939 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5940 if (result != VK_SUCCESS) {
5941 if (result == VK_TIMEOUT)
5942 return VK_NOT_READY;
5943 return result;
5944 }
5945 break;
5946 }
5947 default:
5948 unreachable("Invalid fence type");
5949 }
5950
5951 return VK_SUCCESS;
5952 }
5953
5954
5955 // Queue semaphore functions
5956
5957 static void
5958 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5959 {
5960 timeline->highest_signaled = value;
5961 timeline->highest_submitted = value;
5962 list_inithead(&timeline->points);
5963 list_inithead(&timeline->free_points);
5964 list_inithead(&timeline->waiters);
5965 pthread_mutex_init(&timeline->mutex, NULL);
5966 }
5967
5968 static void
5969 radv_destroy_timeline(struct radv_device *device,
5970 struct radv_timeline *timeline)
5971 {
5972 list_for_each_entry_safe(struct radv_timeline_point, point,
5973 &timeline->free_points, list) {
5974 list_del(&point->list);
5975 device->ws->destroy_syncobj(device->ws, point->syncobj);
5976 free(point);
5977 }
5978 list_for_each_entry_safe(struct radv_timeline_point, point,
5979 &timeline->points, list) {
5980 list_del(&point->list);
5981 device->ws->destroy_syncobj(device->ws, point->syncobj);
5982 free(point);
5983 }
5984 pthread_mutex_destroy(&timeline->mutex);
5985 }
5986
5987 static void
5988 radv_timeline_gc_locked(struct radv_device *device,
5989 struct radv_timeline *timeline)
5990 {
5991 list_for_each_entry_safe(struct radv_timeline_point, point,
5992 &timeline->points, list) {
5993 if (point->wait_count || point->value > timeline->highest_submitted)
5994 return;
5995
5996 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5997 timeline->highest_signaled = point->value;
5998 list_del(&point->list);
5999 list_add(&point->list, &timeline->free_points);
6000 }
6001 }
6002 }
6003
6004 static struct radv_timeline_point *
6005 radv_timeline_find_point_at_least_locked(struct radv_device *device,
6006 struct radv_timeline *timeline,
6007 uint64_t p)
6008 {
6009 radv_timeline_gc_locked(device, timeline);
6010
6011 if (p <= timeline->highest_signaled)
6012 return NULL;
6013
6014 list_for_each_entry(struct radv_timeline_point, point,
6015 &timeline->points, list) {
6016 if (point->value >= p) {
6017 ++point->wait_count;
6018 return point;
6019 }
6020 }
6021 return NULL;
6022 }
6023
6024 static struct radv_timeline_point *
6025 radv_timeline_add_point_locked(struct radv_device *device,
6026 struct radv_timeline *timeline,
6027 uint64_t p)
6028 {
6029 radv_timeline_gc_locked(device, timeline);
6030
6031 struct radv_timeline_point *ret = NULL;
6032 struct radv_timeline_point *prev = NULL;
6033 int r;
6034
6035 if (p <= timeline->highest_signaled)
6036 return NULL;
6037
6038 list_for_each_entry(struct radv_timeline_point, point,
6039 &timeline->points, list) {
6040 if (point->value == p) {
6041 return NULL;
6042 }
6043
6044 if (point->value < p)
6045 prev = point;
6046 }
6047
6048 if (list_is_empty(&timeline->free_points)) {
6049 ret = malloc(sizeof(struct radv_timeline_point));
6050 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
6051 if (r) {
6052 free(ret);
6053 return NULL;
6054 }
6055 } else {
6056 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
6057 list_del(&ret->list);
6058
6059 device->ws->reset_syncobj(device->ws, ret->syncobj);
6060 }
6061
6062 ret->value = p;
6063 ret->wait_count = 1;
6064
6065 if (prev) {
6066 list_add(&ret->list, &prev->list);
6067 } else {
6068 list_addtail(&ret->list, &timeline->points);
6069 }
6070 return ret;
6071 }
6072
6073
6074 static VkResult
6075 radv_timeline_wait(struct radv_device *device,
6076 struct radv_timeline *timeline,
6077 uint64_t value,
6078 uint64_t abs_timeout)
6079 {
6080 pthread_mutex_lock(&timeline->mutex);
6081
6082 while(timeline->highest_submitted < value) {
6083 struct timespec abstime;
6084 timespec_from_nsec(&abstime, abs_timeout);
6085
6086 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
6087
6088 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value) {
6089 pthread_mutex_unlock(&timeline->mutex);
6090 return VK_TIMEOUT;
6091 }
6092 }
6093
6094 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
6095 pthread_mutex_unlock(&timeline->mutex);
6096 if (!point)
6097 return VK_SUCCESS;
6098
6099 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
6100
6101 pthread_mutex_lock(&timeline->mutex);
6102 point->wait_count--;
6103 pthread_mutex_unlock(&timeline->mutex);
6104 return success ? VK_SUCCESS : VK_TIMEOUT;
6105 }
6106
6107 static void
6108 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
6109 struct list_head *processing_list)
6110 {
6111 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
6112 &timeline->waiters, list) {
6113 if (waiter->value > timeline->highest_submitted)
6114 continue;
6115
6116 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
6117 list_del(&waiter->list);
6118 }
6119 }
6120
6121 static
6122 void radv_destroy_semaphore_part(struct radv_device *device,
6123 struct radv_semaphore_part *part)
6124 {
6125 switch(part->kind) {
6126 case RADV_SEMAPHORE_NONE:
6127 break;
6128 case RADV_SEMAPHORE_WINSYS:
6129 device->ws->destroy_sem(part->ws_sem);
6130 break;
6131 case RADV_SEMAPHORE_TIMELINE:
6132 radv_destroy_timeline(device, &part->timeline);
6133 break;
6134 case RADV_SEMAPHORE_SYNCOBJ:
6135 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
6136 device->ws->destroy_syncobj(device->ws, part->syncobj);
6137 break;
6138 }
6139 part->kind = RADV_SEMAPHORE_NONE;
6140 }
6141
6142 static VkSemaphoreTypeKHR
6143 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6144 {
6145 const VkSemaphoreTypeCreateInfo *type_info =
6146 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6147
6148 if (!type_info)
6149 return VK_SEMAPHORE_TYPE_BINARY;
6150
6151 if (initial_value)
6152 *initial_value = type_info->initialValue;
6153 return type_info->semaphoreType;
6154 }
6155
6156 static void
6157 radv_destroy_semaphore(struct radv_device *device,
6158 const VkAllocationCallbacks *pAllocator,
6159 struct radv_semaphore *sem)
6160 {
6161 radv_destroy_semaphore_part(device, &sem->temporary);
6162 radv_destroy_semaphore_part(device, &sem->permanent);
6163 vk_object_base_finish(&sem->base);
6164 vk_free2(&device->vk.alloc, pAllocator, sem);
6165 }
6166
6167 VkResult radv_CreateSemaphore(
6168 VkDevice _device,
6169 const VkSemaphoreCreateInfo* pCreateInfo,
6170 const VkAllocationCallbacks* pAllocator,
6171 VkSemaphore* pSemaphore)
6172 {
6173 RADV_FROM_HANDLE(radv_device, device, _device);
6174 const VkExportSemaphoreCreateInfo *export =
6175 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6176 VkExternalSemaphoreHandleTypeFlags handleTypes =
6177 export ? export->handleTypes : 0;
6178 uint64_t initial_value = 0;
6179 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6180
6181 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
6182 sizeof(*sem), 8,
6183 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6184 if (!sem)
6185 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6186
6187 vk_object_base_init(&device->vk, &sem->base,
6188 VK_OBJECT_TYPE_SEMAPHORE);
6189
6190 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6191 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6192
6193 if (type == VK_SEMAPHORE_TYPE_TIMELINE &&
6194 device->physical_device->rad_info.has_timeline_syncobj) {
6195 int ret = device->ws->create_syncobj(device->ws, false, &sem->permanent.syncobj);
6196 if (ret) {
6197 radv_destroy_semaphore(device, pAllocator, sem);
6198 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6199 }
6200 device->ws->signal_syncobj(device->ws, sem->permanent.syncobj, initial_value);
6201 sem->permanent.timeline_syncobj.max_point = initial_value;
6202 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
6203 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6204 radv_create_timeline(&sem->permanent.timeline, initial_value);
6205 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6206 } else if (device->always_use_syncobj || handleTypes) {
6207 assert (device->physical_device->rad_info.has_syncobj);
6208 int ret = device->ws->create_syncobj(device->ws, false,
6209 &sem->permanent.syncobj);
6210 if (ret) {
6211 radv_destroy_semaphore(device, pAllocator, sem);
6212 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6213 }
6214 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6215 } else {
6216 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6217 if (!sem->permanent.ws_sem) {
6218 radv_destroy_semaphore(device, pAllocator, sem);
6219 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6220 }
6221 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6222 }
6223
6224 *pSemaphore = radv_semaphore_to_handle(sem);
6225 return VK_SUCCESS;
6226 }
6227
6228 void radv_DestroySemaphore(
6229 VkDevice _device,
6230 VkSemaphore _semaphore,
6231 const VkAllocationCallbacks* pAllocator)
6232 {
6233 RADV_FROM_HANDLE(radv_device, device, _device);
6234 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6235 if (!_semaphore)
6236 return;
6237
6238 radv_destroy_semaphore(device, pAllocator, sem);
6239 }
6240
6241 VkResult
6242 radv_GetSemaphoreCounterValue(VkDevice _device,
6243 VkSemaphore _semaphore,
6244 uint64_t* pValue)
6245 {
6246 RADV_FROM_HANDLE(radv_device, device, _device);
6247 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6248
6249 if (radv_device_is_lost(device))
6250 return VK_ERROR_DEVICE_LOST;
6251
6252 struct radv_semaphore_part *part =
6253 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6254
6255 switch (part->kind) {
6256 case RADV_SEMAPHORE_TIMELINE: {
6257 pthread_mutex_lock(&part->timeline.mutex);
6258 radv_timeline_gc_locked(device, &part->timeline);
6259 *pValue = part->timeline.highest_signaled;
6260 pthread_mutex_unlock(&part->timeline.mutex);
6261 return VK_SUCCESS;
6262 }
6263 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6264 return device->ws->query_syncobj(device->ws, part->syncobj, pValue);
6265 }
6266 case RADV_SEMAPHORE_NONE:
6267 case RADV_SEMAPHORE_SYNCOBJ:
6268 case RADV_SEMAPHORE_WINSYS:
6269 unreachable("Invalid semaphore type");
6270 }
6271 unreachable("Unhandled semaphore type");
6272 }
6273
6274
6275 static VkResult
6276 radv_wait_timelines(struct radv_device *device,
6277 const VkSemaphoreWaitInfo* pWaitInfo,
6278 uint64_t abs_timeout)
6279 {
6280 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6281 for (;;) {
6282 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6283 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6284 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6285
6286 if (result == VK_SUCCESS)
6287 return VK_SUCCESS;
6288 }
6289 if (radv_get_current_time() > abs_timeout)
6290 return VK_TIMEOUT;
6291 }
6292 }
6293
6294 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6295 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6296 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6297
6298 if (result != VK_SUCCESS)
6299 return result;
6300 }
6301 return VK_SUCCESS;
6302 }
6303 VkResult
6304 radv_WaitSemaphores(VkDevice _device,
6305 const VkSemaphoreWaitInfo* pWaitInfo,
6306 uint64_t timeout)
6307 {
6308 RADV_FROM_HANDLE(radv_device, device, _device);
6309
6310 if (radv_device_is_lost(device))
6311 return VK_ERROR_DEVICE_LOST;
6312
6313 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6314
6315 if (radv_semaphore_from_handle(pWaitInfo->pSemaphores[0])->permanent.kind == RADV_SEMAPHORE_TIMELINE)
6316 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6317
6318 if (pWaitInfo->semaphoreCount > UINT32_MAX / sizeof(uint32_t))
6319 return vk_errorf(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY, "semaphoreCount integer overflow");
6320
6321 bool wait_all = !(pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR);
6322 uint32_t *handles = malloc(sizeof(*handles) * pWaitInfo->semaphoreCount);
6323 if (!handles)
6324 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6325
6326 for (uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6327 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6328 handles[i] = semaphore->permanent.syncobj;
6329 }
6330
6331 bool success = device->ws->wait_timeline_syncobj(device->ws, handles, pWaitInfo->pValues,
6332 pWaitInfo->semaphoreCount, wait_all, false,
6333 abs_timeout);
6334 free(handles);
6335 return success ? VK_SUCCESS : VK_TIMEOUT;
6336 }
6337
6338 VkResult
6339 radv_SignalSemaphore(VkDevice _device,
6340 const VkSemaphoreSignalInfo* pSignalInfo)
6341 {
6342 RADV_FROM_HANDLE(radv_device, device, _device);
6343 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6344
6345 struct radv_semaphore_part *part =
6346 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6347
6348 switch(part->kind) {
6349 case RADV_SEMAPHORE_TIMELINE: {
6350 pthread_mutex_lock(&part->timeline.mutex);
6351 radv_timeline_gc_locked(device, &part->timeline);
6352 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6353 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6354
6355 struct list_head processing_list;
6356 list_inithead(&processing_list);
6357 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6358 pthread_mutex_unlock(&part->timeline.mutex);
6359
6360 VkResult result = radv_process_submissions(&processing_list);
6361
6362 /* This needs to happen after radv_process_submissions, so
6363 * that any submitted submissions that are now unblocked get
6364 * processed before we wake the application. This way we
6365 * ensure that any binary semaphores that are now unblocked
6366 * are usable by the application. */
6367 pthread_cond_broadcast(&device->timeline_cond);
6368
6369 return result;
6370 }
6371 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6372 part->timeline_syncobj.max_point = MAX2(part->timeline_syncobj.max_point, pSignalInfo->value);
6373 device->ws->signal_syncobj(device->ws, part->syncobj, pSignalInfo->value);
6374 break;
6375 }
6376 case RADV_SEMAPHORE_NONE:
6377 case RADV_SEMAPHORE_SYNCOBJ:
6378 case RADV_SEMAPHORE_WINSYS:
6379 unreachable("Invalid semaphore type");
6380 }
6381 return VK_SUCCESS;
6382 }
6383
6384 static void radv_destroy_event(struct radv_device *device,
6385 const VkAllocationCallbacks* pAllocator,
6386 struct radv_event *event)
6387 {
6388 if (event->bo)
6389 device->ws->buffer_destroy(event->bo);
6390
6391 vk_object_base_finish(&event->base);
6392 vk_free2(&device->vk.alloc, pAllocator, event);
6393 }
6394
6395 VkResult radv_CreateEvent(
6396 VkDevice _device,
6397 const VkEventCreateInfo* pCreateInfo,
6398 const VkAllocationCallbacks* pAllocator,
6399 VkEvent* pEvent)
6400 {
6401 RADV_FROM_HANDLE(radv_device, device, _device);
6402 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6403 sizeof(*event), 8,
6404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6405
6406 if (!event)
6407 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6408
6409 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6410
6411 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6412 RADEON_DOMAIN_GTT,
6413 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6414 RADV_BO_PRIORITY_FENCE);
6415 if (!event->bo) {
6416 radv_destroy_event(device, pAllocator, event);
6417 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6418 }
6419
6420 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6421 if (!event->map) {
6422 radv_destroy_event(device, pAllocator, event);
6423 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6424 }
6425
6426 *pEvent = radv_event_to_handle(event);
6427
6428 return VK_SUCCESS;
6429 }
6430
6431 void radv_DestroyEvent(
6432 VkDevice _device,
6433 VkEvent _event,
6434 const VkAllocationCallbacks* pAllocator)
6435 {
6436 RADV_FROM_HANDLE(radv_device, device, _device);
6437 RADV_FROM_HANDLE(radv_event, event, _event);
6438
6439 if (!event)
6440 return;
6441
6442 radv_destroy_event(device, pAllocator, event);
6443 }
6444
6445 VkResult radv_GetEventStatus(
6446 VkDevice _device,
6447 VkEvent _event)
6448 {
6449 RADV_FROM_HANDLE(radv_device, device, _device);
6450 RADV_FROM_HANDLE(radv_event, event, _event);
6451
6452 if (radv_device_is_lost(device))
6453 return VK_ERROR_DEVICE_LOST;
6454
6455 if (*event->map == 1)
6456 return VK_EVENT_SET;
6457 return VK_EVENT_RESET;
6458 }
6459
6460 VkResult radv_SetEvent(
6461 VkDevice _device,
6462 VkEvent _event)
6463 {
6464 RADV_FROM_HANDLE(radv_event, event, _event);
6465 *event->map = 1;
6466
6467 return VK_SUCCESS;
6468 }
6469
6470 VkResult radv_ResetEvent(
6471 VkDevice _device,
6472 VkEvent _event)
6473 {
6474 RADV_FROM_HANDLE(radv_event, event, _event);
6475 *event->map = 0;
6476
6477 return VK_SUCCESS;
6478 }
6479
6480 static void
6481 radv_destroy_buffer(struct radv_device *device,
6482 const VkAllocationCallbacks *pAllocator,
6483 struct radv_buffer *buffer)
6484 {
6485 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6486 device->ws->buffer_destroy(buffer->bo);
6487
6488 vk_object_base_finish(&buffer->base);
6489 vk_free2(&device->vk.alloc, pAllocator, buffer);
6490 }
6491
6492 VkResult radv_CreateBuffer(
6493 VkDevice _device,
6494 const VkBufferCreateInfo* pCreateInfo,
6495 const VkAllocationCallbacks* pAllocator,
6496 VkBuffer* pBuffer)
6497 {
6498 RADV_FROM_HANDLE(radv_device, device, _device);
6499 struct radv_buffer *buffer;
6500
6501 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6502 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6503
6504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6505
6506 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6507 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6508 if (buffer == NULL)
6509 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6510
6511 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6512
6513 buffer->size = pCreateInfo->size;
6514 buffer->usage = pCreateInfo->usage;
6515 buffer->bo = NULL;
6516 buffer->offset = 0;
6517 buffer->flags = pCreateInfo->flags;
6518
6519 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6520 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6521
6522 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6523 buffer->bo = device->ws->buffer_create(device->ws,
6524 align64(buffer->size, 4096),
6525 4096, 0, RADEON_FLAG_VIRTUAL,
6526 RADV_BO_PRIORITY_VIRTUAL);
6527 if (!buffer->bo) {
6528 radv_destroy_buffer(device, pAllocator, buffer);
6529 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6530 }
6531 }
6532
6533 *pBuffer = radv_buffer_to_handle(buffer);
6534
6535 return VK_SUCCESS;
6536 }
6537
6538 void radv_DestroyBuffer(
6539 VkDevice _device,
6540 VkBuffer _buffer,
6541 const VkAllocationCallbacks* pAllocator)
6542 {
6543 RADV_FROM_HANDLE(radv_device, device, _device);
6544 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6545
6546 if (!buffer)
6547 return;
6548
6549 radv_destroy_buffer(device, pAllocator, buffer);
6550 }
6551
6552 VkDeviceAddress radv_GetBufferDeviceAddress(
6553 VkDevice device,
6554 const VkBufferDeviceAddressInfo* pInfo)
6555 {
6556 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6557 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6558 }
6559
6560
6561 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6562 const VkBufferDeviceAddressInfo* pInfo)
6563 {
6564 return 0;
6565 }
6566
6567 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6568 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6569 {
6570 return 0;
6571 }
6572
6573 static inline unsigned
6574 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6575 {
6576 if (stencil)
6577 return plane->surface.u.legacy.stencil_tiling_index[level];
6578 else
6579 return plane->surface.u.legacy.tiling_index[level];
6580 }
6581
6582 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6583 {
6584 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6585 }
6586
6587 static uint32_t
6588 radv_init_dcc_control_reg(struct radv_device *device,
6589 struct radv_image_view *iview)
6590 {
6591 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6592 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6593 unsigned max_compressed_block_size;
6594 unsigned independent_128b_blocks;
6595 unsigned independent_64b_blocks;
6596
6597 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6598 return 0;
6599
6600 if (!device->physical_device->rad_info.has_dedicated_vram) {
6601 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6602 * dGPU and 64 for APU because all of our APUs to date use
6603 * DIMMs which have a request granularity size of 64B while all
6604 * other chips have a 32B request size.
6605 */
6606 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6607 }
6608
6609 if (device->physical_device->rad_info.chip_class >= GFX10) {
6610 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6611 independent_64b_blocks = 0;
6612 independent_128b_blocks = 1;
6613 } else {
6614 independent_128b_blocks = 0;
6615
6616 if (iview->image->info.samples > 1) {
6617 if (iview->image->planes[0].surface.bpe == 1)
6618 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6619 else if (iview->image->planes[0].surface.bpe == 2)
6620 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6621 }
6622
6623 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6624 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6625 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6626 /* If this DCC image is potentially going to be used in texture
6627 * fetches, we need some special settings.
6628 */
6629 independent_64b_blocks = 1;
6630 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6631 } else {
6632 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6633 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6634 * big as possible for better compression state.
6635 */
6636 independent_64b_blocks = 0;
6637 max_compressed_block_size = max_uncompressed_block_size;
6638 }
6639 }
6640
6641 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6642 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6643 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6644 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6645 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6646 }
6647
6648 void
6649 radv_initialise_color_surface(struct radv_device *device,
6650 struct radv_color_buffer_info *cb,
6651 struct radv_image_view *iview)
6652 {
6653 const struct vk_format_description *desc;
6654 unsigned ntype, format, swap, endian;
6655 unsigned blend_clamp = 0, blend_bypass = 0;
6656 uint64_t va;
6657 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6658 const struct radeon_surf *surf = &plane->surface;
6659
6660 desc = vk_format_description(iview->vk_format);
6661
6662 memset(cb, 0, sizeof(*cb));
6663
6664 /* Intensity is implemented as Red, so treat it that way. */
6665 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6666
6667 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6668
6669 cb->cb_color_base = va >> 8;
6670
6671 if (device->physical_device->rad_info.chip_class >= GFX9) {
6672 if (device->physical_device->rad_info.chip_class >= GFX10) {
6673 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6674 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6675 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6676 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6677 } else {
6678 struct gfx9_surf_meta_flags meta = {
6679 .rb_aligned = 1,
6680 .pipe_aligned = 1,
6681 };
6682
6683 if (surf->dcc_offset)
6684 meta = surf->u.gfx9.dcc;
6685
6686 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6687 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6688 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6689 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6690 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6691 }
6692
6693 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6694 cb->cb_color_base |= surf->tile_swizzle;
6695 } else {
6696 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6697 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6698
6699 cb->cb_color_base += level_info->offset >> 8;
6700 if (level_info->mode == RADEON_SURF_MODE_2D)
6701 cb->cb_color_base |= surf->tile_swizzle;
6702
6703 pitch_tile_max = level_info->nblk_x / 8 - 1;
6704 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6705 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6706
6707 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6708 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6709 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6710
6711 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6712
6713 if (radv_image_has_fmask(iview->image)) {
6714 if (device->physical_device->rad_info.chip_class >= GFX7)
6715 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6716 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6717 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6718 } else {
6719 /* This must be set for fast clear to work without FMASK. */
6720 if (device->physical_device->rad_info.chip_class >= GFX7)
6721 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6722 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6723 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6724 }
6725 }
6726
6727 /* CMASK variables */
6728 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6729 va += surf->cmask_offset;
6730 cb->cb_color_cmask = va >> 8;
6731
6732 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6733 va += surf->dcc_offset;
6734
6735 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6736 device->physical_device->rad_info.chip_class <= GFX8)
6737 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6738
6739 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6740 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6741
6742 cb->cb_dcc_base = va >> 8;
6743 cb->cb_dcc_base |= dcc_tile_swizzle;
6744
6745 /* GFX10 field has the same base shift as the GFX6 field. */
6746 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6747 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6748 S_028C6C_SLICE_MAX_GFX10(max_slice);
6749
6750 if (iview->image->info.samples > 1) {
6751 unsigned log_samples = util_logbase2(iview->image->info.samples);
6752
6753 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6754 S_028C74_NUM_FRAGMENTS(log_samples);
6755 }
6756
6757 if (radv_image_has_fmask(iview->image)) {
6758 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6759 cb->cb_color_fmask = va >> 8;
6760 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6761 } else {
6762 cb->cb_color_fmask = cb->cb_color_base;
6763 }
6764
6765 ntype = radv_translate_color_numformat(iview->vk_format,
6766 desc,
6767 vk_format_get_first_non_void_channel(iview->vk_format));
6768 format = radv_translate_colorformat(iview->vk_format);
6769 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6770 radv_finishme("Illegal color\n");
6771 swap = radv_translate_colorswap(iview->vk_format, false);
6772 endian = radv_colorformat_endian_swap(format);
6773
6774 /* blend clamp should be set for all NORM/SRGB types */
6775 if (ntype == V_028C70_NUMBER_UNORM ||
6776 ntype == V_028C70_NUMBER_SNORM ||
6777 ntype == V_028C70_NUMBER_SRGB)
6778 blend_clamp = 1;
6779
6780 /* set blend bypass according to docs if SINT/UINT or
6781 8/24 COLOR variants */
6782 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6783 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6784 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6785 blend_clamp = 0;
6786 blend_bypass = 1;
6787 }
6788 #if 0
6789 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6790 (format == V_028C70_COLOR_8 ||
6791 format == V_028C70_COLOR_8_8 ||
6792 format == V_028C70_COLOR_8_8_8_8))
6793 ->color_is_int8 = true;
6794 #endif
6795 cb->cb_color_info = S_028C70_FORMAT(format) |
6796 S_028C70_COMP_SWAP(swap) |
6797 S_028C70_BLEND_CLAMP(blend_clamp) |
6798 S_028C70_BLEND_BYPASS(blend_bypass) |
6799 S_028C70_SIMPLE_FLOAT(1) |
6800 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6801 ntype != V_028C70_NUMBER_SNORM &&
6802 ntype != V_028C70_NUMBER_SRGB &&
6803 format != V_028C70_COLOR_8_24 &&
6804 format != V_028C70_COLOR_24_8) |
6805 S_028C70_NUMBER_TYPE(ntype) |
6806 S_028C70_ENDIAN(endian);
6807 if (radv_image_has_fmask(iview->image)) {
6808 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6809 if (device->physical_device->rad_info.chip_class == GFX6) {
6810 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6811 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6812 }
6813
6814 if (radv_image_is_tc_compat_cmask(iview->image)) {
6815 /* Allow the texture block to read FMASK directly
6816 * without decompressing it. This bit must be cleared
6817 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6818 * otherwise the operation doesn't happen.
6819 */
6820 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6821
6822 /* Set CMASK into a tiling format that allows the
6823 * texture block to read it.
6824 */
6825 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6826 }
6827 }
6828
6829 if (radv_image_has_cmask(iview->image) &&
6830 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6831 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6832
6833 if (radv_dcc_enabled(iview->image, iview->base_mip))
6834 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6835
6836 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6837
6838 /* This must be set for fast clear to work without FMASK. */
6839 if (!radv_image_has_fmask(iview->image) &&
6840 device->physical_device->rad_info.chip_class == GFX6) {
6841 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6842 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6843 }
6844
6845 if (device->physical_device->rad_info.chip_class >= GFX9) {
6846 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6847
6848 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6849 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6850 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6851 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6852
6853 if (device->physical_device->rad_info.chip_class >= GFX10) {
6854 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6855
6856 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6857 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6858 S_028EE0_RESOURCE_LEVEL(1);
6859 } else {
6860 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6861 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6862 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6863 }
6864
6865 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6866 S_028C68_MIP0_HEIGHT(height - 1) |
6867 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6868 }
6869 }
6870
6871 static unsigned
6872 radv_calc_decompress_on_z_planes(struct radv_device *device,
6873 struct radv_image_view *iview)
6874 {
6875 unsigned max_zplanes = 0;
6876
6877 assert(radv_image_is_tc_compat_htile(iview->image));
6878
6879 if (device->physical_device->rad_info.chip_class >= GFX9) {
6880 /* Default value for 32-bit depth surfaces. */
6881 max_zplanes = 4;
6882
6883 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6884 iview->image->info.samples > 1)
6885 max_zplanes = 2;
6886
6887 max_zplanes = max_zplanes + 1;
6888 } else {
6889 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6890 /* Do not enable Z plane compression for 16-bit depth
6891 * surfaces because isn't supported on GFX8. Only
6892 * 32-bit depth surfaces are supported by the hardware.
6893 * This allows to maintain shader compatibility and to
6894 * reduce the number of depth decompressions.
6895 */
6896 max_zplanes = 1;
6897 } else {
6898 if (iview->image->info.samples <= 1)
6899 max_zplanes = 5;
6900 else if (iview->image->info.samples <= 4)
6901 max_zplanes = 3;
6902 else
6903 max_zplanes = 2;
6904 }
6905 }
6906
6907 return max_zplanes;
6908 }
6909
6910 void
6911 radv_initialise_ds_surface(struct radv_device *device,
6912 struct radv_ds_buffer_info *ds,
6913 struct radv_image_view *iview)
6914 {
6915 unsigned level = iview->base_mip;
6916 unsigned format, stencil_format;
6917 uint64_t va, s_offs, z_offs;
6918 bool stencil_only = false;
6919 const struct radv_image_plane *plane = &iview->image->planes[0];
6920 const struct radeon_surf *surf = &plane->surface;
6921
6922 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6923
6924 memset(ds, 0, sizeof(*ds));
6925 switch (iview->image->vk_format) {
6926 case VK_FORMAT_D24_UNORM_S8_UINT:
6927 case VK_FORMAT_X8_D24_UNORM_PACK32:
6928 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6929 ds->offset_scale = 2.0f;
6930 break;
6931 case VK_FORMAT_D16_UNORM:
6932 case VK_FORMAT_D16_UNORM_S8_UINT:
6933 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6934 ds->offset_scale = 4.0f;
6935 break;
6936 case VK_FORMAT_D32_SFLOAT:
6937 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6938 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6939 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6940 ds->offset_scale = 1.0f;
6941 break;
6942 case VK_FORMAT_S8_UINT:
6943 stencil_only = true;
6944 break;
6945 default:
6946 break;
6947 }
6948
6949 format = radv_translate_dbformat(iview->image->vk_format);
6950 stencil_format = surf->has_stencil ?
6951 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6952
6953 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6954 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6955 S_028008_SLICE_MAX(max_slice);
6956 if (device->physical_device->rad_info.chip_class >= GFX10) {
6957 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6958 S_028008_SLICE_MAX_HI(max_slice >> 11);
6959 }
6960
6961 ds->db_htile_data_base = 0;
6962 ds->db_htile_surface = 0;
6963
6964 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6965 s_offs = z_offs = va;
6966
6967 if (device->physical_device->rad_info.chip_class >= GFX9) {
6968 assert(surf->u.gfx9.surf_offset == 0);
6969 s_offs += surf->u.gfx9.stencil_offset;
6970
6971 ds->db_z_info = S_028038_FORMAT(format) |
6972 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6973 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6974 S_028038_MAXMIP(iview->image->info.levels - 1) |
6975 S_028038_ZRANGE_PRECISION(1);
6976 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6977 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6978
6979 if (device->physical_device->rad_info.chip_class == GFX9) {
6980 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6981 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6982 }
6983
6984 ds->db_depth_view |= S_028008_MIPID(level);
6985 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6986 S_02801C_Y_MAX(iview->image->info.height - 1);
6987
6988 if (radv_htile_enabled(iview->image, level)) {
6989 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6990
6991 if (radv_image_is_tc_compat_htile(iview->image)) {
6992 unsigned max_zplanes =
6993 radv_calc_decompress_on_z_planes(device, iview);
6994
6995 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6996
6997 if (device->physical_device->rad_info.chip_class >= GFX10) {
6998 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6999 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
7000 } else {
7001 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
7002 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
7003 }
7004 }
7005
7006 if (!surf->has_stencil)
7007 /* Use all of the htile_buffer for depth if there's no stencil. */
7008 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
7009 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7010 surf->htile_offset;
7011 ds->db_htile_data_base = va >> 8;
7012 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
7013 S_028ABC_PIPE_ALIGNED(1);
7014
7015 if (device->physical_device->rad_info.chip_class == GFX9) {
7016 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
7017 }
7018 }
7019 } else {
7020 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
7021
7022 if (stencil_only)
7023 level_info = &surf->u.legacy.stencil_level[level];
7024
7025 z_offs += surf->u.legacy.level[level].offset;
7026 s_offs += surf->u.legacy.stencil_level[level].offset;
7027
7028 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
7029 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
7030 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
7031
7032 if (iview->image->info.samples > 1)
7033 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
7034
7035 if (device->physical_device->rad_info.chip_class >= GFX7) {
7036 struct radeon_info *info = &device->physical_device->rad_info;
7037 unsigned tiling_index = surf->u.legacy.tiling_index[level];
7038 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
7039 unsigned macro_index = surf->u.legacy.macro_tile_index;
7040 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
7041 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
7042 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
7043
7044 if (stencil_only)
7045 tile_mode = stencil_tile_mode;
7046
7047 ds->db_depth_info |=
7048 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
7049 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
7050 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
7051 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
7052 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
7053 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
7054 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
7055 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
7056 } else {
7057 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
7058 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7059 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
7060 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
7061 if (stencil_only)
7062 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7063 }
7064
7065 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
7066 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
7067 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
7068
7069 if (radv_htile_enabled(iview->image, level)) {
7070 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
7071
7072 if (!surf->has_stencil &&
7073 !radv_image_is_tc_compat_htile(iview->image))
7074 /* Use all of the htile_buffer for depth if there's no stencil. */
7075 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
7076
7077 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7078 surf->htile_offset;
7079 ds->db_htile_data_base = va >> 8;
7080 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
7081
7082 if (radv_image_is_tc_compat_htile(iview->image)) {
7083 unsigned max_zplanes =
7084 radv_calc_decompress_on_z_planes(device, iview);
7085
7086 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
7087 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
7088 }
7089 }
7090 }
7091
7092 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
7093 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
7094 }
7095
7096 VkResult radv_CreateFramebuffer(
7097 VkDevice _device,
7098 const VkFramebufferCreateInfo* pCreateInfo,
7099 const VkAllocationCallbacks* pAllocator,
7100 VkFramebuffer* pFramebuffer)
7101 {
7102 RADV_FROM_HANDLE(radv_device, device, _device);
7103 struct radv_framebuffer *framebuffer;
7104 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
7105 vk_find_struct_const(pCreateInfo->pNext,
7106 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
7107
7108 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
7109
7110 size_t size = sizeof(*framebuffer);
7111 if (!imageless_create_info)
7112 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
7113 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
7114 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7115 if (framebuffer == NULL)
7116 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7117
7118 vk_object_base_init(&device->vk, &framebuffer->base,
7119 VK_OBJECT_TYPE_FRAMEBUFFER);
7120
7121 framebuffer->attachment_count = pCreateInfo->attachmentCount;
7122 framebuffer->width = pCreateInfo->width;
7123 framebuffer->height = pCreateInfo->height;
7124 framebuffer->layers = pCreateInfo->layers;
7125 if (imageless_create_info) {
7126 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
7127 const VkFramebufferAttachmentImageInfo *attachment =
7128 imageless_create_info->pAttachmentImageInfos + i;
7129 framebuffer->width = MIN2(framebuffer->width, attachment->width);
7130 framebuffer->height = MIN2(framebuffer->height, attachment->height);
7131 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
7132 }
7133 } else {
7134 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
7135 VkImageView _iview = pCreateInfo->pAttachments[i];
7136 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
7137 framebuffer->attachments[i] = iview;
7138 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
7139 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
7140 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
7141 }
7142 }
7143
7144 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
7145 return VK_SUCCESS;
7146 }
7147
7148 void radv_DestroyFramebuffer(
7149 VkDevice _device,
7150 VkFramebuffer _fb,
7151 const VkAllocationCallbacks* pAllocator)
7152 {
7153 RADV_FROM_HANDLE(radv_device, device, _device);
7154 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
7155
7156 if (!fb)
7157 return;
7158 vk_object_base_finish(&fb->base);
7159 vk_free2(&device->vk.alloc, pAllocator, fb);
7160 }
7161
7162 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
7163 {
7164 switch (address_mode) {
7165 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
7166 return V_008F30_SQ_TEX_WRAP;
7167 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
7168 return V_008F30_SQ_TEX_MIRROR;
7169 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
7170 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
7171 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
7172 return V_008F30_SQ_TEX_CLAMP_BORDER;
7173 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
7174 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
7175 default:
7176 unreachable("illegal tex wrap mode");
7177 break;
7178 }
7179 }
7180
7181 static unsigned
7182 radv_tex_compare(VkCompareOp op)
7183 {
7184 switch (op) {
7185 case VK_COMPARE_OP_NEVER:
7186 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7187 case VK_COMPARE_OP_LESS:
7188 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
7189 case VK_COMPARE_OP_EQUAL:
7190 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
7191 case VK_COMPARE_OP_LESS_OR_EQUAL:
7192 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
7193 case VK_COMPARE_OP_GREATER:
7194 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
7195 case VK_COMPARE_OP_NOT_EQUAL:
7196 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
7197 case VK_COMPARE_OP_GREATER_OR_EQUAL:
7198 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
7199 case VK_COMPARE_OP_ALWAYS:
7200 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
7201 default:
7202 unreachable("illegal compare mode");
7203 break;
7204 }
7205 }
7206
7207 static unsigned
7208 radv_tex_filter(VkFilter filter, unsigned max_ansio)
7209 {
7210 switch (filter) {
7211 case VK_FILTER_NEAREST:
7212 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
7213 V_008F38_SQ_TEX_XY_FILTER_POINT);
7214 case VK_FILTER_LINEAR:
7215 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
7216 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
7217 case VK_FILTER_CUBIC_IMG:
7218 default:
7219 fprintf(stderr, "illegal texture filter");
7220 return 0;
7221 }
7222 }
7223
7224 static unsigned
7225 radv_tex_mipfilter(VkSamplerMipmapMode mode)
7226 {
7227 switch (mode) {
7228 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7229 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7230 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7231 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7232 default:
7233 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7234 }
7235 }
7236
7237 static unsigned
7238 radv_tex_bordercolor(VkBorderColor bcolor)
7239 {
7240 switch (bcolor) {
7241 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7242 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7243 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7244 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7245 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7246 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7247 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7248 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7249 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7250 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
7251 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
7252 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
7253 default:
7254 break;
7255 }
7256 return 0;
7257 }
7258
7259 static unsigned
7260 radv_tex_aniso_filter(unsigned filter)
7261 {
7262 if (filter < 2)
7263 return 0;
7264 if (filter < 4)
7265 return 1;
7266 if (filter < 8)
7267 return 2;
7268 if (filter < 16)
7269 return 3;
7270 return 4;
7271 }
7272
7273 static unsigned
7274 radv_tex_filter_mode(VkSamplerReductionMode mode)
7275 {
7276 switch (mode) {
7277 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7278 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7279 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7280 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7281 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7282 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7283 default:
7284 break;
7285 }
7286 return 0;
7287 }
7288
7289 static uint32_t
7290 radv_get_max_anisotropy(struct radv_device *device,
7291 const VkSamplerCreateInfo *pCreateInfo)
7292 {
7293 if (device->force_aniso >= 0)
7294 return device->force_aniso;
7295
7296 if (pCreateInfo->anisotropyEnable &&
7297 pCreateInfo->maxAnisotropy > 1.0f)
7298 return (uint32_t)pCreateInfo->maxAnisotropy;
7299
7300 return 0;
7301 }
7302
7303 static inline int S_FIXED(float value, unsigned frac_bits)
7304 {
7305 return value * (1 << frac_bits);
7306 }
7307
7308 static uint32_t radv_register_border_color(struct radv_device *device,
7309 VkClearColorValue value)
7310 {
7311 uint32_t slot;
7312
7313 pthread_mutex_lock(&device->border_color_data.mutex);
7314
7315 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
7316 if (!device->border_color_data.used[slot]) {
7317 /* Copy to the GPU wrt endian-ness. */
7318 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7319 &value,
7320 sizeof(VkClearColorValue));
7321
7322 device->border_color_data.used[slot] = true;
7323 break;
7324 }
7325 }
7326
7327 pthread_mutex_unlock(&device->border_color_data.mutex);
7328
7329 return slot;
7330 }
7331
7332 static void radv_unregister_border_color(struct radv_device *device,
7333 uint32_t slot)
7334 {
7335 pthread_mutex_lock(&device->border_color_data.mutex);
7336
7337 device->border_color_data.used[slot] = false;
7338
7339 pthread_mutex_unlock(&device->border_color_data.mutex);
7340 }
7341
7342 static void
7343 radv_init_sampler(struct radv_device *device,
7344 struct radv_sampler *sampler,
7345 const VkSamplerCreateInfo *pCreateInfo)
7346 {
7347 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7348 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7349 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7350 device->physical_device->rad_info.chip_class == GFX9;
7351 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7352 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7353 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7354 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7355 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7356 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7357 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7358 uint32_t border_color_ptr;
7359
7360 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7361 vk_find_struct_const(pCreateInfo->pNext,
7362 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7363 if (sampler_reduction)
7364 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7365
7366 if (pCreateInfo->compareEnable)
7367 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7368
7369 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7370
7371 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7372 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7373 vk_find_struct_const(pCreateInfo->pNext,
7374 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7375
7376 assert(custom_border_color);
7377
7378 sampler->border_color_slot =
7379 radv_register_border_color(device, custom_border_color->customBorderColor);
7380
7381 /* Did we fail to find a slot? */
7382 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7383 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7384 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7385 }
7386 }
7387
7388 /* If we don't have a custom color, set the ptr to 0 */
7389 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7390 ? sampler->border_color_slot
7391 : 0;
7392
7393 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7394 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7395 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7396 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7397 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7398 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7399 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7400 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7401 S_008F30_DISABLE_CUBE_WRAP(0) |
7402 S_008F30_COMPAT_MODE(compat_mode) |
7403 S_008F30_FILTER_MODE(filter_mode) |
7404 S_008F30_TRUNC_COORD(trunc_coord));
7405 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7406 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7407 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7408 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7409 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7410 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7411 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7412 S_008F38_MIP_POINT_PRECLAMP(0));
7413 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7414 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7415
7416 if (device->physical_device->rad_info.chip_class >= GFX10) {
7417 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7418 } else {
7419 sampler->state[2] |=
7420 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7421 S_008F38_FILTER_PREC_FIX(1) |
7422 S_008F38_ANISO_OVERRIDE_GFX8(device->physical_device->rad_info.chip_class >= GFX8);
7423 }
7424 }
7425
7426 VkResult radv_CreateSampler(
7427 VkDevice _device,
7428 const VkSamplerCreateInfo* pCreateInfo,
7429 const VkAllocationCallbacks* pAllocator,
7430 VkSampler* pSampler)
7431 {
7432 RADV_FROM_HANDLE(radv_device, device, _device);
7433 struct radv_sampler *sampler;
7434
7435 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7436 vk_find_struct_const(pCreateInfo->pNext,
7437 SAMPLER_YCBCR_CONVERSION_INFO);
7438
7439 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7440
7441 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7442 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7443 if (!sampler)
7444 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7445
7446 vk_object_base_init(&device->vk, &sampler->base,
7447 VK_OBJECT_TYPE_SAMPLER);
7448
7449 radv_init_sampler(device, sampler, pCreateInfo);
7450
7451 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7452 *pSampler = radv_sampler_to_handle(sampler);
7453
7454 return VK_SUCCESS;
7455 }
7456
7457 void radv_DestroySampler(
7458 VkDevice _device,
7459 VkSampler _sampler,
7460 const VkAllocationCallbacks* pAllocator)
7461 {
7462 RADV_FROM_HANDLE(radv_device, device, _device);
7463 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7464
7465 if (!sampler)
7466 return;
7467
7468 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7469 radv_unregister_border_color(device, sampler->border_color_slot);
7470
7471 vk_object_base_finish(&sampler->base);
7472 vk_free2(&device->vk.alloc, pAllocator, sampler);
7473 }
7474
7475 /* vk_icd.h does not declare this function, so we declare it here to
7476 * suppress Wmissing-prototypes.
7477 */
7478 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7479 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7480
7481 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7482 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7483 {
7484 /* For the full details on loader interface versioning, see
7485 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7486 * What follows is a condensed summary, to help you navigate the large and
7487 * confusing official doc.
7488 *
7489 * - Loader interface v0 is incompatible with later versions. We don't
7490 * support it.
7491 *
7492 * - In loader interface v1:
7493 * - The first ICD entrypoint called by the loader is
7494 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7495 * entrypoint.
7496 * - The ICD must statically expose no other Vulkan symbol unless it is
7497 * linked with -Bsymbolic.
7498 * - Each dispatchable Vulkan handle created by the ICD must be
7499 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7500 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7501 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7502 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7503 * such loader-managed surfaces.
7504 *
7505 * - Loader interface v2 differs from v1 in:
7506 * - The first ICD entrypoint called by the loader is
7507 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7508 * statically expose this entrypoint.
7509 *
7510 * - Loader interface v3 differs from v2 in:
7511 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7512 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7513 * because the loader no longer does so.
7514 */
7515 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7516 return VK_SUCCESS;
7517 }
7518
7519 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7520 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7521 int *pFD)
7522 {
7523 RADV_FROM_HANDLE(radv_device, device, _device);
7524 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7525
7526 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7527
7528 /* At the moment, we support only the below handle types. */
7529 assert(pGetFdInfo->handleType ==
7530 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7531 pGetFdInfo->handleType ==
7532 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7533
7534 bool ret = radv_get_memory_fd(device, memory, pFD);
7535 if (ret == false)
7536 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7537 return VK_SUCCESS;
7538 }
7539
7540 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7541 enum radeon_bo_domain domains,
7542 enum radeon_bo_flag flags,
7543 enum radeon_bo_flag ignore_flags)
7544 {
7545 /* Don't count GTT/CPU as relevant:
7546 *
7547 * - We're not fully consistent between the two.
7548 * - Sometimes VRAM gets VRAM|GTT.
7549 */
7550 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7551 RADEON_DOMAIN_GDS |
7552 RADEON_DOMAIN_OA;
7553 uint32_t bits = 0;
7554 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7555 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7556 continue;
7557
7558 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7559 continue;
7560
7561 bits |= 1u << i;
7562 }
7563
7564 return bits;
7565 }
7566
7567 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7568 enum radeon_bo_domain domains,
7569 enum radeon_bo_flag flags)
7570 {
7571 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7572 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7573
7574 if (!bits) {
7575 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7576 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7577 }
7578
7579 return bits;
7580 }
7581 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7582 VkExternalMemoryHandleTypeFlagBits handleType,
7583 int fd,
7584 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7585 {
7586 RADV_FROM_HANDLE(radv_device, device, _device);
7587
7588 switch (handleType) {
7589 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7590 enum radeon_bo_domain domains;
7591 enum radeon_bo_flag flags;
7592 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7593 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7594
7595 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7596 return VK_SUCCESS;
7597 }
7598 default:
7599 /* The valid usage section for this function says:
7600 *
7601 * "handleType must not be one of the handle types defined as
7602 * opaque."
7603 *
7604 * So opaque handle types fall into the default "unsupported" case.
7605 */
7606 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7607 }
7608 }
7609
7610 static VkResult radv_import_opaque_fd(struct radv_device *device,
7611 int fd,
7612 uint32_t *syncobj)
7613 {
7614 uint32_t syncobj_handle = 0;
7615 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7616 if (ret != 0)
7617 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7618
7619 if (*syncobj)
7620 device->ws->destroy_syncobj(device->ws, *syncobj);
7621
7622 *syncobj = syncobj_handle;
7623 close(fd);
7624
7625 return VK_SUCCESS;
7626 }
7627
7628 static VkResult radv_import_sync_fd(struct radv_device *device,
7629 int fd,
7630 uint32_t *syncobj)
7631 {
7632 /* If we create a syncobj we do it locally so that if we have an error, we don't
7633 * leave a syncobj in an undetermined state in the fence. */
7634 uint32_t syncobj_handle = *syncobj;
7635 if (!syncobj_handle) {
7636 bool create_signaled = fd == -1 ? true : false;
7637
7638 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7639 &syncobj_handle);
7640 if (ret) {
7641 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7642 }
7643 } else {
7644 if (fd == -1)
7645 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7646 }
7647
7648 if (fd != -1) {
7649 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7650 if (ret)
7651 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7652 close(fd);
7653 }
7654
7655 *syncobj = syncobj_handle;
7656
7657 return VK_SUCCESS;
7658 }
7659
7660 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7661 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7662 {
7663 RADV_FROM_HANDLE(radv_device, device, _device);
7664 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7665 VkResult result;
7666 struct radv_semaphore_part *dst = NULL;
7667 bool timeline = sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7668
7669 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7670 assert(!timeline);
7671 dst = &sem->temporary;
7672 } else {
7673 dst = &sem->permanent;
7674 }
7675
7676 uint32_t syncobj = (dst->kind == RADV_SEMAPHORE_SYNCOBJ ||
7677 dst->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) ? dst->syncobj : 0;
7678
7679 switch(pImportSemaphoreFdInfo->handleType) {
7680 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7681 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7682 break;
7683 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7684 assert(!timeline);
7685 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7686 break;
7687 default:
7688 unreachable("Unhandled semaphore handle type");
7689 }
7690
7691 if (result == VK_SUCCESS) {
7692 dst->syncobj = syncobj;
7693 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7694 if (timeline) {
7695 dst->kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7696 dst->timeline_syncobj.max_point = 0;
7697 }
7698 }
7699
7700 return result;
7701 }
7702
7703 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7704 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7705 int *pFd)
7706 {
7707 RADV_FROM_HANDLE(radv_device, device, _device);
7708 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7709 int ret;
7710 uint32_t syncobj_handle;
7711
7712 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7713 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ ||
7714 sem->temporary.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7715 syncobj_handle = sem->temporary.syncobj;
7716 } else {
7717 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ ||
7718 sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7719 syncobj_handle = sem->permanent.syncobj;
7720 }
7721
7722 switch(pGetFdInfo->handleType) {
7723 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7724 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7725 if (ret)
7726 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7727 break;
7728 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7729 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7730 if (ret)
7731 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7732
7733 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7734 radv_destroy_semaphore_part(device, &sem->temporary);
7735 } else {
7736 device->ws->reset_syncobj(device->ws, syncobj_handle);
7737 }
7738 break;
7739 default:
7740 unreachable("Unhandled semaphore handle type");
7741 }
7742
7743 return VK_SUCCESS;
7744 }
7745
7746 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7747 VkPhysicalDevice physicalDevice,
7748 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7749 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7750 {
7751 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7752 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7753
7754 if (type == VK_SEMAPHORE_TYPE_TIMELINE && pdevice->rad_info.has_timeline_syncobj &&
7755 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7756 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7757 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7758 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7759 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7760 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7761 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7762 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7763 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7764
7765 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7766 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7767 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7768 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7769 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7770 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7771 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7772 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7773 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7774 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7775 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7776 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7777 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7778 } else {
7779 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7780 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7781 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7782 }
7783 }
7784
7785 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7786 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7787 {
7788 RADV_FROM_HANDLE(radv_device, device, _device);
7789 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7790 struct radv_fence_part *dst = NULL;
7791 VkResult result;
7792
7793 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7794 dst = &fence->temporary;
7795 } else {
7796 dst = &fence->permanent;
7797 }
7798
7799 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7800
7801 switch(pImportFenceFdInfo->handleType) {
7802 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7803 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7804 break;
7805 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7806 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7807 break;
7808 default:
7809 unreachable("Unhandled fence handle type");
7810 }
7811
7812 if (result == VK_SUCCESS) {
7813 dst->syncobj = syncobj;
7814 dst->kind = RADV_FENCE_SYNCOBJ;
7815 }
7816
7817 return result;
7818 }
7819
7820 VkResult radv_GetFenceFdKHR(VkDevice _device,
7821 const VkFenceGetFdInfoKHR *pGetFdInfo,
7822 int *pFd)
7823 {
7824 RADV_FROM_HANDLE(radv_device, device, _device);
7825 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7826 int ret;
7827
7828 struct radv_fence_part *part =
7829 fence->temporary.kind != RADV_FENCE_NONE ?
7830 &fence->temporary : &fence->permanent;
7831
7832 switch(pGetFdInfo->handleType) {
7833 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7834 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7835 if (ret)
7836 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7837 break;
7838 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7839 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7840 part->syncobj, pFd);
7841 if (ret)
7842 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7843
7844 if (part == &fence->temporary) {
7845 radv_destroy_fence_part(device, part);
7846 } else {
7847 device->ws->reset_syncobj(device->ws, part->syncobj);
7848 }
7849 break;
7850 default:
7851 unreachable("Unhandled fence handle type");
7852 }
7853
7854 return VK_SUCCESS;
7855 }
7856
7857 void radv_GetPhysicalDeviceExternalFenceProperties(
7858 VkPhysicalDevice physicalDevice,
7859 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7860 VkExternalFenceProperties *pExternalFenceProperties)
7861 {
7862 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7863
7864 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7865 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7866 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7867 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7868 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7869 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7870 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7871 } else {
7872 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7873 pExternalFenceProperties->compatibleHandleTypes = 0;
7874 pExternalFenceProperties->externalFenceFeatures = 0;
7875 }
7876 }
7877
7878 VkResult
7879 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7880 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7881 const VkAllocationCallbacks* pAllocator,
7882 VkDebugReportCallbackEXT* pCallback)
7883 {
7884 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7885 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7886 pCreateInfo, pAllocator, &instance->alloc,
7887 pCallback);
7888 }
7889
7890 void
7891 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7892 VkDebugReportCallbackEXT _callback,
7893 const VkAllocationCallbacks* pAllocator)
7894 {
7895 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7896 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7897 _callback, pAllocator, &instance->alloc);
7898 }
7899
7900 void
7901 radv_DebugReportMessageEXT(VkInstance _instance,
7902 VkDebugReportFlagsEXT flags,
7903 VkDebugReportObjectTypeEXT objectType,
7904 uint64_t object,
7905 size_t location,
7906 int32_t messageCode,
7907 const char* pLayerPrefix,
7908 const char* pMessage)
7909 {
7910 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7911 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7912 object, location, messageCode, pLayerPrefix, pMessage);
7913 }
7914
7915 void
7916 radv_GetDeviceGroupPeerMemoryFeatures(
7917 VkDevice device,
7918 uint32_t heapIndex,
7919 uint32_t localDeviceIndex,
7920 uint32_t remoteDeviceIndex,
7921 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7922 {
7923 assert(localDeviceIndex == remoteDeviceIndex);
7924
7925 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7926 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7927 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7928 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7929 }
7930
7931 static const VkTimeDomainEXT radv_time_domains[] = {
7932 VK_TIME_DOMAIN_DEVICE_EXT,
7933 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7934 #ifdef CLOCK_MONOTONIC_RAW
7935 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7936 #endif
7937 };
7938
7939 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7940 VkPhysicalDevice physicalDevice,
7941 uint32_t *pTimeDomainCount,
7942 VkTimeDomainEXT *pTimeDomains)
7943 {
7944 int d;
7945 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7946
7947 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7948 vk_outarray_append(&out, i) {
7949 *i = radv_time_domains[d];
7950 }
7951 }
7952
7953 return vk_outarray_status(&out);
7954 }
7955
7956 static uint64_t
7957 radv_clock_gettime(clockid_t clock_id)
7958 {
7959 struct timespec current;
7960 int ret;
7961
7962 ret = clock_gettime(clock_id, &current);
7963 #ifdef CLOCK_MONOTONIC_RAW
7964 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7965 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7966 #endif
7967 if (ret < 0)
7968 return 0;
7969
7970 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7971 }
7972
7973 VkResult radv_GetCalibratedTimestampsEXT(
7974 VkDevice _device,
7975 uint32_t timestampCount,
7976 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7977 uint64_t *pTimestamps,
7978 uint64_t *pMaxDeviation)
7979 {
7980 RADV_FROM_HANDLE(radv_device, device, _device);
7981 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7982 int d;
7983 uint64_t begin, end;
7984 uint64_t max_clock_period = 0;
7985
7986 #ifdef CLOCK_MONOTONIC_RAW
7987 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7988 #else
7989 begin = radv_clock_gettime(CLOCK_MONOTONIC);
7990 #endif
7991
7992 for (d = 0; d < timestampCount; d++) {
7993 switch (pTimestampInfos[d].timeDomain) {
7994 case VK_TIME_DOMAIN_DEVICE_EXT:
7995 pTimestamps[d] = device->ws->query_value(device->ws,
7996 RADEON_TIMESTAMP);
7997 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7998 max_clock_period = MAX2(max_clock_period, device_period);
7999 break;
8000 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
8001 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
8002 max_clock_period = MAX2(max_clock_period, 1);
8003 break;
8004
8005 #ifdef CLOCK_MONOTONIC_RAW
8006 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
8007 pTimestamps[d] = begin;
8008 break;
8009 #endif
8010 default:
8011 pTimestamps[d] = 0;
8012 break;
8013 }
8014 }
8015
8016 #ifdef CLOCK_MONOTONIC_RAW
8017 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
8018 #else
8019 end = radv_clock_gettime(CLOCK_MONOTONIC);
8020 #endif
8021
8022 /*
8023 * The maximum deviation is the sum of the interval over which we
8024 * perform the sampling and the maximum period of any sampled
8025 * clock. That's because the maximum skew between any two sampled
8026 * clock edges is when the sampled clock with the largest period is
8027 * sampled at the end of that period but right at the beginning of the
8028 * sampling interval and some other clock is sampled right at the
8029 * begining of its sampling period and right at the end of the
8030 * sampling interval. Let's assume the GPU has the longest clock
8031 * period and that the application is sampling GPU and monotonic:
8032 *
8033 * s e
8034 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
8035 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8036 *
8037 * g
8038 * 0 1 2 3
8039 * GPU -----_____-----_____-----_____-----_____
8040 *
8041 * m
8042 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
8043 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8044 *
8045 * Interval <----------------->
8046 * Deviation <-------------------------->
8047 *
8048 * s = read(raw) 2
8049 * g = read(GPU) 1
8050 * m = read(monotonic) 2
8051 * e = read(raw) b
8052 *
8053 * We round the sample interval up by one tick to cover sampling error
8054 * in the interval clock
8055 */
8056
8057 uint64_t sample_interval = end - begin + 1;
8058
8059 *pMaxDeviation = sample_interval + max_clock_period;
8060
8061 return VK_SUCCESS;
8062 }
8063
8064 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
8065 VkPhysicalDevice physicalDevice,
8066 VkSampleCountFlagBits samples,
8067 VkMultisamplePropertiesEXT* pMultisampleProperties)
8068 {
8069 if (samples & (VK_SAMPLE_COUNT_2_BIT |
8070 VK_SAMPLE_COUNT_4_BIT |
8071 VK_SAMPLE_COUNT_8_BIT)) {
8072 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
8073 } else {
8074 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
8075 }
8076 }
8077
8078 VkResult radv_CreatePrivateDataSlotEXT(
8079 VkDevice _device,
8080 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
8081 const VkAllocationCallbacks* pAllocator,
8082 VkPrivateDataSlotEXT* pPrivateDataSlot)
8083 {
8084 RADV_FROM_HANDLE(radv_device, device, _device);
8085 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
8086 pPrivateDataSlot);
8087 }
8088
8089 void radv_DestroyPrivateDataSlotEXT(
8090 VkDevice _device,
8091 VkPrivateDataSlotEXT privateDataSlot,
8092 const VkAllocationCallbacks* pAllocator)
8093 {
8094 RADV_FROM_HANDLE(radv_device, device, _device);
8095 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
8096 }
8097
8098 VkResult radv_SetPrivateDataEXT(
8099 VkDevice _device,
8100 VkObjectType objectType,
8101 uint64_t objectHandle,
8102 VkPrivateDataSlotEXT privateDataSlot,
8103 uint64_t data)
8104 {
8105 RADV_FROM_HANDLE(radv_device, device, _device);
8106 return vk_object_base_set_private_data(&device->vk, objectType,
8107 objectHandle, privateDataSlot,
8108 data);
8109 }
8110
8111 void radv_GetPrivateDataEXT(
8112 VkDevice _device,
8113 VkObjectType objectType,
8114 uint64_t objectHandle,
8115 VkPrivateDataSlotEXT privateDataSlot,
8116 uint64_t* pData)
8117 {
8118 RADV_FROM_HANDLE(radv_device, device, _device);
8119 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
8120 privateDataSlot, pData);
8121 }