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ac/surface: add radeon_surf::has_stencil for convenience
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_cs.h"
35 #include "util/disk_cache.h"
36 #include "util/strtod.h"
37 #include "vk_util.h"
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static const VkExtensionProperties instance_extensions[] = {
79 {
80 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
81 .specVersion = 25,
82 },
83 #ifdef VK_USE_PLATFORM_XCB_KHR
84 {
85 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
86 .specVersion = 6,
87 },
88 #endif
89 #ifdef VK_USE_PLATFORM_XLIB_KHR
90 {
91 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
92 .specVersion = 6,
93 },
94 #endif
95 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
96 {
97 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
98 .specVersion = 6,
99 },
100 #endif
101 {
102 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 {
106 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
107 .specVersion = 1,
108 },
109 {
110 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
111 .specVersion = 1,
112 },
113 };
114
115 static const VkExtensionProperties common_device_extensions[] = {
116 {
117 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
134 .specVersion = 1,
135 },
136 {
137 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
138 .specVersion = 68,
139 },
140 {
141 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 {
161 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
162 .specVersion = 1,
163 },
164 {
165 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
166 .specVersion = 1,
167 },
168 {
169 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
170 .specVersion = 1,
171 },
172 };
173 static const VkExtensionProperties ext_sema_device_extensions[] = {
174 {
175 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
176 .specVersion = 1,
177 },
178 {
179 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
180 .specVersion = 1,
181 },
182 {
183 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
184 .specVersion = 1,
185 },
186 };
187
188 static VkResult
189 radv_extensions_register(struct radv_instance *instance,
190 struct radv_extensions *extensions,
191 const VkExtensionProperties *new_ext,
192 uint32_t num_ext)
193 {
194 size_t new_size;
195 VkExtensionProperties *new_ptr;
196
197 assert(new_ext && num_ext > 0);
198
199 if (!new_ext)
200 return VK_ERROR_INITIALIZATION_FAILED;
201
202 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
203 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
204 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
205
206 /* Old array continues to be valid, update nothing */
207 if (!new_ptr)
208 return VK_ERROR_OUT_OF_HOST_MEMORY;
209
210 memcpy(&new_ptr[extensions->num_ext], new_ext,
211 num_ext * sizeof(VkExtensionProperties));
212 extensions->ext_array = new_ptr;
213 extensions->num_ext += num_ext;
214
215 return VK_SUCCESS;
216 }
217
218 static void
219 radv_extensions_finish(struct radv_instance *instance,
220 struct radv_extensions *extensions)
221 {
222 assert(extensions);
223
224 if (!extensions)
225 radv_loge("Attemted to free invalid extension struct\n");
226
227 if (extensions->ext_array)
228 vk_free(&instance->alloc, extensions->ext_array);
229 }
230
231 static bool
232 is_extension_enabled(const VkExtensionProperties *extensions,
233 size_t num_ext,
234 const char *name)
235 {
236 assert(extensions && name);
237
238 for (uint32_t i = 0; i < num_ext; i++) {
239 if (strcmp(name, extensions[i].extensionName) == 0)
240 return true;
241 }
242
243 return false;
244 }
245
246 static const char *
247 get_chip_name(enum radeon_family family)
248 {
249 switch (family) {
250 case CHIP_TAHITI: return "AMD RADV TAHITI";
251 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
252 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
253 case CHIP_OLAND: return "AMD RADV OLAND";
254 case CHIP_HAINAN: return "AMD RADV HAINAN";
255 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
256 case CHIP_KAVERI: return "AMD RADV KAVERI";
257 case CHIP_KABINI: return "AMD RADV KABINI";
258 case CHIP_HAWAII: return "AMD RADV HAWAII";
259 case CHIP_MULLINS: return "AMD RADV MULLINS";
260 case CHIP_TONGA: return "AMD RADV TONGA";
261 case CHIP_ICELAND: return "AMD RADV ICELAND";
262 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
263 case CHIP_FIJI: return "AMD RADV FIJI";
264 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
265 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
266 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
267 case CHIP_STONEY: return "AMD RADV STONEY";
268 case CHIP_VEGA10: return "AMD RADV VEGA";
269 case CHIP_RAVEN: return "AMD RADV RAVEN";
270 default: return "AMD RADV unknown";
271 }
272 }
273
274 static VkResult
275 radv_physical_device_init(struct radv_physical_device *device,
276 struct radv_instance *instance,
277 drmDevicePtr drm_device)
278 {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 VkResult result;
281 drmVersionPtr version;
282 int fd;
283
284 fd = open(path, O_RDWR | O_CLOEXEC);
285 if (fd < 0)
286 return VK_ERROR_INCOMPATIBLE_DRIVER;
287
288 version = drmGetVersion(fd);
289 if (!version) {
290 close(fd);
291 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
292 "failed to get version %s: %m", path);
293 }
294
295 if (strcmp(version->name, "amdgpu")) {
296 drmFreeVersion(version);
297 close(fd);
298 return VK_ERROR_INCOMPATIBLE_DRIVER;
299 }
300 drmFreeVersion(version);
301
302 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
303 device->instance = instance;
304 assert(strlen(path) < ARRAY_SIZE(device->path));
305 strncpy(device->path, path, ARRAY_SIZE(device->path));
306
307 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
308 instance->perftest_flags);
309 if (!device->ws) {
310 result = VK_ERROR_INCOMPATIBLE_DRIVER;
311 goto fail;
312 }
313
314 device->local_fd = fd;
315 device->ws->query_info(device->ws, &device->rad_info);
316 result = radv_init_wsi(device);
317 if (result != VK_SUCCESS) {
318 device->ws->destroy(device->ws);
319 goto fail;
320 }
321
322 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
323 radv_finish_wsi(device);
324 device->ws->destroy(device->ws);
325 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
326 "cannot generate UUID");
327 goto fail;
328 }
329
330 result = radv_extensions_register(instance,
331 &device->extensions,
332 common_device_extensions,
333 ARRAY_SIZE(common_device_extensions));
334 if (result != VK_SUCCESS)
335 goto fail;
336
337 if (device->rad_info.has_syncobj) {
338 result = radv_extensions_register(instance,
339 &device->extensions,
340 ext_sema_device_extensions,
341 ARRAY_SIZE(ext_sema_device_extensions));
342 if (result != VK_SUCCESS)
343 goto fail;
344 }
345
346 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
347 device->name = get_chip_name(device->rad_info.family);
348
349 radv_get_driver_uuid(&device->device_uuid);
350 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
351
352 if (device->rad_info.family == CHIP_STONEY ||
353 device->rad_info.chip_class >= GFX9) {
354 device->has_rbplus = true;
355 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
356 }
357
358 return VK_SUCCESS;
359
360 fail:
361 close(fd);
362 return result;
363 }
364
365 static void
366 radv_physical_device_finish(struct radv_physical_device *device)
367 {
368 radv_extensions_finish(device->instance, &device->extensions);
369 radv_finish_wsi(device);
370 device->ws->destroy(device->ws);
371 close(device->local_fd);
372 }
373
374 static void *
375 default_alloc_func(void *pUserData, size_t size, size_t align,
376 VkSystemAllocationScope allocationScope)
377 {
378 return malloc(size);
379 }
380
381 static void *
382 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
383 size_t align, VkSystemAllocationScope allocationScope)
384 {
385 return realloc(pOriginal, size);
386 }
387
388 static void
389 default_free_func(void *pUserData, void *pMemory)
390 {
391 free(pMemory);
392 }
393
394 static const VkAllocationCallbacks default_alloc = {
395 .pUserData = NULL,
396 .pfnAllocation = default_alloc_func,
397 .pfnReallocation = default_realloc_func,
398 .pfnFree = default_free_func,
399 };
400
401 static const struct debug_control radv_debug_options[] = {
402 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
403 {"nodcc", RADV_DEBUG_NO_DCC},
404 {"shaders", RADV_DEBUG_DUMP_SHADERS},
405 {"nocache", RADV_DEBUG_NO_CACHE},
406 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
407 {"nohiz", RADV_DEBUG_NO_HIZ},
408 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
409 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
410 {"allbos", RADV_DEBUG_ALL_BOS},
411 {"noibs", RADV_DEBUG_NO_IBS},
412 {"spirv", RADV_DEBUG_DUMP_SPIRV},
413 {NULL, 0}
414 };
415
416 static const struct debug_control radv_perftest_options[] = {
417 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
418 {"sisched", RADV_PERFTEST_SISCHED},
419 {NULL, 0}
420 };
421
422 VkResult radv_CreateInstance(
423 const VkInstanceCreateInfo* pCreateInfo,
424 const VkAllocationCallbacks* pAllocator,
425 VkInstance* pInstance)
426 {
427 struct radv_instance *instance;
428
429 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
430
431 uint32_t client_version;
432 if (pCreateInfo->pApplicationInfo &&
433 pCreateInfo->pApplicationInfo->apiVersion != 0) {
434 client_version = pCreateInfo->pApplicationInfo->apiVersion;
435 } else {
436 client_version = VK_MAKE_VERSION(1, 0, 0);
437 }
438
439 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
440 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
441 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
442 "Client requested version %d.%d.%d",
443 VK_VERSION_MAJOR(client_version),
444 VK_VERSION_MINOR(client_version),
445 VK_VERSION_PATCH(client_version));
446 }
447
448 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
449 if (!is_extension_enabled(instance_extensions,
450 ARRAY_SIZE(instance_extensions),
451 pCreateInfo->ppEnabledExtensionNames[i]))
452 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
453 }
454
455 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
456 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
457 if (!instance)
458 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
459
460 memset(instance, 0, sizeof(*instance));
461
462 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
463
464 if (pAllocator)
465 instance->alloc = *pAllocator;
466 else
467 instance->alloc = default_alloc;
468
469 instance->apiVersion = client_version;
470 instance->physicalDeviceCount = -1;
471
472 _mesa_locale_init();
473
474 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
475
476 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
477 radv_debug_options);
478
479 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
480 radv_perftest_options);
481
482 *pInstance = radv_instance_to_handle(instance);
483
484 return VK_SUCCESS;
485 }
486
487 void radv_DestroyInstance(
488 VkInstance _instance,
489 const VkAllocationCallbacks* pAllocator)
490 {
491 RADV_FROM_HANDLE(radv_instance, instance, _instance);
492
493 if (!instance)
494 return;
495
496 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
497 radv_physical_device_finish(instance->physicalDevices + i);
498 }
499
500 VG(VALGRIND_DESTROY_MEMPOOL(instance));
501
502 _mesa_locale_fini();
503
504 vk_free(&instance->alloc, instance);
505 }
506
507 static VkResult
508 radv_enumerate_devices(struct radv_instance *instance)
509 {
510 /* TODO: Check for more devices ? */
511 drmDevicePtr devices[8];
512 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
513 int max_devices;
514
515 instance->physicalDeviceCount = 0;
516
517 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
518 if (max_devices < 1)
519 return VK_ERROR_INCOMPATIBLE_DRIVER;
520
521 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
522 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
523 devices[i]->bustype == DRM_BUS_PCI &&
524 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
525
526 result = radv_physical_device_init(instance->physicalDevices +
527 instance->physicalDeviceCount,
528 instance,
529 devices[i]);
530 if (result == VK_SUCCESS)
531 ++instance->physicalDeviceCount;
532 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
533 break;
534 }
535 }
536 drmFreeDevices(devices, max_devices);
537
538 return result;
539 }
540
541 VkResult radv_EnumeratePhysicalDevices(
542 VkInstance _instance,
543 uint32_t* pPhysicalDeviceCount,
544 VkPhysicalDevice* pPhysicalDevices)
545 {
546 RADV_FROM_HANDLE(radv_instance, instance, _instance);
547 VkResult result;
548
549 if (instance->physicalDeviceCount < 0) {
550 result = radv_enumerate_devices(instance);
551 if (result != VK_SUCCESS &&
552 result != VK_ERROR_INCOMPATIBLE_DRIVER)
553 return result;
554 }
555
556 if (!pPhysicalDevices) {
557 *pPhysicalDeviceCount = instance->physicalDeviceCount;
558 } else {
559 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
560 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
561 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
562 }
563
564 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
565 : VK_SUCCESS;
566 }
567
568 void radv_GetPhysicalDeviceFeatures(
569 VkPhysicalDevice physicalDevice,
570 VkPhysicalDeviceFeatures* pFeatures)
571 {
572 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
573 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
574 memset(pFeatures, 0, sizeof(*pFeatures));
575
576 *pFeatures = (VkPhysicalDeviceFeatures) {
577 .robustBufferAccess = true,
578 .fullDrawIndexUint32 = true,
579 .imageCubeArray = true,
580 .independentBlend = true,
581 .geometryShader = !is_gfx9,
582 .tessellationShader = !is_gfx9,
583 .sampleRateShading = true,
584 .dualSrcBlend = true,
585 .logicOp = true,
586 .multiDrawIndirect = true,
587 .drawIndirectFirstInstance = true,
588 .depthClamp = true,
589 .depthBiasClamp = true,
590 .fillModeNonSolid = true,
591 .depthBounds = true,
592 .wideLines = true,
593 .largePoints = true,
594 .alphaToOne = true,
595 .multiViewport = true,
596 .samplerAnisotropy = true,
597 .textureCompressionETC2 = false,
598 .textureCompressionASTC_LDR = false,
599 .textureCompressionBC = true,
600 .occlusionQueryPrecise = true,
601 .pipelineStatisticsQuery = true,
602 .vertexPipelineStoresAndAtomics = true,
603 .fragmentStoresAndAtomics = true,
604 .shaderTessellationAndGeometryPointSize = true,
605 .shaderImageGatherExtended = true,
606 .shaderStorageImageExtendedFormats = true,
607 .shaderStorageImageMultisample = false,
608 .shaderUniformBufferArrayDynamicIndexing = true,
609 .shaderSampledImageArrayDynamicIndexing = true,
610 .shaderStorageBufferArrayDynamicIndexing = true,
611 .shaderStorageImageArrayDynamicIndexing = true,
612 .shaderStorageImageReadWithoutFormat = true,
613 .shaderStorageImageWriteWithoutFormat = true,
614 .shaderClipDistance = true,
615 .shaderCullDistance = true,
616 .shaderFloat64 = true,
617 .shaderInt64 = true,
618 .shaderInt16 = false,
619 .sparseBinding = true,
620 .variableMultisampleRate = true,
621 .inheritedQueries = true,
622 };
623 }
624
625 void radv_GetPhysicalDeviceFeatures2KHR(
626 VkPhysicalDevice physicalDevice,
627 VkPhysicalDeviceFeatures2KHR *pFeatures)
628 {
629 vk_foreach_struct(ext, pFeatures->pNext) {
630 switch (ext->sType) {
631 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
632 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
633 features->variablePointersStorageBuffer = true;
634 features->variablePointers = false;
635 break;
636 }
637 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
638 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
639 features->multiview = true;
640 features->multiviewGeometryShader = true;
641 features->multiviewTessellationShader = true;
642 break;
643 }
644 default:
645 break;
646 }
647 }
648 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
649 }
650
651 void radv_GetPhysicalDeviceProperties(
652 VkPhysicalDevice physicalDevice,
653 VkPhysicalDeviceProperties* pProperties)
654 {
655 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
656 VkSampleCountFlags sample_counts = 0xf;
657
658 /* make sure that the entire descriptor set is addressable with a signed
659 * 32-bit int. So the sum of all limits scaled by descriptor size has to
660 * be at most 2 GiB. the combined image & samples object count as one of
661 * both. This limit is for the pipeline layout, not for the set layout, but
662 * there is no set limit, so we just set a pipeline limit. I don't think
663 * any app is going to hit this soon. */
664 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
665 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
666 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
667 32 /* sampler, largest when combined with image */ +
668 64 /* sampled image */ +
669 64 /* storage image */);
670
671 VkPhysicalDeviceLimits limits = {
672 .maxImageDimension1D = (1 << 14),
673 .maxImageDimension2D = (1 << 14),
674 .maxImageDimension3D = (1 << 11),
675 .maxImageDimensionCube = (1 << 14),
676 .maxImageArrayLayers = (1 << 11),
677 .maxTexelBufferElements = 128 * 1024 * 1024,
678 .maxUniformBufferRange = UINT32_MAX,
679 .maxStorageBufferRange = UINT32_MAX,
680 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
681 .maxMemoryAllocationCount = UINT32_MAX,
682 .maxSamplerAllocationCount = 64 * 1024,
683 .bufferImageGranularity = 64, /* A cache line */
684 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
685 .maxBoundDescriptorSets = MAX_SETS,
686 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
687 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
688 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
689 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
690 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
691 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
692 .maxPerStageResources = max_descriptor_set_size,
693 .maxDescriptorSetSamplers = max_descriptor_set_size,
694 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
695 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
696 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
697 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
698 .maxDescriptorSetSampledImages = max_descriptor_set_size,
699 .maxDescriptorSetStorageImages = max_descriptor_set_size,
700 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
701 .maxVertexInputAttributes = 32,
702 .maxVertexInputBindings = 32,
703 .maxVertexInputAttributeOffset = 2047,
704 .maxVertexInputBindingStride = 2048,
705 .maxVertexOutputComponents = 128,
706 .maxTessellationGenerationLevel = 64,
707 .maxTessellationPatchSize = 32,
708 .maxTessellationControlPerVertexInputComponents = 128,
709 .maxTessellationControlPerVertexOutputComponents = 128,
710 .maxTessellationControlPerPatchOutputComponents = 120,
711 .maxTessellationControlTotalOutputComponents = 4096,
712 .maxTessellationEvaluationInputComponents = 128,
713 .maxTessellationEvaluationOutputComponents = 128,
714 .maxGeometryShaderInvocations = 127,
715 .maxGeometryInputComponents = 64,
716 .maxGeometryOutputComponents = 128,
717 .maxGeometryOutputVertices = 256,
718 .maxGeometryTotalOutputComponents = 1024,
719 .maxFragmentInputComponents = 128,
720 .maxFragmentOutputAttachments = 8,
721 .maxFragmentDualSrcAttachments = 1,
722 .maxFragmentCombinedOutputResources = 8,
723 .maxComputeSharedMemorySize = 32768,
724 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
725 .maxComputeWorkGroupInvocations = 2048,
726 .maxComputeWorkGroupSize = {
727 2048,
728 2048,
729 2048
730 },
731 .subPixelPrecisionBits = 4 /* FIXME */,
732 .subTexelPrecisionBits = 4 /* FIXME */,
733 .mipmapPrecisionBits = 4 /* FIXME */,
734 .maxDrawIndexedIndexValue = UINT32_MAX,
735 .maxDrawIndirectCount = UINT32_MAX,
736 .maxSamplerLodBias = 16,
737 .maxSamplerAnisotropy = 16,
738 .maxViewports = MAX_VIEWPORTS,
739 .maxViewportDimensions = { (1 << 14), (1 << 14) },
740 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
741 .viewportSubPixelBits = 13, /* We take a float? */
742 .minMemoryMapAlignment = 4096, /* A page */
743 .minTexelBufferOffsetAlignment = 1,
744 .minUniformBufferOffsetAlignment = 4,
745 .minStorageBufferOffsetAlignment = 4,
746 .minTexelOffset = -32,
747 .maxTexelOffset = 31,
748 .minTexelGatherOffset = -32,
749 .maxTexelGatherOffset = 31,
750 .minInterpolationOffset = -2,
751 .maxInterpolationOffset = 2,
752 .subPixelInterpolationOffsetBits = 8,
753 .maxFramebufferWidth = (1 << 14),
754 .maxFramebufferHeight = (1 << 14),
755 .maxFramebufferLayers = (1 << 10),
756 .framebufferColorSampleCounts = sample_counts,
757 .framebufferDepthSampleCounts = sample_counts,
758 .framebufferStencilSampleCounts = sample_counts,
759 .framebufferNoAttachmentsSampleCounts = sample_counts,
760 .maxColorAttachments = MAX_RTS,
761 .sampledImageColorSampleCounts = sample_counts,
762 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
763 .sampledImageDepthSampleCounts = sample_counts,
764 .sampledImageStencilSampleCounts = sample_counts,
765 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
766 .maxSampleMaskWords = 1,
767 .timestampComputeAndGraphics = true,
768 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
769 .maxClipDistances = 8,
770 .maxCullDistances = 8,
771 .maxCombinedClipAndCullDistances = 8,
772 .discreteQueuePriorities = 1,
773 .pointSizeRange = { 0.125, 255.875 },
774 .lineWidthRange = { 0.0, 7.9921875 },
775 .pointSizeGranularity = (1.0 / 8.0),
776 .lineWidthGranularity = (1.0 / 128.0),
777 .strictLines = false, /* FINISHME */
778 .standardSampleLocations = true,
779 .optimalBufferCopyOffsetAlignment = 128,
780 .optimalBufferCopyRowPitchAlignment = 128,
781 .nonCoherentAtomSize = 64,
782 };
783
784 *pProperties = (VkPhysicalDeviceProperties) {
785 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
786 .driverVersion = vk_get_driver_version(),
787 .vendorID = 0x1002,
788 .deviceID = pdevice->rad_info.pci_id,
789 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
790 .limits = limits,
791 .sparseProperties = {0},
792 };
793
794 strcpy(pProperties->deviceName, pdevice->name);
795 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
796 }
797
798 void radv_GetPhysicalDeviceProperties2KHR(
799 VkPhysicalDevice physicalDevice,
800 VkPhysicalDeviceProperties2KHR *pProperties)
801 {
802 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
803 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
804
805 vk_foreach_struct(ext, pProperties->pNext) {
806 switch (ext->sType) {
807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
808 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
809 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
810 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
814 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
815 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
816 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
817 properties->deviceLUIDValid = false;
818 break;
819 }
820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
821 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
822 properties->maxMultiviewViewCount = MAX_VIEWS;
823 properties->maxMultiviewInstanceIndex = INT_MAX;
824 break;
825 }
826 default:
827 break;
828 }
829 }
830 }
831
832 static void radv_get_physical_device_queue_family_properties(
833 struct radv_physical_device* pdevice,
834 uint32_t* pCount,
835 VkQueueFamilyProperties** pQueueFamilyProperties)
836 {
837 int num_queue_families = 1;
838 int idx;
839 if (pdevice->rad_info.num_compute_rings > 0 &&
840 pdevice->rad_info.chip_class >= CIK &&
841 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
842 num_queue_families++;
843
844 if (pQueueFamilyProperties == NULL) {
845 *pCount = num_queue_families;
846 return;
847 }
848
849 if (!*pCount)
850 return;
851
852 idx = 0;
853 if (*pCount >= 1) {
854 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
855 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
856 VK_QUEUE_COMPUTE_BIT |
857 VK_QUEUE_TRANSFER_BIT |
858 VK_QUEUE_SPARSE_BINDING_BIT,
859 .queueCount = 1,
860 .timestampValidBits = 64,
861 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
862 };
863 idx++;
864 }
865
866 if (pdevice->rad_info.num_compute_rings > 0 &&
867 pdevice->rad_info.chip_class >= CIK &&
868 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
869 if (*pCount > idx) {
870 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
871 .queueFlags = VK_QUEUE_COMPUTE_BIT |
872 VK_QUEUE_TRANSFER_BIT |
873 VK_QUEUE_SPARSE_BINDING_BIT,
874 .queueCount = pdevice->rad_info.num_compute_rings,
875 .timestampValidBits = 64,
876 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
877 };
878 idx++;
879 }
880 }
881 *pCount = idx;
882 }
883
884 void radv_GetPhysicalDeviceQueueFamilyProperties(
885 VkPhysicalDevice physicalDevice,
886 uint32_t* pCount,
887 VkQueueFamilyProperties* pQueueFamilyProperties)
888 {
889 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
890 if (!pQueueFamilyProperties) {
891 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
892 return;
893 }
894 VkQueueFamilyProperties *properties[] = {
895 pQueueFamilyProperties + 0,
896 pQueueFamilyProperties + 1,
897 pQueueFamilyProperties + 2,
898 };
899 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
900 assert(*pCount <= 3);
901 }
902
903 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
904 VkPhysicalDevice physicalDevice,
905 uint32_t* pCount,
906 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
907 {
908 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
909 if (!pQueueFamilyProperties) {
910 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
911 return;
912 }
913 VkQueueFamilyProperties *properties[] = {
914 &pQueueFamilyProperties[0].queueFamilyProperties,
915 &pQueueFamilyProperties[1].queueFamilyProperties,
916 &pQueueFamilyProperties[2].queueFamilyProperties,
917 };
918 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
919 assert(*pCount <= 3);
920 }
921
922 void radv_GetPhysicalDeviceMemoryProperties(
923 VkPhysicalDevice physicalDevice,
924 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
925 {
926 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
927
928 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
929
930 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
931 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
932 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
933 .heapIndex = RADV_MEM_HEAP_VRAM,
934 };
935 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
936 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
937 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
938 .heapIndex = RADV_MEM_HEAP_GTT,
939 };
940 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
941 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
942 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
943 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
944 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
945 };
946 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
947 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
948 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
949 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
950 .heapIndex = RADV_MEM_HEAP_GTT,
951 };
952
953 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
954 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
955 physical_device->rad_info.vram_vis_size);
956
957 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
958 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
959 .size = physical_device->rad_info.vram_size -
960 visible_vram_size,
961 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
962 };
963 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
964 .size = visible_vram_size,
965 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
966 };
967 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
968 .size = physical_device->rad_info.gart_size,
969 .flags = 0,
970 };
971 }
972
973 void radv_GetPhysicalDeviceMemoryProperties2KHR(
974 VkPhysicalDevice physicalDevice,
975 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
976 {
977 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
978 &pMemoryProperties->memoryProperties);
979 }
980
981 static int
982 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
983 int queue_family_index, int idx)
984 {
985 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
986 queue->device = device;
987 queue->queue_family_index = queue_family_index;
988 queue->queue_idx = idx;
989
990 queue->hw_ctx = device->ws->ctx_create(device->ws);
991 if (!queue->hw_ctx)
992 return VK_ERROR_OUT_OF_HOST_MEMORY;
993
994 return VK_SUCCESS;
995 }
996
997 static void
998 radv_queue_finish(struct radv_queue *queue)
999 {
1000 if (queue->hw_ctx)
1001 queue->device->ws->ctx_destroy(queue->hw_ctx);
1002
1003 if (queue->initial_full_flush_preamble_cs)
1004 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1005 if (queue->initial_preamble_cs)
1006 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1007 if (queue->continue_preamble_cs)
1008 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1009 if (queue->descriptor_bo)
1010 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1011 if (queue->scratch_bo)
1012 queue->device->ws->buffer_destroy(queue->scratch_bo);
1013 if (queue->esgs_ring_bo)
1014 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1015 if (queue->gsvs_ring_bo)
1016 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1017 if (queue->tess_factor_ring_bo)
1018 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1019 if (queue->tess_offchip_ring_bo)
1020 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1021 if (queue->compute_scratch_bo)
1022 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1023 }
1024
1025 static void
1026 radv_device_init_gs_info(struct radv_device *device)
1027 {
1028 switch (device->physical_device->rad_info.family) {
1029 case CHIP_OLAND:
1030 case CHIP_HAINAN:
1031 case CHIP_KAVERI:
1032 case CHIP_KABINI:
1033 case CHIP_MULLINS:
1034 case CHIP_ICELAND:
1035 case CHIP_CARRIZO:
1036 case CHIP_STONEY:
1037 device->gs_table_depth = 16;
1038 return;
1039 case CHIP_TAHITI:
1040 case CHIP_PITCAIRN:
1041 case CHIP_VERDE:
1042 case CHIP_BONAIRE:
1043 case CHIP_HAWAII:
1044 case CHIP_TONGA:
1045 case CHIP_FIJI:
1046 case CHIP_POLARIS10:
1047 case CHIP_POLARIS11:
1048 case CHIP_POLARIS12:
1049 case CHIP_VEGA10:
1050 case CHIP_RAVEN:
1051 device->gs_table_depth = 32;
1052 return;
1053 default:
1054 unreachable("unknown GPU");
1055 }
1056 }
1057
1058 VkResult radv_CreateDevice(
1059 VkPhysicalDevice physicalDevice,
1060 const VkDeviceCreateInfo* pCreateInfo,
1061 const VkAllocationCallbacks* pAllocator,
1062 VkDevice* pDevice)
1063 {
1064 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1065 VkResult result;
1066 struct radv_device *device;
1067
1068 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1069 if (!is_extension_enabled(physical_device->extensions.ext_array,
1070 physical_device->extensions.num_ext,
1071 pCreateInfo->ppEnabledExtensionNames[i]))
1072 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1073 }
1074
1075 /* Check enabled features */
1076 if (pCreateInfo->pEnabledFeatures) {
1077 VkPhysicalDeviceFeatures supported_features;
1078 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1079 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1080 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1081 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1082 for (uint32_t i = 0; i < num_features; i++) {
1083 if (enabled_feature[i] && !supported_feature[i])
1084 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1085 }
1086 }
1087
1088 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1089 sizeof(*device), 8,
1090 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1091 if (!device)
1092 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1093
1094 memset(device, 0, sizeof(*device));
1095
1096 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1097 device->instance = physical_device->instance;
1098 device->physical_device = physical_device;
1099
1100 device->debug_flags = device->instance->debug_flags;
1101
1102 device->ws = physical_device->ws;
1103 if (pAllocator)
1104 device->alloc = *pAllocator;
1105 else
1106 device->alloc = physical_device->instance->alloc;
1107
1108 mtx_init(&device->shader_slab_mutex, mtx_plain);
1109 list_inithead(&device->shader_slabs);
1110
1111 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1112 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1113 uint32_t qfi = queue_create->queueFamilyIndex;
1114
1115 device->queues[qfi] = vk_alloc(&device->alloc,
1116 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1117 if (!device->queues[qfi]) {
1118 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1119 goto fail;
1120 }
1121
1122 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1123
1124 device->queue_count[qfi] = queue_create->queueCount;
1125
1126 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1127 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1128 if (result != VK_SUCCESS)
1129 goto fail;
1130 }
1131 }
1132
1133 #if HAVE_LLVM < 0x0400
1134 device->llvm_supports_spill = false;
1135 #else
1136 device->llvm_supports_spill = true;
1137 #endif
1138
1139 /* The maximum number of scratch waves. Scratch space isn't divided
1140 * evenly between CUs. The number is only a function of the number of CUs.
1141 * We can decrease the constant to decrease the scratch buffer size.
1142 *
1143 * sctx->scratch_waves must be >= the maximum posible size of
1144 * 1 threadgroup, so that the hw doesn't hang from being unable
1145 * to start any.
1146 *
1147 * The recommended value is 4 per CU at most. Higher numbers don't
1148 * bring much benefit, but they still occupy chip resources (think
1149 * async compute). I've seen ~2% performance difference between 4 and 32.
1150 */
1151 uint32_t max_threads_per_block = 2048;
1152 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1153 max_threads_per_block / 64);
1154
1155 radv_device_init_gs_info(device);
1156
1157 device->tess_offchip_block_dw_size =
1158 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1159 device->has_distributed_tess =
1160 device->physical_device->rad_info.chip_class >= VI &&
1161 device->physical_device->rad_info.max_se >= 2;
1162
1163 result = radv_device_init_meta(device);
1164 if (result != VK_SUCCESS)
1165 goto fail;
1166
1167 radv_device_init_msaa(device);
1168
1169 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1170 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1171 switch (family) {
1172 case RADV_QUEUE_GENERAL:
1173 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1174 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1175 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1176 break;
1177 case RADV_QUEUE_COMPUTE:
1178 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1179 radeon_emit(device->empty_cs[family], 0);
1180 break;
1181 }
1182 device->ws->cs_finalize(device->empty_cs[family]);
1183 }
1184
1185 if (getenv("RADV_TRACE_FILE")) {
1186 if (!radv_init_trace(device))
1187 goto fail;
1188 }
1189
1190 if (device->physical_device->rad_info.chip_class >= CIK)
1191 cik_create_gfx_config(device);
1192
1193 VkPipelineCacheCreateInfo ci;
1194 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1195 ci.pNext = NULL;
1196 ci.flags = 0;
1197 ci.pInitialData = NULL;
1198 ci.initialDataSize = 0;
1199 VkPipelineCache pc;
1200 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1201 &ci, NULL, &pc);
1202 if (result != VK_SUCCESS)
1203 goto fail;
1204
1205 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1206
1207 *pDevice = radv_device_to_handle(device);
1208 return VK_SUCCESS;
1209
1210 fail:
1211 if (device->trace_bo)
1212 device->ws->buffer_destroy(device->trace_bo);
1213
1214 if (device->gfx_init)
1215 device->ws->buffer_destroy(device->gfx_init);
1216
1217 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1218 for (unsigned q = 0; q < device->queue_count[i]; q++)
1219 radv_queue_finish(&device->queues[i][q]);
1220 if (device->queue_count[i])
1221 vk_free(&device->alloc, device->queues[i]);
1222 }
1223
1224 vk_free(&device->alloc, device);
1225 return result;
1226 }
1227
1228 void radv_DestroyDevice(
1229 VkDevice _device,
1230 const VkAllocationCallbacks* pAllocator)
1231 {
1232 RADV_FROM_HANDLE(radv_device, device, _device);
1233
1234 if (!device)
1235 return;
1236
1237 if (device->trace_bo)
1238 device->ws->buffer_destroy(device->trace_bo);
1239
1240 if (device->gfx_init)
1241 device->ws->buffer_destroy(device->gfx_init);
1242
1243 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1244 for (unsigned q = 0; q < device->queue_count[i]; q++)
1245 radv_queue_finish(&device->queues[i][q]);
1246 if (device->queue_count[i])
1247 vk_free(&device->alloc, device->queues[i]);
1248 if (device->empty_cs[i])
1249 device->ws->cs_destroy(device->empty_cs[i]);
1250 }
1251 radv_device_finish_meta(device);
1252
1253 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1254 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1255
1256 radv_destroy_shader_slabs(device);
1257
1258 vk_free(&device->alloc, device);
1259 }
1260
1261 VkResult radv_EnumerateInstanceExtensionProperties(
1262 const char* pLayerName,
1263 uint32_t* pPropertyCount,
1264 VkExtensionProperties* pProperties)
1265 {
1266 if (pProperties == NULL) {
1267 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1268 return VK_SUCCESS;
1269 }
1270
1271 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1272 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1273
1274 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1275 return VK_INCOMPLETE;
1276
1277 return VK_SUCCESS;
1278 }
1279
1280 VkResult radv_EnumerateDeviceExtensionProperties(
1281 VkPhysicalDevice physicalDevice,
1282 const char* pLayerName,
1283 uint32_t* pPropertyCount,
1284 VkExtensionProperties* pProperties)
1285 {
1286 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1287
1288 if (pProperties == NULL) {
1289 *pPropertyCount = pdevice->extensions.num_ext;
1290 return VK_SUCCESS;
1291 }
1292
1293 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1294 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1295
1296 if (*pPropertyCount < pdevice->extensions.num_ext)
1297 return VK_INCOMPLETE;
1298
1299 return VK_SUCCESS;
1300 }
1301
1302 VkResult radv_EnumerateInstanceLayerProperties(
1303 uint32_t* pPropertyCount,
1304 VkLayerProperties* pProperties)
1305 {
1306 if (pProperties == NULL) {
1307 *pPropertyCount = 0;
1308 return VK_SUCCESS;
1309 }
1310
1311 /* None supported at this time */
1312 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1313 }
1314
1315 VkResult radv_EnumerateDeviceLayerProperties(
1316 VkPhysicalDevice physicalDevice,
1317 uint32_t* pPropertyCount,
1318 VkLayerProperties* pProperties)
1319 {
1320 if (pProperties == NULL) {
1321 *pPropertyCount = 0;
1322 return VK_SUCCESS;
1323 }
1324
1325 /* None supported at this time */
1326 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1327 }
1328
1329 void radv_GetDeviceQueue(
1330 VkDevice _device,
1331 uint32_t queueFamilyIndex,
1332 uint32_t queueIndex,
1333 VkQueue* pQueue)
1334 {
1335 RADV_FROM_HANDLE(radv_device, device, _device);
1336
1337 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1338 }
1339
1340 static void
1341 fill_geom_tess_rings(struct radv_queue *queue,
1342 uint32_t *map,
1343 bool add_sample_positions,
1344 uint32_t esgs_ring_size,
1345 struct radeon_winsys_bo *esgs_ring_bo,
1346 uint32_t gsvs_ring_size,
1347 struct radeon_winsys_bo *gsvs_ring_bo,
1348 uint32_t tess_factor_ring_size,
1349 struct radeon_winsys_bo *tess_factor_ring_bo,
1350 uint32_t tess_offchip_ring_size,
1351 struct radeon_winsys_bo *tess_offchip_ring_bo)
1352 {
1353 uint64_t esgs_va = 0, gsvs_va = 0;
1354 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1355 uint32_t *desc = &map[4];
1356
1357 if (esgs_ring_bo)
1358 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1359 if (gsvs_ring_bo)
1360 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1361 if (tess_factor_ring_bo)
1362 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1363 if (tess_offchip_ring_bo)
1364 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1365
1366 /* stride 0, num records - size, add tid, swizzle, elsize4,
1367 index stride 64 */
1368 desc[0] = esgs_va;
1369 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1370 S_008F04_STRIDE(0) |
1371 S_008F04_SWIZZLE_ENABLE(true);
1372 desc[2] = esgs_ring_size;
1373 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1374 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1375 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1376 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1377 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1378 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1379 S_008F0C_ELEMENT_SIZE(1) |
1380 S_008F0C_INDEX_STRIDE(3) |
1381 S_008F0C_ADD_TID_ENABLE(true);
1382
1383 desc += 4;
1384 /* GS entry for ES->GS ring */
1385 /* stride 0, num records - size, elsize0,
1386 index stride 0 */
1387 desc[0] = esgs_va;
1388 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1389 S_008F04_STRIDE(0) |
1390 S_008F04_SWIZZLE_ENABLE(false);
1391 desc[2] = esgs_ring_size;
1392 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1393 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1394 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1395 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1396 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1397 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1398 S_008F0C_ELEMENT_SIZE(0) |
1399 S_008F0C_INDEX_STRIDE(0) |
1400 S_008F0C_ADD_TID_ENABLE(false);
1401
1402 desc += 4;
1403 /* VS entry for GS->VS ring */
1404 /* stride 0, num records - size, elsize0,
1405 index stride 0 */
1406 desc[0] = gsvs_va;
1407 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1408 S_008F04_STRIDE(0) |
1409 S_008F04_SWIZZLE_ENABLE(false);
1410 desc[2] = gsvs_ring_size;
1411 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1412 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1413 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1414 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1415 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1416 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1417 S_008F0C_ELEMENT_SIZE(0) |
1418 S_008F0C_INDEX_STRIDE(0) |
1419 S_008F0C_ADD_TID_ENABLE(false);
1420 desc += 4;
1421
1422 /* stride gsvs_itemsize, num records 64
1423 elsize 4, index stride 16 */
1424 /* shader will patch stride and desc[2] */
1425 desc[0] = gsvs_va;
1426 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1427 S_008F04_STRIDE(0) |
1428 S_008F04_SWIZZLE_ENABLE(true);
1429 desc[2] = 0;
1430 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1431 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1432 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1433 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1434 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1435 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1436 S_008F0C_ELEMENT_SIZE(1) |
1437 S_008F0C_INDEX_STRIDE(1) |
1438 S_008F0C_ADD_TID_ENABLE(true);
1439 desc += 4;
1440
1441 desc[0] = tess_factor_va;
1442 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1443 S_008F04_STRIDE(0) |
1444 S_008F04_SWIZZLE_ENABLE(false);
1445 desc[2] = tess_factor_ring_size;
1446 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1447 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1448 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1449 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1450 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1451 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1452 S_008F0C_ELEMENT_SIZE(0) |
1453 S_008F0C_INDEX_STRIDE(0) |
1454 S_008F0C_ADD_TID_ENABLE(false);
1455 desc += 4;
1456
1457 desc[0] = tess_offchip_va;
1458 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1459 S_008F04_STRIDE(0) |
1460 S_008F04_SWIZZLE_ENABLE(false);
1461 desc[2] = tess_offchip_ring_size;
1462 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1463 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1464 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1465 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1466 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1467 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1468 S_008F0C_ELEMENT_SIZE(0) |
1469 S_008F0C_INDEX_STRIDE(0) |
1470 S_008F0C_ADD_TID_ENABLE(false);
1471 desc += 4;
1472
1473 /* add sample positions after all rings */
1474 memcpy(desc, queue->device->sample_locations_1x, 8);
1475 desc += 2;
1476 memcpy(desc, queue->device->sample_locations_2x, 16);
1477 desc += 4;
1478 memcpy(desc, queue->device->sample_locations_4x, 32);
1479 desc += 8;
1480 memcpy(desc, queue->device->sample_locations_8x, 64);
1481 desc += 16;
1482 memcpy(desc, queue->device->sample_locations_16x, 128);
1483 }
1484
1485 static unsigned
1486 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1487 {
1488 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1489 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1490 device->physical_device->rad_info.family != CHIP_STONEY;
1491 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1492 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1493 device->physical_device->rad_info.max_se;
1494 unsigned offchip_granularity;
1495 unsigned hs_offchip_param;
1496 switch (device->tess_offchip_block_dw_size) {
1497 default:
1498 assert(0);
1499 /* fall through */
1500 case 8192:
1501 offchip_granularity = V_03093C_X_8K_DWORDS;
1502 break;
1503 case 4096:
1504 offchip_granularity = V_03093C_X_4K_DWORDS;
1505 break;
1506 }
1507
1508 switch (device->physical_device->rad_info.chip_class) {
1509 case SI:
1510 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1511 break;
1512 case CIK:
1513 case VI:
1514 case GFX9:
1515 default:
1516 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1517 break;
1518 }
1519
1520 *max_offchip_buffers_p = max_offchip_buffers;
1521 if (device->physical_device->rad_info.chip_class >= CIK) {
1522 if (device->physical_device->rad_info.chip_class >= VI)
1523 --max_offchip_buffers;
1524 hs_offchip_param =
1525 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1526 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1527 } else {
1528 hs_offchip_param =
1529 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1530 }
1531 return hs_offchip_param;
1532 }
1533
1534 static VkResult
1535 radv_get_preamble_cs(struct radv_queue *queue,
1536 uint32_t scratch_size,
1537 uint32_t compute_scratch_size,
1538 uint32_t esgs_ring_size,
1539 uint32_t gsvs_ring_size,
1540 bool needs_tess_rings,
1541 bool needs_sample_positions,
1542 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1543 struct radeon_winsys_cs **initial_preamble_cs,
1544 struct radeon_winsys_cs **continue_preamble_cs)
1545 {
1546 struct radeon_winsys_bo *scratch_bo = NULL;
1547 struct radeon_winsys_bo *descriptor_bo = NULL;
1548 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1549 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1550 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1551 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1552 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1553 struct radeon_winsys_cs *dest_cs[3] = {0};
1554 bool add_tess_rings = false, add_sample_positions = false;
1555 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1556 unsigned max_offchip_buffers;
1557 unsigned hs_offchip_param = 0;
1558 if (!queue->has_tess_rings) {
1559 if (needs_tess_rings)
1560 add_tess_rings = true;
1561 }
1562 if (!queue->has_sample_positions) {
1563 if (needs_sample_positions)
1564 add_sample_positions = true;
1565 }
1566 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1567 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1568 &max_offchip_buffers);
1569 tess_offchip_ring_size = max_offchip_buffers *
1570 queue->device->tess_offchip_block_dw_size * 4;
1571
1572 if (scratch_size <= queue->scratch_size &&
1573 compute_scratch_size <= queue->compute_scratch_size &&
1574 esgs_ring_size <= queue->esgs_ring_size &&
1575 gsvs_ring_size <= queue->gsvs_ring_size &&
1576 !add_tess_rings && !add_sample_positions &&
1577 queue->initial_preamble_cs) {
1578 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1579 *initial_preamble_cs = queue->initial_preamble_cs;
1580 *continue_preamble_cs = queue->continue_preamble_cs;
1581 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1582 *continue_preamble_cs = NULL;
1583 return VK_SUCCESS;
1584 }
1585
1586 if (scratch_size > queue->scratch_size) {
1587 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1588 scratch_size,
1589 4096,
1590 RADEON_DOMAIN_VRAM,
1591 RADEON_FLAG_NO_CPU_ACCESS);
1592 if (!scratch_bo)
1593 goto fail;
1594 } else
1595 scratch_bo = queue->scratch_bo;
1596
1597 if (compute_scratch_size > queue->compute_scratch_size) {
1598 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1599 compute_scratch_size,
1600 4096,
1601 RADEON_DOMAIN_VRAM,
1602 RADEON_FLAG_NO_CPU_ACCESS);
1603 if (!compute_scratch_bo)
1604 goto fail;
1605
1606 } else
1607 compute_scratch_bo = queue->compute_scratch_bo;
1608
1609 if (esgs_ring_size > queue->esgs_ring_size) {
1610 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1611 esgs_ring_size,
1612 4096,
1613 RADEON_DOMAIN_VRAM,
1614 RADEON_FLAG_NO_CPU_ACCESS);
1615 if (!esgs_ring_bo)
1616 goto fail;
1617 } else {
1618 esgs_ring_bo = queue->esgs_ring_bo;
1619 esgs_ring_size = queue->esgs_ring_size;
1620 }
1621
1622 if (gsvs_ring_size > queue->gsvs_ring_size) {
1623 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1624 gsvs_ring_size,
1625 4096,
1626 RADEON_DOMAIN_VRAM,
1627 RADEON_FLAG_NO_CPU_ACCESS);
1628 if (!gsvs_ring_bo)
1629 goto fail;
1630 } else {
1631 gsvs_ring_bo = queue->gsvs_ring_bo;
1632 gsvs_ring_size = queue->gsvs_ring_size;
1633 }
1634
1635 if (add_tess_rings) {
1636 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1637 tess_factor_ring_size,
1638 256,
1639 RADEON_DOMAIN_VRAM,
1640 RADEON_FLAG_NO_CPU_ACCESS);
1641 if (!tess_factor_ring_bo)
1642 goto fail;
1643 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1644 tess_offchip_ring_size,
1645 256,
1646 RADEON_DOMAIN_VRAM,
1647 RADEON_FLAG_NO_CPU_ACCESS);
1648 if (!tess_offchip_ring_bo)
1649 goto fail;
1650 } else {
1651 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1652 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1653 }
1654
1655 if (scratch_bo != queue->scratch_bo ||
1656 esgs_ring_bo != queue->esgs_ring_bo ||
1657 gsvs_ring_bo != queue->gsvs_ring_bo ||
1658 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1659 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1660 uint32_t size = 0;
1661 if (gsvs_ring_bo || esgs_ring_bo ||
1662 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1663 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1664 if (add_sample_positions)
1665 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1666 }
1667 else if (scratch_bo)
1668 size = 8; /* 2 dword */
1669
1670 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1671 size,
1672 4096,
1673 RADEON_DOMAIN_VRAM,
1674 RADEON_FLAG_CPU_ACCESS);
1675 if (!descriptor_bo)
1676 goto fail;
1677 } else
1678 descriptor_bo = queue->descriptor_bo;
1679
1680 for(int i = 0; i < 3; ++i) {
1681 struct radeon_winsys_cs *cs = NULL;
1682 cs = queue->device->ws->cs_create(queue->device->ws,
1683 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1684 if (!cs)
1685 goto fail;
1686
1687 dest_cs[i] = cs;
1688
1689 if (scratch_bo)
1690 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1691
1692 if (esgs_ring_bo)
1693 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1694
1695 if (gsvs_ring_bo)
1696 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1697
1698 if (tess_factor_ring_bo)
1699 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1700
1701 if (tess_offchip_ring_bo)
1702 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1703
1704 if (descriptor_bo)
1705 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1706
1707 if (descriptor_bo != queue->descriptor_bo) {
1708 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1709
1710 if (scratch_bo) {
1711 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1712 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1713 S_008F04_SWIZZLE_ENABLE(1);
1714 map[0] = scratch_va;
1715 map[1] = rsrc1;
1716 }
1717
1718 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1719 add_sample_positions)
1720 fill_geom_tess_rings(queue, map, add_sample_positions,
1721 esgs_ring_size, esgs_ring_bo,
1722 gsvs_ring_size, gsvs_ring_bo,
1723 tess_factor_ring_size, tess_factor_ring_bo,
1724 tess_offchip_ring_size, tess_offchip_ring_bo);
1725
1726 queue->device->ws->buffer_unmap(descriptor_bo);
1727 }
1728
1729 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1730 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1731 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1732 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1733 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1734 }
1735
1736 if (esgs_ring_bo || gsvs_ring_bo) {
1737 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1738 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1739 radeon_emit(cs, esgs_ring_size >> 8);
1740 radeon_emit(cs, gsvs_ring_size >> 8);
1741 } else {
1742 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1743 radeon_emit(cs, esgs_ring_size >> 8);
1744 radeon_emit(cs, gsvs_ring_size >> 8);
1745 }
1746 }
1747
1748 if (tess_factor_ring_bo) {
1749 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1750 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1751 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1752 S_030938_SIZE(tess_factor_ring_size / 4));
1753 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1754 tf_va >> 8);
1755 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1756 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1757 tf_va >> 40);
1758 }
1759 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1760 } else {
1761 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1762 S_008988_SIZE(tess_factor_ring_size / 4));
1763 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1764 tf_va >> 8);
1765 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1766 hs_offchip_param);
1767 }
1768 }
1769
1770 if (descriptor_bo) {
1771 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1772 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1773 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1774 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1775 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1776 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1777
1778 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1779
1780 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1781 radeon_set_sh_reg_seq(cs, regs[i], 2);
1782 radeon_emit(cs, va);
1783 radeon_emit(cs, va >> 32);
1784 }
1785 }
1786
1787 if (compute_scratch_bo) {
1788 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1789 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1790 S_008F04_SWIZZLE_ENABLE(1);
1791
1792 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1793
1794 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1795 radeon_emit(cs, scratch_va);
1796 radeon_emit(cs, rsrc1);
1797 }
1798
1799 if (i == 0) {
1800 si_cs_emit_cache_flush(cs,
1801 false,
1802 queue->device->physical_device->rad_info.chip_class,
1803 NULL, 0,
1804 queue->queue_family_index == RING_COMPUTE &&
1805 queue->device->physical_device->rad_info.chip_class >= CIK,
1806 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1807 RADV_CMD_FLAG_INV_ICACHE |
1808 RADV_CMD_FLAG_INV_SMEM_L1 |
1809 RADV_CMD_FLAG_INV_VMEM_L1 |
1810 RADV_CMD_FLAG_INV_GLOBAL_L2);
1811 } else if (i == 1) {
1812 si_cs_emit_cache_flush(cs,
1813 false,
1814 queue->device->physical_device->rad_info.chip_class,
1815 NULL, 0,
1816 queue->queue_family_index == RING_COMPUTE &&
1817 queue->device->physical_device->rad_info.chip_class >= CIK,
1818 RADV_CMD_FLAG_INV_ICACHE |
1819 RADV_CMD_FLAG_INV_SMEM_L1 |
1820 RADV_CMD_FLAG_INV_VMEM_L1 |
1821 RADV_CMD_FLAG_INV_GLOBAL_L2);
1822 }
1823
1824 if (!queue->device->ws->cs_finalize(cs))
1825 goto fail;
1826 }
1827
1828 if (queue->initial_full_flush_preamble_cs)
1829 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1830
1831 if (queue->initial_preamble_cs)
1832 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1833
1834 if (queue->continue_preamble_cs)
1835 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1836
1837 queue->initial_full_flush_preamble_cs = dest_cs[0];
1838 queue->initial_preamble_cs = dest_cs[1];
1839 queue->continue_preamble_cs = dest_cs[2];
1840
1841 if (scratch_bo != queue->scratch_bo) {
1842 if (queue->scratch_bo)
1843 queue->device->ws->buffer_destroy(queue->scratch_bo);
1844 queue->scratch_bo = scratch_bo;
1845 queue->scratch_size = scratch_size;
1846 }
1847
1848 if (compute_scratch_bo != queue->compute_scratch_bo) {
1849 if (queue->compute_scratch_bo)
1850 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1851 queue->compute_scratch_bo = compute_scratch_bo;
1852 queue->compute_scratch_size = compute_scratch_size;
1853 }
1854
1855 if (esgs_ring_bo != queue->esgs_ring_bo) {
1856 if (queue->esgs_ring_bo)
1857 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1858 queue->esgs_ring_bo = esgs_ring_bo;
1859 queue->esgs_ring_size = esgs_ring_size;
1860 }
1861
1862 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1863 if (queue->gsvs_ring_bo)
1864 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1865 queue->gsvs_ring_bo = gsvs_ring_bo;
1866 queue->gsvs_ring_size = gsvs_ring_size;
1867 }
1868
1869 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1870 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1871 }
1872
1873 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1874 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1875 queue->has_tess_rings = true;
1876 }
1877
1878 if (descriptor_bo != queue->descriptor_bo) {
1879 if (queue->descriptor_bo)
1880 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1881
1882 queue->descriptor_bo = descriptor_bo;
1883 }
1884
1885 if (add_sample_positions)
1886 queue->has_sample_positions = true;
1887
1888 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1889 *initial_preamble_cs = queue->initial_preamble_cs;
1890 *continue_preamble_cs = queue->continue_preamble_cs;
1891 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1892 *continue_preamble_cs = NULL;
1893 return VK_SUCCESS;
1894 fail:
1895 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1896 if (dest_cs[i])
1897 queue->device->ws->cs_destroy(dest_cs[i]);
1898 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1899 queue->device->ws->buffer_destroy(descriptor_bo);
1900 if (scratch_bo && scratch_bo != queue->scratch_bo)
1901 queue->device->ws->buffer_destroy(scratch_bo);
1902 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1903 queue->device->ws->buffer_destroy(compute_scratch_bo);
1904 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1905 queue->device->ws->buffer_destroy(esgs_ring_bo);
1906 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1907 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1908 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1909 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1910 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1911 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1912 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1913 }
1914
1915 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1916 int num_sems,
1917 const VkSemaphore *sems,
1918 bool reset_temp)
1919 {
1920 int syncobj_idx = 0, sem_idx = 0;
1921
1922 if (num_sems == 0)
1923 return VK_SUCCESS;
1924 for (uint32_t i = 0; i < num_sems; i++) {
1925 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1926
1927 if (sem->temp_syncobj || sem->syncobj)
1928 counts->syncobj_count++;
1929 else
1930 counts->sem_count++;
1931 }
1932
1933 if (counts->syncobj_count) {
1934 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1935 if (!counts->syncobj)
1936 return VK_ERROR_OUT_OF_HOST_MEMORY;
1937 }
1938
1939 if (counts->sem_count) {
1940 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1941 if (!counts->sem) {
1942 free(counts->syncobj);
1943 return VK_ERROR_OUT_OF_HOST_MEMORY;
1944 }
1945 }
1946
1947 for (uint32_t i = 0; i < num_sems; i++) {
1948 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1949
1950 if (sem->temp_syncobj) {
1951 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1952 if (reset_temp) {
1953 /* after we wait on a temp import - drop it */
1954 sem->temp_syncobj = 0;
1955 }
1956 }
1957 else if (sem->syncobj)
1958 counts->syncobj[syncobj_idx++] = sem->syncobj;
1959 else {
1960 assert(sem->sem);
1961 counts->sem[sem_idx++] = sem->sem;
1962 }
1963 }
1964
1965 return VK_SUCCESS;
1966 }
1967
1968 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1969 {
1970 free(sem_info->wait.syncobj);
1971 free(sem_info->wait.sem);
1972 free(sem_info->signal.syncobj);
1973 free(sem_info->signal.sem);
1974 }
1975
1976 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1977 int num_wait_sems,
1978 const VkSemaphore *wait_sems,
1979 int num_signal_sems,
1980 const VkSemaphore *signal_sems)
1981 {
1982 VkResult ret;
1983 memset(sem_info, 0, sizeof(*sem_info));
1984
1985 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1986 if (ret)
1987 return ret;
1988 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1989 if (ret)
1990 radv_free_sem_info(sem_info);
1991
1992 /* caller can override these */
1993 sem_info->cs_emit_wait = true;
1994 sem_info->cs_emit_signal = true;
1995 return ret;
1996 }
1997
1998 VkResult radv_QueueSubmit(
1999 VkQueue _queue,
2000 uint32_t submitCount,
2001 const VkSubmitInfo* pSubmits,
2002 VkFence _fence)
2003 {
2004 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2005 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2006 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2007 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2008 int ret;
2009 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2010 uint32_t scratch_size = 0;
2011 uint32_t compute_scratch_size = 0;
2012 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2013 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2014 VkResult result;
2015 bool fence_emitted = false;
2016 bool tess_rings_needed = false;
2017 bool sample_positions_needed = false;
2018
2019 /* Do this first so failing to allocate scratch buffers can't result in
2020 * partially executed submissions. */
2021 for (uint32_t i = 0; i < submitCount; i++) {
2022 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2024 pSubmits[i].pCommandBuffers[j]);
2025
2026 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2027 compute_scratch_size = MAX2(compute_scratch_size,
2028 cmd_buffer->compute_scratch_size_needed);
2029 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2030 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2031 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2032 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2033 }
2034 }
2035
2036 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2037 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2038 sample_positions_needed, &initial_flush_preamble_cs,
2039 &initial_preamble_cs, &continue_preamble_cs);
2040 if (result != VK_SUCCESS)
2041 return result;
2042
2043 for (uint32_t i = 0; i < submitCount; i++) {
2044 struct radeon_winsys_cs **cs_array;
2045 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2046 bool can_patch = true;
2047 uint32_t advance;
2048 struct radv_winsys_sem_info sem_info;
2049
2050 result = radv_alloc_sem_info(&sem_info,
2051 pSubmits[i].waitSemaphoreCount,
2052 pSubmits[i].pWaitSemaphores,
2053 pSubmits[i].signalSemaphoreCount,
2054 pSubmits[i].pSignalSemaphores);
2055 if (result != VK_SUCCESS)
2056 return result;
2057
2058 if (!pSubmits[i].commandBufferCount) {
2059 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2060 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2061 &queue->device->empty_cs[queue->queue_family_index],
2062 1, NULL, NULL,
2063 &sem_info,
2064 false, base_fence);
2065 if (ret) {
2066 radv_loge("failed to submit CS %d\n", i);
2067 abort();
2068 }
2069 fence_emitted = true;
2070 }
2071 radv_free_sem_info(&sem_info);
2072 continue;
2073 }
2074
2075 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2076 (pSubmits[i].commandBufferCount));
2077
2078 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2080 pSubmits[i].pCommandBuffers[j]);
2081 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2082
2083 cs_array[j] = cmd_buffer->cs;
2084 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2085 can_patch = false;
2086 }
2087
2088 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2089 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2090 advance = MIN2(max_cs_submission,
2091 pSubmits[i].commandBufferCount - j);
2092
2093 if (queue->device->trace_bo)
2094 *queue->device->trace_id_ptr = 0;
2095
2096 sem_info.cs_emit_wait = j == 0;
2097 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2098
2099 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2100 advance, initial_preamble, continue_preamble_cs,
2101 &sem_info,
2102 can_patch, base_fence);
2103
2104 if (ret) {
2105 radv_loge("failed to submit CS %d\n", i);
2106 abort();
2107 }
2108 fence_emitted = true;
2109 if (queue->device->trace_bo) {
2110 radv_check_gpu_hangs(queue, cs_array[j]);
2111 }
2112 }
2113
2114 radv_free_sem_info(&sem_info);
2115 free(cs_array);
2116 }
2117
2118 if (fence) {
2119 if (!fence_emitted) {
2120 struct radv_winsys_sem_info sem_info = {0};
2121 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2122 &queue->device->empty_cs[queue->queue_family_index],
2123 1, NULL, NULL, &sem_info,
2124 false, base_fence);
2125 }
2126 fence->submitted = true;
2127 }
2128
2129 return VK_SUCCESS;
2130 }
2131
2132 VkResult radv_QueueWaitIdle(
2133 VkQueue _queue)
2134 {
2135 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2136
2137 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2138 radv_queue_family_to_ring(queue->queue_family_index),
2139 queue->queue_idx);
2140 return VK_SUCCESS;
2141 }
2142
2143 VkResult radv_DeviceWaitIdle(
2144 VkDevice _device)
2145 {
2146 RADV_FROM_HANDLE(radv_device, device, _device);
2147
2148 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2149 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2150 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2151 }
2152 }
2153 return VK_SUCCESS;
2154 }
2155
2156 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2157 VkInstance instance,
2158 const char* pName)
2159 {
2160 return radv_lookup_entrypoint(pName);
2161 }
2162
2163 /* The loader wants us to expose a second GetInstanceProcAddr function
2164 * to work around certain LD_PRELOAD issues seen in apps.
2165 */
2166 PUBLIC
2167 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2168 VkInstance instance,
2169 const char* pName);
2170
2171 PUBLIC
2172 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2173 VkInstance instance,
2174 const char* pName)
2175 {
2176 return radv_GetInstanceProcAddr(instance, pName);
2177 }
2178
2179 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2180 VkDevice device,
2181 const char* pName)
2182 {
2183 return radv_lookup_entrypoint(pName);
2184 }
2185
2186 bool radv_get_memory_fd(struct radv_device *device,
2187 struct radv_device_memory *memory,
2188 int *pFD)
2189 {
2190 struct radeon_bo_metadata metadata;
2191
2192 if (memory->image) {
2193 radv_init_metadata(device, memory->image, &metadata);
2194 device->ws->buffer_set_metadata(memory->bo, &metadata);
2195 }
2196
2197 return device->ws->buffer_get_fd(device->ws, memory->bo,
2198 pFD);
2199 }
2200
2201 VkResult radv_AllocateMemory(
2202 VkDevice _device,
2203 const VkMemoryAllocateInfo* pAllocateInfo,
2204 const VkAllocationCallbacks* pAllocator,
2205 VkDeviceMemory* pMem)
2206 {
2207 RADV_FROM_HANDLE(radv_device, device, _device);
2208 struct radv_device_memory *mem;
2209 VkResult result;
2210 enum radeon_bo_domain domain;
2211 uint32_t flags = 0;
2212
2213 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2214
2215 if (pAllocateInfo->allocationSize == 0) {
2216 /* Apparently, this is allowed */
2217 *pMem = VK_NULL_HANDLE;
2218 return VK_SUCCESS;
2219 }
2220
2221 const VkImportMemoryFdInfoKHR *import_info =
2222 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2223 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2224 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2225
2226 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2228 if (mem == NULL)
2229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2230
2231 if (dedicate_info) {
2232 mem->image = radv_image_from_handle(dedicate_info->image);
2233 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2234 } else {
2235 mem->image = NULL;
2236 mem->buffer = NULL;
2237 }
2238
2239 if (import_info) {
2240 assert(import_info->handleType ==
2241 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2242 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2243 NULL, NULL);
2244 if (!mem->bo) {
2245 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2246 goto fail;
2247 } else {
2248 close(import_info->fd);
2249 goto out_success;
2250 }
2251 }
2252
2253 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2254 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2255 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2256 domain = RADEON_DOMAIN_GTT;
2257 else
2258 domain = RADEON_DOMAIN_VRAM;
2259
2260 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2261 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2262 else
2263 flags |= RADEON_FLAG_CPU_ACCESS;
2264
2265 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2266 flags |= RADEON_FLAG_GTT_WC;
2267
2268 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2269 domain, flags);
2270
2271 if (!mem->bo) {
2272 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2273 goto fail;
2274 }
2275 mem->type_index = pAllocateInfo->memoryTypeIndex;
2276 out_success:
2277 *pMem = radv_device_memory_to_handle(mem);
2278
2279 return VK_SUCCESS;
2280
2281 fail:
2282 vk_free2(&device->alloc, pAllocator, mem);
2283
2284 return result;
2285 }
2286
2287 void radv_FreeMemory(
2288 VkDevice _device,
2289 VkDeviceMemory _mem,
2290 const VkAllocationCallbacks* pAllocator)
2291 {
2292 RADV_FROM_HANDLE(radv_device, device, _device);
2293 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2294
2295 if (mem == NULL)
2296 return;
2297
2298 device->ws->buffer_destroy(mem->bo);
2299 mem->bo = NULL;
2300
2301 vk_free2(&device->alloc, pAllocator, mem);
2302 }
2303
2304 VkResult radv_MapMemory(
2305 VkDevice _device,
2306 VkDeviceMemory _memory,
2307 VkDeviceSize offset,
2308 VkDeviceSize size,
2309 VkMemoryMapFlags flags,
2310 void** ppData)
2311 {
2312 RADV_FROM_HANDLE(radv_device, device, _device);
2313 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2314
2315 if (mem == NULL) {
2316 *ppData = NULL;
2317 return VK_SUCCESS;
2318 }
2319
2320 *ppData = device->ws->buffer_map(mem->bo);
2321 if (*ppData) {
2322 *ppData += offset;
2323 return VK_SUCCESS;
2324 }
2325
2326 return VK_ERROR_MEMORY_MAP_FAILED;
2327 }
2328
2329 void radv_UnmapMemory(
2330 VkDevice _device,
2331 VkDeviceMemory _memory)
2332 {
2333 RADV_FROM_HANDLE(radv_device, device, _device);
2334 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2335
2336 if (mem == NULL)
2337 return;
2338
2339 device->ws->buffer_unmap(mem->bo);
2340 }
2341
2342 VkResult radv_FlushMappedMemoryRanges(
2343 VkDevice _device,
2344 uint32_t memoryRangeCount,
2345 const VkMappedMemoryRange* pMemoryRanges)
2346 {
2347 return VK_SUCCESS;
2348 }
2349
2350 VkResult radv_InvalidateMappedMemoryRanges(
2351 VkDevice _device,
2352 uint32_t memoryRangeCount,
2353 const VkMappedMemoryRange* pMemoryRanges)
2354 {
2355 return VK_SUCCESS;
2356 }
2357
2358 void radv_GetBufferMemoryRequirements(
2359 VkDevice device,
2360 VkBuffer _buffer,
2361 VkMemoryRequirements* pMemoryRequirements)
2362 {
2363 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2364
2365 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2366
2367 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2368 pMemoryRequirements->alignment = 4096;
2369 else
2370 pMemoryRequirements->alignment = 16;
2371
2372 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2373 }
2374
2375 void radv_GetBufferMemoryRequirements2KHR(
2376 VkDevice device,
2377 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2378 VkMemoryRequirements2KHR* pMemoryRequirements)
2379 {
2380 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2381 &pMemoryRequirements->memoryRequirements);
2382
2383 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2384 switch (ext->sType) {
2385 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2386 VkMemoryDedicatedRequirementsKHR *req =
2387 (VkMemoryDedicatedRequirementsKHR *) ext;
2388 req->requiresDedicatedAllocation = false;
2389 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2390 break;
2391 }
2392 default:
2393 break;
2394 }
2395 }
2396 }
2397
2398 void radv_GetImageMemoryRequirements(
2399 VkDevice device,
2400 VkImage _image,
2401 VkMemoryRequirements* pMemoryRequirements)
2402 {
2403 RADV_FROM_HANDLE(radv_image, image, _image);
2404
2405 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2406
2407 pMemoryRequirements->size = image->size;
2408 pMemoryRequirements->alignment = image->alignment;
2409 }
2410
2411 void radv_GetImageMemoryRequirements2KHR(
2412 VkDevice device,
2413 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2414 VkMemoryRequirements2KHR* pMemoryRequirements)
2415 {
2416 radv_GetImageMemoryRequirements(device, pInfo->image,
2417 &pMemoryRequirements->memoryRequirements);
2418
2419 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2420
2421 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2422 switch (ext->sType) {
2423 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2424 VkMemoryDedicatedRequirementsKHR *req =
2425 (VkMemoryDedicatedRequirementsKHR *) ext;
2426 req->requiresDedicatedAllocation = image->shareable;
2427 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2428 break;
2429 }
2430 default:
2431 break;
2432 }
2433 }
2434 }
2435
2436 void radv_GetImageSparseMemoryRequirements(
2437 VkDevice device,
2438 VkImage image,
2439 uint32_t* pSparseMemoryRequirementCount,
2440 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2441 {
2442 stub();
2443 }
2444
2445 void radv_GetImageSparseMemoryRequirements2KHR(
2446 VkDevice device,
2447 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2448 uint32_t* pSparseMemoryRequirementCount,
2449 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2450 {
2451 stub();
2452 }
2453
2454 void radv_GetDeviceMemoryCommitment(
2455 VkDevice device,
2456 VkDeviceMemory memory,
2457 VkDeviceSize* pCommittedMemoryInBytes)
2458 {
2459 *pCommittedMemoryInBytes = 0;
2460 }
2461
2462 VkResult radv_BindBufferMemory(
2463 VkDevice device,
2464 VkBuffer _buffer,
2465 VkDeviceMemory _memory,
2466 VkDeviceSize memoryOffset)
2467 {
2468 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2469 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2470
2471 if (mem) {
2472 buffer->bo = mem->bo;
2473 buffer->offset = memoryOffset;
2474 } else {
2475 buffer->bo = NULL;
2476 buffer->offset = 0;
2477 }
2478
2479 return VK_SUCCESS;
2480 }
2481
2482 VkResult radv_BindImageMemory(
2483 VkDevice device,
2484 VkImage _image,
2485 VkDeviceMemory _memory,
2486 VkDeviceSize memoryOffset)
2487 {
2488 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2489 RADV_FROM_HANDLE(radv_image, image, _image);
2490
2491 if (mem) {
2492 image->bo = mem->bo;
2493 image->offset = memoryOffset;
2494 } else {
2495 image->bo = NULL;
2496 image->offset = 0;
2497 }
2498
2499 return VK_SUCCESS;
2500 }
2501
2502
2503 static void
2504 radv_sparse_buffer_bind_memory(struct radv_device *device,
2505 const VkSparseBufferMemoryBindInfo *bind)
2506 {
2507 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2508
2509 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2510 struct radv_device_memory *mem = NULL;
2511
2512 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2513 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2514
2515 device->ws->buffer_virtual_bind(buffer->bo,
2516 bind->pBinds[i].resourceOffset,
2517 bind->pBinds[i].size,
2518 mem ? mem->bo : NULL,
2519 bind->pBinds[i].memoryOffset);
2520 }
2521 }
2522
2523 static void
2524 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2525 const VkSparseImageOpaqueMemoryBindInfo *bind)
2526 {
2527 RADV_FROM_HANDLE(radv_image, image, bind->image);
2528
2529 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2530 struct radv_device_memory *mem = NULL;
2531
2532 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2533 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2534
2535 device->ws->buffer_virtual_bind(image->bo,
2536 bind->pBinds[i].resourceOffset,
2537 bind->pBinds[i].size,
2538 mem ? mem->bo : NULL,
2539 bind->pBinds[i].memoryOffset);
2540 }
2541 }
2542
2543 VkResult radv_QueueBindSparse(
2544 VkQueue _queue,
2545 uint32_t bindInfoCount,
2546 const VkBindSparseInfo* pBindInfo,
2547 VkFence _fence)
2548 {
2549 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2550 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2551 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2552 bool fence_emitted = false;
2553
2554 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2555 struct radv_winsys_sem_info sem_info;
2556 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2557 radv_sparse_buffer_bind_memory(queue->device,
2558 pBindInfo[i].pBufferBinds + j);
2559 }
2560
2561 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2562 radv_sparse_image_opaque_bind_memory(queue->device,
2563 pBindInfo[i].pImageOpaqueBinds + j);
2564 }
2565
2566 VkResult result;
2567 result = radv_alloc_sem_info(&sem_info,
2568 pBindInfo[i].waitSemaphoreCount,
2569 pBindInfo[i].pWaitSemaphores,
2570 pBindInfo[i].signalSemaphoreCount,
2571 pBindInfo[i].pSignalSemaphores);
2572 if (result != VK_SUCCESS)
2573 return result;
2574
2575 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2576 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2577 &queue->device->empty_cs[queue->queue_family_index],
2578 1, NULL, NULL,
2579 &sem_info,
2580 false, base_fence);
2581 fence_emitted = true;
2582 if (fence)
2583 fence->submitted = true;
2584 }
2585
2586 radv_free_sem_info(&sem_info);
2587
2588 }
2589
2590 if (fence && !fence_emitted) {
2591 fence->signalled = true;
2592 }
2593
2594 return VK_SUCCESS;
2595 }
2596
2597 VkResult radv_CreateFence(
2598 VkDevice _device,
2599 const VkFenceCreateInfo* pCreateInfo,
2600 const VkAllocationCallbacks* pAllocator,
2601 VkFence* pFence)
2602 {
2603 RADV_FROM_HANDLE(radv_device, device, _device);
2604 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2605 sizeof(*fence), 8,
2606 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2607
2608 if (!fence)
2609 return VK_ERROR_OUT_OF_HOST_MEMORY;
2610
2611 memset(fence, 0, sizeof(*fence));
2612 fence->submitted = false;
2613 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2614 fence->fence = device->ws->create_fence();
2615 if (!fence->fence) {
2616 vk_free2(&device->alloc, pAllocator, fence);
2617 return VK_ERROR_OUT_OF_HOST_MEMORY;
2618 }
2619
2620 *pFence = radv_fence_to_handle(fence);
2621
2622 return VK_SUCCESS;
2623 }
2624
2625 void radv_DestroyFence(
2626 VkDevice _device,
2627 VkFence _fence,
2628 const VkAllocationCallbacks* pAllocator)
2629 {
2630 RADV_FROM_HANDLE(radv_device, device, _device);
2631 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2632
2633 if (!fence)
2634 return;
2635 device->ws->destroy_fence(fence->fence);
2636 vk_free2(&device->alloc, pAllocator, fence);
2637 }
2638
2639 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2640 {
2641 uint64_t current_time;
2642 struct timespec tv;
2643
2644 clock_gettime(CLOCK_MONOTONIC, &tv);
2645 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2646
2647 timeout = MIN2(UINT64_MAX - current_time, timeout);
2648
2649 return current_time + timeout;
2650 }
2651
2652 VkResult radv_WaitForFences(
2653 VkDevice _device,
2654 uint32_t fenceCount,
2655 const VkFence* pFences,
2656 VkBool32 waitAll,
2657 uint64_t timeout)
2658 {
2659 RADV_FROM_HANDLE(radv_device, device, _device);
2660 timeout = radv_get_absolute_timeout(timeout);
2661
2662 if (!waitAll && fenceCount > 1) {
2663 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2664 }
2665
2666 for (uint32_t i = 0; i < fenceCount; ++i) {
2667 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2668 bool expired = false;
2669
2670 if (fence->signalled)
2671 continue;
2672
2673 if (!fence->submitted)
2674 return VK_TIMEOUT;
2675
2676 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2677 if (!expired)
2678 return VK_TIMEOUT;
2679
2680 fence->signalled = true;
2681 }
2682
2683 return VK_SUCCESS;
2684 }
2685
2686 VkResult radv_ResetFences(VkDevice device,
2687 uint32_t fenceCount,
2688 const VkFence *pFences)
2689 {
2690 for (unsigned i = 0; i < fenceCount; ++i) {
2691 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2692 fence->submitted = fence->signalled = false;
2693 }
2694
2695 return VK_SUCCESS;
2696 }
2697
2698 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2699 {
2700 RADV_FROM_HANDLE(radv_device, device, _device);
2701 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2702
2703 if (fence->signalled)
2704 return VK_SUCCESS;
2705 if (!fence->submitted)
2706 return VK_NOT_READY;
2707
2708 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2709 return VK_NOT_READY;
2710
2711 return VK_SUCCESS;
2712 }
2713
2714
2715 // Queue semaphore functions
2716
2717 VkResult radv_CreateSemaphore(
2718 VkDevice _device,
2719 const VkSemaphoreCreateInfo* pCreateInfo,
2720 const VkAllocationCallbacks* pAllocator,
2721 VkSemaphore* pSemaphore)
2722 {
2723 RADV_FROM_HANDLE(radv_device, device, _device);
2724 const VkExportSemaphoreCreateInfoKHR *export =
2725 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2726 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2727 export ? export->handleTypes : 0;
2728
2729 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2730 sizeof(*sem), 8,
2731 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2732 if (!sem)
2733 return VK_ERROR_OUT_OF_HOST_MEMORY;
2734
2735 sem->temp_syncobj = 0;
2736 /* create a syncobject if we are going to export this semaphore */
2737 if (handleTypes) {
2738 assert (device->physical_device->rad_info.has_syncobj);
2739 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2740 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2741 if (ret) {
2742 vk_free2(&device->alloc, pAllocator, sem);
2743 return VK_ERROR_OUT_OF_HOST_MEMORY;
2744 }
2745 sem->sem = NULL;
2746 } else {
2747 sem->sem = device->ws->create_sem(device->ws);
2748 if (!sem->sem) {
2749 vk_free2(&device->alloc, pAllocator, sem);
2750 return VK_ERROR_OUT_OF_HOST_MEMORY;
2751 }
2752 sem->syncobj = 0;
2753 }
2754
2755 *pSemaphore = radv_semaphore_to_handle(sem);
2756 return VK_SUCCESS;
2757 }
2758
2759 void radv_DestroySemaphore(
2760 VkDevice _device,
2761 VkSemaphore _semaphore,
2762 const VkAllocationCallbacks* pAllocator)
2763 {
2764 RADV_FROM_HANDLE(radv_device, device, _device);
2765 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2766 if (!_semaphore)
2767 return;
2768
2769 if (sem->syncobj)
2770 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2771 else
2772 device->ws->destroy_sem(sem->sem);
2773 vk_free2(&device->alloc, pAllocator, sem);
2774 }
2775
2776 VkResult radv_CreateEvent(
2777 VkDevice _device,
2778 const VkEventCreateInfo* pCreateInfo,
2779 const VkAllocationCallbacks* pAllocator,
2780 VkEvent* pEvent)
2781 {
2782 RADV_FROM_HANDLE(radv_device, device, _device);
2783 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2784 sizeof(*event), 8,
2785 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2786
2787 if (!event)
2788 return VK_ERROR_OUT_OF_HOST_MEMORY;
2789
2790 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2791 RADEON_DOMAIN_GTT,
2792 RADEON_FLAG_CPU_ACCESS);
2793 if (!event->bo) {
2794 vk_free2(&device->alloc, pAllocator, event);
2795 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2796 }
2797
2798 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2799
2800 *pEvent = radv_event_to_handle(event);
2801
2802 return VK_SUCCESS;
2803 }
2804
2805 void radv_DestroyEvent(
2806 VkDevice _device,
2807 VkEvent _event,
2808 const VkAllocationCallbacks* pAllocator)
2809 {
2810 RADV_FROM_HANDLE(radv_device, device, _device);
2811 RADV_FROM_HANDLE(radv_event, event, _event);
2812
2813 if (!event)
2814 return;
2815 device->ws->buffer_destroy(event->bo);
2816 vk_free2(&device->alloc, pAllocator, event);
2817 }
2818
2819 VkResult radv_GetEventStatus(
2820 VkDevice _device,
2821 VkEvent _event)
2822 {
2823 RADV_FROM_HANDLE(radv_event, event, _event);
2824
2825 if (*event->map == 1)
2826 return VK_EVENT_SET;
2827 return VK_EVENT_RESET;
2828 }
2829
2830 VkResult radv_SetEvent(
2831 VkDevice _device,
2832 VkEvent _event)
2833 {
2834 RADV_FROM_HANDLE(radv_event, event, _event);
2835 *event->map = 1;
2836
2837 return VK_SUCCESS;
2838 }
2839
2840 VkResult radv_ResetEvent(
2841 VkDevice _device,
2842 VkEvent _event)
2843 {
2844 RADV_FROM_HANDLE(radv_event, event, _event);
2845 *event->map = 0;
2846
2847 return VK_SUCCESS;
2848 }
2849
2850 VkResult radv_CreateBuffer(
2851 VkDevice _device,
2852 const VkBufferCreateInfo* pCreateInfo,
2853 const VkAllocationCallbacks* pAllocator,
2854 VkBuffer* pBuffer)
2855 {
2856 RADV_FROM_HANDLE(radv_device, device, _device);
2857 struct radv_buffer *buffer;
2858
2859 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2860
2861 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2862 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2863 if (buffer == NULL)
2864 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2865
2866 buffer->size = pCreateInfo->size;
2867 buffer->usage = pCreateInfo->usage;
2868 buffer->bo = NULL;
2869 buffer->offset = 0;
2870 buffer->flags = pCreateInfo->flags;
2871
2872 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2873 buffer->bo = device->ws->buffer_create(device->ws,
2874 align64(buffer->size, 4096),
2875 4096, 0, RADEON_FLAG_VIRTUAL);
2876 if (!buffer->bo) {
2877 vk_free2(&device->alloc, pAllocator, buffer);
2878 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2879 }
2880 }
2881
2882 *pBuffer = radv_buffer_to_handle(buffer);
2883
2884 return VK_SUCCESS;
2885 }
2886
2887 void radv_DestroyBuffer(
2888 VkDevice _device,
2889 VkBuffer _buffer,
2890 const VkAllocationCallbacks* pAllocator)
2891 {
2892 RADV_FROM_HANDLE(radv_device, device, _device);
2893 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2894
2895 if (!buffer)
2896 return;
2897
2898 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2899 device->ws->buffer_destroy(buffer->bo);
2900
2901 vk_free2(&device->alloc, pAllocator, buffer);
2902 }
2903
2904 static inline unsigned
2905 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2906 {
2907 if (stencil)
2908 return image->surface.u.legacy.stencil_tiling_index[level];
2909 else
2910 return image->surface.u.legacy.tiling_index[level];
2911 }
2912
2913 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2914 {
2915 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2916 }
2917
2918 static void
2919 radv_initialise_color_surface(struct radv_device *device,
2920 struct radv_color_buffer_info *cb,
2921 struct radv_image_view *iview)
2922 {
2923 const struct vk_format_description *desc;
2924 unsigned ntype, format, swap, endian;
2925 unsigned blend_clamp = 0, blend_bypass = 0;
2926 uint64_t va;
2927 const struct radeon_surf *surf = &iview->image->surface;
2928
2929 desc = vk_format_description(iview->vk_format);
2930
2931 memset(cb, 0, sizeof(*cb));
2932
2933 /* Intensity is implemented as Red, so treat it that way. */
2934 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2935
2936 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2937
2938 cb->cb_color_base = va >> 8;
2939
2940 if (device->physical_device->rad_info.chip_class >= GFX9) {
2941 struct gfx9_surf_meta_flags meta;
2942 if (iview->image->dcc_offset)
2943 meta = iview->image->surface.u.gfx9.dcc;
2944 else
2945 meta = iview->image->surface.u.gfx9.cmask;
2946
2947 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2948 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2949 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2950 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2951
2952 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2953 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2954 } else {
2955 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2956 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2957
2958 cb->cb_color_base += level_info->offset >> 8;
2959 if (level_info->mode == RADEON_SURF_MODE_2D)
2960 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2961
2962 pitch_tile_max = level_info->nblk_x / 8 - 1;
2963 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2964 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2965
2966 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2967 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2968 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2969
2970 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2971 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2972
2973 if (iview->image->fmask.size) {
2974 if (device->physical_device->rad_info.chip_class >= CIK)
2975 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2976 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2977 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2978 } else {
2979 /* This must be set for fast clear to work without FMASK. */
2980 if (device->physical_device->rad_info.chip_class >= CIK)
2981 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2982 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2983 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2984 }
2985 }
2986
2987 /* CMASK variables */
2988 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2989 va += iview->image->cmask.offset;
2990 cb->cb_color_cmask = va >> 8;
2991
2992 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2993 va += iview->image->dcc_offset;
2994 cb->cb_dcc_base = va >> 8;
2995 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2996
2997 uint32_t max_slice = radv_surface_layer_count(iview);
2998 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2999 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3000
3001 if (iview->image->info.samples > 1) {
3002 unsigned log_samples = util_logbase2(iview->image->info.samples);
3003
3004 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3005 S_028C74_NUM_FRAGMENTS(log_samples);
3006 }
3007
3008 if (iview->image->fmask.size) {
3009 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3010 cb->cb_color_fmask = va >> 8;
3011 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3012 } else {
3013 cb->cb_color_fmask = cb->cb_color_base;
3014 }
3015
3016 ntype = radv_translate_color_numformat(iview->vk_format,
3017 desc,
3018 vk_format_get_first_non_void_channel(iview->vk_format));
3019 format = radv_translate_colorformat(iview->vk_format);
3020 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3021 radv_finishme("Illegal color\n");
3022 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3023 endian = radv_colorformat_endian_swap(format);
3024
3025 /* blend clamp should be set for all NORM/SRGB types */
3026 if (ntype == V_028C70_NUMBER_UNORM ||
3027 ntype == V_028C70_NUMBER_SNORM ||
3028 ntype == V_028C70_NUMBER_SRGB)
3029 blend_clamp = 1;
3030
3031 /* set blend bypass according to docs if SINT/UINT or
3032 8/24 COLOR variants */
3033 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3034 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3035 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3036 blend_clamp = 0;
3037 blend_bypass = 1;
3038 }
3039 #if 0
3040 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3041 (format == V_028C70_COLOR_8 ||
3042 format == V_028C70_COLOR_8_8 ||
3043 format == V_028C70_COLOR_8_8_8_8))
3044 ->color_is_int8 = true;
3045 #endif
3046 cb->cb_color_info = S_028C70_FORMAT(format) |
3047 S_028C70_COMP_SWAP(swap) |
3048 S_028C70_BLEND_CLAMP(blend_clamp) |
3049 S_028C70_BLEND_BYPASS(blend_bypass) |
3050 S_028C70_SIMPLE_FLOAT(1) |
3051 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3052 ntype != V_028C70_NUMBER_SNORM &&
3053 ntype != V_028C70_NUMBER_SRGB &&
3054 format != V_028C70_COLOR_8_24 &&
3055 format != V_028C70_COLOR_24_8) |
3056 S_028C70_NUMBER_TYPE(ntype) |
3057 S_028C70_ENDIAN(endian);
3058 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3059 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3060 if (device->physical_device->rad_info.chip_class == SI) {
3061 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3062 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3063 }
3064 }
3065
3066 if (iview->image->cmask.size &&
3067 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3068 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3069
3070 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3071 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3072
3073 if (device->physical_device->rad_info.chip_class >= VI) {
3074 unsigned max_uncompressed_block_size = 2;
3075 if (iview->image->info.samples > 1) {
3076 if (iview->image->surface.bpe == 1)
3077 max_uncompressed_block_size = 0;
3078 else if (iview->image->surface.bpe == 2)
3079 max_uncompressed_block_size = 1;
3080 }
3081
3082 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3083 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3084 }
3085
3086 /* This must be set for fast clear to work without FMASK. */
3087 if (!iview->image->fmask.size &&
3088 device->physical_device->rad_info.chip_class == SI) {
3089 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3090 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3091 }
3092
3093 if (device->physical_device->rad_info.chip_class >= GFX9) {
3094 uint32_t max_slice = radv_surface_layer_count(iview);
3095 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3096
3097 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3098 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3099 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3100 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3101 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3102 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3103
3104 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3105
3106 }
3107 }
3108
3109 static void
3110 radv_initialise_ds_surface(struct radv_device *device,
3111 struct radv_ds_buffer_info *ds,
3112 struct radv_image_view *iview)
3113 {
3114 unsigned level = iview->base_mip;
3115 unsigned format, stencil_format;
3116 uint64_t va, s_offs, z_offs;
3117 bool stencil_only = false;
3118 memset(ds, 0, sizeof(*ds));
3119 switch (iview->image->vk_format) {
3120 case VK_FORMAT_D24_UNORM_S8_UINT:
3121 case VK_FORMAT_X8_D24_UNORM_PACK32:
3122 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3123 ds->offset_scale = 2.0f;
3124 break;
3125 case VK_FORMAT_D16_UNORM:
3126 case VK_FORMAT_D16_UNORM_S8_UINT:
3127 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3128 ds->offset_scale = 4.0f;
3129 break;
3130 case VK_FORMAT_D32_SFLOAT:
3131 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3132 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3133 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3134 ds->offset_scale = 1.0f;
3135 break;
3136 case VK_FORMAT_S8_UINT:
3137 stencil_only = true;
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 format = radv_translate_dbformat(iview->image->vk_format);
3144 stencil_format = iview->image->surface.has_stencil ?
3145 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3146
3147 uint32_t max_slice = radv_surface_layer_count(iview);
3148 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3149 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3150
3151 ds->db_htile_data_base = 0;
3152 ds->db_htile_surface = 0;
3153
3154 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3155 s_offs = z_offs = va;
3156
3157 if (device->physical_device->rad_info.chip_class >= GFX9) {
3158 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3159 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3160
3161 ds->db_z_info = S_028038_FORMAT(format) |
3162 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3163 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3164 S_028038_MAXMIP(iview->image->info.levels - 1);
3165 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3166 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3167
3168 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3169 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3170 ds->db_depth_view |= S_028008_MIPID(level);
3171
3172 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3173 S_02801C_Y_MAX(iview->image->info.height - 1);
3174
3175 /* Only use HTILE for the first level. */
3176 if (iview->image->surface.htile_size && !level) {
3177 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3178
3179 if (!iview->image->surface.has_stencil)
3180 /* Use all of the htile_buffer for depth if there's no stencil. */
3181 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3182 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3183 iview->image->htile_offset;
3184 ds->db_htile_data_base = va >> 8;
3185 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3186 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3187 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3188 }
3189 } else {
3190 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3191
3192 if (stencil_only)
3193 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3194
3195 z_offs += iview->image->surface.u.legacy.level[level].offset;
3196 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3197
3198 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3199 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3200 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3201
3202 if (iview->image->info.samples > 1)
3203 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3204
3205 if (device->physical_device->rad_info.chip_class >= CIK) {
3206 struct radeon_info *info = &device->physical_device->rad_info;
3207 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3208 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3209 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3210 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3211 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3212 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3213
3214 if (stencil_only)
3215 tile_mode = stencil_tile_mode;
3216
3217 ds->db_depth_info |=
3218 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3219 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3220 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3221 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3222 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3223 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3224 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3225 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3226 } else {
3227 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3228 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3229 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3230 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3231 if (stencil_only)
3232 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3233 }
3234
3235 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3236 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3237 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3238
3239 if (iview->image->surface.htile_size && !level) {
3240 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3241
3242 if (!iview->image->surface.has_stencil)
3243 /* Use all of the htile_buffer for depth if there's no stencil. */
3244 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3245
3246 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3247 iview->image->htile_offset;
3248 ds->db_htile_data_base = va >> 8;
3249 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3250 }
3251 }
3252
3253 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3254 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3255 }
3256
3257 VkResult radv_CreateFramebuffer(
3258 VkDevice _device,
3259 const VkFramebufferCreateInfo* pCreateInfo,
3260 const VkAllocationCallbacks* pAllocator,
3261 VkFramebuffer* pFramebuffer)
3262 {
3263 RADV_FROM_HANDLE(radv_device, device, _device);
3264 struct radv_framebuffer *framebuffer;
3265
3266 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3267
3268 size_t size = sizeof(*framebuffer) +
3269 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3270 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3271 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3272 if (framebuffer == NULL)
3273 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3274
3275 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3276 framebuffer->width = pCreateInfo->width;
3277 framebuffer->height = pCreateInfo->height;
3278 framebuffer->layers = pCreateInfo->layers;
3279 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3280 VkImageView _iview = pCreateInfo->pAttachments[i];
3281 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3282 framebuffer->attachments[i].attachment = iview;
3283 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3284 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3285 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3286 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3287 }
3288 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3289 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3290 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3291 }
3292
3293 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3294 return VK_SUCCESS;
3295 }
3296
3297 void radv_DestroyFramebuffer(
3298 VkDevice _device,
3299 VkFramebuffer _fb,
3300 const VkAllocationCallbacks* pAllocator)
3301 {
3302 RADV_FROM_HANDLE(radv_device, device, _device);
3303 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3304
3305 if (!fb)
3306 return;
3307 vk_free2(&device->alloc, pAllocator, fb);
3308 }
3309
3310 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3311 {
3312 switch (address_mode) {
3313 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3314 return V_008F30_SQ_TEX_WRAP;
3315 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3316 return V_008F30_SQ_TEX_MIRROR;
3317 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3318 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3319 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3320 return V_008F30_SQ_TEX_CLAMP_BORDER;
3321 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3322 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3323 default:
3324 unreachable("illegal tex wrap mode");
3325 break;
3326 }
3327 }
3328
3329 static unsigned
3330 radv_tex_compare(VkCompareOp op)
3331 {
3332 switch (op) {
3333 case VK_COMPARE_OP_NEVER:
3334 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3335 case VK_COMPARE_OP_LESS:
3336 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3337 case VK_COMPARE_OP_EQUAL:
3338 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3339 case VK_COMPARE_OP_LESS_OR_EQUAL:
3340 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3341 case VK_COMPARE_OP_GREATER:
3342 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3343 case VK_COMPARE_OP_NOT_EQUAL:
3344 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3345 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3346 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3347 case VK_COMPARE_OP_ALWAYS:
3348 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3349 default:
3350 unreachable("illegal compare mode");
3351 break;
3352 }
3353 }
3354
3355 static unsigned
3356 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3357 {
3358 switch (filter) {
3359 case VK_FILTER_NEAREST:
3360 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3361 V_008F38_SQ_TEX_XY_FILTER_POINT);
3362 case VK_FILTER_LINEAR:
3363 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3364 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3365 case VK_FILTER_CUBIC_IMG:
3366 default:
3367 fprintf(stderr, "illegal texture filter");
3368 return 0;
3369 }
3370 }
3371
3372 static unsigned
3373 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3374 {
3375 switch (mode) {
3376 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3377 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3378 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3379 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3380 default:
3381 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3382 }
3383 }
3384
3385 static unsigned
3386 radv_tex_bordercolor(VkBorderColor bcolor)
3387 {
3388 switch (bcolor) {
3389 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3390 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3391 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3392 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3393 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3394 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3395 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3396 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3397 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3398 default:
3399 break;
3400 }
3401 return 0;
3402 }
3403
3404 static unsigned
3405 radv_tex_aniso_filter(unsigned filter)
3406 {
3407 if (filter < 2)
3408 return 0;
3409 if (filter < 4)
3410 return 1;
3411 if (filter < 8)
3412 return 2;
3413 if (filter < 16)
3414 return 3;
3415 return 4;
3416 }
3417
3418 static void
3419 radv_init_sampler(struct radv_device *device,
3420 struct radv_sampler *sampler,
3421 const VkSamplerCreateInfo *pCreateInfo)
3422 {
3423 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3424 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3425 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3426 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3427
3428 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3429 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3430 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3431 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3432 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3433 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3434 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3435 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3436 S_008F30_DISABLE_CUBE_WRAP(0) |
3437 S_008F30_COMPAT_MODE(is_vi));
3438 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3439 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3440 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3441 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3442 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3443 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3444 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3445 S_008F38_MIP_POINT_PRECLAMP(0) |
3446 S_008F38_DISABLE_LSB_CEIL(1) |
3447 S_008F38_FILTER_PREC_FIX(1) |
3448 S_008F38_ANISO_OVERRIDE(is_vi));
3449 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3450 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3451 }
3452
3453 VkResult radv_CreateSampler(
3454 VkDevice _device,
3455 const VkSamplerCreateInfo* pCreateInfo,
3456 const VkAllocationCallbacks* pAllocator,
3457 VkSampler* pSampler)
3458 {
3459 RADV_FROM_HANDLE(radv_device, device, _device);
3460 struct radv_sampler *sampler;
3461
3462 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3463
3464 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3465 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3466 if (!sampler)
3467 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3468
3469 radv_init_sampler(device, sampler, pCreateInfo);
3470 *pSampler = radv_sampler_to_handle(sampler);
3471
3472 return VK_SUCCESS;
3473 }
3474
3475 void radv_DestroySampler(
3476 VkDevice _device,
3477 VkSampler _sampler,
3478 const VkAllocationCallbacks* pAllocator)
3479 {
3480 RADV_FROM_HANDLE(radv_device, device, _device);
3481 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3482
3483 if (!sampler)
3484 return;
3485 vk_free2(&device->alloc, pAllocator, sampler);
3486 }
3487
3488 /* vk_icd.h does not declare this function, so we declare it here to
3489 * suppress Wmissing-prototypes.
3490 */
3491 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3492 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3493
3494 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3495 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3496 {
3497 /* For the full details on loader interface versioning, see
3498 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3499 * What follows is a condensed summary, to help you navigate the large and
3500 * confusing official doc.
3501 *
3502 * - Loader interface v0 is incompatible with later versions. We don't
3503 * support it.
3504 *
3505 * - In loader interface v1:
3506 * - The first ICD entrypoint called by the loader is
3507 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3508 * entrypoint.
3509 * - The ICD must statically expose no other Vulkan symbol unless it is
3510 * linked with -Bsymbolic.
3511 * - Each dispatchable Vulkan handle created by the ICD must be
3512 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3513 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3514 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3515 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3516 * such loader-managed surfaces.
3517 *
3518 * - Loader interface v2 differs from v1 in:
3519 * - The first ICD entrypoint called by the loader is
3520 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3521 * statically expose this entrypoint.
3522 *
3523 * - Loader interface v3 differs from v2 in:
3524 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3525 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3526 * because the loader no longer does so.
3527 */
3528 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3529 return VK_SUCCESS;
3530 }
3531
3532 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3533 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3534 int *pFD)
3535 {
3536 RADV_FROM_HANDLE(radv_device, device, _device);
3537 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3538
3539 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3540
3541 /* We support only one handle type. */
3542 assert(pGetFdInfo->handleType ==
3543 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3544
3545 bool ret = radv_get_memory_fd(device, memory, pFD);
3546 if (ret == false)
3547 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3548 return VK_SUCCESS;
3549 }
3550
3551 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3552 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3553 int fd,
3554 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3555 {
3556 /* The valid usage section for this function says:
3557 *
3558 * "handleType must not be one of the handle types defined as opaque."
3559 *
3560 * Since we only handle opaque handles for now, there are no FD properties.
3561 */
3562 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3563 }
3564
3565 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3566 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3567 {
3568 RADV_FROM_HANDLE(radv_device, device, _device);
3569 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3570 uint32_t syncobj_handle = 0;
3571 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3572
3573 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3574 if (ret != 0)
3575 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3576
3577 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3578 sem->temp_syncobj = syncobj_handle;
3579 } else {
3580 sem->syncobj = syncobj_handle;
3581 }
3582 close(pImportSemaphoreFdInfo->fd);
3583 return VK_SUCCESS;
3584 }
3585
3586 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3587 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3588 int *pFd)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3592 int ret;
3593 uint32_t syncobj_handle;
3594
3595 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3596 if (sem->temp_syncobj)
3597 syncobj_handle = sem->temp_syncobj;
3598 else
3599 syncobj_handle = sem->syncobj;
3600 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3601 if (ret)
3602 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3603 return VK_SUCCESS;
3604 }
3605
3606 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3607 VkPhysicalDevice physicalDevice,
3608 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3609 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3610 {
3611 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3612 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3613 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3614 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3615 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3616 } else {
3617 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3618 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3619 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3620 }
3621 }