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radv/gfx10: implement radv_init_sampler()
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 /* Out-of-order primitive rasterization. */
366 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
367 device->rad_info.max_se >= 2;
368 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
369 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
370
371 device->dcc_msaa_allowed =
372 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
373
374 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
375 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
376 (device->rad_info.chip_class >= GFX8 &&
377 device->rad_info.me_fw_feature >= 41);
378
379 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
380
381 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
382
383 radv_physical_device_init_mem_types(device);
384 radv_fill_device_extension_table(device, &device->supported_extensions);
385
386 device->bus_info = *drm_device->businfo.pci;
387
388 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
389 ac_print_gpu_info(&device->rad_info);
390
391 /* The WSI is structured as a layer on top of the driver, so this has
392 * to be the last part of initialization (at least until we get other
393 * semi-layers).
394 */
395 result = radv_init_wsi(device);
396 if (result != VK_SUCCESS) {
397 device->ws->destroy(device->ws);
398 vk_error(instance, result);
399 goto fail;
400 }
401
402 return VK_SUCCESS;
403
404 fail:
405 close(fd);
406 if (master_fd != -1)
407 close(master_fd);
408 return result;
409 }
410
411 static void
412 radv_physical_device_finish(struct radv_physical_device *device)
413 {
414 radv_finish_wsi(device);
415 device->ws->destroy(device->ws);
416 disk_cache_destroy(device->disk_cache);
417 close(device->local_fd);
418 if (device->master_fd != -1)
419 close(device->master_fd);
420 }
421
422 static void *
423 default_alloc_func(void *pUserData, size_t size, size_t align,
424 VkSystemAllocationScope allocationScope)
425 {
426 return malloc(size);
427 }
428
429 static void *
430 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
431 size_t align, VkSystemAllocationScope allocationScope)
432 {
433 return realloc(pOriginal, size);
434 }
435
436 static void
437 default_free_func(void *pUserData, void *pMemory)
438 {
439 free(pMemory);
440 }
441
442 static const VkAllocationCallbacks default_alloc = {
443 .pUserData = NULL,
444 .pfnAllocation = default_alloc_func,
445 .pfnReallocation = default_realloc_func,
446 .pfnFree = default_free_func,
447 };
448
449 static const struct debug_control radv_debug_options[] = {
450 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
451 {"nodcc", RADV_DEBUG_NO_DCC},
452 {"shaders", RADV_DEBUG_DUMP_SHADERS},
453 {"nocache", RADV_DEBUG_NO_CACHE},
454 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
455 {"nohiz", RADV_DEBUG_NO_HIZ},
456 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
457 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
458 {"allbos", RADV_DEBUG_ALL_BOS},
459 {"noibs", RADV_DEBUG_NO_IBS},
460 {"spirv", RADV_DEBUG_DUMP_SPIRV},
461 {"vmfaults", RADV_DEBUG_VM_FAULTS},
462 {"zerovram", RADV_DEBUG_ZERO_VRAM},
463 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
464 {"nosisched", RADV_DEBUG_NO_SISCHED},
465 {"preoptir", RADV_DEBUG_PREOPTIR},
466 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
467 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
468 {"info", RADV_DEBUG_INFO},
469 {"errors", RADV_DEBUG_ERRORS},
470 {"startup", RADV_DEBUG_STARTUP},
471 {"checkir", RADV_DEBUG_CHECKIR},
472 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
473 {"nobinning", RADV_DEBUG_NOBINNING},
474 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
475 {NULL, 0}
476 };
477
478 const char *
479 radv_get_debug_option_name(int id)
480 {
481 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
482 return radv_debug_options[id].string;
483 }
484
485 static const struct debug_control radv_perftest_options[] = {
486 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
487 {"sisched", RADV_PERFTEST_SISCHED},
488 {"localbos", RADV_PERFTEST_LOCAL_BOS},
489 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
490 {"bolist", RADV_PERFTEST_BO_LIST},
491 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
492 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
493 {NULL, 0}
494 };
495
496 const char *
497 radv_get_perftest_option_name(int id)
498 {
499 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
500 return radv_perftest_options[id].string;
501 }
502
503 static void
504 radv_handle_per_app_options(struct radv_instance *instance,
505 const VkApplicationInfo *info)
506 {
507 const char *name = info ? info->pApplicationName : NULL;
508
509 if (!name)
510 return;
511
512 if (!strcmp(name, "Talos - Linux - 32bit") ||
513 !strcmp(name, "Talos - Linux - 64bit")) {
514 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
515 /* Force enable LLVM sisched for Talos because it looks
516 * safe and it gives few more FPS.
517 */
518 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
519 }
520 } else if (!strcmp(name, "DOOM_VFR")) {
521 /* Work around a Doom VFR game bug */
522 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
523 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
524 /* Workaround for a WaW hazard when LLVM moves/merges
525 * load/store memory operations.
526 * See https://reviews.llvm.org/D61313
527 */
528 if (HAVE_LLVM < 0x900)
529 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
530 }
531 }
532
533 static int radv_get_instance_extension_index(const char *name)
534 {
535 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
536 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
537 return i;
538 }
539 return -1;
540 }
541
542 static const char radv_dri_options_xml[] =
543 DRI_CONF_BEGIN
544 DRI_CONF_SECTION_QUALITY
545 DRI_CONF_ADAPTIVE_SYNC("true")
546 DRI_CONF_SECTION_END
547 DRI_CONF_END;
548
549 static void radv_init_dri_options(struct radv_instance *instance)
550 {
551 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
552 driParseConfigFiles(&instance->dri_options,
553 &instance->available_dri_options,
554 0, "radv", NULL);
555 }
556
557 VkResult radv_CreateInstance(
558 const VkInstanceCreateInfo* pCreateInfo,
559 const VkAllocationCallbacks* pAllocator,
560 VkInstance* pInstance)
561 {
562 struct radv_instance *instance;
563 VkResult result;
564
565 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
566
567 uint32_t client_version;
568 if (pCreateInfo->pApplicationInfo &&
569 pCreateInfo->pApplicationInfo->apiVersion != 0) {
570 client_version = pCreateInfo->pApplicationInfo->apiVersion;
571 } else {
572 client_version = VK_API_VERSION_1_0;
573 }
574
575 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
576 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
577 if (!instance)
578 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
579
580 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
581
582 if (pAllocator)
583 instance->alloc = *pAllocator;
584 else
585 instance->alloc = default_alloc;
586
587 instance->apiVersion = client_version;
588 instance->physicalDeviceCount = -1;
589
590 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
591 radv_debug_options);
592
593 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
594 radv_perftest_options);
595
596
597 if (instance->debug_flags & RADV_DEBUG_STARTUP)
598 radv_logi("Created an instance");
599
600 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
601 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
602 int index = radv_get_instance_extension_index(ext_name);
603
604 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
605 vk_free2(&default_alloc, pAllocator, instance);
606 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
607 }
608
609 instance->enabled_extensions.extensions[index] = true;
610 }
611
612 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
613 if (result != VK_SUCCESS) {
614 vk_free2(&default_alloc, pAllocator, instance);
615 return vk_error(instance, result);
616 }
617
618 _mesa_locale_init();
619 glsl_type_singleton_init_or_ref();
620
621 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
622
623 radv_init_dri_options(instance);
624 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
625
626 *pInstance = radv_instance_to_handle(instance);
627
628 return VK_SUCCESS;
629 }
630
631 void radv_DestroyInstance(
632 VkInstance _instance,
633 const VkAllocationCallbacks* pAllocator)
634 {
635 RADV_FROM_HANDLE(radv_instance, instance, _instance);
636
637 if (!instance)
638 return;
639
640 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
641 radv_physical_device_finish(instance->physicalDevices + i);
642 }
643
644 VG(VALGRIND_DESTROY_MEMPOOL(instance));
645
646 glsl_type_singleton_decref();
647 _mesa_locale_fini();
648
649 driDestroyOptionCache(&instance->dri_options);
650 driDestroyOptionInfo(&instance->available_dri_options);
651
652 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
653
654 vk_free(&instance->alloc, instance);
655 }
656
657 static VkResult
658 radv_enumerate_devices(struct radv_instance *instance)
659 {
660 /* TODO: Check for more devices ? */
661 drmDevicePtr devices[8];
662 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
663 int max_devices;
664
665 instance->physicalDeviceCount = 0;
666
667 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
668
669 if (instance->debug_flags & RADV_DEBUG_STARTUP)
670 radv_logi("Found %d drm nodes", max_devices);
671
672 if (max_devices < 1)
673 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
674
675 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
676 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
677 devices[i]->bustype == DRM_BUS_PCI &&
678 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
679
680 result = radv_physical_device_init(instance->physicalDevices +
681 instance->physicalDeviceCount,
682 instance,
683 devices[i]);
684 if (result == VK_SUCCESS)
685 ++instance->physicalDeviceCount;
686 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
687 break;
688 }
689 }
690 drmFreeDevices(devices, max_devices);
691
692 return result;
693 }
694
695 VkResult radv_EnumeratePhysicalDevices(
696 VkInstance _instance,
697 uint32_t* pPhysicalDeviceCount,
698 VkPhysicalDevice* pPhysicalDevices)
699 {
700 RADV_FROM_HANDLE(radv_instance, instance, _instance);
701 VkResult result;
702
703 if (instance->physicalDeviceCount < 0) {
704 result = radv_enumerate_devices(instance);
705 if (result != VK_SUCCESS &&
706 result != VK_ERROR_INCOMPATIBLE_DRIVER)
707 return result;
708 }
709
710 if (!pPhysicalDevices) {
711 *pPhysicalDeviceCount = instance->physicalDeviceCount;
712 } else {
713 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
714 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
715 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
716 }
717
718 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
719 : VK_SUCCESS;
720 }
721
722 VkResult radv_EnumeratePhysicalDeviceGroups(
723 VkInstance _instance,
724 uint32_t* pPhysicalDeviceGroupCount,
725 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
726 {
727 RADV_FROM_HANDLE(radv_instance, instance, _instance);
728 VkResult result;
729
730 if (instance->physicalDeviceCount < 0) {
731 result = radv_enumerate_devices(instance);
732 if (result != VK_SUCCESS &&
733 result != VK_ERROR_INCOMPATIBLE_DRIVER)
734 return result;
735 }
736
737 if (!pPhysicalDeviceGroupProperties) {
738 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
739 } else {
740 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
741 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
742 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
743 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
744 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
745 }
746 }
747 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
748 : VK_SUCCESS;
749 }
750
751 void radv_GetPhysicalDeviceFeatures(
752 VkPhysicalDevice physicalDevice,
753 VkPhysicalDeviceFeatures* pFeatures)
754 {
755 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
756 memset(pFeatures, 0, sizeof(*pFeatures));
757
758 *pFeatures = (VkPhysicalDeviceFeatures) {
759 .robustBufferAccess = true,
760 .fullDrawIndexUint32 = true,
761 .imageCubeArray = true,
762 .independentBlend = true,
763 .geometryShader = true,
764 .tessellationShader = true,
765 .sampleRateShading = true,
766 .dualSrcBlend = true,
767 .logicOp = true,
768 .multiDrawIndirect = true,
769 .drawIndirectFirstInstance = true,
770 .depthClamp = true,
771 .depthBiasClamp = true,
772 .fillModeNonSolid = true,
773 .depthBounds = true,
774 .wideLines = true,
775 .largePoints = true,
776 .alphaToOne = true,
777 .multiViewport = true,
778 .samplerAnisotropy = true,
779 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
780 .textureCompressionASTC_LDR = false,
781 .textureCompressionBC = true,
782 .occlusionQueryPrecise = true,
783 .pipelineStatisticsQuery = true,
784 .vertexPipelineStoresAndAtomics = true,
785 .fragmentStoresAndAtomics = true,
786 .shaderTessellationAndGeometryPointSize = true,
787 .shaderImageGatherExtended = true,
788 .shaderStorageImageExtendedFormats = true,
789 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
790 .shaderUniformBufferArrayDynamicIndexing = true,
791 .shaderSampledImageArrayDynamicIndexing = true,
792 .shaderStorageBufferArrayDynamicIndexing = true,
793 .shaderStorageImageArrayDynamicIndexing = true,
794 .shaderStorageImageReadWithoutFormat = true,
795 .shaderStorageImageWriteWithoutFormat = true,
796 .shaderClipDistance = true,
797 .shaderCullDistance = true,
798 .shaderFloat64 = true,
799 .shaderInt64 = true,
800 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
801 .sparseBinding = true,
802 .variableMultisampleRate = true,
803 .inheritedQueries = true,
804 };
805 }
806
807 void radv_GetPhysicalDeviceFeatures2(
808 VkPhysicalDevice physicalDevice,
809 VkPhysicalDeviceFeatures2 *pFeatures)
810 {
811 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
812 vk_foreach_struct(ext, pFeatures->pNext) {
813 switch (ext->sType) {
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
815 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
816 features->variablePointersStorageBuffer = true;
817 features->variablePointers = true;
818 break;
819 }
820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
821 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
822 features->multiview = true;
823 features->multiviewGeometryShader = true;
824 features->multiviewTessellationShader = true;
825 break;
826 }
827 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
828 VkPhysicalDeviceShaderDrawParametersFeatures *features =
829 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
830 features->shaderDrawParameters = true;
831 break;
832 }
833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
834 VkPhysicalDeviceProtectedMemoryFeatures *features =
835 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
836 features->protectedMemory = false;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
840 VkPhysicalDevice16BitStorageFeatures *features =
841 (VkPhysicalDevice16BitStorageFeatures*)ext;
842 bool enabled = pdevice->rad_info.chip_class >= GFX8;
843 features->storageBuffer16BitAccess = enabled;
844 features->uniformAndStorageBuffer16BitAccess = enabled;
845 features->storagePushConstant16 = enabled;
846 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
847 break;
848 }
849 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
850 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
851 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
852 features->samplerYcbcrConversion = true;
853 break;
854 }
855 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
856 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
857 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
858 features->shaderInputAttachmentArrayDynamicIndexing = true;
859 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
860 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
861 features->shaderUniformBufferArrayNonUniformIndexing = true;
862 features->shaderSampledImageArrayNonUniformIndexing = true;
863 features->shaderStorageBufferArrayNonUniformIndexing = true;
864 features->shaderStorageImageArrayNonUniformIndexing = true;
865 features->shaderInputAttachmentArrayNonUniformIndexing = true;
866 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
867 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
868 features->descriptorBindingUniformBufferUpdateAfterBind = true;
869 features->descriptorBindingSampledImageUpdateAfterBind = true;
870 features->descriptorBindingStorageImageUpdateAfterBind = true;
871 features->descriptorBindingStorageBufferUpdateAfterBind = true;
872 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
873 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
874 features->descriptorBindingUpdateUnusedWhilePending = true;
875 features->descriptorBindingPartiallyBound = true;
876 features->descriptorBindingVariableDescriptorCount = true;
877 features->runtimeDescriptorArray = true;
878 break;
879 }
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
881 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
882 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
883 features->conditionalRendering = true;
884 features->inheritedConditionalRendering = false;
885 break;
886 }
887 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
888 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
889 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
890 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
891 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
892 break;
893 }
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
895 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
896 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
897 features->transformFeedback = true;
898 features->geometryStreams = true;
899 break;
900 }
901 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
902 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
903 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
904 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
905 break;
906 }
907 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
908 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
909 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
910 features->memoryPriority = VK_TRUE;
911 break;
912 }
913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
914 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
915 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
916 features->bufferDeviceAddress = true;
917 features->bufferDeviceAddressCaptureReplay = false;
918 features->bufferDeviceAddressMultiDevice = false;
919 break;
920 }
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
922 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
923 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
924 features->depthClipEnable = true;
925 break;
926 }
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
928 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
929 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
930 features->hostQueryReset = true;
931 break;
932 }
933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
934 VkPhysicalDevice8BitStorageFeaturesKHR *features =
935 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
936 bool enabled = pdevice->rad_info.chip_class >= GFX8;
937 features->storageBuffer8BitAccess = enabled;
938 features->uniformAndStorageBuffer8BitAccess = enabled;
939 features->storagePushConstant8 = enabled;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
943 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
944 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
945 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
946 features->shaderInt8 = true;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
950 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
951 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
952 /* TODO: Enable this once the driver supports 64-bit
953 * compare&swap atomic operations.
954 */
955 features->shaderBufferInt64Atomics = false;
956 features->shaderSharedInt64Atomics = false;
957 break;
958 }
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
960 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
961 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
962
963 features->inlineUniformBlock = true;
964 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
968 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
969 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
970 features->computeDerivativeGroupQuads = false;
971 features->computeDerivativeGroupLinear = true;
972 break;
973 }
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
975 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
976 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
977 features->ycbcrImageArrays = true;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
981 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
982 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
983 features->uniformBufferStandardLayout = true;
984 break;
985 }
986 default:
987 break;
988 }
989 }
990 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
991 }
992
993 void radv_GetPhysicalDeviceProperties(
994 VkPhysicalDevice physicalDevice,
995 VkPhysicalDeviceProperties* pProperties)
996 {
997 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
998 VkSampleCountFlags sample_counts = 0xf;
999
1000 /* make sure that the entire descriptor set is addressable with a signed
1001 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1002 * be at most 2 GiB. the combined image & samples object count as one of
1003 * both. This limit is for the pipeline layout, not for the set layout, but
1004 * there is no set limit, so we just set a pipeline limit. I don't think
1005 * any app is going to hit this soon. */
1006 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1007 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1008 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1009 32 /* sampler, largest when combined with image */ +
1010 64 /* sampled image */ +
1011 64 /* storage image */);
1012
1013 VkPhysicalDeviceLimits limits = {
1014 .maxImageDimension1D = (1 << 14),
1015 .maxImageDimension2D = (1 << 14),
1016 .maxImageDimension3D = (1 << 11),
1017 .maxImageDimensionCube = (1 << 14),
1018 .maxImageArrayLayers = (1 << 11),
1019 .maxTexelBufferElements = 128 * 1024 * 1024,
1020 .maxUniformBufferRange = UINT32_MAX,
1021 .maxStorageBufferRange = UINT32_MAX,
1022 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1023 .maxMemoryAllocationCount = UINT32_MAX,
1024 .maxSamplerAllocationCount = 64 * 1024,
1025 .bufferImageGranularity = 64, /* A cache line */
1026 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1027 .maxBoundDescriptorSets = MAX_SETS,
1028 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1029 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1030 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1031 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1032 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1033 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1034 .maxPerStageResources = max_descriptor_set_size,
1035 .maxDescriptorSetSamplers = max_descriptor_set_size,
1036 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1037 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1038 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1039 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1040 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1041 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1042 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1043 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1044 .maxVertexInputBindings = MAX_VBS,
1045 .maxVertexInputAttributeOffset = 2047,
1046 .maxVertexInputBindingStride = 2048,
1047 .maxVertexOutputComponents = 128,
1048 .maxTessellationGenerationLevel = 64,
1049 .maxTessellationPatchSize = 32,
1050 .maxTessellationControlPerVertexInputComponents = 128,
1051 .maxTessellationControlPerVertexOutputComponents = 128,
1052 .maxTessellationControlPerPatchOutputComponents = 120,
1053 .maxTessellationControlTotalOutputComponents = 4096,
1054 .maxTessellationEvaluationInputComponents = 128,
1055 .maxTessellationEvaluationOutputComponents = 128,
1056 .maxGeometryShaderInvocations = 127,
1057 .maxGeometryInputComponents = 64,
1058 .maxGeometryOutputComponents = 128,
1059 .maxGeometryOutputVertices = 256,
1060 .maxGeometryTotalOutputComponents = 1024,
1061 .maxFragmentInputComponents = 128,
1062 .maxFragmentOutputAttachments = 8,
1063 .maxFragmentDualSrcAttachments = 1,
1064 .maxFragmentCombinedOutputResources = 8,
1065 .maxComputeSharedMemorySize = 32768,
1066 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1067 .maxComputeWorkGroupInvocations = 2048,
1068 .maxComputeWorkGroupSize = {
1069 2048,
1070 2048,
1071 2048
1072 },
1073 .subPixelPrecisionBits = 8,
1074 .subTexelPrecisionBits = 8,
1075 .mipmapPrecisionBits = 8,
1076 .maxDrawIndexedIndexValue = UINT32_MAX,
1077 .maxDrawIndirectCount = UINT32_MAX,
1078 .maxSamplerLodBias = 16,
1079 .maxSamplerAnisotropy = 16,
1080 .maxViewports = MAX_VIEWPORTS,
1081 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1082 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1083 .viewportSubPixelBits = 8,
1084 .minMemoryMapAlignment = 4096, /* A page */
1085 .minTexelBufferOffsetAlignment = 1,
1086 .minUniformBufferOffsetAlignment = 4,
1087 .minStorageBufferOffsetAlignment = 4,
1088 .minTexelOffset = -32,
1089 .maxTexelOffset = 31,
1090 .minTexelGatherOffset = -32,
1091 .maxTexelGatherOffset = 31,
1092 .minInterpolationOffset = -2,
1093 .maxInterpolationOffset = 2,
1094 .subPixelInterpolationOffsetBits = 8,
1095 .maxFramebufferWidth = (1 << 14),
1096 .maxFramebufferHeight = (1 << 14),
1097 .maxFramebufferLayers = (1 << 10),
1098 .framebufferColorSampleCounts = sample_counts,
1099 .framebufferDepthSampleCounts = sample_counts,
1100 .framebufferStencilSampleCounts = sample_counts,
1101 .framebufferNoAttachmentsSampleCounts = sample_counts,
1102 .maxColorAttachments = MAX_RTS,
1103 .sampledImageColorSampleCounts = sample_counts,
1104 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1105 .sampledImageDepthSampleCounts = sample_counts,
1106 .sampledImageStencilSampleCounts = sample_counts,
1107 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1108 .maxSampleMaskWords = 1,
1109 .timestampComputeAndGraphics = true,
1110 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1111 .maxClipDistances = 8,
1112 .maxCullDistances = 8,
1113 .maxCombinedClipAndCullDistances = 8,
1114 .discreteQueuePriorities = 2,
1115 .pointSizeRange = { 0.0, 8192.0 },
1116 .lineWidthRange = { 0.0, 7.9921875 },
1117 .pointSizeGranularity = (1.0 / 8.0),
1118 .lineWidthGranularity = (1.0 / 128.0),
1119 .strictLines = false, /* FINISHME */
1120 .standardSampleLocations = true,
1121 .optimalBufferCopyOffsetAlignment = 128,
1122 .optimalBufferCopyRowPitchAlignment = 128,
1123 .nonCoherentAtomSize = 64,
1124 };
1125
1126 *pProperties = (VkPhysicalDeviceProperties) {
1127 .apiVersion = radv_physical_device_api_version(pdevice),
1128 .driverVersion = vk_get_driver_version(),
1129 .vendorID = ATI_VENDOR_ID,
1130 .deviceID = pdevice->rad_info.pci_id,
1131 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1132 .limits = limits,
1133 .sparseProperties = {0},
1134 };
1135
1136 strcpy(pProperties->deviceName, pdevice->name);
1137 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1138 }
1139
1140 void radv_GetPhysicalDeviceProperties2(
1141 VkPhysicalDevice physicalDevice,
1142 VkPhysicalDeviceProperties2 *pProperties)
1143 {
1144 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1145 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1146
1147 vk_foreach_struct(ext, pProperties->pNext) {
1148 switch (ext->sType) {
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1150 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1151 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1152 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1153 break;
1154 }
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1156 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1157 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1158 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1159 properties->deviceLUIDValid = false;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1163 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1164 properties->maxMultiviewViewCount = MAX_VIEWS;
1165 properties->maxMultiviewInstanceIndex = INT_MAX;
1166 break;
1167 }
1168 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1169 VkPhysicalDevicePointClippingProperties *properties =
1170 (VkPhysicalDevicePointClippingProperties*)ext;
1171 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1172 break;
1173 }
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1175 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1176 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1177 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1178 break;
1179 }
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1181 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1182 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1183 properties->minImportedHostPointerAlignment = 4096;
1184 break;
1185 }
1186 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1187 VkPhysicalDeviceSubgroupProperties *properties =
1188 (VkPhysicalDeviceSubgroupProperties*)ext;
1189 properties->subgroupSize = 64;
1190 properties->supportedStages = VK_SHADER_STAGE_ALL;
1191 properties->supportedOperations =
1192 VK_SUBGROUP_FEATURE_BASIC_BIT |
1193 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1194 VK_SUBGROUP_FEATURE_QUAD_BIT |
1195 VK_SUBGROUP_FEATURE_VOTE_BIT;
1196 if (pdevice->rad_info.chip_class >= GFX8) {
1197 properties->supportedOperations |=
1198 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1199 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1200 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1201 }
1202 properties->quadOperationsInAllStages = true;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1206 VkPhysicalDeviceMaintenance3Properties *properties =
1207 (VkPhysicalDeviceMaintenance3Properties*)ext;
1208 /* Make sure everything is addressable by a signed 32-bit int, and
1209 * our largest descriptors are 96 bytes. */
1210 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1211 /* Our buffer size fields allow only this much */
1212 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1213 break;
1214 }
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1216 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1217 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1218 /* GFX6-8 only support single channel min/max filter. */
1219 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1220 properties->filterMinmaxSingleComponentFormats = true;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1224 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1225 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1226
1227 /* Shader engines. */
1228 properties->shaderEngineCount =
1229 pdevice->rad_info.max_se;
1230 properties->shaderArraysPerEngineCount =
1231 pdevice->rad_info.max_sh_per_se;
1232 properties->computeUnitsPerShaderArray =
1233 pdevice->rad_info.num_good_cu_per_sh;
1234 properties->simdPerComputeUnit = 4;
1235 properties->wavefrontsPerSimd =
1236 pdevice->rad_info.family == CHIP_TONGA ||
1237 pdevice->rad_info.family == CHIP_ICELAND ||
1238 pdevice->rad_info.family == CHIP_POLARIS10 ||
1239 pdevice->rad_info.family == CHIP_POLARIS11 ||
1240 pdevice->rad_info.family == CHIP_POLARIS12 ||
1241 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1242 properties->wavefrontSize = 64;
1243
1244 /* SGPR. */
1245 properties->sgprsPerSimd =
1246 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1247 properties->minSgprAllocation =
1248 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1249 properties->maxSgprAllocation =
1250 pdevice->rad_info.family == CHIP_TONGA ||
1251 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1252 properties->sgprAllocationGranularity =
1253 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1254
1255 /* VGPR. */
1256 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1257 properties->minVgprAllocation = 4;
1258 properties->maxVgprAllocation = 256;
1259 properties->vgprAllocationGranularity = 4;
1260 break;
1261 }
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1263 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1264 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1265 properties->maxVertexAttribDivisor = UINT32_MAX;
1266 break;
1267 }
1268 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1269 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1270 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1271 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1272 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1273 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1274 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1275 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1276 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1277 properties->robustBufferAccessUpdateAfterBind = false;
1278 properties->quadDivergentImplicitLod = false;
1279
1280 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1281 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1282 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1283 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1284 32 /* sampler, largest when combined with image */ +
1285 64 /* sampled image */ +
1286 64 /* storage image */);
1287 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1288 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1289 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1290 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1291 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1292 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1293 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1294 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1295 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1296 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1297 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1299 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1301 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1302 break;
1303 }
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1305 VkPhysicalDeviceProtectedMemoryProperties *properties =
1306 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1307 properties->protectedNoFault = false;
1308 break;
1309 }
1310 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1311 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1312 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1313 properties->primitiveOverestimationSize = 0;
1314 properties->maxExtraPrimitiveOverestimationSize = 0;
1315 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1316 properties->primitiveUnderestimation = VK_FALSE;
1317 properties->conservativePointAndLineRasterization = VK_FALSE;
1318 properties->degenerateTrianglesRasterized = VK_FALSE;
1319 properties->degenerateLinesRasterized = VK_FALSE;
1320 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1321 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1325 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1326 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1327 properties->pciDomain = pdevice->bus_info.domain;
1328 properties->pciBus = pdevice->bus_info.bus;
1329 properties->pciDevice = pdevice->bus_info.dev;
1330 properties->pciFunction = pdevice->bus_info.func;
1331 break;
1332 }
1333 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1334 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1335 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1336
1337 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1338 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1339 strcpy(driver_props->driverName, "radv");
1340
1341 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1342 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1343 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1344 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1345
1346 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1347 .major = 1,
1348 .minor = 1,
1349 .subminor = 2,
1350 .patch = 0,
1351 };
1352 break;
1353 }
1354 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1355 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1356 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1357 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1358 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1359 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1360 properties->maxTransformFeedbackStreamDataSize = 512;
1361 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1362 properties->maxTransformFeedbackBufferDataStride = 512;
1363 properties->transformFeedbackQueries = true;
1364 properties->transformFeedbackStreamsLinesTriangles = true;
1365 properties->transformFeedbackRasterizationStreamSelect = false;
1366 properties->transformFeedbackDraw = true;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1370 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1371 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1372
1373 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1374 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1375 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1376 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1377 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1378 break;
1379 }
1380 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1381 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1382 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1383 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1384 VK_SAMPLE_COUNT_4_BIT |
1385 VK_SAMPLE_COUNT_8_BIT;
1386 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1387 properties->sampleLocationCoordinateRange[0] = 0.0f;
1388 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1389 properties->sampleLocationSubPixelBits = 4;
1390 properties->variableSampleLocations = VK_FALSE;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1394 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1395 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1396
1397 /* We support all of the depth resolve modes */
1398 properties->supportedDepthResolveModes =
1399 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1400 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1401 VK_RESOLVE_MODE_MIN_BIT_KHR |
1402 VK_RESOLVE_MODE_MAX_BIT_KHR;
1403
1404 /* Average doesn't make sense for stencil so we don't support that */
1405 properties->supportedStencilResolveModes =
1406 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1407 VK_RESOLVE_MODE_MIN_BIT_KHR |
1408 VK_RESOLVE_MODE_MAX_BIT_KHR;
1409
1410 properties->independentResolveNone = VK_TRUE;
1411 properties->independentResolve = VK_TRUE;
1412 break;
1413 }
1414 default:
1415 break;
1416 }
1417 }
1418 }
1419
1420 static void radv_get_physical_device_queue_family_properties(
1421 struct radv_physical_device* pdevice,
1422 uint32_t* pCount,
1423 VkQueueFamilyProperties** pQueueFamilyProperties)
1424 {
1425 int num_queue_families = 1;
1426 int idx;
1427 if (pdevice->rad_info.num_compute_rings > 0 &&
1428 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1429 num_queue_families++;
1430
1431 if (pQueueFamilyProperties == NULL) {
1432 *pCount = num_queue_families;
1433 return;
1434 }
1435
1436 if (!*pCount)
1437 return;
1438
1439 idx = 0;
1440 if (*pCount >= 1) {
1441 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1442 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1443 VK_QUEUE_COMPUTE_BIT |
1444 VK_QUEUE_TRANSFER_BIT |
1445 VK_QUEUE_SPARSE_BINDING_BIT,
1446 .queueCount = 1,
1447 .timestampValidBits = 64,
1448 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1449 };
1450 idx++;
1451 }
1452
1453 if (pdevice->rad_info.num_compute_rings > 0 &&
1454 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1455 if (*pCount > idx) {
1456 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1457 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1458 VK_QUEUE_TRANSFER_BIT |
1459 VK_QUEUE_SPARSE_BINDING_BIT,
1460 .queueCount = pdevice->rad_info.num_compute_rings,
1461 .timestampValidBits = 64,
1462 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1463 };
1464 idx++;
1465 }
1466 }
1467 *pCount = idx;
1468 }
1469
1470 void radv_GetPhysicalDeviceQueueFamilyProperties(
1471 VkPhysicalDevice physicalDevice,
1472 uint32_t* pCount,
1473 VkQueueFamilyProperties* pQueueFamilyProperties)
1474 {
1475 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1476 if (!pQueueFamilyProperties) {
1477 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1478 return;
1479 }
1480 VkQueueFamilyProperties *properties[] = {
1481 pQueueFamilyProperties + 0,
1482 pQueueFamilyProperties + 1,
1483 pQueueFamilyProperties + 2,
1484 };
1485 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1486 assert(*pCount <= 3);
1487 }
1488
1489 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1490 VkPhysicalDevice physicalDevice,
1491 uint32_t* pCount,
1492 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1493 {
1494 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1495 if (!pQueueFamilyProperties) {
1496 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1497 return;
1498 }
1499 VkQueueFamilyProperties *properties[] = {
1500 &pQueueFamilyProperties[0].queueFamilyProperties,
1501 &pQueueFamilyProperties[1].queueFamilyProperties,
1502 &pQueueFamilyProperties[2].queueFamilyProperties,
1503 };
1504 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1505 assert(*pCount <= 3);
1506 }
1507
1508 void radv_GetPhysicalDeviceMemoryProperties(
1509 VkPhysicalDevice physicalDevice,
1510 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1511 {
1512 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1513
1514 *pMemoryProperties = physical_device->memory_properties;
1515 }
1516
1517 static void
1518 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1519 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1520 {
1521 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1522 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1523 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1524 uint64_t vram_size = radv_get_vram_size(device);
1525 uint64_t gtt_size = device->rad_info.gart_size;
1526 uint64_t heap_budget, heap_usage;
1527
1528 /* For all memory heaps, the computation of budget is as follow:
1529 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1530 *
1531 * The Vulkan spec 1.1.97 says that the budget should include any
1532 * currently allocated device memory.
1533 *
1534 * Note that the application heap usages are not really accurate (eg.
1535 * in presence of shared buffers).
1536 */
1537 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1538 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1539
1540 switch (device->mem_type_indices[i]) {
1541 case RADV_MEM_TYPE_VRAM:
1542 heap_usage = device->ws->query_value(device->ws,
1543 RADEON_ALLOCATED_VRAM);
1544
1545 heap_budget = vram_size -
1546 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1547 heap_usage;
1548
1549 memoryBudget->heapBudget[heap_index] = heap_budget;
1550 memoryBudget->heapUsage[heap_index] = heap_usage;
1551 break;
1552 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1553 heap_usage = device->ws->query_value(device->ws,
1554 RADEON_ALLOCATED_VRAM_VIS);
1555
1556 heap_budget = visible_vram_size -
1557 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1558 heap_usage;
1559
1560 memoryBudget->heapBudget[heap_index] = heap_budget;
1561 memoryBudget->heapUsage[heap_index] = heap_usage;
1562 break;
1563 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1564 heap_usage = device->ws->query_value(device->ws,
1565 RADEON_ALLOCATED_GTT);
1566
1567 heap_budget = gtt_size -
1568 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1569 heap_usage;
1570
1571 memoryBudget->heapBudget[heap_index] = heap_budget;
1572 memoryBudget->heapUsage[heap_index] = heap_usage;
1573 break;
1574 default:
1575 break;
1576 }
1577 }
1578
1579 /* The heapBudget and heapUsage values must be zero for array elements
1580 * greater than or equal to
1581 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1582 */
1583 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1584 memoryBudget->heapBudget[i] = 0;
1585 memoryBudget->heapUsage[i] = 0;
1586 }
1587 }
1588
1589 void radv_GetPhysicalDeviceMemoryProperties2(
1590 VkPhysicalDevice physicalDevice,
1591 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1592 {
1593 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1594 &pMemoryProperties->memoryProperties);
1595
1596 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1597 vk_find_struct(pMemoryProperties->pNext,
1598 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1599 if (memory_budget)
1600 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1601 }
1602
1603 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1604 VkDevice _device,
1605 VkExternalMemoryHandleTypeFlagBits handleType,
1606 const void *pHostPointer,
1607 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1608 {
1609 RADV_FROM_HANDLE(radv_device, device, _device);
1610
1611 switch (handleType)
1612 {
1613 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1614 const struct radv_physical_device *physical_device = device->physical_device;
1615 uint32_t memoryTypeBits = 0;
1616 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1617 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1618 memoryTypeBits = (1 << i);
1619 break;
1620 }
1621 }
1622 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1623 return VK_SUCCESS;
1624 }
1625 default:
1626 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1627 }
1628 }
1629
1630 static enum radeon_ctx_priority
1631 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1632 {
1633 /* Default to MEDIUM when a specific global priority isn't requested */
1634 if (!pObj)
1635 return RADEON_CTX_PRIORITY_MEDIUM;
1636
1637 switch(pObj->globalPriority) {
1638 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1639 return RADEON_CTX_PRIORITY_REALTIME;
1640 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1641 return RADEON_CTX_PRIORITY_HIGH;
1642 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1643 return RADEON_CTX_PRIORITY_MEDIUM;
1644 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1645 return RADEON_CTX_PRIORITY_LOW;
1646 default:
1647 unreachable("Illegal global priority value");
1648 return RADEON_CTX_PRIORITY_INVALID;
1649 }
1650 }
1651
1652 static int
1653 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1654 uint32_t queue_family_index, int idx,
1655 VkDeviceQueueCreateFlags flags,
1656 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1657 {
1658 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1659 queue->device = device;
1660 queue->queue_family_index = queue_family_index;
1661 queue->queue_idx = idx;
1662 queue->priority = radv_get_queue_global_priority(global_priority);
1663 queue->flags = flags;
1664
1665 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1666 if (!queue->hw_ctx)
1667 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1668
1669 return VK_SUCCESS;
1670 }
1671
1672 static void
1673 radv_queue_finish(struct radv_queue *queue)
1674 {
1675 if (queue->hw_ctx)
1676 queue->device->ws->ctx_destroy(queue->hw_ctx);
1677
1678 if (queue->initial_full_flush_preamble_cs)
1679 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1680 if (queue->initial_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1682 if (queue->continue_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1684 if (queue->descriptor_bo)
1685 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1686 if (queue->scratch_bo)
1687 queue->device->ws->buffer_destroy(queue->scratch_bo);
1688 if (queue->esgs_ring_bo)
1689 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1690 if (queue->gsvs_ring_bo)
1691 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1692 if (queue->tess_rings_bo)
1693 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1694 if (queue->compute_scratch_bo)
1695 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1696 }
1697
1698 static void
1699 radv_bo_list_init(struct radv_bo_list *bo_list)
1700 {
1701 pthread_mutex_init(&bo_list->mutex, NULL);
1702 bo_list->list.count = bo_list->capacity = 0;
1703 bo_list->list.bos = NULL;
1704 }
1705
1706 static void
1707 radv_bo_list_finish(struct radv_bo_list *bo_list)
1708 {
1709 free(bo_list->list.bos);
1710 pthread_mutex_destroy(&bo_list->mutex);
1711 }
1712
1713 static VkResult radv_bo_list_add(struct radv_device *device,
1714 struct radeon_winsys_bo *bo)
1715 {
1716 struct radv_bo_list *bo_list = &device->bo_list;
1717
1718 if (bo->is_local)
1719 return VK_SUCCESS;
1720
1721 if (unlikely(!device->use_global_bo_list))
1722 return VK_SUCCESS;
1723
1724 pthread_mutex_lock(&bo_list->mutex);
1725 if (bo_list->list.count == bo_list->capacity) {
1726 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1727 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1728
1729 if (!data) {
1730 pthread_mutex_unlock(&bo_list->mutex);
1731 return VK_ERROR_OUT_OF_HOST_MEMORY;
1732 }
1733
1734 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1735 bo_list->capacity = capacity;
1736 }
1737
1738 bo_list->list.bos[bo_list->list.count++] = bo;
1739 pthread_mutex_unlock(&bo_list->mutex);
1740 return VK_SUCCESS;
1741 }
1742
1743 static void radv_bo_list_remove(struct radv_device *device,
1744 struct radeon_winsys_bo *bo)
1745 {
1746 struct radv_bo_list *bo_list = &device->bo_list;
1747
1748 if (bo->is_local)
1749 return;
1750
1751 if (unlikely(!device->use_global_bo_list))
1752 return;
1753
1754 pthread_mutex_lock(&bo_list->mutex);
1755 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1756 if (bo_list->list.bos[i] == bo) {
1757 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1758 --bo_list->list.count;
1759 break;
1760 }
1761 }
1762 pthread_mutex_unlock(&bo_list->mutex);
1763 }
1764
1765 static void
1766 radv_device_init_gs_info(struct radv_device *device)
1767 {
1768 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1769 device->physical_device->rad_info.family);
1770 }
1771
1772 static int radv_get_device_extension_index(const char *name)
1773 {
1774 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1775 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1776 return i;
1777 }
1778 return -1;
1779 }
1780
1781 static int
1782 radv_get_int_debug_option(const char *name, int default_value)
1783 {
1784 const char *str;
1785 int result;
1786
1787 str = getenv(name);
1788 if (!str) {
1789 result = default_value;
1790 } else {
1791 char *endptr;
1792
1793 result = strtol(str, &endptr, 0);
1794 if (str == endptr) {
1795 /* No digits founs. */
1796 result = default_value;
1797 }
1798 }
1799
1800 return result;
1801 }
1802
1803 VkResult radv_CreateDevice(
1804 VkPhysicalDevice physicalDevice,
1805 const VkDeviceCreateInfo* pCreateInfo,
1806 const VkAllocationCallbacks* pAllocator,
1807 VkDevice* pDevice)
1808 {
1809 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1810 VkResult result;
1811 struct radv_device *device;
1812
1813 bool keep_shader_info = false;
1814
1815 /* Check enabled features */
1816 if (pCreateInfo->pEnabledFeatures) {
1817 VkPhysicalDeviceFeatures supported_features;
1818 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1819 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1820 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1821 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1822 for (uint32_t i = 0; i < num_features; i++) {
1823 if (enabled_feature[i] && !supported_feature[i])
1824 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1825 }
1826 }
1827
1828 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1829 sizeof(*device), 8,
1830 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1831 if (!device)
1832 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1833
1834 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1835 device->instance = physical_device->instance;
1836 device->physical_device = physical_device;
1837
1838 device->ws = physical_device->ws;
1839 if (pAllocator)
1840 device->alloc = *pAllocator;
1841 else
1842 device->alloc = physical_device->instance->alloc;
1843
1844 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1845 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1846 int index = radv_get_device_extension_index(ext_name);
1847 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1848 vk_free(&device->alloc, device);
1849 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1850 }
1851
1852 device->enabled_extensions.extensions[index] = true;
1853 }
1854
1855 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1856
1857 /* With update after bind we can't attach bo's to the command buffer
1858 * from the descriptor set anymore, so we have to use a global BO list.
1859 */
1860 device->use_global_bo_list =
1861 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1862 device->enabled_extensions.EXT_descriptor_indexing ||
1863 device->enabled_extensions.EXT_buffer_device_address;
1864
1865 mtx_init(&device->shader_slab_mutex, mtx_plain);
1866 list_inithead(&device->shader_slabs);
1867
1868 radv_bo_list_init(&device->bo_list);
1869
1870 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1871 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1872 uint32_t qfi = queue_create->queueFamilyIndex;
1873 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1874 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1875
1876 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1877
1878 device->queues[qfi] = vk_alloc(&device->alloc,
1879 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1880 if (!device->queues[qfi]) {
1881 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1882 goto fail;
1883 }
1884
1885 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1886
1887 device->queue_count[qfi] = queue_create->queueCount;
1888
1889 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1890 result = radv_queue_init(device, &device->queues[qfi][q],
1891 qfi, q, queue_create->flags,
1892 global_priority);
1893 if (result != VK_SUCCESS)
1894 goto fail;
1895 }
1896 }
1897
1898 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1899 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1900
1901 /* Disabled and not implemented for now. */
1902 device->dfsm_allowed = device->pbb_allowed &&
1903 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1904 device->physical_device->rad_info.family == CHIP_RAVEN2);
1905
1906 #ifdef ANDROID
1907 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1908 #endif
1909
1910 /* The maximum number of scratch waves. Scratch space isn't divided
1911 * evenly between CUs. The number is only a function of the number of CUs.
1912 * We can decrease the constant to decrease the scratch buffer size.
1913 *
1914 * sctx->scratch_waves must be >= the maximum possible size of
1915 * 1 threadgroup, so that the hw doesn't hang from being unable
1916 * to start any.
1917 *
1918 * The recommended value is 4 per CU at most. Higher numbers don't
1919 * bring much benefit, but they still occupy chip resources (think
1920 * async compute). I've seen ~2% performance difference between 4 and 32.
1921 */
1922 uint32_t max_threads_per_block = 2048;
1923 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1924 max_threads_per_block / 64);
1925
1926 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1927
1928 if (device->physical_device->rad_info.chip_class >= GFX7) {
1929 /* If the KMD allows it (there is a KMD hw register for it),
1930 * allow launching waves out-of-order.
1931 */
1932 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1933 }
1934
1935 radv_device_init_gs_info(device);
1936
1937 device->tess_offchip_block_dw_size =
1938 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1939 device->has_distributed_tess =
1940 device->physical_device->rad_info.chip_class >= GFX8 &&
1941 device->physical_device->rad_info.max_se >= 2;
1942
1943 if (getenv("RADV_TRACE_FILE")) {
1944 const char *filename = getenv("RADV_TRACE_FILE");
1945
1946 keep_shader_info = true;
1947
1948 if (!radv_init_trace(device))
1949 goto fail;
1950
1951 fprintf(stderr, "*****************************************************************************\n");
1952 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1953 fprintf(stderr, "*****************************************************************************\n");
1954
1955 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1956 radv_dump_enabled_options(device, stderr);
1957 }
1958
1959 device->keep_shader_info = keep_shader_info;
1960
1961 result = radv_device_init_meta(device);
1962 if (result != VK_SUCCESS)
1963 goto fail;
1964
1965 radv_device_init_msaa(device);
1966
1967 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1968 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1969 switch (family) {
1970 case RADV_QUEUE_GENERAL:
1971 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1972 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1973 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1974 break;
1975 case RADV_QUEUE_COMPUTE:
1976 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1977 radeon_emit(device->empty_cs[family], 0);
1978 break;
1979 }
1980 device->ws->cs_finalize(device->empty_cs[family]);
1981 }
1982
1983 if (device->physical_device->rad_info.chip_class >= GFX7)
1984 cik_create_gfx_config(device);
1985
1986 VkPipelineCacheCreateInfo ci;
1987 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1988 ci.pNext = NULL;
1989 ci.flags = 0;
1990 ci.pInitialData = NULL;
1991 ci.initialDataSize = 0;
1992 VkPipelineCache pc;
1993 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1994 &ci, NULL, &pc);
1995 if (result != VK_SUCCESS)
1996 goto fail_meta;
1997
1998 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1999
2000 device->force_aniso =
2001 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2002 if (device->force_aniso >= 0) {
2003 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2004 1 << util_logbase2(device->force_aniso));
2005 }
2006
2007 *pDevice = radv_device_to_handle(device);
2008 return VK_SUCCESS;
2009
2010 fail_meta:
2011 radv_device_finish_meta(device);
2012 fail:
2013 radv_bo_list_finish(&device->bo_list);
2014
2015 if (device->trace_bo)
2016 device->ws->buffer_destroy(device->trace_bo);
2017
2018 if (device->gfx_init)
2019 device->ws->buffer_destroy(device->gfx_init);
2020
2021 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2022 for (unsigned q = 0; q < device->queue_count[i]; q++)
2023 radv_queue_finish(&device->queues[i][q]);
2024 if (device->queue_count[i])
2025 vk_free(&device->alloc, device->queues[i]);
2026 }
2027
2028 vk_free(&device->alloc, device);
2029 return result;
2030 }
2031
2032 void radv_DestroyDevice(
2033 VkDevice _device,
2034 const VkAllocationCallbacks* pAllocator)
2035 {
2036 RADV_FROM_HANDLE(radv_device, device, _device);
2037
2038 if (!device)
2039 return;
2040
2041 if (device->trace_bo)
2042 device->ws->buffer_destroy(device->trace_bo);
2043
2044 if (device->gfx_init)
2045 device->ws->buffer_destroy(device->gfx_init);
2046
2047 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2048 for (unsigned q = 0; q < device->queue_count[i]; q++)
2049 radv_queue_finish(&device->queues[i][q]);
2050 if (device->queue_count[i])
2051 vk_free(&device->alloc, device->queues[i]);
2052 if (device->empty_cs[i])
2053 device->ws->cs_destroy(device->empty_cs[i]);
2054 }
2055 radv_device_finish_meta(device);
2056
2057 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2058 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2059
2060 radv_destroy_shader_slabs(device);
2061
2062 radv_bo_list_finish(&device->bo_list);
2063 vk_free(&device->alloc, device);
2064 }
2065
2066 VkResult radv_EnumerateInstanceLayerProperties(
2067 uint32_t* pPropertyCount,
2068 VkLayerProperties* pProperties)
2069 {
2070 if (pProperties == NULL) {
2071 *pPropertyCount = 0;
2072 return VK_SUCCESS;
2073 }
2074
2075 /* None supported at this time */
2076 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2077 }
2078
2079 VkResult radv_EnumerateDeviceLayerProperties(
2080 VkPhysicalDevice physicalDevice,
2081 uint32_t* pPropertyCount,
2082 VkLayerProperties* pProperties)
2083 {
2084 if (pProperties == NULL) {
2085 *pPropertyCount = 0;
2086 return VK_SUCCESS;
2087 }
2088
2089 /* None supported at this time */
2090 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2091 }
2092
2093 void radv_GetDeviceQueue2(
2094 VkDevice _device,
2095 const VkDeviceQueueInfo2* pQueueInfo,
2096 VkQueue* pQueue)
2097 {
2098 RADV_FROM_HANDLE(radv_device, device, _device);
2099 struct radv_queue *queue;
2100
2101 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2102 if (pQueueInfo->flags != queue->flags) {
2103 /* From the Vulkan 1.1.70 spec:
2104 *
2105 * "The queue returned by vkGetDeviceQueue2 must have the same
2106 * flags value from this structure as that used at device
2107 * creation time in a VkDeviceQueueCreateInfo instance. If no
2108 * matching flags were specified at device creation time then
2109 * pQueue will return VK_NULL_HANDLE."
2110 */
2111 *pQueue = VK_NULL_HANDLE;
2112 return;
2113 }
2114
2115 *pQueue = radv_queue_to_handle(queue);
2116 }
2117
2118 void radv_GetDeviceQueue(
2119 VkDevice _device,
2120 uint32_t queueFamilyIndex,
2121 uint32_t queueIndex,
2122 VkQueue* pQueue)
2123 {
2124 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2125 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2126 .queueFamilyIndex = queueFamilyIndex,
2127 .queueIndex = queueIndex
2128 };
2129
2130 radv_GetDeviceQueue2(_device, &info, pQueue);
2131 }
2132
2133 static void
2134 fill_geom_tess_rings(struct radv_queue *queue,
2135 uint32_t *map,
2136 bool add_sample_positions,
2137 uint32_t esgs_ring_size,
2138 struct radeon_winsys_bo *esgs_ring_bo,
2139 uint32_t gsvs_ring_size,
2140 struct radeon_winsys_bo *gsvs_ring_bo,
2141 uint32_t tess_factor_ring_size,
2142 uint32_t tess_offchip_ring_offset,
2143 uint32_t tess_offchip_ring_size,
2144 struct radeon_winsys_bo *tess_rings_bo)
2145 {
2146 uint32_t *desc = &map[4];
2147
2148 if (esgs_ring_bo) {
2149 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2150
2151 /* stride 0, num records - size, add tid, swizzle, elsize4,
2152 index stride 64 */
2153 desc[0] = esgs_va;
2154 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2155 S_008F04_STRIDE(0) |
2156 S_008F04_SWIZZLE_ENABLE(true);
2157 desc[2] = esgs_ring_size;
2158 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2159 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2160 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2161 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2162 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2163 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2164 S_008F0C_ELEMENT_SIZE(1) |
2165 S_008F0C_INDEX_STRIDE(3) |
2166 S_008F0C_ADD_TID_ENABLE(true);
2167
2168 /* GS entry for ES->GS ring */
2169 /* stride 0, num records - size, elsize0,
2170 index stride 0 */
2171 desc[4] = esgs_va;
2172 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2173 S_008F04_STRIDE(0) |
2174 S_008F04_SWIZZLE_ENABLE(false);
2175 desc[6] = esgs_ring_size;
2176 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2177 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2178 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2179 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2180 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2181 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2182 S_008F0C_ELEMENT_SIZE(0) |
2183 S_008F0C_INDEX_STRIDE(0) |
2184 S_008F0C_ADD_TID_ENABLE(false);
2185 }
2186
2187 desc += 8;
2188
2189 if (gsvs_ring_bo) {
2190 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2191
2192 /* VS entry for GS->VS ring */
2193 /* stride 0, num records - size, elsize0,
2194 index stride 0 */
2195 desc[0] = gsvs_va;
2196 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2197 S_008F04_STRIDE(0) |
2198 S_008F04_SWIZZLE_ENABLE(false);
2199 desc[2] = gsvs_ring_size;
2200 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2201 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2202 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2203 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2204 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2205 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2206 S_008F0C_ELEMENT_SIZE(0) |
2207 S_008F0C_INDEX_STRIDE(0) |
2208 S_008F0C_ADD_TID_ENABLE(false);
2209
2210 /* stride gsvs_itemsize, num records 64
2211 elsize 4, index stride 16 */
2212 /* shader will patch stride and desc[2] */
2213 desc[4] = gsvs_va;
2214 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2215 S_008F04_STRIDE(0) |
2216 S_008F04_SWIZZLE_ENABLE(true);
2217 desc[6] = 0;
2218 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2219 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2220 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2221 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2222 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2223 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2224 S_008F0C_ELEMENT_SIZE(1) |
2225 S_008F0C_INDEX_STRIDE(1) |
2226 S_008F0C_ADD_TID_ENABLE(true);
2227 }
2228
2229 desc += 8;
2230
2231 if (tess_rings_bo) {
2232 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2233 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2234
2235 desc[0] = tess_va;
2236 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2237 S_008F04_STRIDE(0) |
2238 S_008F04_SWIZZLE_ENABLE(false);
2239 desc[2] = tess_factor_ring_size;
2240 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2241 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2242 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2243 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2244 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2245 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2246 S_008F0C_ELEMENT_SIZE(0) |
2247 S_008F0C_INDEX_STRIDE(0) |
2248 S_008F0C_ADD_TID_ENABLE(false);
2249
2250 desc[4] = tess_offchip_va;
2251 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2252 S_008F04_STRIDE(0) |
2253 S_008F04_SWIZZLE_ENABLE(false);
2254 desc[6] = tess_offchip_ring_size;
2255 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2256 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2257 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2258 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2259 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2260 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2261 S_008F0C_ELEMENT_SIZE(0) |
2262 S_008F0C_INDEX_STRIDE(0) |
2263 S_008F0C_ADD_TID_ENABLE(false);
2264 }
2265
2266 desc += 8;
2267
2268 if (add_sample_positions) {
2269 /* add sample positions after all rings */
2270 memcpy(desc, queue->device->sample_locations_1x, 8);
2271 desc += 2;
2272 memcpy(desc, queue->device->sample_locations_2x, 16);
2273 desc += 4;
2274 memcpy(desc, queue->device->sample_locations_4x, 32);
2275 desc += 8;
2276 memcpy(desc, queue->device->sample_locations_8x, 64);
2277 }
2278 }
2279
2280 static unsigned
2281 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2282 {
2283 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2284 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2285 device->physical_device->rad_info.family != CHIP_STONEY;
2286 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2287 unsigned max_offchip_buffers;
2288 unsigned offchip_granularity;
2289 unsigned hs_offchip_param;
2290
2291 /*
2292 * Per RadeonSI:
2293 * This must be one less than the maximum number due to a hw limitation.
2294 * Various hardware bugs need thGFX7
2295 *
2296 * Per AMDVLK:
2297 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2298 * Gfx7 should limit max_offchip_buffers to 508
2299 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2300 *
2301 * Follow AMDVLK here.
2302 */
2303 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2304 device->physical_device->rad_info.chip_class == GFX7 ||
2305 device->physical_device->rad_info.chip_class == GFX6)
2306 --max_offchip_buffers_per_se;
2307
2308 max_offchip_buffers = max_offchip_buffers_per_se *
2309 device->physical_device->rad_info.max_se;
2310
2311 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2312 * around by setting 4K granularity.
2313 */
2314 if (device->tess_offchip_block_dw_size == 4096) {
2315 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2316 offchip_granularity = V_03093C_X_4K_DWORDS;
2317 } else {
2318 assert(device->tess_offchip_block_dw_size == 8192);
2319 offchip_granularity = V_03093C_X_8K_DWORDS;
2320 }
2321
2322 switch (device->physical_device->rad_info.chip_class) {
2323 case GFX6:
2324 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2325 break;
2326 case GFX7:
2327 case GFX8:
2328 case GFX9:
2329 default:
2330 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2331 break;
2332 }
2333
2334 *max_offchip_buffers_p = max_offchip_buffers;
2335 if (device->physical_device->rad_info.chip_class >= GFX7) {
2336 if (device->physical_device->rad_info.chip_class >= GFX8)
2337 --max_offchip_buffers;
2338 hs_offchip_param =
2339 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2340 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2341 } else {
2342 hs_offchip_param =
2343 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2344 }
2345 return hs_offchip_param;
2346 }
2347
2348 static void
2349 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2350 struct radeon_winsys_bo *esgs_ring_bo,
2351 uint32_t esgs_ring_size,
2352 struct radeon_winsys_bo *gsvs_ring_bo,
2353 uint32_t gsvs_ring_size)
2354 {
2355 if (!esgs_ring_bo && !gsvs_ring_bo)
2356 return;
2357
2358 if (esgs_ring_bo)
2359 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2360
2361 if (gsvs_ring_bo)
2362 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2363
2364 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2365 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2366 radeon_emit(cs, esgs_ring_size >> 8);
2367 radeon_emit(cs, gsvs_ring_size >> 8);
2368 } else {
2369 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2370 radeon_emit(cs, esgs_ring_size >> 8);
2371 radeon_emit(cs, gsvs_ring_size >> 8);
2372 }
2373 }
2374
2375 static void
2376 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2377 unsigned hs_offchip_param, unsigned tf_ring_size,
2378 struct radeon_winsys_bo *tess_rings_bo)
2379 {
2380 uint64_t tf_va;
2381
2382 if (!tess_rings_bo)
2383 return;
2384
2385 tf_va = radv_buffer_get_va(tess_rings_bo);
2386
2387 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2388
2389 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2390 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2391 S_030938_SIZE(tf_ring_size / 4));
2392 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2393 tf_va >> 8);
2394
2395 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2396 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2397 S_030984_BASE_HI(tf_va >> 40));
2398 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2399 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2400 S_030944_BASE_HI(tf_va >> 40));
2401 }
2402 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2403 hs_offchip_param);
2404 } else {
2405 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2406 S_008988_SIZE(tf_ring_size / 4));
2407 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2408 tf_va >> 8);
2409 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2410 hs_offchip_param);
2411 }
2412 }
2413
2414 static void
2415 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2416 struct radeon_winsys_bo *compute_scratch_bo)
2417 {
2418 uint64_t scratch_va;
2419
2420 if (!compute_scratch_bo)
2421 return;
2422
2423 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2424
2425 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2426
2427 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2428 radeon_emit(cs, scratch_va);
2429 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2430 S_008F04_SWIZZLE_ENABLE(1));
2431 }
2432
2433 static void
2434 radv_emit_global_shader_pointers(struct radv_queue *queue,
2435 struct radeon_cmdbuf *cs,
2436 struct radeon_winsys_bo *descriptor_bo)
2437 {
2438 uint64_t va;
2439
2440 if (!descriptor_bo)
2441 return;
2442
2443 va = radv_buffer_get_va(descriptor_bo);
2444
2445 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2446
2447 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2448 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2449 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2450 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2451 R_00B430_SPI_SHADER_USER_DATA_HS_0};
2452
2453 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2454 radv_emit_shader_pointer(queue->device, cs, regs[i],
2455 va, true);
2456 }
2457 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2458 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2459 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2460 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2461 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2462
2463 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2464 radv_emit_shader_pointer(queue->device, cs, regs[i],
2465 va, true);
2466 }
2467 } else {
2468 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2469 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2470 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2471 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2472 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2473 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2474
2475 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2476 radv_emit_shader_pointer(queue->device, cs, regs[i],
2477 va, true);
2478 }
2479 }
2480 }
2481
2482 static void
2483 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2484 {
2485 struct radv_device *device = queue->device;
2486
2487 if (device->gfx_init) {
2488 uint64_t va = radv_buffer_get_va(device->gfx_init);
2489
2490 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2491 radeon_emit(cs, va);
2492 radeon_emit(cs, va >> 32);
2493 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2494
2495 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2496 } else {
2497 struct radv_physical_device *physical_device = device->physical_device;
2498 si_emit_graphics(physical_device, cs);
2499 }
2500 }
2501
2502 static void
2503 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2504 {
2505 struct radv_physical_device *physical_device = queue->device->physical_device;
2506 si_emit_compute(physical_device, cs);
2507 }
2508
2509 static VkResult
2510 radv_get_preamble_cs(struct radv_queue *queue,
2511 uint32_t scratch_size,
2512 uint32_t compute_scratch_size,
2513 uint32_t esgs_ring_size,
2514 uint32_t gsvs_ring_size,
2515 bool needs_tess_rings,
2516 bool needs_sample_positions,
2517 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2518 struct radeon_cmdbuf **initial_preamble_cs,
2519 struct radeon_cmdbuf **continue_preamble_cs)
2520 {
2521 struct radeon_winsys_bo *scratch_bo = NULL;
2522 struct radeon_winsys_bo *descriptor_bo = NULL;
2523 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2524 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2525 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2526 struct radeon_winsys_bo *tess_rings_bo = NULL;
2527 struct radeon_cmdbuf *dest_cs[3] = {0};
2528 bool add_tess_rings = false, add_sample_positions = false;
2529 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2530 unsigned max_offchip_buffers;
2531 unsigned hs_offchip_param = 0;
2532 unsigned tess_offchip_ring_offset;
2533 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2534 if (!queue->has_tess_rings) {
2535 if (needs_tess_rings)
2536 add_tess_rings = true;
2537 }
2538 if (!queue->has_sample_positions) {
2539 if (needs_sample_positions)
2540 add_sample_positions = true;
2541 }
2542 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2543 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2544 &max_offchip_buffers);
2545 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2546 tess_offchip_ring_size = max_offchip_buffers *
2547 queue->device->tess_offchip_block_dw_size * 4;
2548
2549 if (scratch_size <= queue->scratch_size &&
2550 compute_scratch_size <= queue->compute_scratch_size &&
2551 esgs_ring_size <= queue->esgs_ring_size &&
2552 gsvs_ring_size <= queue->gsvs_ring_size &&
2553 !add_tess_rings && !add_sample_positions &&
2554 queue->initial_preamble_cs) {
2555 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2556 *initial_preamble_cs = queue->initial_preamble_cs;
2557 *continue_preamble_cs = queue->continue_preamble_cs;
2558 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2559 *continue_preamble_cs = NULL;
2560 return VK_SUCCESS;
2561 }
2562
2563 if (scratch_size > queue->scratch_size) {
2564 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2565 scratch_size,
2566 4096,
2567 RADEON_DOMAIN_VRAM,
2568 ring_bo_flags,
2569 RADV_BO_PRIORITY_SCRATCH);
2570 if (!scratch_bo)
2571 goto fail;
2572 } else
2573 scratch_bo = queue->scratch_bo;
2574
2575 if (compute_scratch_size > queue->compute_scratch_size) {
2576 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2577 compute_scratch_size,
2578 4096,
2579 RADEON_DOMAIN_VRAM,
2580 ring_bo_flags,
2581 RADV_BO_PRIORITY_SCRATCH);
2582 if (!compute_scratch_bo)
2583 goto fail;
2584
2585 } else
2586 compute_scratch_bo = queue->compute_scratch_bo;
2587
2588 if (esgs_ring_size > queue->esgs_ring_size) {
2589 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2590 esgs_ring_size,
2591 4096,
2592 RADEON_DOMAIN_VRAM,
2593 ring_bo_flags,
2594 RADV_BO_PRIORITY_SCRATCH);
2595 if (!esgs_ring_bo)
2596 goto fail;
2597 } else {
2598 esgs_ring_bo = queue->esgs_ring_bo;
2599 esgs_ring_size = queue->esgs_ring_size;
2600 }
2601
2602 if (gsvs_ring_size > queue->gsvs_ring_size) {
2603 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2604 gsvs_ring_size,
2605 4096,
2606 RADEON_DOMAIN_VRAM,
2607 ring_bo_flags,
2608 RADV_BO_PRIORITY_SCRATCH);
2609 if (!gsvs_ring_bo)
2610 goto fail;
2611 } else {
2612 gsvs_ring_bo = queue->gsvs_ring_bo;
2613 gsvs_ring_size = queue->gsvs_ring_size;
2614 }
2615
2616 if (add_tess_rings) {
2617 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2618 tess_offchip_ring_offset + tess_offchip_ring_size,
2619 256,
2620 RADEON_DOMAIN_VRAM,
2621 ring_bo_flags,
2622 RADV_BO_PRIORITY_SCRATCH);
2623 if (!tess_rings_bo)
2624 goto fail;
2625 } else {
2626 tess_rings_bo = queue->tess_rings_bo;
2627 }
2628
2629 if (scratch_bo != queue->scratch_bo ||
2630 esgs_ring_bo != queue->esgs_ring_bo ||
2631 gsvs_ring_bo != queue->gsvs_ring_bo ||
2632 tess_rings_bo != queue->tess_rings_bo ||
2633 add_sample_positions) {
2634 uint32_t size = 0;
2635 if (gsvs_ring_bo || esgs_ring_bo ||
2636 tess_rings_bo || add_sample_positions) {
2637 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2638 if (add_sample_positions)
2639 size += 128; /* 64+32+16+8 = 120 bytes */
2640 }
2641 else if (scratch_bo)
2642 size = 8; /* 2 dword */
2643
2644 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2645 size,
2646 4096,
2647 RADEON_DOMAIN_VRAM,
2648 RADEON_FLAG_CPU_ACCESS |
2649 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2650 RADEON_FLAG_READ_ONLY,
2651 RADV_BO_PRIORITY_DESCRIPTOR);
2652 if (!descriptor_bo)
2653 goto fail;
2654 } else
2655 descriptor_bo = queue->descriptor_bo;
2656
2657 if (descriptor_bo != queue->descriptor_bo) {
2658 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2659
2660 if (scratch_bo) {
2661 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2662 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2663 S_008F04_SWIZZLE_ENABLE(1);
2664 map[0] = scratch_va;
2665 map[1] = rsrc1;
2666 }
2667
2668 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2669 fill_geom_tess_rings(queue, map, add_sample_positions,
2670 esgs_ring_size, esgs_ring_bo,
2671 gsvs_ring_size, gsvs_ring_bo,
2672 tess_factor_ring_size,
2673 tess_offchip_ring_offset,
2674 tess_offchip_ring_size,
2675 tess_rings_bo);
2676
2677 queue->device->ws->buffer_unmap(descriptor_bo);
2678 }
2679
2680 for(int i = 0; i < 3; ++i) {
2681 struct radeon_cmdbuf *cs = NULL;
2682 cs = queue->device->ws->cs_create(queue->device->ws,
2683 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2684 if (!cs)
2685 goto fail;
2686
2687 dest_cs[i] = cs;
2688
2689 if (scratch_bo)
2690 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2691
2692 /* Emit initial configuration. */
2693 switch (queue->queue_family_index) {
2694 case RADV_QUEUE_GENERAL:
2695 radv_init_graphics_state(cs, queue);
2696 break;
2697 case RADV_QUEUE_COMPUTE:
2698 radv_init_compute_state(cs, queue);
2699 break;
2700 case RADV_QUEUE_TRANSFER:
2701 break;
2702 }
2703
2704 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2705 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2706 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2707 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2708 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2709 }
2710
2711 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2712 gsvs_ring_bo, gsvs_ring_size);
2713 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2714 tess_factor_ring_size, tess_rings_bo);
2715 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2716 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2717
2718 if (i == 0) {
2719 si_cs_emit_cache_flush(cs,
2720 queue->device->physical_device->rad_info.chip_class,
2721 NULL, 0,
2722 queue->queue_family_index == RING_COMPUTE &&
2723 queue->device->physical_device->rad_info.chip_class >= GFX7,
2724 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2725 RADV_CMD_FLAG_INV_ICACHE |
2726 RADV_CMD_FLAG_INV_SCACHE |
2727 RADV_CMD_FLAG_INV_VCACHE |
2728 RADV_CMD_FLAG_INV_L2 |
2729 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2730 } else if (i == 1) {
2731 si_cs_emit_cache_flush(cs,
2732 queue->device->physical_device->rad_info.chip_class,
2733 NULL, 0,
2734 queue->queue_family_index == RING_COMPUTE &&
2735 queue->device->physical_device->rad_info.chip_class >= GFX7,
2736 RADV_CMD_FLAG_INV_ICACHE |
2737 RADV_CMD_FLAG_INV_SCACHE |
2738 RADV_CMD_FLAG_INV_VCACHE |
2739 RADV_CMD_FLAG_INV_L2 |
2740 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2741 }
2742
2743 if (!queue->device->ws->cs_finalize(cs))
2744 goto fail;
2745 }
2746
2747 if (queue->initial_full_flush_preamble_cs)
2748 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2749
2750 if (queue->initial_preamble_cs)
2751 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2752
2753 if (queue->continue_preamble_cs)
2754 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2755
2756 queue->initial_full_flush_preamble_cs = dest_cs[0];
2757 queue->initial_preamble_cs = dest_cs[1];
2758 queue->continue_preamble_cs = dest_cs[2];
2759
2760 if (scratch_bo != queue->scratch_bo) {
2761 if (queue->scratch_bo)
2762 queue->device->ws->buffer_destroy(queue->scratch_bo);
2763 queue->scratch_bo = scratch_bo;
2764 queue->scratch_size = scratch_size;
2765 }
2766
2767 if (compute_scratch_bo != queue->compute_scratch_bo) {
2768 if (queue->compute_scratch_bo)
2769 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2770 queue->compute_scratch_bo = compute_scratch_bo;
2771 queue->compute_scratch_size = compute_scratch_size;
2772 }
2773
2774 if (esgs_ring_bo != queue->esgs_ring_bo) {
2775 if (queue->esgs_ring_bo)
2776 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2777 queue->esgs_ring_bo = esgs_ring_bo;
2778 queue->esgs_ring_size = esgs_ring_size;
2779 }
2780
2781 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2782 if (queue->gsvs_ring_bo)
2783 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2784 queue->gsvs_ring_bo = gsvs_ring_bo;
2785 queue->gsvs_ring_size = gsvs_ring_size;
2786 }
2787
2788 if (tess_rings_bo != queue->tess_rings_bo) {
2789 queue->tess_rings_bo = tess_rings_bo;
2790 queue->has_tess_rings = true;
2791 }
2792
2793 if (descriptor_bo != queue->descriptor_bo) {
2794 if (queue->descriptor_bo)
2795 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2796
2797 queue->descriptor_bo = descriptor_bo;
2798 }
2799
2800 if (add_sample_positions)
2801 queue->has_sample_positions = true;
2802
2803 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2804 *initial_preamble_cs = queue->initial_preamble_cs;
2805 *continue_preamble_cs = queue->continue_preamble_cs;
2806 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2807 *continue_preamble_cs = NULL;
2808 return VK_SUCCESS;
2809 fail:
2810 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2811 if (dest_cs[i])
2812 queue->device->ws->cs_destroy(dest_cs[i]);
2813 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2814 queue->device->ws->buffer_destroy(descriptor_bo);
2815 if (scratch_bo && scratch_bo != queue->scratch_bo)
2816 queue->device->ws->buffer_destroy(scratch_bo);
2817 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2818 queue->device->ws->buffer_destroy(compute_scratch_bo);
2819 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2820 queue->device->ws->buffer_destroy(esgs_ring_bo);
2821 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2822 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2823 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2824 queue->device->ws->buffer_destroy(tess_rings_bo);
2825 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2826 }
2827
2828 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2829 struct radv_winsys_sem_counts *counts,
2830 int num_sems,
2831 const VkSemaphore *sems,
2832 VkFence _fence,
2833 bool reset_temp)
2834 {
2835 int syncobj_idx = 0, sem_idx = 0;
2836
2837 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2838 return VK_SUCCESS;
2839
2840 for (uint32_t i = 0; i < num_sems; i++) {
2841 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2842
2843 if (sem->temp_syncobj || sem->syncobj)
2844 counts->syncobj_count++;
2845 else
2846 counts->sem_count++;
2847 }
2848
2849 if (_fence != VK_NULL_HANDLE) {
2850 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2851 if (fence->temp_syncobj || fence->syncobj)
2852 counts->syncobj_count++;
2853 }
2854
2855 if (counts->syncobj_count) {
2856 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2857 if (!counts->syncobj)
2858 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2859 }
2860
2861 if (counts->sem_count) {
2862 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2863 if (!counts->sem) {
2864 free(counts->syncobj);
2865 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2866 }
2867 }
2868
2869 for (uint32_t i = 0; i < num_sems; i++) {
2870 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2871
2872 if (sem->temp_syncobj) {
2873 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2874 }
2875 else if (sem->syncobj)
2876 counts->syncobj[syncobj_idx++] = sem->syncobj;
2877 else {
2878 assert(sem->sem);
2879 counts->sem[sem_idx++] = sem->sem;
2880 }
2881 }
2882
2883 if (_fence != VK_NULL_HANDLE) {
2884 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2885 if (fence->temp_syncobj)
2886 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2887 else if (fence->syncobj)
2888 counts->syncobj[syncobj_idx++] = fence->syncobj;
2889 }
2890
2891 return VK_SUCCESS;
2892 }
2893
2894 static void
2895 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2896 {
2897 free(sem_info->wait.syncobj);
2898 free(sem_info->wait.sem);
2899 free(sem_info->signal.syncobj);
2900 free(sem_info->signal.sem);
2901 }
2902
2903
2904 static void radv_free_temp_syncobjs(struct radv_device *device,
2905 int num_sems,
2906 const VkSemaphore *sems)
2907 {
2908 for (uint32_t i = 0; i < num_sems; i++) {
2909 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2910
2911 if (sem->temp_syncobj) {
2912 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2913 sem->temp_syncobj = 0;
2914 }
2915 }
2916 }
2917
2918 static VkResult
2919 radv_alloc_sem_info(struct radv_instance *instance,
2920 struct radv_winsys_sem_info *sem_info,
2921 int num_wait_sems,
2922 const VkSemaphore *wait_sems,
2923 int num_signal_sems,
2924 const VkSemaphore *signal_sems,
2925 VkFence fence)
2926 {
2927 VkResult ret;
2928 memset(sem_info, 0, sizeof(*sem_info));
2929
2930 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2931 if (ret)
2932 return ret;
2933 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2934 if (ret)
2935 radv_free_sem_info(sem_info);
2936
2937 /* caller can override these */
2938 sem_info->cs_emit_wait = true;
2939 sem_info->cs_emit_signal = true;
2940 return ret;
2941 }
2942
2943 /* Signals fence as soon as all the work currently put on queue is done. */
2944 static VkResult radv_signal_fence(struct radv_queue *queue,
2945 struct radv_fence *fence)
2946 {
2947 int ret;
2948 VkResult result;
2949 struct radv_winsys_sem_info sem_info;
2950
2951 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2952 radv_fence_to_handle(fence));
2953 if (result != VK_SUCCESS)
2954 return result;
2955
2956 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2957 &queue->device->empty_cs[queue->queue_family_index],
2958 1, NULL, NULL, &sem_info, NULL,
2959 false, fence->fence);
2960 radv_free_sem_info(&sem_info);
2961
2962 if (ret)
2963 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2964
2965 return VK_SUCCESS;
2966 }
2967
2968 VkResult radv_QueueSubmit(
2969 VkQueue _queue,
2970 uint32_t submitCount,
2971 const VkSubmitInfo* pSubmits,
2972 VkFence _fence)
2973 {
2974 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2975 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2976 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2977 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2978 int ret;
2979 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2980 uint32_t scratch_size = 0;
2981 uint32_t compute_scratch_size = 0;
2982 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2983 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2984 VkResult result;
2985 bool fence_emitted = false;
2986 bool tess_rings_needed = false;
2987 bool sample_positions_needed = false;
2988
2989 /* Do this first so failing to allocate scratch buffers can't result in
2990 * partially executed submissions. */
2991 for (uint32_t i = 0; i < submitCount; i++) {
2992 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2993 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2994 pSubmits[i].pCommandBuffers[j]);
2995
2996 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2997 compute_scratch_size = MAX2(compute_scratch_size,
2998 cmd_buffer->compute_scratch_size_needed);
2999 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3000 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3001 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3002 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3003 }
3004 }
3005
3006 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3007 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3008 sample_positions_needed, &initial_flush_preamble_cs,
3009 &initial_preamble_cs, &continue_preamble_cs);
3010 if (result != VK_SUCCESS)
3011 return result;
3012
3013 for (uint32_t i = 0; i < submitCount; i++) {
3014 struct radeon_cmdbuf **cs_array;
3015 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3016 bool can_patch = true;
3017 uint32_t advance;
3018 struct radv_winsys_sem_info sem_info;
3019
3020 result = radv_alloc_sem_info(queue->device->instance,
3021 &sem_info,
3022 pSubmits[i].waitSemaphoreCount,
3023 pSubmits[i].pWaitSemaphores,
3024 pSubmits[i].signalSemaphoreCount,
3025 pSubmits[i].pSignalSemaphores,
3026 _fence);
3027 if (result != VK_SUCCESS)
3028 return result;
3029
3030 if (!pSubmits[i].commandBufferCount) {
3031 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3032 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3033 &queue->device->empty_cs[queue->queue_family_index],
3034 1, NULL, NULL,
3035 &sem_info, NULL,
3036 false, base_fence);
3037 if (ret) {
3038 radv_loge("failed to submit CS %d\n", i);
3039 abort();
3040 }
3041 fence_emitted = true;
3042 }
3043 radv_free_sem_info(&sem_info);
3044 continue;
3045 }
3046
3047 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3048 (pSubmits[i].commandBufferCount));
3049
3050 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3052 pSubmits[i].pCommandBuffers[j]);
3053 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3054
3055 cs_array[j] = cmd_buffer->cs;
3056 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3057 can_patch = false;
3058
3059 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3060 }
3061
3062 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3063 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3064 const struct radv_winsys_bo_list *bo_list = NULL;
3065
3066 advance = MIN2(max_cs_submission,
3067 pSubmits[i].commandBufferCount - j);
3068
3069 if (queue->device->trace_bo)
3070 *queue->device->trace_id_ptr = 0;
3071
3072 sem_info.cs_emit_wait = j == 0;
3073 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3074
3075 if (unlikely(queue->device->use_global_bo_list)) {
3076 pthread_mutex_lock(&queue->device->bo_list.mutex);
3077 bo_list = &queue->device->bo_list.list;
3078 }
3079
3080 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3081 advance, initial_preamble, continue_preamble_cs,
3082 &sem_info, bo_list,
3083 can_patch, base_fence);
3084
3085 if (unlikely(queue->device->use_global_bo_list))
3086 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3087
3088 if (ret) {
3089 radv_loge("failed to submit CS %d\n", i);
3090 abort();
3091 }
3092 fence_emitted = true;
3093 if (queue->device->trace_bo) {
3094 radv_check_gpu_hangs(queue, cs_array[j]);
3095 }
3096 }
3097
3098 radv_free_temp_syncobjs(queue->device,
3099 pSubmits[i].waitSemaphoreCount,
3100 pSubmits[i].pWaitSemaphores);
3101 radv_free_sem_info(&sem_info);
3102 free(cs_array);
3103 }
3104
3105 if (fence) {
3106 if (!fence_emitted) {
3107 result = radv_signal_fence(queue, fence);
3108 if (result != VK_SUCCESS)
3109 return result;
3110 }
3111 }
3112
3113 return VK_SUCCESS;
3114 }
3115
3116 VkResult radv_QueueWaitIdle(
3117 VkQueue _queue)
3118 {
3119 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3120
3121 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3122 radv_queue_family_to_ring(queue->queue_family_index),
3123 queue->queue_idx);
3124 return VK_SUCCESS;
3125 }
3126
3127 VkResult radv_DeviceWaitIdle(
3128 VkDevice _device)
3129 {
3130 RADV_FROM_HANDLE(radv_device, device, _device);
3131
3132 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3133 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3134 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3135 }
3136 }
3137 return VK_SUCCESS;
3138 }
3139
3140 VkResult radv_EnumerateInstanceExtensionProperties(
3141 const char* pLayerName,
3142 uint32_t* pPropertyCount,
3143 VkExtensionProperties* pProperties)
3144 {
3145 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3146
3147 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3148 if (radv_supported_instance_extensions.extensions[i]) {
3149 vk_outarray_append(&out, prop) {
3150 *prop = radv_instance_extensions[i];
3151 }
3152 }
3153 }
3154
3155 return vk_outarray_status(&out);
3156 }
3157
3158 VkResult radv_EnumerateDeviceExtensionProperties(
3159 VkPhysicalDevice physicalDevice,
3160 const char* pLayerName,
3161 uint32_t* pPropertyCount,
3162 VkExtensionProperties* pProperties)
3163 {
3164 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3165 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3166
3167 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3168 if (device->supported_extensions.extensions[i]) {
3169 vk_outarray_append(&out, prop) {
3170 *prop = radv_device_extensions[i];
3171 }
3172 }
3173 }
3174
3175 return vk_outarray_status(&out);
3176 }
3177
3178 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3179 VkInstance _instance,
3180 const char* pName)
3181 {
3182 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3183
3184 return radv_lookup_entrypoint_checked(pName,
3185 instance ? instance->apiVersion : 0,
3186 instance ? &instance->enabled_extensions : NULL,
3187 NULL);
3188 }
3189
3190 /* The loader wants us to expose a second GetInstanceProcAddr function
3191 * to work around certain LD_PRELOAD issues seen in apps.
3192 */
3193 PUBLIC
3194 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3195 VkInstance instance,
3196 const char* pName);
3197
3198 PUBLIC
3199 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3200 VkInstance instance,
3201 const char* pName)
3202 {
3203 return radv_GetInstanceProcAddr(instance, pName);
3204 }
3205
3206 PUBLIC
3207 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3208 VkInstance _instance,
3209 const char* pName);
3210
3211 PUBLIC
3212 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3213 VkInstance _instance,
3214 const char* pName)
3215 {
3216 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3217
3218 return radv_lookup_physical_device_entrypoint_checked(pName,
3219 instance ? instance->apiVersion : 0,
3220 instance ? &instance->enabled_extensions : NULL);
3221 }
3222
3223 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3224 VkDevice _device,
3225 const char* pName)
3226 {
3227 RADV_FROM_HANDLE(radv_device, device, _device);
3228
3229 return radv_lookup_entrypoint_checked(pName,
3230 device->instance->apiVersion,
3231 &device->instance->enabled_extensions,
3232 &device->enabled_extensions);
3233 }
3234
3235 bool radv_get_memory_fd(struct radv_device *device,
3236 struct radv_device_memory *memory,
3237 int *pFD)
3238 {
3239 struct radeon_bo_metadata metadata;
3240
3241 if (memory->image) {
3242 radv_init_metadata(device, memory->image, &metadata);
3243 device->ws->buffer_set_metadata(memory->bo, &metadata);
3244 }
3245
3246 return device->ws->buffer_get_fd(device->ws, memory->bo,
3247 pFD);
3248 }
3249
3250 static VkResult radv_alloc_memory(struct radv_device *device,
3251 const VkMemoryAllocateInfo* pAllocateInfo,
3252 const VkAllocationCallbacks* pAllocator,
3253 VkDeviceMemory* pMem)
3254 {
3255 struct radv_device_memory *mem;
3256 VkResult result;
3257 enum radeon_bo_domain domain;
3258 uint32_t flags = 0;
3259 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3260
3261 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3262
3263 if (pAllocateInfo->allocationSize == 0) {
3264 /* Apparently, this is allowed */
3265 *pMem = VK_NULL_HANDLE;
3266 return VK_SUCCESS;
3267 }
3268
3269 const VkImportMemoryFdInfoKHR *import_info =
3270 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3271 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3272 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3273 const VkExportMemoryAllocateInfo *export_info =
3274 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3275 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3276 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3277
3278 const struct wsi_memory_allocate_info *wsi_info =
3279 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3280
3281 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3282 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3283 if (mem == NULL)
3284 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3285
3286 if (wsi_info && wsi_info->implicit_sync)
3287 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3288
3289 if (dedicate_info) {
3290 mem->image = radv_image_from_handle(dedicate_info->image);
3291 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3292 } else {
3293 mem->image = NULL;
3294 mem->buffer = NULL;
3295 }
3296
3297 float priority_float = 0.5;
3298 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3299 vk_find_struct_const(pAllocateInfo->pNext,
3300 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3301 if (priority_ext)
3302 priority_float = priority_ext->priority;
3303
3304 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3305 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3306
3307 mem->user_ptr = NULL;
3308
3309 if (import_info) {
3310 assert(import_info->handleType ==
3311 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3312 import_info->handleType ==
3313 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3314 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3315 priority, NULL, NULL);
3316 if (!mem->bo) {
3317 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3318 goto fail;
3319 } else {
3320 close(import_info->fd);
3321 }
3322 } else if (host_ptr_info) {
3323 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3324 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3325 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3326 pAllocateInfo->allocationSize,
3327 priority);
3328 if (!mem->bo) {
3329 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3330 goto fail;
3331 } else {
3332 mem->user_ptr = host_ptr_info->pHostPointer;
3333 }
3334 } else {
3335 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3336 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3337 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3338 domain = RADEON_DOMAIN_GTT;
3339 else
3340 domain = RADEON_DOMAIN_VRAM;
3341
3342 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3343 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3344 else
3345 flags |= RADEON_FLAG_CPU_ACCESS;
3346
3347 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3348 flags |= RADEON_FLAG_GTT_WC;
3349
3350 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3351 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3352 if (device->use_global_bo_list) {
3353 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3354 }
3355 }
3356
3357 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3358 domain, flags, priority);
3359
3360 if (!mem->bo) {
3361 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3362 goto fail;
3363 }
3364 mem->type_index = mem_type_index;
3365 }
3366
3367 result = radv_bo_list_add(device, mem->bo);
3368 if (result != VK_SUCCESS)
3369 goto fail_bo;
3370
3371 *pMem = radv_device_memory_to_handle(mem);
3372
3373 return VK_SUCCESS;
3374
3375 fail_bo:
3376 device->ws->buffer_destroy(mem->bo);
3377 fail:
3378 vk_free2(&device->alloc, pAllocator, mem);
3379
3380 return result;
3381 }
3382
3383 VkResult radv_AllocateMemory(
3384 VkDevice _device,
3385 const VkMemoryAllocateInfo* pAllocateInfo,
3386 const VkAllocationCallbacks* pAllocator,
3387 VkDeviceMemory* pMem)
3388 {
3389 RADV_FROM_HANDLE(radv_device, device, _device);
3390 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3391 }
3392
3393 void radv_FreeMemory(
3394 VkDevice _device,
3395 VkDeviceMemory _mem,
3396 const VkAllocationCallbacks* pAllocator)
3397 {
3398 RADV_FROM_HANDLE(radv_device, device, _device);
3399 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3400
3401 if (mem == NULL)
3402 return;
3403
3404 radv_bo_list_remove(device, mem->bo);
3405 device->ws->buffer_destroy(mem->bo);
3406 mem->bo = NULL;
3407
3408 vk_free2(&device->alloc, pAllocator, mem);
3409 }
3410
3411 VkResult radv_MapMemory(
3412 VkDevice _device,
3413 VkDeviceMemory _memory,
3414 VkDeviceSize offset,
3415 VkDeviceSize size,
3416 VkMemoryMapFlags flags,
3417 void** ppData)
3418 {
3419 RADV_FROM_HANDLE(radv_device, device, _device);
3420 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3421
3422 if (mem == NULL) {
3423 *ppData = NULL;
3424 return VK_SUCCESS;
3425 }
3426
3427 if (mem->user_ptr)
3428 *ppData = mem->user_ptr;
3429 else
3430 *ppData = device->ws->buffer_map(mem->bo);
3431
3432 if (*ppData) {
3433 *ppData += offset;
3434 return VK_SUCCESS;
3435 }
3436
3437 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3438 }
3439
3440 void radv_UnmapMemory(
3441 VkDevice _device,
3442 VkDeviceMemory _memory)
3443 {
3444 RADV_FROM_HANDLE(radv_device, device, _device);
3445 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3446
3447 if (mem == NULL)
3448 return;
3449
3450 if (mem->user_ptr == NULL)
3451 device->ws->buffer_unmap(mem->bo);
3452 }
3453
3454 VkResult radv_FlushMappedMemoryRanges(
3455 VkDevice _device,
3456 uint32_t memoryRangeCount,
3457 const VkMappedMemoryRange* pMemoryRanges)
3458 {
3459 return VK_SUCCESS;
3460 }
3461
3462 VkResult radv_InvalidateMappedMemoryRanges(
3463 VkDevice _device,
3464 uint32_t memoryRangeCount,
3465 const VkMappedMemoryRange* pMemoryRanges)
3466 {
3467 return VK_SUCCESS;
3468 }
3469
3470 void radv_GetBufferMemoryRequirements(
3471 VkDevice _device,
3472 VkBuffer _buffer,
3473 VkMemoryRequirements* pMemoryRequirements)
3474 {
3475 RADV_FROM_HANDLE(radv_device, device, _device);
3476 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3477
3478 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3479
3480 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3481 pMemoryRequirements->alignment = 4096;
3482 else
3483 pMemoryRequirements->alignment = 16;
3484
3485 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3486 }
3487
3488 void radv_GetBufferMemoryRequirements2(
3489 VkDevice device,
3490 const VkBufferMemoryRequirementsInfo2 *pInfo,
3491 VkMemoryRequirements2 *pMemoryRequirements)
3492 {
3493 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3494 &pMemoryRequirements->memoryRequirements);
3495 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3496 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3497 switch (ext->sType) {
3498 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3499 VkMemoryDedicatedRequirements *req =
3500 (VkMemoryDedicatedRequirements *) ext;
3501 req->requiresDedicatedAllocation = buffer->shareable;
3502 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3503 break;
3504 }
3505 default:
3506 break;
3507 }
3508 }
3509 }
3510
3511 void radv_GetImageMemoryRequirements(
3512 VkDevice _device,
3513 VkImage _image,
3514 VkMemoryRequirements* pMemoryRequirements)
3515 {
3516 RADV_FROM_HANDLE(radv_device, device, _device);
3517 RADV_FROM_HANDLE(radv_image, image, _image);
3518
3519 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3520
3521 pMemoryRequirements->size = image->size;
3522 pMemoryRequirements->alignment = image->alignment;
3523 }
3524
3525 void radv_GetImageMemoryRequirements2(
3526 VkDevice device,
3527 const VkImageMemoryRequirementsInfo2 *pInfo,
3528 VkMemoryRequirements2 *pMemoryRequirements)
3529 {
3530 radv_GetImageMemoryRequirements(device, pInfo->image,
3531 &pMemoryRequirements->memoryRequirements);
3532
3533 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3534
3535 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3536 switch (ext->sType) {
3537 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3538 VkMemoryDedicatedRequirements *req =
3539 (VkMemoryDedicatedRequirements *) ext;
3540 req->requiresDedicatedAllocation = image->shareable;
3541 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3542 break;
3543 }
3544 default:
3545 break;
3546 }
3547 }
3548 }
3549
3550 void radv_GetImageSparseMemoryRequirements(
3551 VkDevice device,
3552 VkImage image,
3553 uint32_t* pSparseMemoryRequirementCount,
3554 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3555 {
3556 stub();
3557 }
3558
3559 void radv_GetImageSparseMemoryRequirements2(
3560 VkDevice device,
3561 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3562 uint32_t* pSparseMemoryRequirementCount,
3563 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3564 {
3565 stub();
3566 }
3567
3568 void radv_GetDeviceMemoryCommitment(
3569 VkDevice device,
3570 VkDeviceMemory memory,
3571 VkDeviceSize* pCommittedMemoryInBytes)
3572 {
3573 *pCommittedMemoryInBytes = 0;
3574 }
3575
3576 VkResult radv_BindBufferMemory2(VkDevice device,
3577 uint32_t bindInfoCount,
3578 const VkBindBufferMemoryInfo *pBindInfos)
3579 {
3580 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3581 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3582 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3583
3584 if (mem) {
3585 buffer->bo = mem->bo;
3586 buffer->offset = pBindInfos[i].memoryOffset;
3587 } else {
3588 buffer->bo = NULL;
3589 }
3590 }
3591 return VK_SUCCESS;
3592 }
3593
3594 VkResult radv_BindBufferMemory(
3595 VkDevice device,
3596 VkBuffer buffer,
3597 VkDeviceMemory memory,
3598 VkDeviceSize memoryOffset)
3599 {
3600 const VkBindBufferMemoryInfo info = {
3601 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3602 .buffer = buffer,
3603 .memory = memory,
3604 .memoryOffset = memoryOffset
3605 };
3606
3607 return radv_BindBufferMemory2(device, 1, &info);
3608 }
3609
3610 VkResult radv_BindImageMemory2(VkDevice device,
3611 uint32_t bindInfoCount,
3612 const VkBindImageMemoryInfo *pBindInfos)
3613 {
3614 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3615 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3616 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3617
3618 if (mem) {
3619 image->bo = mem->bo;
3620 image->offset = pBindInfos[i].memoryOffset;
3621 } else {
3622 image->bo = NULL;
3623 image->offset = 0;
3624 }
3625 }
3626 return VK_SUCCESS;
3627 }
3628
3629
3630 VkResult radv_BindImageMemory(
3631 VkDevice device,
3632 VkImage image,
3633 VkDeviceMemory memory,
3634 VkDeviceSize memoryOffset)
3635 {
3636 const VkBindImageMemoryInfo info = {
3637 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3638 .image = image,
3639 .memory = memory,
3640 .memoryOffset = memoryOffset
3641 };
3642
3643 return radv_BindImageMemory2(device, 1, &info);
3644 }
3645
3646
3647 static void
3648 radv_sparse_buffer_bind_memory(struct radv_device *device,
3649 const VkSparseBufferMemoryBindInfo *bind)
3650 {
3651 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3652
3653 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3654 struct radv_device_memory *mem = NULL;
3655
3656 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3657 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3658
3659 device->ws->buffer_virtual_bind(buffer->bo,
3660 bind->pBinds[i].resourceOffset,
3661 bind->pBinds[i].size,
3662 mem ? mem->bo : NULL,
3663 bind->pBinds[i].memoryOffset);
3664 }
3665 }
3666
3667 static void
3668 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3669 const VkSparseImageOpaqueMemoryBindInfo *bind)
3670 {
3671 RADV_FROM_HANDLE(radv_image, image, bind->image);
3672
3673 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3674 struct radv_device_memory *mem = NULL;
3675
3676 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3677 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3678
3679 device->ws->buffer_virtual_bind(image->bo,
3680 bind->pBinds[i].resourceOffset,
3681 bind->pBinds[i].size,
3682 mem ? mem->bo : NULL,
3683 bind->pBinds[i].memoryOffset);
3684 }
3685 }
3686
3687 VkResult radv_QueueBindSparse(
3688 VkQueue _queue,
3689 uint32_t bindInfoCount,
3690 const VkBindSparseInfo* pBindInfo,
3691 VkFence _fence)
3692 {
3693 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3694 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3695 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3696 bool fence_emitted = false;
3697 VkResult result;
3698 int ret;
3699
3700 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3701 struct radv_winsys_sem_info sem_info;
3702 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3703 radv_sparse_buffer_bind_memory(queue->device,
3704 pBindInfo[i].pBufferBinds + j);
3705 }
3706
3707 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3708 radv_sparse_image_opaque_bind_memory(queue->device,
3709 pBindInfo[i].pImageOpaqueBinds + j);
3710 }
3711
3712 VkResult result;
3713 result = radv_alloc_sem_info(queue->device->instance,
3714 &sem_info,
3715 pBindInfo[i].waitSemaphoreCount,
3716 pBindInfo[i].pWaitSemaphores,
3717 pBindInfo[i].signalSemaphoreCount,
3718 pBindInfo[i].pSignalSemaphores,
3719 _fence);
3720 if (result != VK_SUCCESS)
3721 return result;
3722
3723 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3724 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3725 &queue->device->empty_cs[queue->queue_family_index],
3726 1, NULL, NULL,
3727 &sem_info, NULL,
3728 false, base_fence);
3729 if (ret) {
3730 radv_loge("failed to submit CS %d\n", i);
3731 abort();
3732 }
3733
3734 fence_emitted = true;
3735 }
3736
3737 radv_free_sem_info(&sem_info);
3738
3739 }
3740
3741 if (fence) {
3742 if (!fence_emitted) {
3743 result = radv_signal_fence(queue, fence);
3744 if (result != VK_SUCCESS)
3745 return result;
3746 }
3747 }
3748
3749 return VK_SUCCESS;
3750 }
3751
3752 VkResult radv_CreateFence(
3753 VkDevice _device,
3754 const VkFenceCreateInfo* pCreateInfo,
3755 const VkAllocationCallbacks* pAllocator,
3756 VkFence* pFence)
3757 {
3758 RADV_FROM_HANDLE(radv_device, device, _device);
3759 const VkExportFenceCreateInfo *export =
3760 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3761 VkExternalFenceHandleTypeFlags handleTypes =
3762 export ? export->handleTypes : 0;
3763
3764 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3765 sizeof(*fence), 8,
3766 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3767
3768 if (!fence)
3769 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3770
3771 fence->fence_wsi = NULL;
3772 fence->temp_syncobj = 0;
3773 if (device->always_use_syncobj || handleTypes) {
3774 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3775 if (ret) {
3776 vk_free2(&device->alloc, pAllocator, fence);
3777 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3778 }
3779 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3780 device->ws->signal_syncobj(device->ws, fence->syncobj);
3781 }
3782 fence->fence = NULL;
3783 } else {
3784 fence->fence = device->ws->create_fence();
3785 if (!fence->fence) {
3786 vk_free2(&device->alloc, pAllocator, fence);
3787 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3788 }
3789 fence->syncobj = 0;
3790 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3791 device->ws->signal_fence(fence->fence);
3792 }
3793
3794 *pFence = radv_fence_to_handle(fence);
3795
3796 return VK_SUCCESS;
3797 }
3798
3799 void radv_DestroyFence(
3800 VkDevice _device,
3801 VkFence _fence,
3802 const VkAllocationCallbacks* pAllocator)
3803 {
3804 RADV_FROM_HANDLE(radv_device, device, _device);
3805 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3806
3807 if (!fence)
3808 return;
3809
3810 if (fence->temp_syncobj)
3811 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3812 if (fence->syncobj)
3813 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3814 if (fence->fence)
3815 device->ws->destroy_fence(fence->fence);
3816 if (fence->fence_wsi)
3817 fence->fence_wsi->destroy(fence->fence_wsi);
3818 vk_free2(&device->alloc, pAllocator, fence);
3819 }
3820
3821
3822 uint64_t radv_get_current_time(void)
3823 {
3824 struct timespec tv;
3825 clock_gettime(CLOCK_MONOTONIC, &tv);
3826 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3827 }
3828
3829 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3830 {
3831 uint64_t current_time = radv_get_current_time();
3832
3833 timeout = MIN2(UINT64_MAX - current_time, timeout);
3834
3835 return current_time + timeout;
3836 }
3837
3838
3839 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3840 uint32_t fenceCount, const VkFence *pFences)
3841 {
3842 for (uint32_t i = 0; i < fenceCount; ++i) {
3843 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3844 if (fence->fence == NULL || fence->syncobj ||
3845 fence->temp_syncobj || fence->fence_wsi ||
3846 (!device->ws->is_fence_waitable(fence->fence)))
3847 return false;
3848 }
3849 return true;
3850 }
3851
3852 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3853 {
3854 for (uint32_t i = 0; i < fenceCount; ++i) {
3855 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3856 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3857 return false;
3858 }
3859 return true;
3860 }
3861
3862 VkResult radv_WaitForFences(
3863 VkDevice _device,
3864 uint32_t fenceCount,
3865 const VkFence* pFences,
3866 VkBool32 waitAll,
3867 uint64_t timeout)
3868 {
3869 RADV_FROM_HANDLE(radv_device, device, _device);
3870 timeout = radv_get_absolute_timeout(timeout);
3871
3872 if (device->always_use_syncobj &&
3873 radv_all_fences_syncobj(fenceCount, pFences))
3874 {
3875 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3876 if (!handles)
3877 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3878
3879 for (uint32_t i = 0; i < fenceCount; ++i) {
3880 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3881 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3882 }
3883
3884 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3885
3886 free(handles);
3887 return success ? VK_SUCCESS : VK_TIMEOUT;
3888 }
3889
3890 if (!waitAll && fenceCount > 1) {
3891 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3892 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3893 uint32_t wait_count = 0;
3894 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3895 if (!fences)
3896 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3897
3898 for (uint32_t i = 0; i < fenceCount; ++i) {
3899 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3900
3901 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3902 free(fences);
3903 return VK_SUCCESS;
3904 }
3905
3906 fences[wait_count++] = fence->fence;
3907 }
3908
3909 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3910 waitAll, timeout - radv_get_current_time());
3911
3912 free(fences);
3913 return success ? VK_SUCCESS : VK_TIMEOUT;
3914 }
3915
3916 while(radv_get_current_time() <= timeout) {
3917 for (uint32_t i = 0; i < fenceCount; ++i) {
3918 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3919 return VK_SUCCESS;
3920 }
3921 }
3922 return VK_TIMEOUT;
3923 }
3924
3925 for (uint32_t i = 0; i < fenceCount; ++i) {
3926 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3927 bool expired = false;
3928
3929 if (fence->temp_syncobj) {
3930 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3931 return VK_TIMEOUT;
3932 continue;
3933 }
3934
3935 if (fence->syncobj) {
3936 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3937 return VK_TIMEOUT;
3938 continue;
3939 }
3940
3941 if (fence->fence) {
3942 if (!device->ws->is_fence_waitable(fence->fence)) {
3943 while(!device->ws->is_fence_waitable(fence->fence) &&
3944 radv_get_current_time() <= timeout)
3945 /* Do nothing */;
3946 }
3947
3948 expired = device->ws->fence_wait(device->ws,
3949 fence->fence,
3950 true, timeout);
3951 if (!expired)
3952 return VK_TIMEOUT;
3953 }
3954
3955 if (fence->fence_wsi) {
3956 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3957 if (result != VK_SUCCESS)
3958 return result;
3959 }
3960 }
3961
3962 return VK_SUCCESS;
3963 }
3964
3965 VkResult radv_ResetFences(VkDevice _device,
3966 uint32_t fenceCount,
3967 const VkFence *pFences)
3968 {
3969 RADV_FROM_HANDLE(radv_device, device, _device);
3970
3971 for (unsigned i = 0; i < fenceCount; ++i) {
3972 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3973 if (fence->fence)
3974 device->ws->reset_fence(fence->fence);
3975
3976 /* Per spec, we first restore the permanent payload, and then reset, so
3977 * having a temp syncobj should not skip resetting the permanent syncobj. */
3978 if (fence->temp_syncobj) {
3979 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3980 fence->temp_syncobj = 0;
3981 }
3982
3983 if (fence->syncobj) {
3984 device->ws->reset_syncobj(device->ws, fence->syncobj);
3985 }
3986 }
3987
3988 return VK_SUCCESS;
3989 }
3990
3991 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3992 {
3993 RADV_FROM_HANDLE(radv_device, device, _device);
3994 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3995
3996 if (fence->temp_syncobj) {
3997 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3998 return success ? VK_SUCCESS : VK_NOT_READY;
3999 }
4000
4001 if (fence->syncobj) {
4002 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4003 return success ? VK_SUCCESS : VK_NOT_READY;
4004 }
4005
4006 if (fence->fence) {
4007 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4008 return VK_NOT_READY;
4009 }
4010 if (fence->fence_wsi) {
4011 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4012
4013 if (result != VK_SUCCESS) {
4014 if (result == VK_TIMEOUT)
4015 return VK_NOT_READY;
4016 return result;
4017 }
4018 }
4019 return VK_SUCCESS;
4020 }
4021
4022
4023 // Queue semaphore functions
4024
4025 VkResult radv_CreateSemaphore(
4026 VkDevice _device,
4027 const VkSemaphoreCreateInfo* pCreateInfo,
4028 const VkAllocationCallbacks* pAllocator,
4029 VkSemaphore* pSemaphore)
4030 {
4031 RADV_FROM_HANDLE(radv_device, device, _device);
4032 const VkExportSemaphoreCreateInfo *export =
4033 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4034 VkExternalSemaphoreHandleTypeFlags handleTypes =
4035 export ? export->handleTypes : 0;
4036
4037 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4038 sizeof(*sem), 8,
4039 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4040 if (!sem)
4041 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4042
4043 sem->temp_syncobj = 0;
4044 /* create a syncobject if we are going to export this semaphore */
4045 if (device->always_use_syncobj || handleTypes) {
4046 assert (device->physical_device->rad_info.has_syncobj);
4047 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4048 if (ret) {
4049 vk_free2(&device->alloc, pAllocator, sem);
4050 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4051 }
4052 sem->sem = NULL;
4053 } else {
4054 sem->sem = device->ws->create_sem(device->ws);
4055 if (!sem->sem) {
4056 vk_free2(&device->alloc, pAllocator, sem);
4057 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4058 }
4059 sem->syncobj = 0;
4060 }
4061
4062 *pSemaphore = radv_semaphore_to_handle(sem);
4063 return VK_SUCCESS;
4064 }
4065
4066 void radv_DestroySemaphore(
4067 VkDevice _device,
4068 VkSemaphore _semaphore,
4069 const VkAllocationCallbacks* pAllocator)
4070 {
4071 RADV_FROM_HANDLE(radv_device, device, _device);
4072 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4073 if (!_semaphore)
4074 return;
4075
4076 if (sem->syncobj)
4077 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4078 else
4079 device->ws->destroy_sem(sem->sem);
4080 vk_free2(&device->alloc, pAllocator, sem);
4081 }
4082
4083 VkResult radv_CreateEvent(
4084 VkDevice _device,
4085 const VkEventCreateInfo* pCreateInfo,
4086 const VkAllocationCallbacks* pAllocator,
4087 VkEvent* pEvent)
4088 {
4089 RADV_FROM_HANDLE(radv_device, device, _device);
4090 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4091 sizeof(*event), 8,
4092 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4093
4094 if (!event)
4095 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4096
4097 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4098 RADEON_DOMAIN_GTT,
4099 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4100 RADV_BO_PRIORITY_FENCE);
4101 if (!event->bo) {
4102 vk_free2(&device->alloc, pAllocator, event);
4103 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4104 }
4105
4106 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4107
4108 *pEvent = radv_event_to_handle(event);
4109
4110 return VK_SUCCESS;
4111 }
4112
4113 void radv_DestroyEvent(
4114 VkDevice _device,
4115 VkEvent _event,
4116 const VkAllocationCallbacks* pAllocator)
4117 {
4118 RADV_FROM_HANDLE(radv_device, device, _device);
4119 RADV_FROM_HANDLE(radv_event, event, _event);
4120
4121 if (!event)
4122 return;
4123 device->ws->buffer_destroy(event->bo);
4124 vk_free2(&device->alloc, pAllocator, event);
4125 }
4126
4127 VkResult radv_GetEventStatus(
4128 VkDevice _device,
4129 VkEvent _event)
4130 {
4131 RADV_FROM_HANDLE(radv_event, event, _event);
4132
4133 if (*event->map == 1)
4134 return VK_EVENT_SET;
4135 return VK_EVENT_RESET;
4136 }
4137
4138 VkResult radv_SetEvent(
4139 VkDevice _device,
4140 VkEvent _event)
4141 {
4142 RADV_FROM_HANDLE(radv_event, event, _event);
4143 *event->map = 1;
4144
4145 return VK_SUCCESS;
4146 }
4147
4148 VkResult radv_ResetEvent(
4149 VkDevice _device,
4150 VkEvent _event)
4151 {
4152 RADV_FROM_HANDLE(radv_event, event, _event);
4153 *event->map = 0;
4154
4155 return VK_SUCCESS;
4156 }
4157
4158 VkResult radv_CreateBuffer(
4159 VkDevice _device,
4160 const VkBufferCreateInfo* pCreateInfo,
4161 const VkAllocationCallbacks* pAllocator,
4162 VkBuffer* pBuffer)
4163 {
4164 RADV_FROM_HANDLE(radv_device, device, _device);
4165 struct radv_buffer *buffer;
4166
4167 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4168
4169 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4170 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4171 if (buffer == NULL)
4172 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4173
4174 buffer->size = pCreateInfo->size;
4175 buffer->usage = pCreateInfo->usage;
4176 buffer->bo = NULL;
4177 buffer->offset = 0;
4178 buffer->flags = pCreateInfo->flags;
4179
4180 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4181 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4182
4183 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4184 buffer->bo = device->ws->buffer_create(device->ws,
4185 align64(buffer->size, 4096),
4186 4096, 0, RADEON_FLAG_VIRTUAL,
4187 RADV_BO_PRIORITY_VIRTUAL);
4188 if (!buffer->bo) {
4189 vk_free2(&device->alloc, pAllocator, buffer);
4190 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4191 }
4192 }
4193
4194 *pBuffer = radv_buffer_to_handle(buffer);
4195
4196 return VK_SUCCESS;
4197 }
4198
4199 void radv_DestroyBuffer(
4200 VkDevice _device,
4201 VkBuffer _buffer,
4202 const VkAllocationCallbacks* pAllocator)
4203 {
4204 RADV_FROM_HANDLE(radv_device, device, _device);
4205 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4206
4207 if (!buffer)
4208 return;
4209
4210 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4211 device->ws->buffer_destroy(buffer->bo);
4212
4213 vk_free2(&device->alloc, pAllocator, buffer);
4214 }
4215
4216 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4217 VkDevice device,
4218 const VkBufferDeviceAddressInfoEXT* pInfo)
4219 {
4220 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4221 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4222 }
4223
4224
4225 static inline unsigned
4226 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4227 {
4228 if (stencil)
4229 return plane->surface.u.legacy.stencil_tiling_index[level];
4230 else
4231 return plane->surface.u.legacy.tiling_index[level];
4232 }
4233
4234 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4235 {
4236 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4237 }
4238
4239 static uint32_t
4240 radv_init_dcc_control_reg(struct radv_device *device,
4241 struct radv_image_view *iview)
4242 {
4243 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4244 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4245 unsigned max_compressed_block_size;
4246 unsigned independent_128b_blocks;
4247 unsigned independent_64b_blocks;
4248
4249 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4250 return 0;
4251
4252 if (!device->physical_device->rad_info.has_dedicated_vram) {
4253 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4254 * dGPU and 64 for APU because all of our APUs to date use
4255 * DIMMs which have a request granularity size of 64B while all
4256 * other chips have a 32B request size.
4257 */
4258 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4259 }
4260
4261 if (device->physical_device->rad_info.chip_class >= GFX10) {
4262 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4263 independent_64b_blocks = 0;
4264 independent_128b_blocks = 1;
4265 } else {
4266 independent_128b_blocks = 0;
4267
4268 if (iview->image->info.samples > 1) {
4269 if (iview->image->planes[0].surface.bpe == 1)
4270 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4271 else if (iview->image->planes[0].surface.bpe == 2)
4272 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4273 }
4274
4275 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4276 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4277 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4278 /* If this DCC image is potentially going to be used in texture
4279 * fetches, we need some special settings.
4280 */
4281 independent_64b_blocks = 1;
4282 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4283 } else {
4284 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4285 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4286 * big as possible for better compression state.
4287 */
4288 independent_64b_blocks = 0;
4289 max_compressed_block_size = max_uncompressed_block_size;
4290 }
4291 }
4292
4293 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4294 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4295 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4296 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4297 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4298 }
4299
4300 static void
4301 radv_initialise_color_surface(struct radv_device *device,
4302 struct radv_color_buffer_info *cb,
4303 struct radv_image_view *iview)
4304 {
4305 const struct vk_format_description *desc;
4306 unsigned ntype, format, swap, endian;
4307 unsigned blend_clamp = 0, blend_bypass = 0;
4308 uint64_t va;
4309 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4310 const struct radeon_surf *surf = &plane->surface;
4311
4312 desc = vk_format_description(iview->vk_format);
4313
4314 memset(cb, 0, sizeof(*cb));
4315
4316 /* Intensity is implemented as Red, so treat it that way. */
4317 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4318
4319 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4320
4321 cb->cb_color_base = va >> 8;
4322
4323 if (device->physical_device->rad_info.chip_class >= GFX9) {
4324 struct gfx9_surf_meta_flags meta;
4325 if (iview->image->dcc_offset)
4326 meta = surf->u.gfx9.dcc;
4327 else
4328 meta = surf->u.gfx9.cmask;
4329
4330 if (device->physical_device->rad_info.chip_class >= GFX10) {
4331 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4332 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4333 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4334 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4335 } else {
4336 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4337 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4338 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4339 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4340 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4341 }
4342
4343 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4344 cb->cb_color_base |= surf->tile_swizzle;
4345 } else {
4346 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4347 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4348
4349 cb->cb_color_base += level_info->offset >> 8;
4350 if (level_info->mode == RADEON_SURF_MODE_2D)
4351 cb->cb_color_base |= surf->tile_swizzle;
4352
4353 pitch_tile_max = level_info->nblk_x / 8 - 1;
4354 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4355 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4356
4357 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4358 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4359 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4360
4361 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4362
4363 if (radv_image_has_fmask(iview->image)) {
4364 if (device->physical_device->rad_info.chip_class >= GFX7)
4365 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4366 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4367 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4368 } else {
4369 /* This must be set for fast clear to work without FMASK. */
4370 if (device->physical_device->rad_info.chip_class >= GFX7)
4371 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4372 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4373 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4374 }
4375 }
4376
4377 /* CMASK variables */
4378 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4379 va += iview->image->cmask.offset;
4380 cb->cb_color_cmask = va >> 8;
4381
4382 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4383 va += iview->image->dcc_offset;
4384
4385 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4386 device->physical_device->rad_info.chip_class <= GFX8)
4387 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4388
4389 cb->cb_dcc_base = va >> 8;
4390 cb->cb_dcc_base |= surf->tile_swizzle;
4391
4392 /* GFX10 field has the same base shift as the GFX6 field. */
4393 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4394 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4395 S_028C6C_SLICE_MAX_GFX10(max_slice);
4396
4397 if (iview->image->info.samples > 1) {
4398 unsigned log_samples = util_logbase2(iview->image->info.samples);
4399
4400 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4401 S_028C74_NUM_FRAGMENTS(log_samples);
4402 }
4403
4404 if (radv_image_has_fmask(iview->image)) {
4405 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4406 cb->cb_color_fmask = va >> 8;
4407 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4408 } else {
4409 cb->cb_color_fmask = cb->cb_color_base;
4410 }
4411
4412 ntype = radv_translate_color_numformat(iview->vk_format,
4413 desc,
4414 vk_format_get_first_non_void_channel(iview->vk_format));
4415 format = radv_translate_colorformat(iview->vk_format);
4416 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4417 radv_finishme("Illegal color\n");
4418 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4419 endian = radv_colorformat_endian_swap(format);
4420
4421 /* blend clamp should be set for all NORM/SRGB types */
4422 if (ntype == V_028C70_NUMBER_UNORM ||
4423 ntype == V_028C70_NUMBER_SNORM ||
4424 ntype == V_028C70_NUMBER_SRGB)
4425 blend_clamp = 1;
4426
4427 /* set blend bypass according to docs if SINT/UINT or
4428 8/24 COLOR variants */
4429 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4430 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4431 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4432 blend_clamp = 0;
4433 blend_bypass = 1;
4434 }
4435 #if 0
4436 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4437 (format == V_028C70_COLOR_8 ||
4438 format == V_028C70_COLOR_8_8 ||
4439 format == V_028C70_COLOR_8_8_8_8))
4440 ->color_is_int8 = true;
4441 #endif
4442 cb->cb_color_info = S_028C70_FORMAT(format) |
4443 S_028C70_COMP_SWAP(swap) |
4444 S_028C70_BLEND_CLAMP(blend_clamp) |
4445 S_028C70_BLEND_BYPASS(blend_bypass) |
4446 S_028C70_SIMPLE_FLOAT(1) |
4447 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4448 ntype != V_028C70_NUMBER_SNORM &&
4449 ntype != V_028C70_NUMBER_SRGB &&
4450 format != V_028C70_COLOR_8_24 &&
4451 format != V_028C70_COLOR_24_8) |
4452 S_028C70_NUMBER_TYPE(ntype) |
4453 S_028C70_ENDIAN(endian);
4454 if (radv_image_has_fmask(iview->image)) {
4455 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4456 if (device->physical_device->rad_info.chip_class == GFX6) {
4457 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4458 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4459 }
4460
4461 if (radv_image_is_tc_compat_cmask(iview->image)) {
4462 /* Allow the texture block to read FMASK directly
4463 * without decompressing it. This bit must be cleared
4464 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4465 * otherwise the operation doesn't happen.
4466 */
4467 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4468
4469 /* Set CMASK into a tiling format that allows the
4470 * texture block to read it.
4471 */
4472 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4473 }
4474 }
4475
4476 if (radv_image_has_cmask(iview->image) &&
4477 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4478 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4479
4480 if (radv_dcc_enabled(iview->image, iview->base_mip))
4481 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4482
4483 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4484
4485 /* This must be set for fast clear to work without FMASK. */
4486 if (!radv_image_has_fmask(iview->image) &&
4487 device->physical_device->rad_info.chip_class == GFX6) {
4488 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4489 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4490 }
4491
4492 if (device->physical_device->rad_info.chip_class >= GFX9) {
4493 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4494
4495 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4496 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4497 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4498 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4499
4500 if (device->physical_device->rad_info.chip_class >= GFX10) {
4501 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4502
4503 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4504 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4505 S_028EE0_RESOURCE_LEVEL(1);
4506 } else {
4507 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4508 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4509 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4510 }
4511
4512 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4513 S_028C68_MIP0_HEIGHT(height - 1) |
4514 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4515 }
4516 }
4517
4518 static unsigned
4519 radv_calc_decompress_on_z_planes(struct radv_device *device,
4520 struct radv_image_view *iview)
4521 {
4522 unsigned max_zplanes = 0;
4523
4524 assert(radv_image_is_tc_compat_htile(iview->image));
4525
4526 if (device->physical_device->rad_info.chip_class >= GFX9) {
4527 /* Default value for 32-bit depth surfaces. */
4528 max_zplanes = 4;
4529
4530 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4531 iview->image->info.samples > 1)
4532 max_zplanes = 2;
4533
4534 max_zplanes = max_zplanes + 1;
4535 } else {
4536 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4537 /* Do not enable Z plane compression for 16-bit depth
4538 * surfaces because isn't supported on GFX8. Only
4539 * 32-bit depth surfaces are supported by the hardware.
4540 * This allows to maintain shader compatibility and to
4541 * reduce the number of depth decompressions.
4542 */
4543 max_zplanes = 1;
4544 } else {
4545 if (iview->image->info.samples <= 1)
4546 max_zplanes = 5;
4547 else if (iview->image->info.samples <= 4)
4548 max_zplanes = 3;
4549 else
4550 max_zplanes = 2;
4551 }
4552 }
4553
4554 return max_zplanes;
4555 }
4556
4557 static void
4558 radv_initialise_ds_surface(struct radv_device *device,
4559 struct radv_ds_buffer_info *ds,
4560 struct radv_image_view *iview)
4561 {
4562 unsigned level = iview->base_mip;
4563 unsigned format, stencil_format;
4564 uint64_t va, s_offs, z_offs;
4565 bool stencil_only = false;
4566 const struct radv_image_plane *plane = &iview->image->planes[0];
4567 const struct radeon_surf *surf = &plane->surface;
4568
4569 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4570
4571 memset(ds, 0, sizeof(*ds));
4572 switch (iview->image->vk_format) {
4573 case VK_FORMAT_D24_UNORM_S8_UINT:
4574 case VK_FORMAT_X8_D24_UNORM_PACK32:
4575 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4576 ds->offset_scale = 2.0f;
4577 break;
4578 case VK_FORMAT_D16_UNORM:
4579 case VK_FORMAT_D16_UNORM_S8_UINT:
4580 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4581 ds->offset_scale = 4.0f;
4582 break;
4583 case VK_FORMAT_D32_SFLOAT:
4584 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4585 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4586 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4587 ds->offset_scale = 1.0f;
4588 break;
4589 case VK_FORMAT_S8_UINT:
4590 stencil_only = true;
4591 break;
4592 default:
4593 break;
4594 }
4595
4596 format = radv_translate_dbformat(iview->image->vk_format);
4597 stencil_format = surf->has_stencil ?
4598 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4599
4600 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4601 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4602 S_028008_SLICE_MAX(max_slice);
4603 if (device->physical_device->rad_info.chip_class >= GFX10) {
4604 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4605 S_028008_SLICE_MAX_HI(max_slice >> 11);
4606 }
4607
4608 ds->db_htile_data_base = 0;
4609 ds->db_htile_surface = 0;
4610
4611 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4612 s_offs = z_offs = va;
4613
4614 if (device->physical_device->rad_info.chip_class >= GFX9) {
4615 assert(surf->u.gfx9.surf_offset == 0);
4616 s_offs += surf->u.gfx9.stencil_offset;
4617
4618 ds->db_z_info = S_028038_FORMAT(format) |
4619 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4620 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4621 S_028038_MAXMIP(iview->image->info.levels - 1) |
4622 S_028038_ZRANGE_PRECISION(1);
4623 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4624 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4625
4626 if (device->physical_device->rad_info.chip_class == GFX9) {
4627 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4628 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4629 }
4630
4631 ds->db_depth_view |= S_028008_MIPID(level);
4632 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4633 S_02801C_Y_MAX(iview->image->info.height - 1);
4634
4635 if (radv_htile_enabled(iview->image, level)) {
4636 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4637
4638 if (radv_image_is_tc_compat_htile(iview->image)) {
4639 unsigned max_zplanes =
4640 radv_calc_decompress_on_z_planes(device, iview);
4641
4642 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4643
4644 if (device->physical_device->rad_info.chip_class >= GFX10) {
4645 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4646 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4647 } else {
4648 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4649 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4650 }
4651 }
4652
4653 if (!surf->has_stencil)
4654 /* Use all of the htile_buffer for depth if there's no stencil. */
4655 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4656 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4657 iview->image->htile_offset;
4658 ds->db_htile_data_base = va >> 8;
4659 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4660 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4661
4662 if (device->physical_device->rad_info.chip_class == GFX9) {
4663 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4664 }
4665 }
4666 } else {
4667 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4668
4669 if (stencil_only)
4670 level_info = &surf->u.legacy.stencil_level[level];
4671
4672 z_offs += surf->u.legacy.level[level].offset;
4673 s_offs += surf->u.legacy.stencil_level[level].offset;
4674
4675 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4676 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4677 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4678
4679 if (iview->image->info.samples > 1)
4680 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4681
4682 if (device->physical_device->rad_info.chip_class >= GFX7) {
4683 struct radeon_info *info = &device->physical_device->rad_info;
4684 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4685 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4686 unsigned macro_index = surf->u.legacy.macro_tile_index;
4687 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4688 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4689 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4690
4691 if (stencil_only)
4692 tile_mode = stencil_tile_mode;
4693
4694 ds->db_depth_info |=
4695 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4696 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4697 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4698 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4699 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4700 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4701 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4702 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4703 } else {
4704 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4705 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4706 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4707 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4708 if (stencil_only)
4709 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4710 }
4711
4712 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4713 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4714 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4715
4716 if (radv_htile_enabled(iview->image, level)) {
4717 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4718
4719 if (!surf->has_stencil &&
4720 !radv_image_is_tc_compat_htile(iview->image))
4721 /* Use all of the htile_buffer for depth if there's no stencil. */
4722 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4723
4724 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4725 iview->image->htile_offset;
4726 ds->db_htile_data_base = va >> 8;
4727 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4728
4729 if (radv_image_is_tc_compat_htile(iview->image)) {
4730 unsigned max_zplanes =
4731 radv_calc_decompress_on_z_planes(device, iview);
4732
4733 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4734 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4735 }
4736 }
4737 }
4738
4739 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4740 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4741 }
4742
4743 VkResult radv_CreateFramebuffer(
4744 VkDevice _device,
4745 const VkFramebufferCreateInfo* pCreateInfo,
4746 const VkAllocationCallbacks* pAllocator,
4747 VkFramebuffer* pFramebuffer)
4748 {
4749 RADV_FROM_HANDLE(radv_device, device, _device);
4750 struct radv_framebuffer *framebuffer;
4751
4752 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4753
4754 size_t size = sizeof(*framebuffer) +
4755 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4756 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4757 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4758 if (framebuffer == NULL)
4759 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4760
4761 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4762 framebuffer->width = pCreateInfo->width;
4763 framebuffer->height = pCreateInfo->height;
4764 framebuffer->layers = pCreateInfo->layers;
4765 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4766 VkImageView _iview = pCreateInfo->pAttachments[i];
4767 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4768 framebuffer->attachments[i].attachment = iview;
4769 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4770 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4771 } else {
4772 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4773 }
4774 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4775 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4776 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4777 }
4778
4779 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4780 return VK_SUCCESS;
4781 }
4782
4783 void radv_DestroyFramebuffer(
4784 VkDevice _device,
4785 VkFramebuffer _fb,
4786 const VkAllocationCallbacks* pAllocator)
4787 {
4788 RADV_FROM_HANDLE(radv_device, device, _device);
4789 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4790
4791 if (!fb)
4792 return;
4793 vk_free2(&device->alloc, pAllocator, fb);
4794 }
4795
4796 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4797 {
4798 switch (address_mode) {
4799 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4800 return V_008F30_SQ_TEX_WRAP;
4801 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4802 return V_008F30_SQ_TEX_MIRROR;
4803 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4804 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4805 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4806 return V_008F30_SQ_TEX_CLAMP_BORDER;
4807 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4808 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4809 default:
4810 unreachable("illegal tex wrap mode");
4811 break;
4812 }
4813 }
4814
4815 static unsigned
4816 radv_tex_compare(VkCompareOp op)
4817 {
4818 switch (op) {
4819 case VK_COMPARE_OP_NEVER:
4820 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4821 case VK_COMPARE_OP_LESS:
4822 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4823 case VK_COMPARE_OP_EQUAL:
4824 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4825 case VK_COMPARE_OP_LESS_OR_EQUAL:
4826 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4827 case VK_COMPARE_OP_GREATER:
4828 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4829 case VK_COMPARE_OP_NOT_EQUAL:
4830 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4831 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4832 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4833 case VK_COMPARE_OP_ALWAYS:
4834 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4835 default:
4836 unreachable("illegal compare mode");
4837 break;
4838 }
4839 }
4840
4841 static unsigned
4842 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4843 {
4844 switch (filter) {
4845 case VK_FILTER_NEAREST:
4846 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4847 V_008F38_SQ_TEX_XY_FILTER_POINT);
4848 case VK_FILTER_LINEAR:
4849 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4850 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4851 case VK_FILTER_CUBIC_IMG:
4852 default:
4853 fprintf(stderr, "illegal texture filter");
4854 return 0;
4855 }
4856 }
4857
4858 static unsigned
4859 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4860 {
4861 switch (mode) {
4862 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4863 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4864 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4865 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4866 default:
4867 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4868 }
4869 }
4870
4871 static unsigned
4872 radv_tex_bordercolor(VkBorderColor bcolor)
4873 {
4874 switch (bcolor) {
4875 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4876 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4877 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4878 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4879 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4880 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4881 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4882 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4883 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4884 default:
4885 break;
4886 }
4887 return 0;
4888 }
4889
4890 static unsigned
4891 radv_tex_aniso_filter(unsigned filter)
4892 {
4893 if (filter < 2)
4894 return 0;
4895 if (filter < 4)
4896 return 1;
4897 if (filter < 8)
4898 return 2;
4899 if (filter < 16)
4900 return 3;
4901 return 4;
4902 }
4903
4904 static unsigned
4905 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4906 {
4907 switch (mode) {
4908 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4909 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4910 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4911 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4912 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4913 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4914 default:
4915 break;
4916 }
4917 return 0;
4918 }
4919
4920 static uint32_t
4921 radv_get_max_anisotropy(struct radv_device *device,
4922 const VkSamplerCreateInfo *pCreateInfo)
4923 {
4924 if (device->force_aniso >= 0)
4925 return device->force_aniso;
4926
4927 if (pCreateInfo->anisotropyEnable &&
4928 pCreateInfo->maxAnisotropy > 1.0f)
4929 return (uint32_t)pCreateInfo->maxAnisotropy;
4930
4931 return 0;
4932 }
4933
4934 static void
4935 radv_init_sampler(struct radv_device *device,
4936 struct radv_sampler *sampler,
4937 const VkSamplerCreateInfo *pCreateInfo)
4938 {
4939 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4940 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4941 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4942 device->physical_device->rad_info.chip_class == GFX9;
4943 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4944
4945 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4946 vk_find_struct_const(pCreateInfo->pNext,
4947 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4948 if (sampler_reduction)
4949 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4950
4951 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4952 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4953 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4954 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4955 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4956 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4957 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4958 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4959 S_008F30_DISABLE_CUBE_WRAP(0) |
4960 S_008F30_COMPAT_MODE(compat_mode) |
4961 S_008F30_FILTER_MODE(filter_mode));
4962 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4963 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4964 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4965 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4966 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4967 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4968 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4969 S_008F38_MIP_POINT_PRECLAMP(0));
4970 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4971 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4972
4973 if (device->physical_device->rad_info.chip_class >= GFX10) {
4974 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4975 } else {
4976 sampler->state[2] |=
4977 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4978 S_008F38_FILTER_PREC_FIX(1) |
4979 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
4980 }
4981 }
4982
4983 VkResult radv_CreateSampler(
4984 VkDevice _device,
4985 const VkSamplerCreateInfo* pCreateInfo,
4986 const VkAllocationCallbacks* pAllocator,
4987 VkSampler* pSampler)
4988 {
4989 RADV_FROM_HANDLE(radv_device, device, _device);
4990 struct radv_sampler *sampler;
4991
4992 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4993 vk_find_struct_const(pCreateInfo->pNext,
4994 SAMPLER_YCBCR_CONVERSION_INFO);
4995
4996 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4997
4998 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4999 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5000 if (!sampler)
5001 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5002
5003 radv_init_sampler(device, sampler, pCreateInfo);
5004
5005 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5006 *pSampler = radv_sampler_to_handle(sampler);
5007
5008 return VK_SUCCESS;
5009 }
5010
5011 void radv_DestroySampler(
5012 VkDevice _device,
5013 VkSampler _sampler,
5014 const VkAllocationCallbacks* pAllocator)
5015 {
5016 RADV_FROM_HANDLE(radv_device, device, _device);
5017 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5018
5019 if (!sampler)
5020 return;
5021 vk_free2(&device->alloc, pAllocator, sampler);
5022 }
5023
5024 /* vk_icd.h does not declare this function, so we declare it here to
5025 * suppress Wmissing-prototypes.
5026 */
5027 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5028 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5029
5030 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5031 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5032 {
5033 /* For the full details on loader interface versioning, see
5034 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5035 * What follows is a condensed summary, to help you navigate the large and
5036 * confusing official doc.
5037 *
5038 * - Loader interface v0 is incompatible with later versions. We don't
5039 * support it.
5040 *
5041 * - In loader interface v1:
5042 * - The first ICD entrypoint called by the loader is
5043 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5044 * entrypoint.
5045 * - The ICD must statically expose no other Vulkan symbol unless it is
5046 * linked with -Bsymbolic.
5047 * - Each dispatchable Vulkan handle created by the ICD must be
5048 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5049 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5050 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5051 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5052 * such loader-managed surfaces.
5053 *
5054 * - Loader interface v2 differs from v1 in:
5055 * - The first ICD entrypoint called by the loader is
5056 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5057 * statically expose this entrypoint.
5058 *
5059 * - Loader interface v3 differs from v2 in:
5060 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5061 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5062 * because the loader no longer does so.
5063 */
5064 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5065 return VK_SUCCESS;
5066 }
5067
5068 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5069 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5070 int *pFD)
5071 {
5072 RADV_FROM_HANDLE(radv_device, device, _device);
5073 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5074
5075 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5076
5077 /* At the moment, we support only the below handle types. */
5078 assert(pGetFdInfo->handleType ==
5079 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5080 pGetFdInfo->handleType ==
5081 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5082
5083 bool ret = radv_get_memory_fd(device, memory, pFD);
5084 if (ret == false)
5085 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5086 return VK_SUCCESS;
5087 }
5088
5089 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5090 VkExternalMemoryHandleTypeFlagBits handleType,
5091 int fd,
5092 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5093 {
5094 RADV_FROM_HANDLE(radv_device, device, _device);
5095
5096 switch (handleType) {
5097 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5098 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5099 return VK_SUCCESS;
5100
5101 default:
5102 /* The valid usage section for this function says:
5103 *
5104 * "handleType must not be one of the handle types defined as
5105 * opaque."
5106 *
5107 * So opaque handle types fall into the default "unsupported" case.
5108 */
5109 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5110 }
5111 }
5112
5113 static VkResult radv_import_opaque_fd(struct radv_device *device,
5114 int fd,
5115 uint32_t *syncobj)
5116 {
5117 uint32_t syncobj_handle = 0;
5118 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5119 if (ret != 0)
5120 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5121
5122 if (*syncobj)
5123 device->ws->destroy_syncobj(device->ws, *syncobj);
5124
5125 *syncobj = syncobj_handle;
5126 close(fd);
5127
5128 return VK_SUCCESS;
5129 }
5130
5131 static VkResult radv_import_sync_fd(struct radv_device *device,
5132 int fd,
5133 uint32_t *syncobj)
5134 {
5135 /* If we create a syncobj we do it locally so that if we have an error, we don't
5136 * leave a syncobj in an undetermined state in the fence. */
5137 uint32_t syncobj_handle = *syncobj;
5138 if (!syncobj_handle) {
5139 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5140 if (ret) {
5141 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5142 }
5143 }
5144
5145 if (fd == -1) {
5146 device->ws->signal_syncobj(device->ws, syncobj_handle);
5147 } else {
5148 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5149 if (ret != 0)
5150 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5151 }
5152
5153 *syncobj = syncobj_handle;
5154 if (fd != -1)
5155 close(fd);
5156
5157 return VK_SUCCESS;
5158 }
5159
5160 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5161 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5162 {
5163 RADV_FROM_HANDLE(radv_device, device, _device);
5164 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5165 uint32_t *syncobj_dst = NULL;
5166
5167 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5168 syncobj_dst = &sem->temp_syncobj;
5169 } else {
5170 syncobj_dst = &sem->syncobj;
5171 }
5172
5173 switch(pImportSemaphoreFdInfo->handleType) {
5174 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5175 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5176 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5177 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5178 default:
5179 unreachable("Unhandled semaphore handle type");
5180 }
5181 }
5182
5183 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5184 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5185 int *pFd)
5186 {
5187 RADV_FROM_HANDLE(radv_device, device, _device);
5188 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5189 int ret;
5190 uint32_t syncobj_handle;
5191
5192 if (sem->temp_syncobj)
5193 syncobj_handle = sem->temp_syncobj;
5194 else
5195 syncobj_handle = sem->syncobj;
5196
5197 switch(pGetFdInfo->handleType) {
5198 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5199 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5200 break;
5201 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5202 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5203 if (!ret) {
5204 if (sem->temp_syncobj) {
5205 close (sem->temp_syncobj);
5206 sem->temp_syncobj = 0;
5207 } else {
5208 device->ws->reset_syncobj(device->ws, syncobj_handle);
5209 }
5210 }
5211 break;
5212 default:
5213 unreachable("Unhandled semaphore handle type");
5214 }
5215
5216 if (ret)
5217 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5218 return VK_SUCCESS;
5219 }
5220
5221 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5222 VkPhysicalDevice physicalDevice,
5223 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5224 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5225 {
5226 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5227
5228 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5229 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5230 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5231 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5232 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5233 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5234 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5235 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5236 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5237 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5238 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5239 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5240 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5241 } else {
5242 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5243 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5244 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5245 }
5246 }
5247
5248 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5249 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5250 {
5251 RADV_FROM_HANDLE(radv_device, device, _device);
5252 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5253 uint32_t *syncobj_dst = NULL;
5254
5255
5256 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5257 syncobj_dst = &fence->temp_syncobj;
5258 } else {
5259 syncobj_dst = &fence->syncobj;
5260 }
5261
5262 switch(pImportFenceFdInfo->handleType) {
5263 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5264 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5265 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5266 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5267 default:
5268 unreachable("Unhandled fence handle type");
5269 }
5270 }
5271
5272 VkResult radv_GetFenceFdKHR(VkDevice _device,
5273 const VkFenceGetFdInfoKHR *pGetFdInfo,
5274 int *pFd)
5275 {
5276 RADV_FROM_HANDLE(radv_device, device, _device);
5277 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5278 int ret;
5279 uint32_t syncobj_handle;
5280
5281 if (fence->temp_syncobj)
5282 syncobj_handle = fence->temp_syncobj;
5283 else
5284 syncobj_handle = fence->syncobj;
5285
5286 switch(pGetFdInfo->handleType) {
5287 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5288 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5289 break;
5290 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5291 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5292 if (!ret) {
5293 if (fence->temp_syncobj) {
5294 close (fence->temp_syncobj);
5295 fence->temp_syncobj = 0;
5296 } else {
5297 device->ws->reset_syncobj(device->ws, syncobj_handle);
5298 }
5299 }
5300 break;
5301 default:
5302 unreachable("Unhandled fence handle type");
5303 }
5304
5305 if (ret)
5306 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5307 return VK_SUCCESS;
5308 }
5309
5310 void radv_GetPhysicalDeviceExternalFenceProperties(
5311 VkPhysicalDevice physicalDevice,
5312 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5313 VkExternalFenceProperties *pExternalFenceProperties)
5314 {
5315 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5316
5317 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5318 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5319 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5320 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5321 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5322 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5323 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5324 } else {
5325 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5326 pExternalFenceProperties->compatibleHandleTypes = 0;
5327 pExternalFenceProperties->externalFenceFeatures = 0;
5328 }
5329 }
5330
5331 VkResult
5332 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5333 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5334 const VkAllocationCallbacks* pAllocator,
5335 VkDebugReportCallbackEXT* pCallback)
5336 {
5337 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5338 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5339 pCreateInfo, pAllocator, &instance->alloc,
5340 pCallback);
5341 }
5342
5343 void
5344 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5345 VkDebugReportCallbackEXT _callback,
5346 const VkAllocationCallbacks* pAllocator)
5347 {
5348 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5349 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5350 _callback, pAllocator, &instance->alloc);
5351 }
5352
5353 void
5354 radv_DebugReportMessageEXT(VkInstance _instance,
5355 VkDebugReportFlagsEXT flags,
5356 VkDebugReportObjectTypeEXT objectType,
5357 uint64_t object,
5358 size_t location,
5359 int32_t messageCode,
5360 const char* pLayerPrefix,
5361 const char* pMessage)
5362 {
5363 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5364 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5365 object, location, messageCode, pLayerPrefix, pMessage);
5366 }
5367
5368 void
5369 radv_GetDeviceGroupPeerMemoryFeatures(
5370 VkDevice device,
5371 uint32_t heapIndex,
5372 uint32_t localDeviceIndex,
5373 uint32_t remoteDeviceIndex,
5374 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5375 {
5376 assert(localDeviceIndex == remoteDeviceIndex);
5377
5378 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5379 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5380 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5381 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5382 }
5383
5384 static const VkTimeDomainEXT radv_time_domains[] = {
5385 VK_TIME_DOMAIN_DEVICE_EXT,
5386 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5387 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5388 };
5389
5390 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5391 VkPhysicalDevice physicalDevice,
5392 uint32_t *pTimeDomainCount,
5393 VkTimeDomainEXT *pTimeDomains)
5394 {
5395 int d;
5396 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5397
5398 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5399 vk_outarray_append(&out, i) {
5400 *i = radv_time_domains[d];
5401 }
5402 }
5403
5404 return vk_outarray_status(&out);
5405 }
5406
5407 static uint64_t
5408 radv_clock_gettime(clockid_t clock_id)
5409 {
5410 struct timespec current;
5411 int ret;
5412
5413 ret = clock_gettime(clock_id, &current);
5414 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5415 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5416 if (ret < 0)
5417 return 0;
5418
5419 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5420 }
5421
5422 VkResult radv_GetCalibratedTimestampsEXT(
5423 VkDevice _device,
5424 uint32_t timestampCount,
5425 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5426 uint64_t *pTimestamps,
5427 uint64_t *pMaxDeviation)
5428 {
5429 RADV_FROM_HANDLE(radv_device, device, _device);
5430 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5431 int d;
5432 uint64_t begin, end;
5433 uint64_t max_clock_period = 0;
5434
5435 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5436
5437 for (d = 0; d < timestampCount; d++) {
5438 switch (pTimestampInfos[d].timeDomain) {
5439 case VK_TIME_DOMAIN_DEVICE_EXT:
5440 pTimestamps[d] = device->ws->query_value(device->ws,
5441 RADEON_TIMESTAMP);
5442 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5443 max_clock_period = MAX2(max_clock_period, device_period);
5444 break;
5445 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5446 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5447 max_clock_period = MAX2(max_clock_period, 1);
5448 break;
5449
5450 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5451 pTimestamps[d] = begin;
5452 break;
5453 default:
5454 pTimestamps[d] = 0;
5455 break;
5456 }
5457 }
5458
5459 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5460
5461 /*
5462 * The maximum deviation is the sum of the interval over which we
5463 * perform the sampling and the maximum period of any sampled
5464 * clock. That's because the maximum skew between any two sampled
5465 * clock edges is when the sampled clock with the largest period is
5466 * sampled at the end of that period but right at the beginning of the
5467 * sampling interval and some other clock is sampled right at the
5468 * begining of its sampling period and right at the end of the
5469 * sampling interval. Let's assume the GPU has the longest clock
5470 * period and that the application is sampling GPU and monotonic:
5471 *
5472 * s e
5473 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5474 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5475 *
5476 * g
5477 * 0 1 2 3
5478 * GPU -----_____-----_____-----_____-----_____
5479 *
5480 * m
5481 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5482 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5483 *
5484 * Interval <----------------->
5485 * Deviation <-------------------------->
5486 *
5487 * s = read(raw) 2
5488 * g = read(GPU) 1
5489 * m = read(monotonic) 2
5490 * e = read(raw) b
5491 *
5492 * We round the sample interval up by one tick to cover sampling error
5493 * in the interval clock
5494 */
5495
5496 uint64_t sample_interval = end - begin + 1;
5497
5498 *pMaxDeviation = sample_interval + max_clock_period;
5499
5500 return VK_SUCCESS;
5501 }
5502
5503 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5504 VkPhysicalDevice physicalDevice,
5505 VkSampleCountFlagBits samples,
5506 VkMultisamplePropertiesEXT* pMultisampleProperties)
5507 {
5508 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5509 VK_SAMPLE_COUNT_4_BIT |
5510 VK_SAMPLE_COUNT_8_BIT)) {
5511 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5512 } else {
5513 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5514 }
5515 }