2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_is_mem_type_vram(enum radv_mem_type type
)
135 return type
== RADV_MEM_TYPE_VRAM
||
136 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
140 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
142 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
143 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
148 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
149 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
155 return type
== RADV_MEM_TYPE_GTT_CACHED
||
156 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
160 radv_is_mem_type_uncached(enum radv_mem_type type
)
162 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
163 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
164 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
169 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
172 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
173 uint64_t vram_size
= radv_get_vram_size(device
);
174 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
175 device
->memory_properties
.memoryHeapCount
= 0;
177 vram_index
= device
->memory_properties
.memoryHeapCount
++;
178 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
180 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 if (visible_vram_size
) {
184 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
185 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
186 .size
= visible_vram_size
,
187 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
190 if (device
->rad_info
.gart_size
> 0) {
191 gart_index
= device
->memory_properties
.memoryHeapCount
++;
192 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
193 .size
= device
->rad_info
.gart_size
,
194 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
199 unsigned type_count
= 0;
200 if (vram_index
>= 0) {
201 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
202 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
203 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
204 .heapIndex
= vram_index
,
207 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
212 .heapIndex
= gart_index
,
215 if (visible_vram_index
>= 0) {
216 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
221 .heapIndex
= visible_vram_index
,
224 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
230 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
231 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
234 .heapIndex
= gart_index
,
237 if (gart_index
>= 0) {
238 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
239 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
240 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
243 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
244 .heapIndex
= gart_index
,
247 device
->memory_properties
.memoryTypeCount
= type_count
;
249 if (device
->rad_info
.has_l2_uncached
) {
250 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
251 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
253 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
255 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
256 enum radv_mem_type mem_type_id
;
258 switch (device
->mem_type_indices
[i
]) {
259 case RADV_MEM_TYPE_VRAM
:
260 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
263 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
266 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
268 case RADV_MEM_TYPE_GTT_CACHED
:
269 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
272 unreachable("invalid memory type");
275 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
279 device
->mem_type_indices
[type_count
] = mem_type_id
;
280 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
281 .propertyFlags
= property_flags
,
282 .heapIndex
= mem_type
.heapIndex
,
286 device
->memory_properties
.memoryTypeCount
= type_count
;
291 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
293 const char *family
= getenv("RADV_FORCE_FAMILY");
299 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
300 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
301 /* Override family and chip_class. */
302 device
->rad_info
.family
= i
;
303 device
->rad_info
.name
= "OVERRIDDEN";
305 if (i
>= CHIP_NAVI10
)
306 device
->rad_info
.chip_class
= GFX10
;
307 else if (i
>= CHIP_VEGA10
)
308 device
->rad_info
.chip_class
= GFX9
;
309 else if (i
>= CHIP_TONGA
)
310 device
->rad_info
.chip_class
= GFX8
;
311 else if (i
>= CHIP_BONAIRE
)
312 device
->rad_info
.chip_class
= GFX7
;
314 device
->rad_info
.chip_class
= GFX6
;
316 /* Don't submit any IBs. */
317 device
->instance
->debug_flags
|= RADV_DEBUG_NOOP
;
322 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
327 radv_physical_device_init(struct radv_physical_device
*device
,
328 struct radv_instance
*instance
,
329 drmDevicePtr drm_device
)
331 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
333 drmVersionPtr version
;
337 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
339 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
340 radv_logi("Could not open device '%s'", path
);
342 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
345 version
= drmGetVersion(fd
);
349 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
350 radv_logi("Could not get the kernel driver version for device '%s'", path
);
352 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
353 "failed to get version %s: %m", path
);
356 if (strcmp(version
->name
, "amdgpu")) {
357 drmFreeVersion(version
);
360 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
361 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
363 return VK_ERROR_INCOMPATIBLE_DRIVER
;
365 drmFreeVersion(version
);
367 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
368 radv_logi("Found compatible device '%s'.", path
);
370 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
371 device
->instance
= instance
;
373 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
374 instance
->perftest_flags
);
376 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
380 if (instance
->enabled_extensions
.KHR_display
) {
381 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
382 if (master_fd
>= 0) {
383 uint32_t accel_working
= 0;
384 struct drm_amdgpu_info request
= {
385 .return_pointer
= (uintptr_t)&accel_working
,
386 .return_size
= sizeof(accel_working
),
387 .query
= AMDGPU_INFO_ACCEL_WORKING
390 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
397 device
->master_fd
= master_fd
;
398 device
->local_fd
= fd
;
399 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
401 radv_handle_env_var_force_family(device
);
403 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
405 snprintf(device
->name
, sizeof(device
->name
),
406 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
407 device
->rad_info
.name
);
409 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
410 device
->ws
->destroy(device
->ws
);
411 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
412 "cannot generate UUID");
416 /* These flags affect shader compilation. */
417 uint64_t shader_env_flags
=
418 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
419 (device
->use_aco
? 0x2 : 0);
421 /* The gpu id is already embedded in the uuid so we just pass "radv"
422 * when creating the cache.
424 char buf
[VK_UUID_SIZE
* 2 + 1];
425 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
426 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
428 if (device
->rad_info
.chip_class
< GFX8
)
429 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
431 radv_get_driver_uuid(&device
->driver_uuid
);
432 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
434 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
435 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
437 device
->dcc_msaa_allowed
=
438 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
440 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
441 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
443 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
444 device
->rad_info
.family
!= CHIP_NAVI14
&&
445 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
446 if (device
->use_aco
&& device
->use_ngg
) {
447 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
448 device
->use_ngg
= false;
451 device
->use_ngg_streamout
= false;
453 /* Determine the number of threads per wave for all stages. */
454 device
->cs_wave_size
= 64;
455 device
->ps_wave_size
= 64;
456 device
->ge_wave_size
= 64;
458 if (device
->rad_info
.chip_class
>= GFX10
) {
459 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
460 device
->cs_wave_size
= 32;
462 /* For pixel shaders, wave64 is recommanded. */
463 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
464 device
->ps_wave_size
= 32;
466 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
467 device
->ge_wave_size
= 32;
470 radv_physical_device_init_mem_types(device
);
471 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
473 device
->bus_info
= *drm_device
->businfo
.pci
;
475 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
476 ac_print_gpu_info(&device
->rad_info
);
478 /* The WSI is structured as a layer on top of the driver, so this has
479 * to be the last part of initialization (at least until we get other
482 result
= radv_init_wsi(device
);
483 if (result
!= VK_SUCCESS
) {
484 device
->ws
->destroy(device
->ws
);
485 vk_error(instance
, result
);
499 radv_physical_device_finish(struct radv_physical_device
*device
)
501 radv_finish_wsi(device
);
502 device
->ws
->destroy(device
->ws
);
503 disk_cache_destroy(device
->disk_cache
);
504 close(device
->local_fd
);
505 if (device
->master_fd
!= -1)
506 close(device
->master_fd
);
510 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
511 VkSystemAllocationScope allocationScope
)
517 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
518 size_t align
, VkSystemAllocationScope allocationScope
)
520 return realloc(pOriginal
, size
);
524 default_free_func(void *pUserData
, void *pMemory
)
529 static const VkAllocationCallbacks default_alloc
= {
531 .pfnAllocation
= default_alloc_func
,
532 .pfnReallocation
= default_realloc_func
,
533 .pfnFree
= default_free_func
,
536 static const struct debug_control radv_debug_options
[] = {
537 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
538 {"nodcc", RADV_DEBUG_NO_DCC
},
539 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
540 {"nocache", RADV_DEBUG_NO_CACHE
},
541 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
542 {"nohiz", RADV_DEBUG_NO_HIZ
},
543 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
544 {"allbos", RADV_DEBUG_ALL_BOS
},
545 {"noibs", RADV_DEBUG_NO_IBS
},
546 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
547 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
548 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
549 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
550 {"nosisched", RADV_DEBUG_NO_SISCHED
},
551 {"preoptir", RADV_DEBUG_PREOPTIR
},
552 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
553 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
554 {"info", RADV_DEBUG_INFO
},
555 {"errors", RADV_DEBUG_ERRORS
},
556 {"startup", RADV_DEBUG_STARTUP
},
557 {"checkir", RADV_DEBUG_CHECKIR
},
558 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
559 {"nobinning", RADV_DEBUG_NOBINNING
},
560 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
561 {"nongg", RADV_DEBUG_NO_NGG
},
562 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
563 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
564 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
565 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
566 {"noop", RADV_DEBUG_NOOP
},
571 radv_get_debug_option_name(int id
)
573 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
574 return radv_debug_options
[id
].string
;
577 static const struct debug_control radv_perftest_options
[] = {
578 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
579 {"sisched", RADV_PERFTEST_SISCHED
},
580 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
581 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
582 {"bolist", RADV_PERFTEST_BO_LIST
},
583 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
584 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
585 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
586 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
587 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
588 {"dfsm", RADV_PERFTEST_DFSM
},
589 {"aco", RADV_PERFTEST_ACO
},
594 radv_get_perftest_option_name(int id
)
596 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
597 return radv_perftest_options
[id
].string
;
601 radv_handle_per_app_options(struct radv_instance
*instance
,
602 const VkApplicationInfo
*info
)
604 const char *name
= info
? info
->pApplicationName
: NULL
;
609 if (!strcmp(name
, "Talos - Linux - 32bit") ||
610 !strcmp(name
, "Talos - Linux - 64bit")) {
611 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
612 /* Force enable LLVM sisched for Talos because it looks
613 * safe and it gives few more FPS.
615 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
617 } else if (!strcmp(name
, "DOOM_VFR")) {
618 /* Work around a Doom VFR game bug */
619 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
620 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
621 /* Workaround for a WaW hazard when LLVM moves/merges
622 * load/store memory operations.
623 * See https://reviews.llvm.org/D61313
625 if (LLVM_VERSION_MAJOR
< 9)
626 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
627 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
628 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
629 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
630 /* Force enable VK_AMD_shader_ballot because it looks
631 * safe and it gives a nice boost (+20% on Vega 56 at
632 * this time). It also prevents corruption on LLVM.
634 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
636 } else if (!strcmp(name
, "Fledge")) {
638 * Zero VRAM for "The Surge 2"
640 * This avoid a hang when when rendering any level. Likely
641 * uninitialized data in an indirect draw.
643 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
647 static int radv_get_instance_extension_index(const char *name
)
649 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
650 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
656 static const char radv_dri_options_xml
[] =
658 DRI_CONF_SECTION_PERFORMANCE
659 DRI_CONF_ADAPTIVE_SYNC("true")
660 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
661 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
664 DRI_CONF_SECTION_DEBUG
665 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
669 static void radv_init_dri_options(struct radv_instance
*instance
)
671 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
672 driParseConfigFiles(&instance
->dri_options
,
673 &instance
->available_dri_options
,
675 instance
->engineName
,
676 instance
->engineVersion
);
679 VkResult
radv_CreateInstance(
680 const VkInstanceCreateInfo
* pCreateInfo
,
681 const VkAllocationCallbacks
* pAllocator
,
682 VkInstance
* pInstance
)
684 struct radv_instance
*instance
;
687 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
689 uint32_t client_version
;
690 if (pCreateInfo
->pApplicationInfo
&&
691 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
692 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
694 client_version
= VK_API_VERSION_1_0
;
697 const char *engine_name
= NULL
;
698 uint32_t engine_version
= 0;
699 if (pCreateInfo
->pApplicationInfo
) {
700 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
701 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
704 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
705 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
707 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
709 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
712 instance
->alloc
= *pAllocator
;
714 instance
->alloc
= default_alloc
;
716 instance
->apiVersion
= client_version
;
717 instance
->physicalDeviceCount
= -1;
719 /* Get secure compile thread count. NOTE: We cap this at 32 */
720 #define MAX_SC_PROCS 32
721 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
723 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
725 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
728 /* Disable memory cache when secure compile is set */
729 if (radv_device_use_secure_compile(instance
))
730 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
732 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
733 radv_perftest_options
);
735 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
736 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
738 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
739 radv_logi("Created an instance");
741 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
742 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
743 int index
= radv_get_instance_extension_index(ext_name
);
745 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
746 vk_free2(&default_alloc
, pAllocator
, instance
);
747 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
750 instance
->enabled_extensions
.extensions
[index
] = true;
753 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
754 if (result
!= VK_SUCCESS
) {
755 vk_free2(&default_alloc
, pAllocator
, instance
);
756 return vk_error(instance
, result
);
759 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
760 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
761 instance
->engineVersion
= engine_version
;
763 glsl_type_singleton_init_or_ref();
765 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
767 radv_init_dri_options(instance
);
768 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
770 *pInstance
= radv_instance_to_handle(instance
);
775 void radv_DestroyInstance(
776 VkInstance _instance
,
777 const VkAllocationCallbacks
* pAllocator
)
779 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
784 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
785 radv_physical_device_finish(instance
->physicalDevices
+ i
);
788 vk_free(&instance
->alloc
, instance
->engineName
);
790 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
792 glsl_type_singleton_decref();
794 driDestroyOptionCache(&instance
->dri_options
);
795 driDestroyOptionInfo(&instance
->available_dri_options
);
797 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
799 vk_free(&instance
->alloc
, instance
);
803 radv_enumerate_devices(struct radv_instance
*instance
)
805 /* TODO: Check for more devices ? */
806 drmDevicePtr devices
[8];
807 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
810 instance
->physicalDeviceCount
= 0;
812 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
814 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
815 radv_logi("Found %d drm nodes", max_devices
);
818 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
820 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
821 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
822 devices
[i
]->bustype
== DRM_BUS_PCI
&&
823 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
825 result
= radv_physical_device_init(instance
->physicalDevices
+
826 instance
->physicalDeviceCount
,
829 if (result
== VK_SUCCESS
)
830 ++instance
->physicalDeviceCount
;
831 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
835 drmFreeDevices(devices
, max_devices
);
840 VkResult
radv_EnumeratePhysicalDevices(
841 VkInstance _instance
,
842 uint32_t* pPhysicalDeviceCount
,
843 VkPhysicalDevice
* pPhysicalDevices
)
845 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
848 if (instance
->physicalDeviceCount
< 0) {
849 result
= radv_enumerate_devices(instance
);
850 if (result
!= VK_SUCCESS
&&
851 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
855 if (!pPhysicalDevices
) {
856 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
858 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
859 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
860 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
863 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
867 VkResult
radv_EnumeratePhysicalDeviceGroups(
868 VkInstance _instance
,
869 uint32_t* pPhysicalDeviceGroupCount
,
870 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
872 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
875 if (instance
->physicalDeviceCount
< 0) {
876 result
= radv_enumerate_devices(instance
);
877 if (result
!= VK_SUCCESS
&&
878 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
882 if (!pPhysicalDeviceGroupProperties
) {
883 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
885 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
886 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
887 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
888 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
889 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
892 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
896 void radv_GetPhysicalDeviceFeatures(
897 VkPhysicalDevice physicalDevice
,
898 VkPhysicalDeviceFeatures
* pFeatures
)
900 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
901 memset(pFeatures
, 0, sizeof(*pFeatures
));
903 *pFeatures
= (VkPhysicalDeviceFeatures
) {
904 .robustBufferAccess
= true,
905 .fullDrawIndexUint32
= true,
906 .imageCubeArray
= true,
907 .independentBlend
= true,
908 .geometryShader
= true,
909 .tessellationShader
= true,
910 .sampleRateShading
= true,
911 .dualSrcBlend
= true,
913 .multiDrawIndirect
= true,
914 .drawIndirectFirstInstance
= true,
916 .depthBiasClamp
= true,
917 .fillModeNonSolid
= true,
922 .multiViewport
= true,
923 .samplerAnisotropy
= true,
924 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
925 .textureCompressionASTC_LDR
= false,
926 .textureCompressionBC
= true,
927 .occlusionQueryPrecise
= true,
928 .pipelineStatisticsQuery
= true,
929 .vertexPipelineStoresAndAtomics
= true,
930 .fragmentStoresAndAtomics
= true,
931 .shaderTessellationAndGeometryPointSize
= true,
932 .shaderImageGatherExtended
= true,
933 .shaderStorageImageExtendedFormats
= true,
934 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
935 .shaderUniformBufferArrayDynamicIndexing
= true,
936 .shaderSampledImageArrayDynamicIndexing
= true,
937 .shaderStorageBufferArrayDynamicIndexing
= true,
938 .shaderStorageImageArrayDynamicIndexing
= true,
939 .shaderStorageImageReadWithoutFormat
= true,
940 .shaderStorageImageWriteWithoutFormat
= true,
941 .shaderClipDistance
= true,
942 .shaderCullDistance
= true,
943 .shaderFloat64
= true,
945 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
946 .sparseBinding
= true,
947 .variableMultisampleRate
= true,
948 .inheritedQueries
= true,
952 void radv_GetPhysicalDeviceFeatures2(
953 VkPhysicalDevice physicalDevice
,
954 VkPhysicalDeviceFeatures2
*pFeatures
)
956 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
957 vk_foreach_struct(ext
, pFeatures
->pNext
) {
958 switch (ext
->sType
) {
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
960 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
961 features
->variablePointersStorageBuffer
= true;
962 features
->variablePointers
= true;
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
966 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
967 features
->multiview
= true;
968 features
->multiviewGeometryShader
= true;
969 features
->multiviewTessellationShader
= true;
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
973 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
974 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
975 features
->shaderDrawParameters
= true;
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
979 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
980 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
981 features
->protectedMemory
= false;
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
985 VkPhysicalDevice16BitStorageFeatures
*features
=
986 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
987 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
988 features
->storageBuffer16BitAccess
= enabled
;
989 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
990 features
->storagePushConstant16
= enabled
;
991 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
995 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
996 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
997 features
->samplerYcbcrConversion
= true;
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1001 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1002 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1003 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1004 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1005 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1006 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1007 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1008 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1009 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1010 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1011 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1012 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1013 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1014 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1015 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1016 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1017 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1018 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1019 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1020 features
->descriptorBindingPartiallyBound
= true;
1021 features
->descriptorBindingVariableDescriptorCount
= true;
1022 features
->runtimeDescriptorArray
= true;
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1026 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1027 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1028 features
->conditionalRendering
= true;
1029 features
->inheritedConditionalRendering
= false;
1032 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1033 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1034 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1035 features
->vertexAttributeInstanceRateDivisor
= true;
1036 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1040 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1041 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1042 features
->transformFeedback
= true;
1043 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1047 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1048 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1049 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1053 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1054 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1055 features
->memoryPriority
= true;
1058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1059 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1060 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1061 features
->bufferDeviceAddress
= true;
1062 features
->bufferDeviceAddressCaptureReplay
= false;
1063 features
->bufferDeviceAddressMultiDevice
= false;
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1067 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1068 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1069 features
->bufferDeviceAddress
= true;
1070 features
->bufferDeviceAddressCaptureReplay
= false;
1071 features
->bufferDeviceAddressMultiDevice
= false;
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1075 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1076 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1077 features
->depthClipEnable
= true;
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1081 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1082 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1083 features
->hostQueryReset
= true;
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1087 VkPhysicalDevice8BitStorageFeatures
*features
=
1088 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1089 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1090 features
->storageBuffer8BitAccess
= enabled
;
1091 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1092 features
->storagePushConstant8
= enabled
;
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1096 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1097 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1098 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1099 features
->shaderInt8
= !pdevice
->use_aco
;
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1103 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1104 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1105 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1106 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1110 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1111 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1112 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1116 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1117 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1119 features
->inlineUniformBlock
= true;
1120 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1123 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1124 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1125 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1126 features
->computeDerivativeGroupQuads
= false;
1127 features
->computeDerivativeGroupLinear
= true;
1130 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1131 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1132 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1133 features
->ycbcrImageArrays
= true;
1136 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1137 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1138 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1139 features
->uniformBufferStandardLayout
= true;
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1143 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1144 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1145 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1149 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1150 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1151 features
->imagelessFramebuffer
= true;
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1155 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1156 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1157 features
->pipelineExecutableInfo
= true;
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1161 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1162 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1163 features
->shaderSubgroupClock
= true;
1164 features
->shaderDeviceClock
= false;
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1168 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1169 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1170 features
->texelBufferAlignment
= true;
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1174 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1175 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1176 features
->timelineSemaphore
= true;
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1180 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1181 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1182 features
->subgroupSizeControl
= true;
1183 features
->computeFullSubgroups
= true;
1186 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1187 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1188 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1189 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1193 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1194 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1195 features
->shaderSubgroupExtendedTypes
= true;
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1199 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1200 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1201 features
->separateDepthStencilLayouts
= true;
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1205 VkPhysicalDeviceVulkan11Features
*features
=
1206 (VkPhysicalDeviceVulkan11Features
*)ext
;
1207 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1208 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1209 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1210 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1211 features
->multiview
= true;
1212 features
->multiviewGeometryShader
= true;
1213 features
->multiviewTessellationShader
= true;
1214 features
->variablePointersStorageBuffer
= true;
1215 features
->variablePointers
= true;
1216 features
->protectedMemory
= false;
1217 features
->samplerYcbcrConversion
= true;
1218 features
->shaderDrawParameters
= true;
1221 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1222 VkPhysicalDeviceVulkan12Features
*features
=
1223 (VkPhysicalDeviceVulkan12Features
*)ext
;
1224 features
->samplerMirrorClampToEdge
= true;
1225 features
->drawIndirectCount
= true;
1226 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1227 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1228 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1229 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1230 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1231 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1232 features
->shaderInt8
= !pdevice
->use_aco
;
1233 features
->descriptorIndexing
= true;
1234 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1235 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1236 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1237 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1238 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1239 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1240 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1241 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1242 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1243 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1244 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1245 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1246 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1247 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1248 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1249 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1250 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1251 features
->descriptorBindingPartiallyBound
= true;
1252 features
->descriptorBindingVariableDescriptorCount
= true;
1253 features
->runtimeDescriptorArray
= true;
1254 features
->samplerFilterMinmax
= pdevice
->rad_info
.chip_class
>= GFX7
;
1255 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1256 features
->imagelessFramebuffer
= true;
1257 features
->uniformBufferStandardLayout
= true;
1258 features
->shaderSubgroupExtendedTypes
= true;
1259 features
->separateDepthStencilLayouts
= true;
1260 features
->hostQueryReset
= true;
1261 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1262 features
->bufferDeviceAddress
= true;
1263 features
->bufferDeviceAddressCaptureReplay
= false;
1264 features
->bufferDeviceAddressMultiDevice
= false;
1265 features
->vulkanMemoryModel
= false;
1266 features
->vulkanMemoryModelDeviceScope
= false;
1267 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1268 features
->shaderOutputViewportIndex
= true;
1269 features
->shaderOutputLayer
= true;
1270 features
->subgroupBroadcastDynamicId
= true;
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1274 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1275 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1276 features
->rectangularLines
= false;
1277 features
->bresenhamLines
= true;
1278 features
->smoothLines
= false;
1279 features
->stippledRectangularLines
= false;
1280 features
->stippledBresenhamLines
= true;
1281 features
->stippledSmoothLines
= false;
1288 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1292 radv_max_descriptor_set_size()
1294 /* make sure that the entire descriptor set is addressable with a signed
1295 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1296 * be at most 2 GiB. the combined image & samples object count as one of
1297 * both. This limit is for the pipeline layout, not for the set layout, but
1298 * there is no set limit, so we just set a pipeline limit. I don't think
1299 * any app is going to hit this soon. */
1300 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1301 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1302 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1303 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1304 32 /* sampler, largest when combined with image */ +
1305 64 /* sampled image */ +
1306 64 /* storage image */);
1309 void radv_GetPhysicalDeviceProperties(
1310 VkPhysicalDevice physicalDevice
,
1311 VkPhysicalDeviceProperties
* pProperties
)
1313 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1314 VkSampleCountFlags sample_counts
= 0xf;
1316 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1318 VkPhysicalDeviceLimits limits
= {
1319 .maxImageDimension1D
= (1 << 14),
1320 .maxImageDimension2D
= (1 << 14),
1321 .maxImageDimension3D
= (1 << 11),
1322 .maxImageDimensionCube
= (1 << 14),
1323 .maxImageArrayLayers
= (1 << 11),
1324 .maxTexelBufferElements
= 128 * 1024 * 1024,
1325 .maxUniformBufferRange
= UINT32_MAX
,
1326 .maxStorageBufferRange
= UINT32_MAX
,
1327 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1328 .maxMemoryAllocationCount
= UINT32_MAX
,
1329 .maxSamplerAllocationCount
= 64 * 1024,
1330 .bufferImageGranularity
= 64, /* A cache line */
1331 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1332 .maxBoundDescriptorSets
= MAX_SETS
,
1333 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1334 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1335 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1336 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1337 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1338 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1339 .maxPerStageResources
= max_descriptor_set_size
,
1340 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1341 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1342 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1343 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1344 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1345 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1346 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1347 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1348 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1349 .maxVertexInputBindings
= MAX_VBS
,
1350 .maxVertexInputAttributeOffset
= 2047,
1351 .maxVertexInputBindingStride
= 2048,
1352 .maxVertexOutputComponents
= 128,
1353 .maxTessellationGenerationLevel
= 64,
1354 .maxTessellationPatchSize
= 32,
1355 .maxTessellationControlPerVertexInputComponents
= 128,
1356 .maxTessellationControlPerVertexOutputComponents
= 128,
1357 .maxTessellationControlPerPatchOutputComponents
= 120,
1358 .maxTessellationControlTotalOutputComponents
= 4096,
1359 .maxTessellationEvaluationInputComponents
= 128,
1360 .maxTessellationEvaluationOutputComponents
= 128,
1361 .maxGeometryShaderInvocations
= 127,
1362 .maxGeometryInputComponents
= 64,
1363 .maxGeometryOutputComponents
= 128,
1364 .maxGeometryOutputVertices
= 256,
1365 .maxGeometryTotalOutputComponents
= 1024,
1366 .maxFragmentInputComponents
= 128,
1367 .maxFragmentOutputAttachments
= 8,
1368 .maxFragmentDualSrcAttachments
= 1,
1369 .maxFragmentCombinedOutputResources
= 8,
1370 .maxComputeSharedMemorySize
= 32768,
1371 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1372 .maxComputeWorkGroupInvocations
= 1024,
1373 .maxComputeWorkGroupSize
= {
1378 .subPixelPrecisionBits
= 8,
1379 .subTexelPrecisionBits
= 8,
1380 .mipmapPrecisionBits
= 8,
1381 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1382 .maxDrawIndirectCount
= UINT32_MAX
,
1383 .maxSamplerLodBias
= 16,
1384 .maxSamplerAnisotropy
= 16,
1385 .maxViewports
= MAX_VIEWPORTS
,
1386 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1387 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1388 .viewportSubPixelBits
= 8,
1389 .minMemoryMapAlignment
= 4096, /* A page */
1390 .minTexelBufferOffsetAlignment
= 4,
1391 .minUniformBufferOffsetAlignment
= 4,
1392 .minStorageBufferOffsetAlignment
= 4,
1393 .minTexelOffset
= -32,
1394 .maxTexelOffset
= 31,
1395 .minTexelGatherOffset
= -32,
1396 .maxTexelGatherOffset
= 31,
1397 .minInterpolationOffset
= -2,
1398 .maxInterpolationOffset
= 2,
1399 .subPixelInterpolationOffsetBits
= 8,
1400 .maxFramebufferWidth
= (1 << 14),
1401 .maxFramebufferHeight
= (1 << 14),
1402 .maxFramebufferLayers
= (1 << 10),
1403 .framebufferColorSampleCounts
= sample_counts
,
1404 .framebufferDepthSampleCounts
= sample_counts
,
1405 .framebufferStencilSampleCounts
= sample_counts
,
1406 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1407 .maxColorAttachments
= MAX_RTS
,
1408 .sampledImageColorSampleCounts
= sample_counts
,
1409 .sampledImageIntegerSampleCounts
= sample_counts
,
1410 .sampledImageDepthSampleCounts
= sample_counts
,
1411 .sampledImageStencilSampleCounts
= sample_counts
,
1412 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1413 .maxSampleMaskWords
= 1,
1414 .timestampComputeAndGraphics
= true,
1415 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1416 .maxClipDistances
= 8,
1417 .maxCullDistances
= 8,
1418 .maxCombinedClipAndCullDistances
= 8,
1419 .discreteQueuePriorities
= 2,
1420 .pointSizeRange
= { 0.0, 8192.0 },
1421 .lineWidthRange
= { 0.0, 8192.0 },
1422 .pointSizeGranularity
= (1.0 / 8.0),
1423 .lineWidthGranularity
= (1.0 / 8.0),
1424 .strictLines
= false, /* FINISHME */
1425 .standardSampleLocations
= true,
1426 .optimalBufferCopyOffsetAlignment
= 128,
1427 .optimalBufferCopyRowPitchAlignment
= 128,
1428 .nonCoherentAtomSize
= 64,
1431 *pProperties
= (VkPhysicalDeviceProperties
) {
1432 .apiVersion
= radv_physical_device_api_version(pdevice
),
1433 .driverVersion
= vk_get_driver_version(),
1434 .vendorID
= ATI_VENDOR_ID
,
1435 .deviceID
= pdevice
->rad_info
.pci_id
,
1436 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1438 .sparseProperties
= {0},
1441 strcpy(pProperties
->deviceName
, pdevice
->name
);
1442 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1446 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1447 VkPhysicalDeviceVulkan11Properties
*p
)
1449 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1451 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1452 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1453 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1454 /* The LUID is for Windows. */
1455 p
->deviceLUIDValid
= false;
1456 p
->deviceNodeMask
= 0;
1458 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1459 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1460 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1461 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1462 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1463 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1464 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1465 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1467 if (pdevice
->rad_info
.chip_class
== GFX8
||
1468 pdevice
->rad_info
.chip_class
== GFX9
) {
1469 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1470 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1472 p
->subgroupQuadOperationsInAllStages
= true;
1474 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1475 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1476 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1477 p
->protectedNoFault
= false;
1478 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1479 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1483 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1484 VkPhysicalDeviceVulkan12Properties
*p
)
1486 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1488 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1489 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1490 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1491 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1492 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1493 p
->conformanceVersion
= (VkConformanceVersion
) {
1500 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1501 * controlled by the same config register.
1503 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1504 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1506 /* Do not allow both preserving and flushing denorms because different
1507 * shaders in the same pipeline can have different settings and this
1508 * won't work for merged shaders. To make it work, this requires LLVM
1509 * support for changing the register. The same logic applies for the
1510 * rounding modes because they are configured with the same config
1511 * register. TODO: we can enable a lot of these for ACO when it
1512 * supports all stages.
1514 p
->shaderDenormFlushToZeroFloat32
= true;
1515 p
->shaderDenormPreserveFloat32
= false;
1516 p
->shaderRoundingModeRTEFloat32
= true;
1517 p
->shaderRoundingModeRTZFloat32
= false;
1518 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1520 p
->shaderDenormFlushToZeroFloat16
= false;
1521 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1522 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1523 p
->shaderRoundingModeRTZFloat16
= false;
1524 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1526 p
->shaderDenormFlushToZeroFloat64
= false;
1527 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1528 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1529 p
->shaderRoundingModeRTZFloat64
= false;
1530 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1532 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1533 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1534 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1535 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1536 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1537 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1538 p
->robustBufferAccessUpdateAfterBind
= false;
1539 p
->quadDivergentImplicitLod
= false;
1541 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1542 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1543 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1544 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1545 32 /* sampler, largest when combined with image */ +
1546 64 /* sampled image */ +
1547 64 /* storage image */);
1548 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1549 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1550 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1551 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1552 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1553 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1554 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1555 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1556 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1557 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1558 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1559 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1560 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1561 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1562 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1564 /* We support all of the depth resolve modes */
1565 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1566 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1567 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1568 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1570 /* Average doesn't make sense for stencil so we don't support that */
1571 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1572 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1573 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1575 p
->independentResolveNone
= true;
1576 p
->independentResolve
= true;
1578 /* GFX6-8 only support single channel min/max filter. */
1579 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1580 p
->filterMinmaxSingleComponentFormats
= true;
1582 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1584 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1587 void radv_GetPhysicalDeviceProperties2(
1588 VkPhysicalDevice physicalDevice
,
1589 VkPhysicalDeviceProperties2
*pProperties
)
1591 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1592 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1594 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1595 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1597 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1599 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1600 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1602 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1604 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1605 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1606 sizeof(core_##major##_##minor.core_property))
1608 #define CORE_PROPERTY(major, minor, property) \
1609 CORE_RENAMED_PROPERTY(major, minor, property, property)
1611 vk_foreach_struct(ext
, pProperties
->pNext
) {
1612 switch (ext
->sType
) {
1613 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1614 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1615 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1616 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1619 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1620 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1621 CORE_PROPERTY(1, 1, deviceUUID
);
1622 CORE_PROPERTY(1, 1, driverUUID
);
1623 CORE_PROPERTY(1, 1, deviceLUID
);
1624 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1627 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1628 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1629 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1630 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1633 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1634 VkPhysicalDevicePointClippingProperties
*properties
=
1635 (VkPhysicalDevicePointClippingProperties
*)ext
;
1636 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1639 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1640 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1641 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1642 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1645 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1646 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1647 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1648 properties
->minImportedHostPointerAlignment
= 4096;
1651 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1652 VkPhysicalDeviceSubgroupProperties
*properties
=
1653 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1654 CORE_PROPERTY(1, 1, subgroupSize
);
1655 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1656 subgroupSupportedStages
);
1657 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1658 subgroupSupportedOperations
);
1659 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1660 subgroupQuadOperationsInAllStages
);
1663 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1664 VkPhysicalDeviceMaintenance3Properties
*properties
=
1665 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1666 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1667 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1670 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1671 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1672 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1673 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1674 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1677 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1678 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1679 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1681 /* Shader engines. */
1682 properties
->shaderEngineCount
=
1683 pdevice
->rad_info
.max_se
;
1684 properties
->shaderArraysPerEngineCount
=
1685 pdevice
->rad_info
.max_sh_per_se
;
1686 properties
->computeUnitsPerShaderArray
=
1687 pdevice
->rad_info
.num_good_cu_per_sh
;
1688 properties
->simdPerComputeUnit
= 4;
1689 properties
->wavefrontsPerSimd
=
1690 pdevice
->rad_info
.family
== CHIP_TONGA
||
1691 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1692 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1693 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1694 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1695 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1696 properties
->wavefrontSize
= 64;
1699 properties
->sgprsPerSimd
=
1700 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1701 properties
->minSgprAllocation
=
1702 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1703 properties
->maxSgprAllocation
=
1704 pdevice
->rad_info
.family
== CHIP_TONGA
||
1705 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1706 properties
->sgprAllocationGranularity
=
1707 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1710 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1711 properties
->minVgprAllocation
= 4;
1712 properties
->maxVgprAllocation
= 256;
1713 properties
->vgprAllocationGranularity
= 4;
1716 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1717 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1718 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1720 properties
->shaderCoreFeatures
= 0;
1721 properties
->activeComputeUnitCount
=
1722 pdevice
->rad_info
.num_good_compute_units
;
1725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1726 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1727 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1728 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1732 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1733 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1734 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1735 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1736 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1737 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1738 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1739 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1740 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1741 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1742 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1743 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1744 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1745 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1746 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1747 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1748 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1749 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1750 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1751 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1752 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1753 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1754 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1755 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1756 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1760 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1761 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1762 CORE_PROPERTY(1, 1, protectedNoFault
);
1765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1766 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1767 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1768 properties
->primitiveOverestimationSize
= 0;
1769 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1770 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1771 properties
->primitiveUnderestimation
= false;
1772 properties
->conservativePointAndLineRasterization
= false;
1773 properties
->degenerateTrianglesRasterized
= false;
1774 properties
->degenerateLinesRasterized
= false;
1775 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1776 properties
->conservativeRasterizationPostDepthCoverage
= false;
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1780 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1781 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1782 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1783 properties
->pciBus
= pdevice
->bus_info
.bus
;
1784 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1785 properties
->pciFunction
= pdevice
->bus_info
.func
;
1788 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1789 VkPhysicalDeviceDriverProperties
*properties
=
1790 (VkPhysicalDeviceDriverProperties
*) ext
;
1791 CORE_PROPERTY(1, 2, driverID
);
1792 CORE_PROPERTY(1, 2, driverName
);
1793 CORE_PROPERTY(1, 2, driverInfo
);
1794 CORE_PROPERTY(1, 2, conformanceVersion
);
1797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1798 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1799 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1800 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1801 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1802 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1803 properties
->maxTransformFeedbackStreamDataSize
= 512;
1804 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1805 properties
->maxTransformFeedbackBufferDataStride
= 512;
1806 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1807 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1808 properties
->transformFeedbackRasterizationStreamSelect
= false;
1809 properties
->transformFeedbackDraw
= true;
1812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1813 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1814 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1816 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1817 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1818 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1819 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1820 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1824 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1825 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1826 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1827 VK_SAMPLE_COUNT_4_BIT
|
1828 VK_SAMPLE_COUNT_8_BIT
;
1829 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1830 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1831 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1832 properties
->sampleLocationSubPixelBits
= 4;
1833 properties
->variableSampleLocations
= false;
1836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1837 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1838 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1839 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1840 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1841 CORE_PROPERTY(1, 2, independentResolveNone
);
1842 CORE_PROPERTY(1, 2, independentResolve
);
1845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1846 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1847 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1848 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1849 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1850 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1851 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1855 VkPhysicalDeviceFloatControlsProperties
*properties
=
1856 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1857 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1858 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1859 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1860 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1861 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1862 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1863 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1864 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1865 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1866 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1867 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1868 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1869 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1870 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1871 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1872 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1873 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1877 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1878 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1879 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1883 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1884 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1885 props
->minSubgroupSize
= 64;
1886 props
->maxSubgroupSize
= 64;
1887 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1888 props
->requiredSubgroupSizeStages
= 0;
1890 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1891 /* Only GFX10+ supports wave32. */
1892 props
->minSubgroupSize
= 32;
1893 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1897 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1898 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1901 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1904 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1905 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1906 props
->lineSubPixelPrecisionBits
= 4;
1915 static void radv_get_physical_device_queue_family_properties(
1916 struct radv_physical_device
* pdevice
,
1918 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1920 int num_queue_families
= 1;
1922 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1923 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1924 num_queue_families
++;
1926 if (pQueueFamilyProperties
== NULL
) {
1927 *pCount
= num_queue_families
;
1936 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1937 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1938 VK_QUEUE_COMPUTE_BIT
|
1939 VK_QUEUE_TRANSFER_BIT
|
1940 VK_QUEUE_SPARSE_BINDING_BIT
,
1942 .timestampValidBits
= 64,
1943 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1948 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1949 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1950 if (*pCount
> idx
) {
1951 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1952 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1953 VK_QUEUE_TRANSFER_BIT
|
1954 VK_QUEUE_SPARSE_BINDING_BIT
,
1955 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1956 .timestampValidBits
= 64,
1957 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1965 void radv_GetPhysicalDeviceQueueFamilyProperties(
1966 VkPhysicalDevice physicalDevice
,
1968 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1970 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1971 if (!pQueueFamilyProperties
) {
1972 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1975 VkQueueFamilyProperties
*properties
[] = {
1976 pQueueFamilyProperties
+ 0,
1977 pQueueFamilyProperties
+ 1,
1978 pQueueFamilyProperties
+ 2,
1980 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1981 assert(*pCount
<= 3);
1984 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1985 VkPhysicalDevice physicalDevice
,
1987 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1989 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1990 if (!pQueueFamilyProperties
) {
1991 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1994 VkQueueFamilyProperties
*properties
[] = {
1995 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1996 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1997 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1999 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2000 assert(*pCount
<= 3);
2003 void radv_GetPhysicalDeviceMemoryProperties(
2004 VkPhysicalDevice physicalDevice
,
2005 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2007 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2009 *pMemoryProperties
= physical_device
->memory_properties
;
2013 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2014 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2016 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2017 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2018 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2019 uint64_t vram_size
= radv_get_vram_size(device
);
2020 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2021 uint64_t heap_budget
, heap_usage
;
2023 /* For all memory heaps, the computation of budget is as follow:
2024 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2026 * The Vulkan spec 1.1.97 says that the budget should include any
2027 * currently allocated device memory.
2029 * Note that the application heap usages are not really accurate (eg.
2030 * in presence of shared buffers).
2032 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2033 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2035 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2036 heap_usage
= device
->ws
->query_value(device
->ws
,
2037 RADEON_ALLOCATED_VRAM
);
2039 heap_budget
= vram_size
-
2040 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2043 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2044 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2045 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2046 heap_usage
= device
->ws
->query_value(device
->ws
,
2047 RADEON_ALLOCATED_VRAM_VIS
);
2049 heap_budget
= visible_vram_size
-
2050 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2053 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2054 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2055 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2056 heap_usage
= device
->ws
->query_value(device
->ws
,
2057 RADEON_ALLOCATED_GTT
);
2059 heap_budget
= gtt_size
-
2060 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2063 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2064 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2068 /* The heapBudget and heapUsage values must be zero for array elements
2069 * greater than or equal to
2070 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2072 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2073 memoryBudget
->heapBudget
[i
] = 0;
2074 memoryBudget
->heapUsage
[i
] = 0;
2078 void radv_GetPhysicalDeviceMemoryProperties2(
2079 VkPhysicalDevice physicalDevice
,
2080 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2082 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2083 &pMemoryProperties
->memoryProperties
);
2085 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2086 vk_find_struct(pMemoryProperties
->pNext
,
2087 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2089 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2092 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2094 VkExternalMemoryHandleTypeFlagBits handleType
,
2095 const void *pHostPointer
,
2096 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2098 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2102 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2103 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2104 uint32_t memoryTypeBits
= 0;
2105 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2106 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2107 memoryTypeBits
= (1 << i
);
2111 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2115 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2119 static enum radeon_ctx_priority
2120 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2122 /* Default to MEDIUM when a specific global priority isn't requested */
2124 return RADEON_CTX_PRIORITY_MEDIUM
;
2126 switch(pObj
->globalPriority
) {
2127 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2128 return RADEON_CTX_PRIORITY_REALTIME
;
2129 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2130 return RADEON_CTX_PRIORITY_HIGH
;
2131 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2132 return RADEON_CTX_PRIORITY_MEDIUM
;
2133 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2134 return RADEON_CTX_PRIORITY_LOW
;
2136 unreachable("Illegal global priority value");
2137 return RADEON_CTX_PRIORITY_INVALID
;
2142 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2143 uint32_t queue_family_index
, int idx
,
2144 VkDeviceQueueCreateFlags flags
,
2145 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2147 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2148 queue
->device
= device
;
2149 queue
->queue_family_index
= queue_family_index
;
2150 queue
->queue_idx
= idx
;
2151 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2152 queue
->flags
= flags
;
2154 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2156 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2158 list_inithead(&queue
->pending_submissions
);
2159 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2165 radv_queue_finish(struct radv_queue
*queue
)
2167 pthread_mutex_destroy(&queue
->pending_mutex
);
2170 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2172 if (queue
->initial_full_flush_preamble_cs
)
2173 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2174 if (queue
->initial_preamble_cs
)
2175 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2176 if (queue
->continue_preamble_cs
)
2177 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2178 if (queue
->descriptor_bo
)
2179 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2180 if (queue
->scratch_bo
)
2181 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2182 if (queue
->esgs_ring_bo
)
2183 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2184 if (queue
->gsvs_ring_bo
)
2185 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2186 if (queue
->tess_rings_bo
)
2187 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2189 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2190 if (queue
->gds_oa_bo
)
2191 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2192 if (queue
->compute_scratch_bo
)
2193 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2197 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2199 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2200 bo_list
->list
.count
= bo_list
->capacity
= 0;
2201 bo_list
->list
.bos
= NULL
;
2205 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2207 free(bo_list
->list
.bos
);
2208 pthread_mutex_destroy(&bo_list
->mutex
);
2211 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2212 struct radeon_winsys_bo
*bo
)
2214 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2219 if (unlikely(!device
->use_global_bo_list
))
2222 pthread_mutex_lock(&bo_list
->mutex
);
2223 if (bo_list
->list
.count
== bo_list
->capacity
) {
2224 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2225 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2228 pthread_mutex_unlock(&bo_list
->mutex
);
2229 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2232 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2233 bo_list
->capacity
= capacity
;
2236 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2237 pthread_mutex_unlock(&bo_list
->mutex
);
2241 static void radv_bo_list_remove(struct radv_device
*device
,
2242 struct radeon_winsys_bo
*bo
)
2244 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2249 if (unlikely(!device
->use_global_bo_list
))
2252 pthread_mutex_lock(&bo_list
->mutex
);
2253 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2254 if (bo_list
->list
.bos
[i
] == bo
) {
2255 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2256 --bo_list
->list
.count
;
2260 pthread_mutex_unlock(&bo_list
->mutex
);
2264 radv_device_init_gs_info(struct radv_device
*device
)
2266 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2267 device
->physical_device
->rad_info
.family
);
2270 static int radv_get_device_extension_index(const char *name
)
2272 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2273 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2280 radv_get_int_debug_option(const char *name
, int default_value
)
2287 result
= default_value
;
2291 result
= strtol(str
, &endptr
, 0);
2292 if (str
== endptr
) {
2293 /* No digits founs. */
2294 result
= default_value
;
2301 static int install_seccomp_filter() {
2303 struct sock_filter filter
[] = {
2304 /* Check arch is 64bit x86 */
2305 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2306 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2308 /* Futex is required for mutex locks */
2309 #if defined __NR__newselect
2310 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2311 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2312 #elif defined __NR_select
2313 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2314 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2316 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2317 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2320 /* Allow system exit calls for the forked process */
2321 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2322 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2324 /* Allow system read calls */
2325 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2326 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2328 /* Allow system write calls */
2329 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2330 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2332 /* Allow system brk calls (we need this for malloc) */
2333 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2334 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2336 /* Futex is required for mutex locks */
2337 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2338 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2340 /* Return error if we hit a system call not on the whitelist */
2341 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2343 /* Allow whitelisted system calls */
2344 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2347 struct sock_fprog prog
= {
2348 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2352 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2355 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2361 /* Helper function with timeout support for reading from the pipe between
2362 * processes used for secure compile.
2364 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2373 /* We can't rely on the value of tv after calling select() so
2374 * we must reset it on each iteration of the loop.
2379 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2385 ssize_t bytes_read
= read(fd
, buf
, size
);
2394 /* select timeout */
2400 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2404 d
= opendir("/proc/self/fd");
2407 int dir_fd
= dirfd(d
);
2409 while ((dir
= readdir(d
)) != NULL
) {
2410 if (dir
->d_name
[0] == '.')
2413 int fd
= atoi(dir
->d_name
);
2418 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2419 if (keep_fds
[i
] == fd
)
2431 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2432 int *fd_server
, int *fd_client
,
2433 unsigned process
, bool make_fifo
)
2435 bool result
= false;
2436 char *fifo_server_path
= NULL
;
2437 char *fifo_client_path
= NULL
;
2439 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2440 goto open_fifo_exit
;
2442 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2443 goto open_fifo_exit
;
2446 int file1
= mkfifo(fifo_server_path
, 0666);
2448 goto open_fifo_exit
;
2450 int file2
= mkfifo(fifo_client_path
, 0666);
2452 goto open_fifo_exit
;
2455 *fd_server
= open(fifo_server_path
, O_RDWR
);
2457 goto open_fifo_exit
;
2459 *fd_client
= open(fifo_client_path
, O_RDWR
);
2460 if(*fd_client
< 1) {
2462 goto open_fifo_exit
;
2468 free(fifo_server_path
);
2469 free(fifo_client_path
);
2474 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2475 int fd_idle_device_output
)
2477 int fd_secure_input
;
2478 int fd_secure_output
;
2479 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2484 enum radv_secure_compile_type sc_type
;
2486 const int needed_fds
[] = {
2489 fd_idle_device_output
,
2492 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2493 install_seccomp_filter() == -1) {
2494 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2496 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2497 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2498 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2501 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2503 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2504 goto secure_compile_exit
;
2507 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2509 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2510 struct radv_pipeline
*pipeline
;
2511 bool sc_read
= true;
2513 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2514 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2516 pipeline
->device
= device
;
2518 /* Read pipeline layout */
2519 struct radv_pipeline_layout layout
;
2520 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2521 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2523 goto secure_compile_exit
;
2525 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2526 uint32_t layout_size
;
2527 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2529 goto secure_compile_exit
;
2531 layout
.set
[set
].layout
= malloc(layout_size
);
2532 layout
.set
[set
].layout
->layout_size
= layout_size
;
2533 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2534 layout
.set
[set
].layout
->layout_size
, true);
2537 pipeline
->layout
= &layout
;
2539 /* Read pipeline key */
2540 struct radv_pipeline_key key
;
2541 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2543 /* Read pipeline create flags */
2544 VkPipelineCreateFlags flags
;
2545 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2547 /* Read stage and shader information */
2548 uint32_t num_stages
;
2549 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2550 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2552 goto secure_compile_exit
;
2554 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2557 gl_shader_stage stage
;
2558 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2560 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2562 /* Read entry point name */
2564 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2566 goto secure_compile_exit
;
2568 char *ep_name
= malloc(name_size
);
2569 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2570 pStage
->pName
= ep_name
;
2572 /* Read shader module */
2574 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2576 goto secure_compile_exit
;
2578 struct radv_shader_module
*module
= malloc(module_size
);
2579 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2580 pStage
->module
= radv_shader_module_to_handle(module
);
2582 /* Read specialization info */
2584 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2586 goto secure_compile_exit
;
2588 if (has_spec_info
) {
2589 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2590 pStage
->pSpecializationInfo
= specInfo
;
2592 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2594 goto secure_compile_exit
;
2596 void *si_data
= malloc(specInfo
->dataSize
);
2597 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2598 specInfo
->pData
= si_data
;
2600 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2602 goto secure_compile_exit
;
2604 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2605 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2606 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2608 goto secure_compile_exit
;
2611 specInfo
->pMapEntries
= mapEntries
;
2614 pStages
[stage
] = pStage
;
2617 /* Compile the shaders */
2618 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2619 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2621 /* free memory allocated above */
2622 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2623 free(layout
.set
[set
].layout
);
2625 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2629 free((void *) pStages
[i
]->pName
);
2630 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2631 if (pStages
[i
]->pSpecializationInfo
) {
2632 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2633 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2634 free((void *) pStages
[i
]->pSpecializationInfo
);
2636 free((void *) pStages
[i
]);
2639 vk_free(&device
->alloc
, pipeline
);
2641 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2642 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2644 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2645 goto secure_compile_exit
;
2649 secure_compile_exit
:
2650 close(fd_secure_input
);
2651 close(fd_secure_output
);
2652 close(fd_idle_device_output
);
2656 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2658 int fd_secure_input
[2];
2659 int fd_secure_output
[2];
2661 /* create pipe descriptors (used to communicate between processes) */
2662 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2663 return RADV_SC_TYPE_INIT_FAILURE
;
2667 if ((sc_pid
= fork()) == 0) {
2668 device
->sc_state
->secure_compile_thread_counter
= process
;
2669 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2672 return RADV_SC_TYPE_INIT_FAILURE
;
2674 /* Read the init result returned from the secure process */
2675 enum radv_secure_compile_type sc_type
;
2676 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2678 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2679 close(fd_secure_input
[0]);
2680 close(fd_secure_input
[1]);
2681 close(fd_secure_output
[1]);
2682 close(fd_secure_output
[0]);
2684 waitpid(sc_pid
, &status
, 0);
2686 return RADV_SC_TYPE_INIT_FAILURE
;
2688 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2689 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2691 close(fd_secure_input
[0]);
2692 close(fd_secure_input
[1]);
2693 close(fd_secure_output
[1]);
2694 close(fd_secure_output
[0]);
2697 waitpid(sc_pid
, &status
, 0);
2701 return RADV_SC_TYPE_INIT_SUCCESS
;
2704 /* Run a bare bones fork of a device that was forked right after its creation.
2705 * This device will have low overhead when it is forked again before each
2706 * pipeline compilation. This device sits idle and its only job is to fork
2709 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2710 int fd_secure_input
, int fd_secure_output
)
2712 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2713 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2714 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2716 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2719 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2721 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2722 sc_type
= fork_secure_compile_device(device
, process
);
2724 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2725 goto secure_compile_exit
;
2727 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2728 goto secure_compile_exit
;
2732 secure_compile_exit
:
2733 close(fd_secure_input
);
2734 close(fd_secure_output
);
2738 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2740 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2742 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2743 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2745 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2746 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2749 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2752 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2754 device
->sc_state
= vk_zalloc(&device
->alloc
,
2755 sizeof(struct radv_secure_compile_state
),
2756 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2758 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2760 pid_t upid
= getpid();
2761 time_t seconds
= time(NULL
);
2764 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2765 return VK_ERROR_INITIALIZATION_FAILED
;
2767 device
->sc_state
->uid
= uid
;
2769 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2770 int fd_secure_input
[MAX_SC_PROCS
][2];
2771 int fd_secure_output
[MAX_SC_PROCS
][2];
2773 /* create pipe descriptors (used to communicate between processes) */
2774 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2775 if (pipe(fd_secure_input
[i
]) == -1 ||
2776 pipe(fd_secure_output
[i
]) == -1) {
2777 return VK_ERROR_INITIALIZATION_FAILED
;
2781 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2782 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2783 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2785 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2786 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2787 device
->sc_state
->secure_compile_thread_counter
= process
;
2788 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2790 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2791 return VK_ERROR_INITIALIZATION_FAILED
;
2793 /* Read the init result returned from the secure process */
2794 enum radv_secure_compile_type sc_type
;
2795 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2798 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2799 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2800 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2801 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2804 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2805 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2808 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2809 close(fd_secure_input
[process
][0]);
2810 close(fd_secure_input
[process
][1]);
2811 close(fd_secure_output
[process
][1]);
2812 close(fd_secure_output
[process
][0]);
2814 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2816 /* Destroy any forks that were created sucessfully */
2817 for (unsigned i
= 0; i
< process
; i
++) {
2818 destroy_secure_compile_device(device
, i
);
2821 return VK_ERROR_INITIALIZATION_FAILED
;
2829 radv_create_pthread_cond(pthread_cond_t
*cond
)
2831 pthread_condattr_t condattr
;
2832 if (pthread_condattr_init(&condattr
)) {
2833 return VK_ERROR_INITIALIZATION_FAILED
;
2836 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2837 pthread_condattr_destroy(&condattr
);
2838 return VK_ERROR_INITIALIZATION_FAILED
;
2840 if (pthread_cond_init(cond
, &condattr
)) {
2841 pthread_condattr_destroy(&condattr
);
2842 return VK_ERROR_INITIALIZATION_FAILED
;
2844 pthread_condattr_destroy(&condattr
);
2848 VkResult
radv_CreateDevice(
2849 VkPhysicalDevice physicalDevice
,
2850 const VkDeviceCreateInfo
* pCreateInfo
,
2851 const VkAllocationCallbacks
* pAllocator
,
2854 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2856 struct radv_device
*device
;
2858 bool keep_shader_info
= false;
2860 /* Check enabled features */
2861 if (pCreateInfo
->pEnabledFeatures
) {
2862 VkPhysicalDeviceFeatures supported_features
;
2863 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2864 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2865 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2866 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2867 for (uint32_t i
= 0; i
< num_features
; i
++) {
2868 if (enabled_feature
[i
] && !supported_feature
[i
])
2869 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2873 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2875 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2877 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2879 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2880 device
->instance
= physical_device
->instance
;
2881 device
->physical_device
= physical_device
;
2883 device
->ws
= physical_device
->ws
;
2885 device
->alloc
= *pAllocator
;
2887 device
->alloc
= physical_device
->instance
->alloc
;
2889 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2890 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2891 int index
= radv_get_device_extension_index(ext_name
);
2892 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2893 vk_free(&device
->alloc
, device
);
2894 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2897 device
->enabled_extensions
.extensions
[index
] = true;
2900 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2902 /* With update after bind we can't attach bo's to the command buffer
2903 * from the descriptor set anymore, so we have to use a global BO list.
2905 device
->use_global_bo_list
=
2906 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2907 device
->enabled_extensions
.EXT_descriptor_indexing
||
2908 device
->enabled_extensions
.EXT_buffer_device_address
||
2909 device
->enabled_extensions
.KHR_buffer_device_address
;
2911 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2912 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2914 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2915 list_inithead(&device
->shader_slabs
);
2917 radv_bo_list_init(&device
->bo_list
);
2919 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2920 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2921 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2922 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2923 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2925 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2927 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2928 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2929 if (!device
->queues
[qfi
]) {
2930 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2934 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2936 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2938 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2939 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2940 qfi
, q
, queue_create
->flags
,
2942 if (result
!= VK_SUCCESS
)
2947 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2948 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2950 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2951 device
->dfsm_allowed
= device
->pbb_allowed
&&
2952 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2954 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2956 /* The maximum number of scratch waves. Scratch space isn't divided
2957 * evenly between CUs. The number is only a function of the number of CUs.
2958 * We can decrease the constant to decrease the scratch buffer size.
2960 * sctx->scratch_waves must be >= the maximum possible size of
2961 * 1 threadgroup, so that the hw doesn't hang from being unable
2964 * The recommended value is 4 per CU at most. Higher numbers don't
2965 * bring much benefit, but they still occupy chip resources (think
2966 * async compute). I've seen ~2% performance difference between 4 and 32.
2968 uint32_t max_threads_per_block
= 2048;
2969 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2970 max_threads_per_block
/ 64);
2972 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2974 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2975 /* If the KMD allows it (there is a KMD hw register for it),
2976 * allow launching waves out-of-order.
2978 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2981 radv_device_init_gs_info(device
);
2983 device
->tess_offchip_block_dw_size
=
2984 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2986 if (getenv("RADV_TRACE_FILE")) {
2987 const char *filename
= getenv("RADV_TRACE_FILE");
2989 keep_shader_info
= true;
2991 if (!radv_init_trace(device
))
2994 fprintf(stderr
, "*****************************************************************************\n");
2995 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2996 fprintf(stderr
, "*****************************************************************************\n");
2998 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2999 radv_dump_enabled_options(device
, stderr
);
3002 /* Temporarily disable secure compile while we create meta shaders, etc */
3003 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
3005 device
->instance
->num_sc_threads
= 0;
3007 device
->keep_shader_info
= keep_shader_info
;
3008 result
= radv_device_init_meta(device
);
3009 if (result
!= VK_SUCCESS
)
3012 radv_device_init_msaa(device
);
3014 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
3015 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3017 case RADV_QUEUE_GENERAL
:
3018 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3019 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3020 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3022 case RADV_QUEUE_COMPUTE
:
3023 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3024 radeon_emit(device
->empty_cs
[family
], 0);
3027 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3030 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3031 cik_create_gfx_config(device
);
3033 VkPipelineCacheCreateInfo ci
;
3034 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3037 ci
.pInitialData
= NULL
;
3038 ci
.initialDataSize
= 0;
3040 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3042 if (result
!= VK_SUCCESS
)
3045 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3047 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3048 if (result
!= VK_SUCCESS
)
3049 goto fail_mem_cache
;
3051 device
->force_aniso
=
3052 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3053 if (device
->force_aniso
>= 0) {
3054 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3055 1 << util_logbase2(device
->force_aniso
));
3058 /* Fork device for secure compile as required */
3059 device
->instance
->num_sc_threads
= sc_threads
;
3060 if (radv_device_use_secure_compile(device
->instance
)) {
3062 result
= fork_secure_compile_idle_device(device
);
3063 if (result
!= VK_SUCCESS
)
3067 *pDevice
= radv_device_to_handle(device
);
3071 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3073 radv_device_finish_meta(device
);
3075 radv_bo_list_finish(&device
->bo_list
);
3077 if (device
->trace_bo
)
3078 device
->ws
->buffer_destroy(device
->trace_bo
);
3080 if (device
->gfx_init
)
3081 device
->ws
->buffer_destroy(device
->gfx_init
);
3083 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3084 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3085 radv_queue_finish(&device
->queues
[i
][q
]);
3086 if (device
->queue_count
[i
])
3087 vk_free(&device
->alloc
, device
->queues
[i
]);
3090 vk_free(&device
->alloc
, device
);
3094 void radv_DestroyDevice(
3096 const VkAllocationCallbacks
* pAllocator
)
3098 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3103 if (device
->trace_bo
)
3104 device
->ws
->buffer_destroy(device
->trace_bo
);
3106 if (device
->gfx_init
)
3107 device
->ws
->buffer_destroy(device
->gfx_init
);
3109 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3110 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3111 radv_queue_finish(&device
->queues
[i
][q
]);
3112 if (device
->queue_count
[i
])
3113 vk_free(&device
->alloc
, device
->queues
[i
]);
3114 if (device
->empty_cs
[i
])
3115 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3117 radv_device_finish_meta(device
);
3119 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3120 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3122 radv_destroy_shader_slabs(device
);
3124 pthread_cond_destroy(&device
->timeline_cond
);
3125 radv_bo_list_finish(&device
->bo_list
);
3126 if (radv_device_use_secure_compile(device
->instance
)) {
3127 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3128 destroy_secure_compile_device(device
, i
);
3132 if (device
->sc_state
) {
3133 free(device
->sc_state
->uid
);
3134 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3136 vk_free(&device
->alloc
, device
->sc_state
);
3137 vk_free(&device
->alloc
, device
);
3140 VkResult
radv_EnumerateInstanceLayerProperties(
3141 uint32_t* pPropertyCount
,
3142 VkLayerProperties
* pProperties
)
3144 if (pProperties
== NULL
) {
3145 *pPropertyCount
= 0;
3149 /* None supported at this time */
3150 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3153 VkResult
radv_EnumerateDeviceLayerProperties(
3154 VkPhysicalDevice physicalDevice
,
3155 uint32_t* pPropertyCount
,
3156 VkLayerProperties
* pProperties
)
3158 if (pProperties
== NULL
) {
3159 *pPropertyCount
= 0;
3163 /* None supported at this time */
3164 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3167 void radv_GetDeviceQueue2(
3169 const VkDeviceQueueInfo2
* pQueueInfo
,
3172 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3173 struct radv_queue
*queue
;
3175 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3176 if (pQueueInfo
->flags
!= queue
->flags
) {
3177 /* From the Vulkan 1.1.70 spec:
3179 * "The queue returned by vkGetDeviceQueue2 must have the same
3180 * flags value from this structure as that used at device
3181 * creation time in a VkDeviceQueueCreateInfo instance. If no
3182 * matching flags were specified at device creation time then
3183 * pQueue will return VK_NULL_HANDLE."
3185 *pQueue
= VK_NULL_HANDLE
;
3189 *pQueue
= radv_queue_to_handle(queue
);
3192 void radv_GetDeviceQueue(
3194 uint32_t queueFamilyIndex
,
3195 uint32_t queueIndex
,
3198 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3199 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3200 .queueFamilyIndex
= queueFamilyIndex
,
3201 .queueIndex
= queueIndex
3204 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3208 fill_geom_tess_rings(struct radv_queue
*queue
,
3210 bool add_sample_positions
,
3211 uint32_t esgs_ring_size
,
3212 struct radeon_winsys_bo
*esgs_ring_bo
,
3213 uint32_t gsvs_ring_size
,
3214 struct radeon_winsys_bo
*gsvs_ring_bo
,
3215 uint32_t tess_factor_ring_size
,
3216 uint32_t tess_offchip_ring_offset
,
3217 uint32_t tess_offchip_ring_size
,
3218 struct radeon_winsys_bo
*tess_rings_bo
)
3220 uint32_t *desc
= &map
[4];
3223 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3225 /* stride 0, num records - size, add tid, swizzle, elsize4,
3228 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3229 S_008F04_SWIZZLE_ENABLE(true);
3230 desc
[2] = esgs_ring_size
;
3231 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3232 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3233 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3234 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3235 S_008F0C_INDEX_STRIDE(3) |
3236 S_008F0C_ADD_TID_ENABLE(1);
3238 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3239 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3240 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3241 S_008F0C_RESOURCE_LEVEL(1);
3243 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3244 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3245 S_008F0C_ELEMENT_SIZE(1);
3248 /* GS entry for ES->GS ring */
3249 /* stride 0, num records - size, elsize0,
3252 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3253 desc
[6] = esgs_ring_size
;
3254 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3255 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3256 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3257 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3259 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3260 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3261 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3262 S_008F0C_RESOURCE_LEVEL(1);
3264 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3265 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3272 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3274 /* VS entry for GS->VS ring */
3275 /* stride 0, num records - size, elsize0,
3278 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3279 desc
[2] = gsvs_ring_size
;
3280 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3281 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3282 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3283 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3285 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3286 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3287 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3288 S_008F0C_RESOURCE_LEVEL(1);
3290 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3291 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3294 /* stride gsvs_itemsize, num records 64
3295 elsize 4, index stride 16 */
3296 /* shader will patch stride and desc[2] */
3298 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3299 S_008F04_SWIZZLE_ENABLE(1);
3301 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3302 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3303 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3304 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3305 S_008F0C_INDEX_STRIDE(1) |
3306 S_008F0C_ADD_TID_ENABLE(true);
3308 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3309 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3310 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3311 S_008F0C_RESOURCE_LEVEL(1);
3313 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3314 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3315 S_008F0C_ELEMENT_SIZE(1);
3322 if (tess_rings_bo
) {
3323 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3324 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3327 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3328 desc
[2] = tess_factor_ring_size
;
3329 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3330 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3331 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3332 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3334 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3335 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3336 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3337 S_008F0C_RESOURCE_LEVEL(1);
3339 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3340 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3343 desc
[4] = tess_offchip_va
;
3344 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3345 desc
[6] = tess_offchip_ring_size
;
3346 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3347 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3348 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3349 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3351 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3352 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3353 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3354 S_008F0C_RESOURCE_LEVEL(1);
3356 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3357 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3363 if (add_sample_positions
) {
3364 /* add sample positions after all rings */
3365 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3367 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3369 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3371 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3376 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3378 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3379 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3380 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3381 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3382 unsigned max_offchip_buffers
;
3383 unsigned offchip_granularity
;
3384 unsigned hs_offchip_param
;
3388 * This must be one less than the maximum number due to a hw limitation.
3389 * Various hardware bugs need thGFX7
3392 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3393 * Gfx7 should limit max_offchip_buffers to 508
3394 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3396 * Follow AMDVLK here.
3398 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3399 max_offchip_buffers_per_se
= 256;
3400 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3401 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3402 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3403 --max_offchip_buffers_per_se
;
3405 max_offchip_buffers
= max_offchip_buffers_per_se
*
3406 device
->physical_device
->rad_info
.max_se
;
3408 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3409 * around by setting 4K granularity.
3411 if (device
->tess_offchip_block_dw_size
== 4096) {
3412 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3413 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3415 assert(device
->tess_offchip_block_dw_size
== 8192);
3416 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3419 switch (device
->physical_device
->rad_info
.chip_class
) {
3421 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3426 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3434 *max_offchip_buffers_p
= max_offchip_buffers
;
3435 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3436 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3437 --max_offchip_buffers
;
3439 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3440 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3443 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3445 return hs_offchip_param
;
3449 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3450 struct radeon_winsys_bo
*esgs_ring_bo
,
3451 uint32_t esgs_ring_size
,
3452 struct radeon_winsys_bo
*gsvs_ring_bo
,
3453 uint32_t gsvs_ring_size
)
3455 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3459 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3462 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3464 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3465 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3466 radeon_emit(cs
, esgs_ring_size
>> 8);
3467 radeon_emit(cs
, gsvs_ring_size
>> 8);
3469 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3470 radeon_emit(cs
, esgs_ring_size
>> 8);
3471 radeon_emit(cs
, gsvs_ring_size
>> 8);
3476 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3477 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3478 struct radeon_winsys_bo
*tess_rings_bo
)
3485 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3487 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3489 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3490 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3491 S_030938_SIZE(tf_ring_size
/ 4));
3492 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3495 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3496 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3497 S_030984_BASE_HI(tf_va
>> 40));
3498 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3499 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3500 S_030944_BASE_HI(tf_va
>> 40));
3502 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3505 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3506 S_008988_SIZE(tf_ring_size
/ 4));
3507 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3509 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3515 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3516 uint32_t size_per_wave
, uint32_t waves
,
3517 struct radeon_winsys_bo
*scratch_bo
)
3519 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3525 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3527 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3528 S_0286E8_WAVES(waves
) |
3529 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3533 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3534 uint32_t size_per_wave
, uint32_t waves
,
3535 struct radeon_winsys_bo
*compute_scratch_bo
)
3537 uint64_t scratch_va
;
3539 if (!compute_scratch_bo
)
3542 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3544 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3546 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3547 radeon_emit(cs
, scratch_va
);
3548 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3549 S_008F04_SWIZZLE_ENABLE(1));
3551 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3552 S_00B860_WAVES(waves
) |
3553 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3557 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3558 struct radeon_cmdbuf
*cs
,
3559 struct radeon_winsys_bo
*descriptor_bo
)
3566 va
= radv_buffer_get_va(descriptor_bo
);
3568 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3570 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3571 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3572 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3573 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3574 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3576 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3577 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3580 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3581 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3582 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3583 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3584 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3586 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3587 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3591 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3592 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3593 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3594 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3595 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3596 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3598 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3599 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3606 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3608 struct radv_device
*device
= queue
->device
;
3610 if (device
->gfx_init
) {
3611 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3613 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3614 radeon_emit(cs
, va
);
3615 radeon_emit(cs
, va
>> 32);
3616 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3618 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3620 struct radv_physical_device
*physical_device
= device
->physical_device
;
3621 si_emit_graphics(physical_device
, cs
);
3626 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3628 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3629 si_emit_compute(physical_device
, cs
);
3633 radv_get_preamble_cs(struct radv_queue
*queue
,
3634 uint32_t scratch_size_per_wave
,
3635 uint32_t scratch_waves
,
3636 uint32_t compute_scratch_size_per_wave
,
3637 uint32_t compute_scratch_waves
,
3638 uint32_t esgs_ring_size
,
3639 uint32_t gsvs_ring_size
,
3640 bool needs_tess_rings
,
3643 bool needs_sample_positions
,
3644 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3645 struct radeon_cmdbuf
**initial_preamble_cs
,
3646 struct radeon_cmdbuf
**continue_preamble_cs
)
3648 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3649 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3650 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3651 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3652 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3653 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3654 struct radeon_winsys_bo
*gds_bo
= NULL
;
3655 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3656 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3657 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3658 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3659 unsigned max_offchip_buffers
;
3660 unsigned hs_offchip_param
= 0;
3661 unsigned tess_offchip_ring_offset
;
3662 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3663 if (!queue
->has_tess_rings
) {
3664 if (needs_tess_rings
)
3665 add_tess_rings
= true;
3667 if (!queue
->has_gds
) {
3671 if (!queue
->has_gds_oa
) {
3675 if (!queue
->has_sample_positions
) {
3676 if (needs_sample_positions
)
3677 add_sample_positions
= true;
3679 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3680 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3681 &max_offchip_buffers
);
3682 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3683 tess_offchip_ring_size
= max_offchip_buffers
*
3684 queue
->device
->tess_offchip_block_dw_size
* 4;
3686 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3687 if (scratch_size_per_wave
)
3688 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3692 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3693 if (compute_scratch_size_per_wave
)
3694 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3696 compute_scratch_waves
= 0;
3698 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3699 scratch_waves
<= queue
->scratch_waves
&&
3700 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3701 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3702 esgs_ring_size
<= queue
->esgs_ring_size
&&
3703 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3704 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3705 queue
->initial_preamble_cs
) {
3706 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3707 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3708 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3709 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3710 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3711 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3712 *continue_preamble_cs
= NULL
;
3716 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3717 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3718 if (scratch_size
> queue_scratch_size
) {
3719 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3724 RADV_BO_PRIORITY_SCRATCH
);
3728 scratch_bo
= queue
->scratch_bo
;
3730 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3731 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3732 if (compute_scratch_size
> compute_queue_scratch_size
) {
3733 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3734 compute_scratch_size
,
3738 RADV_BO_PRIORITY_SCRATCH
);
3739 if (!compute_scratch_bo
)
3743 compute_scratch_bo
= queue
->compute_scratch_bo
;
3745 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3746 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3751 RADV_BO_PRIORITY_SCRATCH
);
3755 esgs_ring_bo
= queue
->esgs_ring_bo
;
3756 esgs_ring_size
= queue
->esgs_ring_size
;
3759 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3760 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3765 RADV_BO_PRIORITY_SCRATCH
);
3769 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3770 gsvs_ring_size
= queue
->gsvs_ring_size
;
3773 if (add_tess_rings
) {
3774 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3775 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3779 RADV_BO_PRIORITY_SCRATCH
);
3783 tess_rings_bo
= queue
->tess_rings_bo
;
3787 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3789 /* 4 streamout GDS counters.
3790 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3792 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3796 RADV_BO_PRIORITY_SCRATCH
);
3800 gds_bo
= queue
->gds_bo
;
3804 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3806 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3810 RADV_BO_PRIORITY_SCRATCH
);
3814 gds_oa_bo
= queue
->gds_oa_bo
;
3817 if (scratch_bo
!= queue
->scratch_bo
||
3818 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3819 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3820 tess_rings_bo
!= queue
->tess_rings_bo
||
3821 add_sample_positions
) {
3823 if (gsvs_ring_bo
|| esgs_ring_bo
||
3824 tess_rings_bo
|| add_sample_positions
) {
3825 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3826 if (add_sample_positions
)
3827 size
+= 128; /* 64+32+16+8 = 120 bytes */
3829 else if (scratch_bo
)
3830 size
= 8; /* 2 dword */
3832 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3836 RADEON_FLAG_CPU_ACCESS
|
3837 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3838 RADEON_FLAG_READ_ONLY
,
3839 RADV_BO_PRIORITY_DESCRIPTOR
);
3843 descriptor_bo
= queue
->descriptor_bo
;
3845 if (descriptor_bo
!= queue
->descriptor_bo
) {
3846 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3849 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3850 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3851 S_008F04_SWIZZLE_ENABLE(1);
3852 map
[0] = scratch_va
;
3856 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3857 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3858 esgs_ring_size
, esgs_ring_bo
,
3859 gsvs_ring_size
, gsvs_ring_bo
,
3860 tess_factor_ring_size
,
3861 tess_offchip_ring_offset
,
3862 tess_offchip_ring_size
,
3865 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3868 for(int i
= 0; i
< 3; ++i
) {
3869 struct radeon_cmdbuf
*cs
= NULL
;
3870 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3871 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3878 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3880 /* Emit initial configuration. */
3881 switch (queue
->queue_family_index
) {
3882 case RADV_QUEUE_GENERAL
:
3883 radv_init_graphics_state(cs
, queue
);
3885 case RADV_QUEUE_COMPUTE
:
3886 radv_init_compute_state(cs
, queue
);
3888 case RADV_QUEUE_TRANSFER
:
3892 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3893 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3894 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3896 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3897 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3900 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3901 gsvs_ring_bo
, gsvs_ring_size
);
3902 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3903 tess_factor_ring_size
, tess_rings_bo
);
3904 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3905 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3906 compute_scratch_waves
, compute_scratch_bo
);
3907 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3908 scratch_waves
, scratch_bo
);
3911 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3913 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3916 si_cs_emit_cache_flush(cs
,
3917 queue
->device
->physical_device
->rad_info
.chip_class
,
3919 queue
->queue_family_index
== RING_COMPUTE
&&
3920 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3921 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3922 RADV_CMD_FLAG_INV_ICACHE
|
3923 RADV_CMD_FLAG_INV_SCACHE
|
3924 RADV_CMD_FLAG_INV_VCACHE
|
3925 RADV_CMD_FLAG_INV_L2
|
3926 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3927 } else if (i
== 1) {
3928 si_cs_emit_cache_flush(cs
,
3929 queue
->device
->physical_device
->rad_info
.chip_class
,
3931 queue
->queue_family_index
== RING_COMPUTE
&&
3932 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3933 RADV_CMD_FLAG_INV_ICACHE
|
3934 RADV_CMD_FLAG_INV_SCACHE
|
3935 RADV_CMD_FLAG_INV_VCACHE
|
3936 RADV_CMD_FLAG_INV_L2
|
3937 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3940 if (!queue
->device
->ws
->cs_finalize(cs
))
3944 if (queue
->initial_full_flush_preamble_cs
)
3945 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3947 if (queue
->initial_preamble_cs
)
3948 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3950 if (queue
->continue_preamble_cs
)
3951 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3953 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3954 queue
->initial_preamble_cs
= dest_cs
[1];
3955 queue
->continue_preamble_cs
= dest_cs
[2];
3957 if (scratch_bo
!= queue
->scratch_bo
) {
3958 if (queue
->scratch_bo
)
3959 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3960 queue
->scratch_bo
= scratch_bo
;
3962 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3963 queue
->scratch_waves
= scratch_waves
;
3965 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3966 if (queue
->compute_scratch_bo
)
3967 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3968 queue
->compute_scratch_bo
= compute_scratch_bo
;
3970 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3971 queue
->compute_scratch_waves
= compute_scratch_waves
;
3973 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3974 if (queue
->esgs_ring_bo
)
3975 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3976 queue
->esgs_ring_bo
= esgs_ring_bo
;
3977 queue
->esgs_ring_size
= esgs_ring_size
;
3980 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3981 if (queue
->gsvs_ring_bo
)
3982 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3983 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3984 queue
->gsvs_ring_size
= gsvs_ring_size
;
3987 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3988 queue
->tess_rings_bo
= tess_rings_bo
;
3989 queue
->has_tess_rings
= true;
3992 if (gds_bo
!= queue
->gds_bo
) {
3993 queue
->gds_bo
= gds_bo
;
3994 queue
->has_gds
= true;
3997 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3998 queue
->gds_oa_bo
= gds_oa_bo
;
3999 queue
->has_gds_oa
= true;
4002 if (descriptor_bo
!= queue
->descriptor_bo
) {
4003 if (queue
->descriptor_bo
)
4004 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
4006 queue
->descriptor_bo
= descriptor_bo
;
4009 if (add_sample_positions
)
4010 queue
->has_sample_positions
= true;
4012 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
4013 *initial_preamble_cs
= queue
->initial_preamble_cs
;
4014 *continue_preamble_cs
= queue
->continue_preamble_cs
;
4015 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
4016 *continue_preamble_cs
= NULL
;
4019 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4021 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4022 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4023 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4024 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4025 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4026 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4027 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4028 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4029 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4030 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4031 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4032 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4033 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4034 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4035 queue
->device
->ws
->buffer_destroy(gds_bo
);
4036 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4037 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4039 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4042 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4043 struct radv_winsys_sem_counts
*counts
,
4045 struct radv_semaphore_part
**sems
,
4046 const uint64_t *timeline_values
,
4050 int syncobj_idx
= 0, sem_idx
= 0;
4052 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4055 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4056 switch(sems
[i
]->kind
) {
4057 case RADV_SEMAPHORE_SYNCOBJ
:
4058 counts
->syncobj_count
++;
4060 case RADV_SEMAPHORE_WINSYS
:
4061 counts
->sem_count
++;
4063 case RADV_SEMAPHORE_NONE
:
4065 case RADV_SEMAPHORE_TIMELINE
:
4066 counts
->syncobj_count
++;
4071 if (_fence
!= VK_NULL_HANDLE
) {
4072 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4073 if (fence
->temp_syncobj
|| fence
->syncobj
)
4074 counts
->syncobj_count
++;
4077 if (counts
->syncobj_count
) {
4078 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4079 if (!counts
->syncobj
)
4080 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4083 if (counts
->sem_count
) {
4084 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4086 free(counts
->syncobj
);
4087 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4091 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4092 switch(sems
[i
]->kind
) {
4093 case RADV_SEMAPHORE_NONE
:
4094 unreachable("Empty semaphore");
4096 case RADV_SEMAPHORE_SYNCOBJ
:
4097 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4099 case RADV_SEMAPHORE_WINSYS
:
4100 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4102 case RADV_SEMAPHORE_TIMELINE
: {
4103 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4104 struct radv_timeline_point
*point
= NULL
;
4106 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4108 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4111 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4114 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4116 /* Explicitly remove the semaphore so we might not find
4117 * a point later post-submit. */
4125 if (_fence
!= VK_NULL_HANDLE
) {
4126 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4127 if (fence
->temp_syncobj
)
4128 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4129 else if (fence
->syncobj
)
4130 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4133 assert(syncobj_idx
<= counts
->syncobj_count
);
4134 counts
->syncobj_count
= syncobj_idx
;
4140 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4142 free(sem_info
->wait
.syncobj
);
4143 free(sem_info
->wait
.sem
);
4144 free(sem_info
->signal
.syncobj
);
4145 free(sem_info
->signal
.sem
);
4149 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4151 struct radv_semaphore_part
*sems
)
4153 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4154 radv_destroy_semaphore_part(device
, sems
+ i
);
4159 radv_alloc_sem_info(struct radv_device
*device
,
4160 struct radv_winsys_sem_info
*sem_info
,
4162 struct radv_semaphore_part
**wait_sems
,
4163 const uint64_t *wait_values
,
4164 int num_signal_sems
,
4165 struct radv_semaphore_part
**signal_sems
,
4166 const uint64_t *signal_values
,
4170 memset(sem_info
, 0, sizeof(*sem_info
));
4172 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4175 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4177 radv_free_sem_info(sem_info
);
4179 /* caller can override these */
4180 sem_info
->cs_emit_wait
= true;
4181 sem_info
->cs_emit_signal
= true;
4186 radv_finalize_timelines(struct radv_device
*device
,
4187 uint32_t num_wait_sems
,
4188 struct radv_semaphore_part
**wait_sems
,
4189 const uint64_t *wait_values
,
4190 uint32_t num_signal_sems
,
4191 struct radv_semaphore_part
**signal_sems
,
4192 const uint64_t *signal_values
,
4193 struct list_head
*processing_list
)
4195 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4196 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4197 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4198 struct radv_timeline_point
*point
=
4199 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4200 point
->wait_count
-= 2;
4201 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4204 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4205 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4206 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4207 struct radv_timeline_point
*point
=
4208 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4209 signal_sems
[i
]->timeline
.highest_submitted
=
4210 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4211 point
->wait_count
-= 2;
4212 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4213 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4219 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4220 const VkSparseBufferMemoryBindInfo
*bind
)
4222 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4224 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4225 struct radv_device_memory
*mem
= NULL
;
4227 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4228 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4230 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4231 bind
->pBinds
[i
].resourceOffset
,
4232 bind
->pBinds
[i
].size
,
4233 mem
? mem
->bo
: NULL
,
4234 bind
->pBinds
[i
].memoryOffset
);
4239 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4240 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4242 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4244 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4245 struct radv_device_memory
*mem
= NULL
;
4247 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4248 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4250 device
->ws
->buffer_virtual_bind(image
->bo
,
4251 bind
->pBinds
[i
].resourceOffset
,
4252 bind
->pBinds
[i
].size
,
4253 mem
? mem
->bo
: NULL
,
4254 bind
->pBinds
[i
].memoryOffset
);
4259 radv_get_preambles(struct radv_queue
*queue
,
4260 const VkCommandBuffer
*cmd_buffers
,
4261 uint32_t cmd_buffer_count
,
4262 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4263 struct radeon_cmdbuf
**initial_preamble_cs
,
4264 struct radeon_cmdbuf
**continue_preamble_cs
)
4266 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4267 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4268 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4269 bool tess_rings_needed
= false;
4270 bool gds_needed
= false;
4271 bool gds_oa_needed
= false;
4272 bool sample_positions_needed
= false;
4274 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4275 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4278 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4279 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4280 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4281 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4282 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4283 cmd_buffer
->compute_scratch_waves_wanted
);
4284 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4285 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4286 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4287 gds_needed
|= cmd_buffer
->gds_needed
;
4288 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4289 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4292 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4293 compute_scratch_size_per_wave
, compute_waves_wanted
,
4294 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4295 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4296 initial_full_flush_preamble_cs
,
4297 initial_preamble_cs
, continue_preamble_cs
);
4300 struct radv_deferred_queue_submission
{
4301 struct radv_queue
*queue
;
4302 VkCommandBuffer
*cmd_buffers
;
4303 uint32_t cmd_buffer_count
;
4305 /* Sparse bindings that happen on a queue. */
4306 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4307 uint32_t buffer_bind_count
;
4308 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4309 uint32_t image_opaque_bind_count
;
4312 VkShaderStageFlags wait_dst_stage_mask
;
4313 struct radv_semaphore_part
**wait_semaphores
;
4314 uint32_t wait_semaphore_count
;
4315 struct radv_semaphore_part
**signal_semaphores
;
4316 uint32_t signal_semaphore_count
;
4319 uint64_t *wait_values
;
4320 uint64_t *signal_values
;
4322 struct radv_semaphore_part
*temporary_semaphore_parts
;
4323 uint32_t temporary_semaphore_part_count
;
4325 struct list_head queue_pending_list
;
4326 uint32_t submission_wait_count
;
4327 struct radv_timeline_waiter
*wait_nodes
;
4329 struct list_head processing_list
;
4332 struct radv_queue_submission
{
4333 const VkCommandBuffer
*cmd_buffers
;
4334 uint32_t cmd_buffer_count
;
4336 /* Sparse bindings that happen on a queue. */
4337 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4338 uint32_t buffer_bind_count
;
4339 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4340 uint32_t image_opaque_bind_count
;
4343 VkPipelineStageFlags wait_dst_stage_mask
;
4344 const VkSemaphore
*wait_semaphores
;
4345 uint32_t wait_semaphore_count
;
4346 const VkSemaphore
*signal_semaphores
;
4347 uint32_t signal_semaphore_count
;
4350 const uint64_t *wait_values
;
4351 uint32_t wait_value_count
;
4352 const uint64_t *signal_values
;
4353 uint32_t signal_value_count
;
4357 radv_create_deferred_submission(struct radv_queue
*queue
,
4358 const struct radv_queue_submission
*submission
,
4359 struct radv_deferred_queue_submission
**out
)
4361 struct radv_deferred_queue_submission
*deferred
= NULL
;
4362 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4364 uint32_t temporary_count
= 0;
4365 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4366 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4367 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4371 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4372 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4373 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4374 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4375 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4376 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4377 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4378 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4379 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4381 deferred
= calloc(1, size
);
4383 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4385 deferred
->queue
= queue
;
4387 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4388 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4389 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4390 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4392 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4393 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4394 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4395 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4397 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4398 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4399 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4400 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4402 deferred
->flush_caches
= submission
->flush_caches
;
4403 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4405 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4406 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4408 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4409 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4411 deferred
->fence
= submission
->fence
;
4413 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4414 deferred
->temporary_semaphore_part_count
= temporary_count
;
4416 uint32_t temporary_idx
= 0;
4417 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4418 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4419 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4420 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4421 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4422 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4425 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4428 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4429 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4430 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4431 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4433 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4437 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4438 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4439 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4440 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4442 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4443 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4444 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4445 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4452 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4453 struct list_head
*processing_list
)
4455 uint32_t wait_cnt
= 0;
4456 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4457 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4458 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4459 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4460 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4462 waiter
->value
= submission
->wait_values
[i
];
4463 waiter
->submission
= submission
;
4464 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4467 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4471 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4473 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4474 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4476 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4478 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4479 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4481 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4482 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4483 list_addtail(&submission
->processing_list
, processing_list
);
4488 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4489 struct list_head
*processing_list
)
4491 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4492 list_del(&submission
->queue_pending_list
);
4494 /* trigger the next submission in the queue. */
4495 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4496 struct radv_deferred_queue_submission
*next_submission
=
4497 list_first_entry(&submission
->queue
->pending_submissions
,
4498 struct radv_deferred_queue_submission
,
4499 queue_pending_list
);
4500 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4501 list_addtail(&next_submission
->processing_list
, processing_list
);
4504 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4506 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4510 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4511 struct list_head
*processing_list
)
4513 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4514 struct radv_queue
*queue
= submission
->queue
;
4515 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4516 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4517 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4518 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4519 bool can_patch
= true;
4521 struct radv_winsys_sem_info sem_info
;
4524 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4525 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4526 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4528 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4529 submission
->cmd_buffer_count
,
4530 &initial_preamble_cs
,
4531 &initial_flush_preamble_cs
,
4532 &continue_preamble_cs
);
4533 if (result
!= VK_SUCCESS
)
4536 result
= radv_alloc_sem_info(queue
->device
,
4538 submission
->wait_semaphore_count
,
4539 submission
->wait_semaphores
,
4540 submission
->wait_values
,
4541 submission
->signal_semaphore_count
,
4542 submission
->signal_semaphores
,
4543 submission
->signal_values
,
4545 if (result
!= VK_SUCCESS
)
4548 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4549 radv_sparse_buffer_bind_memory(queue
->device
,
4550 submission
->buffer_binds
+ i
);
4553 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4554 radv_sparse_image_opaque_bind_memory(queue
->device
,
4555 submission
->image_opaque_binds
+ i
);
4558 if (!submission
->cmd_buffer_count
) {
4559 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4560 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4565 radv_loge("failed to submit CS\n");
4571 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4572 (submission
->cmd_buffer_count
));
4574 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4575 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4576 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4578 cs_array
[j
] = cmd_buffer
->cs
;
4579 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4582 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4585 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4586 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4587 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4589 advance
= MIN2(max_cs_submission
,
4590 submission
->cmd_buffer_count
- j
);
4592 if (queue
->device
->trace_bo
)
4593 *queue
->device
->trace_id_ptr
= 0;
4595 sem_info
.cs_emit_wait
= j
== 0;
4596 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4598 if (unlikely(queue
->device
->use_global_bo_list
)) {
4599 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4600 bo_list
= &queue
->device
->bo_list
.list
;
4603 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4604 advance
, initial_preamble
, continue_preamble_cs
,
4606 can_patch
, base_fence
);
4608 if (unlikely(queue
->device
->use_global_bo_list
))
4609 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4612 radv_loge("failed to submit CS\n");
4615 if (queue
->device
->trace_bo
) {
4616 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4624 radv_free_temp_syncobjs(queue
->device
,
4625 submission
->temporary_semaphore_part_count
,
4626 submission
->temporary_semaphore_parts
);
4627 radv_finalize_timelines(queue
->device
,
4628 submission
->wait_semaphore_count
,
4629 submission
->wait_semaphores
,
4630 submission
->wait_values
,
4631 submission
->signal_semaphore_count
,
4632 submission
->signal_semaphores
,
4633 submission
->signal_values
,
4635 /* Has to happen after timeline finalization to make sure the
4636 * condition variable is only triggered when timelines and queue have
4638 radv_queue_submission_update_queue(submission
, processing_list
);
4639 radv_free_sem_info(&sem_info
);
4644 radv_free_temp_syncobjs(queue
->device
,
4645 submission
->temporary_semaphore_part_count
,
4646 submission
->temporary_semaphore_parts
);
4648 return VK_ERROR_DEVICE_LOST
;
4652 radv_process_submissions(struct list_head
*processing_list
)
4654 while(!list_is_empty(processing_list
)) {
4655 struct radv_deferred_queue_submission
*submission
=
4656 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4657 list_del(&submission
->processing_list
);
4659 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4660 if (result
!= VK_SUCCESS
)
4666 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4667 const struct radv_queue_submission
*submission
)
4669 struct radv_deferred_queue_submission
*deferred
= NULL
;
4671 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4672 if (result
!= VK_SUCCESS
)
4675 struct list_head processing_list
;
4676 list_inithead(&processing_list
);
4678 radv_queue_enqueue_submission(deferred
, &processing_list
);
4679 return radv_process_submissions(&processing_list
);
4682 /* Signals fence as soon as all the work currently put on queue is done. */
4683 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4686 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4691 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4693 return info
->commandBufferCount
||
4694 info
->waitSemaphoreCount
||
4695 info
->signalSemaphoreCount
;
4698 VkResult
radv_QueueSubmit(
4700 uint32_t submitCount
,
4701 const VkSubmitInfo
* pSubmits
,
4704 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4706 uint32_t fence_idx
= 0;
4707 bool flushed_caches
= false;
4709 if (fence
!= VK_NULL_HANDLE
) {
4710 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4711 if (radv_submit_has_effects(pSubmits
+ i
))
4714 fence_idx
= UINT32_MAX
;
4716 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4717 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4720 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4721 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4722 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4725 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4726 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4728 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4729 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4730 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4731 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4732 .flush_caches
= !flushed_caches
,
4733 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4734 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4735 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4736 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4737 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4738 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4739 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4740 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4741 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4743 if (result
!= VK_SUCCESS
)
4746 flushed_caches
= true;
4749 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4750 result
= radv_signal_fence(queue
, fence
);
4751 if (result
!= VK_SUCCESS
)
4758 VkResult
radv_QueueWaitIdle(
4761 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4763 pthread_mutex_lock(&queue
->pending_mutex
);
4764 while (!list_is_empty(&queue
->pending_submissions
)) {
4765 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4767 pthread_mutex_unlock(&queue
->pending_mutex
);
4769 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4770 radv_queue_family_to_ring(queue
->queue_family_index
),
4775 VkResult
radv_DeviceWaitIdle(
4778 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4780 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4781 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4782 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4788 VkResult
radv_EnumerateInstanceExtensionProperties(
4789 const char* pLayerName
,
4790 uint32_t* pPropertyCount
,
4791 VkExtensionProperties
* pProperties
)
4793 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4795 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4796 if (radv_supported_instance_extensions
.extensions
[i
]) {
4797 vk_outarray_append(&out
, prop
) {
4798 *prop
= radv_instance_extensions
[i
];
4803 return vk_outarray_status(&out
);
4806 VkResult
radv_EnumerateDeviceExtensionProperties(
4807 VkPhysicalDevice physicalDevice
,
4808 const char* pLayerName
,
4809 uint32_t* pPropertyCount
,
4810 VkExtensionProperties
* pProperties
)
4812 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4813 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4815 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4816 if (device
->supported_extensions
.extensions
[i
]) {
4817 vk_outarray_append(&out
, prop
) {
4818 *prop
= radv_device_extensions
[i
];
4823 return vk_outarray_status(&out
);
4826 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4827 VkInstance _instance
,
4830 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4831 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4834 return radv_lookup_entrypoint_unchecked(pName
);
4836 return radv_lookup_entrypoint_checked(pName
,
4837 instance
? instance
->apiVersion
: 0,
4838 instance
? &instance
->enabled_extensions
: NULL
,
4843 /* The loader wants us to expose a second GetInstanceProcAddr function
4844 * to work around certain LD_PRELOAD issues seen in apps.
4847 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4848 VkInstance instance
,
4852 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4853 VkInstance instance
,
4856 return radv_GetInstanceProcAddr(instance
, pName
);
4860 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4861 VkInstance _instance
,
4865 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4866 VkInstance _instance
,
4869 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4871 return radv_lookup_physical_device_entrypoint_checked(pName
,
4872 instance
? instance
->apiVersion
: 0,
4873 instance
? &instance
->enabled_extensions
: NULL
);
4876 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4880 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4881 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4884 return radv_lookup_entrypoint_unchecked(pName
);
4886 return radv_lookup_entrypoint_checked(pName
,
4887 device
->instance
->apiVersion
,
4888 &device
->instance
->enabled_extensions
,
4889 &device
->enabled_extensions
);
4893 bool radv_get_memory_fd(struct radv_device
*device
,
4894 struct radv_device_memory
*memory
,
4897 struct radeon_bo_metadata metadata
;
4899 if (memory
->image
) {
4900 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4901 radv_init_metadata(device
, memory
->image
, &metadata
);
4902 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4905 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4910 static void radv_free_memory(struct radv_device
*device
,
4911 const VkAllocationCallbacks
* pAllocator
,
4912 struct radv_device_memory
*mem
)
4917 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4918 if (mem
->android_hardware_buffer
)
4919 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4923 radv_bo_list_remove(device
, mem
->bo
);
4924 device
->ws
->buffer_destroy(mem
->bo
);
4928 vk_free2(&device
->alloc
, pAllocator
, mem
);
4931 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4932 const VkMemoryAllocateInfo
* pAllocateInfo
,
4933 const VkAllocationCallbacks
* pAllocator
,
4934 VkDeviceMemory
* pMem
)
4936 struct radv_device_memory
*mem
;
4938 enum radeon_bo_domain domain
;
4940 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
4942 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4944 const VkImportMemoryFdInfoKHR
*import_info
=
4945 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4946 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4947 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4948 const VkExportMemoryAllocateInfo
*export_info
=
4949 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4950 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4951 vk_find_struct_const(pAllocateInfo
->pNext
,
4952 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4953 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4954 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4956 const struct wsi_memory_allocate_info
*wsi_info
=
4957 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4959 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4960 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4961 /* Apparently, this is allowed */
4962 *pMem
= VK_NULL_HANDLE
;
4966 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4967 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4969 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4971 if (wsi_info
&& wsi_info
->implicit_sync
)
4972 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4974 if (dedicate_info
) {
4975 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4976 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4982 float priority_float
= 0.5;
4983 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4984 vk_find_struct_const(pAllocateInfo
->pNext
,
4985 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4987 priority_float
= priority_ext
->priority
;
4989 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4990 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4992 mem
->user_ptr
= NULL
;
4995 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4996 mem
->android_hardware_buffer
= NULL
;
4999 if (ahb_import_info
) {
5000 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
5001 if (result
!= VK_SUCCESS
)
5003 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
5004 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5005 if (result
!= VK_SUCCESS
)
5007 } else if (import_info
) {
5008 assert(import_info
->handleType
==
5009 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5010 import_info
->handleType
==
5011 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5012 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5015 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5018 close(import_info
->fd
);
5020 } else if (host_ptr_info
) {
5021 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5022 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5023 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5024 pAllocateInfo
->allocationSize
,
5027 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5030 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5033 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5034 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5035 radv_is_mem_type_gtt_cached(mem_type_index
))
5036 domain
= RADEON_DOMAIN_GTT
;
5038 domain
= RADEON_DOMAIN_VRAM
;
5040 if (radv_is_mem_type_vram(mem_type_index
))
5041 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5043 flags
|= RADEON_FLAG_CPU_ACCESS
;
5045 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5046 flags
|= RADEON_FLAG_GTT_WC
;
5048 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5049 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5050 if (device
->use_global_bo_list
) {
5051 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5055 if (radv_is_mem_type_uncached(mem_type_index
)) {
5056 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5057 flags
|= RADEON_FLAG_VA_UNCACHED
;
5060 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5061 domain
, flags
, priority
);
5064 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5067 mem
->type_index
= mem_type_index
;
5070 result
= radv_bo_list_add(device
, mem
->bo
);
5071 if (result
!= VK_SUCCESS
)
5074 *pMem
= radv_device_memory_to_handle(mem
);
5079 radv_free_memory(device
, pAllocator
,mem
);
5084 VkResult
radv_AllocateMemory(
5086 const VkMemoryAllocateInfo
* pAllocateInfo
,
5087 const VkAllocationCallbacks
* pAllocator
,
5088 VkDeviceMemory
* pMem
)
5090 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5091 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5094 void radv_FreeMemory(
5096 VkDeviceMemory _mem
,
5097 const VkAllocationCallbacks
* pAllocator
)
5099 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5100 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5102 radv_free_memory(device
, pAllocator
, mem
);
5105 VkResult
radv_MapMemory(
5107 VkDeviceMemory _memory
,
5108 VkDeviceSize offset
,
5110 VkMemoryMapFlags flags
,
5113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5114 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5122 *ppData
= mem
->user_ptr
;
5124 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5131 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5134 void radv_UnmapMemory(
5136 VkDeviceMemory _memory
)
5138 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5139 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5144 if (mem
->user_ptr
== NULL
)
5145 device
->ws
->buffer_unmap(mem
->bo
);
5148 VkResult
radv_FlushMappedMemoryRanges(
5150 uint32_t memoryRangeCount
,
5151 const VkMappedMemoryRange
* pMemoryRanges
)
5156 VkResult
radv_InvalidateMappedMemoryRanges(
5158 uint32_t memoryRangeCount
,
5159 const VkMappedMemoryRange
* pMemoryRanges
)
5164 void radv_GetBufferMemoryRequirements(
5167 VkMemoryRequirements
* pMemoryRequirements
)
5169 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5170 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5172 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5174 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5175 pMemoryRequirements
->alignment
= 4096;
5177 pMemoryRequirements
->alignment
= 16;
5179 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5182 void radv_GetBufferMemoryRequirements2(
5184 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5185 VkMemoryRequirements2
*pMemoryRequirements
)
5187 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5188 &pMemoryRequirements
->memoryRequirements
);
5189 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5190 switch (ext
->sType
) {
5191 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5192 VkMemoryDedicatedRequirements
*req
=
5193 (VkMemoryDedicatedRequirements
*) ext
;
5194 req
->requiresDedicatedAllocation
= false;
5195 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5204 void radv_GetImageMemoryRequirements(
5207 VkMemoryRequirements
* pMemoryRequirements
)
5209 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5210 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5212 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5214 pMemoryRequirements
->size
= image
->size
;
5215 pMemoryRequirements
->alignment
= image
->alignment
;
5218 void radv_GetImageMemoryRequirements2(
5220 const VkImageMemoryRequirementsInfo2
*pInfo
,
5221 VkMemoryRequirements2
*pMemoryRequirements
)
5223 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5224 &pMemoryRequirements
->memoryRequirements
);
5226 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5228 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5229 switch (ext
->sType
) {
5230 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5231 VkMemoryDedicatedRequirements
*req
=
5232 (VkMemoryDedicatedRequirements
*) ext
;
5233 req
->requiresDedicatedAllocation
= image
->shareable
&&
5234 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5235 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5244 void radv_GetImageSparseMemoryRequirements(
5247 uint32_t* pSparseMemoryRequirementCount
,
5248 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5253 void radv_GetImageSparseMemoryRequirements2(
5255 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5256 uint32_t* pSparseMemoryRequirementCount
,
5257 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5262 void radv_GetDeviceMemoryCommitment(
5264 VkDeviceMemory memory
,
5265 VkDeviceSize
* pCommittedMemoryInBytes
)
5267 *pCommittedMemoryInBytes
= 0;
5270 VkResult
radv_BindBufferMemory2(VkDevice device
,
5271 uint32_t bindInfoCount
,
5272 const VkBindBufferMemoryInfo
*pBindInfos
)
5274 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5275 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5276 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5279 buffer
->bo
= mem
->bo
;
5280 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5288 VkResult
radv_BindBufferMemory(
5291 VkDeviceMemory memory
,
5292 VkDeviceSize memoryOffset
)
5294 const VkBindBufferMemoryInfo info
= {
5295 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5298 .memoryOffset
= memoryOffset
5301 return radv_BindBufferMemory2(device
, 1, &info
);
5304 VkResult
radv_BindImageMemory2(VkDevice device
,
5305 uint32_t bindInfoCount
,
5306 const VkBindImageMemoryInfo
*pBindInfos
)
5308 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5309 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5310 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5313 image
->bo
= mem
->bo
;
5314 image
->offset
= pBindInfos
[i
].memoryOffset
;
5324 VkResult
radv_BindImageMemory(
5327 VkDeviceMemory memory
,
5328 VkDeviceSize memoryOffset
)
5330 const VkBindImageMemoryInfo info
= {
5331 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5334 .memoryOffset
= memoryOffset
5337 return radv_BindImageMemory2(device
, 1, &info
);
5340 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5342 return info
->bufferBindCount
||
5343 info
->imageOpaqueBindCount
||
5344 info
->imageBindCount
||
5345 info
->waitSemaphoreCount
||
5346 info
->signalSemaphoreCount
;
5349 VkResult
radv_QueueBindSparse(
5351 uint32_t bindInfoCount
,
5352 const VkBindSparseInfo
* pBindInfo
,
5355 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5357 uint32_t fence_idx
= 0;
5359 if (fence
!= VK_NULL_HANDLE
) {
5360 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5361 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5364 fence_idx
= UINT32_MAX
;
5366 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5367 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5370 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5371 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5373 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5374 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5375 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5376 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5377 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5378 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5379 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5380 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5381 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5382 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5383 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5384 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5385 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5386 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5389 if (result
!= VK_SUCCESS
)
5393 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5394 result
= radv_signal_fence(queue
, fence
);
5395 if (result
!= VK_SUCCESS
)
5402 VkResult
radv_CreateFence(
5404 const VkFenceCreateInfo
* pCreateInfo
,
5405 const VkAllocationCallbacks
* pAllocator
,
5408 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5409 const VkExportFenceCreateInfo
*export
=
5410 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5411 VkExternalFenceHandleTypeFlags handleTypes
=
5412 export
? export
->handleTypes
: 0;
5414 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5416 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5419 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5421 fence
->fence_wsi
= NULL
;
5422 fence
->temp_syncobj
= 0;
5423 if (device
->always_use_syncobj
|| handleTypes
) {
5424 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5426 vk_free2(&device
->alloc
, pAllocator
, fence
);
5427 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5429 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5430 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5432 fence
->fence
= NULL
;
5434 fence
->fence
= device
->ws
->create_fence();
5435 if (!fence
->fence
) {
5436 vk_free2(&device
->alloc
, pAllocator
, fence
);
5437 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5440 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5441 device
->ws
->signal_fence(fence
->fence
);
5444 *pFence
= radv_fence_to_handle(fence
);
5449 void radv_DestroyFence(
5452 const VkAllocationCallbacks
* pAllocator
)
5454 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5455 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5460 if (fence
->temp_syncobj
)
5461 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5463 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5465 device
->ws
->destroy_fence(fence
->fence
);
5466 if (fence
->fence_wsi
)
5467 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5468 vk_free2(&device
->alloc
, pAllocator
, fence
);
5472 uint64_t radv_get_current_time(void)
5475 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5476 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5479 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5481 uint64_t current_time
= radv_get_current_time();
5483 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5485 return current_time
+ timeout
;
5489 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5490 uint32_t fenceCount
, const VkFence
*pFences
)
5492 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5493 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5494 if (fence
->fence
== NULL
|| fence
->syncobj
||
5495 fence
->temp_syncobj
|| fence
->fence_wsi
||
5496 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5502 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5504 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5505 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5506 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5512 VkResult
radv_WaitForFences(
5514 uint32_t fenceCount
,
5515 const VkFence
* pFences
,
5519 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5520 timeout
= radv_get_absolute_timeout(timeout
);
5522 if (device
->always_use_syncobj
&&
5523 radv_all_fences_syncobj(fenceCount
, pFences
))
5525 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5527 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5529 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5530 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5531 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5534 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5537 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5540 if (!waitAll
&& fenceCount
> 1) {
5541 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5542 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5543 uint32_t wait_count
= 0;
5544 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5546 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5548 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5549 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5551 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5556 fences
[wait_count
++] = fence
->fence
;
5559 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5560 waitAll
, timeout
- radv_get_current_time());
5563 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5566 while(radv_get_current_time() <= timeout
) {
5567 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5568 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5575 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5576 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5577 bool expired
= false;
5579 if (fence
->temp_syncobj
) {
5580 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5585 if (fence
->syncobj
) {
5586 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5592 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5593 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5594 radv_get_current_time() <= timeout
)
5598 expired
= device
->ws
->fence_wait(device
->ws
,
5605 if (fence
->fence_wsi
) {
5606 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5607 if (result
!= VK_SUCCESS
)
5615 VkResult
radv_ResetFences(VkDevice _device
,
5616 uint32_t fenceCount
,
5617 const VkFence
*pFences
)
5619 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5621 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5622 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5624 device
->ws
->reset_fence(fence
->fence
);
5626 /* Per spec, we first restore the permanent payload, and then reset, so
5627 * having a temp syncobj should not skip resetting the permanent syncobj. */
5628 if (fence
->temp_syncobj
) {
5629 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5630 fence
->temp_syncobj
= 0;
5633 if (fence
->syncobj
) {
5634 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5641 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5643 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5644 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5646 if (fence
->temp_syncobj
) {
5647 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5648 return success
? VK_SUCCESS
: VK_NOT_READY
;
5651 if (fence
->syncobj
) {
5652 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5653 return success
? VK_SUCCESS
: VK_NOT_READY
;
5657 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5658 return VK_NOT_READY
;
5660 if (fence
->fence_wsi
) {
5661 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5663 if (result
!= VK_SUCCESS
) {
5664 if (result
== VK_TIMEOUT
)
5665 return VK_NOT_READY
;
5673 // Queue semaphore functions
5676 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5678 timeline
->highest_signaled
= value
;
5679 timeline
->highest_submitted
= value
;
5680 list_inithead(&timeline
->points
);
5681 list_inithead(&timeline
->free_points
);
5682 list_inithead(&timeline
->waiters
);
5683 pthread_mutex_init(&timeline
->mutex
, NULL
);
5687 radv_destroy_timeline(struct radv_device
*device
,
5688 struct radv_timeline
*timeline
)
5690 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5691 &timeline
->free_points
, list
) {
5692 list_del(&point
->list
);
5693 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5696 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5697 &timeline
->points
, list
) {
5698 list_del(&point
->list
);
5699 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5702 pthread_mutex_destroy(&timeline
->mutex
);
5706 radv_timeline_gc_locked(struct radv_device
*device
,
5707 struct radv_timeline
*timeline
)
5709 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5710 &timeline
->points
, list
) {
5711 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5714 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5715 timeline
->highest_signaled
= point
->value
;
5716 list_del(&point
->list
);
5717 list_add(&point
->list
, &timeline
->free_points
);
5722 static struct radv_timeline_point
*
5723 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5724 struct radv_timeline
*timeline
,
5727 radv_timeline_gc_locked(device
, timeline
);
5729 if (p
<= timeline
->highest_signaled
)
5732 list_for_each_entry(struct radv_timeline_point
, point
,
5733 &timeline
->points
, list
) {
5734 if (point
->value
>= p
) {
5735 ++point
->wait_count
;
5742 static struct radv_timeline_point
*
5743 radv_timeline_add_point_locked(struct radv_device
*device
,
5744 struct radv_timeline
*timeline
,
5747 radv_timeline_gc_locked(device
, timeline
);
5749 struct radv_timeline_point
*ret
= NULL
;
5750 struct radv_timeline_point
*prev
= NULL
;
5752 if (p
<= timeline
->highest_signaled
)
5755 list_for_each_entry(struct radv_timeline_point
, point
,
5756 &timeline
->points
, list
) {
5757 if (point
->value
== p
) {
5761 if (point
->value
< p
)
5765 if (list_is_empty(&timeline
->free_points
)) {
5766 ret
= malloc(sizeof(struct radv_timeline_point
));
5767 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5769 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5770 list_del(&ret
->list
);
5772 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5776 ret
->wait_count
= 1;
5779 list_add(&ret
->list
, &prev
->list
);
5781 list_addtail(&ret
->list
, &timeline
->points
);
5788 radv_timeline_wait_locked(struct radv_device
*device
,
5789 struct radv_timeline
*timeline
,
5791 uint64_t abs_timeout
)
5793 while(timeline
->highest_submitted
< value
) {
5794 struct timespec abstime
;
5795 timespec_from_nsec(&abstime
, abs_timeout
);
5797 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5799 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5803 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5807 pthread_mutex_unlock(&timeline
->mutex
);
5809 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5811 pthread_mutex_lock(&timeline
->mutex
);
5812 point
->wait_count
--;
5813 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5817 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5818 struct list_head
*processing_list
)
5820 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5821 &timeline
->waiters
, list
) {
5822 if (waiter
->value
> timeline
->highest_submitted
)
5825 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5826 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5828 list_del(&waiter
->list
);
5833 void radv_destroy_semaphore_part(struct radv_device
*device
,
5834 struct radv_semaphore_part
*part
)
5836 switch(part
->kind
) {
5837 case RADV_SEMAPHORE_NONE
:
5839 case RADV_SEMAPHORE_WINSYS
:
5840 device
->ws
->destroy_sem(part
->ws_sem
);
5842 case RADV_SEMAPHORE_TIMELINE
:
5843 radv_destroy_timeline(device
, &part
->timeline
);
5845 case RADV_SEMAPHORE_SYNCOBJ
:
5846 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5849 part
->kind
= RADV_SEMAPHORE_NONE
;
5852 static VkSemaphoreTypeKHR
5853 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5855 const VkSemaphoreTypeCreateInfo
*type_info
=
5856 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5859 return VK_SEMAPHORE_TYPE_BINARY
;
5862 *initial_value
= type_info
->initialValue
;
5863 return type_info
->semaphoreType
;
5866 VkResult
radv_CreateSemaphore(
5868 const VkSemaphoreCreateInfo
* pCreateInfo
,
5869 const VkAllocationCallbacks
* pAllocator
,
5870 VkSemaphore
* pSemaphore
)
5872 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5873 const VkExportSemaphoreCreateInfo
*export
=
5874 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5875 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5876 export
? export
->handleTypes
: 0;
5877 uint64_t initial_value
= 0;
5878 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5880 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5882 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5884 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5886 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5887 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5889 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5890 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5891 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5892 } else if (device
->always_use_syncobj
|| handleTypes
) {
5893 assert (device
->physical_device
->rad_info
.has_syncobj
);
5894 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
5896 vk_free2(&device
->alloc
, pAllocator
, sem
);
5897 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5899 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5901 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5902 if (!sem
->permanent
.ws_sem
) {
5903 vk_free2(&device
->alloc
, pAllocator
, sem
);
5904 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5906 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5909 *pSemaphore
= radv_semaphore_to_handle(sem
);
5913 void radv_DestroySemaphore(
5915 VkSemaphore _semaphore
,
5916 const VkAllocationCallbacks
* pAllocator
)
5918 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5919 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5923 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5924 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5925 vk_free2(&device
->alloc
, pAllocator
, sem
);
5929 radv_GetSemaphoreCounterValue(VkDevice _device
,
5930 VkSemaphore _semaphore
,
5933 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5934 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5936 struct radv_semaphore_part
*part
=
5937 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5939 switch (part
->kind
) {
5940 case RADV_SEMAPHORE_TIMELINE
: {
5941 pthread_mutex_lock(&part
->timeline
.mutex
);
5942 radv_timeline_gc_locked(device
, &part
->timeline
);
5943 *pValue
= part
->timeline
.highest_signaled
;
5944 pthread_mutex_unlock(&part
->timeline
.mutex
);
5947 case RADV_SEMAPHORE_NONE
:
5948 case RADV_SEMAPHORE_SYNCOBJ
:
5949 case RADV_SEMAPHORE_WINSYS
:
5950 unreachable("Invalid semaphore type");
5952 unreachable("Unhandled semaphore type");
5957 radv_wait_timelines(struct radv_device
*device
,
5958 const VkSemaphoreWaitInfo
* pWaitInfo
,
5959 uint64_t abs_timeout
)
5961 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5963 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5964 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5965 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5966 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5967 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5969 if (result
== VK_SUCCESS
)
5972 if (radv_get_current_time() > abs_timeout
)
5977 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5978 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5979 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5980 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5981 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5983 if (result
!= VK_SUCCESS
)
5989 radv_WaitSemaphores(VkDevice _device
,
5990 const VkSemaphoreWaitInfo
* pWaitInfo
,
5993 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5994 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5995 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5999 radv_SignalSemaphore(VkDevice _device
,
6000 const VkSemaphoreSignalInfo
* pSignalInfo
)
6002 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6003 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6005 struct radv_semaphore_part
*part
=
6006 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6008 switch(part
->kind
) {
6009 case RADV_SEMAPHORE_TIMELINE
: {
6010 pthread_mutex_lock(&part
->timeline
.mutex
);
6011 radv_timeline_gc_locked(device
, &part
->timeline
);
6012 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6013 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6015 struct list_head processing_list
;
6016 list_inithead(&processing_list
);
6017 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6018 pthread_mutex_unlock(&part
->timeline
.mutex
);
6020 return radv_process_submissions(&processing_list
);
6022 case RADV_SEMAPHORE_NONE
:
6023 case RADV_SEMAPHORE_SYNCOBJ
:
6024 case RADV_SEMAPHORE_WINSYS
:
6025 unreachable("Invalid semaphore type");
6032 VkResult
radv_CreateEvent(
6034 const VkEventCreateInfo
* pCreateInfo
,
6035 const VkAllocationCallbacks
* pAllocator
,
6038 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6039 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6041 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6044 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6046 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6048 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6049 RADV_BO_PRIORITY_FENCE
);
6051 vk_free2(&device
->alloc
, pAllocator
, event
);
6052 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6055 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6057 *pEvent
= radv_event_to_handle(event
);
6062 void radv_DestroyEvent(
6065 const VkAllocationCallbacks
* pAllocator
)
6067 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6068 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6072 device
->ws
->buffer_destroy(event
->bo
);
6073 vk_free2(&device
->alloc
, pAllocator
, event
);
6076 VkResult
radv_GetEventStatus(
6080 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6082 if (*event
->map
== 1)
6083 return VK_EVENT_SET
;
6084 return VK_EVENT_RESET
;
6087 VkResult
radv_SetEvent(
6091 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6097 VkResult
radv_ResetEvent(
6101 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6107 VkResult
radv_CreateBuffer(
6109 const VkBufferCreateInfo
* pCreateInfo
,
6110 const VkAllocationCallbacks
* pAllocator
,
6113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6114 struct radv_buffer
*buffer
;
6116 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6118 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6119 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6121 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6123 buffer
->size
= pCreateInfo
->size
;
6124 buffer
->usage
= pCreateInfo
->usage
;
6127 buffer
->flags
= pCreateInfo
->flags
;
6129 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6130 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6132 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6133 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6134 align64(buffer
->size
, 4096),
6135 4096, 0, RADEON_FLAG_VIRTUAL
,
6136 RADV_BO_PRIORITY_VIRTUAL
);
6138 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6139 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6143 *pBuffer
= radv_buffer_to_handle(buffer
);
6148 void radv_DestroyBuffer(
6151 const VkAllocationCallbacks
* pAllocator
)
6153 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6154 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6159 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6160 device
->ws
->buffer_destroy(buffer
->bo
);
6162 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6165 VkDeviceAddress
radv_GetBufferDeviceAddress(
6167 const VkBufferDeviceAddressInfo
* pInfo
)
6169 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6170 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6174 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6175 const VkBufferDeviceAddressInfo
* pInfo
)
6180 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6181 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6186 static inline unsigned
6187 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6190 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6192 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6195 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6197 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6201 radv_init_dcc_control_reg(struct radv_device
*device
,
6202 struct radv_image_view
*iview
)
6204 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6205 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6206 unsigned max_compressed_block_size
;
6207 unsigned independent_128b_blocks
;
6208 unsigned independent_64b_blocks
;
6210 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6213 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6214 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6215 * dGPU and 64 for APU because all of our APUs to date use
6216 * DIMMs which have a request granularity size of 64B while all
6217 * other chips have a 32B request size.
6219 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6222 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6223 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6224 independent_64b_blocks
= 0;
6225 independent_128b_blocks
= 1;
6227 independent_128b_blocks
= 0;
6229 if (iview
->image
->info
.samples
> 1) {
6230 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6231 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6232 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6233 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6236 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6237 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6238 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6239 /* If this DCC image is potentially going to be used in texture
6240 * fetches, we need some special settings.
6242 independent_64b_blocks
= 1;
6243 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6245 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6246 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6247 * big as possible for better compression state.
6249 independent_64b_blocks
= 0;
6250 max_compressed_block_size
= max_uncompressed_block_size
;
6254 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6255 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6256 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6257 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6258 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6262 radv_initialise_color_surface(struct radv_device
*device
,
6263 struct radv_color_buffer_info
*cb
,
6264 struct radv_image_view
*iview
)
6266 const struct vk_format_description
*desc
;
6267 unsigned ntype
, format
, swap
, endian
;
6268 unsigned blend_clamp
= 0, blend_bypass
= 0;
6270 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6271 const struct radeon_surf
*surf
= &plane
->surface
;
6273 desc
= vk_format_description(iview
->vk_format
);
6275 memset(cb
, 0, sizeof(*cb
));
6277 /* Intensity is implemented as Red, so treat it that way. */
6278 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6280 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6282 cb
->cb_color_base
= va
>> 8;
6284 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6285 struct gfx9_surf_meta_flags meta
;
6286 if (iview
->image
->dcc_offset
)
6287 meta
= surf
->u
.gfx9
.dcc
;
6289 meta
= surf
->u
.gfx9
.cmask
;
6291 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6292 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6293 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6294 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6295 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6297 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6298 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6299 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6300 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6301 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6304 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6305 cb
->cb_color_base
|= surf
->tile_swizzle
;
6307 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6308 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6310 cb
->cb_color_base
+= level_info
->offset
>> 8;
6311 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6312 cb
->cb_color_base
|= surf
->tile_swizzle
;
6314 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6315 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6316 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6318 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6319 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6320 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6322 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6324 if (radv_image_has_fmask(iview
->image
)) {
6325 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6326 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6327 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6328 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6330 /* This must be set for fast clear to work without FMASK. */
6331 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6332 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6333 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6334 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6338 /* CMASK variables */
6339 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6340 va
+= iview
->image
->cmask_offset
;
6341 cb
->cb_color_cmask
= va
>> 8;
6343 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6344 va
+= iview
->image
->dcc_offset
;
6346 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6347 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6348 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6350 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6351 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6353 cb
->cb_dcc_base
= va
>> 8;
6354 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6356 /* GFX10 field has the same base shift as the GFX6 field. */
6357 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6358 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6359 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6361 if (iview
->image
->info
.samples
> 1) {
6362 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6364 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6365 S_028C74_NUM_FRAGMENTS(log_samples
);
6368 if (radv_image_has_fmask(iview
->image
)) {
6369 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6370 cb
->cb_color_fmask
= va
>> 8;
6371 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6373 cb
->cb_color_fmask
= cb
->cb_color_base
;
6376 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6378 vk_format_get_first_non_void_channel(iview
->vk_format
));
6379 format
= radv_translate_colorformat(iview
->vk_format
);
6380 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6381 radv_finishme("Illegal color\n");
6382 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6383 endian
= radv_colorformat_endian_swap(format
);
6385 /* blend clamp should be set for all NORM/SRGB types */
6386 if (ntype
== V_028C70_NUMBER_UNORM
||
6387 ntype
== V_028C70_NUMBER_SNORM
||
6388 ntype
== V_028C70_NUMBER_SRGB
)
6391 /* set blend bypass according to docs if SINT/UINT or
6392 8/24 COLOR variants */
6393 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6394 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6395 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6400 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6401 (format
== V_028C70_COLOR_8
||
6402 format
== V_028C70_COLOR_8_8
||
6403 format
== V_028C70_COLOR_8_8_8_8
))
6404 ->color_is_int8
= true;
6406 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6407 S_028C70_COMP_SWAP(swap
) |
6408 S_028C70_BLEND_CLAMP(blend_clamp
) |
6409 S_028C70_BLEND_BYPASS(blend_bypass
) |
6410 S_028C70_SIMPLE_FLOAT(1) |
6411 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6412 ntype
!= V_028C70_NUMBER_SNORM
&&
6413 ntype
!= V_028C70_NUMBER_SRGB
&&
6414 format
!= V_028C70_COLOR_8_24
&&
6415 format
!= V_028C70_COLOR_24_8
) |
6416 S_028C70_NUMBER_TYPE(ntype
) |
6417 S_028C70_ENDIAN(endian
);
6418 if (radv_image_has_fmask(iview
->image
)) {
6419 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6420 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6421 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6422 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6425 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6426 /* Allow the texture block to read FMASK directly
6427 * without decompressing it. This bit must be cleared
6428 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6429 * otherwise the operation doesn't happen.
6431 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6433 /* Set CMASK into a tiling format that allows the
6434 * texture block to read it.
6436 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6440 if (radv_image_has_cmask(iview
->image
) &&
6441 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6442 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6444 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6445 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6447 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6449 /* This must be set for fast clear to work without FMASK. */
6450 if (!radv_image_has_fmask(iview
->image
) &&
6451 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6452 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6453 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6456 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6457 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6459 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6460 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6461 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6462 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6464 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6465 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6467 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6468 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6469 S_028EE0_RESOURCE_LEVEL(1);
6471 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6472 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6473 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6476 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6477 S_028C68_MIP0_HEIGHT(height
- 1) |
6478 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6483 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6484 struct radv_image_view
*iview
)
6486 unsigned max_zplanes
= 0;
6488 assert(radv_image_is_tc_compat_htile(iview
->image
));
6490 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6491 /* Default value for 32-bit depth surfaces. */
6494 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6495 iview
->image
->info
.samples
> 1)
6498 max_zplanes
= max_zplanes
+ 1;
6500 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6501 /* Do not enable Z plane compression for 16-bit depth
6502 * surfaces because isn't supported on GFX8. Only
6503 * 32-bit depth surfaces are supported by the hardware.
6504 * This allows to maintain shader compatibility and to
6505 * reduce the number of depth decompressions.
6509 if (iview
->image
->info
.samples
<= 1)
6511 else if (iview
->image
->info
.samples
<= 4)
6522 radv_initialise_ds_surface(struct radv_device
*device
,
6523 struct radv_ds_buffer_info
*ds
,
6524 struct radv_image_view
*iview
)
6526 unsigned level
= iview
->base_mip
;
6527 unsigned format
, stencil_format
;
6528 uint64_t va
, s_offs
, z_offs
;
6529 bool stencil_only
= false;
6530 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6531 const struct radeon_surf
*surf
= &plane
->surface
;
6533 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6535 memset(ds
, 0, sizeof(*ds
));
6536 switch (iview
->image
->vk_format
) {
6537 case VK_FORMAT_D24_UNORM_S8_UINT
:
6538 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6539 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6540 ds
->offset_scale
= 2.0f
;
6542 case VK_FORMAT_D16_UNORM
:
6543 case VK_FORMAT_D16_UNORM_S8_UINT
:
6544 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6545 ds
->offset_scale
= 4.0f
;
6547 case VK_FORMAT_D32_SFLOAT
:
6548 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6549 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6550 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6551 ds
->offset_scale
= 1.0f
;
6553 case VK_FORMAT_S8_UINT
:
6554 stencil_only
= true;
6560 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6561 stencil_format
= surf
->has_stencil
?
6562 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6564 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6565 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6566 S_028008_SLICE_MAX(max_slice
);
6567 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6568 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6569 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6572 ds
->db_htile_data_base
= 0;
6573 ds
->db_htile_surface
= 0;
6575 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6576 s_offs
= z_offs
= va
;
6578 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6579 assert(surf
->u
.gfx9
.surf_offset
== 0);
6580 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6582 ds
->db_z_info
= S_028038_FORMAT(format
) |
6583 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6584 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6585 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6586 S_028038_ZRANGE_PRECISION(1);
6587 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6588 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6590 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6591 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6592 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6595 ds
->db_depth_view
|= S_028008_MIPID(level
);
6596 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6597 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6599 if (radv_htile_enabled(iview
->image
, level
)) {
6600 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6602 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6603 unsigned max_zplanes
=
6604 radv_calc_decompress_on_z_planes(device
, iview
);
6606 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6608 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6609 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6610 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6612 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6613 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6617 if (!surf
->has_stencil
)
6618 /* Use all of the htile_buffer for depth if there's no stencil. */
6619 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6620 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6621 iview
->image
->htile_offset
;
6622 ds
->db_htile_data_base
= va
>> 8;
6623 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6624 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6626 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6627 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6631 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6634 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6636 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6637 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6639 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6640 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6641 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6643 if (iview
->image
->info
.samples
> 1)
6644 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6646 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6647 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6648 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6649 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6650 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6651 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6652 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6653 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6656 tile_mode
= stencil_tile_mode
;
6658 ds
->db_depth_info
|=
6659 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6660 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6661 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6662 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6663 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6664 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6665 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6666 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6668 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6669 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6670 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6671 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6673 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6676 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6677 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6678 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6680 if (radv_htile_enabled(iview
->image
, level
)) {
6681 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6683 if (!surf
->has_stencil
&&
6684 !radv_image_is_tc_compat_htile(iview
->image
))
6685 /* Use all of the htile_buffer for depth if there's no stencil. */
6686 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6688 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6689 iview
->image
->htile_offset
;
6690 ds
->db_htile_data_base
= va
>> 8;
6691 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6693 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6694 unsigned max_zplanes
=
6695 radv_calc_decompress_on_z_planes(device
, iview
);
6697 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6698 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6703 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6704 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6707 VkResult
radv_CreateFramebuffer(
6709 const VkFramebufferCreateInfo
* pCreateInfo
,
6710 const VkAllocationCallbacks
* pAllocator
,
6711 VkFramebuffer
* pFramebuffer
)
6713 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6714 struct radv_framebuffer
*framebuffer
;
6715 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6716 vk_find_struct_const(pCreateInfo
->pNext
,
6717 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6719 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6721 size_t size
= sizeof(*framebuffer
);
6722 if (!imageless_create_info
)
6723 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6724 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6725 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6726 if (framebuffer
== NULL
)
6727 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6729 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6730 framebuffer
->width
= pCreateInfo
->width
;
6731 framebuffer
->height
= pCreateInfo
->height
;
6732 framebuffer
->layers
= pCreateInfo
->layers
;
6733 if (imageless_create_info
) {
6734 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6735 const VkFramebufferAttachmentImageInfo
*attachment
=
6736 imageless_create_info
->pAttachmentImageInfos
+ i
;
6737 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6738 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6739 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6742 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6743 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6744 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6745 framebuffer
->attachments
[i
] = iview
;
6746 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6747 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6748 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6752 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6756 void radv_DestroyFramebuffer(
6759 const VkAllocationCallbacks
* pAllocator
)
6761 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6762 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6766 vk_free2(&device
->alloc
, pAllocator
, fb
);
6769 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6771 switch (address_mode
) {
6772 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6773 return V_008F30_SQ_TEX_WRAP
;
6774 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6775 return V_008F30_SQ_TEX_MIRROR
;
6776 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6777 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6778 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6779 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6780 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6781 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6783 unreachable("illegal tex wrap mode");
6789 radv_tex_compare(VkCompareOp op
)
6792 case VK_COMPARE_OP_NEVER
:
6793 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6794 case VK_COMPARE_OP_LESS
:
6795 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6796 case VK_COMPARE_OP_EQUAL
:
6797 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6798 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6799 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6800 case VK_COMPARE_OP_GREATER
:
6801 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6802 case VK_COMPARE_OP_NOT_EQUAL
:
6803 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6804 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6805 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6806 case VK_COMPARE_OP_ALWAYS
:
6807 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6809 unreachable("illegal compare mode");
6815 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6818 case VK_FILTER_NEAREST
:
6819 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6820 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6821 case VK_FILTER_LINEAR
:
6822 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6823 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6824 case VK_FILTER_CUBIC_IMG
:
6826 fprintf(stderr
, "illegal texture filter");
6832 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6835 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6836 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6837 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6838 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6840 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6845 radv_tex_bordercolor(VkBorderColor bcolor
)
6848 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6849 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6850 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6851 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6852 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6853 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6854 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6855 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6856 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6864 radv_tex_aniso_filter(unsigned filter
)
6878 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6881 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6882 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6883 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6884 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6885 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6886 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6894 radv_get_max_anisotropy(struct radv_device
*device
,
6895 const VkSamplerCreateInfo
*pCreateInfo
)
6897 if (device
->force_aniso
>= 0)
6898 return device
->force_aniso
;
6900 if (pCreateInfo
->anisotropyEnable
&&
6901 pCreateInfo
->maxAnisotropy
> 1.0f
)
6902 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6908 radv_init_sampler(struct radv_device
*device
,
6909 struct radv_sampler
*sampler
,
6910 const VkSamplerCreateInfo
*pCreateInfo
)
6912 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6913 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6914 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6915 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6916 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6917 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6919 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6920 vk_find_struct_const(pCreateInfo
->pNext
,
6921 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6922 if (sampler_reduction
)
6923 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6925 if (pCreateInfo
->compareEnable
)
6926 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6928 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6929 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6930 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6931 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6932 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6933 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6934 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6935 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6936 S_008F30_DISABLE_CUBE_WRAP(0) |
6937 S_008F30_COMPAT_MODE(compat_mode
) |
6938 S_008F30_FILTER_MODE(filter_mode
));
6939 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6940 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6941 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6942 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6943 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6944 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6945 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6946 S_008F38_MIP_POINT_PRECLAMP(0));
6947 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6948 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
6950 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6951 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6953 sampler
->state
[2] |=
6954 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6955 S_008F38_FILTER_PREC_FIX(1) |
6956 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6960 VkResult
radv_CreateSampler(
6962 const VkSamplerCreateInfo
* pCreateInfo
,
6963 const VkAllocationCallbacks
* pAllocator
,
6964 VkSampler
* pSampler
)
6966 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6967 struct radv_sampler
*sampler
;
6969 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
6970 vk_find_struct_const(pCreateInfo
->pNext
,
6971 SAMPLER_YCBCR_CONVERSION_INFO
);
6973 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
6975 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
6976 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6978 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6980 radv_init_sampler(device
, sampler
, pCreateInfo
);
6982 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
6983 *pSampler
= radv_sampler_to_handle(sampler
);
6988 void radv_DestroySampler(
6991 const VkAllocationCallbacks
* pAllocator
)
6993 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6994 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
6998 vk_free2(&device
->alloc
, pAllocator
, sampler
);
7001 /* vk_icd.h does not declare this function, so we declare it here to
7002 * suppress Wmissing-prototypes.
7004 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7005 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7007 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7008 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7010 /* For the full details on loader interface versioning, see
7011 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7012 * What follows is a condensed summary, to help you navigate the large and
7013 * confusing official doc.
7015 * - Loader interface v0 is incompatible with later versions. We don't
7018 * - In loader interface v1:
7019 * - The first ICD entrypoint called by the loader is
7020 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7022 * - The ICD must statically expose no other Vulkan symbol unless it is
7023 * linked with -Bsymbolic.
7024 * - Each dispatchable Vulkan handle created by the ICD must be
7025 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7026 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7027 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7028 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7029 * such loader-managed surfaces.
7031 * - Loader interface v2 differs from v1 in:
7032 * - The first ICD entrypoint called by the loader is
7033 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7034 * statically expose this entrypoint.
7036 * - Loader interface v3 differs from v2 in:
7037 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7038 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7039 * because the loader no longer does so.
7041 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7045 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7046 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7049 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7050 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7052 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7054 /* At the moment, we support only the below handle types. */
7055 assert(pGetFdInfo
->handleType
==
7056 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7057 pGetFdInfo
->handleType
==
7058 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7060 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7062 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7066 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7067 VkExternalMemoryHandleTypeFlagBits handleType
,
7069 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7071 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7073 switch (handleType
) {
7074 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7075 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7079 /* The valid usage section for this function says:
7081 * "handleType must not be one of the handle types defined as
7084 * So opaque handle types fall into the default "unsupported" case.
7086 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7090 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7094 uint32_t syncobj_handle
= 0;
7095 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7097 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7100 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7102 *syncobj
= syncobj_handle
;
7108 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7112 /* If we create a syncobj we do it locally so that if we have an error, we don't
7113 * leave a syncobj in an undetermined state in the fence. */
7114 uint32_t syncobj_handle
= *syncobj
;
7115 if (!syncobj_handle
) {
7116 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7118 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7123 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7125 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7127 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7130 *syncobj
= syncobj_handle
;
7137 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7138 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7140 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7141 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7143 struct radv_semaphore_part
*dst
= NULL
;
7145 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7146 dst
= &sem
->temporary
;
7148 dst
= &sem
->permanent
;
7151 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7153 switch(pImportSemaphoreFdInfo
->handleType
) {
7154 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7155 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7157 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7158 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7161 unreachable("Unhandled semaphore handle type");
7164 if (result
== VK_SUCCESS
) {
7165 dst
->syncobj
= syncobj
;
7166 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7172 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7173 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7176 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7177 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7179 uint32_t syncobj_handle
;
7181 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7182 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7183 syncobj_handle
= sem
->temporary
.syncobj
;
7185 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7186 syncobj_handle
= sem
->permanent
.syncobj
;
7189 switch(pGetFdInfo
->handleType
) {
7190 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7191 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7193 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7194 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7196 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7197 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7199 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7204 unreachable("Unhandled semaphore handle type");
7208 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7212 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7213 VkPhysicalDevice physicalDevice
,
7214 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7215 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7217 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7218 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7220 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7221 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7222 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7223 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7225 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7226 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7227 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7228 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7229 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7230 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7231 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7232 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7233 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7234 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7235 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7236 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7237 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7239 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7240 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7241 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7245 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7246 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7248 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7249 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7250 uint32_t *syncobj_dst
= NULL
;
7253 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7254 syncobj_dst
= &fence
->temp_syncobj
;
7256 syncobj_dst
= &fence
->syncobj
;
7259 switch(pImportFenceFdInfo
->handleType
) {
7260 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7261 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7262 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7263 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7265 unreachable("Unhandled fence handle type");
7269 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7270 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7273 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7274 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7276 uint32_t syncobj_handle
;
7278 if (fence
->temp_syncobj
)
7279 syncobj_handle
= fence
->temp_syncobj
;
7281 syncobj_handle
= fence
->syncobj
;
7283 switch(pGetFdInfo
->handleType
) {
7284 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7285 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7287 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7288 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7290 if (fence
->temp_syncobj
) {
7291 close (fence
->temp_syncobj
);
7292 fence
->temp_syncobj
= 0;
7294 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7299 unreachable("Unhandled fence handle type");
7303 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7307 void radv_GetPhysicalDeviceExternalFenceProperties(
7308 VkPhysicalDevice physicalDevice
,
7309 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7310 VkExternalFenceProperties
*pExternalFenceProperties
)
7312 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7314 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7315 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7316 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7317 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7318 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7319 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7320 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7322 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7323 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7324 pExternalFenceProperties
->externalFenceFeatures
= 0;
7329 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7330 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7331 const VkAllocationCallbacks
* pAllocator
,
7332 VkDebugReportCallbackEXT
* pCallback
)
7334 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7335 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7336 pCreateInfo
, pAllocator
, &instance
->alloc
,
7341 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7342 VkDebugReportCallbackEXT _callback
,
7343 const VkAllocationCallbacks
* pAllocator
)
7345 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7346 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7347 _callback
, pAllocator
, &instance
->alloc
);
7351 radv_DebugReportMessageEXT(VkInstance _instance
,
7352 VkDebugReportFlagsEXT flags
,
7353 VkDebugReportObjectTypeEXT objectType
,
7356 int32_t messageCode
,
7357 const char* pLayerPrefix
,
7358 const char* pMessage
)
7360 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7361 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7362 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7366 radv_GetDeviceGroupPeerMemoryFeatures(
7369 uint32_t localDeviceIndex
,
7370 uint32_t remoteDeviceIndex
,
7371 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7373 assert(localDeviceIndex
== remoteDeviceIndex
);
7375 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7376 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7377 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7378 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7381 static const VkTimeDomainEXT radv_time_domains
[] = {
7382 VK_TIME_DOMAIN_DEVICE_EXT
,
7383 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7384 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7387 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7388 VkPhysicalDevice physicalDevice
,
7389 uint32_t *pTimeDomainCount
,
7390 VkTimeDomainEXT
*pTimeDomains
)
7393 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7395 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7396 vk_outarray_append(&out
, i
) {
7397 *i
= radv_time_domains
[d
];
7401 return vk_outarray_status(&out
);
7405 radv_clock_gettime(clockid_t clock_id
)
7407 struct timespec current
;
7410 ret
= clock_gettime(clock_id
, ¤t
);
7411 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7412 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7416 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7419 VkResult
radv_GetCalibratedTimestampsEXT(
7421 uint32_t timestampCount
,
7422 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7423 uint64_t *pTimestamps
,
7424 uint64_t *pMaxDeviation
)
7426 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7427 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7429 uint64_t begin
, end
;
7430 uint64_t max_clock_period
= 0;
7432 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7434 for (d
= 0; d
< timestampCount
; d
++) {
7435 switch (pTimestampInfos
[d
].timeDomain
) {
7436 case VK_TIME_DOMAIN_DEVICE_EXT
:
7437 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7439 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7440 max_clock_period
= MAX2(max_clock_period
, device_period
);
7442 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7443 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7444 max_clock_period
= MAX2(max_clock_period
, 1);
7447 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7448 pTimestamps
[d
] = begin
;
7456 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7459 * The maximum deviation is the sum of the interval over which we
7460 * perform the sampling and the maximum period of any sampled
7461 * clock. That's because the maximum skew between any two sampled
7462 * clock edges is when the sampled clock with the largest period is
7463 * sampled at the end of that period but right at the beginning of the
7464 * sampling interval and some other clock is sampled right at the
7465 * begining of its sampling period and right at the end of the
7466 * sampling interval. Let's assume the GPU has the longest clock
7467 * period and that the application is sampling GPU and monotonic:
7470 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7471 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7475 * GPU -----_____-----_____-----_____-----_____
7478 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7479 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7481 * Interval <----------------->
7482 * Deviation <-------------------------->
7486 * m = read(monotonic) 2
7489 * We round the sample interval up by one tick to cover sampling error
7490 * in the interval clock
7493 uint64_t sample_interval
= end
- begin
+ 1;
7495 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7500 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7501 VkPhysicalDevice physicalDevice
,
7502 VkSampleCountFlagBits samples
,
7503 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7505 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7506 VK_SAMPLE_COUNT_4_BIT
|
7507 VK_SAMPLE_COUNT_8_BIT
)) {
7508 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7510 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };