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radv: Add winsys functions for timeline syncobj.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {NULL, 0}
527 };
528
529 const char *
530 radv_get_debug_option_name(int id)
531 {
532 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
533 return radv_debug_options[id].string;
534 }
535
536 static const struct debug_control radv_perftest_options[] = {
537 {"localbos", RADV_PERFTEST_LOCAL_BOS},
538 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
539 {"bolist", RADV_PERFTEST_BO_LIST},
540 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
541 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
542 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
543 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
544 {"dfsm", RADV_PERFTEST_DFSM},
545 {NULL, 0}
546 };
547
548 const char *
549 radv_get_perftest_option_name(int id)
550 {
551 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
552 return radv_perftest_options[id].string;
553 }
554
555 static void
556 radv_handle_per_app_options(struct radv_instance *instance,
557 const VkApplicationInfo *info)
558 {
559 const char *name = info ? info->pApplicationName : NULL;
560 const char *engine_name = info ? info->pEngineName : NULL;
561
562 if (name) {
563 if (!strcmp(name, "DOOM_VFR")) {
564 /* Work around a Doom VFR game bug */
565 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
566 } else if (!strcmp(name, "Fledge")) {
567 /*
568 * Zero VRAM for "The Surge 2"
569 *
570 * This avoid a hang when when rendering any level. Likely
571 * uninitialized data in an indirect draw.
572 */
573 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
574 } else if (!strcmp(name, "No Man's Sky")) {
575 /* Work around a NMS game bug */
576 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
577 } else if (!strcmp(name, "DOOMEternal")) {
578 /* Zero VRAM for Doom Eternal to fix rendering issues. */
579 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
580 } else if (!strcmp(name, "Red Dead Redemption 2")) {
581 /* Work around a RDR2 game bug */
582 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
583 }
584 }
585
586 if (engine_name) {
587 if (!strcmp(engine_name, "vkd3d")) {
588 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
589 * rendering issues.
590 */
591 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
592 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
593 /* Fix various artifacts in Detroit: Become Human */
594 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
595 RADV_DEBUG_DISCARD_TO_DEMOTE;
596 }
597 }
598
599 instance->enable_mrt_output_nan_fixup =
600 driQueryOptionb(&instance->dri_options,
601 "radv_enable_mrt_output_nan_fixup");
602
603 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
604 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
605 }
606
607 static const char radv_dri_options_xml[] =
608 DRI_CONF_BEGIN
609 DRI_CONF_SECTION_PERFORMANCE
610 DRI_CONF_ADAPTIVE_SYNC("true")
611 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
612 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
613 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
614 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
615 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
616 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
617 DRI_CONF_SECTION_END
618
619 DRI_CONF_SECTION_DEBUG
620 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
621 DRI_CONF_SECTION_END
622 DRI_CONF_END;
623
624 static void radv_init_dri_options(struct radv_instance *instance)
625 {
626 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
627 driParseConfigFiles(&instance->dri_options,
628 &instance->available_dri_options,
629 0, "radv", NULL,
630 instance->engineName,
631 instance->engineVersion);
632 }
633
634 VkResult radv_CreateInstance(
635 const VkInstanceCreateInfo* pCreateInfo,
636 const VkAllocationCallbacks* pAllocator,
637 VkInstance* pInstance)
638 {
639 struct radv_instance *instance;
640 VkResult result;
641
642 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
643 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
644 if (!instance)
645 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
646
647 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
648
649 if (pAllocator)
650 instance->alloc = *pAllocator;
651 else
652 instance->alloc = default_alloc;
653
654 if (pCreateInfo->pApplicationInfo) {
655 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
656
657 instance->engineName =
658 vk_strdup(&instance->alloc, app->pEngineName,
659 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
660 instance->engineVersion = app->engineVersion;
661 instance->apiVersion = app->apiVersion;
662 }
663
664 if (instance->apiVersion == 0)
665 instance->apiVersion = VK_API_VERSION_1_0;
666
667 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
668 radv_debug_options);
669
670 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
671 radv_perftest_options);
672
673 if (instance->debug_flags & RADV_DEBUG_STARTUP)
674 radv_logi("Created an instance");
675
676 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
677 int idx;
678 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
679 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
680 radv_instance_extensions[idx].extensionName))
681 break;
682 }
683
684 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
685 !radv_instance_extensions_supported.extensions[idx]) {
686 vk_object_base_finish(&instance->base);
687 vk_free2(&default_alloc, pAllocator, instance);
688 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
689 }
690
691 instance->enabled_extensions.extensions[idx] = true;
692 }
693
694 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
695
696 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
697 /* Vulkan requires that entrypoints for extensions which have
698 * not been enabled must not be advertised.
699 */
700 if (!unchecked &&
701 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
702 &instance->enabled_extensions)) {
703 instance->dispatch.entrypoints[i] = NULL;
704 } else {
705 instance->dispatch.entrypoints[i] =
706 radv_instance_dispatch_table.entrypoints[i];
707 }
708 }
709
710 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
711 /* Vulkan requires that entrypoints for extensions which have
712 * not been enabled must not be advertised.
713 */
714 if (!unchecked &&
715 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
716 &instance->enabled_extensions)) {
717 instance->physical_device_dispatch.entrypoints[i] = NULL;
718 } else {
719 instance->physical_device_dispatch.entrypoints[i] =
720 radv_physical_device_dispatch_table.entrypoints[i];
721 }
722 }
723
724 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
725 /* Vulkan requires that entrypoints for extensions which have
726 * not been enabled must not be advertised.
727 */
728 if (!unchecked &&
729 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
730 &instance->enabled_extensions, NULL)) {
731 instance->device_dispatch.entrypoints[i] = NULL;
732 } else {
733 instance->device_dispatch.entrypoints[i] =
734 radv_device_dispatch_table.entrypoints[i];
735 }
736 }
737
738 instance->physical_devices_enumerated = false;
739 list_inithead(&instance->physical_devices);
740
741 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
742 if (result != VK_SUCCESS) {
743 vk_object_base_finish(&instance->base);
744 vk_free2(&default_alloc, pAllocator, instance);
745 return vk_error(instance, result);
746 }
747
748 glsl_type_singleton_init_or_ref();
749
750 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
751
752 radv_init_dri_options(instance);
753 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
754
755 *pInstance = radv_instance_to_handle(instance);
756
757 return VK_SUCCESS;
758 }
759
760 void radv_DestroyInstance(
761 VkInstance _instance,
762 const VkAllocationCallbacks* pAllocator)
763 {
764 RADV_FROM_HANDLE(radv_instance, instance, _instance);
765
766 if (!instance)
767 return;
768
769 list_for_each_entry_safe(struct radv_physical_device, pdevice,
770 &instance->physical_devices, link) {
771 radv_physical_device_destroy(pdevice);
772 }
773
774 vk_free(&instance->alloc, instance->engineName);
775
776 VG(VALGRIND_DESTROY_MEMPOOL(instance));
777
778 glsl_type_singleton_decref();
779
780 driDestroyOptionCache(&instance->dri_options);
781 driDestroyOptionInfo(&instance->available_dri_options);
782
783 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
784
785 vk_object_base_finish(&instance->base);
786 vk_free(&instance->alloc, instance);
787 }
788
789 static VkResult
790 radv_enumerate_physical_devices(struct radv_instance *instance)
791 {
792 if (instance->physical_devices_enumerated)
793 return VK_SUCCESS;
794
795 instance->physical_devices_enumerated = true;
796
797 /* TODO: Check for more devices ? */
798 drmDevicePtr devices[8];
799 VkResult result = VK_SUCCESS;
800 int max_devices;
801
802 if (getenv("RADV_FORCE_FAMILY")) {
803 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
804 * device that allows to test the compiler without having an
805 * AMDGPU instance.
806 */
807 struct radv_physical_device *pdevice;
808
809 result = radv_physical_device_try_create(instance, NULL, &pdevice);
810 if (result != VK_SUCCESS)
811 return result;
812
813 list_addtail(&pdevice->link, &instance->physical_devices);
814 return VK_SUCCESS;
815 }
816
817 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
818
819 if (instance->debug_flags & RADV_DEBUG_STARTUP)
820 radv_logi("Found %d drm nodes", max_devices);
821
822 if (max_devices < 1)
823 return vk_error(instance, VK_SUCCESS);
824
825 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
826 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
827 devices[i]->bustype == DRM_BUS_PCI &&
828 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
829
830 struct radv_physical_device *pdevice;
831 result = radv_physical_device_try_create(instance, devices[i],
832 &pdevice);
833 /* Incompatible DRM device, skip. */
834 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
835 result = VK_SUCCESS;
836 continue;
837 }
838
839 /* Error creating the physical device, report the error. */
840 if (result != VK_SUCCESS)
841 break;
842
843 list_addtail(&pdevice->link, &instance->physical_devices);
844 }
845 }
846 drmFreeDevices(devices, max_devices);
847
848 /* If we successfully enumerated any devices, call it success */
849 return result;
850 }
851
852 VkResult radv_EnumeratePhysicalDevices(
853 VkInstance _instance,
854 uint32_t* pPhysicalDeviceCount,
855 VkPhysicalDevice* pPhysicalDevices)
856 {
857 RADV_FROM_HANDLE(radv_instance, instance, _instance);
858 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
859
860 VkResult result = radv_enumerate_physical_devices(instance);
861 if (result != VK_SUCCESS)
862 return result;
863
864 list_for_each_entry(struct radv_physical_device, pdevice,
865 &instance->physical_devices, link) {
866 vk_outarray_append(&out, i) {
867 *i = radv_physical_device_to_handle(pdevice);
868 }
869 }
870
871 return vk_outarray_status(&out);
872 }
873
874 VkResult radv_EnumeratePhysicalDeviceGroups(
875 VkInstance _instance,
876 uint32_t* pPhysicalDeviceGroupCount,
877 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
878 {
879 RADV_FROM_HANDLE(radv_instance, instance, _instance);
880 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
881 pPhysicalDeviceGroupCount);
882
883 VkResult result = radv_enumerate_physical_devices(instance);
884 if (result != VK_SUCCESS)
885 return result;
886
887 list_for_each_entry(struct radv_physical_device, pdevice,
888 &instance->physical_devices, link) {
889 vk_outarray_append(&out, p) {
890 p->physicalDeviceCount = 1;
891 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
892 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
893 p->subsetAllocation = false;
894 }
895 }
896
897 return vk_outarray_status(&out);
898 }
899
900 void radv_GetPhysicalDeviceFeatures(
901 VkPhysicalDevice physicalDevice,
902 VkPhysicalDeviceFeatures* pFeatures)
903 {
904 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
905 memset(pFeatures, 0, sizeof(*pFeatures));
906
907 *pFeatures = (VkPhysicalDeviceFeatures) {
908 .robustBufferAccess = true,
909 .fullDrawIndexUint32 = true,
910 .imageCubeArray = true,
911 .independentBlend = true,
912 .geometryShader = true,
913 .tessellationShader = true,
914 .sampleRateShading = true,
915 .dualSrcBlend = true,
916 .logicOp = true,
917 .multiDrawIndirect = true,
918 .drawIndirectFirstInstance = true,
919 .depthClamp = true,
920 .depthBiasClamp = true,
921 .fillModeNonSolid = true,
922 .depthBounds = true,
923 .wideLines = true,
924 .largePoints = true,
925 .alphaToOne = true,
926 .multiViewport = true,
927 .samplerAnisotropy = true,
928 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
929 .textureCompressionASTC_LDR = false,
930 .textureCompressionBC = true,
931 .occlusionQueryPrecise = true,
932 .pipelineStatisticsQuery = true,
933 .vertexPipelineStoresAndAtomics = true,
934 .fragmentStoresAndAtomics = true,
935 .shaderTessellationAndGeometryPointSize = true,
936 .shaderImageGatherExtended = true,
937 .shaderStorageImageExtendedFormats = true,
938 .shaderStorageImageMultisample = true,
939 .shaderUniformBufferArrayDynamicIndexing = true,
940 .shaderSampledImageArrayDynamicIndexing = true,
941 .shaderStorageBufferArrayDynamicIndexing = true,
942 .shaderStorageImageArrayDynamicIndexing = true,
943 .shaderStorageImageReadWithoutFormat = true,
944 .shaderStorageImageWriteWithoutFormat = true,
945 .shaderClipDistance = true,
946 .shaderCullDistance = true,
947 .shaderFloat64 = true,
948 .shaderInt64 = true,
949 .shaderInt16 = true,
950 .sparseBinding = true,
951 .variableMultisampleRate = true,
952 .shaderResourceMinLod = true,
953 .inheritedQueries = true,
954 };
955 }
956
957 static void
958 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
959 VkPhysicalDeviceVulkan11Features *f)
960 {
961 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
962
963 f->storageBuffer16BitAccess = true;
964 f->uniformAndStorageBuffer16BitAccess = true;
965 f->storagePushConstant16 = true;
966 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
967 f->multiview = true;
968 f->multiviewGeometryShader = true;
969 f->multiviewTessellationShader = true;
970 f->variablePointersStorageBuffer = true;
971 f->variablePointers = true;
972 f->protectedMemory = false;
973 f->samplerYcbcrConversion = true;
974 f->shaderDrawParameters = true;
975 }
976
977 static void
978 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
979 VkPhysicalDeviceVulkan12Features *f)
980 {
981 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
982
983 f->samplerMirrorClampToEdge = true;
984 f->drawIndirectCount = true;
985 f->storageBuffer8BitAccess = true;
986 f->uniformAndStorageBuffer8BitAccess = true;
987 f->storagePushConstant8 = true;
988 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
989 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
990 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
991 f->shaderInt8 = true;
992
993 f->descriptorIndexing = true;
994 f->shaderInputAttachmentArrayDynamicIndexing = true;
995 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
996 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
997 f->shaderUniformBufferArrayNonUniformIndexing = true;
998 f->shaderSampledImageArrayNonUniformIndexing = true;
999 f->shaderStorageBufferArrayNonUniformIndexing = true;
1000 f->shaderStorageImageArrayNonUniformIndexing = true;
1001 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1002 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1003 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1004 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1005 f->descriptorBindingSampledImageUpdateAfterBind = true;
1006 f->descriptorBindingStorageImageUpdateAfterBind = true;
1007 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1008 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1009 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1010 f->descriptorBindingUpdateUnusedWhilePending = true;
1011 f->descriptorBindingPartiallyBound = true;
1012 f->descriptorBindingVariableDescriptorCount = true;
1013 f->runtimeDescriptorArray = true;
1014
1015 f->samplerFilterMinmax = true;
1016 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1017 f->imagelessFramebuffer = true;
1018 f->uniformBufferStandardLayout = true;
1019 f->shaderSubgroupExtendedTypes = true;
1020 f->separateDepthStencilLayouts = true;
1021 f->hostQueryReset = true;
1022 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1023 f->bufferDeviceAddress = true;
1024 f->bufferDeviceAddressCaptureReplay = false;
1025 f->bufferDeviceAddressMultiDevice = false;
1026 f->vulkanMemoryModel = false;
1027 f->vulkanMemoryModelDeviceScope = false;
1028 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1029 f->shaderOutputViewportIndex = true;
1030 f->shaderOutputLayer = true;
1031 f->subgroupBroadcastDynamicId = true;
1032 }
1033
1034 void radv_GetPhysicalDeviceFeatures2(
1035 VkPhysicalDevice physicalDevice,
1036 VkPhysicalDeviceFeatures2 *pFeatures)
1037 {
1038 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1039 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1040
1041 VkPhysicalDeviceVulkan11Features core_1_1 = {
1042 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1043 };
1044 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1045
1046 VkPhysicalDeviceVulkan12Features core_1_2 = {
1047 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1048 };
1049 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1050
1051 #define CORE_FEATURE(major, minor, feature) \
1052 features->feature = core_##major##_##minor.feature
1053
1054 vk_foreach_struct(ext, pFeatures->pNext) {
1055 switch (ext->sType) {
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1057 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1058 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1059 CORE_FEATURE(1, 1, variablePointers);
1060 break;
1061 }
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1063 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1064 CORE_FEATURE(1, 1, multiview);
1065 CORE_FEATURE(1, 1, multiviewGeometryShader);
1066 CORE_FEATURE(1, 1, multiviewTessellationShader);
1067 break;
1068 }
1069 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1070 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1071 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1072 CORE_FEATURE(1, 1, shaderDrawParameters);
1073 break;
1074 }
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1076 VkPhysicalDeviceProtectedMemoryFeatures *features =
1077 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1078 CORE_FEATURE(1, 1, protectedMemory);
1079 break;
1080 }
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1082 VkPhysicalDevice16BitStorageFeatures *features =
1083 (VkPhysicalDevice16BitStorageFeatures*)ext;
1084 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1085 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1086 CORE_FEATURE(1, 1, storagePushConstant16);
1087 CORE_FEATURE(1, 1, storageInputOutput16);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1091 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1092 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1093 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1094 break;
1095 }
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1097 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1098 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1099 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1100 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1101 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1102 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1103 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1104 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1105 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1106 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1107 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1108 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1109 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1110 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1111 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1112 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1113 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1114 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1115 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1116 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1117 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1118 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1119 break;
1120 }
1121 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1122 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1123 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1124 features->conditionalRendering = true;
1125 features->inheritedConditionalRendering = false;
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1129 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1130 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1131 features->vertexAttributeInstanceRateDivisor = true;
1132 features->vertexAttributeInstanceRateZeroDivisor = true;
1133 break;
1134 }
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1136 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1137 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1138 features->transformFeedback = true;
1139 features->geometryStreams = !pdevice->use_ngg_streamout;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1143 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1144 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1145 CORE_FEATURE(1, 2, scalarBlockLayout);
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1149 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1150 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1151 features->memoryPriority = true;
1152 break;
1153 }
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1155 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1156 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1157 features->bufferDeviceAddress = true;
1158 features->bufferDeviceAddressCaptureReplay = false;
1159 features->bufferDeviceAddressMultiDevice = false;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1163 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1164 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1165 CORE_FEATURE(1, 2, bufferDeviceAddress);
1166 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1167 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1171 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1172 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1173 features->depthClipEnable = true;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1177 VkPhysicalDeviceHostQueryResetFeatures *features =
1178 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1179 CORE_FEATURE(1, 2, hostQueryReset);
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1183 VkPhysicalDevice8BitStorageFeatures *features =
1184 (VkPhysicalDevice8BitStorageFeatures *)ext;
1185 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1186 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1187 CORE_FEATURE(1, 2, storagePushConstant8);
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1191 VkPhysicalDeviceShaderFloat16Int8Features *features =
1192 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1193 CORE_FEATURE(1, 2, shaderFloat16);
1194 CORE_FEATURE(1, 2, shaderInt8);
1195 break;
1196 }
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1198 VkPhysicalDeviceShaderAtomicInt64Features *features =
1199 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1200 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1201 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1205 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1206 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1207 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1211 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1212 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1213
1214 features->inlineUniformBlock = true;
1215 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1219 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1220 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1221 features->computeDerivativeGroupQuads = false;
1222 features->computeDerivativeGroupLinear = true;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1226 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1227 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1228 features->ycbcrImageArrays = true;
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1232 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1233 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1234 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1235 break;
1236 }
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1238 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1239 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1240 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1241 break;
1242 }
1243 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1244 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1245 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1246 CORE_FEATURE(1, 2, imagelessFramebuffer);
1247 break;
1248 }
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1250 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1251 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1252 features->pipelineExecutableInfo = true;
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1256 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1257 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1258 features->shaderSubgroupClock = true;
1259 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1260 break;
1261 }
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1263 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1264 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1265 features->texelBufferAlignment = true;
1266 break;
1267 }
1268 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1269 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1270 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1271 CORE_FEATURE(1, 2, timelineSemaphore);
1272 break;
1273 }
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1275 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1276 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1277 features->subgroupSizeControl = true;
1278 features->computeFullSubgroups = true;
1279 break;
1280 }
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1282 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1283 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1284 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1288 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1289 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1290 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1291 break;
1292 }
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1294 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1295 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1296 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1300 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1301 break;
1302 }
1303 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1304 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1308 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1309 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1310 features->rectangularLines = false;
1311 features->bresenhamLines = true;
1312 features->smoothLines = false;
1313 features->stippledRectangularLines = false;
1314 features->stippledBresenhamLines = true;
1315 features->stippledSmoothLines = false;
1316 break;
1317 }
1318 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1319 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1320 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1321 features->overallocationBehavior = true;
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1325 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1326 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1327 features->robustBufferAccess2 = true;
1328 features->robustImageAccess2 = true;
1329 features->nullDescriptor = true;
1330 break;
1331 }
1332 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1333 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1334 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1335 features->customBorderColors = true;
1336 features->customBorderColorWithoutFormat = true;
1337 break;
1338 }
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1340 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1341 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1342 features->privateData = true;
1343 break;
1344 }
1345 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1346 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1347 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1348 features-> pipelineCreationCacheControl = true;
1349 break;
1350 }
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1352 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1353 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1354 features->extendedDynamicState = true;
1355 break;
1356 }
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1358 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1359 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1360 features->robustImageAccess = true;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1364 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1365 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1366 features->shaderBufferFloat32Atomics = true;
1367 features->shaderBufferFloat32AtomicAdd = false;
1368 features->shaderBufferFloat64Atomics = true;
1369 features->shaderBufferFloat64AtomicAdd = false;
1370 features->shaderSharedFloat32Atomics = true;
1371 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1372 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1373 features->shaderSharedFloat64Atomics = true;
1374 features->shaderSharedFloat64AtomicAdd = false;
1375 features->shaderImageFloat32Atomics = true;
1376 features->shaderImageFloat32AtomicAdd = false;
1377 features->sparseImageFloat32Atomics = false;
1378 features->sparseImageFloat32AtomicAdd = false;
1379 break;
1380 }
1381 default:
1382 break;
1383 }
1384 }
1385 #undef CORE_FEATURE
1386 }
1387
1388 static size_t
1389 radv_max_descriptor_set_size()
1390 {
1391 /* make sure that the entire descriptor set is addressable with a signed
1392 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1393 * be at most 2 GiB. the combined image & samples object count as one of
1394 * both. This limit is for the pipeline layout, not for the set layout, but
1395 * there is no set limit, so we just set a pipeline limit. I don't think
1396 * any app is going to hit this soon. */
1397 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1398 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1399 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1400 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1401 32 /* sampler, largest when combined with image */ +
1402 64 /* sampled image */ +
1403 64 /* storage image */);
1404 }
1405
1406 void radv_GetPhysicalDeviceProperties(
1407 VkPhysicalDevice physicalDevice,
1408 VkPhysicalDeviceProperties* pProperties)
1409 {
1410 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1411 VkSampleCountFlags sample_counts = 0xf;
1412
1413 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1414
1415 VkPhysicalDeviceLimits limits = {
1416 .maxImageDimension1D = (1 << 14),
1417 .maxImageDimension2D = (1 << 14),
1418 .maxImageDimension3D = (1 << 11),
1419 .maxImageDimensionCube = (1 << 14),
1420 .maxImageArrayLayers = (1 << 11),
1421 .maxTexelBufferElements = UINT32_MAX,
1422 .maxUniformBufferRange = UINT32_MAX,
1423 .maxStorageBufferRange = UINT32_MAX,
1424 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1425 .maxMemoryAllocationCount = UINT32_MAX,
1426 .maxSamplerAllocationCount = 64 * 1024,
1427 .bufferImageGranularity = 64, /* A cache line */
1428 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1429 .maxBoundDescriptorSets = MAX_SETS,
1430 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1431 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1432 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1433 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1434 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1435 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1436 .maxPerStageResources = max_descriptor_set_size,
1437 .maxDescriptorSetSamplers = max_descriptor_set_size,
1438 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1439 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1440 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1441 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1442 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1443 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1444 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1445 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1446 .maxVertexInputBindings = MAX_VBS,
1447 .maxVertexInputAttributeOffset = 2047,
1448 .maxVertexInputBindingStride = 2048,
1449 .maxVertexOutputComponents = 128,
1450 .maxTessellationGenerationLevel = 64,
1451 .maxTessellationPatchSize = 32,
1452 .maxTessellationControlPerVertexInputComponents = 128,
1453 .maxTessellationControlPerVertexOutputComponents = 128,
1454 .maxTessellationControlPerPatchOutputComponents = 120,
1455 .maxTessellationControlTotalOutputComponents = 4096,
1456 .maxTessellationEvaluationInputComponents = 128,
1457 .maxTessellationEvaluationOutputComponents = 128,
1458 .maxGeometryShaderInvocations = 127,
1459 .maxGeometryInputComponents = 64,
1460 .maxGeometryOutputComponents = 128,
1461 .maxGeometryOutputVertices = 256,
1462 .maxGeometryTotalOutputComponents = 1024,
1463 .maxFragmentInputComponents = 128,
1464 .maxFragmentOutputAttachments = 8,
1465 .maxFragmentDualSrcAttachments = 1,
1466 .maxFragmentCombinedOutputResources = 8,
1467 .maxComputeSharedMemorySize = 32768,
1468 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1469 .maxComputeWorkGroupInvocations = 1024,
1470 .maxComputeWorkGroupSize = {
1471 1024,
1472 1024,
1473 1024
1474 },
1475 .subPixelPrecisionBits = 8,
1476 .subTexelPrecisionBits = 8,
1477 .mipmapPrecisionBits = 8,
1478 .maxDrawIndexedIndexValue = UINT32_MAX,
1479 .maxDrawIndirectCount = UINT32_MAX,
1480 .maxSamplerLodBias = 16,
1481 .maxSamplerAnisotropy = 16,
1482 .maxViewports = MAX_VIEWPORTS,
1483 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1484 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1485 .viewportSubPixelBits = 8,
1486 .minMemoryMapAlignment = 4096, /* A page */
1487 .minTexelBufferOffsetAlignment = 4,
1488 .minUniformBufferOffsetAlignment = 4,
1489 .minStorageBufferOffsetAlignment = 4,
1490 .minTexelOffset = -32,
1491 .maxTexelOffset = 31,
1492 .minTexelGatherOffset = -32,
1493 .maxTexelGatherOffset = 31,
1494 .minInterpolationOffset = -2,
1495 .maxInterpolationOffset = 2,
1496 .subPixelInterpolationOffsetBits = 8,
1497 .maxFramebufferWidth = (1 << 14),
1498 .maxFramebufferHeight = (1 << 14),
1499 .maxFramebufferLayers = (1 << 10),
1500 .framebufferColorSampleCounts = sample_counts,
1501 .framebufferDepthSampleCounts = sample_counts,
1502 .framebufferStencilSampleCounts = sample_counts,
1503 .framebufferNoAttachmentsSampleCounts = sample_counts,
1504 .maxColorAttachments = MAX_RTS,
1505 .sampledImageColorSampleCounts = sample_counts,
1506 .sampledImageIntegerSampleCounts = sample_counts,
1507 .sampledImageDepthSampleCounts = sample_counts,
1508 .sampledImageStencilSampleCounts = sample_counts,
1509 .storageImageSampleCounts = sample_counts,
1510 .maxSampleMaskWords = 1,
1511 .timestampComputeAndGraphics = true,
1512 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1513 .maxClipDistances = 8,
1514 .maxCullDistances = 8,
1515 .maxCombinedClipAndCullDistances = 8,
1516 .discreteQueuePriorities = 2,
1517 .pointSizeRange = { 0.0, 8191.875 },
1518 .lineWidthRange = { 0.0, 8191.875 },
1519 .pointSizeGranularity = (1.0 / 8.0),
1520 .lineWidthGranularity = (1.0 / 8.0),
1521 .strictLines = false, /* FINISHME */
1522 .standardSampleLocations = true,
1523 .optimalBufferCopyOffsetAlignment = 128,
1524 .optimalBufferCopyRowPitchAlignment = 128,
1525 .nonCoherentAtomSize = 64,
1526 };
1527
1528 *pProperties = (VkPhysicalDeviceProperties) {
1529 .apiVersion = radv_physical_device_api_version(pdevice),
1530 .driverVersion = vk_get_driver_version(),
1531 .vendorID = ATI_VENDOR_ID,
1532 .deviceID = pdevice->rad_info.pci_id,
1533 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1534 .limits = limits,
1535 .sparseProperties = {0},
1536 };
1537
1538 strcpy(pProperties->deviceName, pdevice->name);
1539 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1540 }
1541
1542 static void
1543 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1544 VkPhysicalDeviceVulkan11Properties *p)
1545 {
1546 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1547
1548 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1549 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1550 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1551 /* The LUID is for Windows. */
1552 p->deviceLUIDValid = false;
1553 p->deviceNodeMask = 0;
1554
1555 p->subgroupSize = RADV_SUBGROUP_SIZE;
1556 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1557 VK_SHADER_STAGE_COMPUTE_BIT;
1558 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1559 VK_SUBGROUP_FEATURE_VOTE_BIT |
1560 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1561 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1562 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1563 VK_SUBGROUP_FEATURE_QUAD_BIT |
1564 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1565 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1566 p->subgroupQuadOperationsInAllStages = true;
1567
1568 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1569 p->maxMultiviewViewCount = MAX_VIEWS;
1570 p->maxMultiviewInstanceIndex = INT_MAX;
1571 p->protectedNoFault = false;
1572 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1573 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1574 }
1575
1576 static void
1577 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1578 VkPhysicalDeviceVulkan12Properties *p)
1579 {
1580 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1581
1582 p->driverID = VK_DRIVER_ID_MESA_RADV;
1583 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1584 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1585 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1586 radv_get_compiler_string(pdevice));
1587 p->conformanceVersion = (VkConformanceVersion) {
1588 .major = 1,
1589 .minor = 2,
1590 .subminor = 0,
1591 .patch = 0,
1592 };
1593
1594 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1595 * controlled by the same config register.
1596 */
1597 if (pdevice->rad_info.has_packed_math_16bit) {
1598 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1599 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1600 } else {
1601 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1602 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1603 }
1604
1605 /* With LLVM, do not allow both preserving and flushing denorms because
1606 * different shaders in the same pipeline can have different settings and
1607 * this won't work for merged shaders. To make it work, this requires LLVM
1608 * support for changing the register. The same logic applies for the
1609 * rounding modes because they are configured with the same config
1610 * register.
1611 */
1612 p->shaderDenormFlushToZeroFloat32 = true;
1613 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1614 p->shaderRoundingModeRTEFloat32 = true;
1615 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1616 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1617
1618 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1619 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1620 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1621 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1622 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1623
1624 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1625 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1626 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1627 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1628 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1629
1630 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1631 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1632 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1633 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1634 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1635 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1636 p->robustBufferAccessUpdateAfterBind = false;
1637 p->quadDivergentImplicitLod = false;
1638
1639 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1640 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1641 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1642 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1643 32 /* sampler, largest when combined with image */ +
1644 64 /* sampled image */ +
1645 64 /* storage image */);
1646 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1647 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1648 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1649 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1650 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1651 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1652 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1653 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1654 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1655 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1656 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1657 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1658 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1659 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1660 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1661
1662 /* We support all of the depth resolve modes */
1663 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1664 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1665 VK_RESOLVE_MODE_MIN_BIT_KHR |
1666 VK_RESOLVE_MODE_MAX_BIT_KHR;
1667
1668 /* Average doesn't make sense for stencil so we don't support that */
1669 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1670 VK_RESOLVE_MODE_MIN_BIT_KHR |
1671 VK_RESOLVE_MODE_MAX_BIT_KHR;
1672
1673 p->independentResolveNone = true;
1674 p->independentResolve = true;
1675
1676 /* GFX6-8 only support single channel min/max filter. */
1677 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1678 p->filterMinmaxSingleComponentFormats = true;
1679
1680 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1681
1682 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1683 }
1684
1685 void radv_GetPhysicalDeviceProperties2(
1686 VkPhysicalDevice physicalDevice,
1687 VkPhysicalDeviceProperties2 *pProperties)
1688 {
1689 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1690 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1691
1692 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1693 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1694 };
1695 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1696
1697 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1698 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1699 };
1700 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1701
1702 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1703 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1704 sizeof(core_##major##_##minor.core_property))
1705
1706 #define CORE_PROPERTY(major, minor, property) \
1707 CORE_RENAMED_PROPERTY(major, minor, property, property)
1708
1709 vk_foreach_struct(ext, pProperties->pNext) {
1710 switch (ext->sType) {
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1712 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1713 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1714 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1715 break;
1716 }
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1718 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1719 CORE_PROPERTY(1, 1, deviceUUID);
1720 CORE_PROPERTY(1, 1, driverUUID);
1721 CORE_PROPERTY(1, 1, deviceLUID);
1722 CORE_PROPERTY(1, 1, deviceLUIDValid);
1723 break;
1724 }
1725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1726 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1727 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1728 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1729 break;
1730 }
1731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1732 VkPhysicalDevicePointClippingProperties *properties =
1733 (VkPhysicalDevicePointClippingProperties*)ext;
1734 CORE_PROPERTY(1, 1, pointClippingBehavior);
1735 break;
1736 }
1737 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1738 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1739 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1740 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1741 break;
1742 }
1743 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1744 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1745 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1746 properties->minImportedHostPointerAlignment = 4096;
1747 break;
1748 }
1749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1750 VkPhysicalDeviceSubgroupProperties *properties =
1751 (VkPhysicalDeviceSubgroupProperties*)ext;
1752 CORE_PROPERTY(1, 1, subgroupSize);
1753 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1754 subgroupSupportedStages);
1755 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1756 subgroupSupportedOperations);
1757 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1758 subgroupQuadOperationsInAllStages);
1759 break;
1760 }
1761 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1762 VkPhysicalDeviceMaintenance3Properties *properties =
1763 (VkPhysicalDeviceMaintenance3Properties*)ext;
1764 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1765 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1766 break;
1767 }
1768 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1769 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1770 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1771 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1772 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1776 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1777 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1778
1779 /* Shader engines. */
1780 properties->shaderEngineCount =
1781 pdevice->rad_info.max_se;
1782 properties->shaderArraysPerEngineCount =
1783 pdevice->rad_info.max_sh_per_se;
1784 properties->computeUnitsPerShaderArray =
1785 pdevice->rad_info.min_good_cu_per_sa;
1786 properties->simdPerComputeUnit =
1787 pdevice->rad_info.num_simd_per_compute_unit;
1788 properties->wavefrontsPerSimd =
1789 pdevice->rad_info.max_wave64_per_simd;
1790 properties->wavefrontSize = 64;
1791
1792 /* SGPR. */
1793 properties->sgprsPerSimd =
1794 pdevice->rad_info.num_physical_sgprs_per_simd;
1795 properties->minSgprAllocation =
1796 pdevice->rad_info.min_sgpr_alloc;
1797 properties->maxSgprAllocation =
1798 pdevice->rad_info.max_sgpr_alloc;
1799 properties->sgprAllocationGranularity =
1800 pdevice->rad_info.sgpr_alloc_granularity;
1801
1802 /* VGPR. */
1803 properties->vgprsPerSimd =
1804 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1805 properties->minVgprAllocation =
1806 pdevice->rad_info.min_wave64_vgpr_alloc;
1807 properties->maxVgprAllocation =
1808 pdevice->rad_info.max_vgpr_alloc;
1809 properties->vgprAllocationGranularity =
1810 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1811 break;
1812 }
1813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1814 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1815 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1816
1817 properties->shaderCoreFeatures = 0;
1818 properties->activeComputeUnitCount =
1819 pdevice->rad_info.num_good_compute_units;
1820 break;
1821 }
1822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1823 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1824 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1825 properties->maxVertexAttribDivisor = UINT32_MAX;
1826 break;
1827 }
1828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1829 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1830 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1831 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1832 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1833 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1834 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1835 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1836 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1837 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1838 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1839 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1840 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1841 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1842 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1843 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1844 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1845 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1846 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1847 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1848 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1849 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1850 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1851 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1852 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1853 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1854 break;
1855 }
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1857 VkPhysicalDeviceProtectedMemoryProperties *properties =
1858 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1859 CORE_PROPERTY(1, 1, protectedNoFault);
1860 break;
1861 }
1862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1863 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1864 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1865 properties->primitiveOverestimationSize = 0;
1866 properties->maxExtraPrimitiveOverestimationSize = 0;
1867 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1868 properties->primitiveUnderestimation = false;
1869 properties->conservativePointAndLineRasterization = false;
1870 properties->degenerateTrianglesRasterized = false;
1871 properties->degenerateLinesRasterized = false;
1872 properties->fullyCoveredFragmentShaderInputVariable = false;
1873 properties->conservativeRasterizationPostDepthCoverage = false;
1874 break;
1875 }
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1877 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1878 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1879 properties->pciDomain = pdevice->bus_info.domain;
1880 properties->pciBus = pdevice->bus_info.bus;
1881 properties->pciDevice = pdevice->bus_info.dev;
1882 properties->pciFunction = pdevice->bus_info.func;
1883 break;
1884 }
1885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1886 VkPhysicalDeviceDriverProperties *properties =
1887 (VkPhysicalDeviceDriverProperties *) ext;
1888 CORE_PROPERTY(1, 2, driverID);
1889 CORE_PROPERTY(1, 2, driverName);
1890 CORE_PROPERTY(1, 2, driverInfo);
1891 CORE_PROPERTY(1, 2, conformanceVersion);
1892 break;
1893 }
1894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1895 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1896 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1897 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1898 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1899 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1900 properties->maxTransformFeedbackStreamDataSize = 512;
1901 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1902 properties->maxTransformFeedbackBufferDataStride = 512;
1903 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1904 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1905 properties->transformFeedbackRasterizationStreamSelect = false;
1906 properties->transformFeedbackDraw = true;
1907 break;
1908 }
1909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1910 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1911 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1912
1913 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1914 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1915 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1916 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1917 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1921 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1922 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1923 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1924 VK_SAMPLE_COUNT_4_BIT |
1925 VK_SAMPLE_COUNT_8_BIT;
1926 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1927 properties->sampleLocationCoordinateRange[0] = 0.0f;
1928 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1929 properties->sampleLocationSubPixelBits = 4;
1930 properties->variableSampleLocations = false;
1931 break;
1932 }
1933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1934 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1935 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1936 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1937 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1938 CORE_PROPERTY(1, 2, independentResolveNone);
1939 CORE_PROPERTY(1, 2, independentResolve);
1940 break;
1941 }
1942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1943 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1944 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1945 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1946 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1947 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1948 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1949 break;
1950 }
1951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1952 VkPhysicalDeviceFloatControlsProperties *properties =
1953 (VkPhysicalDeviceFloatControlsProperties *)ext;
1954 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1955 CORE_PROPERTY(1, 2, roundingModeIndependence);
1956 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1957 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1958 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1959 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1960 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1961 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1962 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1963 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1964 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1965 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1966 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1967 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1968 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1969 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1970 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1971 break;
1972 }
1973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1974 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1975 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1976 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1977 break;
1978 }
1979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1980 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1981 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1982 props->minSubgroupSize = 64;
1983 props->maxSubgroupSize = 64;
1984 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1985 props->requiredSubgroupSizeStages = 0;
1986
1987 if (pdevice->rad_info.chip_class >= GFX10) {
1988 /* Only GFX10+ supports wave32. */
1989 props->minSubgroupSize = 32;
1990 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1991 }
1992 break;
1993 }
1994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1995 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1996 break;
1997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1998 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1999 break;
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2001 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2002 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2003 props->lineSubPixelPrecisionBits = 4;
2004 break;
2005 }
2006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2007 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2008 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2009 properties->robustStorageBufferAccessSizeAlignment = 4;
2010 properties->robustUniformBufferAccessSizeAlignment = 4;
2011 break;
2012 }
2013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2014 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2015 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2016 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2017 break;
2018 }
2019 default:
2020 break;
2021 }
2022 }
2023 }
2024
2025 static void radv_get_physical_device_queue_family_properties(
2026 struct radv_physical_device* pdevice,
2027 uint32_t* pCount,
2028 VkQueueFamilyProperties** pQueueFamilyProperties)
2029 {
2030 int num_queue_families = 1;
2031 int idx;
2032 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2033 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2034 num_queue_families++;
2035
2036 if (pQueueFamilyProperties == NULL) {
2037 *pCount = num_queue_families;
2038 return;
2039 }
2040
2041 if (!*pCount)
2042 return;
2043
2044 idx = 0;
2045 if (*pCount >= 1) {
2046 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2047 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2048 VK_QUEUE_COMPUTE_BIT |
2049 VK_QUEUE_TRANSFER_BIT |
2050 VK_QUEUE_SPARSE_BINDING_BIT,
2051 .queueCount = 1,
2052 .timestampValidBits = 64,
2053 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2054 };
2055 idx++;
2056 }
2057
2058 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2059 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2060 if (*pCount > idx) {
2061 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2062 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2063 VK_QUEUE_TRANSFER_BIT |
2064 VK_QUEUE_SPARSE_BINDING_BIT,
2065 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2066 .timestampValidBits = 64,
2067 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2068 };
2069 idx++;
2070 }
2071 }
2072 *pCount = idx;
2073 }
2074
2075 void radv_GetPhysicalDeviceQueueFamilyProperties(
2076 VkPhysicalDevice physicalDevice,
2077 uint32_t* pCount,
2078 VkQueueFamilyProperties* pQueueFamilyProperties)
2079 {
2080 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2081 if (!pQueueFamilyProperties) {
2082 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2083 return;
2084 }
2085 VkQueueFamilyProperties *properties[] = {
2086 pQueueFamilyProperties + 0,
2087 pQueueFamilyProperties + 1,
2088 pQueueFamilyProperties + 2,
2089 };
2090 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2091 assert(*pCount <= 3);
2092 }
2093
2094 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2095 VkPhysicalDevice physicalDevice,
2096 uint32_t* pCount,
2097 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2098 {
2099 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2100 if (!pQueueFamilyProperties) {
2101 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2102 return;
2103 }
2104 VkQueueFamilyProperties *properties[] = {
2105 &pQueueFamilyProperties[0].queueFamilyProperties,
2106 &pQueueFamilyProperties[1].queueFamilyProperties,
2107 &pQueueFamilyProperties[2].queueFamilyProperties,
2108 };
2109 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2110 assert(*pCount <= 3);
2111 }
2112
2113 void radv_GetPhysicalDeviceMemoryProperties(
2114 VkPhysicalDevice physicalDevice,
2115 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2116 {
2117 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2118
2119 *pMemoryProperties = physical_device->memory_properties;
2120 }
2121
2122 static void
2123 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2124 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2125 {
2126 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2127 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2128 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2129 uint64_t vram_size = radv_get_vram_size(device);
2130 uint64_t gtt_size = device->rad_info.gart_size;
2131 uint64_t heap_budget, heap_usage;
2132
2133 /* For all memory heaps, the computation of budget is as follow:
2134 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2135 *
2136 * The Vulkan spec 1.1.97 says that the budget should include any
2137 * currently allocated device memory.
2138 *
2139 * Note that the application heap usages are not really accurate (eg.
2140 * in presence of shared buffers).
2141 */
2142 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2143 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2144
2145 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2146 heap_usage = device->ws->query_value(device->ws,
2147 RADEON_ALLOCATED_VRAM);
2148
2149 heap_budget = vram_size -
2150 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2151 heap_usage;
2152
2153 memoryBudget->heapBudget[heap_index] = heap_budget;
2154 memoryBudget->heapUsage[heap_index] = heap_usage;
2155 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2156 heap_usage = device->ws->query_value(device->ws,
2157 RADEON_ALLOCATED_VRAM_VIS);
2158
2159 heap_budget = visible_vram_size -
2160 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2161 heap_usage;
2162
2163 memoryBudget->heapBudget[heap_index] = heap_budget;
2164 memoryBudget->heapUsage[heap_index] = heap_usage;
2165 } else {
2166 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2167
2168 heap_usage = device->ws->query_value(device->ws,
2169 RADEON_ALLOCATED_GTT);
2170
2171 heap_budget = gtt_size -
2172 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2173 heap_usage;
2174
2175 memoryBudget->heapBudget[heap_index] = heap_budget;
2176 memoryBudget->heapUsage[heap_index] = heap_usage;
2177 }
2178 }
2179
2180 /* The heapBudget and heapUsage values must be zero for array elements
2181 * greater than or equal to
2182 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2183 */
2184 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2185 memoryBudget->heapBudget[i] = 0;
2186 memoryBudget->heapUsage[i] = 0;
2187 }
2188 }
2189
2190 void radv_GetPhysicalDeviceMemoryProperties2(
2191 VkPhysicalDevice physicalDevice,
2192 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2193 {
2194 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2195 &pMemoryProperties->memoryProperties);
2196
2197 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2198 vk_find_struct(pMemoryProperties->pNext,
2199 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2200 if (memory_budget)
2201 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2202 }
2203
2204 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2205 VkDevice _device,
2206 VkExternalMemoryHandleTypeFlagBits handleType,
2207 const void *pHostPointer,
2208 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2209 {
2210 RADV_FROM_HANDLE(radv_device, device, _device);
2211
2212 switch (handleType)
2213 {
2214 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2215 const struct radv_physical_device *physical_device = device->physical_device;
2216 uint32_t memoryTypeBits = 0;
2217 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2218 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2219 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2220 memoryTypeBits = (1 << i);
2221 break;
2222 }
2223 }
2224 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2225 return VK_SUCCESS;
2226 }
2227 default:
2228 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2229 }
2230 }
2231
2232 static enum radeon_ctx_priority
2233 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2234 {
2235 /* Default to MEDIUM when a specific global priority isn't requested */
2236 if (!pObj)
2237 return RADEON_CTX_PRIORITY_MEDIUM;
2238
2239 switch(pObj->globalPriority) {
2240 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2241 return RADEON_CTX_PRIORITY_REALTIME;
2242 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2243 return RADEON_CTX_PRIORITY_HIGH;
2244 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2245 return RADEON_CTX_PRIORITY_MEDIUM;
2246 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2247 return RADEON_CTX_PRIORITY_LOW;
2248 default:
2249 unreachable("Illegal global priority value");
2250 return RADEON_CTX_PRIORITY_INVALID;
2251 }
2252 }
2253
2254 static int
2255 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2256 uint32_t queue_family_index, int idx,
2257 VkDeviceQueueCreateFlags flags,
2258 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2259 {
2260 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2261 queue->device = device;
2262 queue->queue_family_index = queue_family_index;
2263 queue->queue_idx = idx;
2264 queue->priority = radv_get_queue_global_priority(global_priority);
2265 queue->flags = flags;
2266 queue->hw_ctx = NULL;
2267
2268 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2269 if (result != VK_SUCCESS)
2270 return vk_error(device->instance, result);
2271
2272 list_inithead(&queue->pending_submissions);
2273 pthread_mutex_init(&queue->pending_mutex, NULL);
2274
2275 pthread_mutex_init(&queue->thread_mutex, NULL);
2276 queue->thread_submission = NULL;
2277 queue->thread_running = queue->thread_exit = false;
2278 result = radv_create_pthread_cond(&queue->thread_cond);
2279 if (result != VK_SUCCESS)
2280 return vk_error(device->instance, result);
2281
2282 return VK_SUCCESS;
2283 }
2284
2285 static void
2286 radv_queue_finish(struct radv_queue *queue)
2287 {
2288 if (queue->thread_running) {
2289 p_atomic_set(&queue->thread_exit, true);
2290 pthread_cond_broadcast(&queue->thread_cond);
2291 pthread_join(queue->submission_thread, NULL);
2292 }
2293 pthread_cond_destroy(&queue->thread_cond);
2294 pthread_mutex_destroy(&queue->pending_mutex);
2295 pthread_mutex_destroy(&queue->thread_mutex);
2296
2297 if (queue->hw_ctx)
2298 queue->device->ws->ctx_destroy(queue->hw_ctx);
2299
2300 if (queue->initial_full_flush_preamble_cs)
2301 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2302 if (queue->initial_preamble_cs)
2303 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2304 if (queue->continue_preamble_cs)
2305 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2306 if (queue->descriptor_bo)
2307 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2308 if (queue->scratch_bo)
2309 queue->device->ws->buffer_destroy(queue->scratch_bo);
2310 if (queue->esgs_ring_bo)
2311 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2312 if (queue->gsvs_ring_bo)
2313 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2314 if (queue->tess_rings_bo)
2315 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2316 if (queue->gds_bo)
2317 queue->device->ws->buffer_destroy(queue->gds_bo);
2318 if (queue->gds_oa_bo)
2319 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2320 if (queue->compute_scratch_bo)
2321 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2322 }
2323
2324 static void
2325 radv_bo_list_init(struct radv_bo_list *bo_list)
2326 {
2327 pthread_mutex_init(&bo_list->mutex, NULL);
2328 bo_list->list.count = bo_list->capacity = 0;
2329 bo_list->list.bos = NULL;
2330 }
2331
2332 static void
2333 radv_bo_list_finish(struct radv_bo_list *bo_list)
2334 {
2335 free(bo_list->list.bos);
2336 pthread_mutex_destroy(&bo_list->mutex);
2337 }
2338
2339 VkResult radv_bo_list_add(struct radv_device *device,
2340 struct radeon_winsys_bo *bo)
2341 {
2342 struct radv_bo_list *bo_list = &device->bo_list;
2343
2344 if (bo->is_local)
2345 return VK_SUCCESS;
2346
2347 if (unlikely(!device->use_global_bo_list))
2348 return VK_SUCCESS;
2349
2350 pthread_mutex_lock(&bo_list->mutex);
2351 if (bo_list->list.count == bo_list->capacity) {
2352 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2353 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2354
2355 if (!data) {
2356 pthread_mutex_unlock(&bo_list->mutex);
2357 return VK_ERROR_OUT_OF_HOST_MEMORY;
2358 }
2359
2360 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2361 bo_list->capacity = capacity;
2362 }
2363
2364 bo_list->list.bos[bo_list->list.count++] = bo;
2365 pthread_mutex_unlock(&bo_list->mutex);
2366 return VK_SUCCESS;
2367 }
2368
2369 void radv_bo_list_remove(struct radv_device *device,
2370 struct radeon_winsys_bo *bo)
2371 {
2372 struct radv_bo_list *bo_list = &device->bo_list;
2373
2374 if (bo->is_local)
2375 return;
2376
2377 if (unlikely(!device->use_global_bo_list))
2378 return;
2379
2380 pthread_mutex_lock(&bo_list->mutex);
2381 /* Loop the list backwards so we find the most recently added
2382 * memory first. */
2383 for(unsigned i = bo_list->list.count; i-- > 0;) {
2384 if (bo_list->list.bos[i] == bo) {
2385 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2386 --bo_list->list.count;
2387 break;
2388 }
2389 }
2390 pthread_mutex_unlock(&bo_list->mutex);
2391 }
2392
2393 static void
2394 radv_device_init_gs_info(struct radv_device *device)
2395 {
2396 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2397 device->physical_device->rad_info.family);
2398 }
2399
2400 static int radv_get_device_extension_index(const char *name)
2401 {
2402 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2403 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2404 return i;
2405 }
2406 return -1;
2407 }
2408
2409 static int
2410 radv_get_int_debug_option(const char *name, int default_value)
2411 {
2412 const char *str;
2413 int result;
2414
2415 str = getenv(name);
2416 if (!str) {
2417 result = default_value;
2418 } else {
2419 char *endptr;
2420
2421 result = strtol(str, &endptr, 0);
2422 if (str == endptr) {
2423 /* No digits founs. */
2424 result = default_value;
2425 }
2426 }
2427
2428 return result;
2429 }
2430
2431 static void
2432 radv_device_init_dispatch(struct radv_device *device)
2433 {
2434 const struct radv_instance *instance = device->physical_device->instance;
2435 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2436 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2437 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2438
2439 if (radv_thread_trace >= 0) {
2440 /* Use device entrypoints from the SQTT layer if enabled. */
2441 dispatch_table_layer = &sqtt_device_dispatch_table;
2442 }
2443
2444 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2445 /* Vulkan requires that entrypoints for extensions which have not been
2446 * enabled must not be advertised.
2447 */
2448 if (!unchecked &&
2449 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2450 &instance->enabled_extensions,
2451 &device->enabled_extensions)) {
2452 device->dispatch.entrypoints[i] = NULL;
2453 } else if (dispatch_table_layer &&
2454 dispatch_table_layer->entrypoints[i]) {
2455 device->dispatch.entrypoints[i] =
2456 dispatch_table_layer->entrypoints[i];
2457 } else {
2458 device->dispatch.entrypoints[i] =
2459 radv_device_dispatch_table.entrypoints[i];
2460 }
2461 }
2462 }
2463
2464 static VkResult
2465 radv_create_pthread_cond(pthread_cond_t *cond)
2466 {
2467 pthread_condattr_t condattr;
2468 if (pthread_condattr_init(&condattr)) {
2469 return VK_ERROR_INITIALIZATION_FAILED;
2470 }
2471
2472 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2473 pthread_condattr_destroy(&condattr);
2474 return VK_ERROR_INITIALIZATION_FAILED;
2475 }
2476 if (pthread_cond_init(cond, &condattr)) {
2477 pthread_condattr_destroy(&condattr);
2478 return VK_ERROR_INITIALIZATION_FAILED;
2479 }
2480 pthread_condattr_destroy(&condattr);
2481 return VK_SUCCESS;
2482 }
2483
2484 static VkResult
2485 check_physical_device_features(VkPhysicalDevice physicalDevice,
2486 const VkPhysicalDeviceFeatures *features)
2487 {
2488 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2489 VkPhysicalDeviceFeatures supported_features;
2490 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2491 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2492 VkBool32 *enabled_feature = (VkBool32 *)features;
2493 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2494 for (uint32_t i = 0; i < num_features; i++) {
2495 if (enabled_feature[i] && !supported_feature[i])
2496 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2497 }
2498
2499 return VK_SUCCESS;
2500 }
2501
2502 static VkResult radv_device_init_border_color(struct radv_device *device)
2503 {
2504 device->border_color_data.bo =
2505 device->ws->buffer_create(device->ws,
2506 RADV_BORDER_COLOR_BUFFER_SIZE,
2507 4096,
2508 RADEON_DOMAIN_VRAM,
2509 RADEON_FLAG_CPU_ACCESS |
2510 RADEON_FLAG_READ_ONLY |
2511 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2512 RADV_BO_PRIORITY_SHADER);
2513
2514 if (device->border_color_data.bo == NULL)
2515 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2516
2517 device->border_color_data.colors_gpu_ptr =
2518 device->ws->buffer_map(device->border_color_data.bo);
2519 if (!device->border_color_data.colors_gpu_ptr)
2520 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2521 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2522
2523 return VK_SUCCESS;
2524 }
2525
2526 static void radv_device_finish_border_color(struct radv_device *device)
2527 {
2528 if (device->border_color_data.bo) {
2529 device->ws->buffer_destroy(device->border_color_data.bo);
2530
2531 pthread_mutex_destroy(&device->border_color_data.mutex);
2532 }
2533 }
2534
2535 VkResult radv_CreateDevice(
2536 VkPhysicalDevice physicalDevice,
2537 const VkDeviceCreateInfo* pCreateInfo,
2538 const VkAllocationCallbacks* pAllocator,
2539 VkDevice* pDevice)
2540 {
2541 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2542 VkResult result;
2543 struct radv_device *device;
2544
2545 bool keep_shader_info = false;
2546 bool robust_buffer_access = false;
2547 bool overallocation_disallowed = false;
2548 bool custom_border_colors = false;
2549
2550 /* Check enabled features */
2551 if (pCreateInfo->pEnabledFeatures) {
2552 result = check_physical_device_features(physicalDevice,
2553 pCreateInfo->pEnabledFeatures);
2554 if (result != VK_SUCCESS)
2555 return result;
2556
2557 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2558 robust_buffer_access = true;
2559 }
2560
2561 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2562 switch (ext->sType) {
2563 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2564 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2565 result = check_physical_device_features(physicalDevice,
2566 &features->features);
2567 if (result != VK_SUCCESS)
2568 return result;
2569
2570 if (features->features.robustBufferAccess)
2571 robust_buffer_access = true;
2572 break;
2573 }
2574 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2575 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2576 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2577 overallocation_disallowed = true;
2578 break;
2579 }
2580 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2581 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2582 custom_border_colors = border_color_features->customBorderColors;
2583 break;
2584 }
2585 default:
2586 break;
2587 }
2588 }
2589
2590 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2591 sizeof(*device), 8,
2592 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2593 if (!device)
2594 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2595
2596 vk_device_init(&device->vk, pCreateInfo,
2597 &physical_device->instance->alloc, pAllocator);
2598
2599 device->instance = physical_device->instance;
2600 device->physical_device = physical_device;
2601
2602 device->ws = physical_device->ws;
2603
2604 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2605 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2606 int index = radv_get_device_extension_index(ext_name);
2607 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2608 vk_free(&device->vk.alloc, device);
2609 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2610 }
2611
2612 device->enabled_extensions.extensions[index] = true;
2613 }
2614
2615 radv_device_init_dispatch(device);
2616
2617 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2618
2619 /* With update after bind we can't attach bo's to the command buffer
2620 * from the descriptor set anymore, so we have to use a global BO list.
2621 */
2622 device->use_global_bo_list =
2623 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2624 device->enabled_extensions.EXT_descriptor_indexing ||
2625 device->enabled_extensions.EXT_buffer_device_address ||
2626 device->enabled_extensions.KHR_buffer_device_address;
2627
2628 device->robust_buffer_access = robust_buffer_access;
2629
2630 mtx_init(&device->shader_slab_mutex, mtx_plain);
2631 list_inithead(&device->shader_slabs);
2632
2633 device->overallocation_disallowed = overallocation_disallowed;
2634 mtx_init(&device->overallocation_mutex, mtx_plain);
2635
2636 radv_bo_list_init(&device->bo_list);
2637
2638 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2639 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2640 uint32_t qfi = queue_create->queueFamilyIndex;
2641 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2642 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2643
2644 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2645
2646 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2647 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2648 if (!device->queues[qfi]) {
2649 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2650 goto fail;
2651 }
2652
2653 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2654
2655 device->queue_count[qfi] = queue_create->queueCount;
2656
2657 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2658 result = radv_queue_init(device, &device->queues[qfi][q],
2659 qfi, q, queue_create->flags,
2660 global_priority);
2661 if (result != VK_SUCCESS)
2662 goto fail;
2663 }
2664 }
2665
2666 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2667 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2668
2669 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2670 device->dfsm_allowed = device->pbb_allowed &&
2671 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2672
2673 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2674
2675 /* The maximum number of scratch waves. Scratch space isn't divided
2676 * evenly between CUs. The number is only a function of the number of CUs.
2677 * We can decrease the constant to decrease the scratch buffer size.
2678 *
2679 * sctx->scratch_waves must be >= the maximum possible size of
2680 * 1 threadgroup, so that the hw doesn't hang from being unable
2681 * to start any.
2682 *
2683 * The recommended value is 4 per CU at most. Higher numbers don't
2684 * bring much benefit, but they still occupy chip resources (think
2685 * async compute). I've seen ~2% performance difference between 4 and 32.
2686 */
2687 uint32_t max_threads_per_block = 2048;
2688 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2689 max_threads_per_block / 64);
2690
2691 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2692
2693 if (device->physical_device->rad_info.chip_class >= GFX7) {
2694 /* If the KMD allows it (there is a KMD hw register for it),
2695 * allow launching waves out-of-order.
2696 */
2697 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2698 }
2699
2700 radv_device_init_gs_info(device);
2701
2702 device->tess_offchip_block_dw_size =
2703 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2704
2705 if (getenv("RADV_TRACE_FILE")) {
2706 const char *filename = getenv("RADV_TRACE_FILE");
2707
2708 keep_shader_info = true;
2709
2710 if (!radv_init_trace(device))
2711 goto fail;
2712
2713 fprintf(stderr, "*****************************************************************************\n");
2714 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2715 fprintf(stderr, "*****************************************************************************\n");
2716
2717 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2718 radv_dump_enabled_options(device, stderr);
2719 }
2720
2721 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2722 if (radv_thread_trace >= 0) {
2723 fprintf(stderr, "*************************************************\n");
2724 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2725 fprintf(stderr, "*************************************************\n");
2726
2727 if (device->physical_device->rad_info.chip_class < GFX8) {
2728 fprintf(stderr, "GPU hardware not supported: refer to "
2729 "the RGP documentation for the list of "
2730 "supported GPUs!\n");
2731 abort();
2732 }
2733
2734 /* Default buffer size set to 1MB per SE. */
2735 device->thread_trace_buffer_size =
2736 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2737 device->thread_trace_start_frame = radv_thread_trace;
2738
2739 if (!radv_thread_trace_init(device))
2740 goto fail;
2741 }
2742
2743 device->keep_shader_info = keep_shader_info;
2744 result = radv_device_init_meta(device);
2745 if (result != VK_SUCCESS)
2746 goto fail;
2747
2748 radv_device_init_msaa(device);
2749
2750 /* If the border color extension is enabled, let's create the buffer we need. */
2751 if (custom_border_colors) {
2752 result = radv_device_init_border_color(device);
2753 if (result != VK_SUCCESS)
2754 goto fail;
2755 }
2756
2757 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2758 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2759 if (!device->empty_cs[family])
2760 goto fail;
2761
2762 switch (family) {
2763 case RADV_QUEUE_GENERAL:
2764 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2765 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2766 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2767 break;
2768 case RADV_QUEUE_COMPUTE:
2769 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2770 radeon_emit(device->empty_cs[family], 0);
2771 break;
2772 }
2773
2774 result = device->ws->cs_finalize(device->empty_cs[family]);
2775 if (result != VK_SUCCESS)
2776 goto fail;
2777 }
2778
2779 if (device->physical_device->rad_info.chip_class >= GFX7)
2780 cik_create_gfx_config(device);
2781
2782 VkPipelineCacheCreateInfo ci;
2783 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2784 ci.pNext = NULL;
2785 ci.flags = 0;
2786 ci.pInitialData = NULL;
2787 ci.initialDataSize = 0;
2788 VkPipelineCache pc;
2789 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2790 &ci, NULL, &pc);
2791 if (result != VK_SUCCESS)
2792 goto fail_meta;
2793
2794 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2795
2796 result = radv_create_pthread_cond(&device->timeline_cond);
2797 if (result != VK_SUCCESS)
2798 goto fail_mem_cache;
2799
2800 device->force_aniso =
2801 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2802 if (device->force_aniso >= 0) {
2803 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2804 1 << util_logbase2(device->force_aniso));
2805 }
2806
2807 *pDevice = radv_device_to_handle(device);
2808 return VK_SUCCESS;
2809
2810 fail_mem_cache:
2811 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2812 fail_meta:
2813 radv_device_finish_meta(device);
2814 fail:
2815 radv_bo_list_finish(&device->bo_list);
2816
2817 radv_thread_trace_finish(device);
2818
2819 if (device->trace_bo)
2820 device->ws->buffer_destroy(device->trace_bo);
2821
2822 if (device->gfx_init)
2823 device->ws->buffer_destroy(device->gfx_init);
2824
2825 radv_device_finish_border_color(device);
2826
2827 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2828 for (unsigned q = 0; q < device->queue_count[i]; q++)
2829 radv_queue_finish(&device->queues[i][q]);
2830 if (device->queue_count[i])
2831 vk_free(&device->vk.alloc, device->queues[i]);
2832 }
2833
2834 vk_free(&device->vk.alloc, device);
2835 return result;
2836 }
2837
2838 void radv_DestroyDevice(
2839 VkDevice _device,
2840 const VkAllocationCallbacks* pAllocator)
2841 {
2842 RADV_FROM_HANDLE(radv_device, device, _device);
2843
2844 if (!device)
2845 return;
2846
2847 if (device->trace_bo)
2848 device->ws->buffer_destroy(device->trace_bo);
2849
2850 if (device->gfx_init)
2851 device->ws->buffer_destroy(device->gfx_init);
2852
2853 radv_device_finish_border_color(device);
2854
2855 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2856 for (unsigned q = 0; q < device->queue_count[i]; q++)
2857 radv_queue_finish(&device->queues[i][q]);
2858 if (device->queue_count[i])
2859 vk_free(&device->vk.alloc, device->queues[i]);
2860 if (device->empty_cs[i])
2861 device->ws->cs_destroy(device->empty_cs[i]);
2862 }
2863 radv_device_finish_meta(device);
2864
2865 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2866 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2867
2868 radv_destroy_shader_slabs(device);
2869
2870 pthread_cond_destroy(&device->timeline_cond);
2871 radv_bo_list_finish(&device->bo_list);
2872
2873 radv_thread_trace_finish(device);
2874
2875 vk_free(&device->vk.alloc, device);
2876 }
2877
2878 VkResult radv_EnumerateInstanceLayerProperties(
2879 uint32_t* pPropertyCount,
2880 VkLayerProperties* pProperties)
2881 {
2882 if (pProperties == NULL) {
2883 *pPropertyCount = 0;
2884 return VK_SUCCESS;
2885 }
2886
2887 /* None supported at this time */
2888 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2889 }
2890
2891 VkResult radv_EnumerateDeviceLayerProperties(
2892 VkPhysicalDevice physicalDevice,
2893 uint32_t* pPropertyCount,
2894 VkLayerProperties* pProperties)
2895 {
2896 if (pProperties == NULL) {
2897 *pPropertyCount = 0;
2898 return VK_SUCCESS;
2899 }
2900
2901 /* None supported at this time */
2902 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2903 }
2904
2905 void radv_GetDeviceQueue2(
2906 VkDevice _device,
2907 const VkDeviceQueueInfo2* pQueueInfo,
2908 VkQueue* pQueue)
2909 {
2910 RADV_FROM_HANDLE(radv_device, device, _device);
2911 struct radv_queue *queue;
2912
2913 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2914 if (pQueueInfo->flags != queue->flags) {
2915 /* From the Vulkan 1.1.70 spec:
2916 *
2917 * "The queue returned by vkGetDeviceQueue2 must have the same
2918 * flags value from this structure as that used at device
2919 * creation time in a VkDeviceQueueCreateInfo instance. If no
2920 * matching flags were specified at device creation time then
2921 * pQueue will return VK_NULL_HANDLE."
2922 */
2923 *pQueue = VK_NULL_HANDLE;
2924 return;
2925 }
2926
2927 *pQueue = radv_queue_to_handle(queue);
2928 }
2929
2930 void radv_GetDeviceQueue(
2931 VkDevice _device,
2932 uint32_t queueFamilyIndex,
2933 uint32_t queueIndex,
2934 VkQueue* pQueue)
2935 {
2936 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2937 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2938 .queueFamilyIndex = queueFamilyIndex,
2939 .queueIndex = queueIndex
2940 };
2941
2942 radv_GetDeviceQueue2(_device, &info, pQueue);
2943 }
2944
2945 static void
2946 fill_geom_tess_rings(struct radv_queue *queue,
2947 uint32_t *map,
2948 bool add_sample_positions,
2949 uint32_t esgs_ring_size,
2950 struct radeon_winsys_bo *esgs_ring_bo,
2951 uint32_t gsvs_ring_size,
2952 struct radeon_winsys_bo *gsvs_ring_bo,
2953 uint32_t tess_factor_ring_size,
2954 uint32_t tess_offchip_ring_offset,
2955 uint32_t tess_offchip_ring_size,
2956 struct radeon_winsys_bo *tess_rings_bo)
2957 {
2958 uint32_t *desc = &map[4];
2959
2960 if (esgs_ring_bo) {
2961 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2962
2963 /* stride 0, num records - size, add tid, swizzle, elsize4,
2964 index stride 64 */
2965 desc[0] = esgs_va;
2966 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2967 S_008F04_SWIZZLE_ENABLE(true);
2968 desc[2] = esgs_ring_size;
2969 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2970 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2971 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2972 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2973 S_008F0C_INDEX_STRIDE(3) |
2974 S_008F0C_ADD_TID_ENABLE(1);
2975
2976 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2977 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2978 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2979 S_008F0C_RESOURCE_LEVEL(1);
2980 } else {
2981 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2982 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2983 S_008F0C_ELEMENT_SIZE(1);
2984 }
2985
2986 /* GS entry for ES->GS ring */
2987 /* stride 0, num records - size, elsize0,
2988 index stride 0 */
2989 desc[4] = esgs_va;
2990 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2991 desc[6] = esgs_ring_size;
2992 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2993 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2994 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2995 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2996
2997 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2998 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2999 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3000 S_008F0C_RESOURCE_LEVEL(1);
3001 } else {
3002 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3003 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3004 }
3005 }
3006
3007 desc += 8;
3008
3009 if (gsvs_ring_bo) {
3010 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3011
3012 /* VS entry for GS->VS ring */
3013 /* stride 0, num records - size, elsize0,
3014 index stride 0 */
3015 desc[0] = gsvs_va;
3016 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3017 desc[2] = gsvs_ring_size;
3018 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3019 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3020 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3021 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3022
3023 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3024 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3025 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3026 S_008F0C_RESOURCE_LEVEL(1);
3027 } else {
3028 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3030 }
3031
3032 /* stride gsvs_itemsize, num records 64
3033 elsize 4, index stride 16 */
3034 /* shader will patch stride and desc[2] */
3035 desc[4] = gsvs_va;
3036 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3037 S_008F04_SWIZZLE_ENABLE(1);
3038 desc[6] = 0;
3039 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3040 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3041 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3042 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3043 S_008F0C_INDEX_STRIDE(1) |
3044 S_008F0C_ADD_TID_ENABLE(true);
3045
3046 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3047 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3048 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3049 S_008F0C_RESOURCE_LEVEL(1);
3050 } else {
3051 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3052 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3053 S_008F0C_ELEMENT_SIZE(1);
3054 }
3055
3056 }
3057
3058 desc += 8;
3059
3060 if (tess_rings_bo) {
3061 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3062 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3063
3064 desc[0] = tess_va;
3065 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3066 desc[2] = tess_factor_ring_size;
3067 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3068 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3069 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3070 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3071
3072 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3073 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3074 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3075 S_008F0C_RESOURCE_LEVEL(1);
3076 } else {
3077 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3078 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3079 }
3080
3081 desc[4] = tess_offchip_va;
3082 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3083 desc[6] = tess_offchip_ring_size;
3084 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3085 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3086 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3087 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3088
3089 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3090 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3091 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3092 S_008F0C_RESOURCE_LEVEL(1);
3093 } else {
3094 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3096 }
3097 }
3098
3099 desc += 8;
3100
3101 if (add_sample_positions) {
3102 /* add sample positions after all rings */
3103 memcpy(desc, queue->device->sample_locations_1x, 8);
3104 desc += 2;
3105 memcpy(desc, queue->device->sample_locations_2x, 16);
3106 desc += 4;
3107 memcpy(desc, queue->device->sample_locations_4x, 32);
3108 desc += 8;
3109 memcpy(desc, queue->device->sample_locations_8x, 64);
3110 }
3111 }
3112
3113 static unsigned
3114 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3115 {
3116 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3117 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3118 device->physical_device->rad_info.family != CHIP_STONEY;
3119 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3120 unsigned max_offchip_buffers;
3121 unsigned offchip_granularity;
3122 unsigned hs_offchip_param;
3123
3124 /*
3125 * Per RadeonSI:
3126 * This must be one less than the maximum number due to a hw limitation.
3127 * Various hardware bugs need thGFX7
3128 *
3129 * Per AMDVLK:
3130 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3131 * Gfx7 should limit max_offchip_buffers to 508
3132 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3133 *
3134 * Follow AMDVLK here.
3135 */
3136 if (device->physical_device->rad_info.chip_class >= GFX10) {
3137 max_offchip_buffers_per_se = 256;
3138 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3139 device->physical_device->rad_info.chip_class == GFX7 ||
3140 device->physical_device->rad_info.chip_class == GFX6)
3141 --max_offchip_buffers_per_se;
3142
3143 max_offchip_buffers = max_offchip_buffers_per_se *
3144 device->physical_device->rad_info.max_se;
3145
3146 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3147 * around by setting 4K granularity.
3148 */
3149 if (device->tess_offchip_block_dw_size == 4096) {
3150 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3151 offchip_granularity = V_03093C_X_4K_DWORDS;
3152 } else {
3153 assert(device->tess_offchip_block_dw_size == 8192);
3154 offchip_granularity = V_03093C_X_8K_DWORDS;
3155 }
3156
3157 switch (device->physical_device->rad_info.chip_class) {
3158 case GFX6:
3159 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3160 break;
3161 case GFX7:
3162 case GFX8:
3163 case GFX9:
3164 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3165 break;
3166 case GFX10:
3167 break;
3168 default:
3169 break;
3170 }
3171
3172 *max_offchip_buffers_p = max_offchip_buffers;
3173 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3174 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3175 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3176 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3177 if (device->physical_device->rad_info.chip_class >= GFX8)
3178 --max_offchip_buffers;
3179 hs_offchip_param =
3180 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3181 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3182 } else {
3183 hs_offchip_param =
3184 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3185 }
3186 return hs_offchip_param;
3187 }
3188
3189 static void
3190 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3191 struct radeon_winsys_bo *esgs_ring_bo,
3192 uint32_t esgs_ring_size,
3193 struct radeon_winsys_bo *gsvs_ring_bo,
3194 uint32_t gsvs_ring_size)
3195 {
3196 if (!esgs_ring_bo && !gsvs_ring_bo)
3197 return;
3198
3199 if (esgs_ring_bo)
3200 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3201
3202 if (gsvs_ring_bo)
3203 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3204
3205 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3206 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3207 radeon_emit(cs, esgs_ring_size >> 8);
3208 radeon_emit(cs, gsvs_ring_size >> 8);
3209 } else {
3210 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3211 radeon_emit(cs, esgs_ring_size >> 8);
3212 radeon_emit(cs, gsvs_ring_size >> 8);
3213 }
3214 }
3215
3216 static void
3217 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3218 unsigned hs_offchip_param, unsigned tf_ring_size,
3219 struct radeon_winsys_bo *tess_rings_bo)
3220 {
3221 uint64_t tf_va;
3222
3223 if (!tess_rings_bo)
3224 return;
3225
3226 tf_va = radv_buffer_get_va(tess_rings_bo);
3227
3228 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3229
3230 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3231 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3232 S_030938_SIZE(tf_ring_size / 4));
3233 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3234 tf_va >> 8);
3235
3236 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3237 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3238 S_030984_BASE_HI(tf_va >> 40));
3239 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3240 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3241 S_030944_BASE_HI(tf_va >> 40));
3242 }
3243 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3244 hs_offchip_param);
3245 } else {
3246 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3247 S_008988_SIZE(tf_ring_size / 4));
3248 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3249 tf_va >> 8);
3250 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3251 hs_offchip_param);
3252 }
3253 }
3254
3255 static void
3256 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3257 uint32_t size_per_wave, uint32_t waves,
3258 struct radeon_winsys_bo *scratch_bo)
3259 {
3260 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3261 return;
3262
3263 if (!scratch_bo)
3264 return;
3265
3266 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3267
3268 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3269 S_0286E8_WAVES(waves) |
3270 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3271 }
3272
3273 static void
3274 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3275 uint32_t size_per_wave, uint32_t waves,
3276 struct radeon_winsys_bo *compute_scratch_bo)
3277 {
3278 uint64_t scratch_va;
3279
3280 if (!compute_scratch_bo)
3281 return;
3282
3283 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3284
3285 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3286
3287 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3288 radeon_emit(cs, scratch_va);
3289 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3290 S_008F04_SWIZZLE_ENABLE(1));
3291
3292 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3293 S_00B860_WAVES(waves) |
3294 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3295 }
3296
3297 static void
3298 radv_emit_global_shader_pointers(struct radv_queue *queue,
3299 struct radeon_cmdbuf *cs,
3300 struct radeon_winsys_bo *descriptor_bo)
3301 {
3302 uint64_t va;
3303
3304 if (!descriptor_bo)
3305 return;
3306
3307 va = radv_buffer_get_va(descriptor_bo);
3308
3309 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3310
3311 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3312 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3313 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3314 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3315 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3316
3317 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3318 radv_emit_shader_pointer(queue->device, cs, regs[i],
3319 va, true);
3320 }
3321 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3322 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3323 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3324 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3325 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3326
3327 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3328 radv_emit_shader_pointer(queue->device, cs, regs[i],
3329 va, true);
3330 }
3331 } else {
3332 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3333 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3334 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3335 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3336 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3337 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3338
3339 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3340 radv_emit_shader_pointer(queue->device, cs, regs[i],
3341 va, true);
3342 }
3343 }
3344 }
3345
3346 static void
3347 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3348 {
3349 struct radv_device *device = queue->device;
3350
3351 if (device->gfx_init) {
3352 uint64_t va = radv_buffer_get_va(device->gfx_init);
3353
3354 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3355 radeon_emit(cs, va);
3356 radeon_emit(cs, va >> 32);
3357 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3358
3359 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3360 } else {
3361 si_emit_graphics(device, cs);
3362 }
3363 }
3364
3365 static void
3366 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3367 {
3368 struct radv_physical_device *physical_device = queue->device->physical_device;
3369 si_emit_compute(physical_device, cs);
3370 }
3371
3372 static VkResult
3373 radv_get_preamble_cs(struct radv_queue *queue,
3374 uint32_t scratch_size_per_wave,
3375 uint32_t scratch_waves,
3376 uint32_t compute_scratch_size_per_wave,
3377 uint32_t compute_scratch_waves,
3378 uint32_t esgs_ring_size,
3379 uint32_t gsvs_ring_size,
3380 bool needs_tess_rings,
3381 bool needs_gds,
3382 bool needs_gds_oa,
3383 bool needs_sample_positions,
3384 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3385 struct radeon_cmdbuf **initial_preamble_cs,
3386 struct radeon_cmdbuf **continue_preamble_cs)
3387 {
3388 struct radeon_winsys_bo *scratch_bo = NULL;
3389 struct radeon_winsys_bo *descriptor_bo = NULL;
3390 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3391 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3392 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3393 struct radeon_winsys_bo *tess_rings_bo = NULL;
3394 struct radeon_winsys_bo *gds_bo = NULL;
3395 struct radeon_winsys_bo *gds_oa_bo = NULL;
3396 struct radeon_cmdbuf *dest_cs[3] = {0};
3397 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3398 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3399 unsigned max_offchip_buffers;
3400 unsigned hs_offchip_param = 0;
3401 unsigned tess_offchip_ring_offset;
3402 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3403 if (!queue->has_tess_rings) {
3404 if (needs_tess_rings)
3405 add_tess_rings = true;
3406 }
3407 if (!queue->has_gds) {
3408 if (needs_gds)
3409 add_gds = true;
3410 }
3411 if (!queue->has_gds_oa) {
3412 if (needs_gds_oa)
3413 add_gds_oa = true;
3414 }
3415 if (!queue->has_sample_positions) {
3416 if (needs_sample_positions)
3417 add_sample_positions = true;
3418 }
3419 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3420 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3421 &max_offchip_buffers);
3422 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3423 tess_offchip_ring_size = max_offchip_buffers *
3424 queue->device->tess_offchip_block_dw_size * 4;
3425
3426 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3427 if (scratch_size_per_wave)
3428 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3429 else
3430 scratch_waves = 0;
3431
3432 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3433 if (compute_scratch_size_per_wave)
3434 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3435 else
3436 compute_scratch_waves = 0;
3437
3438 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3439 scratch_waves <= queue->scratch_waves &&
3440 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3441 compute_scratch_waves <= queue->compute_scratch_waves &&
3442 esgs_ring_size <= queue->esgs_ring_size &&
3443 gsvs_ring_size <= queue->gsvs_ring_size &&
3444 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3445 queue->initial_preamble_cs) {
3446 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3447 *initial_preamble_cs = queue->initial_preamble_cs;
3448 *continue_preamble_cs = queue->continue_preamble_cs;
3449 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3450 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3451 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3452 *continue_preamble_cs = NULL;
3453 return VK_SUCCESS;
3454 }
3455
3456 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3457 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3458 if (scratch_size > queue_scratch_size) {
3459 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3460 scratch_size,
3461 4096,
3462 RADEON_DOMAIN_VRAM,
3463 ring_bo_flags,
3464 RADV_BO_PRIORITY_SCRATCH);
3465 if (!scratch_bo)
3466 goto fail;
3467 } else
3468 scratch_bo = queue->scratch_bo;
3469
3470 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3471 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3472 if (compute_scratch_size > compute_queue_scratch_size) {
3473 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3474 compute_scratch_size,
3475 4096,
3476 RADEON_DOMAIN_VRAM,
3477 ring_bo_flags,
3478 RADV_BO_PRIORITY_SCRATCH);
3479 if (!compute_scratch_bo)
3480 goto fail;
3481
3482 } else
3483 compute_scratch_bo = queue->compute_scratch_bo;
3484
3485 if (esgs_ring_size > queue->esgs_ring_size) {
3486 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3487 esgs_ring_size,
3488 4096,
3489 RADEON_DOMAIN_VRAM,
3490 ring_bo_flags,
3491 RADV_BO_PRIORITY_SCRATCH);
3492 if (!esgs_ring_bo)
3493 goto fail;
3494 } else {
3495 esgs_ring_bo = queue->esgs_ring_bo;
3496 esgs_ring_size = queue->esgs_ring_size;
3497 }
3498
3499 if (gsvs_ring_size > queue->gsvs_ring_size) {
3500 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3501 gsvs_ring_size,
3502 4096,
3503 RADEON_DOMAIN_VRAM,
3504 ring_bo_flags,
3505 RADV_BO_PRIORITY_SCRATCH);
3506 if (!gsvs_ring_bo)
3507 goto fail;
3508 } else {
3509 gsvs_ring_bo = queue->gsvs_ring_bo;
3510 gsvs_ring_size = queue->gsvs_ring_size;
3511 }
3512
3513 if (add_tess_rings) {
3514 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3515 tess_offchip_ring_offset + tess_offchip_ring_size,
3516 256,
3517 RADEON_DOMAIN_VRAM,
3518 ring_bo_flags,
3519 RADV_BO_PRIORITY_SCRATCH);
3520 if (!tess_rings_bo)
3521 goto fail;
3522 } else {
3523 tess_rings_bo = queue->tess_rings_bo;
3524 }
3525
3526 if (add_gds) {
3527 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3528
3529 /* 4 streamout GDS counters.
3530 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3531 */
3532 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3533 256, 4,
3534 RADEON_DOMAIN_GDS,
3535 ring_bo_flags,
3536 RADV_BO_PRIORITY_SCRATCH);
3537 if (!gds_bo)
3538 goto fail;
3539 } else {
3540 gds_bo = queue->gds_bo;
3541 }
3542
3543 if (add_gds_oa) {
3544 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3545
3546 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3547 4, 1,
3548 RADEON_DOMAIN_OA,
3549 ring_bo_flags,
3550 RADV_BO_PRIORITY_SCRATCH);
3551 if (!gds_oa_bo)
3552 goto fail;
3553 } else {
3554 gds_oa_bo = queue->gds_oa_bo;
3555 }
3556
3557 if (scratch_bo != queue->scratch_bo ||
3558 esgs_ring_bo != queue->esgs_ring_bo ||
3559 gsvs_ring_bo != queue->gsvs_ring_bo ||
3560 tess_rings_bo != queue->tess_rings_bo ||
3561 add_sample_positions) {
3562 uint32_t size = 0;
3563 if (gsvs_ring_bo || esgs_ring_bo ||
3564 tess_rings_bo || add_sample_positions) {
3565 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3566 if (add_sample_positions)
3567 size += 128; /* 64+32+16+8 = 120 bytes */
3568 }
3569 else if (scratch_bo)
3570 size = 8; /* 2 dword */
3571
3572 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3573 size,
3574 4096,
3575 RADEON_DOMAIN_VRAM,
3576 RADEON_FLAG_CPU_ACCESS |
3577 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3578 RADEON_FLAG_READ_ONLY,
3579 RADV_BO_PRIORITY_DESCRIPTOR);
3580 if (!descriptor_bo)
3581 goto fail;
3582 } else
3583 descriptor_bo = queue->descriptor_bo;
3584
3585 if (descriptor_bo != queue->descriptor_bo) {
3586 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3587 if (!map)
3588 goto fail;
3589
3590 if (scratch_bo) {
3591 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3592 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3593 S_008F04_SWIZZLE_ENABLE(1);
3594 map[0] = scratch_va;
3595 map[1] = rsrc1;
3596 }
3597
3598 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3599 fill_geom_tess_rings(queue, map, add_sample_positions,
3600 esgs_ring_size, esgs_ring_bo,
3601 gsvs_ring_size, gsvs_ring_bo,
3602 tess_factor_ring_size,
3603 tess_offchip_ring_offset,
3604 tess_offchip_ring_size,
3605 tess_rings_bo);
3606
3607 queue->device->ws->buffer_unmap(descriptor_bo);
3608 }
3609
3610 for(int i = 0; i < 3; ++i) {
3611 struct radeon_cmdbuf *cs = NULL;
3612 cs = queue->device->ws->cs_create(queue->device->ws,
3613 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3614 if (!cs)
3615 goto fail;
3616
3617 dest_cs[i] = cs;
3618
3619 if (scratch_bo)
3620 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3621
3622 /* Emit initial configuration. */
3623 switch (queue->queue_family_index) {
3624 case RADV_QUEUE_GENERAL:
3625 radv_init_graphics_state(cs, queue);
3626 break;
3627 case RADV_QUEUE_COMPUTE:
3628 radv_init_compute_state(cs, queue);
3629 break;
3630 case RADV_QUEUE_TRANSFER:
3631 break;
3632 }
3633
3634 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3635 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3636 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3637
3638 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3639 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3640 }
3641
3642 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3643 gsvs_ring_bo, gsvs_ring_size);
3644 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3645 tess_factor_ring_size, tess_rings_bo);
3646 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3647 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3648 compute_scratch_waves, compute_scratch_bo);
3649 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3650 scratch_waves, scratch_bo);
3651
3652 if (gds_bo)
3653 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3654 if (gds_oa_bo)
3655 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3656
3657 if (queue->device->trace_bo)
3658 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3659
3660 if (queue->device->border_color_data.bo)
3661 radv_cs_add_buffer(queue->device->ws, cs,
3662 queue->device->border_color_data.bo);
3663
3664 if (i == 0) {
3665 si_cs_emit_cache_flush(cs,
3666 queue->device->physical_device->rad_info.chip_class,
3667 NULL, 0,
3668 queue->queue_family_index == RING_COMPUTE &&
3669 queue->device->physical_device->rad_info.chip_class >= GFX7,
3670 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3671 RADV_CMD_FLAG_INV_ICACHE |
3672 RADV_CMD_FLAG_INV_SCACHE |
3673 RADV_CMD_FLAG_INV_VCACHE |
3674 RADV_CMD_FLAG_INV_L2 |
3675 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3676 } else if (i == 1) {
3677 si_cs_emit_cache_flush(cs,
3678 queue->device->physical_device->rad_info.chip_class,
3679 NULL, 0,
3680 queue->queue_family_index == RING_COMPUTE &&
3681 queue->device->physical_device->rad_info.chip_class >= GFX7,
3682 RADV_CMD_FLAG_INV_ICACHE |
3683 RADV_CMD_FLAG_INV_SCACHE |
3684 RADV_CMD_FLAG_INV_VCACHE |
3685 RADV_CMD_FLAG_INV_L2 |
3686 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3687 }
3688
3689 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3690 goto fail;
3691 }
3692
3693 if (queue->initial_full_flush_preamble_cs)
3694 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3695
3696 if (queue->initial_preamble_cs)
3697 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3698
3699 if (queue->continue_preamble_cs)
3700 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3701
3702 queue->initial_full_flush_preamble_cs = dest_cs[0];
3703 queue->initial_preamble_cs = dest_cs[1];
3704 queue->continue_preamble_cs = dest_cs[2];
3705
3706 if (scratch_bo != queue->scratch_bo) {
3707 if (queue->scratch_bo)
3708 queue->device->ws->buffer_destroy(queue->scratch_bo);
3709 queue->scratch_bo = scratch_bo;
3710 }
3711 queue->scratch_size_per_wave = scratch_size_per_wave;
3712 queue->scratch_waves = scratch_waves;
3713
3714 if (compute_scratch_bo != queue->compute_scratch_bo) {
3715 if (queue->compute_scratch_bo)
3716 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3717 queue->compute_scratch_bo = compute_scratch_bo;
3718 }
3719 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3720 queue->compute_scratch_waves = compute_scratch_waves;
3721
3722 if (esgs_ring_bo != queue->esgs_ring_bo) {
3723 if (queue->esgs_ring_bo)
3724 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3725 queue->esgs_ring_bo = esgs_ring_bo;
3726 queue->esgs_ring_size = esgs_ring_size;
3727 }
3728
3729 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3730 if (queue->gsvs_ring_bo)
3731 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3732 queue->gsvs_ring_bo = gsvs_ring_bo;
3733 queue->gsvs_ring_size = gsvs_ring_size;
3734 }
3735
3736 if (tess_rings_bo != queue->tess_rings_bo) {
3737 queue->tess_rings_bo = tess_rings_bo;
3738 queue->has_tess_rings = true;
3739 }
3740
3741 if (gds_bo != queue->gds_bo) {
3742 queue->gds_bo = gds_bo;
3743 queue->has_gds = true;
3744 }
3745
3746 if (gds_oa_bo != queue->gds_oa_bo) {
3747 queue->gds_oa_bo = gds_oa_bo;
3748 queue->has_gds_oa = true;
3749 }
3750
3751 if (descriptor_bo != queue->descriptor_bo) {
3752 if (queue->descriptor_bo)
3753 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3754
3755 queue->descriptor_bo = descriptor_bo;
3756 }
3757
3758 if (add_sample_positions)
3759 queue->has_sample_positions = true;
3760
3761 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3762 *initial_preamble_cs = queue->initial_preamble_cs;
3763 *continue_preamble_cs = queue->continue_preamble_cs;
3764 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3765 *continue_preamble_cs = NULL;
3766 return VK_SUCCESS;
3767 fail:
3768 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3769 if (dest_cs[i])
3770 queue->device->ws->cs_destroy(dest_cs[i]);
3771 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3772 queue->device->ws->buffer_destroy(descriptor_bo);
3773 if (scratch_bo && scratch_bo != queue->scratch_bo)
3774 queue->device->ws->buffer_destroy(scratch_bo);
3775 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3776 queue->device->ws->buffer_destroy(compute_scratch_bo);
3777 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3778 queue->device->ws->buffer_destroy(esgs_ring_bo);
3779 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3780 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3781 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3782 queue->device->ws->buffer_destroy(tess_rings_bo);
3783 if (gds_bo && gds_bo != queue->gds_bo)
3784 queue->device->ws->buffer_destroy(gds_bo);
3785 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3786 queue->device->ws->buffer_destroy(gds_oa_bo);
3787
3788 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3789 }
3790
3791 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3792 struct radv_winsys_sem_counts *counts,
3793 int num_sems,
3794 struct radv_semaphore_part **sems,
3795 const uint64_t *timeline_values,
3796 VkFence _fence,
3797 bool is_signal)
3798 {
3799 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0;
3800
3801 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3802 return VK_SUCCESS;
3803
3804 for (uint32_t i = 0; i < num_sems; i++) {
3805 switch(sems[i]->kind) {
3806 case RADV_SEMAPHORE_SYNCOBJ:
3807 counts->syncobj_count++;
3808 counts->syncobj_reset_count++;
3809 break;
3810 case RADV_SEMAPHORE_WINSYS:
3811 counts->sem_count++;
3812 break;
3813 case RADV_SEMAPHORE_NONE:
3814 break;
3815 case RADV_SEMAPHORE_TIMELINE:
3816 counts->syncobj_count++;
3817 break;
3818 }
3819 }
3820
3821 if (_fence != VK_NULL_HANDLE) {
3822 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3823
3824 struct radv_fence_part *part =
3825 fence->temporary.kind != RADV_FENCE_NONE ?
3826 &fence->temporary : &fence->permanent;
3827 if (part->kind == RADV_FENCE_SYNCOBJ)
3828 counts->syncobj_count++;
3829 }
3830
3831 if (counts->syncobj_count) {
3832 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3833 if (!counts->syncobj)
3834 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3835 }
3836
3837 if (counts->sem_count) {
3838 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3839 if (!counts->sem) {
3840 free(counts->syncobj);
3841 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3842 }
3843 }
3844
3845 non_reset_idx = counts->syncobj_reset_count;
3846
3847 for (uint32_t i = 0; i < num_sems; i++) {
3848 switch(sems[i]->kind) {
3849 case RADV_SEMAPHORE_NONE:
3850 unreachable("Empty semaphore");
3851 break;
3852 case RADV_SEMAPHORE_SYNCOBJ:
3853 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3854 break;
3855 case RADV_SEMAPHORE_WINSYS:
3856 counts->sem[sem_idx++] = sems[i]->ws_sem;
3857 break;
3858 case RADV_SEMAPHORE_TIMELINE: {
3859 pthread_mutex_lock(&sems[i]->timeline.mutex);
3860 struct radv_timeline_point *point = NULL;
3861 if (is_signal) {
3862 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3863 } else {
3864 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3865 }
3866
3867 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3868
3869 if (point) {
3870 counts->syncobj[non_reset_idx++] = point->syncobj;
3871 } else {
3872 /* Explicitly remove the semaphore so we might not find
3873 * a point later post-submit. */
3874 sems[i] = NULL;
3875 }
3876 break;
3877 }
3878 }
3879 }
3880
3881 if (_fence != VK_NULL_HANDLE) {
3882 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3883
3884 struct radv_fence_part *part =
3885 fence->temporary.kind != RADV_FENCE_NONE ?
3886 &fence->temporary : &fence->permanent;
3887 if (part->kind == RADV_FENCE_SYNCOBJ)
3888 counts->syncobj[non_reset_idx++] = part->syncobj;
3889 }
3890
3891 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
3892 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
3893
3894 return VK_SUCCESS;
3895 }
3896
3897 static void
3898 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3899 {
3900 free(sem_info->wait.syncobj);
3901 free(sem_info->wait.sem);
3902 free(sem_info->signal.syncobj);
3903 free(sem_info->signal.sem);
3904 }
3905
3906
3907 static void radv_free_temp_syncobjs(struct radv_device *device,
3908 int num_sems,
3909 struct radv_semaphore_part *sems)
3910 {
3911 for (uint32_t i = 0; i < num_sems; i++) {
3912 radv_destroy_semaphore_part(device, sems + i);
3913 }
3914 }
3915
3916 static VkResult
3917 radv_alloc_sem_info(struct radv_device *device,
3918 struct radv_winsys_sem_info *sem_info,
3919 int num_wait_sems,
3920 struct radv_semaphore_part **wait_sems,
3921 const uint64_t *wait_values,
3922 int num_signal_sems,
3923 struct radv_semaphore_part **signal_sems,
3924 const uint64_t *signal_values,
3925 VkFence fence)
3926 {
3927 VkResult ret;
3928 memset(sem_info, 0, sizeof(*sem_info));
3929
3930 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3931 if (ret)
3932 return ret;
3933 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3934 if (ret)
3935 radv_free_sem_info(sem_info);
3936
3937 /* caller can override these */
3938 sem_info->cs_emit_wait = true;
3939 sem_info->cs_emit_signal = true;
3940 return ret;
3941 }
3942
3943 static void
3944 radv_finalize_timelines(struct radv_device *device,
3945 uint32_t num_wait_sems,
3946 struct radv_semaphore_part **wait_sems,
3947 const uint64_t *wait_values,
3948 uint32_t num_signal_sems,
3949 struct radv_semaphore_part **signal_sems,
3950 const uint64_t *signal_values,
3951 struct list_head *processing_list)
3952 {
3953 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3954 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3955 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3956 struct radv_timeline_point *point =
3957 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3958 point->wait_count -= 2;
3959 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3960 }
3961 }
3962 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3963 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3964 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3965 struct radv_timeline_point *point =
3966 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3967 signal_sems[i]->timeline.highest_submitted =
3968 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3969 point->wait_count -= 2;
3970 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3971 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3972 }
3973 }
3974 }
3975
3976 static VkResult
3977 radv_sparse_buffer_bind_memory(struct radv_device *device,
3978 const VkSparseBufferMemoryBindInfo *bind)
3979 {
3980 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3981 VkResult result;
3982
3983 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3984 struct radv_device_memory *mem = NULL;
3985
3986 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3987 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3988
3989 result = device->ws->buffer_virtual_bind(buffer->bo,
3990 bind->pBinds[i].resourceOffset,
3991 bind->pBinds[i].size,
3992 mem ? mem->bo : NULL,
3993 bind->pBinds[i].memoryOffset);
3994 if (result != VK_SUCCESS)
3995 return result;
3996 }
3997
3998 return VK_SUCCESS;
3999 }
4000
4001 static VkResult
4002 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4003 const VkSparseImageOpaqueMemoryBindInfo *bind)
4004 {
4005 RADV_FROM_HANDLE(radv_image, image, bind->image);
4006 VkResult result;
4007
4008 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4009 struct radv_device_memory *mem = NULL;
4010
4011 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4012 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4013
4014 result = device->ws->buffer_virtual_bind(image->bo,
4015 bind->pBinds[i].resourceOffset,
4016 bind->pBinds[i].size,
4017 mem ? mem->bo : NULL,
4018 bind->pBinds[i].memoryOffset);
4019 if (result != VK_SUCCESS)
4020 return result;
4021 }
4022
4023 return VK_SUCCESS;
4024 }
4025
4026 static VkResult
4027 radv_get_preambles(struct radv_queue *queue,
4028 const VkCommandBuffer *cmd_buffers,
4029 uint32_t cmd_buffer_count,
4030 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4031 struct radeon_cmdbuf **initial_preamble_cs,
4032 struct radeon_cmdbuf **continue_preamble_cs)
4033 {
4034 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4035 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4036 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4037 bool tess_rings_needed = false;
4038 bool gds_needed = false;
4039 bool gds_oa_needed = false;
4040 bool sample_positions_needed = false;
4041
4042 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4044 cmd_buffers[j]);
4045
4046 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4047 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4048 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4049 cmd_buffer->compute_scratch_size_per_wave_needed);
4050 compute_waves_wanted = MAX2(compute_waves_wanted,
4051 cmd_buffer->compute_scratch_waves_wanted);
4052 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4053 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4054 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4055 gds_needed |= cmd_buffer->gds_needed;
4056 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4057 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4058 }
4059
4060 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4061 compute_scratch_size_per_wave, compute_waves_wanted,
4062 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4063 gds_needed, gds_oa_needed, sample_positions_needed,
4064 initial_full_flush_preamble_cs,
4065 initial_preamble_cs, continue_preamble_cs);
4066 }
4067
4068 struct radv_deferred_queue_submission {
4069 struct radv_queue *queue;
4070 VkCommandBuffer *cmd_buffers;
4071 uint32_t cmd_buffer_count;
4072
4073 /* Sparse bindings that happen on a queue. */
4074 VkSparseBufferMemoryBindInfo *buffer_binds;
4075 uint32_t buffer_bind_count;
4076 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4077 uint32_t image_opaque_bind_count;
4078
4079 bool flush_caches;
4080 VkShaderStageFlags wait_dst_stage_mask;
4081 struct radv_semaphore_part **wait_semaphores;
4082 uint32_t wait_semaphore_count;
4083 struct radv_semaphore_part **signal_semaphores;
4084 uint32_t signal_semaphore_count;
4085 VkFence fence;
4086
4087 uint64_t *wait_values;
4088 uint64_t *signal_values;
4089
4090 struct radv_semaphore_part *temporary_semaphore_parts;
4091 uint32_t temporary_semaphore_part_count;
4092
4093 struct list_head queue_pending_list;
4094 uint32_t submission_wait_count;
4095 struct radv_timeline_waiter *wait_nodes;
4096
4097 struct list_head processing_list;
4098 };
4099
4100 struct radv_queue_submission {
4101 const VkCommandBuffer *cmd_buffers;
4102 uint32_t cmd_buffer_count;
4103
4104 /* Sparse bindings that happen on a queue. */
4105 const VkSparseBufferMemoryBindInfo *buffer_binds;
4106 uint32_t buffer_bind_count;
4107 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4108 uint32_t image_opaque_bind_count;
4109
4110 bool flush_caches;
4111 VkPipelineStageFlags wait_dst_stage_mask;
4112 const VkSemaphore *wait_semaphores;
4113 uint32_t wait_semaphore_count;
4114 const VkSemaphore *signal_semaphores;
4115 uint32_t signal_semaphore_count;
4116 VkFence fence;
4117
4118 const uint64_t *wait_values;
4119 uint32_t wait_value_count;
4120 const uint64_t *signal_values;
4121 uint32_t signal_value_count;
4122 };
4123
4124 static VkResult
4125 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4126 uint32_t decrement,
4127 struct list_head *processing_list);
4128
4129 static VkResult
4130 radv_create_deferred_submission(struct radv_queue *queue,
4131 const struct radv_queue_submission *submission,
4132 struct radv_deferred_queue_submission **out)
4133 {
4134 struct radv_deferred_queue_submission *deferred = NULL;
4135 size_t size = sizeof(struct radv_deferred_queue_submission);
4136
4137 uint32_t temporary_count = 0;
4138 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4139 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4140 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4141 ++temporary_count;
4142 }
4143
4144 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4145 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4146 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4147 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4148 size += temporary_count * sizeof(struct radv_semaphore_part);
4149 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4150 size += submission->wait_value_count * sizeof(uint64_t);
4151 size += submission->signal_value_count * sizeof(uint64_t);
4152 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4153
4154 deferred = calloc(1, size);
4155 if (!deferred)
4156 return VK_ERROR_OUT_OF_HOST_MEMORY;
4157
4158 deferred->queue = queue;
4159
4160 deferred->cmd_buffers = (void*)(deferred + 1);
4161 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4162 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4163 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4164
4165 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4166 deferred->buffer_bind_count = submission->buffer_bind_count;
4167 memcpy(deferred->buffer_binds, submission->buffer_binds,
4168 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4169
4170 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4171 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4172 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4173 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4174
4175 deferred->flush_caches = submission->flush_caches;
4176 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4177
4178 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4179 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4180
4181 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4182 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4183
4184 deferred->fence = submission->fence;
4185
4186 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4187 deferred->temporary_semaphore_part_count = temporary_count;
4188
4189 uint32_t temporary_idx = 0;
4190 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4191 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4192 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4193 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4194 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4195 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4196 ++temporary_idx;
4197 } else
4198 deferred->wait_semaphores[i] = &semaphore->permanent;
4199 }
4200
4201 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4202 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4203 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4204 deferred->signal_semaphores[i] = &semaphore->temporary;
4205 } else {
4206 deferred->signal_semaphores[i] = &semaphore->permanent;
4207 }
4208 }
4209
4210 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4211 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4212 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4213 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4214
4215 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4216 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4217 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4218 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4219
4220 *out = deferred;
4221 return VK_SUCCESS;
4222 }
4223
4224 static VkResult
4225 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4226 struct list_head *processing_list)
4227 {
4228 uint32_t wait_cnt = 0;
4229 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4230 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4231 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4232 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4233 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4234 ++wait_cnt;
4235 waiter->value = submission->wait_values[i];
4236 waiter->submission = submission;
4237 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4238 ++waiter;
4239 }
4240 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4241 }
4242 }
4243
4244 pthread_mutex_lock(&submission->queue->pending_mutex);
4245
4246 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4247 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4248
4249 pthread_mutex_unlock(&submission->queue->pending_mutex);
4250
4251 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4252 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4253 * submission. */
4254 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4255 return radv_queue_trigger_submission(submission, decrement, processing_list);
4256 }
4257
4258 static void
4259 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4260 struct list_head *processing_list)
4261 {
4262 pthread_mutex_lock(&submission->queue->pending_mutex);
4263 list_del(&submission->queue_pending_list);
4264
4265 /* trigger the next submission in the queue. */
4266 if (!list_is_empty(&submission->queue->pending_submissions)) {
4267 struct radv_deferred_queue_submission *next_submission =
4268 list_first_entry(&submission->queue->pending_submissions,
4269 struct radv_deferred_queue_submission,
4270 queue_pending_list);
4271 radv_queue_trigger_submission(next_submission, 1, processing_list);
4272 }
4273 pthread_mutex_unlock(&submission->queue->pending_mutex);
4274
4275 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4276 }
4277
4278 static VkResult
4279 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4280 struct list_head *processing_list)
4281 {
4282 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4283 struct radv_queue *queue = submission->queue;
4284 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4285 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4286 struct radeon_winsys_fence *base_fence = NULL;
4287 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4288 bool can_patch = true;
4289 uint32_t advance;
4290 struct radv_winsys_sem_info sem_info;
4291 VkResult result;
4292 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4293 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4294 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4295
4296 if (fence) {
4297 /* Under most circumstances, out fences won't be temporary.
4298 * However, the spec does allow it for opaque_fd.
4299 *
4300 * From the Vulkan 1.0.53 spec:
4301 *
4302 * "If the import is temporary, the implementation must
4303 * restore the semaphore to its prior permanent state after
4304 * submitting the next semaphore wait operation."
4305 */
4306 struct radv_fence_part *part =
4307 fence->temporary.kind != RADV_FENCE_NONE ?
4308 &fence->temporary : &fence->permanent;
4309 if (part->kind == RADV_FENCE_WINSYS)
4310 base_fence = part->fence;
4311 }
4312
4313 result = radv_get_preambles(queue, submission->cmd_buffers,
4314 submission->cmd_buffer_count,
4315 &initial_preamble_cs,
4316 &initial_flush_preamble_cs,
4317 &continue_preamble_cs);
4318 if (result != VK_SUCCESS)
4319 goto fail;
4320
4321 result = radv_alloc_sem_info(queue->device,
4322 &sem_info,
4323 submission->wait_semaphore_count,
4324 submission->wait_semaphores,
4325 submission->wait_values,
4326 submission->signal_semaphore_count,
4327 submission->signal_semaphores,
4328 submission->signal_values,
4329 submission->fence);
4330 if (result != VK_SUCCESS)
4331 goto fail;
4332
4333 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4334 result = radv_sparse_buffer_bind_memory(queue->device,
4335 submission->buffer_binds + i);
4336 if (result != VK_SUCCESS)
4337 goto fail;
4338 }
4339
4340 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4341 result = radv_sparse_image_opaque_bind_memory(queue->device,
4342 submission->image_opaque_binds + i);
4343 if (result != VK_SUCCESS)
4344 goto fail;
4345 }
4346
4347 if (!submission->cmd_buffer_count) {
4348 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4349 &queue->device->empty_cs[queue->queue_family_index],
4350 1, NULL, NULL,
4351 &sem_info, NULL,
4352 false, base_fence);
4353 if (result != VK_SUCCESS)
4354 goto fail;
4355 } else {
4356 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4357 (submission->cmd_buffer_count));
4358
4359 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4361 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4362
4363 cs_array[j] = cmd_buffer->cs;
4364 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4365 can_patch = false;
4366
4367 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4368 }
4369
4370 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4371 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4372 const struct radv_winsys_bo_list *bo_list = NULL;
4373
4374 advance = MIN2(max_cs_submission,
4375 submission->cmd_buffer_count - j);
4376
4377 if (queue->device->trace_bo)
4378 *queue->device->trace_id_ptr = 0;
4379
4380 sem_info.cs_emit_wait = j == 0;
4381 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4382
4383 if (unlikely(queue->device->use_global_bo_list)) {
4384 pthread_mutex_lock(&queue->device->bo_list.mutex);
4385 bo_list = &queue->device->bo_list.list;
4386 }
4387
4388 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4389 advance, initial_preamble, continue_preamble_cs,
4390 &sem_info, bo_list,
4391 can_patch, base_fence);
4392
4393 if (unlikely(queue->device->use_global_bo_list))
4394 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4395
4396 if (result != VK_SUCCESS)
4397 goto fail;
4398
4399 if (queue->device->trace_bo) {
4400 radv_check_gpu_hangs(queue, cs_array[j]);
4401 }
4402 }
4403
4404 free(cs_array);
4405 }
4406
4407 radv_free_temp_syncobjs(queue->device,
4408 submission->temporary_semaphore_part_count,
4409 submission->temporary_semaphore_parts);
4410 radv_finalize_timelines(queue->device,
4411 submission->wait_semaphore_count,
4412 submission->wait_semaphores,
4413 submission->wait_values,
4414 submission->signal_semaphore_count,
4415 submission->signal_semaphores,
4416 submission->signal_values,
4417 processing_list);
4418 /* Has to happen after timeline finalization to make sure the
4419 * condition variable is only triggered when timelines and queue have
4420 * been updated. */
4421 radv_queue_submission_update_queue(submission, processing_list);
4422 radv_free_sem_info(&sem_info);
4423 free(submission);
4424 return VK_SUCCESS;
4425
4426 fail:
4427 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4428 /* When something bad happened during the submission, such as
4429 * an out of memory issue, it might be hard to recover from
4430 * this inconsistent state. To avoid this sort of problem, we
4431 * assume that we are in a really bad situation and return
4432 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4433 * to submit the same job again to this device.
4434 */
4435 result = VK_ERROR_DEVICE_LOST;
4436 }
4437
4438 radv_free_temp_syncobjs(queue->device,
4439 submission->temporary_semaphore_part_count,
4440 submission->temporary_semaphore_parts);
4441 free(submission);
4442 return result;
4443 }
4444
4445 static VkResult
4446 radv_process_submissions(struct list_head *processing_list)
4447 {
4448 while(!list_is_empty(processing_list)) {
4449 struct radv_deferred_queue_submission *submission =
4450 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4451 list_del(&submission->processing_list);
4452
4453 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4454 if (result != VK_SUCCESS)
4455 return result;
4456 }
4457 return VK_SUCCESS;
4458 }
4459
4460 static VkResult
4461 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4462 uint64_t timeout)
4463 {
4464 return VK_SUCCESS; /* TODO: when we implement timeline syncobj. */
4465 }
4466
4467 static void* radv_queue_submission_thread_run(void *q)
4468 {
4469 struct radv_queue *queue = q;
4470
4471 pthread_mutex_lock(&queue->thread_mutex);
4472 while (!p_atomic_read(&queue->thread_exit)) {
4473 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4474 struct list_head processing_list;
4475 VkResult result = VK_SUCCESS;
4476 if (!submission) {
4477 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4478 continue;
4479 }
4480 pthread_mutex_unlock(&queue->thread_mutex);
4481
4482 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4483 * a semaphore never gets signaled. If it takes longer we just retry
4484 * the wait next iteration. */
4485 result = wait_for_submission_timelines_available(submission,
4486 radv_get_absolute_timeout(5000000000));
4487 if (result != VK_SUCCESS) {
4488 pthread_mutex_lock(&queue->thread_mutex);
4489 continue;
4490 }
4491
4492 /* The lock isn't held but nobody will add one until we finish
4493 * the current submission. */
4494 p_atomic_set(&queue->thread_submission, NULL);
4495
4496 list_inithead(&processing_list);
4497 list_addtail(&submission->processing_list, &processing_list);
4498 result = radv_process_submissions(&processing_list);
4499
4500 pthread_mutex_lock(&queue->thread_mutex);
4501 }
4502 pthread_mutex_unlock(&queue->thread_mutex);
4503 return NULL;
4504 }
4505
4506 static VkResult
4507 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4508 uint32_t decrement,
4509 struct list_head *processing_list)
4510 {
4511 struct radv_queue *queue = submission->queue;
4512 int ret;
4513 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4514 return VK_SUCCESS;
4515
4516 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4517 list_addtail(&submission->processing_list, processing_list);
4518 return VK_SUCCESS;
4519 }
4520
4521 pthread_mutex_lock(&queue->thread_mutex);
4522
4523 /* A submission can only be ready for the thread if it doesn't have
4524 * any predecessors in the same queue, so there can only be one such
4525 * submission at a time. */
4526 assert(queue->thread_submission == NULL);
4527
4528 /* Only start the thread on demand to save resources for the many games
4529 * which only use binary semaphores. */
4530 if (!queue->thread_running) {
4531 ret = pthread_create(&queue->submission_thread, NULL,
4532 radv_queue_submission_thread_run, queue);
4533 if (ret) {
4534 pthread_mutex_unlock(&queue->thread_mutex);
4535 return vk_errorf(queue->device->instance,
4536 VK_ERROR_DEVICE_LOST,
4537 "Failed to start submission thread");
4538 }
4539 queue->thread_running = true;
4540 }
4541
4542 queue->thread_submission = submission;
4543 pthread_mutex_unlock(&queue->thread_mutex);
4544
4545 pthread_cond_signal(&queue->thread_cond);
4546 return VK_SUCCESS;
4547 }
4548
4549 static VkResult radv_queue_submit(struct radv_queue *queue,
4550 const struct radv_queue_submission *submission)
4551 {
4552 struct radv_deferred_queue_submission *deferred = NULL;
4553
4554 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4555 if (result != VK_SUCCESS)
4556 return result;
4557
4558 struct list_head processing_list;
4559 list_inithead(&processing_list);
4560
4561 result = radv_queue_enqueue_submission(deferred, &processing_list);
4562 if (result != VK_SUCCESS) {
4563 /* If anything is in the list we leak. */
4564 assert(list_is_empty(&processing_list));
4565 return result;
4566 }
4567 return radv_process_submissions(&processing_list);
4568 }
4569
4570 bool
4571 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4572 {
4573 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4574 struct radv_winsys_sem_info sem_info;
4575 VkResult result;
4576
4577 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4578 0, NULL, VK_NULL_HANDLE);
4579 if (result != VK_SUCCESS)
4580 return false;
4581
4582 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4583 NULL, NULL, &sem_info, NULL,
4584 false, NULL);
4585 radv_free_sem_info(&sem_info);
4586 if (result != VK_SUCCESS)
4587 return false;
4588
4589 return true;
4590
4591 }
4592
4593 /* Signals fence as soon as all the work currently put on queue is done. */
4594 static VkResult radv_signal_fence(struct radv_queue *queue,
4595 VkFence fence)
4596 {
4597 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4598 .fence = fence
4599 });
4600 }
4601
4602 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4603 {
4604 return info->commandBufferCount ||
4605 info->waitSemaphoreCount ||
4606 info->signalSemaphoreCount;
4607 }
4608
4609 VkResult radv_QueueSubmit(
4610 VkQueue _queue,
4611 uint32_t submitCount,
4612 const VkSubmitInfo* pSubmits,
4613 VkFence fence)
4614 {
4615 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4616 VkResult result;
4617 uint32_t fence_idx = 0;
4618 bool flushed_caches = false;
4619
4620 if (fence != VK_NULL_HANDLE) {
4621 for (uint32_t i = 0; i < submitCount; ++i)
4622 if (radv_submit_has_effects(pSubmits + i))
4623 fence_idx = i;
4624 } else
4625 fence_idx = UINT32_MAX;
4626
4627 for (uint32_t i = 0; i < submitCount; i++) {
4628 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4629 continue;
4630
4631 VkPipelineStageFlags wait_dst_stage_mask = 0;
4632 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4633 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4634 }
4635
4636 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4637 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4638
4639 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4640 .cmd_buffers = pSubmits[i].pCommandBuffers,
4641 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4642 .wait_dst_stage_mask = wait_dst_stage_mask,
4643 .flush_caches = !flushed_caches,
4644 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4645 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4646 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4647 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4648 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4649 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4650 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4651 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4652 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4653 });
4654 if (result != VK_SUCCESS)
4655 return result;
4656
4657 flushed_caches = true;
4658 }
4659
4660 if (fence != VK_NULL_HANDLE && !submitCount) {
4661 result = radv_signal_fence(queue, fence);
4662 if (result != VK_SUCCESS)
4663 return result;
4664 }
4665
4666 return VK_SUCCESS;
4667 }
4668
4669 VkResult radv_QueueWaitIdle(
4670 VkQueue _queue)
4671 {
4672 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4673
4674 pthread_mutex_lock(&queue->pending_mutex);
4675 while (!list_is_empty(&queue->pending_submissions)) {
4676 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4677 }
4678 pthread_mutex_unlock(&queue->pending_mutex);
4679
4680 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4681 radv_queue_family_to_ring(queue->queue_family_index),
4682 queue->queue_idx))
4683 return VK_ERROR_DEVICE_LOST;
4684
4685 return VK_SUCCESS;
4686 }
4687
4688 VkResult radv_DeviceWaitIdle(
4689 VkDevice _device)
4690 {
4691 RADV_FROM_HANDLE(radv_device, device, _device);
4692
4693 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4694 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4695 VkResult result =
4696 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4697
4698 if (result != VK_SUCCESS)
4699 return result;
4700 }
4701 }
4702 return VK_SUCCESS;
4703 }
4704
4705 VkResult radv_EnumerateInstanceExtensionProperties(
4706 const char* pLayerName,
4707 uint32_t* pPropertyCount,
4708 VkExtensionProperties* pProperties)
4709 {
4710 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4711
4712 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4713 if (radv_instance_extensions_supported.extensions[i]) {
4714 vk_outarray_append(&out, prop) {
4715 *prop = radv_instance_extensions[i];
4716 }
4717 }
4718 }
4719
4720 return vk_outarray_status(&out);
4721 }
4722
4723 VkResult radv_EnumerateDeviceExtensionProperties(
4724 VkPhysicalDevice physicalDevice,
4725 const char* pLayerName,
4726 uint32_t* pPropertyCount,
4727 VkExtensionProperties* pProperties)
4728 {
4729 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4730 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4731
4732 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4733 if (device->supported_extensions.extensions[i]) {
4734 vk_outarray_append(&out, prop) {
4735 *prop = radv_device_extensions[i];
4736 }
4737 }
4738 }
4739
4740 return vk_outarray_status(&out);
4741 }
4742
4743 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4744 VkInstance _instance,
4745 const char* pName)
4746 {
4747 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4748
4749 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4750 * when we have to return valid function pointers, NULL, or it's left
4751 * undefined. See the table for exact details.
4752 */
4753 if (pName == NULL)
4754 return NULL;
4755
4756 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4757 if (strcmp(pName, "vk" #entrypoint) == 0) \
4758 return (PFN_vkVoidFunction)radv_##entrypoint
4759
4760 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4761 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4762 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4763 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4764
4765 /* GetInstanceProcAddr() can also be called with a NULL instance.
4766 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4767 */
4768 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4769
4770 #undef LOOKUP_RADV_ENTRYPOINT
4771
4772 if (instance == NULL)
4773 return NULL;
4774
4775 int idx = radv_get_instance_entrypoint_index(pName);
4776 if (idx >= 0)
4777 return instance->dispatch.entrypoints[idx];
4778
4779 idx = radv_get_physical_device_entrypoint_index(pName);
4780 if (idx >= 0)
4781 return instance->physical_device_dispatch.entrypoints[idx];
4782
4783 idx = radv_get_device_entrypoint_index(pName);
4784 if (idx >= 0)
4785 return instance->device_dispatch.entrypoints[idx];
4786
4787 return NULL;
4788 }
4789
4790 /* The loader wants us to expose a second GetInstanceProcAddr function
4791 * to work around certain LD_PRELOAD issues seen in apps.
4792 */
4793 PUBLIC
4794 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4795 VkInstance instance,
4796 const char* pName);
4797
4798 PUBLIC
4799 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4800 VkInstance instance,
4801 const char* pName)
4802 {
4803 return radv_GetInstanceProcAddr(instance, pName);
4804 }
4805
4806 PUBLIC
4807 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4808 VkInstance _instance,
4809 const char* pName);
4810
4811 PUBLIC
4812 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4813 VkInstance _instance,
4814 const char* pName)
4815 {
4816 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4817
4818 if (!pName || !instance)
4819 return NULL;
4820
4821 int idx = radv_get_physical_device_entrypoint_index(pName);
4822 if (idx < 0)
4823 return NULL;
4824
4825 return instance->physical_device_dispatch.entrypoints[idx];
4826 }
4827
4828 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4829 VkDevice _device,
4830 const char* pName)
4831 {
4832 RADV_FROM_HANDLE(radv_device, device, _device);
4833
4834 if (!device || !pName)
4835 return NULL;
4836
4837 int idx = radv_get_device_entrypoint_index(pName);
4838 if (idx < 0)
4839 return NULL;
4840
4841 return device->dispatch.entrypoints[idx];
4842 }
4843
4844 bool radv_get_memory_fd(struct radv_device *device,
4845 struct radv_device_memory *memory,
4846 int *pFD)
4847 {
4848 struct radeon_bo_metadata metadata;
4849
4850 if (memory->image) {
4851 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
4852 radv_init_metadata(device, memory->image, &metadata);
4853 device->ws->buffer_set_metadata(memory->bo, &metadata);
4854 }
4855
4856 return device->ws->buffer_get_fd(device->ws, memory->bo,
4857 pFD);
4858 }
4859
4860
4861 void
4862 radv_free_memory(struct radv_device *device,
4863 const VkAllocationCallbacks* pAllocator,
4864 struct radv_device_memory *mem)
4865 {
4866 if (mem == NULL)
4867 return;
4868
4869 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4870 if (mem->android_hardware_buffer)
4871 AHardwareBuffer_release(mem->android_hardware_buffer);
4872 #endif
4873
4874 if (mem->bo) {
4875 if (device->overallocation_disallowed) {
4876 mtx_lock(&device->overallocation_mutex);
4877 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
4878 mtx_unlock(&device->overallocation_mutex);
4879 }
4880
4881 radv_bo_list_remove(device, mem->bo);
4882 device->ws->buffer_destroy(mem->bo);
4883 mem->bo = NULL;
4884 }
4885
4886 vk_object_base_finish(&mem->base);
4887 vk_free2(&device->vk.alloc, pAllocator, mem);
4888 }
4889
4890 static VkResult radv_alloc_memory(struct radv_device *device,
4891 const VkMemoryAllocateInfo* pAllocateInfo,
4892 const VkAllocationCallbacks* pAllocator,
4893 VkDeviceMemory* pMem)
4894 {
4895 struct radv_device_memory *mem;
4896 VkResult result;
4897 enum radeon_bo_domain domain;
4898 uint32_t flags = 0;
4899
4900 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4901
4902 const VkImportMemoryFdInfoKHR *import_info =
4903 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4904 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4905 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4906 const VkExportMemoryAllocateInfo *export_info =
4907 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4908 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4909 vk_find_struct_const(pAllocateInfo->pNext,
4910 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4911 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4912 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4913
4914 const struct wsi_memory_allocate_info *wsi_info =
4915 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4916
4917 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4918 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4919 /* Apparently, this is allowed */
4920 *pMem = VK_NULL_HANDLE;
4921 return VK_SUCCESS;
4922 }
4923
4924 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
4925 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4926 if (mem == NULL)
4927 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4928
4929 vk_object_base_init(&device->vk, &mem->base,
4930 VK_OBJECT_TYPE_DEVICE_MEMORY);
4931
4932 if (wsi_info && wsi_info->implicit_sync)
4933 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4934
4935 if (dedicate_info) {
4936 mem->image = radv_image_from_handle(dedicate_info->image);
4937 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4938 } else {
4939 mem->image = NULL;
4940 mem->buffer = NULL;
4941 }
4942
4943 float priority_float = 0.5;
4944 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4945 vk_find_struct_const(pAllocateInfo->pNext,
4946 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4947 if (priority_ext)
4948 priority_float = priority_ext->priority;
4949
4950 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4951 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4952
4953 mem->user_ptr = NULL;
4954 mem->bo = NULL;
4955
4956 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4957 mem->android_hardware_buffer = NULL;
4958 #endif
4959
4960 if (ahb_import_info) {
4961 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4962 if (result != VK_SUCCESS)
4963 goto fail;
4964 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4965 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4966 if (result != VK_SUCCESS)
4967 goto fail;
4968 } else if (import_info) {
4969 assert(import_info->handleType ==
4970 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4971 import_info->handleType ==
4972 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4973 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4974 priority, NULL);
4975 if (!mem->bo) {
4976 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4977 goto fail;
4978 } else {
4979 close(import_info->fd);
4980 }
4981 } else if (host_ptr_info) {
4982 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4983 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4984 pAllocateInfo->allocationSize,
4985 priority);
4986 if (!mem->bo) {
4987 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4988 goto fail;
4989 } else {
4990 mem->user_ptr = host_ptr_info->pHostPointer;
4991 }
4992 } else {
4993 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4994 uint32_t heap_index;
4995
4996 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
4997 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
4998 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
4999
5000 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5001 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5002 if (device->use_global_bo_list) {
5003 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5004 }
5005 }
5006
5007 if (device->overallocation_disallowed) {
5008 uint64_t total_size =
5009 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5010
5011 mtx_lock(&device->overallocation_mutex);
5012 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5013 mtx_unlock(&device->overallocation_mutex);
5014 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5015 goto fail;
5016 }
5017 device->allocated_memory_size[heap_index] += alloc_size;
5018 mtx_unlock(&device->overallocation_mutex);
5019 }
5020
5021 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5022 domain, flags, priority);
5023
5024 if (!mem->bo) {
5025 if (device->overallocation_disallowed) {
5026 mtx_lock(&device->overallocation_mutex);
5027 device->allocated_memory_size[heap_index] -= alloc_size;
5028 mtx_unlock(&device->overallocation_mutex);
5029 }
5030 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5031 goto fail;
5032 }
5033
5034 mem->heap_index = heap_index;
5035 mem->alloc_size = alloc_size;
5036 }
5037
5038 if (!wsi_info) {
5039 result = radv_bo_list_add(device, mem->bo);
5040 if (result != VK_SUCCESS)
5041 goto fail;
5042 }
5043
5044 *pMem = radv_device_memory_to_handle(mem);
5045
5046 return VK_SUCCESS;
5047
5048 fail:
5049 radv_free_memory(device, pAllocator,mem);
5050
5051 return result;
5052 }
5053
5054 VkResult radv_AllocateMemory(
5055 VkDevice _device,
5056 const VkMemoryAllocateInfo* pAllocateInfo,
5057 const VkAllocationCallbacks* pAllocator,
5058 VkDeviceMemory* pMem)
5059 {
5060 RADV_FROM_HANDLE(radv_device, device, _device);
5061 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5062 }
5063
5064 void radv_FreeMemory(
5065 VkDevice _device,
5066 VkDeviceMemory _mem,
5067 const VkAllocationCallbacks* pAllocator)
5068 {
5069 RADV_FROM_HANDLE(radv_device, device, _device);
5070 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5071
5072 radv_free_memory(device, pAllocator, mem);
5073 }
5074
5075 VkResult radv_MapMemory(
5076 VkDevice _device,
5077 VkDeviceMemory _memory,
5078 VkDeviceSize offset,
5079 VkDeviceSize size,
5080 VkMemoryMapFlags flags,
5081 void** ppData)
5082 {
5083 RADV_FROM_HANDLE(radv_device, device, _device);
5084 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5085
5086 if (mem == NULL) {
5087 *ppData = NULL;
5088 return VK_SUCCESS;
5089 }
5090
5091 if (mem->user_ptr)
5092 *ppData = mem->user_ptr;
5093 else
5094 *ppData = device->ws->buffer_map(mem->bo);
5095
5096 if (*ppData) {
5097 *ppData += offset;
5098 return VK_SUCCESS;
5099 }
5100
5101 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5102 }
5103
5104 void radv_UnmapMemory(
5105 VkDevice _device,
5106 VkDeviceMemory _memory)
5107 {
5108 RADV_FROM_HANDLE(radv_device, device, _device);
5109 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5110
5111 if (mem == NULL)
5112 return;
5113
5114 if (mem->user_ptr == NULL)
5115 device->ws->buffer_unmap(mem->bo);
5116 }
5117
5118 VkResult radv_FlushMappedMemoryRanges(
5119 VkDevice _device,
5120 uint32_t memoryRangeCount,
5121 const VkMappedMemoryRange* pMemoryRanges)
5122 {
5123 return VK_SUCCESS;
5124 }
5125
5126 VkResult radv_InvalidateMappedMemoryRanges(
5127 VkDevice _device,
5128 uint32_t memoryRangeCount,
5129 const VkMappedMemoryRange* pMemoryRanges)
5130 {
5131 return VK_SUCCESS;
5132 }
5133
5134 void radv_GetBufferMemoryRequirements(
5135 VkDevice _device,
5136 VkBuffer _buffer,
5137 VkMemoryRequirements* pMemoryRequirements)
5138 {
5139 RADV_FROM_HANDLE(radv_device, device, _device);
5140 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5141
5142 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5143
5144 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5145 pMemoryRequirements->alignment = 4096;
5146 else
5147 pMemoryRequirements->alignment = 16;
5148
5149 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5150 }
5151
5152 void radv_GetBufferMemoryRequirements2(
5153 VkDevice device,
5154 const VkBufferMemoryRequirementsInfo2 *pInfo,
5155 VkMemoryRequirements2 *pMemoryRequirements)
5156 {
5157 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5158 &pMemoryRequirements->memoryRequirements);
5159 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5160 switch (ext->sType) {
5161 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5162 VkMemoryDedicatedRequirements *req =
5163 (VkMemoryDedicatedRequirements *) ext;
5164 req->requiresDedicatedAllocation = false;
5165 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5166 break;
5167 }
5168 default:
5169 break;
5170 }
5171 }
5172 }
5173
5174 void radv_GetImageMemoryRequirements(
5175 VkDevice _device,
5176 VkImage _image,
5177 VkMemoryRequirements* pMemoryRequirements)
5178 {
5179 RADV_FROM_HANDLE(radv_device, device, _device);
5180 RADV_FROM_HANDLE(radv_image, image, _image);
5181
5182 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5183
5184 pMemoryRequirements->size = image->size;
5185 pMemoryRequirements->alignment = image->alignment;
5186 }
5187
5188 void radv_GetImageMemoryRequirements2(
5189 VkDevice device,
5190 const VkImageMemoryRequirementsInfo2 *pInfo,
5191 VkMemoryRequirements2 *pMemoryRequirements)
5192 {
5193 radv_GetImageMemoryRequirements(device, pInfo->image,
5194 &pMemoryRequirements->memoryRequirements);
5195
5196 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5197
5198 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5199 switch (ext->sType) {
5200 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5201 VkMemoryDedicatedRequirements *req =
5202 (VkMemoryDedicatedRequirements *) ext;
5203 req->requiresDedicatedAllocation = image->shareable &&
5204 image->tiling != VK_IMAGE_TILING_LINEAR;
5205 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5206 break;
5207 }
5208 default:
5209 break;
5210 }
5211 }
5212 }
5213
5214 void radv_GetImageSparseMemoryRequirements(
5215 VkDevice device,
5216 VkImage image,
5217 uint32_t* pSparseMemoryRequirementCount,
5218 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5219 {
5220 stub();
5221 }
5222
5223 void radv_GetImageSparseMemoryRequirements2(
5224 VkDevice device,
5225 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5226 uint32_t* pSparseMemoryRequirementCount,
5227 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5228 {
5229 stub();
5230 }
5231
5232 void radv_GetDeviceMemoryCommitment(
5233 VkDevice device,
5234 VkDeviceMemory memory,
5235 VkDeviceSize* pCommittedMemoryInBytes)
5236 {
5237 *pCommittedMemoryInBytes = 0;
5238 }
5239
5240 VkResult radv_BindBufferMemory2(VkDevice device,
5241 uint32_t bindInfoCount,
5242 const VkBindBufferMemoryInfo *pBindInfos)
5243 {
5244 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5245 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5246 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5247
5248 if (mem) {
5249 buffer->bo = mem->bo;
5250 buffer->offset = pBindInfos[i].memoryOffset;
5251 } else {
5252 buffer->bo = NULL;
5253 }
5254 }
5255 return VK_SUCCESS;
5256 }
5257
5258 VkResult radv_BindBufferMemory(
5259 VkDevice device,
5260 VkBuffer buffer,
5261 VkDeviceMemory memory,
5262 VkDeviceSize memoryOffset)
5263 {
5264 const VkBindBufferMemoryInfo info = {
5265 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5266 .buffer = buffer,
5267 .memory = memory,
5268 .memoryOffset = memoryOffset
5269 };
5270
5271 return radv_BindBufferMemory2(device, 1, &info);
5272 }
5273
5274 VkResult radv_BindImageMemory2(VkDevice device,
5275 uint32_t bindInfoCount,
5276 const VkBindImageMemoryInfo *pBindInfos)
5277 {
5278 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5279 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5280 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5281
5282 if (mem) {
5283 image->bo = mem->bo;
5284 image->offset = pBindInfos[i].memoryOffset;
5285 } else {
5286 image->bo = NULL;
5287 image->offset = 0;
5288 }
5289 }
5290 return VK_SUCCESS;
5291 }
5292
5293
5294 VkResult radv_BindImageMemory(
5295 VkDevice device,
5296 VkImage image,
5297 VkDeviceMemory memory,
5298 VkDeviceSize memoryOffset)
5299 {
5300 const VkBindImageMemoryInfo info = {
5301 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5302 .image = image,
5303 .memory = memory,
5304 .memoryOffset = memoryOffset
5305 };
5306
5307 return radv_BindImageMemory2(device, 1, &info);
5308 }
5309
5310 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5311 {
5312 return info->bufferBindCount ||
5313 info->imageOpaqueBindCount ||
5314 info->imageBindCount ||
5315 info->waitSemaphoreCount ||
5316 info->signalSemaphoreCount;
5317 }
5318
5319 VkResult radv_QueueBindSparse(
5320 VkQueue _queue,
5321 uint32_t bindInfoCount,
5322 const VkBindSparseInfo* pBindInfo,
5323 VkFence fence)
5324 {
5325 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5326 VkResult result;
5327 uint32_t fence_idx = 0;
5328
5329 if (fence != VK_NULL_HANDLE) {
5330 for (uint32_t i = 0; i < bindInfoCount; ++i)
5331 if (radv_sparse_bind_has_effects(pBindInfo + i))
5332 fence_idx = i;
5333 } else
5334 fence_idx = UINT32_MAX;
5335
5336 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5337 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5338 continue;
5339
5340 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5341 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5342
5343 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5344 .buffer_binds = pBindInfo[i].pBufferBinds,
5345 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5346 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5347 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5348 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5349 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5350 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5351 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5352 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5353 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5354 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5355 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5356 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5357 });
5358
5359 if (result != VK_SUCCESS)
5360 return result;
5361 }
5362
5363 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5364 result = radv_signal_fence(queue, fence);
5365 if (result != VK_SUCCESS)
5366 return result;
5367 }
5368
5369 return VK_SUCCESS;
5370 }
5371
5372 static void
5373 radv_destroy_fence_part(struct radv_device *device,
5374 struct radv_fence_part *part)
5375 {
5376 switch (part->kind) {
5377 case RADV_FENCE_NONE:
5378 break;
5379 case RADV_FENCE_WINSYS:
5380 device->ws->destroy_fence(part->fence);
5381 break;
5382 case RADV_FENCE_SYNCOBJ:
5383 device->ws->destroy_syncobj(device->ws, part->syncobj);
5384 break;
5385 case RADV_FENCE_WSI:
5386 part->fence_wsi->destroy(part->fence_wsi);
5387 break;
5388 default:
5389 unreachable("Invalid fence type");
5390 }
5391
5392 part->kind = RADV_FENCE_NONE;
5393 }
5394
5395 static void
5396 radv_destroy_fence(struct radv_device *device,
5397 const VkAllocationCallbacks *pAllocator,
5398 struct radv_fence *fence)
5399 {
5400 radv_destroy_fence_part(device, &fence->temporary);
5401 radv_destroy_fence_part(device, &fence->permanent);
5402
5403 vk_object_base_finish(&fence->base);
5404 vk_free2(&device->vk.alloc, pAllocator, fence);
5405 }
5406
5407 VkResult radv_CreateFence(
5408 VkDevice _device,
5409 const VkFenceCreateInfo* pCreateInfo,
5410 const VkAllocationCallbacks* pAllocator,
5411 VkFence* pFence)
5412 {
5413 RADV_FROM_HANDLE(radv_device, device, _device);
5414 const VkExportFenceCreateInfo *export =
5415 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5416 VkExternalFenceHandleTypeFlags handleTypes =
5417 export ? export->handleTypes : 0;
5418 struct radv_fence *fence;
5419
5420 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5421 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5422 if (!fence)
5423 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5424
5425 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5426
5427 if (device->always_use_syncobj || handleTypes) {
5428 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5429
5430 bool create_signaled = false;
5431 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5432 create_signaled = true;
5433
5434 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5435 &fence->permanent.syncobj);
5436 if (ret) {
5437 radv_destroy_fence(device, pAllocator, fence);
5438 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5439 }
5440 } else {
5441 fence->permanent.kind = RADV_FENCE_WINSYS;
5442
5443 fence->permanent.fence = device->ws->create_fence();
5444 if (!fence->permanent.fence) {
5445 vk_free2(&device->vk.alloc, pAllocator, fence);
5446 radv_destroy_fence(device, pAllocator, fence);
5447 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5448 }
5449 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5450 device->ws->signal_fence(fence->permanent.fence);
5451 }
5452
5453 *pFence = radv_fence_to_handle(fence);
5454
5455 return VK_SUCCESS;
5456 }
5457
5458
5459 void radv_DestroyFence(
5460 VkDevice _device,
5461 VkFence _fence,
5462 const VkAllocationCallbacks* pAllocator)
5463 {
5464 RADV_FROM_HANDLE(radv_device, device, _device);
5465 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5466
5467 if (!fence)
5468 return;
5469
5470 radv_destroy_fence(device, pAllocator, fence);
5471 }
5472
5473 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5474 uint32_t fenceCount, const VkFence *pFences)
5475 {
5476 for (uint32_t i = 0; i < fenceCount; ++i) {
5477 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5478
5479 struct radv_fence_part *part =
5480 fence->temporary.kind != RADV_FENCE_NONE ?
5481 &fence->temporary : &fence->permanent;
5482 if (part->kind != RADV_FENCE_WINSYS ||
5483 !device->ws->is_fence_waitable(part->fence))
5484 return false;
5485 }
5486 return true;
5487 }
5488
5489 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5490 {
5491 for (uint32_t i = 0; i < fenceCount; ++i) {
5492 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5493
5494 struct radv_fence_part *part =
5495 fence->temporary.kind != RADV_FENCE_NONE ?
5496 &fence->temporary : &fence->permanent;
5497 if (part->kind != RADV_FENCE_SYNCOBJ)
5498 return false;
5499 }
5500 return true;
5501 }
5502
5503 VkResult radv_WaitForFences(
5504 VkDevice _device,
5505 uint32_t fenceCount,
5506 const VkFence* pFences,
5507 VkBool32 waitAll,
5508 uint64_t timeout)
5509 {
5510 RADV_FROM_HANDLE(radv_device, device, _device);
5511 timeout = radv_get_absolute_timeout(timeout);
5512
5513 if (device->always_use_syncobj &&
5514 radv_all_fences_syncobj(fenceCount, pFences))
5515 {
5516 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5517 if (!handles)
5518 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5519
5520 for (uint32_t i = 0; i < fenceCount; ++i) {
5521 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5522
5523 struct radv_fence_part *part =
5524 fence->temporary.kind != RADV_FENCE_NONE ?
5525 &fence->temporary : &fence->permanent;
5526
5527 assert(part->kind == RADV_FENCE_SYNCOBJ);
5528 handles[i] = part->syncobj;
5529 }
5530
5531 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5532
5533 free(handles);
5534 return success ? VK_SUCCESS : VK_TIMEOUT;
5535 }
5536
5537 if (!waitAll && fenceCount > 1) {
5538 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5539 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5540 uint32_t wait_count = 0;
5541 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5542 if (!fences)
5543 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5544
5545 for (uint32_t i = 0; i < fenceCount; ++i) {
5546 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5547
5548 struct radv_fence_part *part =
5549 fence->temporary.kind != RADV_FENCE_NONE ?
5550 &fence->temporary : &fence->permanent;
5551 assert(part->kind == RADV_FENCE_WINSYS);
5552
5553 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5554 free(fences);
5555 return VK_SUCCESS;
5556 }
5557
5558 fences[wait_count++] = part->fence;
5559 }
5560
5561 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5562 waitAll, timeout - radv_get_current_time());
5563
5564 free(fences);
5565 return success ? VK_SUCCESS : VK_TIMEOUT;
5566 }
5567
5568 while(radv_get_current_time() <= timeout) {
5569 for (uint32_t i = 0; i < fenceCount; ++i) {
5570 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5571 return VK_SUCCESS;
5572 }
5573 }
5574 return VK_TIMEOUT;
5575 }
5576
5577 for (uint32_t i = 0; i < fenceCount; ++i) {
5578 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5579 bool expired = false;
5580
5581 struct radv_fence_part *part =
5582 fence->temporary.kind != RADV_FENCE_NONE ?
5583 &fence->temporary : &fence->permanent;
5584
5585 switch (part->kind) {
5586 case RADV_FENCE_NONE:
5587 break;
5588 case RADV_FENCE_WINSYS:
5589 if (!device->ws->is_fence_waitable(part->fence)) {
5590 while (!device->ws->is_fence_waitable(part->fence) &&
5591 radv_get_current_time() <= timeout)
5592 /* Do nothing */;
5593 }
5594
5595 expired = device->ws->fence_wait(device->ws,
5596 part->fence,
5597 true, timeout);
5598 if (!expired)
5599 return VK_TIMEOUT;
5600 break;
5601 case RADV_FENCE_SYNCOBJ:
5602 if (!device->ws->wait_syncobj(device->ws,
5603 &part->syncobj, 1, true,
5604 timeout))
5605 return VK_TIMEOUT;
5606 break;
5607 case RADV_FENCE_WSI: {
5608 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5609 if (result != VK_SUCCESS)
5610 return result;
5611 break;
5612 }
5613 default:
5614 unreachable("Invalid fence type");
5615 }
5616 }
5617
5618 return VK_SUCCESS;
5619 }
5620
5621 VkResult radv_ResetFences(VkDevice _device,
5622 uint32_t fenceCount,
5623 const VkFence *pFences)
5624 {
5625 RADV_FROM_HANDLE(radv_device, device, _device);
5626
5627 for (unsigned i = 0; i < fenceCount; ++i) {
5628 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5629
5630 /* From the Vulkan 1.0.53 spec:
5631 *
5632 * "If any member of pFences currently has its payload
5633 * imported with temporary permanence, that fence’s prior
5634 * permanent payload is irst restored. The remaining
5635 * operations described therefore operate on the restored
5636 * payload."
5637 */
5638 if (fence->temporary.kind != RADV_FENCE_NONE)
5639 radv_destroy_fence_part(device, &fence->temporary);
5640
5641 struct radv_fence_part *part = &fence->permanent;
5642
5643 switch (part->kind) {
5644 case RADV_FENCE_WSI:
5645 device->ws->reset_fence(part->fence);
5646 break;
5647 case RADV_FENCE_SYNCOBJ:
5648 device->ws->reset_syncobj(device->ws, part->syncobj);
5649 break;
5650 default:
5651 unreachable("Invalid fence type");
5652 }
5653 }
5654
5655 return VK_SUCCESS;
5656 }
5657
5658 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5659 {
5660 RADV_FROM_HANDLE(radv_device, device, _device);
5661 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5662
5663 struct radv_fence_part *part =
5664 fence->temporary.kind != RADV_FENCE_NONE ?
5665 &fence->temporary : &fence->permanent;
5666
5667 switch (part->kind) {
5668 case RADV_FENCE_NONE:
5669 break;
5670 case RADV_FENCE_WINSYS:
5671 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5672 return VK_NOT_READY;
5673 break;
5674 case RADV_FENCE_SYNCOBJ: {
5675 bool success = device->ws->wait_syncobj(device->ws,
5676 &part->syncobj, 1, true, 0);
5677 if (!success)
5678 return VK_NOT_READY;
5679 break;
5680 }
5681 case RADV_FENCE_WSI: {
5682 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5683 if (result != VK_SUCCESS) {
5684 if (result == VK_TIMEOUT)
5685 return VK_NOT_READY;
5686 return result;
5687 }
5688 break;
5689 }
5690 default:
5691 unreachable("Invalid fence type");
5692 }
5693
5694 return VK_SUCCESS;
5695 }
5696
5697
5698 // Queue semaphore functions
5699
5700 static void
5701 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5702 {
5703 timeline->highest_signaled = value;
5704 timeline->highest_submitted = value;
5705 list_inithead(&timeline->points);
5706 list_inithead(&timeline->free_points);
5707 list_inithead(&timeline->waiters);
5708 pthread_mutex_init(&timeline->mutex, NULL);
5709 }
5710
5711 static void
5712 radv_destroy_timeline(struct radv_device *device,
5713 struct radv_timeline *timeline)
5714 {
5715 list_for_each_entry_safe(struct radv_timeline_point, point,
5716 &timeline->free_points, list) {
5717 list_del(&point->list);
5718 device->ws->destroy_syncobj(device->ws, point->syncobj);
5719 free(point);
5720 }
5721 list_for_each_entry_safe(struct radv_timeline_point, point,
5722 &timeline->points, list) {
5723 list_del(&point->list);
5724 device->ws->destroy_syncobj(device->ws, point->syncobj);
5725 free(point);
5726 }
5727 pthread_mutex_destroy(&timeline->mutex);
5728 }
5729
5730 static void
5731 radv_timeline_gc_locked(struct radv_device *device,
5732 struct radv_timeline *timeline)
5733 {
5734 list_for_each_entry_safe(struct radv_timeline_point, point,
5735 &timeline->points, list) {
5736 if (point->wait_count || point->value > timeline->highest_submitted)
5737 return;
5738
5739 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5740 timeline->highest_signaled = point->value;
5741 list_del(&point->list);
5742 list_add(&point->list, &timeline->free_points);
5743 }
5744 }
5745 }
5746
5747 static struct radv_timeline_point *
5748 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5749 struct radv_timeline *timeline,
5750 uint64_t p)
5751 {
5752 radv_timeline_gc_locked(device, timeline);
5753
5754 if (p <= timeline->highest_signaled)
5755 return NULL;
5756
5757 list_for_each_entry(struct radv_timeline_point, point,
5758 &timeline->points, list) {
5759 if (point->value >= p) {
5760 ++point->wait_count;
5761 return point;
5762 }
5763 }
5764 return NULL;
5765 }
5766
5767 static struct radv_timeline_point *
5768 radv_timeline_add_point_locked(struct radv_device *device,
5769 struct radv_timeline *timeline,
5770 uint64_t p)
5771 {
5772 radv_timeline_gc_locked(device, timeline);
5773
5774 struct radv_timeline_point *ret = NULL;
5775 struct radv_timeline_point *prev = NULL;
5776 int r;
5777
5778 if (p <= timeline->highest_signaled)
5779 return NULL;
5780
5781 list_for_each_entry(struct radv_timeline_point, point,
5782 &timeline->points, list) {
5783 if (point->value == p) {
5784 return NULL;
5785 }
5786
5787 if (point->value < p)
5788 prev = point;
5789 }
5790
5791 if (list_is_empty(&timeline->free_points)) {
5792 ret = malloc(sizeof(struct radv_timeline_point));
5793 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
5794 if (r) {
5795 free(ret);
5796 return NULL;
5797 }
5798 } else {
5799 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5800 list_del(&ret->list);
5801
5802 device->ws->reset_syncobj(device->ws, ret->syncobj);
5803 }
5804
5805 ret->value = p;
5806 ret->wait_count = 1;
5807
5808 if (prev) {
5809 list_add(&ret->list, &prev->list);
5810 } else {
5811 list_addtail(&ret->list, &timeline->points);
5812 }
5813 return ret;
5814 }
5815
5816
5817 static VkResult
5818 radv_timeline_wait_locked(struct radv_device *device,
5819 struct radv_timeline *timeline,
5820 uint64_t value,
5821 uint64_t abs_timeout)
5822 {
5823 while(timeline->highest_submitted < value) {
5824 struct timespec abstime;
5825 timespec_from_nsec(&abstime, abs_timeout);
5826
5827 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5828
5829 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5830 return VK_TIMEOUT;
5831 }
5832
5833 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5834 if (!point)
5835 return VK_SUCCESS;
5836
5837 pthread_mutex_unlock(&timeline->mutex);
5838
5839 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5840
5841 pthread_mutex_lock(&timeline->mutex);
5842 point->wait_count--;
5843 return success ? VK_SUCCESS : VK_TIMEOUT;
5844 }
5845
5846 static void
5847 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5848 struct list_head *processing_list)
5849 {
5850 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5851 &timeline->waiters, list) {
5852 if (waiter->value > timeline->highest_submitted)
5853 continue;
5854
5855 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
5856 list_del(&waiter->list);
5857 }
5858 }
5859
5860 static
5861 void radv_destroy_semaphore_part(struct radv_device *device,
5862 struct radv_semaphore_part *part)
5863 {
5864 switch(part->kind) {
5865 case RADV_SEMAPHORE_NONE:
5866 break;
5867 case RADV_SEMAPHORE_WINSYS:
5868 device->ws->destroy_sem(part->ws_sem);
5869 break;
5870 case RADV_SEMAPHORE_TIMELINE:
5871 radv_destroy_timeline(device, &part->timeline);
5872 break;
5873 case RADV_SEMAPHORE_SYNCOBJ:
5874 device->ws->destroy_syncobj(device->ws, part->syncobj);
5875 break;
5876 }
5877 part->kind = RADV_SEMAPHORE_NONE;
5878 }
5879
5880 static VkSemaphoreTypeKHR
5881 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5882 {
5883 const VkSemaphoreTypeCreateInfo *type_info =
5884 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
5885
5886 if (!type_info)
5887 return VK_SEMAPHORE_TYPE_BINARY;
5888
5889 if (initial_value)
5890 *initial_value = type_info->initialValue;
5891 return type_info->semaphoreType;
5892 }
5893
5894 static void
5895 radv_destroy_semaphore(struct radv_device *device,
5896 const VkAllocationCallbacks *pAllocator,
5897 struct radv_semaphore *sem)
5898 {
5899 radv_destroy_semaphore_part(device, &sem->temporary);
5900 radv_destroy_semaphore_part(device, &sem->permanent);
5901 vk_object_base_finish(&sem->base);
5902 vk_free2(&device->vk.alloc, pAllocator, sem);
5903 }
5904
5905 VkResult radv_CreateSemaphore(
5906 VkDevice _device,
5907 const VkSemaphoreCreateInfo* pCreateInfo,
5908 const VkAllocationCallbacks* pAllocator,
5909 VkSemaphore* pSemaphore)
5910 {
5911 RADV_FROM_HANDLE(radv_device, device, _device);
5912 const VkExportSemaphoreCreateInfo *export =
5913 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5914 VkExternalSemaphoreHandleTypeFlags handleTypes =
5915 export ? export->handleTypes : 0;
5916 uint64_t initial_value = 0;
5917 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5918
5919 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
5920 sizeof(*sem), 8,
5921 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5922 if (!sem)
5923 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5924
5925 vk_object_base_init(&device->vk, &sem->base,
5926 VK_OBJECT_TYPE_SEMAPHORE);
5927
5928 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5929 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5930
5931 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
5932 radv_create_timeline(&sem->permanent.timeline, initial_value);
5933 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5934 } else if (device->always_use_syncobj || handleTypes) {
5935 assert (device->physical_device->rad_info.has_syncobj);
5936 int ret = device->ws->create_syncobj(device->ws, false,
5937 &sem->permanent.syncobj);
5938 if (ret) {
5939 radv_destroy_semaphore(device, pAllocator, sem);
5940 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5941 }
5942 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5943 } else {
5944 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5945 if (!sem->permanent.ws_sem) {
5946 radv_destroy_semaphore(device, pAllocator, sem);
5947 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5948 }
5949 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5950 }
5951
5952 *pSemaphore = radv_semaphore_to_handle(sem);
5953 return VK_SUCCESS;
5954 }
5955
5956 void radv_DestroySemaphore(
5957 VkDevice _device,
5958 VkSemaphore _semaphore,
5959 const VkAllocationCallbacks* pAllocator)
5960 {
5961 RADV_FROM_HANDLE(radv_device, device, _device);
5962 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5963 if (!_semaphore)
5964 return;
5965
5966 radv_destroy_semaphore(device, pAllocator, sem);
5967 }
5968
5969 VkResult
5970 radv_GetSemaphoreCounterValue(VkDevice _device,
5971 VkSemaphore _semaphore,
5972 uint64_t* pValue)
5973 {
5974 RADV_FROM_HANDLE(radv_device, device, _device);
5975 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5976
5977 struct radv_semaphore_part *part =
5978 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5979
5980 switch (part->kind) {
5981 case RADV_SEMAPHORE_TIMELINE: {
5982 pthread_mutex_lock(&part->timeline.mutex);
5983 radv_timeline_gc_locked(device, &part->timeline);
5984 *pValue = part->timeline.highest_signaled;
5985 pthread_mutex_unlock(&part->timeline.mutex);
5986 return VK_SUCCESS;
5987 }
5988 case RADV_SEMAPHORE_NONE:
5989 case RADV_SEMAPHORE_SYNCOBJ:
5990 case RADV_SEMAPHORE_WINSYS:
5991 unreachable("Invalid semaphore type");
5992 }
5993 unreachable("Unhandled semaphore type");
5994 }
5995
5996
5997 static VkResult
5998 radv_wait_timelines(struct radv_device *device,
5999 const VkSemaphoreWaitInfo* pWaitInfo,
6000 uint64_t abs_timeout)
6001 {
6002 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6003 for (;;) {
6004 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6005 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6006 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6007 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6008 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6009
6010 if (result == VK_SUCCESS)
6011 return VK_SUCCESS;
6012 }
6013 if (radv_get_current_time() > abs_timeout)
6014 return VK_TIMEOUT;
6015 }
6016 }
6017
6018 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6019 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6020 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6021 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6022 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6023
6024 if (result != VK_SUCCESS)
6025 return result;
6026 }
6027 return VK_SUCCESS;
6028 }
6029 VkResult
6030 radv_WaitSemaphores(VkDevice _device,
6031 const VkSemaphoreWaitInfo* pWaitInfo,
6032 uint64_t timeout)
6033 {
6034 RADV_FROM_HANDLE(radv_device, device, _device);
6035 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6036 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6037 }
6038
6039 VkResult
6040 radv_SignalSemaphore(VkDevice _device,
6041 const VkSemaphoreSignalInfo* pSignalInfo)
6042 {
6043 RADV_FROM_HANDLE(radv_device, device, _device);
6044 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6045
6046 struct radv_semaphore_part *part =
6047 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6048
6049 switch(part->kind) {
6050 case RADV_SEMAPHORE_TIMELINE: {
6051 pthread_mutex_lock(&part->timeline.mutex);
6052 radv_timeline_gc_locked(device, &part->timeline);
6053 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6054 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6055
6056 struct list_head processing_list;
6057 list_inithead(&processing_list);
6058 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6059 pthread_mutex_unlock(&part->timeline.mutex);
6060
6061 return radv_process_submissions(&processing_list);
6062 }
6063 case RADV_SEMAPHORE_NONE:
6064 case RADV_SEMAPHORE_SYNCOBJ:
6065 case RADV_SEMAPHORE_WINSYS:
6066 unreachable("Invalid semaphore type");
6067 }
6068 return VK_SUCCESS;
6069 }
6070
6071 static void radv_destroy_event(struct radv_device *device,
6072 const VkAllocationCallbacks* pAllocator,
6073 struct radv_event *event)
6074 {
6075 if (event->bo)
6076 device->ws->buffer_destroy(event->bo);
6077
6078 vk_object_base_finish(&event->base);
6079 vk_free2(&device->vk.alloc, pAllocator, event);
6080 }
6081
6082 VkResult radv_CreateEvent(
6083 VkDevice _device,
6084 const VkEventCreateInfo* pCreateInfo,
6085 const VkAllocationCallbacks* pAllocator,
6086 VkEvent* pEvent)
6087 {
6088 RADV_FROM_HANDLE(radv_device, device, _device);
6089 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6090 sizeof(*event), 8,
6091 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6092
6093 if (!event)
6094 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6095
6096 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6097
6098 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6099 RADEON_DOMAIN_GTT,
6100 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6101 RADV_BO_PRIORITY_FENCE);
6102 if (!event->bo) {
6103 radv_destroy_event(device, pAllocator, event);
6104 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6105 }
6106
6107 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6108 if (!event->map) {
6109 radv_destroy_event(device, pAllocator, event);
6110 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6111 }
6112
6113 *pEvent = radv_event_to_handle(event);
6114
6115 return VK_SUCCESS;
6116 }
6117
6118 void radv_DestroyEvent(
6119 VkDevice _device,
6120 VkEvent _event,
6121 const VkAllocationCallbacks* pAllocator)
6122 {
6123 RADV_FROM_HANDLE(radv_device, device, _device);
6124 RADV_FROM_HANDLE(radv_event, event, _event);
6125
6126 if (!event)
6127 return;
6128
6129 radv_destroy_event(device, pAllocator, event);
6130 }
6131
6132 VkResult radv_GetEventStatus(
6133 VkDevice _device,
6134 VkEvent _event)
6135 {
6136 RADV_FROM_HANDLE(radv_event, event, _event);
6137
6138 if (*event->map == 1)
6139 return VK_EVENT_SET;
6140 return VK_EVENT_RESET;
6141 }
6142
6143 VkResult radv_SetEvent(
6144 VkDevice _device,
6145 VkEvent _event)
6146 {
6147 RADV_FROM_HANDLE(radv_event, event, _event);
6148 *event->map = 1;
6149
6150 return VK_SUCCESS;
6151 }
6152
6153 VkResult radv_ResetEvent(
6154 VkDevice _device,
6155 VkEvent _event)
6156 {
6157 RADV_FROM_HANDLE(radv_event, event, _event);
6158 *event->map = 0;
6159
6160 return VK_SUCCESS;
6161 }
6162
6163 static void
6164 radv_destroy_buffer(struct radv_device *device,
6165 const VkAllocationCallbacks *pAllocator,
6166 struct radv_buffer *buffer)
6167 {
6168 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6169 device->ws->buffer_destroy(buffer->bo);
6170
6171 vk_object_base_finish(&buffer->base);
6172 vk_free2(&device->vk.alloc, pAllocator, buffer);
6173 }
6174
6175 VkResult radv_CreateBuffer(
6176 VkDevice _device,
6177 const VkBufferCreateInfo* pCreateInfo,
6178 const VkAllocationCallbacks* pAllocator,
6179 VkBuffer* pBuffer)
6180 {
6181 RADV_FROM_HANDLE(radv_device, device, _device);
6182 struct radv_buffer *buffer;
6183
6184 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6185 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6186
6187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6188
6189 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6190 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6191 if (buffer == NULL)
6192 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6193
6194 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6195
6196 buffer->size = pCreateInfo->size;
6197 buffer->usage = pCreateInfo->usage;
6198 buffer->bo = NULL;
6199 buffer->offset = 0;
6200 buffer->flags = pCreateInfo->flags;
6201
6202 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6203 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6204
6205 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6206 buffer->bo = device->ws->buffer_create(device->ws,
6207 align64(buffer->size, 4096),
6208 4096, 0, RADEON_FLAG_VIRTUAL,
6209 RADV_BO_PRIORITY_VIRTUAL);
6210 if (!buffer->bo) {
6211 radv_destroy_buffer(device, pAllocator, buffer);
6212 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6213 }
6214 }
6215
6216 *pBuffer = radv_buffer_to_handle(buffer);
6217
6218 return VK_SUCCESS;
6219 }
6220
6221 void radv_DestroyBuffer(
6222 VkDevice _device,
6223 VkBuffer _buffer,
6224 const VkAllocationCallbacks* pAllocator)
6225 {
6226 RADV_FROM_HANDLE(radv_device, device, _device);
6227 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6228
6229 if (!buffer)
6230 return;
6231
6232 radv_destroy_buffer(device, pAllocator, buffer);
6233 }
6234
6235 VkDeviceAddress radv_GetBufferDeviceAddress(
6236 VkDevice device,
6237 const VkBufferDeviceAddressInfo* pInfo)
6238 {
6239 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6240 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6241 }
6242
6243
6244 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6245 const VkBufferDeviceAddressInfo* pInfo)
6246 {
6247 return 0;
6248 }
6249
6250 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6251 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6252 {
6253 return 0;
6254 }
6255
6256 static inline unsigned
6257 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6258 {
6259 if (stencil)
6260 return plane->surface.u.legacy.stencil_tiling_index[level];
6261 else
6262 return plane->surface.u.legacy.tiling_index[level];
6263 }
6264
6265 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6266 {
6267 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6268 }
6269
6270 static uint32_t
6271 radv_init_dcc_control_reg(struct radv_device *device,
6272 struct radv_image_view *iview)
6273 {
6274 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6275 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6276 unsigned max_compressed_block_size;
6277 unsigned independent_128b_blocks;
6278 unsigned independent_64b_blocks;
6279
6280 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6281 return 0;
6282
6283 if (!device->physical_device->rad_info.has_dedicated_vram) {
6284 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6285 * dGPU and 64 for APU because all of our APUs to date use
6286 * DIMMs which have a request granularity size of 64B while all
6287 * other chips have a 32B request size.
6288 */
6289 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6290 }
6291
6292 if (device->physical_device->rad_info.chip_class >= GFX10) {
6293 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6294 independent_64b_blocks = 0;
6295 independent_128b_blocks = 1;
6296 } else {
6297 independent_128b_blocks = 0;
6298
6299 if (iview->image->info.samples > 1) {
6300 if (iview->image->planes[0].surface.bpe == 1)
6301 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6302 else if (iview->image->planes[0].surface.bpe == 2)
6303 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6304 }
6305
6306 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6307 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6308 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6309 /* If this DCC image is potentially going to be used in texture
6310 * fetches, we need some special settings.
6311 */
6312 independent_64b_blocks = 1;
6313 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6314 } else {
6315 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6316 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6317 * big as possible for better compression state.
6318 */
6319 independent_64b_blocks = 0;
6320 max_compressed_block_size = max_uncompressed_block_size;
6321 }
6322 }
6323
6324 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6325 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6326 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6327 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6328 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6329 }
6330
6331 void
6332 radv_initialise_color_surface(struct radv_device *device,
6333 struct radv_color_buffer_info *cb,
6334 struct radv_image_view *iview)
6335 {
6336 const struct vk_format_description *desc;
6337 unsigned ntype, format, swap, endian;
6338 unsigned blend_clamp = 0, blend_bypass = 0;
6339 uint64_t va;
6340 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6341 const struct radeon_surf *surf = &plane->surface;
6342
6343 desc = vk_format_description(iview->vk_format);
6344
6345 memset(cb, 0, sizeof(*cb));
6346
6347 /* Intensity is implemented as Red, so treat it that way. */
6348 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6349
6350 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6351
6352 cb->cb_color_base = va >> 8;
6353
6354 if (device->physical_device->rad_info.chip_class >= GFX9) {
6355 if (device->physical_device->rad_info.chip_class >= GFX10) {
6356 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6357 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6358 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6359 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6360 } else {
6361 struct gfx9_surf_meta_flags meta = {
6362 .rb_aligned = 1,
6363 .pipe_aligned = 1,
6364 };
6365
6366 if (surf->dcc_offset)
6367 meta = surf->u.gfx9.dcc;
6368
6369 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6370 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6371 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6372 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6373 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6374 }
6375
6376 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6377 cb->cb_color_base |= surf->tile_swizzle;
6378 } else {
6379 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6380 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6381
6382 cb->cb_color_base += level_info->offset >> 8;
6383 if (level_info->mode == RADEON_SURF_MODE_2D)
6384 cb->cb_color_base |= surf->tile_swizzle;
6385
6386 pitch_tile_max = level_info->nblk_x / 8 - 1;
6387 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6388 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6389
6390 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6391 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6392 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6393
6394 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6395
6396 if (radv_image_has_fmask(iview->image)) {
6397 if (device->physical_device->rad_info.chip_class >= GFX7)
6398 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6399 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6400 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6401 } else {
6402 /* This must be set for fast clear to work without FMASK. */
6403 if (device->physical_device->rad_info.chip_class >= GFX7)
6404 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6405 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6406 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6407 }
6408 }
6409
6410 /* CMASK variables */
6411 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6412 va += surf->cmask_offset;
6413 cb->cb_color_cmask = va >> 8;
6414
6415 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6416 va += surf->dcc_offset;
6417
6418 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6419 device->physical_device->rad_info.chip_class <= GFX8)
6420 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6421
6422 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6423 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6424
6425 cb->cb_dcc_base = va >> 8;
6426 cb->cb_dcc_base |= dcc_tile_swizzle;
6427
6428 /* GFX10 field has the same base shift as the GFX6 field. */
6429 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6430 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6431 S_028C6C_SLICE_MAX_GFX10(max_slice);
6432
6433 if (iview->image->info.samples > 1) {
6434 unsigned log_samples = util_logbase2(iview->image->info.samples);
6435
6436 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6437 S_028C74_NUM_FRAGMENTS(log_samples);
6438 }
6439
6440 if (radv_image_has_fmask(iview->image)) {
6441 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6442 cb->cb_color_fmask = va >> 8;
6443 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6444 } else {
6445 cb->cb_color_fmask = cb->cb_color_base;
6446 }
6447
6448 ntype = radv_translate_color_numformat(iview->vk_format,
6449 desc,
6450 vk_format_get_first_non_void_channel(iview->vk_format));
6451 format = radv_translate_colorformat(iview->vk_format);
6452 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6453 radv_finishme("Illegal color\n");
6454 swap = radv_translate_colorswap(iview->vk_format, false);
6455 endian = radv_colorformat_endian_swap(format);
6456
6457 /* blend clamp should be set for all NORM/SRGB types */
6458 if (ntype == V_028C70_NUMBER_UNORM ||
6459 ntype == V_028C70_NUMBER_SNORM ||
6460 ntype == V_028C70_NUMBER_SRGB)
6461 blend_clamp = 1;
6462
6463 /* set blend bypass according to docs if SINT/UINT or
6464 8/24 COLOR variants */
6465 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6466 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6467 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6468 blend_clamp = 0;
6469 blend_bypass = 1;
6470 }
6471 #if 0
6472 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6473 (format == V_028C70_COLOR_8 ||
6474 format == V_028C70_COLOR_8_8 ||
6475 format == V_028C70_COLOR_8_8_8_8))
6476 ->color_is_int8 = true;
6477 #endif
6478 cb->cb_color_info = S_028C70_FORMAT(format) |
6479 S_028C70_COMP_SWAP(swap) |
6480 S_028C70_BLEND_CLAMP(blend_clamp) |
6481 S_028C70_BLEND_BYPASS(blend_bypass) |
6482 S_028C70_SIMPLE_FLOAT(1) |
6483 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6484 ntype != V_028C70_NUMBER_SNORM &&
6485 ntype != V_028C70_NUMBER_SRGB &&
6486 format != V_028C70_COLOR_8_24 &&
6487 format != V_028C70_COLOR_24_8) |
6488 S_028C70_NUMBER_TYPE(ntype) |
6489 S_028C70_ENDIAN(endian);
6490 if (radv_image_has_fmask(iview->image)) {
6491 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6492 if (device->physical_device->rad_info.chip_class == GFX6) {
6493 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6494 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6495 }
6496
6497 if (radv_image_is_tc_compat_cmask(iview->image)) {
6498 /* Allow the texture block to read FMASK directly
6499 * without decompressing it. This bit must be cleared
6500 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6501 * otherwise the operation doesn't happen.
6502 */
6503 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6504
6505 /* Set CMASK into a tiling format that allows the
6506 * texture block to read it.
6507 */
6508 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6509 }
6510 }
6511
6512 if (radv_image_has_cmask(iview->image) &&
6513 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6514 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6515
6516 if (radv_dcc_enabled(iview->image, iview->base_mip))
6517 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6518
6519 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6520
6521 /* This must be set for fast clear to work without FMASK. */
6522 if (!radv_image_has_fmask(iview->image) &&
6523 device->physical_device->rad_info.chip_class == GFX6) {
6524 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6525 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6526 }
6527
6528 if (device->physical_device->rad_info.chip_class >= GFX9) {
6529 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6530
6531 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6532 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6533 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6534 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6535
6536 if (device->physical_device->rad_info.chip_class >= GFX10) {
6537 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6538
6539 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6540 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6541 S_028EE0_RESOURCE_LEVEL(1);
6542 } else {
6543 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6544 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6545 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6546 }
6547
6548 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6549 S_028C68_MIP0_HEIGHT(height - 1) |
6550 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6551 }
6552 }
6553
6554 static unsigned
6555 radv_calc_decompress_on_z_planes(struct radv_device *device,
6556 struct radv_image_view *iview)
6557 {
6558 unsigned max_zplanes = 0;
6559
6560 assert(radv_image_is_tc_compat_htile(iview->image));
6561
6562 if (device->physical_device->rad_info.chip_class >= GFX9) {
6563 /* Default value for 32-bit depth surfaces. */
6564 max_zplanes = 4;
6565
6566 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6567 iview->image->info.samples > 1)
6568 max_zplanes = 2;
6569
6570 max_zplanes = max_zplanes + 1;
6571 } else {
6572 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6573 /* Do not enable Z plane compression for 16-bit depth
6574 * surfaces because isn't supported on GFX8. Only
6575 * 32-bit depth surfaces are supported by the hardware.
6576 * This allows to maintain shader compatibility and to
6577 * reduce the number of depth decompressions.
6578 */
6579 max_zplanes = 1;
6580 } else {
6581 if (iview->image->info.samples <= 1)
6582 max_zplanes = 5;
6583 else if (iview->image->info.samples <= 4)
6584 max_zplanes = 3;
6585 else
6586 max_zplanes = 2;
6587 }
6588 }
6589
6590 return max_zplanes;
6591 }
6592
6593 void
6594 radv_initialise_ds_surface(struct radv_device *device,
6595 struct radv_ds_buffer_info *ds,
6596 struct radv_image_view *iview)
6597 {
6598 unsigned level = iview->base_mip;
6599 unsigned format, stencil_format;
6600 uint64_t va, s_offs, z_offs;
6601 bool stencil_only = false;
6602 const struct radv_image_plane *plane = &iview->image->planes[0];
6603 const struct radeon_surf *surf = &plane->surface;
6604
6605 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6606
6607 memset(ds, 0, sizeof(*ds));
6608 switch (iview->image->vk_format) {
6609 case VK_FORMAT_D24_UNORM_S8_UINT:
6610 case VK_FORMAT_X8_D24_UNORM_PACK32:
6611 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6612 ds->offset_scale = 2.0f;
6613 break;
6614 case VK_FORMAT_D16_UNORM:
6615 case VK_FORMAT_D16_UNORM_S8_UINT:
6616 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6617 ds->offset_scale = 4.0f;
6618 break;
6619 case VK_FORMAT_D32_SFLOAT:
6620 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6621 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6622 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6623 ds->offset_scale = 1.0f;
6624 break;
6625 case VK_FORMAT_S8_UINT:
6626 stencil_only = true;
6627 break;
6628 default:
6629 break;
6630 }
6631
6632 format = radv_translate_dbformat(iview->image->vk_format);
6633 stencil_format = surf->has_stencil ?
6634 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6635
6636 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6637 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6638 S_028008_SLICE_MAX(max_slice);
6639 if (device->physical_device->rad_info.chip_class >= GFX10) {
6640 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6641 S_028008_SLICE_MAX_HI(max_slice >> 11);
6642 }
6643
6644 ds->db_htile_data_base = 0;
6645 ds->db_htile_surface = 0;
6646
6647 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6648 s_offs = z_offs = va;
6649
6650 if (device->physical_device->rad_info.chip_class >= GFX9) {
6651 assert(surf->u.gfx9.surf_offset == 0);
6652 s_offs += surf->u.gfx9.stencil_offset;
6653
6654 ds->db_z_info = S_028038_FORMAT(format) |
6655 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6656 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6657 S_028038_MAXMIP(iview->image->info.levels - 1) |
6658 S_028038_ZRANGE_PRECISION(1);
6659 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6660 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6661
6662 if (device->physical_device->rad_info.chip_class == GFX9) {
6663 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6664 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6665 }
6666
6667 ds->db_depth_view |= S_028008_MIPID(level);
6668 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6669 S_02801C_Y_MAX(iview->image->info.height - 1);
6670
6671 if (radv_htile_enabled(iview->image, level)) {
6672 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6673
6674 if (radv_image_is_tc_compat_htile(iview->image)) {
6675 unsigned max_zplanes =
6676 radv_calc_decompress_on_z_planes(device, iview);
6677
6678 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6679
6680 if (device->physical_device->rad_info.chip_class >= GFX10) {
6681 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6682 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6683 } else {
6684 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6685 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6686 }
6687 }
6688
6689 if (!surf->has_stencil)
6690 /* Use all of the htile_buffer for depth if there's no stencil. */
6691 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6692 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6693 surf->htile_offset;
6694 ds->db_htile_data_base = va >> 8;
6695 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6696 S_028ABC_PIPE_ALIGNED(1);
6697
6698 if (device->physical_device->rad_info.chip_class == GFX9) {
6699 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6700 }
6701 }
6702 } else {
6703 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6704
6705 if (stencil_only)
6706 level_info = &surf->u.legacy.stencil_level[level];
6707
6708 z_offs += surf->u.legacy.level[level].offset;
6709 s_offs += surf->u.legacy.stencil_level[level].offset;
6710
6711 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6712 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6713 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6714
6715 if (iview->image->info.samples > 1)
6716 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6717
6718 if (device->physical_device->rad_info.chip_class >= GFX7) {
6719 struct radeon_info *info = &device->physical_device->rad_info;
6720 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6721 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6722 unsigned macro_index = surf->u.legacy.macro_tile_index;
6723 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6724 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6725 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6726
6727 if (stencil_only)
6728 tile_mode = stencil_tile_mode;
6729
6730 ds->db_depth_info |=
6731 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6732 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6733 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6734 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6735 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6736 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6737 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6738 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6739 } else {
6740 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6741 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6742 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6743 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6744 if (stencil_only)
6745 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6746 }
6747
6748 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6749 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6750 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6751
6752 if (radv_htile_enabled(iview->image, level)) {
6753 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6754
6755 if (!surf->has_stencil &&
6756 !radv_image_is_tc_compat_htile(iview->image))
6757 /* Use all of the htile_buffer for depth if there's no stencil. */
6758 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6759
6760 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6761 surf->htile_offset;
6762 ds->db_htile_data_base = va >> 8;
6763 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6764
6765 if (radv_image_is_tc_compat_htile(iview->image)) {
6766 unsigned max_zplanes =
6767 radv_calc_decompress_on_z_planes(device, iview);
6768
6769 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6770 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6771 }
6772 }
6773 }
6774
6775 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6776 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6777 }
6778
6779 VkResult radv_CreateFramebuffer(
6780 VkDevice _device,
6781 const VkFramebufferCreateInfo* pCreateInfo,
6782 const VkAllocationCallbacks* pAllocator,
6783 VkFramebuffer* pFramebuffer)
6784 {
6785 RADV_FROM_HANDLE(radv_device, device, _device);
6786 struct radv_framebuffer *framebuffer;
6787 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6788 vk_find_struct_const(pCreateInfo->pNext,
6789 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6790
6791 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6792
6793 size_t size = sizeof(*framebuffer);
6794 if (!imageless_create_info)
6795 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6796 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
6797 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6798 if (framebuffer == NULL)
6799 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6800
6801 vk_object_base_init(&device->vk, &framebuffer->base,
6802 VK_OBJECT_TYPE_FRAMEBUFFER);
6803
6804 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6805 framebuffer->width = pCreateInfo->width;
6806 framebuffer->height = pCreateInfo->height;
6807 framebuffer->layers = pCreateInfo->layers;
6808 if (imageless_create_info) {
6809 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6810 const VkFramebufferAttachmentImageInfo *attachment =
6811 imageless_create_info->pAttachmentImageInfos + i;
6812 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6813 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6814 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6815 }
6816 } else {
6817 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6818 VkImageView _iview = pCreateInfo->pAttachments[i];
6819 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6820 framebuffer->attachments[i] = iview;
6821 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6822 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6823 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6824 }
6825 }
6826
6827 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6828 return VK_SUCCESS;
6829 }
6830
6831 void radv_DestroyFramebuffer(
6832 VkDevice _device,
6833 VkFramebuffer _fb,
6834 const VkAllocationCallbacks* pAllocator)
6835 {
6836 RADV_FROM_HANDLE(radv_device, device, _device);
6837 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6838
6839 if (!fb)
6840 return;
6841 vk_object_base_finish(&fb->base);
6842 vk_free2(&device->vk.alloc, pAllocator, fb);
6843 }
6844
6845 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6846 {
6847 switch (address_mode) {
6848 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6849 return V_008F30_SQ_TEX_WRAP;
6850 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6851 return V_008F30_SQ_TEX_MIRROR;
6852 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6853 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6854 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6855 return V_008F30_SQ_TEX_CLAMP_BORDER;
6856 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6857 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6858 default:
6859 unreachable("illegal tex wrap mode");
6860 break;
6861 }
6862 }
6863
6864 static unsigned
6865 radv_tex_compare(VkCompareOp op)
6866 {
6867 switch (op) {
6868 case VK_COMPARE_OP_NEVER:
6869 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6870 case VK_COMPARE_OP_LESS:
6871 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6872 case VK_COMPARE_OP_EQUAL:
6873 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6874 case VK_COMPARE_OP_LESS_OR_EQUAL:
6875 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6876 case VK_COMPARE_OP_GREATER:
6877 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6878 case VK_COMPARE_OP_NOT_EQUAL:
6879 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6880 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6881 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6882 case VK_COMPARE_OP_ALWAYS:
6883 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6884 default:
6885 unreachable("illegal compare mode");
6886 break;
6887 }
6888 }
6889
6890 static unsigned
6891 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6892 {
6893 switch (filter) {
6894 case VK_FILTER_NEAREST:
6895 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6896 V_008F38_SQ_TEX_XY_FILTER_POINT);
6897 case VK_FILTER_LINEAR:
6898 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6899 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6900 case VK_FILTER_CUBIC_IMG:
6901 default:
6902 fprintf(stderr, "illegal texture filter");
6903 return 0;
6904 }
6905 }
6906
6907 static unsigned
6908 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6909 {
6910 switch (mode) {
6911 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6912 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6913 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6914 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6915 default:
6916 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6917 }
6918 }
6919
6920 static unsigned
6921 radv_tex_bordercolor(VkBorderColor bcolor)
6922 {
6923 switch (bcolor) {
6924 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6925 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6926 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6927 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6928 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6929 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6930 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6931 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6932 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6933 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
6934 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
6935 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
6936 default:
6937 break;
6938 }
6939 return 0;
6940 }
6941
6942 static unsigned
6943 radv_tex_aniso_filter(unsigned filter)
6944 {
6945 if (filter < 2)
6946 return 0;
6947 if (filter < 4)
6948 return 1;
6949 if (filter < 8)
6950 return 2;
6951 if (filter < 16)
6952 return 3;
6953 return 4;
6954 }
6955
6956 static unsigned
6957 radv_tex_filter_mode(VkSamplerReductionMode mode)
6958 {
6959 switch (mode) {
6960 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6961 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6962 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6963 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6964 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6965 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6966 default:
6967 break;
6968 }
6969 return 0;
6970 }
6971
6972 static uint32_t
6973 radv_get_max_anisotropy(struct radv_device *device,
6974 const VkSamplerCreateInfo *pCreateInfo)
6975 {
6976 if (device->force_aniso >= 0)
6977 return device->force_aniso;
6978
6979 if (pCreateInfo->anisotropyEnable &&
6980 pCreateInfo->maxAnisotropy > 1.0f)
6981 return (uint32_t)pCreateInfo->maxAnisotropy;
6982
6983 return 0;
6984 }
6985
6986 static inline int S_FIXED(float value, unsigned frac_bits)
6987 {
6988 return value * (1 << frac_bits);
6989 }
6990
6991 static uint32_t radv_register_border_color(struct radv_device *device,
6992 VkClearColorValue value)
6993 {
6994 uint32_t slot;
6995
6996 pthread_mutex_lock(&device->border_color_data.mutex);
6997
6998 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
6999 if (!device->border_color_data.used[slot]) {
7000 /* Copy to the GPU wrt endian-ness. */
7001 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7002 &value,
7003 sizeof(VkClearColorValue));
7004
7005 device->border_color_data.used[slot] = true;
7006 break;
7007 }
7008 }
7009
7010 pthread_mutex_unlock(&device->border_color_data.mutex);
7011
7012 return slot;
7013 }
7014
7015 static void radv_unregister_border_color(struct radv_device *device,
7016 uint32_t slot)
7017 {
7018 pthread_mutex_lock(&device->border_color_data.mutex);
7019
7020 device->border_color_data.used[slot] = false;
7021
7022 pthread_mutex_unlock(&device->border_color_data.mutex);
7023 }
7024
7025 static void
7026 radv_init_sampler(struct radv_device *device,
7027 struct radv_sampler *sampler,
7028 const VkSamplerCreateInfo *pCreateInfo)
7029 {
7030 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7031 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7032 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7033 device->physical_device->rad_info.chip_class == GFX9;
7034 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7035 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7036 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7037 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7038 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7039 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7040 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7041 uint32_t border_color_ptr;
7042
7043 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7044 vk_find_struct_const(pCreateInfo->pNext,
7045 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7046 if (sampler_reduction)
7047 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7048
7049 if (pCreateInfo->compareEnable)
7050 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7051
7052 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7053
7054 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7055 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7056 vk_find_struct_const(pCreateInfo->pNext,
7057 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7058
7059 assert(custom_border_color);
7060
7061 sampler->border_color_slot =
7062 radv_register_border_color(device, custom_border_color->customBorderColor);
7063
7064 /* Did we fail to find a slot? */
7065 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7066 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7067 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7068 }
7069 }
7070
7071 /* If we don't have a custom color, set the ptr to 0 */
7072 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7073 ? sampler->border_color_slot
7074 : 0;
7075
7076 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7077 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7078 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7079 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7080 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7081 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7082 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7083 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7084 S_008F30_DISABLE_CUBE_WRAP(0) |
7085 S_008F30_COMPAT_MODE(compat_mode) |
7086 S_008F30_FILTER_MODE(filter_mode) |
7087 S_008F30_TRUNC_COORD(trunc_coord));
7088 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7089 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7090 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7091 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7092 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7093 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7094 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7095 S_008F38_MIP_POINT_PRECLAMP(0));
7096 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7097 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7098
7099 if (device->physical_device->rad_info.chip_class >= GFX10) {
7100 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7101 } else {
7102 sampler->state[2] |=
7103 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7104 S_008F38_FILTER_PREC_FIX(1) |
7105 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7106 }
7107 }
7108
7109 VkResult radv_CreateSampler(
7110 VkDevice _device,
7111 const VkSamplerCreateInfo* pCreateInfo,
7112 const VkAllocationCallbacks* pAllocator,
7113 VkSampler* pSampler)
7114 {
7115 RADV_FROM_HANDLE(radv_device, device, _device);
7116 struct radv_sampler *sampler;
7117
7118 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7119 vk_find_struct_const(pCreateInfo->pNext,
7120 SAMPLER_YCBCR_CONVERSION_INFO);
7121
7122 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7123
7124 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7125 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7126 if (!sampler)
7127 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7128
7129 vk_object_base_init(&device->vk, &sampler->base,
7130 VK_OBJECT_TYPE_SAMPLER);
7131
7132 radv_init_sampler(device, sampler, pCreateInfo);
7133
7134 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7135 *pSampler = radv_sampler_to_handle(sampler);
7136
7137 return VK_SUCCESS;
7138 }
7139
7140 void radv_DestroySampler(
7141 VkDevice _device,
7142 VkSampler _sampler,
7143 const VkAllocationCallbacks* pAllocator)
7144 {
7145 RADV_FROM_HANDLE(radv_device, device, _device);
7146 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7147
7148 if (!sampler)
7149 return;
7150
7151 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7152 radv_unregister_border_color(device, sampler->border_color_slot);
7153
7154 vk_object_base_finish(&sampler->base);
7155 vk_free2(&device->vk.alloc, pAllocator, sampler);
7156 }
7157
7158 /* vk_icd.h does not declare this function, so we declare it here to
7159 * suppress Wmissing-prototypes.
7160 */
7161 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7162 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7163
7164 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7165 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7166 {
7167 /* For the full details on loader interface versioning, see
7168 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7169 * What follows is a condensed summary, to help you navigate the large and
7170 * confusing official doc.
7171 *
7172 * - Loader interface v0 is incompatible with later versions. We don't
7173 * support it.
7174 *
7175 * - In loader interface v1:
7176 * - The first ICD entrypoint called by the loader is
7177 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7178 * entrypoint.
7179 * - The ICD must statically expose no other Vulkan symbol unless it is
7180 * linked with -Bsymbolic.
7181 * - Each dispatchable Vulkan handle created by the ICD must be
7182 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7183 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7184 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7185 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7186 * such loader-managed surfaces.
7187 *
7188 * - Loader interface v2 differs from v1 in:
7189 * - The first ICD entrypoint called by the loader is
7190 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7191 * statically expose this entrypoint.
7192 *
7193 * - Loader interface v3 differs from v2 in:
7194 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7195 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7196 * because the loader no longer does so.
7197 */
7198 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7199 return VK_SUCCESS;
7200 }
7201
7202 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7203 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7204 int *pFD)
7205 {
7206 RADV_FROM_HANDLE(radv_device, device, _device);
7207 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7208
7209 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7210
7211 /* At the moment, we support only the below handle types. */
7212 assert(pGetFdInfo->handleType ==
7213 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7214 pGetFdInfo->handleType ==
7215 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7216
7217 bool ret = radv_get_memory_fd(device, memory, pFD);
7218 if (ret == false)
7219 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7220 return VK_SUCCESS;
7221 }
7222
7223 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7224 enum radeon_bo_domain domains,
7225 enum radeon_bo_flag flags,
7226 enum radeon_bo_flag ignore_flags)
7227 {
7228 /* Don't count GTT/CPU as relevant:
7229 *
7230 * - We're not fully consistent between the two.
7231 * - Sometimes VRAM gets VRAM|GTT.
7232 */
7233 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7234 RADEON_DOMAIN_GDS |
7235 RADEON_DOMAIN_OA;
7236 uint32_t bits = 0;
7237 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7238 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7239 continue;
7240
7241 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7242 continue;
7243
7244 bits |= 1u << i;
7245 }
7246
7247 return bits;
7248 }
7249
7250 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7251 enum radeon_bo_domain domains,
7252 enum radeon_bo_flag flags)
7253 {
7254 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7255 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7256
7257 if (!bits) {
7258 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7259 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7260 }
7261
7262 return bits;
7263 }
7264 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7265 VkExternalMemoryHandleTypeFlagBits handleType,
7266 int fd,
7267 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7268 {
7269 RADV_FROM_HANDLE(radv_device, device, _device);
7270
7271 switch (handleType) {
7272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7273 enum radeon_bo_domain domains;
7274 enum radeon_bo_flag flags;
7275 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7276 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7277
7278 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7279 return VK_SUCCESS;
7280 }
7281 default:
7282 /* The valid usage section for this function says:
7283 *
7284 * "handleType must not be one of the handle types defined as
7285 * opaque."
7286 *
7287 * So opaque handle types fall into the default "unsupported" case.
7288 */
7289 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7290 }
7291 }
7292
7293 static VkResult radv_import_opaque_fd(struct radv_device *device,
7294 int fd,
7295 uint32_t *syncobj)
7296 {
7297 uint32_t syncobj_handle = 0;
7298 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7299 if (ret != 0)
7300 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7301
7302 if (*syncobj)
7303 device->ws->destroy_syncobj(device->ws, *syncobj);
7304
7305 *syncobj = syncobj_handle;
7306 close(fd);
7307
7308 return VK_SUCCESS;
7309 }
7310
7311 static VkResult radv_import_sync_fd(struct radv_device *device,
7312 int fd,
7313 uint32_t *syncobj)
7314 {
7315 /* If we create a syncobj we do it locally so that if we have an error, we don't
7316 * leave a syncobj in an undetermined state in the fence. */
7317 uint32_t syncobj_handle = *syncobj;
7318 if (!syncobj_handle) {
7319 bool create_signaled = fd == -1 ? true : false;
7320
7321 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7322 &syncobj_handle);
7323 if (ret) {
7324 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7325 }
7326 } else {
7327 if (fd == -1)
7328 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7329 }
7330
7331 if (fd != -1) {
7332 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7333 if (ret)
7334 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7335 close(fd);
7336 }
7337
7338 *syncobj = syncobj_handle;
7339
7340 return VK_SUCCESS;
7341 }
7342
7343 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7344 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7345 {
7346 RADV_FROM_HANDLE(radv_device, device, _device);
7347 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7348 VkResult result;
7349 struct radv_semaphore_part *dst = NULL;
7350
7351 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7352 dst = &sem->temporary;
7353 } else {
7354 dst = &sem->permanent;
7355 }
7356
7357 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7358
7359 switch(pImportSemaphoreFdInfo->handleType) {
7360 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7361 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7362 break;
7363 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7364 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7365 break;
7366 default:
7367 unreachable("Unhandled semaphore handle type");
7368 }
7369
7370 if (result == VK_SUCCESS) {
7371 dst->syncobj = syncobj;
7372 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7373 }
7374
7375 return result;
7376 }
7377
7378 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7379 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7380 int *pFd)
7381 {
7382 RADV_FROM_HANDLE(radv_device, device, _device);
7383 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7384 int ret;
7385 uint32_t syncobj_handle;
7386
7387 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7388 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7389 syncobj_handle = sem->temporary.syncobj;
7390 } else {
7391 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7392 syncobj_handle = sem->permanent.syncobj;
7393 }
7394
7395 switch(pGetFdInfo->handleType) {
7396 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7397 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7398 if (ret)
7399 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7400 break;
7401 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7402 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7403 if (ret)
7404 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7405
7406 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7407 radv_destroy_semaphore_part(device, &sem->temporary);
7408 } else {
7409 device->ws->reset_syncobj(device->ws, syncobj_handle);
7410 }
7411 break;
7412 default:
7413 unreachable("Unhandled semaphore handle type");
7414 }
7415
7416 return VK_SUCCESS;
7417 }
7418
7419 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7420 VkPhysicalDevice physicalDevice,
7421 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7422 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7423 {
7424 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7425 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7426
7427 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7428 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7429 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7430 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7431
7432 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7433 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7434 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7435 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7436 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7437 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7438 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7439 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7440 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7441 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7442 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7443 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7444 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7445 } else {
7446 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7447 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7448 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7449 }
7450 }
7451
7452 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7453 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7454 {
7455 RADV_FROM_HANDLE(radv_device, device, _device);
7456 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7457 struct radv_fence_part *dst = NULL;
7458 VkResult result;
7459
7460 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7461 dst = &fence->temporary;
7462 } else {
7463 dst = &fence->permanent;
7464 }
7465
7466 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7467
7468 switch(pImportFenceFdInfo->handleType) {
7469 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7470 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7471 break;
7472 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7473 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7474 break;
7475 default:
7476 unreachable("Unhandled fence handle type");
7477 }
7478
7479 if (result == VK_SUCCESS) {
7480 dst->syncobj = syncobj;
7481 dst->kind = RADV_FENCE_SYNCOBJ;
7482 }
7483
7484 return result;
7485 }
7486
7487 VkResult radv_GetFenceFdKHR(VkDevice _device,
7488 const VkFenceGetFdInfoKHR *pGetFdInfo,
7489 int *pFd)
7490 {
7491 RADV_FROM_HANDLE(radv_device, device, _device);
7492 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7493 int ret;
7494
7495 struct radv_fence_part *part =
7496 fence->temporary.kind != RADV_FENCE_NONE ?
7497 &fence->temporary : &fence->permanent;
7498
7499 switch(pGetFdInfo->handleType) {
7500 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7501 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7502 if (ret)
7503 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7504 break;
7505 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7506 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7507 part->syncobj, pFd);
7508 if (ret)
7509 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7510
7511 if (part == &fence->temporary) {
7512 radv_destroy_fence_part(device, part);
7513 } else {
7514 device->ws->reset_syncobj(device->ws, part->syncobj);
7515 }
7516 break;
7517 default:
7518 unreachable("Unhandled fence handle type");
7519 }
7520
7521 return VK_SUCCESS;
7522 }
7523
7524 void radv_GetPhysicalDeviceExternalFenceProperties(
7525 VkPhysicalDevice physicalDevice,
7526 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7527 VkExternalFenceProperties *pExternalFenceProperties)
7528 {
7529 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7530
7531 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7532 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7533 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7534 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7535 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7536 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7537 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7538 } else {
7539 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7540 pExternalFenceProperties->compatibleHandleTypes = 0;
7541 pExternalFenceProperties->externalFenceFeatures = 0;
7542 }
7543 }
7544
7545 VkResult
7546 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7547 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7548 const VkAllocationCallbacks* pAllocator,
7549 VkDebugReportCallbackEXT* pCallback)
7550 {
7551 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7552 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7553 pCreateInfo, pAllocator, &instance->alloc,
7554 pCallback);
7555 }
7556
7557 void
7558 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7559 VkDebugReportCallbackEXT _callback,
7560 const VkAllocationCallbacks* pAllocator)
7561 {
7562 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7563 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7564 _callback, pAllocator, &instance->alloc);
7565 }
7566
7567 void
7568 radv_DebugReportMessageEXT(VkInstance _instance,
7569 VkDebugReportFlagsEXT flags,
7570 VkDebugReportObjectTypeEXT objectType,
7571 uint64_t object,
7572 size_t location,
7573 int32_t messageCode,
7574 const char* pLayerPrefix,
7575 const char* pMessage)
7576 {
7577 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7578 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7579 object, location, messageCode, pLayerPrefix, pMessage);
7580 }
7581
7582 void
7583 radv_GetDeviceGroupPeerMemoryFeatures(
7584 VkDevice device,
7585 uint32_t heapIndex,
7586 uint32_t localDeviceIndex,
7587 uint32_t remoteDeviceIndex,
7588 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7589 {
7590 assert(localDeviceIndex == remoteDeviceIndex);
7591
7592 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7593 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7594 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7595 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7596 }
7597
7598 static const VkTimeDomainEXT radv_time_domains[] = {
7599 VK_TIME_DOMAIN_DEVICE_EXT,
7600 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7601 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7602 };
7603
7604 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7605 VkPhysicalDevice physicalDevice,
7606 uint32_t *pTimeDomainCount,
7607 VkTimeDomainEXT *pTimeDomains)
7608 {
7609 int d;
7610 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7611
7612 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7613 vk_outarray_append(&out, i) {
7614 *i = radv_time_domains[d];
7615 }
7616 }
7617
7618 return vk_outarray_status(&out);
7619 }
7620
7621 static uint64_t
7622 radv_clock_gettime(clockid_t clock_id)
7623 {
7624 struct timespec current;
7625 int ret;
7626
7627 ret = clock_gettime(clock_id, &current);
7628 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7629 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7630 if (ret < 0)
7631 return 0;
7632
7633 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7634 }
7635
7636 VkResult radv_GetCalibratedTimestampsEXT(
7637 VkDevice _device,
7638 uint32_t timestampCount,
7639 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7640 uint64_t *pTimestamps,
7641 uint64_t *pMaxDeviation)
7642 {
7643 RADV_FROM_HANDLE(radv_device, device, _device);
7644 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7645 int d;
7646 uint64_t begin, end;
7647 uint64_t max_clock_period = 0;
7648
7649 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7650
7651 for (d = 0; d < timestampCount; d++) {
7652 switch (pTimestampInfos[d].timeDomain) {
7653 case VK_TIME_DOMAIN_DEVICE_EXT:
7654 pTimestamps[d] = device->ws->query_value(device->ws,
7655 RADEON_TIMESTAMP);
7656 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7657 max_clock_period = MAX2(max_clock_period, device_period);
7658 break;
7659 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7660 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7661 max_clock_period = MAX2(max_clock_period, 1);
7662 break;
7663
7664 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7665 pTimestamps[d] = begin;
7666 break;
7667 default:
7668 pTimestamps[d] = 0;
7669 break;
7670 }
7671 }
7672
7673 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7674
7675 /*
7676 * The maximum deviation is the sum of the interval over which we
7677 * perform the sampling and the maximum period of any sampled
7678 * clock. That's because the maximum skew between any two sampled
7679 * clock edges is when the sampled clock with the largest period is
7680 * sampled at the end of that period but right at the beginning of the
7681 * sampling interval and some other clock is sampled right at the
7682 * begining of its sampling period and right at the end of the
7683 * sampling interval. Let's assume the GPU has the longest clock
7684 * period and that the application is sampling GPU and monotonic:
7685 *
7686 * s e
7687 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7688 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7689 *
7690 * g
7691 * 0 1 2 3
7692 * GPU -----_____-----_____-----_____-----_____
7693 *
7694 * m
7695 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7696 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7697 *
7698 * Interval <----------------->
7699 * Deviation <-------------------------->
7700 *
7701 * s = read(raw) 2
7702 * g = read(GPU) 1
7703 * m = read(monotonic) 2
7704 * e = read(raw) b
7705 *
7706 * We round the sample interval up by one tick to cover sampling error
7707 * in the interval clock
7708 */
7709
7710 uint64_t sample_interval = end - begin + 1;
7711
7712 *pMaxDeviation = sample_interval + max_clock_period;
7713
7714 return VK_SUCCESS;
7715 }
7716
7717 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7718 VkPhysicalDevice physicalDevice,
7719 VkSampleCountFlagBits samples,
7720 VkMultisamplePropertiesEXT* pMultisampleProperties)
7721 {
7722 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7723 VK_SAMPLE_COUNT_4_BIT |
7724 VK_SAMPLE_COUNT_8_BIT)) {
7725 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7726 } else {
7727 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7728 }
7729 }
7730
7731 VkResult radv_CreatePrivateDataSlotEXT(
7732 VkDevice _device,
7733 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
7734 const VkAllocationCallbacks* pAllocator,
7735 VkPrivateDataSlotEXT* pPrivateDataSlot)
7736 {
7737 RADV_FROM_HANDLE(radv_device, device, _device);
7738 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
7739 pPrivateDataSlot);
7740 }
7741
7742 void radv_DestroyPrivateDataSlotEXT(
7743 VkDevice _device,
7744 VkPrivateDataSlotEXT privateDataSlot,
7745 const VkAllocationCallbacks* pAllocator)
7746 {
7747 RADV_FROM_HANDLE(radv_device, device, _device);
7748 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
7749 }
7750
7751 VkResult radv_SetPrivateDataEXT(
7752 VkDevice _device,
7753 VkObjectType objectType,
7754 uint64_t objectHandle,
7755 VkPrivateDataSlotEXT privateDataSlot,
7756 uint64_t data)
7757 {
7758 RADV_FROM_HANDLE(radv_device, device, _device);
7759 return vk_object_base_set_private_data(&device->vk, objectType,
7760 objectHandle, privateDataSlot,
7761 data);
7762 }
7763
7764 void radv_GetPrivateDataEXT(
7765 VkDevice _device,
7766 VkObjectType objectType,
7767 uint64_t objectHandle,
7768 VkPrivateDataSlotEXT privateDataSlot,
7769 uint64_t* pData)
7770 {
7771 RADV_FROM_HANDLE(radv_device, device, _device);
7772 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
7773 privateDataSlot, pData);
7774 }