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radv: Don't use a separate can_expclear.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 {
88 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
89 .specVersion = 1,
90 },
91 };
92
93 static const VkExtensionProperties common_device_extensions[] = {
94 {
95 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
100 .specVersion = 1,
101 },
102 {
103 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
116 .specVersion = 68,
117 },
118 {
119 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 {
123 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
124 .specVersion = 1,
125 },
126 {
127 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
128 .specVersion = 1,
129 },
130 };
131
132 static VkResult
133 radv_extensions_register(struct radv_instance *instance,
134 struct radv_extensions *extensions,
135 const VkExtensionProperties *new_ext,
136 uint32_t num_ext)
137 {
138 size_t new_size;
139 VkExtensionProperties *new_ptr;
140
141 assert(new_ext && num_ext > 0);
142
143 if (!new_ext)
144 return VK_ERROR_INITIALIZATION_FAILED;
145
146 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
147 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
148 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
149
150 /* Old array continues to be valid, update nothing */
151 if (!new_ptr)
152 return VK_ERROR_OUT_OF_HOST_MEMORY;
153
154 memcpy(&new_ptr[extensions->num_ext], new_ext,
155 num_ext * sizeof(VkExtensionProperties));
156 extensions->ext_array = new_ptr;
157 extensions->num_ext += num_ext;
158
159 return VK_SUCCESS;
160 }
161
162 static void
163 radv_extensions_finish(struct radv_instance *instance,
164 struct radv_extensions *extensions)
165 {
166 assert(extensions);
167
168 if (!extensions)
169 radv_loge("Attemted to free invalid extension struct\n");
170
171 if (extensions->ext_array)
172 vk_free(&instance->alloc, extensions->ext_array);
173 }
174
175 static bool
176 is_extension_enabled(const VkExtensionProperties *extensions,
177 size_t num_ext,
178 const char *name)
179 {
180 assert(extensions && name);
181
182 for (uint32_t i = 0; i < num_ext; i++) {
183 if (strcmp(name, extensions[i].extensionName) == 0)
184 return true;
185 }
186
187 return false;
188 }
189
190 static VkResult
191 radv_physical_device_init(struct radv_physical_device *device,
192 struct radv_instance *instance,
193 const char *path)
194 {
195 VkResult result;
196 drmVersionPtr version;
197 int fd;
198
199 fd = open(path, O_RDWR | O_CLOEXEC);
200 if (fd < 0)
201 return VK_ERROR_INCOMPATIBLE_DRIVER;
202
203 version = drmGetVersion(fd);
204 if (!version) {
205 close(fd);
206 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
207 "failed to get version %s: %m", path);
208 }
209
210 if (strcmp(version->name, "amdgpu")) {
211 drmFreeVersion(version);
212 close(fd);
213 return VK_ERROR_INCOMPATIBLE_DRIVER;
214 }
215 drmFreeVersion(version);
216
217 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 device->instance = instance;
219 assert(strlen(path) < ARRAY_SIZE(device->path));
220 strncpy(device->path, path, ARRAY_SIZE(device->path));
221
222 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
223 if (!device->ws) {
224 result = VK_ERROR_INCOMPATIBLE_DRIVER;
225 goto fail;
226 }
227
228 device->local_fd = fd;
229 device->ws->query_info(device->ws, &device->rad_info);
230 result = radv_init_wsi(device);
231 if (result != VK_SUCCESS) {
232 device->ws->destroy(device->ws);
233 goto fail;
234 }
235
236 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
237 radv_finish_wsi(device);
238 device->ws->destroy(device->ws);
239 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
240 "cannot generate UUID");
241 goto fail;
242 }
243
244 result = radv_extensions_register(instance,
245 &device->extensions,
246 common_device_extensions,
247 ARRAY_SIZE(common_device_extensions));
248 if (result != VK_SUCCESS)
249 goto fail;
250
251 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 device->name = device->rad_info.name;
253
254 return VK_SUCCESS;
255
256 fail:
257 close(fd);
258 return result;
259 }
260
261 static void
262 radv_physical_device_finish(struct radv_physical_device *device)
263 {
264 radv_extensions_finish(device->instance, &device->extensions);
265 radv_finish_wsi(device);
266 device->ws->destroy(device->ws);
267 close(device->local_fd);
268 }
269
270
271 static void *
272 default_alloc_func(void *pUserData, size_t size, size_t align,
273 VkSystemAllocationScope allocationScope)
274 {
275 return malloc(size);
276 }
277
278 static void *
279 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
280 size_t align, VkSystemAllocationScope allocationScope)
281 {
282 return realloc(pOriginal, size);
283 }
284
285 static void
286 default_free_func(void *pUserData, void *pMemory)
287 {
288 free(pMemory);
289 }
290
291 static const VkAllocationCallbacks default_alloc = {
292 .pUserData = NULL,
293 .pfnAllocation = default_alloc_func,
294 .pfnReallocation = default_realloc_func,
295 .pfnFree = default_free_func,
296 };
297
298 static const struct debug_control radv_debug_options[] = {
299 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
300 {"nodcc", RADV_DEBUG_NO_DCC},
301 {"shaders", RADV_DEBUG_DUMP_SHADERS},
302 {"nocache", RADV_DEBUG_NO_CACHE},
303 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
304 {"nohiz", RADV_DEBUG_NO_HIZ},
305 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
306 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
307 {"allbos", RADV_DEBUG_ALL_BOS},
308 {"noibs", RADV_DEBUG_NO_IBS},
309 {NULL, 0}
310 };
311
312 VkResult radv_CreateInstance(
313 const VkInstanceCreateInfo* pCreateInfo,
314 const VkAllocationCallbacks* pAllocator,
315 VkInstance* pInstance)
316 {
317 struct radv_instance *instance;
318
319 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
320
321 uint32_t client_version;
322 if (pCreateInfo->pApplicationInfo &&
323 pCreateInfo->pApplicationInfo->apiVersion != 0) {
324 client_version = pCreateInfo->pApplicationInfo->apiVersion;
325 } else {
326 client_version = VK_MAKE_VERSION(1, 0, 0);
327 }
328
329 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
330 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
331 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
332 "Client requested version %d.%d.%d",
333 VK_VERSION_MAJOR(client_version),
334 VK_VERSION_MINOR(client_version),
335 VK_VERSION_PATCH(client_version));
336 }
337
338 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
339 if (!is_extension_enabled(instance_extensions,
340 ARRAY_SIZE(instance_extensions),
341 pCreateInfo->ppEnabledExtensionNames[i]))
342 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
343 }
344
345 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
346 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
347 if (!instance)
348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
349
350 memset(instance, 0, sizeof(*instance));
351
352 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
353
354 if (pAllocator)
355 instance->alloc = *pAllocator;
356 else
357 instance->alloc = default_alloc;
358
359 instance->apiVersion = client_version;
360 instance->physicalDeviceCount = -1;
361
362 _mesa_locale_init();
363
364 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
365
366 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
367 radv_debug_options);
368
369 *pInstance = radv_instance_to_handle(instance);
370
371 return VK_SUCCESS;
372 }
373
374 void radv_DestroyInstance(
375 VkInstance _instance,
376 const VkAllocationCallbacks* pAllocator)
377 {
378 RADV_FROM_HANDLE(radv_instance, instance, _instance);
379
380 if (!instance)
381 return;
382
383 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
384 radv_physical_device_finish(instance->physicalDevices + i);
385 }
386
387 VG(VALGRIND_DESTROY_MEMPOOL(instance));
388
389 _mesa_locale_fini();
390
391 vk_free(&instance->alloc, instance);
392 }
393
394 static VkResult
395 radv_enumerate_devices(struct radv_instance *instance)
396 {
397 /* TODO: Check for more devices ? */
398 drmDevicePtr devices[8];
399 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
400 int max_devices;
401
402 instance->physicalDeviceCount = 0;
403
404 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
405 if (max_devices < 1)
406 return VK_ERROR_INCOMPATIBLE_DRIVER;
407
408 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
409 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
410 devices[i]->bustype == DRM_BUS_PCI &&
411 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
412
413 result = radv_physical_device_init(instance->physicalDevices +
414 instance->physicalDeviceCount,
415 instance,
416 devices[i]->nodes[DRM_NODE_RENDER]);
417 if (result == VK_SUCCESS)
418 ++instance->physicalDeviceCount;
419 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
420 break;
421 }
422 }
423 drmFreeDevices(devices, max_devices);
424
425 return result;
426 }
427
428 VkResult radv_EnumeratePhysicalDevices(
429 VkInstance _instance,
430 uint32_t* pPhysicalDeviceCount,
431 VkPhysicalDevice* pPhysicalDevices)
432 {
433 RADV_FROM_HANDLE(radv_instance, instance, _instance);
434 VkResult result;
435
436 if (instance->physicalDeviceCount < 0) {
437 result = radv_enumerate_devices(instance);
438 if (result != VK_SUCCESS &&
439 result != VK_ERROR_INCOMPATIBLE_DRIVER)
440 return result;
441 }
442
443 if (!pPhysicalDevices) {
444 *pPhysicalDeviceCount = instance->physicalDeviceCount;
445 } else {
446 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
447 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
448 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
449 }
450
451 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
452 : VK_SUCCESS;
453 }
454
455 void radv_GetPhysicalDeviceFeatures(
456 VkPhysicalDevice physicalDevice,
457 VkPhysicalDeviceFeatures* pFeatures)
458 {
459 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
460
461 memset(pFeatures, 0, sizeof(*pFeatures));
462
463 *pFeatures = (VkPhysicalDeviceFeatures) {
464 .robustBufferAccess = true,
465 .fullDrawIndexUint32 = true,
466 .imageCubeArray = true,
467 .independentBlend = true,
468 .geometryShader = true,
469 .tessellationShader = true,
470 .sampleRateShading = false,
471 .dualSrcBlend = true,
472 .logicOp = true,
473 .multiDrawIndirect = true,
474 .drawIndirectFirstInstance = true,
475 .depthClamp = true,
476 .depthBiasClamp = true,
477 .fillModeNonSolid = true,
478 .depthBounds = true,
479 .wideLines = true,
480 .largePoints = true,
481 .alphaToOne = true,
482 .multiViewport = true,
483 .samplerAnisotropy = true,
484 .textureCompressionETC2 = false,
485 .textureCompressionASTC_LDR = false,
486 .textureCompressionBC = true,
487 .occlusionQueryPrecise = true,
488 .pipelineStatisticsQuery = true,
489 .vertexPipelineStoresAndAtomics = true,
490 .fragmentStoresAndAtomics = true,
491 .shaderTessellationAndGeometryPointSize = true,
492 .shaderImageGatherExtended = true,
493 .shaderStorageImageExtendedFormats = true,
494 .shaderStorageImageMultisample = false,
495 .shaderUniformBufferArrayDynamicIndexing = true,
496 .shaderSampledImageArrayDynamicIndexing = true,
497 .shaderStorageBufferArrayDynamicIndexing = true,
498 .shaderStorageImageArrayDynamicIndexing = true,
499 .shaderStorageImageReadWithoutFormat = true,
500 .shaderStorageImageWriteWithoutFormat = true,
501 .shaderClipDistance = true,
502 .shaderCullDistance = true,
503 .shaderFloat64 = true,
504 .shaderInt64 = false,
505 .shaderInt16 = false,
506 .sparseBinding = true,
507 .variableMultisampleRate = true,
508 .inheritedQueries = true,
509 };
510 }
511
512 void radv_GetPhysicalDeviceFeatures2KHR(
513 VkPhysicalDevice physicalDevice,
514 VkPhysicalDeviceFeatures2KHR *pFeatures)
515 {
516 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
517 }
518
519 static uint32_t radv_get_driver_version()
520 {
521 const char *minor_string = strchr(VERSION, '.');
522 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
523 int major = atoi(VERSION);
524 int minor = minor_string ? atoi(minor_string + 1) : 0;
525 int patch = patch_string ? atoi(patch_string + 1) : 0;
526 if (strstr(VERSION, "devel")) {
527 if (patch == 0) {
528 patch = 99;
529 if (minor == 0) {
530 minor = 99;
531 --major;
532 } else
533 --minor;
534 } else
535 --patch;
536 }
537 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
538 return version;
539 }
540
541 void radv_GetPhysicalDeviceProperties(
542 VkPhysicalDevice physicalDevice,
543 VkPhysicalDeviceProperties* pProperties)
544 {
545 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
546 VkSampleCountFlags sample_counts = 0xf;
547
548 /* make sure that the entire descriptor set is addressable with a signed
549 * 32-bit int. So the sum of all limits scaled by descriptor size has to
550 * be at most 2 GiB. the combined image & samples object count as one of
551 * both. This limit is for the pipeline layout, not for the set layout, but
552 * there is no set limit, so we just set a pipeline limit. I don't think
553 * any app is going to hit this soon. */
554 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
555 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
556 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
557 32 /* sampler, largest when combined with image */ +
558 64 /* sampled image */ +
559 64 /* storage image */);
560
561 VkPhysicalDeviceLimits limits = {
562 .maxImageDimension1D = (1 << 14),
563 .maxImageDimension2D = (1 << 14),
564 .maxImageDimension3D = (1 << 11),
565 .maxImageDimensionCube = (1 << 14),
566 .maxImageArrayLayers = (1 << 11),
567 .maxTexelBufferElements = 128 * 1024 * 1024,
568 .maxUniformBufferRange = UINT32_MAX,
569 .maxStorageBufferRange = UINT32_MAX,
570 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
571 .maxMemoryAllocationCount = UINT32_MAX,
572 .maxSamplerAllocationCount = 64 * 1024,
573 .bufferImageGranularity = 64, /* A cache line */
574 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
575 .maxBoundDescriptorSets = MAX_SETS,
576 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
577 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
578 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
579 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
580 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
581 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
582 .maxPerStageResources = max_descriptor_set_size,
583 .maxDescriptorSetSamplers = max_descriptor_set_size,
584 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
585 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
586 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
587 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
588 .maxDescriptorSetSampledImages = max_descriptor_set_size,
589 .maxDescriptorSetStorageImages = max_descriptor_set_size,
590 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
591 .maxVertexInputAttributes = 32,
592 .maxVertexInputBindings = 32,
593 .maxVertexInputAttributeOffset = 2047,
594 .maxVertexInputBindingStride = 2048,
595 .maxVertexOutputComponents = 128,
596 .maxTessellationGenerationLevel = 64,
597 .maxTessellationPatchSize = 32,
598 .maxTessellationControlPerVertexInputComponents = 128,
599 .maxTessellationControlPerVertexOutputComponents = 128,
600 .maxTessellationControlPerPatchOutputComponents = 120,
601 .maxTessellationControlTotalOutputComponents = 4096,
602 .maxTessellationEvaluationInputComponents = 128,
603 .maxTessellationEvaluationOutputComponents = 128,
604 .maxGeometryShaderInvocations = 127,
605 .maxGeometryInputComponents = 64,
606 .maxGeometryOutputComponents = 128,
607 .maxGeometryOutputVertices = 256,
608 .maxGeometryTotalOutputComponents = 1024,
609 .maxFragmentInputComponents = 128,
610 .maxFragmentOutputAttachments = 8,
611 .maxFragmentDualSrcAttachments = 1,
612 .maxFragmentCombinedOutputResources = 8,
613 .maxComputeSharedMemorySize = 32768,
614 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
615 .maxComputeWorkGroupInvocations = 2048,
616 .maxComputeWorkGroupSize = {
617 2048,
618 2048,
619 2048
620 },
621 .subPixelPrecisionBits = 4 /* FIXME */,
622 .subTexelPrecisionBits = 4 /* FIXME */,
623 .mipmapPrecisionBits = 4 /* FIXME */,
624 .maxDrawIndexedIndexValue = UINT32_MAX,
625 .maxDrawIndirectCount = UINT32_MAX,
626 .maxSamplerLodBias = 16,
627 .maxSamplerAnisotropy = 16,
628 .maxViewports = MAX_VIEWPORTS,
629 .maxViewportDimensions = { (1 << 14), (1 << 14) },
630 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
631 .viewportSubPixelBits = 13, /* We take a float? */
632 .minMemoryMapAlignment = 4096, /* A page */
633 .minTexelBufferOffsetAlignment = 1,
634 .minUniformBufferOffsetAlignment = 4,
635 .minStorageBufferOffsetAlignment = 4,
636 .minTexelOffset = -32,
637 .maxTexelOffset = 31,
638 .minTexelGatherOffset = -32,
639 .maxTexelGatherOffset = 31,
640 .minInterpolationOffset = -2,
641 .maxInterpolationOffset = 2,
642 .subPixelInterpolationOffsetBits = 8,
643 .maxFramebufferWidth = (1 << 14),
644 .maxFramebufferHeight = (1 << 14),
645 .maxFramebufferLayers = (1 << 10),
646 .framebufferColorSampleCounts = sample_counts,
647 .framebufferDepthSampleCounts = sample_counts,
648 .framebufferStencilSampleCounts = sample_counts,
649 .framebufferNoAttachmentsSampleCounts = sample_counts,
650 .maxColorAttachments = MAX_RTS,
651 .sampledImageColorSampleCounts = sample_counts,
652 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
653 .sampledImageDepthSampleCounts = sample_counts,
654 .sampledImageStencilSampleCounts = sample_counts,
655 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
656 .maxSampleMaskWords = 1,
657 .timestampComputeAndGraphics = true,
658 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
659 .maxClipDistances = 8,
660 .maxCullDistances = 8,
661 .maxCombinedClipAndCullDistances = 8,
662 .discreteQueuePriorities = 1,
663 .pointSizeRange = { 0.125, 255.875 },
664 .lineWidthRange = { 0.0, 7.9921875 },
665 .pointSizeGranularity = (1.0 / 8.0),
666 .lineWidthGranularity = (1.0 / 128.0),
667 .strictLines = false, /* FINISHME */
668 .standardSampleLocations = true,
669 .optimalBufferCopyOffsetAlignment = 128,
670 .optimalBufferCopyRowPitchAlignment = 128,
671 .nonCoherentAtomSize = 64,
672 };
673
674 *pProperties = (VkPhysicalDeviceProperties) {
675 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
676 .driverVersion = radv_get_driver_version(),
677 .vendorID = 0x1002,
678 .deviceID = pdevice->rad_info.pci_id,
679 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
680 .limits = limits,
681 .sparseProperties = {0},
682 };
683
684 strcpy(pProperties->deviceName, pdevice->name);
685 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
686 }
687
688 void radv_GetPhysicalDeviceProperties2KHR(
689 VkPhysicalDevice physicalDevice,
690 VkPhysicalDeviceProperties2KHR *pProperties)
691 {
692 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
693
694 vk_foreach_struct(ext, pProperties->pNext) {
695 switch (ext->sType) {
696 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
697 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
698 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
699 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
700 break;
701 }
702 default:
703 break;
704 }
705 }
706 }
707
708 static void radv_get_physical_device_queue_family_properties(
709 struct radv_physical_device* pdevice,
710 uint32_t* pCount,
711 VkQueueFamilyProperties** pQueueFamilyProperties)
712 {
713 int num_queue_families = 1;
714 int idx;
715 if (pdevice->rad_info.compute_rings > 0 &&
716 pdevice->rad_info.chip_class >= CIK &&
717 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
718 num_queue_families++;
719
720 if (pQueueFamilyProperties == NULL) {
721 *pCount = num_queue_families;
722 return;
723 }
724
725 if (!*pCount)
726 return;
727
728 idx = 0;
729 if (*pCount >= 1) {
730 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
731 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
732 VK_QUEUE_COMPUTE_BIT |
733 VK_QUEUE_TRANSFER_BIT |
734 VK_QUEUE_SPARSE_BINDING_BIT,
735 .queueCount = 1,
736 .timestampValidBits = 64,
737 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
738 };
739 idx++;
740 }
741
742 if (pdevice->rad_info.compute_rings > 0 &&
743 pdevice->rad_info.chip_class >= CIK &&
744 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
745 if (*pCount > idx) {
746 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
747 .queueFlags = VK_QUEUE_COMPUTE_BIT |
748 VK_QUEUE_TRANSFER_BIT |
749 VK_QUEUE_SPARSE_BINDING_BIT,
750 .queueCount = pdevice->rad_info.compute_rings,
751 .timestampValidBits = 64,
752 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
753 };
754 idx++;
755 }
756 }
757 *pCount = idx;
758 }
759
760 void radv_GetPhysicalDeviceQueueFamilyProperties(
761 VkPhysicalDevice physicalDevice,
762 uint32_t* pCount,
763 VkQueueFamilyProperties* pQueueFamilyProperties)
764 {
765 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
766 if (!pQueueFamilyProperties) {
767 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
768 return;
769 }
770 VkQueueFamilyProperties *properties[] = {
771 pQueueFamilyProperties + 0,
772 pQueueFamilyProperties + 1,
773 pQueueFamilyProperties + 2,
774 };
775 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
776 assert(*pCount <= 3);
777 }
778
779 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
780 VkPhysicalDevice physicalDevice,
781 uint32_t* pCount,
782 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
783 {
784 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
785 if (!pQueueFamilyProperties) {
786 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
787 return;
788 }
789 VkQueueFamilyProperties *properties[] = {
790 &pQueueFamilyProperties[0].queueFamilyProperties,
791 &pQueueFamilyProperties[1].queueFamilyProperties,
792 &pQueueFamilyProperties[2].queueFamilyProperties,
793 };
794 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
795 assert(*pCount <= 3);
796 }
797
798 void radv_GetPhysicalDeviceMemoryProperties(
799 VkPhysicalDevice physicalDevice,
800 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
801 {
802 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
803
804 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
805
806 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
807 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
808 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
809 .heapIndex = RADV_MEM_HEAP_VRAM,
810 };
811 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
812 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
813 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
814 .heapIndex = RADV_MEM_HEAP_GTT,
815 };
816 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
817 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
818 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
819 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
820 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
821 };
822 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
823 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
824 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
825 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
826 .heapIndex = RADV_MEM_HEAP_GTT,
827 };
828
829 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
830
831 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
832 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
833 .size = physical_device->rad_info.vram_size -
834 physical_device->rad_info.visible_vram_size,
835 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
836 };
837 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
838 .size = physical_device->rad_info.visible_vram_size,
839 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
840 };
841 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
842 .size = physical_device->rad_info.gart_size,
843 .flags = 0,
844 };
845 }
846
847 void radv_GetPhysicalDeviceMemoryProperties2KHR(
848 VkPhysicalDevice physicalDevice,
849 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
850 {
851 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
852 &pMemoryProperties->memoryProperties);
853 }
854
855 static int
856 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
857 int queue_family_index, int idx)
858 {
859 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
860 queue->device = device;
861 queue->queue_family_index = queue_family_index;
862 queue->queue_idx = idx;
863
864 queue->hw_ctx = device->ws->ctx_create(device->ws);
865 if (!queue->hw_ctx)
866 return VK_ERROR_OUT_OF_HOST_MEMORY;
867
868 return VK_SUCCESS;
869 }
870
871 static void
872 radv_queue_finish(struct radv_queue *queue)
873 {
874 if (queue->hw_ctx)
875 queue->device->ws->ctx_destroy(queue->hw_ctx);
876
877 if (queue->initial_preamble_cs)
878 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
879 if (queue->continue_preamble_cs)
880 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
881 if (queue->descriptor_bo)
882 queue->device->ws->buffer_destroy(queue->descriptor_bo);
883 if (queue->scratch_bo)
884 queue->device->ws->buffer_destroy(queue->scratch_bo);
885 if (queue->esgs_ring_bo)
886 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
887 if (queue->gsvs_ring_bo)
888 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
889 if (queue->tess_factor_ring_bo)
890 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
891 if (queue->tess_offchip_ring_bo)
892 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
893 if (queue->compute_scratch_bo)
894 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
895 }
896
897 static void
898 radv_device_init_gs_info(struct radv_device *device)
899 {
900 switch (device->physical_device->rad_info.family) {
901 case CHIP_OLAND:
902 case CHIP_HAINAN:
903 case CHIP_KAVERI:
904 case CHIP_KABINI:
905 case CHIP_MULLINS:
906 case CHIP_ICELAND:
907 case CHIP_CARRIZO:
908 case CHIP_STONEY:
909 device->gs_table_depth = 16;
910 return;
911 case CHIP_TAHITI:
912 case CHIP_PITCAIRN:
913 case CHIP_VERDE:
914 case CHIP_BONAIRE:
915 case CHIP_HAWAII:
916 case CHIP_TONGA:
917 case CHIP_FIJI:
918 case CHIP_POLARIS10:
919 case CHIP_POLARIS11:
920 case CHIP_POLARIS12:
921 device->gs_table_depth = 32;
922 return;
923 default:
924 unreachable("unknown GPU");
925 }
926 }
927
928 VkResult radv_CreateDevice(
929 VkPhysicalDevice physicalDevice,
930 const VkDeviceCreateInfo* pCreateInfo,
931 const VkAllocationCallbacks* pAllocator,
932 VkDevice* pDevice)
933 {
934 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
935 VkResult result;
936 struct radv_device *device;
937
938 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
939 if (!is_extension_enabled(physical_device->extensions.ext_array,
940 physical_device->extensions.num_ext,
941 pCreateInfo->ppEnabledExtensionNames[i]))
942 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
943 }
944
945 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
946 sizeof(*device), 8,
947 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
948 if (!device)
949 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
950
951 memset(device, 0, sizeof(*device));
952
953 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
954 device->instance = physical_device->instance;
955 device->physical_device = physical_device;
956
957 device->debug_flags = device->instance->debug_flags;
958
959 device->ws = physical_device->ws;
960 if (pAllocator)
961 device->alloc = *pAllocator;
962 else
963 device->alloc = physical_device->instance->alloc;
964
965 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
966 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
967 uint32_t qfi = queue_create->queueFamilyIndex;
968
969 device->queues[qfi] = vk_alloc(&device->alloc,
970 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
971 if (!device->queues[qfi]) {
972 result = VK_ERROR_OUT_OF_HOST_MEMORY;
973 goto fail;
974 }
975
976 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
977
978 device->queue_count[qfi] = queue_create->queueCount;
979
980 for (unsigned q = 0; q < queue_create->queueCount; q++) {
981 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
982 if (result != VK_SUCCESS)
983 goto fail;
984 }
985 }
986
987 #if HAVE_LLVM < 0x0400
988 device->llvm_supports_spill = false;
989 #else
990 device->llvm_supports_spill = true;
991 #endif
992
993 /* The maximum number of scratch waves. Scratch space isn't divided
994 * evenly between CUs. The number is only a function of the number of CUs.
995 * We can decrease the constant to decrease the scratch buffer size.
996 *
997 * sctx->scratch_waves must be >= the maximum posible size of
998 * 1 threadgroup, so that the hw doesn't hang from being unable
999 * to start any.
1000 *
1001 * The recommended value is 4 per CU at most. Higher numbers don't
1002 * bring much benefit, but they still occupy chip resources (think
1003 * async compute). I've seen ~2% performance difference between 4 and 32.
1004 */
1005 uint32_t max_threads_per_block = 2048;
1006 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1007 max_threads_per_block / 64);
1008
1009 radv_device_init_gs_info(device);
1010
1011 device->tess_offchip_block_dw_size =
1012 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1013 device->has_distributed_tess =
1014 device->physical_device->rad_info.chip_class >= VI &&
1015 device->physical_device->rad_info.max_se >= 2;
1016
1017 result = radv_device_init_meta(device);
1018 if (result != VK_SUCCESS)
1019 goto fail;
1020
1021 radv_device_init_msaa(device);
1022
1023 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1024 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1025 switch (family) {
1026 case RADV_QUEUE_GENERAL:
1027 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1028 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1029 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1030 break;
1031 case RADV_QUEUE_COMPUTE:
1032 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1033 radeon_emit(device->empty_cs[family], 0);
1034 break;
1035 }
1036 device->ws->cs_finalize(device->empty_cs[family]);
1037
1038 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1039 switch (family) {
1040 case RADV_QUEUE_GENERAL:
1041 case RADV_QUEUE_COMPUTE:
1042 si_cs_emit_cache_flush(device->flush_cs[family],
1043 device->physical_device->rad_info.chip_class,
1044 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1045 RADV_CMD_FLAG_INV_ICACHE |
1046 RADV_CMD_FLAG_INV_SMEM_L1 |
1047 RADV_CMD_FLAG_INV_VMEM_L1 |
1048 RADV_CMD_FLAG_INV_GLOBAL_L2);
1049 break;
1050 }
1051 device->ws->cs_finalize(device->flush_cs[family]);
1052
1053 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1054 switch (family) {
1055 case RADV_QUEUE_GENERAL:
1056 case RADV_QUEUE_COMPUTE:
1057 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1058 device->physical_device->rad_info.chip_class,
1059 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1060 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1061 RADV_CMD_FLAG_INV_ICACHE |
1062 RADV_CMD_FLAG_INV_SMEM_L1 |
1063 RADV_CMD_FLAG_INV_VMEM_L1 |
1064 RADV_CMD_FLAG_INV_GLOBAL_L2);
1065 break;
1066 }
1067 device->ws->cs_finalize(device->flush_shader_cs[family]);
1068 }
1069
1070 if (getenv("RADV_TRACE_FILE")) {
1071 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1072 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1073 if (!device->trace_bo)
1074 goto fail;
1075
1076 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1077 if (!device->trace_id_ptr)
1078 goto fail;
1079 }
1080
1081 if (device->physical_device->rad_info.chip_class >= CIK)
1082 cik_create_gfx_config(device);
1083
1084 VkPipelineCacheCreateInfo ci;
1085 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1086 ci.pNext = NULL;
1087 ci.flags = 0;
1088 ci.pInitialData = NULL;
1089 ci.initialDataSize = 0;
1090 VkPipelineCache pc;
1091 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1092 &ci, NULL, &pc);
1093 if (result != VK_SUCCESS)
1094 goto fail;
1095
1096 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1097
1098 *pDevice = radv_device_to_handle(device);
1099 return VK_SUCCESS;
1100
1101 fail:
1102 if (device->trace_bo)
1103 device->ws->buffer_destroy(device->trace_bo);
1104
1105 if (device->gfx_init)
1106 device->ws->buffer_destroy(device->gfx_init);
1107
1108 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1109 for (unsigned q = 0; q < device->queue_count[i]; q++)
1110 radv_queue_finish(&device->queues[i][q]);
1111 if (device->queue_count[i])
1112 vk_free(&device->alloc, device->queues[i]);
1113 }
1114
1115 vk_free(&device->alloc, device);
1116 return result;
1117 }
1118
1119 void radv_DestroyDevice(
1120 VkDevice _device,
1121 const VkAllocationCallbacks* pAllocator)
1122 {
1123 RADV_FROM_HANDLE(radv_device, device, _device);
1124
1125 if (!device)
1126 return;
1127
1128 if (device->trace_bo)
1129 device->ws->buffer_destroy(device->trace_bo);
1130
1131 if (device->gfx_init)
1132 device->ws->buffer_destroy(device->gfx_init);
1133
1134 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1135 for (unsigned q = 0; q < device->queue_count[i]; q++)
1136 radv_queue_finish(&device->queues[i][q]);
1137 if (device->queue_count[i])
1138 vk_free(&device->alloc, device->queues[i]);
1139 if (device->empty_cs[i])
1140 device->ws->cs_destroy(device->empty_cs[i]);
1141 if (device->flush_cs[i])
1142 device->ws->cs_destroy(device->flush_cs[i]);
1143 if (device->flush_shader_cs[i])
1144 device->ws->cs_destroy(device->flush_shader_cs[i]);
1145 }
1146 radv_device_finish_meta(device);
1147
1148 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1149 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1150
1151 vk_free(&device->alloc, device);
1152 }
1153
1154 VkResult radv_EnumerateInstanceExtensionProperties(
1155 const char* pLayerName,
1156 uint32_t* pPropertyCount,
1157 VkExtensionProperties* pProperties)
1158 {
1159 if (pProperties == NULL) {
1160 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1161 return VK_SUCCESS;
1162 }
1163
1164 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1165 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1166
1167 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1168 return VK_INCOMPLETE;
1169
1170 return VK_SUCCESS;
1171 }
1172
1173 VkResult radv_EnumerateDeviceExtensionProperties(
1174 VkPhysicalDevice physicalDevice,
1175 const char* pLayerName,
1176 uint32_t* pPropertyCount,
1177 VkExtensionProperties* pProperties)
1178 {
1179 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1180
1181 if (pProperties == NULL) {
1182 *pPropertyCount = pdevice->extensions.num_ext;
1183 return VK_SUCCESS;
1184 }
1185
1186 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1187 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1188
1189 if (*pPropertyCount < pdevice->extensions.num_ext)
1190 return VK_INCOMPLETE;
1191
1192 return VK_SUCCESS;
1193 }
1194
1195 VkResult radv_EnumerateInstanceLayerProperties(
1196 uint32_t* pPropertyCount,
1197 VkLayerProperties* pProperties)
1198 {
1199 if (pProperties == NULL) {
1200 *pPropertyCount = 0;
1201 return VK_SUCCESS;
1202 }
1203
1204 /* None supported at this time */
1205 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1206 }
1207
1208 VkResult radv_EnumerateDeviceLayerProperties(
1209 VkPhysicalDevice physicalDevice,
1210 uint32_t* pPropertyCount,
1211 VkLayerProperties* pProperties)
1212 {
1213 if (pProperties == NULL) {
1214 *pPropertyCount = 0;
1215 return VK_SUCCESS;
1216 }
1217
1218 /* None supported at this time */
1219 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1220 }
1221
1222 void radv_GetDeviceQueue(
1223 VkDevice _device,
1224 uint32_t queueFamilyIndex,
1225 uint32_t queueIndex,
1226 VkQueue* pQueue)
1227 {
1228 RADV_FROM_HANDLE(radv_device, device, _device);
1229
1230 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1231 }
1232
1233 static void radv_dump_trace(struct radv_device *device,
1234 struct radeon_winsys_cs *cs)
1235 {
1236 const char *filename = getenv("RADV_TRACE_FILE");
1237 FILE *f = fopen(filename, "w");
1238 if (!f) {
1239 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1240 return;
1241 }
1242
1243 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1244 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1245 fclose(f);
1246 }
1247
1248 static void
1249 fill_geom_tess_rings(struct radv_queue *queue,
1250 uint32_t *map,
1251 bool add_sample_positions,
1252 uint32_t esgs_ring_size,
1253 struct radeon_winsys_bo *esgs_ring_bo,
1254 uint32_t gsvs_ring_size,
1255 struct radeon_winsys_bo *gsvs_ring_bo,
1256 uint32_t tess_factor_ring_size,
1257 struct radeon_winsys_bo *tess_factor_ring_bo,
1258 uint32_t tess_offchip_ring_size,
1259 struct radeon_winsys_bo *tess_offchip_ring_bo)
1260 {
1261 uint64_t esgs_va = 0, gsvs_va = 0;
1262 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1263 uint32_t *desc = &map[4];
1264
1265 if (esgs_ring_bo)
1266 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1267 if (gsvs_ring_bo)
1268 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1269 if (tess_factor_ring_bo)
1270 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1271 if (tess_offchip_ring_bo)
1272 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1273
1274 /* stride 0, num records - size, add tid, swizzle, elsize4,
1275 index stride 64 */
1276 desc[0] = esgs_va;
1277 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1278 S_008F04_STRIDE(0) |
1279 S_008F04_SWIZZLE_ENABLE(true);
1280 desc[2] = esgs_ring_size;
1281 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1282 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1283 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1284 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1285 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1286 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1287 S_008F0C_ELEMENT_SIZE(1) |
1288 S_008F0C_INDEX_STRIDE(3) |
1289 S_008F0C_ADD_TID_ENABLE(true);
1290
1291 desc += 4;
1292 /* GS entry for ES->GS ring */
1293 /* stride 0, num records - size, elsize0,
1294 index stride 0 */
1295 desc[0] = esgs_va;
1296 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1297 S_008F04_STRIDE(0) |
1298 S_008F04_SWIZZLE_ENABLE(false);
1299 desc[2] = esgs_ring_size;
1300 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1301 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1302 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1303 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1304 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1306 S_008F0C_ELEMENT_SIZE(0) |
1307 S_008F0C_INDEX_STRIDE(0) |
1308 S_008F0C_ADD_TID_ENABLE(false);
1309
1310 desc += 4;
1311 /* VS entry for GS->VS ring */
1312 /* stride 0, num records - size, elsize0,
1313 index stride 0 */
1314 desc[0] = gsvs_va;
1315 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1316 S_008F04_STRIDE(0) |
1317 S_008F04_SWIZZLE_ENABLE(false);
1318 desc[2] = gsvs_ring_size;
1319 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1320 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1321 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1322 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1323 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1325 S_008F0C_ELEMENT_SIZE(0) |
1326 S_008F0C_INDEX_STRIDE(0) |
1327 S_008F0C_ADD_TID_ENABLE(false);
1328 desc += 4;
1329
1330 /* stride gsvs_itemsize, num records 64
1331 elsize 4, index stride 16 */
1332 /* shader will patch stride and desc[2] */
1333 desc[0] = gsvs_va;
1334 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1335 S_008F04_STRIDE(0) |
1336 S_008F04_SWIZZLE_ENABLE(true);
1337 desc[2] = 0;
1338 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1342 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1344 S_008F0C_ELEMENT_SIZE(1) |
1345 S_008F0C_INDEX_STRIDE(1) |
1346 S_008F0C_ADD_TID_ENABLE(true);
1347 desc += 4;
1348
1349 desc[0] = tess_factor_va;
1350 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1351 S_008F04_STRIDE(0) |
1352 S_008F04_SWIZZLE_ENABLE(false);
1353 desc[2] = tess_factor_ring_size;
1354 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1360 S_008F0C_ELEMENT_SIZE(0) |
1361 S_008F0C_INDEX_STRIDE(0) |
1362 S_008F0C_ADD_TID_ENABLE(false);
1363 desc += 4;
1364
1365 desc[0] = tess_offchip_va;
1366 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1367 S_008F04_STRIDE(0) |
1368 S_008F04_SWIZZLE_ENABLE(false);
1369 desc[2] = tess_offchip_ring_size;
1370 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1371 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1372 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1373 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1374 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1376 S_008F0C_ELEMENT_SIZE(0) |
1377 S_008F0C_INDEX_STRIDE(0) |
1378 S_008F0C_ADD_TID_ENABLE(false);
1379 desc += 4;
1380
1381 /* add sample positions after all rings */
1382 memcpy(desc, queue->device->sample_locations_1x, 8);
1383 desc += 2;
1384 memcpy(desc, queue->device->sample_locations_2x, 16);
1385 desc += 4;
1386 memcpy(desc, queue->device->sample_locations_4x, 32);
1387 desc += 8;
1388 memcpy(desc, queue->device->sample_locations_8x, 64);
1389 desc += 16;
1390 memcpy(desc, queue->device->sample_locations_16x, 128);
1391 }
1392
1393 static unsigned
1394 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1395 {
1396 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1397 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1398 device->physical_device->rad_info.family != CHIP_STONEY;
1399 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1400 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1401 device->physical_device->rad_info.max_se;
1402 unsigned offchip_granularity;
1403 unsigned hs_offchip_param;
1404 switch (device->tess_offchip_block_dw_size) {
1405 default:
1406 assert(0);
1407 /* fall through */
1408 case 8192:
1409 offchip_granularity = V_03093C_X_8K_DWORDS;
1410 break;
1411 case 4096:
1412 offchip_granularity = V_03093C_X_4K_DWORDS;
1413 break;
1414 }
1415
1416 switch (device->physical_device->rad_info.chip_class) {
1417 case SI:
1418 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1419 break;
1420 case CIK:
1421 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1422 break;
1423 case VI:
1424 default:
1425 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
1426 break;
1427 }
1428
1429 *max_offchip_buffers_p = max_offchip_buffers;
1430 if (device->physical_device->rad_info.chip_class >= CIK) {
1431 if (device->physical_device->rad_info.chip_class >= VI)
1432 --max_offchip_buffers;
1433 hs_offchip_param =
1434 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1435 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1436 } else {
1437 hs_offchip_param =
1438 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1439 }
1440 return hs_offchip_param;
1441 }
1442
1443 static VkResult
1444 radv_get_preamble_cs(struct radv_queue *queue,
1445 uint32_t scratch_size,
1446 uint32_t compute_scratch_size,
1447 uint32_t esgs_ring_size,
1448 uint32_t gsvs_ring_size,
1449 bool needs_tess_rings,
1450 bool needs_sample_positions,
1451 struct radeon_winsys_cs **initial_preamble_cs,
1452 struct radeon_winsys_cs **continue_preamble_cs)
1453 {
1454 struct radeon_winsys_bo *scratch_bo = NULL;
1455 struct radeon_winsys_bo *descriptor_bo = NULL;
1456 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1457 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1458 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1459 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1460 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1461 struct radeon_winsys_cs *dest_cs[2] = {0};
1462 bool add_tess_rings = false, add_sample_positions = false;
1463 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1464 unsigned max_offchip_buffers;
1465 unsigned hs_offchip_param = 0;
1466 if (!queue->has_tess_rings) {
1467 if (needs_tess_rings)
1468 add_tess_rings = true;
1469 }
1470 if (!queue->has_sample_positions) {
1471 if (needs_sample_positions)
1472 add_sample_positions = true;
1473 }
1474 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1475 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1476 &max_offchip_buffers);
1477 tess_offchip_ring_size = max_offchip_buffers *
1478 queue->device->tess_offchip_block_dw_size * 4;
1479
1480 if (scratch_size <= queue->scratch_size &&
1481 compute_scratch_size <= queue->compute_scratch_size &&
1482 esgs_ring_size <= queue->esgs_ring_size &&
1483 gsvs_ring_size <= queue->gsvs_ring_size &&
1484 !add_tess_rings && !add_sample_positions &&
1485 queue->initial_preamble_cs) {
1486 *initial_preamble_cs = queue->initial_preamble_cs;
1487 *continue_preamble_cs = queue->continue_preamble_cs;
1488 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1489 *continue_preamble_cs = NULL;
1490 return VK_SUCCESS;
1491 }
1492
1493 if (scratch_size > queue->scratch_size) {
1494 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1495 scratch_size,
1496 4096,
1497 RADEON_DOMAIN_VRAM,
1498 RADEON_FLAG_NO_CPU_ACCESS);
1499 if (!scratch_bo)
1500 goto fail;
1501 } else
1502 scratch_bo = queue->scratch_bo;
1503
1504 if (compute_scratch_size > queue->compute_scratch_size) {
1505 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1506 compute_scratch_size,
1507 4096,
1508 RADEON_DOMAIN_VRAM,
1509 RADEON_FLAG_NO_CPU_ACCESS);
1510 if (!compute_scratch_bo)
1511 goto fail;
1512
1513 } else
1514 compute_scratch_bo = queue->compute_scratch_bo;
1515
1516 if (esgs_ring_size > queue->esgs_ring_size) {
1517 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1518 esgs_ring_size,
1519 4096,
1520 RADEON_DOMAIN_VRAM,
1521 RADEON_FLAG_NO_CPU_ACCESS);
1522 if (!esgs_ring_bo)
1523 goto fail;
1524 } else {
1525 esgs_ring_bo = queue->esgs_ring_bo;
1526 esgs_ring_size = queue->esgs_ring_size;
1527 }
1528
1529 if (gsvs_ring_size > queue->gsvs_ring_size) {
1530 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1531 gsvs_ring_size,
1532 4096,
1533 RADEON_DOMAIN_VRAM,
1534 RADEON_FLAG_NO_CPU_ACCESS);
1535 if (!gsvs_ring_bo)
1536 goto fail;
1537 } else {
1538 gsvs_ring_bo = queue->gsvs_ring_bo;
1539 gsvs_ring_size = queue->gsvs_ring_size;
1540 }
1541
1542 if (add_tess_rings) {
1543 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1544 tess_factor_ring_size,
1545 256,
1546 RADEON_DOMAIN_VRAM,
1547 RADEON_FLAG_NO_CPU_ACCESS);
1548 if (!tess_factor_ring_bo)
1549 goto fail;
1550 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1551 tess_offchip_ring_size,
1552 256,
1553 RADEON_DOMAIN_VRAM,
1554 RADEON_FLAG_NO_CPU_ACCESS);
1555 if (!tess_offchip_ring_bo)
1556 goto fail;
1557 } else {
1558 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1559 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1560 }
1561
1562 if (scratch_bo != queue->scratch_bo ||
1563 esgs_ring_bo != queue->esgs_ring_bo ||
1564 gsvs_ring_bo != queue->gsvs_ring_bo ||
1565 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1566 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1567 uint32_t size = 0;
1568 if (gsvs_ring_bo || esgs_ring_bo ||
1569 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1570 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1571 if (add_sample_positions)
1572 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1573 }
1574 else if (scratch_bo)
1575 size = 8; /* 2 dword */
1576
1577 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1578 size,
1579 4096,
1580 RADEON_DOMAIN_VRAM,
1581 RADEON_FLAG_CPU_ACCESS);
1582 if (!descriptor_bo)
1583 goto fail;
1584 } else
1585 descriptor_bo = queue->descriptor_bo;
1586
1587 for(int i = 0; i < 2; ++i) {
1588 struct radeon_winsys_cs *cs = NULL;
1589 cs = queue->device->ws->cs_create(queue->device->ws,
1590 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1591 if (!cs)
1592 goto fail;
1593
1594 dest_cs[i] = cs;
1595
1596 if (scratch_bo)
1597 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1598
1599 if (esgs_ring_bo)
1600 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1601
1602 if (gsvs_ring_bo)
1603 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1604
1605 if (tess_factor_ring_bo)
1606 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1607
1608 if (tess_offchip_ring_bo)
1609 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1610
1611 if (descriptor_bo)
1612 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1613
1614 if (descriptor_bo != queue->descriptor_bo) {
1615 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1616
1617 if (scratch_bo) {
1618 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1619 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1620 S_008F04_SWIZZLE_ENABLE(1);
1621 map[0] = scratch_va;
1622 map[1] = rsrc1;
1623 }
1624
1625 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1626 add_sample_positions)
1627 fill_geom_tess_rings(queue, map, add_sample_positions,
1628 esgs_ring_size, esgs_ring_bo,
1629 gsvs_ring_size, gsvs_ring_bo,
1630 tess_factor_ring_size, tess_factor_ring_bo,
1631 tess_offchip_ring_size, tess_offchip_ring_bo);
1632
1633 queue->device->ws->buffer_unmap(descriptor_bo);
1634 }
1635
1636 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1637 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1638 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1639 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1640 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1641 }
1642
1643 if (esgs_ring_bo || gsvs_ring_bo) {
1644 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1645 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1646 radeon_emit(cs, esgs_ring_size >> 8);
1647 radeon_emit(cs, gsvs_ring_size >> 8);
1648 } else {
1649 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1650 radeon_emit(cs, esgs_ring_size >> 8);
1651 radeon_emit(cs, gsvs_ring_size >> 8);
1652 }
1653 }
1654
1655 if (tess_factor_ring_bo) {
1656 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1657 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1658 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1659 S_030938_SIZE(tess_factor_ring_size / 4));
1660 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1661 tf_va >> 8);
1662 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1663 } else {
1664 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1665 S_008988_SIZE(tess_factor_ring_size / 4));
1666 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1667 tf_va >> 8);
1668 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1669 hs_offchip_param);
1670 }
1671 }
1672
1673 if (descriptor_bo) {
1674 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1675 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1676 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1677 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1678 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1679 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1680
1681 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1682
1683 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1684 radeon_set_sh_reg_seq(cs, regs[i], 2);
1685 radeon_emit(cs, va);
1686 radeon_emit(cs, va >> 32);
1687 }
1688 }
1689
1690 if (compute_scratch_bo) {
1691 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1692 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1693 S_008F04_SWIZZLE_ENABLE(1);
1694
1695 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1696
1697 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1698 radeon_emit(cs, scratch_va);
1699 radeon_emit(cs, rsrc1);
1700 }
1701
1702 if (!i) {
1703 si_cs_emit_cache_flush(cs,
1704 queue->device->physical_device->rad_info.chip_class,
1705 queue->queue_family_index == RING_COMPUTE &&
1706 queue->device->physical_device->rad_info.chip_class >= CIK,
1707 RADV_CMD_FLAG_INV_ICACHE |
1708 RADV_CMD_FLAG_INV_SMEM_L1 |
1709 RADV_CMD_FLAG_INV_VMEM_L1 |
1710 RADV_CMD_FLAG_INV_GLOBAL_L2);
1711 }
1712
1713 if (!queue->device->ws->cs_finalize(cs))
1714 goto fail;
1715 }
1716
1717 if (queue->initial_preamble_cs)
1718 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1719
1720 if (queue->continue_preamble_cs)
1721 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1722
1723 queue->initial_preamble_cs = dest_cs[0];
1724 queue->continue_preamble_cs = dest_cs[1];
1725
1726 if (scratch_bo != queue->scratch_bo) {
1727 if (queue->scratch_bo)
1728 queue->device->ws->buffer_destroy(queue->scratch_bo);
1729 queue->scratch_bo = scratch_bo;
1730 queue->scratch_size = scratch_size;
1731 }
1732
1733 if (compute_scratch_bo != queue->compute_scratch_bo) {
1734 if (queue->compute_scratch_bo)
1735 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1736 queue->compute_scratch_bo = compute_scratch_bo;
1737 queue->compute_scratch_size = compute_scratch_size;
1738 }
1739
1740 if (esgs_ring_bo != queue->esgs_ring_bo) {
1741 if (queue->esgs_ring_bo)
1742 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1743 queue->esgs_ring_bo = esgs_ring_bo;
1744 queue->esgs_ring_size = esgs_ring_size;
1745 }
1746
1747 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1748 if (queue->gsvs_ring_bo)
1749 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1750 queue->gsvs_ring_bo = gsvs_ring_bo;
1751 queue->gsvs_ring_size = gsvs_ring_size;
1752 }
1753
1754 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1755 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1756 }
1757
1758 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1759 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1760 queue->has_tess_rings = true;
1761 }
1762
1763 if (descriptor_bo != queue->descriptor_bo) {
1764 if (queue->descriptor_bo)
1765 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1766
1767 queue->descriptor_bo = descriptor_bo;
1768 }
1769
1770 if (add_sample_positions)
1771 queue->has_sample_positions = true;
1772
1773 *initial_preamble_cs = queue->initial_preamble_cs;
1774 *continue_preamble_cs = queue->continue_preamble_cs;
1775 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1776 *continue_preamble_cs = NULL;
1777 return VK_SUCCESS;
1778 fail:
1779 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1780 if (dest_cs[i])
1781 queue->device->ws->cs_destroy(dest_cs[i]);
1782 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1783 queue->device->ws->buffer_destroy(descriptor_bo);
1784 if (scratch_bo && scratch_bo != queue->scratch_bo)
1785 queue->device->ws->buffer_destroy(scratch_bo);
1786 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1787 queue->device->ws->buffer_destroy(compute_scratch_bo);
1788 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1789 queue->device->ws->buffer_destroy(esgs_ring_bo);
1790 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1791 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1792 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1793 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1794 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1795 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1796 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1797 }
1798
1799 VkResult radv_QueueSubmit(
1800 VkQueue _queue,
1801 uint32_t submitCount,
1802 const VkSubmitInfo* pSubmits,
1803 VkFence _fence)
1804 {
1805 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1806 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1807 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1808 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1809 int ret;
1810 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1811 uint32_t scratch_size = 0;
1812 uint32_t compute_scratch_size = 0;
1813 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1814 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1815 VkResult result;
1816 bool fence_emitted = false;
1817 bool tess_rings_needed = false;
1818 bool sample_positions_needed = false;
1819
1820 /* Do this first so failing to allocate scratch buffers can't result in
1821 * partially executed submissions. */
1822 for (uint32_t i = 0; i < submitCount; i++) {
1823 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1824 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1825 pSubmits[i].pCommandBuffers[j]);
1826
1827 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1828 compute_scratch_size = MAX2(compute_scratch_size,
1829 cmd_buffer->compute_scratch_size_needed);
1830 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1831 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1832 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1833 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1834 }
1835 }
1836
1837 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1838 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1839 sample_positions_needed,
1840 &initial_preamble_cs, &continue_preamble_cs);
1841 if (result != VK_SUCCESS)
1842 return result;
1843
1844 for (uint32_t i = 0; i < submitCount; i++) {
1845 struct radeon_winsys_cs **cs_array;
1846 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1847 bool can_patch = !do_flush;
1848 uint32_t advance;
1849
1850 if (!pSubmits[i].commandBufferCount) {
1851 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1852 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1853 &queue->device->empty_cs[queue->queue_family_index],
1854 1, NULL, NULL,
1855 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1856 pSubmits[i].waitSemaphoreCount,
1857 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1858 pSubmits[i].signalSemaphoreCount,
1859 false, base_fence);
1860 if (ret) {
1861 radv_loge("failed to submit CS %d\n", i);
1862 abort();
1863 }
1864 fence_emitted = true;
1865 }
1866 continue;
1867 }
1868
1869 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1870 (pSubmits[i].commandBufferCount + do_flush));
1871
1872 if(do_flush)
1873 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
1874 queue->device->flush_shader_cs[queue->queue_family_index] :
1875 queue->device->flush_cs[queue->queue_family_index];
1876
1877 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1879 pSubmits[i].pCommandBuffers[j]);
1880 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1881
1882 cs_array[j + do_flush] = cmd_buffer->cs;
1883 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1884 can_patch = false;
1885 }
1886
1887 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1888 advance = MIN2(max_cs_submission,
1889 pSubmits[i].commandBufferCount + do_flush - j);
1890 bool b = j == 0;
1891 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1892
1893 if (queue->device->trace_bo)
1894 *queue->device->trace_id_ptr = 0;
1895
1896 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1897 advance, initial_preamble_cs, continue_preamble_cs,
1898 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1899 b ? pSubmits[i].waitSemaphoreCount : 0,
1900 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1901 e ? pSubmits[i].signalSemaphoreCount : 0,
1902 can_patch, base_fence);
1903
1904 if (ret) {
1905 radv_loge("failed to submit CS %d\n", i);
1906 abort();
1907 }
1908 fence_emitted = true;
1909 if (queue->device->trace_bo) {
1910 bool success = queue->device->ws->ctx_wait_idle(
1911 queue->hw_ctx,
1912 radv_queue_family_to_ring(
1913 queue->queue_family_index),
1914 queue->queue_idx);
1915
1916 if (!success) { /* Hang */
1917 radv_dump_trace(queue->device, cs_array[j]);
1918 abort();
1919 }
1920 }
1921 }
1922 free(cs_array);
1923 }
1924
1925 if (fence) {
1926 if (!fence_emitted)
1927 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1928 &queue->device->empty_cs[queue->queue_family_index],
1929 1, NULL, NULL, NULL, 0, NULL, 0,
1930 false, base_fence);
1931
1932 fence->submitted = true;
1933 }
1934
1935 return VK_SUCCESS;
1936 }
1937
1938 VkResult radv_QueueWaitIdle(
1939 VkQueue _queue)
1940 {
1941 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1942
1943 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1944 radv_queue_family_to_ring(queue->queue_family_index),
1945 queue->queue_idx);
1946 return VK_SUCCESS;
1947 }
1948
1949 VkResult radv_DeviceWaitIdle(
1950 VkDevice _device)
1951 {
1952 RADV_FROM_HANDLE(radv_device, device, _device);
1953
1954 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1955 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1956 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1957 }
1958 }
1959 return VK_SUCCESS;
1960 }
1961
1962 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1963 VkInstance instance,
1964 const char* pName)
1965 {
1966 return radv_lookup_entrypoint(pName);
1967 }
1968
1969 /* The loader wants us to expose a second GetInstanceProcAddr function
1970 * to work around certain LD_PRELOAD issues seen in apps.
1971 */
1972 PUBLIC
1973 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1974 VkInstance instance,
1975 const char* pName);
1976
1977 PUBLIC
1978 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1979 VkInstance instance,
1980 const char* pName)
1981 {
1982 return radv_GetInstanceProcAddr(instance, pName);
1983 }
1984
1985 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1986 VkDevice device,
1987 const char* pName)
1988 {
1989 return radv_lookup_entrypoint(pName);
1990 }
1991
1992 bool radv_get_memory_fd(struct radv_device *device,
1993 struct radv_device_memory *memory,
1994 int *pFD)
1995 {
1996 struct radeon_bo_metadata metadata;
1997
1998 if (memory->image) {
1999 radv_init_metadata(device, memory->image, &metadata);
2000 device->ws->buffer_set_metadata(memory->bo, &metadata);
2001 }
2002
2003 return device->ws->buffer_get_fd(device->ws, memory->bo,
2004 pFD);
2005 }
2006
2007 VkResult radv_AllocateMemory(
2008 VkDevice _device,
2009 const VkMemoryAllocateInfo* pAllocateInfo,
2010 const VkAllocationCallbacks* pAllocator,
2011 VkDeviceMemory* pMem)
2012 {
2013 RADV_FROM_HANDLE(radv_device, device, _device);
2014 struct radv_device_memory *mem;
2015 VkResult result;
2016 enum radeon_bo_domain domain;
2017 uint32_t flags = 0;
2018 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
2019 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2020
2021 if (pAllocateInfo->allocationSize == 0) {
2022 /* Apparently, this is allowed */
2023 *pMem = VK_NULL_HANDLE;
2024 return VK_SUCCESS;
2025 }
2026
2027 vk_foreach_struct(ext, pAllocateInfo->pNext) {
2028 switch (ext->sType) {
2029 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
2030 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
2031 break;
2032 default:
2033 break;
2034 }
2035 }
2036
2037 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2038 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2039 if (mem == NULL)
2040 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2041
2042 if (dedicate_info) {
2043 mem->image = radv_image_from_handle(dedicate_info->image);
2044 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2045 } else {
2046 mem->image = NULL;
2047 mem->buffer = NULL;
2048 }
2049
2050 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2051 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2052 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2053 domain = RADEON_DOMAIN_GTT;
2054 else
2055 domain = RADEON_DOMAIN_VRAM;
2056
2057 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2058 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2059 else
2060 flags |= RADEON_FLAG_CPU_ACCESS;
2061
2062 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2063 flags |= RADEON_FLAG_GTT_WC;
2064
2065 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2066 domain, flags);
2067
2068 if (!mem->bo) {
2069 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2070 goto fail;
2071 }
2072 mem->type_index = pAllocateInfo->memoryTypeIndex;
2073
2074 *pMem = radv_device_memory_to_handle(mem);
2075
2076 return VK_SUCCESS;
2077
2078 fail:
2079 vk_free2(&device->alloc, pAllocator, mem);
2080
2081 return result;
2082 }
2083
2084 void radv_FreeMemory(
2085 VkDevice _device,
2086 VkDeviceMemory _mem,
2087 const VkAllocationCallbacks* pAllocator)
2088 {
2089 RADV_FROM_HANDLE(radv_device, device, _device);
2090 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2091
2092 if (mem == NULL)
2093 return;
2094
2095 device->ws->buffer_destroy(mem->bo);
2096 mem->bo = NULL;
2097
2098 vk_free2(&device->alloc, pAllocator, mem);
2099 }
2100
2101 VkResult radv_MapMemory(
2102 VkDevice _device,
2103 VkDeviceMemory _memory,
2104 VkDeviceSize offset,
2105 VkDeviceSize size,
2106 VkMemoryMapFlags flags,
2107 void** ppData)
2108 {
2109 RADV_FROM_HANDLE(radv_device, device, _device);
2110 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2111
2112 if (mem == NULL) {
2113 *ppData = NULL;
2114 return VK_SUCCESS;
2115 }
2116
2117 *ppData = device->ws->buffer_map(mem->bo);
2118 if (*ppData) {
2119 *ppData += offset;
2120 return VK_SUCCESS;
2121 }
2122
2123 return VK_ERROR_MEMORY_MAP_FAILED;
2124 }
2125
2126 void radv_UnmapMemory(
2127 VkDevice _device,
2128 VkDeviceMemory _memory)
2129 {
2130 RADV_FROM_HANDLE(radv_device, device, _device);
2131 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2132
2133 if (mem == NULL)
2134 return;
2135
2136 device->ws->buffer_unmap(mem->bo);
2137 }
2138
2139 VkResult radv_FlushMappedMemoryRanges(
2140 VkDevice _device,
2141 uint32_t memoryRangeCount,
2142 const VkMappedMemoryRange* pMemoryRanges)
2143 {
2144 return VK_SUCCESS;
2145 }
2146
2147 VkResult radv_InvalidateMappedMemoryRanges(
2148 VkDevice _device,
2149 uint32_t memoryRangeCount,
2150 const VkMappedMemoryRange* pMemoryRanges)
2151 {
2152 return VK_SUCCESS;
2153 }
2154
2155 void radv_GetBufferMemoryRequirements(
2156 VkDevice device,
2157 VkBuffer _buffer,
2158 VkMemoryRequirements* pMemoryRequirements)
2159 {
2160 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2161
2162 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2163
2164 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2165 pMemoryRequirements->alignment = 4096;
2166 else
2167 pMemoryRequirements->alignment = 16;
2168
2169 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2170 }
2171
2172 void radv_GetImageMemoryRequirements(
2173 VkDevice device,
2174 VkImage _image,
2175 VkMemoryRequirements* pMemoryRequirements)
2176 {
2177 RADV_FROM_HANDLE(radv_image, image, _image);
2178
2179 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2180
2181 pMemoryRequirements->size = image->size;
2182 pMemoryRequirements->alignment = image->alignment;
2183 }
2184
2185 void radv_GetImageSparseMemoryRequirements(
2186 VkDevice device,
2187 VkImage image,
2188 uint32_t* pSparseMemoryRequirementCount,
2189 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2190 {
2191 stub();
2192 }
2193
2194 void radv_GetDeviceMemoryCommitment(
2195 VkDevice device,
2196 VkDeviceMemory memory,
2197 VkDeviceSize* pCommittedMemoryInBytes)
2198 {
2199 *pCommittedMemoryInBytes = 0;
2200 }
2201
2202 VkResult radv_BindBufferMemory(
2203 VkDevice device,
2204 VkBuffer _buffer,
2205 VkDeviceMemory _memory,
2206 VkDeviceSize memoryOffset)
2207 {
2208 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2209 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2210
2211 if (mem) {
2212 buffer->bo = mem->bo;
2213 buffer->offset = memoryOffset;
2214 } else {
2215 buffer->bo = NULL;
2216 buffer->offset = 0;
2217 }
2218
2219 return VK_SUCCESS;
2220 }
2221
2222 VkResult radv_BindImageMemory(
2223 VkDevice device,
2224 VkImage _image,
2225 VkDeviceMemory _memory,
2226 VkDeviceSize memoryOffset)
2227 {
2228 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2229 RADV_FROM_HANDLE(radv_image, image, _image);
2230
2231 if (mem) {
2232 image->bo = mem->bo;
2233 image->offset = memoryOffset;
2234 } else {
2235 image->bo = NULL;
2236 image->offset = 0;
2237 }
2238
2239 return VK_SUCCESS;
2240 }
2241
2242
2243 static void
2244 radv_sparse_buffer_bind_memory(struct radv_device *device,
2245 const VkSparseBufferMemoryBindInfo *bind)
2246 {
2247 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2248
2249 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2250 struct radv_device_memory *mem = NULL;
2251
2252 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2253 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2254
2255 device->ws->buffer_virtual_bind(buffer->bo,
2256 bind->pBinds[i].resourceOffset,
2257 bind->pBinds[i].size,
2258 mem ? mem->bo : NULL,
2259 bind->pBinds[i].memoryOffset);
2260 }
2261 }
2262
2263 static void
2264 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2265 const VkSparseImageOpaqueMemoryBindInfo *bind)
2266 {
2267 RADV_FROM_HANDLE(radv_image, image, bind->image);
2268
2269 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2270 struct radv_device_memory *mem = NULL;
2271
2272 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2273 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2274
2275 device->ws->buffer_virtual_bind(image->bo,
2276 bind->pBinds[i].resourceOffset,
2277 bind->pBinds[i].size,
2278 mem ? mem->bo : NULL,
2279 bind->pBinds[i].memoryOffset);
2280 }
2281 }
2282
2283 VkResult radv_QueueBindSparse(
2284 VkQueue _queue,
2285 uint32_t bindInfoCount,
2286 const VkBindSparseInfo* pBindInfo,
2287 VkFence _fence)
2288 {
2289 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2290 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2291 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2292 bool fence_emitted = false;
2293
2294 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2295 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2296 radv_sparse_buffer_bind_memory(queue->device,
2297 pBindInfo[i].pBufferBinds + j);
2298 }
2299
2300 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2301 radv_sparse_image_opaque_bind_memory(queue->device,
2302 pBindInfo[i].pImageOpaqueBinds + j);
2303 }
2304
2305 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2306 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2307 &queue->device->empty_cs[queue->queue_family_index],
2308 1, NULL, NULL,
2309 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2310 pBindInfo[i].waitSemaphoreCount,
2311 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2312 pBindInfo[i].signalSemaphoreCount,
2313 false, base_fence);
2314 fence_emitted = true;
2315 if (fence)
2316 fence->submitted = true;
2317 }
2318 }
2319
2320 if (fence && !fence_emitted) {
2321 fence->signalled = true;
2322 }
2323
2324 return VK_SUCCESS;
2325 }
2326
2327 VkResult radv_CreateFence(
2328 VkDevice _device,
2329 const VkFenceCreateInfo* pCreateInfo,
2330 const VkAllocationCallbacks* pAllocator,
2331 VkFence* pFence)
2332 {
2333 RADV_FROM_HANDLE(radv_device, device, _device);
2334 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2335 sizeof(*fence), 8,
2336 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2337
2338 if (!fence)
2339 return VK_ERROR_OUT_OF_HOST_MEMORY;
2340
2341 memset(fence, 0, sizeof(*fence));
2342 fence->submitted = false;
2343 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2344 fence->fence = device->ws->create_fence();
2345 if (!fence->fence) {
2346 vk_free2(&device->alloc, pAllocator, fence);
2347 return VK_ERROR_OUT_OF_HOST_MEMORY;
2348 }
2349
2350 *pFence = radv_fence_to_handle(fence);
2351
2352 return VK_SUCCESS;
2353 }
2354
2355 void radv_DestroyFence(
2356 VkDevice _device,
2357 VkFence _fence,
2358 const VkAllocationCallbacks* pAllocator)
2359 {
2360 RADV_FROM_HANDLE(radv_device, device, _device);
2361 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2362
2363 if (!fence)
2364 return;
2365 device->ws->destroy_fence(fence->fence);
2366 vk_free2(&device->alloc, pAllocator, fence);
2367 }
2368
2369 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2370 {
2371 uint64_t current_time;
2372 struct timespec tv;
2373
2374 clock_gettime(CLOCK_MONOTONIC, &tv);
2375 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2376
2377 timeout = MIN2(UINT64_MAX - current_time, timeout);
2378
2379 return current_time + timeout;
2380 }
2381
2382 VkResult radv_WaitForFences(
2383 VkDevice _device,
2384 uint32_t fenceCount,
2385 const VkFence* pFences,
2386 VkBool32 waitAll,
2387 uint64_t timeout)
2388 {
2389 RADV_FROM_HANDLE(radv_device, device, _device);
2390 timeout = radv_get_absolute_timeout(timeout);
2391
2392 if (!waitAll && fenceCount > 1) {
2393 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2394 }
2395
2396 for (uint32_t i = 0; i < fenceCount; ++i) {
2397 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2398 bool expired = false;
2399
2400 if (fence->signalled)
2401 continue;
2402
2403 if (!fence->submitted)
2404 return VK_TIMEOUT;
2405
2406 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2407 if (!expired)
2408 return VK_TIMEOUT;
2409
2410 fence->signalled = true;
2411 }
2412
2413 return VK_SUCCESS;
2414 }
2415
2416 VkResult radv_ResetFences(VkDevice device,
2417 uint32_t fenceCount,
2418 const VkFence *pFences)
2419 {
2420 for (unsigned i = 0; i < fenceCount; ++i) {
2421 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2422 fence->submitted = fence->signalled = false;
2423 }
2424
2425 return VK_SUCCESS;
2426 }
2427
2428 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2429 {
2430 RADV_FROM_HANDLE(radv_device, device, _device);
2431 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2432
2433 if (fence->signalled)
2434 return VK_SUCCESS;
2435 if (!fence->submitted)
2436 return VK_NOT_READY;
2437
2438 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2439 return VK_NOT_READY;
2440
2441 return VK_SUCCESS;
2442 }
2443
2444
2445 // Queue semaphore functions
2446
2447 VkResult radv_CreateSemaphore(
2448 VkDevice _device,
2449 const VkSemaphoreCreateInfo* pCreateInfo,
2450 const VkAllocationCallbacks* pAllocator,
2451 VkSemaphore* pSemaphore)
2452 {
2453 RADV_FROM_HANDLE(radv_device, device, _device);
2454 struct radeon_winsys_sem *sem;
2455
2456 sem = device->ws->create_sem(device->ws);
2457 if (!sem)
2458 return VK_ERROR_OUT_OF_HOST_MEMORY;
2459
2460 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2461 return VK_SUCCESS;
2462 }
2463
2464 void radv_DestroySemaphore(
2465 VkDevice _device,
2466 VkSemaphore _semaphore,
2467 const VkAllocationCallbacks* pAllocator)
2468 {
2469 RADV_FROM_HANDLE(radv_device, device, _device);
2470 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2471 if (!_semaphore)
2472 return;
2473
2474 device->ws->destroy_sem(sem);
2475 }
2476
2477 VkResult radv_CreateEvent(
2478 VkDevice _device,
2479 const VkEventCreateInfo* pCreateInfo,
2480 const VkAllocationCallbacks* pAllocator,
2481 VkEvent* pEvent)
2482 {
2483 RADV_FROM_HANDLE(radv_device, device, _device);
2484 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2485 sizeof(*event), 8,
2486 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2487
2488 if (!event)
2489 return VK_ERROR_OUT_OF_HOST_MEMORY;
2490
2491 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2492 RADEON_DOMAIN_GTT,
2493 RADEON_FLAG_CPU_ACCESS);
2494 if (!event->bo) {
2495 vk_free2(&device->alloc, pAllocator, event);
2496 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2497 }
2498
2499 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2500
2501 *pEvent = radv_event_to_handle(event);
2502
2503 return VK_SUCCESS;
2504 }
2505
2506 void radv_DestroyEvent(
2507 VkDevice _device,
2508 VkEvent _event,
2509 const VkAllocationCallbacks* pAllocator)
2510 {
2511 RADV_FROM_HANDLE(radv_device, device, _device);
2512 RADV_FROM_HANDLE(radv_event, event, _event);
2513
2514 if (!event)
2515 return;
2516 device->ws->buffer_destroy(event->bo);
2517 vk_free2(&device->alloc, pAllocator, event);
2518 }
2519
2520 VkResult radv_GetEventStatus(
2521 VkDevice _device,
2522 VkEvent _event)
2523 {
2524 RADV_FROM_HANDLE(radv_event, event, _event);
2525
2526 if (*event->map == 1)
2527 return VK_EVENT_SET;
2528 return VK_EVENT_RESET;
2529 }
2530
2531 VkResult radv_SetEvent(
2532 VkDevice _device,
2533 VkEvent _event)
2534 {
2535 RADV_FROM_HANDLE(radv_event, event, _event);
2536 *event->map = 1;
2537
2538 return VK_SUCCESS;
2539 }
2540
2541 VkResult radv_ResetEvent(
2542 VkDevice _device,
2543 VkEvent _event)
2544 {
2545 RADV_FROM_HANDLE(radv_event, event, _event);
2546 *event->map = 0;
2547
2548 return VK_SUCCESS;
2549 }
2550
2551 VkResult radv_CreateBuffer(
2552 VkDevice _device,
2553 const VkBufferCreateInfo* pCreateInfo,
2554 const VkAllocationCallbacks* pAllocator,
2555 VkBuffer* pBuffer)
2556 {
2557 RADV_FROM_HANDLE(radv_device, device, _device);
2558 struct radv_buffer *buffer;
2559
2560 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2561
2562 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2563 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2564 if (buffer == NULL)
2565 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2566
2567 buffer->size = pCreateInfo->size;
2568 buffer->usage = pCreateInfo->usage;
2569 buffer->bo = NULL;
2570 buffer->offset = 0;
2571 buffer->flags = pCreateInfo->flags;
2572
2573 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2574 buffer->bo = device->ws->buffer_create(device->ws,
2575 align64(buffer->size, 4096),
2576 4096, 0, RADEON_FLAG_VIRTUAL);
2577 if (!buffer->bo) {
2578 vk_free2(&device->alloc, pAllocator, buffer);
2579 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2580 }
2581 }
2582
2583 *pBuffer = radv_buffer_to_handle(buffer);
2584
2585 return VK_SUCCESS;
2586 }
2587
2588 void radv_DestroyBuffer(
2589 VkDevice _device,
2590 VkBuffer _buffer,
2591 const VkAllocationCallbacks* pAllocator)
2592 {
2593 RADV_FROM_HANDLE(radv_device, device, _device);
2594 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2595
2596 if (!buffer)
2597 return;
2598
2599 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2600 device->ws->buffer_destroy(buffer->bo);
2601
2602 vk_free2(&device->alloc, pAllocator, buffer);
2603 }
2604
2605 static inline unsigned
2606 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2607 {
2608 if (stencil)
2609 return image->surface.stencil_tiling_index[level];
2610 else
2611 return image->surface.tiling_index[level];
2612 }
2613
2614 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2615 {
2616 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2617 }
2618
2619 static void
2620 radv_initialise_color_surface(struct radv_device *device,
2621 struct radv_color_buffer_info *cb,
2622 struct radv_image_view *iview)
2623 {
2624 const struct vk_format_description *desc;
2625 unsigned ntype, format, swap, endian;
2626 unsigned blend_clamp = 0, blend_bypass = 0;
2627 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2628 uint64_t va;
2629 const struct radeon_surf *surf = &iview->image->surface;
2630 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2631
2632 desc = vk_format_description(iview->vk_format);
2633
2634 memset(cb, 0, sizeof(*cb));
2635
2636 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2637 va += level_info->offset;
2638 cb->cb_color_base = va >> 8;
2639
2640 /* CMASK variables */
2641 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2642 va += iview->image->cmask.offset;
2643 cb->cb_color_cmask = va >> 8;
2644 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2645
2646 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2647 va += iview->image->dcc_offset;
2648 cb->cb_dcc_base = va >> 8;
2649
2650 uint32_t max_slice = radv_surface_layer_count(iview);
2651 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2652 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2653
2654 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2655 pitch_tile_max = level_info->nblk_x / 8 - 1;
2656 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2657 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2658
2659 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2660 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2661
2662 /* Intensity is implemented as Red, so treat it that way. */
2663 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2664 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2665
2666 if (iview->image->info.samples > 1) {
2667 unsigned log_samples = util_logbase2(iview->image->info.samples);
2668
2669 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2670 S_028C74_NUM_FRAGMENTS(log_samples);
2671 }
2672
2673 if (iview->image->fmask.size) {
2674 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2675 if (device->physical_device->rad_info.chip_class >= CIK)
2676 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2677 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2678 cb->cb_color_fmask = va >> 8;
2679 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2680 } else {
2681 /* This must be set for fast clear to work without FMASK. */
2682 if (device->physical_device->rad_info.chip_class >= CIK)
2683 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2684 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2685 cb->cb_color_fmask = cb->cb_color_base;
2686 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2687 }
2688
2689 ntype = radv_translate_color_numformat(iview->vk_format,
2690 desc,
2691 vk_format_get_first_non_void_channel(iview->vk_format));
2692 format = radv_translate_colorformat(iview->vk_format);
2693 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2694 radv_finishme("Illegal color\n");
2695 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2696 endian = radv_colorformat_endian_swap(format);
2697
2698 /* blend clamp should be set for all NORM/SRGB types */
2699 if (ntype == V_028C70_NUMBER_UNORM ||
2700 ntype == V_028C70_NUMBER_SNORM ||
2701 ntype == V_028C70_NUMBER_SRGB)
2702 blend_clamp = 1;
2703
2704 /* set blend bypass according to docs if SINT/UINT or
2705 8/24 COLOR variants */
2706 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2707 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2708 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2709 blend_clamp = 0;
2710 blend_bypass = 1;
2711 }
2712 #if 0
2713 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2714 (format == V_028C70_COLOR_8 ||
2715 format == V_028C70_COLOR_8_8 ||
2716 format == V_028C70_COLOR_8_8_8_8))
2717 ->color_is_int8 = true;
2718 #endif
2719 cb->cb_color_info = S_028C70_FORMAT(format) |
2720 S_028C70_COMP_SWAP(swap) |
2721 S_028C70_BLEND_CLAMP(blend_clamp) |
2722 S_028C70_BLEND_BYPASS(blend_bypass) |
2723 S_028C70_SIMPLE_FLOAT(1) |
2724 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2725 ntype != V_028C70_NUMBER_SNORM &&
2726 ntype != V_028C70_NUMBER_SRGB &&
2727 format != V_028C70_COLOR_8_24 &&
2728 format != V_028C70_COLOR_24_8) |
2729 S_028C70_NUMBER_TYPE(ntype) |
2730 S_028C70_ENDIAN(endian);
2731 if (iview->image->info.samples > 1)
2732 if (iview->image->fmask.size)
2733 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2734
2735 if (iview->image->cmask.size &&
2736 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2737 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2738
2739 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2740 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2741
2742 if (device->physical_device->rad_info.chip_class >= VI) {
2743 unsigned max_uncompressed_block_size = 2;
2744 if (iview->image->info.samples > 1) {
2745 if (iview->image->surface.bpe == 1)
2746 max_uncompressed_block_size = 0;
2747 else if (iview->image->surface.bpe == 2)
2748 max_uncompressed_block_size = 1;
2749 }
2750
2751 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2752 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2753 }
2754
2755 /* This must be set for fast clear to work without FMASK. */
2756 if (!iview->image->fmask.size &&
2757 device->physical_device->rad_info.chip_class == SI) {
2758 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2759 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2760 }
2761 }
2762
2763 static void
2764 radv_initialise_ds_surface(struct radv_device *device,
2765 struct radv_ds_buffer_info *ds,
2766 struct radv_image_view *iview)
2767 {
2768 unsigned level = iview->base_mip;
2769 unsigned format;
2770 uint64_t va, s_offs, z_offs;
2771 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2772 bool stencil_only = false;
2773 memset(ds, 0, sizeof(*ds));
2774 switch (iview->vk_format) {
2775 case VK_FORMAT_D24_UNORM_S8_UINT:
2776 case VK_FORMAT_X8_D24_UNORM_PACK32:
2777 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2778 ds->offset_scale = 2.0f;
2779 break;
2780 case VK_FORMAT_D16_UNORM:
2781 case VK_FORMAT_D16_UNORM_S8_UINT:
2782 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2783 ds->offset_scale = 4.0f;
2784 break;
2785 case VK_FORMAT_D32_SFLOAT:
2786 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2787 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2788 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2789 ds->offset_scale = 1.0f;
2790 break;
2791 case VK_FORMAT_S8_UINT:
2792 stencil_only = true;
2793 level_info = &iview->image->surface.stencil_level[level];
2794 break;
2795 default:
2796 break;
2797 }
2798
2799 format = radv_translate_dbformat(iview->vk_format);
2800
2801 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2802 s_offs = z_offs = va;
2803 z_offs += iview->image->surface.level[level].offset;
2804 s_offs += iview->image->surface.stencil_level[level].offset;
2805
2806 uint32_t max_slice = radv_surface_layer_count(iview);
2807 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2808 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2809 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2810 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2811
2812 if (iview->image->info.samples > 1)
2813 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
2814
2815 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2816 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2817 else
2818 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2819
2820 if (device->physical_device->rad_info.chip_class >= CIK) {
2821 struct radeon_info *info = &device->physical_device->rad_info;
2822 unsigned tiling_index = iview->image->surface.tiling_index[level];
2823 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2824 unsigned macro_index = iview->image->surface.macro_tile_index;
2825 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2826 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2827 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2828
2829 if (stencil_only)
2830 tile_mode = stencil_tile_mode;
2831
2832 ds->db_depth_info |=
2833 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2834 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2835 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2836 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2837 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2838 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2839 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2840 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2841 } else {
2842 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2843 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2844 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2845 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2846 }
2847
2848 if (iview->image->surface.htile_size && !level) {
2849 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
2850
2851 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
2852 /* Use all of the htile_buffer for depth if there's no stencil. */
2853 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2854
2855 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2856 iview->image->htile_offset;
2857 ds->db_htile_data_base = va >> 8;
2858 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2859 } else {
2860 ds->db_htile_data_base = 0;
2861 ds->db_htile_surface = 0;
2862 }
2863
2864 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2865 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2866
2867 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2868 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2869 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2870 }
2871
2872 VkResult radv_CreateFramebuffer(
2873 VkDevice _device,
2874 const VkFramebufferCreateInfo* pCreateInfo,
2875 const VkAllocationCallbacks* pAllocator,
2876 VkFramebuffer* pFramebuffer)
2877 {
2878 RADV_FROM_HANDLE(radv_device, device, _device);
2879 struct radv_framebuffer *framebuffer;
2880
2881 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2882
2883 size_t size = sizeof(*framebuffer) +
2884 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2885 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2886 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2887 if (framebuffer == NULL)
2888 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2889
2890 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2891 framebuffer->width = pCreateInfo->width;
2892 framebuffer->height = pCreateInfo->height;
2893 framebuffer->layers = pCreateInfo->layers;
2894 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2895 VkImageView _iview = pCreateInfo->pAttachments[i];
2896 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2897 framebuffer->attachments[i].attachment = iview;
2898 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2899 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2900 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2901 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2902 }
2903 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2904 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2905 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2906 }
2907
2908 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2909 return VK_SUCCESS;
2910 }
2911
2912 void radv_DestroyFramebuffer(
2913 VkDevice _device,
2914 VkFramebuffer _fb,
2915 const VkAllocationCallbacks* pAllocator)
2916 {
2917 RADV_FROM_HANDLE(radv_device, device, _device);
2918 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2919
2920 if (!fb)
2921 return;
2922 vk_free2(&device->alloc, pAllocator, fb);
2923 }
2924
2925 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2926 {
2927 switch (address_mode) {
2928 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2929 return V_008F30_SQ_TEX_WRAP;
2930 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2931 return V_008F30_SQ_TEX_MIRROR;
2932 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2933 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2934 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2935 return V_008F30_SQ_TEX_CLAMP_BORDER;
2936 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2937 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2938 default:
2939 unreachable("illegal tex wrap mode");
2940 break;
2941 }
2942 }
2943
2944 static unsigned
2945 radv_tex_compare(VkCompareOp op)
2946 {
2947 switch (op) {
2948 case VK_COMPARE_OP_NEVER:
2949 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2950 case VK_COMPARE_OP_LESS:
2951 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2952 case VK_COMPARE_OP_EQUAL:
2953 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2954 case VK_COMPARE_OP_LESS_OR_EQUAL:
2955 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2956 case VK_COMPARE_OP_GREATER:
2957 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2958 case VK_COMPARE_OP_NOT_EQUAL:
2959 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2960 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2961 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2962 case VK_COMPARE_OP_ALWAYS:
2963 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2964 default:
2965 unreachable("illegal compare mode");
2966 break;
2967 }
2968 }
2969
2970 static unsigned
2971 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2972 {
2973 switch (filter) {
2974 case VK_FILTER_NEAREST:
2975 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2976 V_008F38_SQ_TEX_XY_FILTER_POINT);
2977 case VK_FILTER_LINEAR:
2978 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2979 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2980 case VK_FILTER_CUBIC_IMG:
2981 default:
2982 fprintf(stderr, "illegal texture filter");
2983 return 0;
2984 }
2985 }
2986
2987 static unsigned
2988 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2989 {
2990 switch (mode) {
2991 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2992 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2993 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2994 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2995 default:
2996 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2997 }
2998 }
2999
3000 static unsigned
3001 radv_tex_bordercolor(VkBorderColor bcolor)
3002 {
3003 switch (bcolor) {
3004 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3005 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3006 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3007 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3008 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3009 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3010 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3011 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3012 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3013 default:
3014 break;
3015 }
3016 return 0;
3017 }
3018
3019 static unsigned
3020 radv_tex_aniso_filter(unsigned filter)
3021 {
3022 if (filter < 2)
3023 return 0;
3024 if (filter < 4)
3025 return 1;
3026 if (filter < 8)
3027 return 2;
3028 if (filter < 16)
3029 return 3;
3030 return 4;
3031 }
3032
3033 static void
3034 radv_init_sampler(struct radv_device *device,
3035 struct radv_sampler *sampler,
3036 const VkSamplerCreateInfo *pCreateInfo)
3037 {
3038 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3039 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3040 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3041 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3042
3043 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3044 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3045 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3046 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3047 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3048 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3049 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3050 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3051 S_008F30_DISABLE_CUBE_WRAP(0) |
3052 S_008F30_COMPAT_MODE(is_vi));
3053 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3054 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3055 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3056 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3057 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3058 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3059 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3060 S_008F38_MIP_POINT_PRECLAMP(0) |
3061 S_008F38_DISABLE_LSB_CEIL(1) |
3062 S_008F38_FILTER_PREC_FIX(1) |
3063 S_008F38_ANISO_OVERRIDE(is_vi));
3064 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3065 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3066 }
3067
3068 VkResult radv_CreateSampler(
3069 VkDevice _device,
3070 const VkSamplerCreateInfo* pCreateInfo,
3071 const VkAllocationCallbacks* pAllocator,
3072 VkSampler* pSampler)
3073 {
3074 RADV_FROM_HANDLE(radv_device, device, _device);
3075 struct radv_sampler *sampler;
3076
3077 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3078
3079 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3080 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3081 if (!sampler)
3082 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3083
3084 radv_init_sampler(device, sampler, pCreateInfo);
3085 *pSampler = radv_sampler_to_handle(sampler);
3086
3087 return VK_SUCCESS;
3088 }
3089
3090 void radv_DestroySampler(
3091 VkDevice _device,
3092 VkSampler _sampler,
3093 const VkAllocationCallbacks* pAllocator)
3094 {
3095 RADV_FROM_HANDLE(radv_device, device, _device);
3096 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3097
3098 if (!sampler)
3099 return;
3100 vk_free2(&device->alloc, pAllocator, sampler);
3101 }
3102
3103
3104 /* vk_icd.h does not declare this function, so we declare it here to
3105 * suppress Wmissing-prototypes.
3106 */
3107 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3108 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3109
3110 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3111 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3112 {
3113 /* For the full details on loader interface versioning, see
3114 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3115 * What follows is a condensed summary, to help you navigate the large and
3116 * confusing official doc.
3117 *
3118 * - Loader interface v0 is incompatible with later versions. We don't
3119 * support it.
3120 *
3121 * - In loader interface v1:
3122 * - The first ICD entrypoint called by the loader is
3123 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3124 * entrypoint.
3125 * - The ICD must statically expose no other Vulkan symbol unless it is
3126 * linked with -Bsymbolic.
3127 * - Each dispatchable Vulkan handle created by the ICD must be
3128 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3129 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3130 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3131 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3132 * such loader-managed surfaces.
3133 *
3134 * - Loader interface v2 differs from v1 in:
3135 * - The first ICD entrypoint called by the loader is
3136 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3137 * statically expose this entrypoint.
3138 *
3139 * - Loader interface v3 differs from v2 in:
3140 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3141 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3142 * because the loader no longer does so.
3143 */
3144 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3145 return VK_SUCCESS;
3146 }