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ac: add has_rbplus to ac_gpu_info
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
194 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
195 * as they have identical property flags, and according to the
196 * spec, for types with identical flags, the one with greater
197 * performance must be given a lower index. */
198 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
199 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
200 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
201 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
202 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
203 .heapIndex = gart_index,
204 };
205 }
206 if (gart_index >= 0) {
207 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
208 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
209 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
210 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
212 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
213 .heapIndex = gart_index,
214 };
215 }
216 device->memory_properties.memoryTypeCount = type_count;
217 }
218
219 static void
220 radv_handle_env_var_force_family(struct radv_physical_device *device)
221 {
222 const char *family = getenv("RADV_FORCE_FAMILY");
223 unsigned i;
224
225 if (!family)
226 return;
227
228 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
229 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
230 /* Override family and chip_class. */
231 device->rad_info.family = i;
232
233 if (i >= CHIP_NAVI10)
234 device->rad_info.chip_class = GFX10;
235 else if (i >= CHIP_VEGA10)
236 device->rad_info.chip_class = GFX9;
237 else if (i >= CHIP_TONGA)
238 device->rad_info.chip_class = GFX8;
239 else if (i >= CHIP_BONAIRE)
240 device->rad_info.chip_class = GFX7;
241 else
242 device->rad_info.chip_class = GFX6;
243
244 return;
245 }
246 }
247
248 fprintf(stderr, "radv: Unknown family: %s\n", family);
249 exit(1);
250 }
251
252 static VkResult
253 radv_physical_device_init(struct radv_physical_device *device,
254 struct radv_instance *instance,
255 drmDevicePtr drm_device)
256 {
257 const char *path = drm_device->nodes[DRM_NODE_RENDER];
258 VkResult result;
259 drmVersionPtr version;
260 int fd;
261 int master_fd = -1;
262
263 fd = open(path, O_RDWR | O_CLOEXEC);
264 if (fd < 0) {
265 if (instance->debug_flags & RADV_DEBUG_STARTUP)
266 radv_logi("Could not open device '%s'", path);
267
268 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
269 }
270
271 version = drmGetVersion(fd);
272 if (!version) {
273 close(fd);
274
275 if (instance->debug_flags & RADV_DEBUG_STARTUP)
276 radv_logi("Could not get the kernel driver version for device '%s'", path);
277
278 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
279 "failed to get version %s: %m", path);
280 }
281
282 if (strcmp(version->name, "amdgpu")) {
283 drmFreeVersion(version);
284 close(fd);
285
286 if (instance->debug_flags & RADV_DEBUG_STARTUP)
287 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
288
289 return VK_ERROR_INCOMPATIBLE_DRIVER;
290 }
291 drmFreeVersion(version);
292
293 if (instance->debug_flags & RADV_DEBUG_STARTUP)
294 radv_logi("Found compatible device '%s'.", path);
295
296 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
297 device->instance = instance;
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
303 goto fail;
304 }
305
306 if (instance->enabled_extensions.KHR_display) {
307 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
308 if (master_fd >= 0) {
309 uint32_t accel_working = 0;
310 struct drm_amdgpu_info request = {
311 .return_pointer = (uintptr_t)&accel_working,
312 .return_size = sizeof(accel_working),
313 .query = AMDGPU_INFO_ACCEL_WORKING
314 };
315
316 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
317 close(master_fd);
318 master_fd = -1;
319 }
320 }
321 }
322
323 device->master_fd = master_fd;
324 device->local_fd = fd;
325 device->ws->query_info(device->ws, &device->rad_info);
326
327 radv_handle_env_var_force_family(device);
328
329 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
330
331 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
332 device->ws->destroy(device->ws);
333 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
334 "cannot generate UUID");
335 goto fail;
336 }
337
338 /* These flags affect shader compilation. */
339 uint64_t shader_env_flags =
340 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
341 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
342
343 /* The gpu id is already embedded in the uuid so we just pass "radv"
344 * when creating the cache.
345 */
346 char buf[VK_UUID_SIZE * 2 + 1];
347 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
348 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
349
350 if (device->rad_info.chip_class < GFX8 ||
351 device->rad_info.chip_class > GFX9)
352 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
353
354 radv_get_driver_uuid(&device->driver_uuid);
355 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
356
357 if (device->rad_info.family == CHIP_STONEY ||
358 device->rad_info.chip_class >= GFX9) {
359 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
360 device->rad_info.family == CHIP_VEGA12 ||
361 device->rad_info.family == CHIP_RAVEN ||
362 device->rad_info.family == CHIP_RAVEN2 ||
363 device->rad_info.family == CHIP_RENOIR;
364 }
365
366 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
367
368 /* Vega10/Raven need a special workaround for a hardware bug. */
369 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
370 device->rad_info.family == CHIP_RAVEN;
371
372 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
373
374 /* Out-of-order primitive rasterization. */
375 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
376 device->rad_info.max_se >= 2;
377 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
378 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
379
380 device->dcc_msaa_allowed =
381 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
382
383 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
384 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
385 (device->rad_info.chip_class >= GFX8 &&
386 device->rad_info.me_fw_feature >= 41);
387
388 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
389 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
390
391 /* Determine the number of threads per wave for all stages. */
392 device->cs_wave_size = 64;
393 device->ps_wave_size = 64;
394 device->ge_wave_size = 64;
395
396 if (device->rad_info.chip_class >= GFX10) {
397 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
398 device->cs_wave_size = 32;
399
400 /* For pixel shaders, wave64 is recommanded. */
401 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
402 device->ps_wave_size = 32;
403
404 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
405 device->ge_wave_size = 32;
406 }
407
408 radv_physical_device_init_mem_types(device);
409 radv_fill_device_extension_table(device, &device->supported_extensions);
410
411 device->bus_info = *drm_device->businfo.pci;
412
413 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
414 ac_print_gpu_info(&device->rad_info);
415
416 /* The WSI is structured as a layer on top of the driver, so this has
417 * to be the last part of initialization (at least until we get other
418 * semi-layers).
419 */
420 result = radv_init_wsi(device);
421 if (result != VK_SUCCESS) {
422 device->ws->destroy(device->ws);
423 vk_error(instance, result);
424 goto fail;
425 }
426
427 return VK_SUCCESS;
428
429 fail:
430 close(fd);
431 if (master_fd != -1)
432 close(master_fd);
433 return result;
434 }
435
436 static void
437 radv_physical_device_finish(struct radv_physical_device *device)
438 {
439 radv_finish_wsi(device);
440 device->ws->destroy(device->ws);
441 disk_cache_destroy(device->disk_cache);
442 close(device->local_fd);
443 if (device->master_fd != -1)
444 close(device->master_fd);
445 }
446
447 static void *
448 default_alloc_func(void *pUserData, size_t size, size_t align,
449 VkSystemAllocationScope allocationScope)
450 {
451 return malloc(size);
452 }
453
454 static void *
455 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
456 size_t align, VkSystemAllocationScope allocationScope)
457 {
458 return realloc(pOriginal, size);
459 }
460
461 static void
462 default_free_func(void *pUserData, void *pMemory)
463 {
464 free(pMemory);
465 }
466
467 static const VkAllocationCallbacks default_alloc = {
468 .pUserData = NULL,
469 .pfnAllocation = default_alloc_func,
470 .pfnReallocation = default_realloc_func,
471 .pfnFree = default_free_func,
472 };
473
474 static const struct debug_control radv_debug_options[] = {
475 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
476 {"nodcc", RADV_DEBUG_NO_DCC},
477 {"shaders", RADV_DEBUG_DUMP_SHADERS},
478 {"nocache", RADV_DEBUG_NO_CACHE},
479 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
480 {"nohiz", RADV_DEBUG_NO_HIZ},
481 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
482 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
483 {"allbos", RADV_DEBUG_ALL_BOS},
484 {"noibs", RADV_DEBUG_NO_IBS},
485 {"spirv", RADV_DEBUG_DUMP_SPIRV},
486 {"vmfaults", RADV_DEBUG_VM_FAULTS},
487 {"zerovram", RADV_DEBUG_ZERO_VRAM},
488 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
489 {"nosisched", RADV_DEBUG_NO_SISCHED},
490 {"preoptir", RADV_DEBUG_PREOPTIR},
491 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
492 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
493 {"info", RADV_DEBUG_INFO},
494 {"errors", RADV_DEBUG_ERRORS},
495 {"startup", RADV_DEBUG_STARTUP},
496 {"checkir", RADV_DEBUG_CHECKIR},
497 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
498 {"nobinning", RADV_DEBUG_NOBINNING},
499 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
500 {"nongg", RADV_DEBUG_NO_NGG},
501 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
502 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
503 {NULL, 0}
504 };
505
506 const char *
507 radv_get_debug_option_name(int id)
508 {
509 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
510 return radv_debug_options[id].string;
511 }
512
513 static const struct debug_control radv_perftest_options[] = {
514 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
515 {"sisched", RADV_PERFTEST_SISCHED},
516 {"localbos", RADV_PERFTEST_LOCAL_BOS},
517 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
518 {"bolist", RADV_PERFTEST_BO_LIST},
519 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
520 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
521 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
522 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
523 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
524 {NULL, 0}
525 };
526
527 const char *
528 radv_get_perftest_option_name(int id)
529 {
530 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
531 return radv_perftest_options[id].string;
532 }
533
534 static void
535 radv_handle_per_app_options(struct radv_instance *instance,
536 const VkApplicationInfo *info)
537 {
538 const char *name = info ? info->pApplicationName : NULL;
539
540 if (!name)
541 return;
542
543 if (!strcmp(name, "Talos - Linux - 32bit") ||
544 !strcmp(name, "Talos - Linux - 64bit")) {
545 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
546 /* Force enable LLVM sisched for Talos because it looks
547 * safe and it gives few more FPS.
548 */
549 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
550 }
551 } else if (!strcmp(name, "DOOM_VFR")) {
552 /* Work around a Doom VFR game bug */
553 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
554 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
555 /* Workaround for a WaW hazard when LLVM moves/merges
556 * load/store memory operations.
557 * See https://reviews.llvm.org/D61313
558 */
559 if (HAVE_LLVM < 0x900)
560 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
561 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
562 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
563 /* Force enable VK_AMD_shader_ballot because it looks
564 * safe and it gives a nice boost (+20% on Vega 56 at
565 * this time).
566 */
567 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
568 }
569 }
570 }
571
572 static int radv_get_instance_extension_index(const char *name)
573 {
574 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
575 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
576 return i;
577 }
578 return -1;
579 }
580
581 static const char radv_dri_options_xml[] =
582 DRI_CONF_BEGIN
583 DRI_CONF_SECTION_QUALITY
584 DRI_CONF_ADAPTIVE_SYNC("true")
585 DRI_CONF_SECTION_END
586 DRI_CONF_END;
587
588 static void radv_init_dri_options(struct radv_instance *instance)
589 {
590 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
591 driParseConfigFiles(&instance->dri_options,
592 &instance->available_dri_options,
593 0, "radv", NULL);
594 }
595
596 VkResult radv_CreateInstance(
597 const VkInstanceCreateInfo* pCreateInfo,
598 const VkAllocationCallbacks* pAllocator,
599 VkInstance* pInstance)
600 {
601 struct radv_instance *instance;
602 VkResult result;
603
604 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
605
606 uint32_t client_version;
607 if (pCreateInfo->pApplicationInfo &&
608 pCreateInfo->pApplicationInfo->apiVersion != 0) {
609 client_version = pCreateInfo->pApplicationInfo->apiVersion;
610 } else {
611 client_version = VK_API_VERSION_1_0;
612 }
613
614 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
615 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
616 if (!instance)
617 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
618
619 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
620
621 if (pAllocator)
622 instance->alloc = *pAllocator;
623 else
624 instance->alloc = default_alloc;
625
626 instance->apiVersion = client_version;
627 instance->physicalDeviceCount = -1;
628
629 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
630 radv_debug_options);
631
632 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
633 radv_perftest_options);
634
635
636 if (instance->debug_flags & RADV_DEBUG_STARTUP)
637 radv_logi("Created an instance");
638
639 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
640 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
641 int index = radv_get_instance_extension_index(ext_name);
642
643 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
644 vk_free2(&default_alloc, pAllocator, instance);
645 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
646 }
647
648 instance->enabled_extensions.extensions[index] = true;
649 }
650
651 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
652 if (result != VK_SUCCESS) {
653 vk_free2(&default_alloc, pAllocator, instance);
654 return vk_error(instance, result);
655 }
656
657 _mesa_locale_init();
658 glsl_type_singleton_init_or_ref();
659
660 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
661
662 radv_init_dri_options(instance);
663 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
664
665 *pInstance = radv_instance_to_handle(instance);
666
667 return VK_SUCCESS;
668 }
669
670 void radv_DestroyInstance(
671 VkInstance _instance,
672 const VkAllocationCallbacks* pAllocator)
673 {
674 RADV_FROM_HANDLE(radv_instance, instance, _instance);
675
676 if (!instance)
677 return;
678
679 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
680 radv_physical_device_finish(instance->physicalDevices + i);
681 }
682
683 VG(VALGRIND_DESTROY_MEMPOOL(instance));
684
685 glsl_type_singleton_decref();
686 _mesa_locale_fini();
687
688 driDestroyOptionCache(&instance->dri_options);
689 driDestroyOptionInfo(&instance->available_dri_options);
690
691 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
692
693 vk_free(&instance->alloc, instance);
694 }
695
696 static VkResult
697 radv_enumerate_devices(struct radv_instance *instance)
698 {
699 /* TODO: Check for more devices ? */
700 drmDevicePtr devices[8];
701 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
702 int max_devices;
703
704 instance->physicalDeviceCount = 0;
705
706 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
707
708 if (instance->debug_flags & RADV_DEBUG_STARTUP)
709 radv_logi("Found %d drm nodes", max_devices);
710
711 if (max_devices < 1)
712 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
713
714 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
715 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
716 devices[i]->bustype == DRM_BUS_PCI &&
717 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
718
719 result = radv_physical_device_init(instance->physicalDevices +
720 instance->physicalDeviceCount,
721 instance,
722 devices[i]);
723 if (result == VK_SUCCESS)
724 ++instance->physicalDeviceCount;
725 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
726 break;
727 }
728 }
729 drmFreeDevices(devices, max_devices);
730
731 return result;
732 }
733
734 VkResult radv_EnumeratePhysicalDevices(
735 VkInstance _instance,
736 uint32_t* pPhysicalDeviceCount,
737 VkPhysicalDevice* pPhysicalDevices)
738 {
739 RADV_FROM_HANDLE(radv_instance, instance, _instance);
740 VkResult result;
741
742 if (instance->physicalDeviceCount < 0) {
743 result = radv_enumerate_devices(instance);
744 if (result != VK_SUCCESS &&
745 result != VK_ERROR_INCOMPATIBLE_DRIVER)
746 return result;
747 }
748
749 if (!pPhysicalDevices) {
750 *pPhysicalDeviceCount = instance->physicalDeviceCount;
751 } else {
752 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
753 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
754 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
755 }
756
757 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
758 : VK_SUCCESS;
759 }
760
761 VkResult radv_EnumeratePhysicalDeviceGroups(
762 VkInstance _instance,
763 uint32_t* pPhysicalDeviceGroupCount,
764 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
765 {
766 RADV_FROM_HANDLE(radv_instance, instance, _instance);
767 VkResult result;
768
769 if (instance->physicalDeviceCount < 0) {
770 result = radv_enumerate_devices(instance);
771 if (result != VK_SUCCESS &&
772 result != VK_ERROR_INCOMPATIBLE_DRIVER)
773 return result;
774 }
775
776 if (!pPhysicalDeviceGroupProperties) {
777 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
778 } else {
779 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
780 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
781 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
782 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
783 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
784 }
785 }
786 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
787 : VK_SUCCESS;
788 }
789
790 void radv_GetPhysicalDeviceFeatures(
791 VkPhysicalDevice physicalDevice,
792 VkPhysicalDeviceFeatures* pFeatures)
793 {
794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
795 memset(pFeatures, 0, sizeof(*pFeatures));
796
797 *pFeatures = (VkPhysicalDeviceFeatures) {
798 .robustBufferAccess = true,
799 .fullDrawIndexUint32 = true,
800 .imageCubeArray = true,
801 .independentBlend = true,
802 .geometryShader = true,
803 .tessellationShader = true,
804 .sampleRateShading = true,
805 .dualSrcBlend = true,
806 .logicOp = true,
807 .multiDrawIndirect = true,
808 .drawIndirectFirstInstance = true,
809 .depthClamp = true,
810 .depthBiasClamp = true,
811 .fillModeNonSolid = true,
812 .depthBounds = true,
813 .wideLines = true,
814 .largePoints = true,
815 .alphaToOne = true,
816 .multiViewport = true,
817 .samplerAnisotropy = true,
818 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
819 .textureCompressionASTC_LDR = false,
820 .textureCompressionBC = true,
821 .occlusionQueryPrecise = true,
822 .pipelineStatisticsQuery = true,
823 .vertexPipelineStoresAndAtomics = true,
824 .fragmentStoresAndAtomics = true,
825 .shaderTessellationAndGeometryPointSize = true,
826 .shaderImageGatherExtended = true,
827 .shaderStorageImageExtendedFormats = true,
828 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
829 .shaderUniformBufferArrayDynamicIndexing = true,
830 .shaderSampledImageArrayDynamicIndexing = true,
831 .shaderStorageBufferArrayDynamicIndexing = true,
832 .shaderStorageImageArrayDynamicIndexing = true,
833 .shaderStorageImageReadWithoutFormat = true,
834 .shaderStorageImageWriteWithoutFormat = true,
835 .shaderClipDistance = true,
836 .shaderCullDistance = true,
837 .shaderFloat64 = true,
838 .shaderInt64 = true,
839 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
840 .sparseBinding = true,
841 .variableMultisampleRate = true,
842 .inheritedQueries = true,
843 };
844 }
845
846 void radv_GetPhysicalDeviceFeatures2(
847 VkPhysicalDevice physicalDevice,
848 VkPhysicalDeviceFeatures2 *pFeatures)
849 {
850 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
851 vk_foreach_struct(ext, pFeatures->pNext) {
852 switch (ext->sType) {
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
854 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
855 features->variablePointersStorageBuffer = true;
856 features->variablePointers = true;
857 break;
858 }
859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
860 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
861 features->multiview = true;
862 features->multiviewGeometryShader = true;
863 features->multiviewTessellationShader = true;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
867 VkPhysicalDeviceShaderDrawParametersFeatures *features =
868 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
869 features->shaderDrawParameters = true;
870 break;
871 }
872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
873 VkPhysicalDeviceProtectedMemoryFeatures *features =
874 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
875 features->protectedMemory = false;
876 break;
877 }
878 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
879 VkPhysicalDevice16BitStorageFeatures *features =
880 (VkPhysicalDevice16BitStorageFeatures*)ext;
881 bool enabled = pdevice->rad_info.chip_class >= GFX8;
882 features->storageBuffer16BitAccess = enabled;
883 features->uniformAndStorageBuffer16BitAccess = enabled;
884 features->storagePushConstant16 = enabled;
885 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
886 break;
887 }
888 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
889 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
890 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
891 features->samplerYcbcrConversion = true;
892 break;
893 }
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
895 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
896 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
897 features->shaderInputAttachmentArrayDynamicIndexing = true;
898 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
899 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
900 features->shaderUniformBufferArrayNonUniformIndexing = true;
901 features->shaderSampledImageArrayNonUniformIndexing = true;
902 features->shaderStorageBufferArrayNonUniformIndexing = true;
903 features->shaderStorageImageArrayNonUniformIndexing = true;
904 features->shaderInputAttachmentArrayNonUniformIndexing = true;
905 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
906 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
907 features->descriptorBindingUniformBufferUpdateAfterBind = true;
908 features->descriptorBindingSampledImageUpdateAfterBind = true;
909 features->descriptorBindingStorageImageUpdateAfterBind = true;
910 features->descriptorBindingStorageBufferUpdateAfterBind = true;
911 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
912 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
913 features->descriptorBindingUpdateUnusedWhilePending = true;
914 features->descriptorBindingPartiallyBound = true;
915 features->descriptorBindingVariableDescriptorCount = true;
916 features->runtimeDescriptorArray = true;
917 break;
918 }
919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
920 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
921 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
922 features->conditionalRendering = true;
923 features->inheritedConditionalRendering = false;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
927 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
928 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
929 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
930 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
931 break;
932 }
933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
934 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
935 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
936 features->transformFeedback = true;
937 features->geometryStreams = true;
938 break;
939 }
940 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
941 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
942 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
943 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
947 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
948 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
949 features->memoryPriority = VK_TRUE;
950 break;
951 }
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
953 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
954 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
955 features->bufferDeviceAddress = true;
956 features->bufferDeviceAddressCaptureReplay = false;
957 features->bufferDeviceAddressMultiDevice = false;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
961 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
962 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
963 features->depthClipEnable = true;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
967 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
968 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
969 features->hostQueryReset = true;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
973 VkPhysicalDevice8BitStorageFeaturesKHR *features =
974 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
975 bool enabled = pdevice->rad_info.chip_class >= GFX8;
976 features->storageBuffer8BitAccess = enabled;
977 features->uniformAndStorageBuffer8BitAccess = enabled;
978 features->storagePushConstant8 = enabled;
979 break;
980 }
981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
982 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
983 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
984 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8;
985 features->shaderInt8 = true;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
989 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
990 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
991 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
992 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
996 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
997 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
998
999 features->inlineUniformBlock = true;
1000 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1001 break;
1002 }
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1004 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1005 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1006 features->computeDerivativeGroupQuads = false;
1007 features->computeDerivativeGroupLinear = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1011 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1012 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1013 features->ycbcrImageArrays = true;
1014 break;
1015 }
1016 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1017 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1018 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1019 features->uniformBufferStandardLayout = true;
1020 break;
1021 }
1022 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1023 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1024 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1025 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1026 break;
1027 }
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1029 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1030 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1031 features->imagelessFramebuffer = true;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1035 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1036 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1037 features->pipelineExecutableInfo = true;
1038 break;
1039 }
1040 default:
1041 break;
1042 }
1043 }
1044 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1045 }
1046
1047 void radv_GetPhysicalDeviceProperties(
1048 VkPhysicalDevice physicalDevice,
1049 VkPhysicalDeviceProperties* pProperties)
1050 {
1051 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1052 VkSampleCountFlags sample_counts = 0xf;
1053
1054 /* make sure that the entire descriptor set is addressable with a signed
1055 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1056 * be at most 2 GiB. the combined image & samples object count as one of
1057 * both. This limit is for the pipeline layout, not for the set layout, but
1058 * there is no set limit, so we just set a pipeline limit. I don't think
1059 * any app is going to hit this soon. */
1060 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1061 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1062 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1063 32 /* sampler, largest when combined with image */ +
1064 64 /* sampled image */ +
1065 64 /* storage image */);
1066
1067 VkPhysicalDeviceLimits limits = {
1068 .maxImageDimension1D = (1 << 14),
1069 .maxImageDimension2D = (1 << 14),
1070 .maxImageDimension3D = (1 << 11),
1071 .maxImageDimensionCube = (1 << 14),
1072 .maxImageArrayLayers = (1 << 11),
1073 .maxTexelBufferElements = 128 * 1024 * 1024,
1074 .maxUniformBufferRange = UINT32_MAX,
1075 .maxStorageBufferRange = UINT32_MAX,
1076 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1077 .maxMemoryAllocationCount = UINT32_MAX,
1078 .maxSamplerAllocationCount = 64 * 1024,
1079 .bufferImageGranularity = 64, /* A cache line */
1080 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1081 .maxBoundDescriptorSets = MAX_SETS,
1082 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1083 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1084 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1085 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1086 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1087 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1088 .maxPerStageResources = max_descriptor_set_size,
1089 .maxDescriptorSetSamplers = max_descriptor_set_size,
1090 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1091 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1092 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1093 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1094 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1095 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1096 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1097 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1098 .maxVertexInputBindings = MAX_VBS,
1099 .maxVertexInputAttributeOffset = 2047,
1100 .maxVertexInputBindingStride = 2048,
1101 .maxVertexOutputComponents = 128,
1102 .maxTessellationGenerationLevel = 64,
1103 .maxTessellationPatchSize = 32,
1104 .maxTessellationControlPerVertexInputComponents = 128,
1105 .maxTessellationControlPerVertexOutputComponents = 128,
1106 .maxTessellationControlPerPatchOutputComponents = 120,
1107 .maxTessellationControlTotalOutputComponents = 4096,
1108 .maxTessellationEvaluationInputComponents = 128,
1109 .maxTessellationEvaluationOutputComponents = 128,
1110 .maxGeometryShaderInvocations = 127,
1111 .maxGeometryInputComponents = 64,
1112 .maxGeometryOutputComponents = 128,
1113 .maxGeometryOutputVertices = 256,
1114 .maxGeometryTotalOutputComponents = 1024,
1115 .maxFragmentInputComponents = 128,
1116 .maxFragmentOutputAttachments = 8,
1117 .maxFragmentDualSrcAttachments = 1,
1118 .maxFragmentCombinedOutputResources = 8,
1119 .maxComputeSharedMemorySize = 32768,
1120 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1121 .maxComputeWorkGroupInvocations = 2048,
1122 .maxComputeWorkGroupSize = {
1123 2048,
1124 2048,
1125 2048
1126 },
1127 .subPixelPrecisionBits = 8,
1128 .subTexelPrecisionBits = 8,
1129 .mipmapPrecisionBits = 8,
1130 .maxDrawIndexedIndexValue = UINT32_MAX,
1131 .maxDrawIndirectCount = UINT32_MAX,
1132 .maxSamplerLodBias = 16,
1133 .maxSamplerAnisotropy = 16,
1134 .maxViewports = MAX_VIEWPORTS,
1135 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1136 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1137 .viewportSubPixelBits = 8,
1138 .minMemoryMapAlignment = 4096, /* A page */
1139 .minTexelBufferOffsetAlignment = 1,
1140 .minUniformBufferOffsetAlignment = 4,
1141 .minStorageBufferOffsetAlignment = 4,
1142 .minTexelOffset = -32,
1143 .maxTexelOffset = 31,
1144 .minTexelGatherOffset = -32,
1145 .maxTexelGatherOffset = 31,
1146 .minInterpolationOffset = -2,
1147 .maxInterpolationOffset = 2,
1148 .subPixelInterpolationOffsetBits = 8,
1149 .maxFramebufferWidth = (1 << 14),
1150 .maxFramebufferHeight = (1 << 14),
1151 .maxFramebufferLayers = (1 << 10),
1152 .framebufferColorSampleCounts = sample_counts,
1153 .framebufferDepthSampleCounts = sample_counts,
1154 .framebufferStencilSampleCounts = sample_counts,
1155 .framebufferNoAttachmentsSampleCounts = sample_counts,
1156 .maxColorAttachments = MAX_RTS,
1157 .sampledImageColorSampleCounts = sample_counts,
1158 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1159 .sampledImageDepthSampleCounts = sample_counts,
1160 .sampledImageStencilSampleCounts = sample_counts,
1161 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1162 .maxSampleMaskWords = 1,
1163 .timestampComputeAndGraphics = true,
1164 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1165 .maxClipDistances = 8,
1166 .maxCullDistances = 8,
1167 .maxCombinedClipAndCullDistances = 8,
1168 .discreteQueuePriorities = 2,
1169 .pointSizeRange = { 0.0, 8192.0 },
1170 .lineWidthRange = { 0.0, 7.9921875 },
1171 .pointSizeGranularity = (1.0 / 8.0),
1172 .lineWidthGranularity = (1.0 / 128.0),
1173 .strictLines = false, /* FINISHME */
1174 .standardSampleLocations = true,
1175 .optimalBufferCopyOffsetAlignment = 128,
1176 .optimalBufferCopyRowPitchAlignment = 128,
1177 .nonCoherentAtomSize = 64,
1178 };
1179
1180 *pProperties = (VkPhysicalDeviceProperties) {
1181 .apiVersion = radv_physical_device_api_version(pdevice),
1182 .driverVersion = vk_get_driver_version(),
1183 .vendorID = ATI_VENDOR_ID,
1184 .deviceID = pdevice->rad_info.pci_id,
1185 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1186 .limits = limits,
1187 .sparseProperties = {0},
1188 };
1189
1190 strcpy(pProperties->deviceName, pdevice->name);
1191 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1192 }
1193
1194 void radv_GetPhysicalDeviceProperties2(
1195 VkPhysicalDevice physicalDevice,
1196 VkPhysicalDeviceProperties2 *pProperties)
1197 {
1198 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1199 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1200
1201 vk_foreach_struct(ext, pProperties->pNext) {
1202 switch (ext->sType) {
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1204 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1205 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1206 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1207 break;
1208 }
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1210 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1211 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1212 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1213 properties->deviceLUIDValid = false;
1214 break;
1215 }
1216 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1217 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1218 properties->maxMultiviewViewCount = MAX_VIEWS;
1219 properties->maxMultiviewInstanceIndex = INT_MAX;
1220 break;
1221 }
1222 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1223 VkPhysicalDevicePointClippingProperties *properties =
1224 (VkPhysicalDevicePointClippingProperties*)ext;
1225 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1229 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1230 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1231 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1232 break;
1233 }
1234 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1235 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1236 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1237 properties->minImportedHostPointerAlignment = 4096;
1238 break;
1239 }
1240 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1241 VkPhysicalDeviceSubgroupProperties *properties =
1242 (VkPhysicalDeviceSubgroupProperties*)ext;
1243 properties->subgroupSize = 64;
1244 properties->supportedStages = VK_SHADER_STAGE_ALL;
1245 properties->supportedOperations =
1246 VK_SUBGROUP_FEATURE_BASIC_BIT |
1247 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1248 VK_SUBGROUP_FEATURE_QUAD_BIT |
1249 VK_SUBGROUP_FEATURE_VOTE_BIT;
1250 if (pdevice->rad_info.chip_class >= GFX8) {
1251 properties->supportedOperations |=
1252 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1253 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1254 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1255 }
1256 properties->quadOperationsInAllStages = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1260 VkPhysicalDeviceMaintenance3Properties *properties =
1261 (VkPhysicalDeviceMaintenance3Properties*)ext;
1262 /* Make sure everything is addressable by a signed 32-bit int, and
1263 * our largest descriptors are 96 bytes. */
1264 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1265 /* Our buffer size fields allow only this much */
1266 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1267 break;
1268 }
1269 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1270 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1271 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1272 /* GFX6-8 only support single channel min/max filter. */
1273 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1274 properties->filterMinmaxSingleComponentFormats = true;
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1278 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1279 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1280
1281 /* Shader engines. */
1282 properties->shaderEngineCount =
1283 pdevice->rad_info.max_se;
1284 properties->shaderArraysPerEngineCount =
1285 pdevice->rad_info.max_sh_per_se;
1286 properties->computeUnitsPerShaderArray =
1287 pdevice->rad_info.num_good_cu_per_sh;
1288 properties->simdPerComputeUnit = 4;
1289 properties->wavefrontsPerSimd =
1290 pdevice->rad_info.family == CHIP_TONGA ||
1291 pdevice->rad_info.family == CHIP_ICELAND ||
1292 pdevice->rad_info.family == CHIP_POLARIS10 ||
1293 pdevice->rad_info.family == CHIP_POLARIS11 ||
1294 pdevice->rad_info.family == CHIP_POLARIS12 ||
1295 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1296 properties->wavefrontSize = 64;
1297
1298 /* SGPR. */
1299 properties->sgprsPerSimd =
1300 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1301 properties->minSgprAllocation =
1302 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1303 properties->maxSgprAllocation =
1304 pdevice->rad_info.family == CHIP_TONGA ||
1305 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1306 properties->sgprAllocationGranularity =
1307 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1308
1309 /* VGPR. */
1310 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1311 properties->minVgprAllocation = 4;
1312 properties->maxVgprAllocation = 256;
1313 properties->vgprAllocationGranularity = 4;
1314 break;
1315 }
1316 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1317 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1318 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1319
1320 properties->shaderCoreFeatures = 0;
1321 properties->activeComputeUnitCount =
1322 pdevice->rad_info.num_good_compute_units;
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1326 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1327 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1328 properties->maxVertexAttribDivisor = UINT32_MAX;
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1332 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1333 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1334 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1335 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1336 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1337 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1338 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1339 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1340 properties->robustBufferAccessUpdateAfterBind = false;
1341 properties->quadDivergentImplicitLod = false;
1342
1343 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1344 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1345 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1346 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1347 32 /* sampler, largest when combined with image */ +
1348 64 /* sampled image */ +
1349 64 /* storage image */);
1350 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1351 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1352 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1353 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1354 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1355 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1356 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1357 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1358 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1359 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1360 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1361 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1362 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1363 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1364 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1368 VkPhysicalDeviceProtectedMemoryProperties *properties =
1369 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1370 properties->protectedNoFault = false;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1374 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1375 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1376 properties->primitiveOverestimationSize = 0;
1377 properties->maxExtraPrimitiveOverestimationSize = 0;
1378 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1379 properties->primitiveUnderestimation = VK_FALSE;
1380 properties->conservativePointAndLineRasterization = VK_FALSE;
1381 properties->degenerateTrianglesRasterized = VK_FALSE;
1382 properties->degenerateLinesRasterized = VK_FALSE;
1383 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1384 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1388 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1389 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1390 properties->pciDomain = pdevice->bus_info.domain;
1391 properties->pciBus = pdevice->bus_info.bus;
1392 properties->pciDevice = pdevice->bus_info.dev;
1393 properties->pciFunction = pdevice->bus_info.func;
1394 break;
1395 }
1396 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1397 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1398 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1399
1400 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1401 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1402 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1403 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1404 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1405
1406 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1407 .major = 1,
1408 .minor = 1,
1409 .subminor = 2,
1410 .patch = 0,
1411 };
1412 break;
1413 }
1414 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1415 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1416 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1417 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1418 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1419 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1420 properties->maxTransformFeedbackStreamDataSize = 512;
1421 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1422 properties->maxTransformFeedbackBufferDataStride = 512;
1423 properties->transformFeedbackQueries = true;
1424 properties->transformFeedbackStreamsLinesTriangles = true;
1425 properties->transformFeedbackRasterizationStreamSelect = false;
1426 properties->transformFeedbackDraw = true;
1427 break;
1428 }
1429 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1430 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1431 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1432
1433 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1434 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1435 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1436 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1437 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1438 break;
1439 }
1440 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1441 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1442 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1443 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1444 VK_SAMPLE_COUNT_4_BIT |
1445 VK_SAMPLE_COUNT_8_BIT;
1446 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1447 properties->sampleLocationCoordinateRange[0] = 0.0f;
1448 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1449 properties->sampleLocationSubPixelBits = 4;
1450 properties->variableSampleLocations = VK_FALSE;
1451 break;
1452 }
1453 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1454 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1455 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1456
1457 /* We support all of the depth resolve modes */
1458 properties->supportedDepthResolveModes =
1459 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1460 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1461 VK_RESOLVE_MODE_MIN_BIT_KHR |
1462 VK_RESOLVE_MODE_MAX_BIT_KHR;
1463
1464 /* Average doesn't make sense for stencil so we don't support that */
1465 properties->supportedStencilResolveModes =
1466 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1467 VK_RESOLVE_MODE_MIN_BIT_KHR |
1468 VK_RESOLVE_MODE_MAX_BIT_KHR;
1469
1470 properties->independentResolveNone = VK_TRUE;
1471 properties->independentResolve = VK_TRUE;
1472 break;
1473 }
1474 default:
1475 break;
1476 }
1477 }
1478 }
1479
1480 static void radv_get_physical_device_queue_family_properties(
1481 struct radv_physical_device* pdevice,
1482 uint32_t* pCount,
1483 VkQueueFamilyProperties** pQueueFamilyProperties)
1484 {
1485 int num_queue_families = 1;
1486 int idx;
1487 if (pdevice->rad_info.num_compute_rings > 0 &&
1488 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1489 num_queue_families++;
1490
1491 if (pQueueFamilyProperties == NULL) {
1492 *pCount = num_queue_families;
1493 return;
1494 }
1495
1496 if (!*pCount)
1497 return;
1498
1499 idx = 0;
1500 if (*pCount >= 1) {
1501 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1502 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1503 VK_QUEUE_COMPUTE_BIT |
1504 VK_QUEUE_TRANSFER_BIT |
1505 VK_QUEUE_SPARSE_BINDING_BIT,
1506 .queueCount = 1,
1507 .timestampValidBits = 64,
1508 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1509 };
1510 idx++;
1511 }
1512
1513 if (pdevice->rad_info.num_compute_rings > 0 &&
1514 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1515 if (*pCount > idx) {
1516 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1517 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1518 VK_QUEUE_TRANSFER_BIT |
1519 VK_QUEUE_SPARSE_BINDING_BIT,
1520 .queueCount = pdevice->rad_info.num_compute_rings,
1521 .timestampValidBits = 64,
1522 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1523 };
1524 idx++;
1525 }
1526 }
1527 *pCount = idx;
1528 }
1529
1530 void radv_GetPhysicalDeviceQueueFamilyProperties(
1531 VkPhysicalDevice physicalDevice,
1532 uint32_t* pCount,
1533 VkQueueFamilyProperties* pQueueFamilyProperties)
1534 {
1535 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1536 if (!pQueueFamilyProperties) {
1537 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1538 return;
1539 }
1540 VkQueueFamilyProperties *properties[] = {
1541 pQueueFamilyProperties + 0,
1542 pQueueFamilyProperties + 1,
1543 pQueueFamilyProperties + 2,
1544 };
1545 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1546 assert(*pCount <= 3);
1547 }
1548
1549 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1550 VkPhysicalDevice physicalDevice,
1551 uint32_t* pCount,
1552 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1553 {
1554 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1555 if (!pQueueFamilyProperties) {
1556 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1557 return;
1558 }
1559 VkQueueFamilyProperties *properties[] = {
1560 &pQueueFamilyProperties[0].queueFamilyProperties,
1561 &pQueueFamilyProperties[1].queueFamilyProperties,
1562 &pQueueFamilyProperties[2].queueFamilyProperties,
1563 };
1564 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1565 assert(*pCount <= 3);
1566 }
1567
1568 void radv_GetPhysicalDeviceMemoryProperties(
1569 VkPhysicalDevice physicalDevice,
1570 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1571 {
1572 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1573
1574 *pMemoryProperties = physical_device->memory_properties;
1575 }
1576
1577 static void
1578 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1579 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1580 {
1581 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1582 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1583 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1584 uint64_t vram_size = radv_get_vram_size(device);
1585 uint64_t gtt_size = device->rad_info.gart_size;
1586 uint64_t heap_budget, heap_usage;
1587
1588 /* For all memory heaps, the computation of budget is as follow:
1589 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1590 *
1591 * The Vulkan spec 1.1.97 says that the budget should include any
1592 * currently allocated device memory.
1593 *
1594 * Note that the application heap usages are not really accurate (eg.
1595 * in presence of shared buffers).
1596 */
1597 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1598 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1599
1600 switch (device->mem_type_indices[i]) {
1601 case RADV_MEM_TYPE_VRAM:
1602 heap_usage = device->ws->query_value(device->ws,
1603 RADEON_ALLOCATED_VRAM);
1604
1605 heap_budget = vram_size -
1606 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1607 heap_usage;
1608
1609 memoryBudget->heapBudget[heap_index] = heap_budget;
1610 memoryBudget->heapUsage[heap_index] = heap_usage;
1611 break;
1612 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1613 heap_usage = device->ws->query_value(device->ws,
1614 RADEON_ALLOCATED_VRAM_VIS);
1615
1616 heap_budget = visible_vram_size -
1617 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1618 heap_usage;
1619
1620 memoryBudget->heapBudget[heap_index] = heap_budget;
1621 memoryBudget->heapUsage[heap_index] = heap_usage;
1622 break;
1623 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1624 heap_usage = device->ws->query_value(device->ws,
1625 RADEON_ALLOCATED_GTT);
1626
1627 heap_budget = gtt_size -
1628 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1629 heap_usage;
1630
1631 memoryBudget->heapBudget[heap_index] = heap_budget;
1632 memoryBudget->heapUsage[heap_index] = heap_usage;
1633 break;
1634 default:
1635 break;
1636 }
1637 }
1638
1639 /* The heapBudget and heapUsage values must be zero for array elements
1640 * greater than or equal to
1641 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1642 */
1643 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1644 memoryBudget->heapBudget[i] = 0;
1645 memoryBudget->heapUsage[i] = 0;
1646 }
1647 }
1648
1649 void radv_GetPhysicalDeviceMemoryProperties2(
1650 VkPhysicalDevice physicalDevice,
1651 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1652 {
1653 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1654 &pMemoryProperties->memoryProperties);
1655
1656 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1657 vk_find_struct(pMemoryProperties->pNext,
1658 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1659 if (memory_budget)
1660 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1661 }
1662
1663 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1664 VkDevice _device,
1665 VkExternalMemoryHandleTypeFlagBits handleType,
1666 const void *pHostPointer,
1667 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1668 {
1669 RADV_FROM_HANDLE(radv_device, device, _device);
1670
1671 switch (handleType)
1672 {
1673 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1674 const struct radv_physical_device *physical_device = device->physical_device;
1675 uint32_t memoryTypeBits = 0;
1676 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1677 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1678 memoryTypeBits = (1 << i);
1679 break;
1680 }
1681 }
1682 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1683 return VK_SUCCESS;
1684 }
1685 default:
1686 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1687 }
1688 }
1689
1690 static enum radeon_ctx_priority
1691 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1692 {
1693 /* Default to MEDIUM when a specific global priority isn't requested */
1694 if (!pObj)
1695 return RADEON_CTX_PRIORITY_MEDIUM;
1696
1697 switch(pObj->globalPriority) {
1698 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1699 return RADEON_CTX_PRIORITY_REALTIME;
1700 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1701 return RADEON_CTX_PRIORITY_HIGH;
1702 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1703 return RADEON_CTX_PRIORITY_MEDIUM;
1704 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1705 return RADEON_CTX_PRIORITY_LOW;
1706 default:
1707 unreachable("Illegal global priority value");
1708 return RADEON_CTX_PRIORITY_INVALID;
1709 }
1710 }
1711
1712 static int
1713 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1714 uint32_t queue_family_index, int idx,
1715 VkDeviceQueueCreateFlags flags,
1716 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1717 {
1718 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1719 queue->device = device;
1720 queue->queue_family_index = queue_family_index;
1721 queue->queue_idx = idx;
1722 queue->priority = radv_get_queue_global_priority(global_priority);
1723 queue->flags = flags;
1724
1725 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1726 if (!queue->hw_ctx)
1727 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1728
1729 return VK_SUCCESS;
1730 }
1731
1732 static void
1733 radv_queue_finish(struct radv_queue *queue)
1734 {
1735 if (queue->hw_ctx)
1736 queue->device->ws->ctx_destroy(queue->hw_ctx);
1737
1738 if (queue->initial_full_flush_preamble_cs)
1739 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1740 if (queue->initial_preamble_cs)
1741 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1742 if (queue->continue_preamble_cs)
1743 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1744 if (queue->descriptor_bo)
1745 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1746 if (queue->scratch_bo)
1747 queue->device->ws->buffer_destroy(queue->scratch_bo);
1748 if (queue->esgs_ring_bo)
1749 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1750 if (queue->gsvs_ring_bo)
1751 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1752 if (queue->tess_rings_bo)
1753 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1754 if (queue->compute_scratch_bo)
1755 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1756 }
1757
1758 static void
1759 radv_bo_list_init(struct radv_bo_list *bo_list)
1760 {
1761 pthread_mutex_init(&bo_list->mutex, NULL);
1762 bo_list->list.count = bo_list->capacity = 0;
1763 bo_list->list.bos = NULL;
1764 }
1765
1766 static void
1767 radv_bo_list_finish(struct radv_bo_list *bo_list)
1768 {
1769 free(bo_list->list.bos);
1770 pthread_mutex_destroy(&bo_list->mutex);
1771 }
1772
1773 static VkResult radv_bo_list_add(struct radv_device *device,
1774 struct radeon_winsys_bo *bo)
1775 {
1776 struct radv_bo_list *bo_list = &device->bo_list;
1777
1778 if (bo->is_local)
1779 return VK_SUCCESS;
1780
1781 if (unlikely(!device->use_global_bo_list))
1782 return VK_SUCCESS;
1783
1784 pthread_mutex_lock(&bo_list->mutex);
1785 if (bo_list->list.count == bo_list->capacity) {
1786 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1787 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1788
1789 if (!data) {
1790 pthread_mutex_unlock(&bo_list->mutex);
1791 return VK_ERROR_OUT_OF_HOST_MEMORY;
1792 }
1793
1794 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1795 bo_list->capacity = capacity;
1796 }
1797
1798 bo_list->list.bos[bo_list->list.count++] = bo;
1799 pthread_mutex_unlock(&bo_list->mutex);
1800 return VK_SUCCESS;
1801 }
1802
1803 static void radv_bo_list_remove(struct radv_device *device,
1804 struct radeon_winsys_bo *bo)
1805 {
1806 struct radv_bo_list *bo_list = &device->bo_list;
1807
1808 if (bo->is_local)
1809 return;
1810
1811 if (unlikely(!device->use_global_bo_list))
1812 return;
1813
1814 pthread_mutex_lock(&bo_list->mutex);
1815 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1816 if (bo_list->list.bos[i] == bo) {
1817 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1818 --bo_list->list.count;
1819 break;
1820 }
1821 }
1822 pthread_mutex_unlock(&bo_list->mutex);
1823 }
1824
1825 static void
1826 radv_device_init_gs_info(struct radv_device *device)
1827 {
1828 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1829 device->physical_device->rad_info.family);
1830 }
1831
1832 static int radv_get_device_extension_index(const char *name)
1833 {
1834 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1835 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1836 return i;
1837 }
1838 return -1;
1839 }
1840
1841 static int
1842 radv_get_int_debug_option(const char *name, int default_value)
1843 {
1844 const char *str;
1845 int result;
1846
1847 str = getenv(name);
1848 if (!str) {
1849 result = default_value;
1850 } else {
1851 char *endptr;
1852
1853 result = strtol(str, &endptr, 0);
1854 if (str == endptr) {
1855 /* No digits founs. */
1856 result = default_value;
1857 }
1858 }
1859
1860 return result;
1861 }
1862
1863 VkResult radv_CreateDevice(
1864 VkPhysicalDevice physicalDevice,
1865 const VkDeviceCreateInfo* pCreateInfo,
1866 const VkAllocationCallbacks* pAllocator,
1867 VkDevice* pDevice)
1868 {
1869 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1870 VkResult result;
1871 struct radv_device *device;
1872
1873 bool keep_shader_info = false;
1874
1875 /* Check enabled features */
1876 if (pCreateInfo->pEnabledFeatures) {
1877 VkPhysicalDeviceFeatures supported_features;
1878 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1879 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1880 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1881 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1882 for (uint32_t i = 0; i < num_features; i++) {
1883 if (enabled_feature[i] && !supported_feature[i])
1884 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1885 }
1886 }
1887
1888 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1889 sizeof(*device), 8,
1890 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1891 if (!device)
1892 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1893
1894 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1895 device->instance = physical_device->instance;
1896 device->physical_device = physical_device;
1897
1898 device->ws = physical_device->ws;
1899 if (pAllocator)
1900 device->alloc = *pAllocator;
1901 else
1902 device->alloc = physical_device->instance->alloc;
1903
1904 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1905 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1906 int index = radv_get_device_extension_index(ext_name);
1907 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1908 vk_free(&device->alloc, device);
1909 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1910 }
1911
1912 device->enabled_extensions.extensions[index] = true;
1913 }
1914
1915 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1916
1917 /* With update after bind we can't attach bo's to the command buffer
1918 * from the descriptor set anymore, so we have to use a global BO list.
1919 */
1920 device->use_global_bo_list =
1921 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1922 device->enabled_extensions.EXT_descriptor_indexing ||
1923 device->enabled_extensions.EXT_buffer_device_address;
1924
1925 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1926 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1927
1928 mtx_init(&device->shader_slab_mutex, mtx_plain);
1929 list_inithead(&device->shader_slabs);
1930
1931 radv_bo_list_init(&device->bo_list);
1932
1933 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1934 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1935 uint32_t qfi = queue_create->queueFamilyIndex;
1936 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1937 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1938
1939 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1940
1941 device->queues[qfi] = vk_alloc(&device->alloc,
1942 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1943 if (!device->queues[qfi]) {
1944 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1945 goto fail;
1946 }
1947
1948 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1949
1950 device->queue_count[qfi] = queue_create->queueCount;
1951
1952 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1953 result = radv_queue_init(device, &device->queues[qfi][q],
1954 qfi, q, queue_create->flags,
1955 global_priority);
1956 if (result != VK_SUCCESS)
1957 goto fail;
1958 }
1959 }
1960
1961 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1962 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1963
1964 device->dfsm_allowed = device->pbb_allowed &&
1965 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1966 device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1967 device->physical_device->rad_info.family == CHIP_RENOIR);
1968
1969 #ifdef ANDROID
1970 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1971 #endif
1972
1973 /* The maximum number of scratch waves. Scratch space isn't divided
1974 * evenly between CUs. The number is only a function of the number of CUs.
1975 * We can decrease the constant to decrease the scratch buffer size.
1976 *
1977 * sctx->scratch_waves must be >= the maximum possible size of
1978 * 1 threadgroup, so that the hw doesn't hang from being unable
1979 * to start any.
1980 *
1981 * The recommended value is 4 per CU at most. Higher numbers don't
1982 * bring much benefit, but they still occupy chip resources (think
1983 * async compute). I've seen ~2% performance difference between 4 and 32.
1984 */
1985 uint32_t max_threads_per_block = 2048;
1986 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1987 max_threads_per_block / 64);
1988
1989 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1990 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1991
1992 if (device->physical_device->rad_info.chip_class >= GFX7) {
1993 /* If the KMD allows it (there is a KMD hw register for it),
1994 * allow launching waves out-of-order.
1995 */
1996 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1997 }
1998
1999 radv_device_init_gs_info(device);
2000
2001 device->tess_offchip_block_dw_size =
2002 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2003
2004 if (getenv("RADV_TRACE_FILE")) {
2005 const char *filename = getenv("RADV_TRACE_FILE");
2006
2007 keep_shader_info = true;
2008
2009 if (!radv_init_trace(device))
2010 goto fail;
2011
2012 fprintf(stderr, "*****************************************************************************\n");
2013 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2014 fprintf(stderr, "*****************************************************************************\n");
2015
2016 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2017 radv_dump_enabled_options(device, stderr);
2018 }
2019
2020 device->keep_shader_info = keep_shader_info;
2021
2022 result = radv_device_init_meta(device);
2023 if (result != VK_SUCCESS)
2024 goto fail;
2025
2026 radv_device_init_msaa(device);
2027
2028 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2029 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2030 switch (family) {
2031 case RADV_QUEUE_GENERAL:
2032 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2033 if (device->physical_device->rad_info.drm_minor < 6) {
2034 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2035 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2036 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2037 }
2038 break;
2039 case RADV_QUEUE_COMPUTE:
2040 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2041 radeon_emit(device->empty_cs[family], 0);
2042 break;
2043 }
2044 device->ws->cs_finalize(device->empty_cs[family]);
2045 }
2046
2047 if (device->physical_device->rad_info.chip_class >= GFX7)
2048 cik_create_gfx_config(device);
2049
2050 VkPipelineCacheCreateInfo ci;
2051 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2052 ci.pNext = NULL;
2053 ci.flags = 0;
2054 ci.pInitialData = NULL;
2055 ci.initialDataSize = 0;
2056 VkPipelineCache pc;
2057 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2058 &ci, NULL, &pc);
2059 if (result != VK_SUCCESS)
2060 goto fail_meta;
2061
2062 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2063
2064 device->force_aniso =
2065 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2066 if (device->force_aniso >= 0) {
2067 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2068 1 << util_logbase2(device->force_aniso));
2069 }
2070
2071 *pDevice = radv_device_to_handle(device);
2072 return VK_SUCCESS;
2073
2074 fail_meta:
2075 radv_device_finish_meta(device);
2076 fail:
2077 radv_bo_list_finish(&device->bo_list);
2078
2079 if (device->trace_bo)
2080 device->ws->buffer_destroy(device->trace_bo);
2081
2082 if (device->gfx_init)
2083 device->ws->buffer_destroy(device->gfx_init);
2084
2085 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2086 for (unsigned q = 0; q < device->queue_count[i]; q++)
2087 radv_queue_finish(&device->queues[i][q]);
2088 if (device->queue_count[i])
2089 vk_free(&device->alloc, device->queues[i]);
2090 }
2091
2092 vk_free(&device->alloc, device);
2093 return result;
2094 }
2095
2096 void radv_DestroyDevice(
2097 VkDevice _device,
2098 const VkAllocationCallbacks* pAllocator)
2099 {
2100 RADV_FROM_HANDLE(radv_device, device, _device);
2101
2102 if (!device)
2103 return;
2104
2105 if (device->trace_bo)
2106 device->ws->buffer_destroy(device->trace_bo);
2107
2108 if (device->gfx_init)
2109 device->ws->buffer_destroy(device->gfx_init);
2110
2111 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2112 for (unsigned q = 0; q < device->queue_count[i]; q++)
2113 radv_queue_finish(&device->queues[i][q]);
2114 if (device->queue_count[i])
2115 vk_free(&device->alloc, device->queues[i]);
2116 if (device->empty_cs[i])
2117 device->ws->cs_destroy(device->empty_cs[i]);
2118 }
2119 radv_device_finish_meta(device);
2120
2121 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2122 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2123
2124 radv_destroy_shader_slabs(device);
2125
2126 radv_bo_list_finish(&device->bo_list);
2127 vk_free(&device->alloc, device);
2128 }
2129
2130 VkResult radv_EnumerateInstanceLayerProperties(
2131 uint32_t* pPropertyCount,
2132 VkLayerProperties* pProperties)
2133 {
2134 if (pProperties == NULL) {
2135 *pPropertyCount = 0;
2136 return VK_SUCCESS;
2137 }
2138
2139 /* None supported at this time */
2140 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2141 }
2142
2143 VkResult radv_EnumerateDeviceLayerProperties(
2144 VkPhysicalDevice physicalDevice,
2145 uint32_t* pPropertyCount,
2146 VkLayerProperties* pProperties)
2147 {
2148 if (pProperties == NULL) {
2149 *pPropertyCount = 0;
2150 return VK_SUCCESS;
2151 }
2152
2153 /* None supported at this time */
2154 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2155 }
2156
2157 void radv_GetDeviceQueue2(
2158 VkDevice _device,
2159 const VkDeviceQueueInfo2* pQueueInfo,
2160 VkQueue* pQueue)
2161 {
2162 RADV_FROM_HANDLE(radv_device, device, _device);
2163 struct radv_queue *queue;
2164
2165 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2166 if (pQueueInfo->flags != queue->flags) {
2167 /* From the Vulkan 1.1.70 spec:
2168 *
2169 * "The queue returned by vkGetDeviceQueue2 must have the same
2170 * flags value from this structure as that used at device
2171 * creation time in a VkDeviceQueueCreateInfo instance. If no
2172 * matching flags were specified at device creation time then
2173 * pQueue will return VK_NULL_HANDLE."
2174 */
2175 *pQueue = VK_NULL_HANDLE;
2176 return;
2177 }
2178
2179 *pQueue = radv_queue_to_handle(queue);
2180 }
2181
2182 void radv_GetDeviceQueue(
2183 VkDevice _device,
2184 uint32_t queueFamilyIndex,
2185 uint32_t queueIndex,
2186 VkQueue* pQueue)
2187 {
2188 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2189 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2190 .queueFamilyIndex = queueFamilyIndex,
2191 .queueIndex = queueIndex
2192 };
2193
2194 radv_GetDeviceQueue2(_device, &info, pQueue);
2195 }
2196
2197 static void
2198 fill_geom_tess_rings(struct radv_queue *queue,
2199 uint32_t *map,
2200 bool add_sample_positions,
2201 uint32_t esgs_ring_size,
2202 struct radeon_winsys_bo *esgs_ring_bo,
2203 uint32_t gsvs_ring_size,
2204 struct radeon_winsys_bo *gsvs_ring_bo,
2205 uint32_t tess_factor_ring_size,
2206 uint32_t tess_offchip_ring_offset,
2207 uint32_t tess_offchip_ring_size,
2208 struct radeon_winsys_bo *tess_rings_bo)
2209 {
2210 uint32_t *desc = &map[4];
2211
2212 if (esgs_ring_bo) {
2213 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2214
2215 /* stride 0, num records - size, add tid, swizzle, elsize4,
2216 index stride 64 */
2217 desc[0] = esgs_va;
2218 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2219 S_008F04_SWIZZLE_ENABLE(true);
2220 desc[2] = esgs_ring_size;
2221 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2222 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2223 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2224 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2225 S_008F0C_INDEX_STRIDE(3) |
2226 S_008F0C_ADD_TID_ENABLE(1);
2227
2228 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2229 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2230 S_008F0C_OOB_SELECT(2) |
2231 S_008F0C_RESOURCE_LEVEL(1);
2232 } else {
2233 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2235 S_008F0C_ELEMENT_SIZE(1);
2236 }
2237
2238 /* GS entry for ES->GS ring */
2239 /* stride 0, num records - size, elsize0,
2240 index stride 0 */
2241 desc[4] = esgs_va;
2242 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2243 desc[6] = esgs_ring_size;
2244 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2245 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2246 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2247 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2248
2249 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2250 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2251 S_008F0C_OOB_SELECT(2) |
2252 S_008F0C_RESOURCE_LEVEL(1);
2253 } else {
2254 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2256 }
2257 }
2258
2259 desc += 8;
2260
2261 if (gsvs_ring_bo) {
2262 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2263
2264 /* VS entry for GS->VS ring */
2265 /* stride 0, num records - size, elsize0,
2266 index stride 0 */
2267 desc[0] = gsvs_va;
2268 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2269 desc[2] = gsvs_ring_size;
2270 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2271 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2272 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2273 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2274
2275 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2276 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2277 S_008F0C_OOB_SELECT(2) |
2278 S_008F0C_RESOURCE_LEVEL(1);
2279 } else {
2280 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2281 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2282 }
2283
2284 /* stride gsvs_itemsize, num records 64
2285 elsize 4, index stride 16 */
2286 /* shader will patch stride and desc[2] */
2287 desc[4] = gsvs_va;
2288 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2289 S_008F04_SWIZZLE_ENABLE(1);
2290 desc[6] = 0;
2291 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2292 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2293 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2294 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2295 S_008F0C_INDEX_STRIDE(1) |
2296 S_008F0C_ADD_TID_ENABLE(true);
2297
2298 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2299 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2300 S_008F0C_OOB_SELECT(2) |
2301 S_008F0C_RESOURCE_LEVEL(1);
2302 } else {
2303 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2304 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2305 S_008F0C_ELEMENT_SIZE(1);
2306 }
2307
2308 }
2309
2310 desc += 8;
2311
2312 if (tess_rings_bo) {
2313 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2314 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2315
2316 desc[0] = tess_va;
2317 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2318 desc[2] = tess_factor_ring_size;
2319 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2320 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2321 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2322 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2323
2324 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2325 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2326 S_008F0C_OOB_SELECT(3) |
2327 S_008F0C_RESOURCE_LEVEL(1);
2328 } else {
2329 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2330 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2331 }
2332
2333 desc[4] = tess_offchip_va;
2334 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2335 desc[6] = tess_offchip_ring_size;
2336 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2337 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2338 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2339 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2340
2341 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2342 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2343 S_008F0C_OOB_SELECT(3) |
2344 S_008F0C_RESOURCE_LEVEL(1);
2345 } else {
2346 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2347 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2348 }
2349 }
2350
2351 desc += 8;
2352
2353 if (add_sample_positions) {
2354 /* add sample positions after all rings */
2355 memcpy(desc, queue->device->sample_locations_1x, 8);
2356 desc += 2;
2357 memcpy(desc, queue->device->sample_locations_2x, 16);
2358 desc += 4;
2359 memcpy(desc, queue->device->sample_locations_4x, 32);
2360 desc += 8;
2361 memcpy(desc, queue->device->sample_locations_8x, 64);
2362 }
2363 }
2364
2365 static unsigned
2366 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2367 {
2368 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2369 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2370 device->physical_device->rad_info.family != CHIP_STONEY;
2371 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2372 unsigned max_offchip_buffers;
2373 unsigned offchip_granularity;
2374 unsigned hs_offchip_param;
2375
2376 /*
2377 * Per RadeonSI:
2378 * This must be one less than the maximum number due to a hw limitation.
2379 * Various hardware bugs need thGFX7
2380 *
2381 * Per AMDVLK:
2382 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2383 * Gfx7 should limit max_offchip_buffers to 508
2384 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2385 *
2386 * Follow AMDVLK here.
2387 */
2388 if (device->physical_device->rad_info.chip_class >= GFX10) {
2389 max_offchip_buffers_per_se = 256;
2390 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2391 device->physical_device->rad_info.chip_class == GFX7 ||
2392 device->physical_device->rad_info.chip_class == GFX6)
2393 --max_offchip_buffers_per_se;
2394
2395 max_offchip_buffers = max_offchip_buffers_per_se *
2396 device->physical_device->rad_info.max_se;
2397
2398 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2399 * around by setting 4K granularity.
2400 */
2401 if (device->tess_offchip_block_dw_size == 4096) {
2402 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2403 offchip_granularity = V_03093C_X_4K_DWORDS;
2404 } else {
2405 assert(device->tess_offchip_block_dw_size == 8192);
2406 offchip_granularity = V_03093C_X_8K_DWORDS;
2407 }
2408
2409 switch (device->physical_device->rad_info.chip_class) {
2410 case GFX6:
2411 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2412 break;
2413 case GFX7:
2414 case GFX8:
2415 case GFX9:
2416 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2417 break;
2418 case GFX10:
2419 break;
2420 default:
2421 break;
2422 }
2423
2424 *max_offchip_buffers_p = max_offchip_buffers;
2425 if (device->physical_device->rad_info.chip_class >= GFX7) {
2426 if (device->physical_device->rad_info.chip_class >= GFX8)
2427 --max_offchip_buffers;
2428 hs_offchip_param =
2429 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2430 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2431 } else {
2432 hs_offchip_param =
2433 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2434 }
2435 return hs_offchip_param;
2436 }
2437
2438 static void
2439 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2440 struct radeon_winsys_bo *esgs_ring_bo,
2441 uint32_t esgs_ring_size,
2442 struct radeon_winsys_bo *gsvs_ring_bo,
2443 uint32_t gsvs_ring_size)
2444 {
2445 if (!esgs_ring_bo && !gsvs_ring_bo)
2446 return;
2447
2448 if (esgs_ring_bo)
2449 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2450
2451 if (gsvs_ring_bo)
2452 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2453
2454 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2455 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2456 radeon_emit(cs, esgs_ring_size >> 8);
2457 radeon_emit(cs, gsvs_ring_size >> 8);
2458 } else {
2459 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2460 radeon_emit(cs, esgs_ring_size >> 8);
2461 radeon_emit(cs, gsvs_ring_size >> 8);
2462 }
2463 }
2464
2465 static void
2466 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2467 unsigned hs_offchip_param, unsigned tf_ring_size,
2468 struct radeon_winsys_bo *tess_rings_bo)
2469 {
2470 uint64_t tf_va;
2471
2472 if (!tess_rings_bo)
2473 return;
2474
2475 tf_va = radv_buffer_get_va(tess_rings_bo);
2476
2477 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2478
2479 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2480 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2481 S_030938_SIZE(tf_ring_size / 4));
2482 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2483 tf_va >> 8);
2484
2485 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2486 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2487 S_030984_BASE_HI(tf_va >> 40));
2488 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2489 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2490 S_030944_BASE_HI(tf_va >> 40));
2491 }
2492 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2493 hs_offchip_param);
2494 } else {
2495 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2496 S_008988_SIZE(tf_ring_size / 4));
2497 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2498 tf_va >> 8);
2499 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2500 hs_offchip_param);
2501 }
2502 }
2503
2504 static void
2505 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2506 struct radeon_winsys_bo *compute_scratch_bo)
2507 {
2508 uint64_t scratch_va;
2509
2510 if (!compute_scratch_bo)
2511 return;
2512
2513 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2514
2515 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2516
2517 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2518 radeon_emit(cs, scratch_va);
2519 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2520 S_008F04_SWIZZLE_ENABLE(1));
2521 }
2522
2523 static void
2524 radv_emit_global_shader_pointers(struct radv_queue *queue,
2525 struct radeon_cmdbuf *cs,
2526 struct radeon_winsys_bo *descriptor_bo)
2527 {
2528 uint64_t va;
2529
2530 if (!descriptor_bo)
2531 return;
2532
2533 va = radv_buffer_get_va(descriptor_bo);
2534
2535 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2536
2537 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2538 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2539 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2540 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2541 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2542
2543 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2544 radv_emit_shader_pointer(queue->device, cs, regs[i],
2545 va, true);
2546 }
2547 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2548 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2549 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2550 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2551 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2552
2553 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2554 radv_emit_shader_pointer(queue->device, cs, regs[i],
2555 va, true);
2556 }
2557 } else {
2558 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2559 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2560 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2561 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2562 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2563 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2564
2565 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2566 radv_emit_shader_pointer(queue->device, cs, regs[i],
2567 va, true);
2568 }
2569 }
2570 }
2571
2572 static void
2573 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2574 {
2575 struct radv_device *device = queue->device;
2576
2577 if (device->gfx_init) {
2578 uint64_t va = radv_buffer_get_va(device->gfx_init);
2579
2580 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2581 radeon_emit(cs, va);
2582 radeon_emit(cs, va >> 32);
2583 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2584
2585 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2586 } else {
2587 struct radv_physical_device *physical_device = device->physical_device;
2588 si_emit_graphics(physical_device, cs);
2589 }
2590 }
2591
2592 static void
2593 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2594 {
2595 struct radv_physical_device *physical_device = queue->device->physical_device;
2596 si_emit_compute(physical_device, cs);
2597 }
2598
2599 static VkResult
2600 radv_get_preamble_cs(struct radv_queue *queue,
2601 uint32_t scratch_size,
2602 uint32_t compute_scratch_size,
2603 uint32_t esgs_ring_size,
2604 uint32_t gsvs_ring_size,
2605 bool needs_tess_rings,
2606 bool needs_sample_positions,
2607 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2608 struct radeon_cmdbuf **initial_preamble_cs,
2609 struct radeon_cmdbuf **continue_preamble_cs)
2610 {
2611 struct radeon_winsys_bo *scratch_bo = NULL;
2612 struct radeon_winsys_bo *descriptor_bo = NULL;
2613 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2614 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2615 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2616 struct radeon_winsys_bo *tess_rings_bo = NULL;
2617 struct radeon_cmdbuf *dest_cs[3] = {0};
2618 bool add_tess_rings = false, add_sample_positions = false;
2619 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2620 unsigned max_offchip_buffers;
2621 unsigned hs_offchip_param = 0;
2622 unsigned tess_offchip_ring_offset;
2623 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2624 if (!queue->has_tess_rings) {
2625 if (needs_tess_rings)
2626 add_tess_rings = true;
2627 }
2628 if (!queue->has_sample_positions) {
2629 if (needs_sample_positions)
2630 add_sample_positions = true;
2631 }
2632 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2633 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2634 &max_offchip_buffers);
2635 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2636 tess_offchip_ring_size = max_offchip_buffers *
2637 queue->device->tess_offchip_block_dw_size * 4;
2638
2639 if (scratch_size <= queue->scratch_size &&
2640 compute_scratch_size <= queue->compute_scratch_size &&
2641 esgs_ring_size <= queue->esgs_ring_size &&
2642 gsvs_ring_size <= queue->gsvs_ring_size &&
2643 !add_tess_rings && !add_sample_positions &&
2644 queue->initial_preamble_cs) {
2645 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2646 *initial_preamble_cs = queue->initial_preamble_cs;
2647 *continue_preamble_cs = queue->continue_preamble_cs;
2648 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2649 *continue_preamble_cs = NULL;
2650 return VK_SUCCESS;
2651 }
2652
2653 if (scratch_size > queue->scratch_size) {
2654 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2655 scratch_size,
2656 4096,
2657 RADEON_DOMAIN_VRAM,
2658 ring_bo_flags,
2659 RADV_BO_PRIORITY_SCRATCH);
2660 if (!scratch_bo)
2661 goto fail;
2662 } else
2663 scratch_bo = queue->scratch_bo;
2664
2665 if (compute_scratch_size > queue->compute_scratch_size) {
2666 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2667 compute_scratch_size,
2668 4096,
2669 RADEON_DOMAIN_VRAM,
2670 ring_bo_flags,
2671 RADV_BO_PRIORITY_SCRATCH);
2672 if (!compute_scratch_bo)
2673 goto fail;
2674
2675 } else
2676 compute_scratch_bo = queue->compute_scratch_bo;
2677
2678 if (esgs_ring_size > queue->esgs_ring_size) {
2679 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2680 esgs_ring_size,
2681 4096,
2682 RADEON_DOMAIN_VRAM,
2683 ring_bo_flags,
2684 RADV_BO_PRIORITY_SCRATCH);
2685 if (!esgs_ring_bo)
2686 goto fail;
2687 } else {
2688 esgs_ring_bo = queue->esgs_ring_bo;
2689 esgs_ring_size = queue->esgs_ring_size;
2690 }
2691
2692 if (gsvs_ring_size > queue->gsvs_ring_size) {
2693 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2694 gsvs_ring_size,
2695 4096,
2696 RADEON_DOMAIN_VRAM,
2697 ring_bo_flags,
2698 RADV_BO_PRIORITY_SCRATCH);
2699 if (!gsvs_ring_bo)
2700 goto fail;
2701 } else {
2702 gsvs_ring_bo = queue->gsvs_ring_bo;
2703 gsvs_ring_size = queue->gsvs_ring_size;
2704 }
2705
2706 if (add_tess_rings) {
2707 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2708 tess_offchip_ring_offset + tess_offchip_ring_size,
2709 256,
2710 RADEON_DOMAIN_VRAM,
2711 ring_bo_flags,
2712 RADV_BO_PRIORITY_SCRATCH);
2713 if (!tess_rings_bo)
2714 goto fail;
2715 } else {
2716 tess_rings_bo = queue->tess_rings_bo;
2717 }
2718
2719 if (scratch_bo != queue->scratch_bo ||
2720 esgs_ring_bo != queue->esgs_ring_bo ||
2721 gsvs_ring_bo != queue->gsvs_ring_bo ||
2722 tess_rings_bo != queue->tess_rings_bo ||
2723 add_sample_positions) {
2724 uint32_t size = 0;
2725 if (gsvs_ring_bo || esgs_ring_bo ||
2726 tess_rings_bo || add_sample_positions) {
2727 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2728 if (add_sample_positions)
2729 size += 128; /* 64+32+16+8 = 120 bytes */
2730 }
2731 else if (scratch_bo)
2732 size = 8; /* 2 dword */
2733
2734 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2735 size,
2736 4096,
2737 RADEON_DOMAIN_VRAM,
2738 RADEON_FLAG_CPU_ACCESS |
2739 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2740 RADEON_FLAG_READ_ONLY,
2741 RADV_BO_PRIORITY_DESCRIPTOR);
2742 if (!descriptor_bo)
2743 goto fail;
2744 } else
2745 descriptor_bo = queue->descriptor_bo;
2746
2747 if (descriptor_bo != queue->descriptor_bo) {
2748 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2749
2750 if (scratch_bo) {
2751 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2752 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2753 S_008F04_SWIZZLE_ENABLE(1);
2754 map[0] = scratch_va;
2755 map[1] = rsrc1;
2756 }
2757
2758 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2759 fill_geom_tess_rings(queue, map, add_sample_positions,
2760 esgs_ring_size, esgs_ring_bo,
2761 gsvs_ring_size, gsvs_ring_bo,
2762 tess_factor_ring_size,
2763 tess_offchip_ring_offset,
2764 tess_offchip_ring_size,
2765 tess_rings_bo);
2766
2767 queue->device->ws->buffer_unmap(descriptor_bo);
2768 }
2769
2770 for(int i = 0; i < 3; ++i) {
2771 struct radeon_cmdbuf *cs = NULL;
2772 cs = queue->device->ws->cs_create(queue->device->ws,
2773 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2774 if (!cs)
2775 goto fail;
2776
2777 dest_cs[i] = cs;
2778
2779 if (scratch_bo)
2780 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2781
2782 /* Emit initial configuration. */
2783 switch (queue->queue_family_index) {
2784 case RADV_QUEUE_GENERAL:
2785 radv_init_graphics_state(cs, queue);
2786 break;
2787 case RADV_QUEUE_COMPUTE:
2788 radv_init_compute_state(cs, queue);
2789 break;
2790 case RADV_QUEUE_TRANSFER:
2791 break;
2792 }
2793
2794 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2795 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2796 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2797
2798 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2799 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2800 }
2801
2802 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2803 gsvs_ring_bo, gsvs_ring_size);
2804 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2805 tess_factor_ring_size, tess_rings_bo);
2806 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2807 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2808
2809 if (i == 0) {
2810 si_cs_emit_cache_flush(cs,
2811 queue->device->physical_device->rad_info.chip_class,
2812 NULL, 0,
2813 queue->queue_family_index == RING_COMPUTE &&
2814 queue->device->physical_device->rad_info.chip_class >= GFX7,
2815 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2816 RADV_CMD_FLAG_INV_ICACHE |
2817 RADV_CMD_FLAG_INV_SCACHE |
2818 RADV_CMD_FLAG_INV_VCACHE |
2819 RADV_CMD_FLAG_INV_L2 |
2820 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2821 } else if (i == 1) {
2822 si_cs_emit_cache_flush(cs,
2823 queue->device->physical_device->rad_info.chip_class,
2824 NULL, 0,
2825 queue->queue_family_index == RING_COMPUTE &&
2826 queue->device->physical_device->rad_info.chip_class >= GFX7,
2827 RADV_CMD_FLAG_INV_ICACHE |
2828 RADV_CMD_FLAG_INV_SCACHE |
2829 RADV_CMD_FLAG_INV_VCACHE |
2830 RADV_CMD_FLAG_INV_L2 |
2831 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2832 }
2833
2834 if (!queue->device->ws->cs_finalize(cs))
2835 goto fail;
2836 }
2837
2838 if (queue->initial_full_flush_preamble_cs)
2839 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2840
2841 if (queue->initial_preamble_cs)
2842 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2843
2844 if (queue->continue_preamble_cs)
2845 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2846
2847 queue->initial_full_flush_preamble_cs = dest_cs[0];
2848 queue->initial_preamble_cs = dest_cs[1];
2849 queue->continue_preamble_cs = dest_cs[2];
2850
2851 if (scratch_bo != queue->scratch_bo) {
2852 if (queue->scratch_bo)
2853 queue->device->ws->buffer_destroy(queue->scratch_bo);
2854 queue->scratch_bo = scratch_bo;
2855 queue->scratch_size = scratch_size;
2856 }
2857
2858 if (compute_scratch_bo != queue->compute_scratch_bo) {
2859 if (queue->compute_scratch_bo)
2860 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2861 queue->compute_scratch_bo = compute_scratch_bo;
2862 queue->compute_scratch_size = compute_scratch_size;
2863 }
2864
2865 if (esgs_ring_bo != queue->esgs_ring_bo) {
2866 if (queue->esgs_ring_bo)
2867 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2868 queue->esgs_ring_bo = esgs_ring_bo;
2869 queue->esgs_ring_size = esgs_ring_size;
2870 }
2871
2872 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2873 if (queue->gsvs_ring_bo)
2874 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2875 queue->gsvs_ring_bo = gsvs_ring_bo;
2876 queue->gsvs_ring_size = gsvs_ring_size;
2877 }
2878
2879 if (tess_rings_bo != queue->tess_rings_bo) {
2880 queue->tess_rings_bo = tess_rings_bo;
2881 queue->has_tess_rings = true;
2882 }
2883
2884 if (descriptor_bo != queue->descriptor_bo) {
2885 if (queue->descriptor_bo)
2886 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2887
2888 queue->descriptor_bo = descriptor_bo;
2889 }
2890
2891 if (add_sample_positions)
2892 queue->has_sample_positions = true;
2893
2894 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2895 *initial_preamble_cs = queue->initial_preamble_cs;
2896 *continue_preamble_cs = queue->continue_preamble_cs;
2897 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2898 *continue_preamble_cs = NULL;
2899 return VK_SUCCESS;
2900 fail:
2901 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2902 if (dest_cs[i])
2903 queue->device->ws->cs_destroy(dest_cs[i]);
2904 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2905 queue->device->ws->buffer_destroy(descriptor_bo);
2906 if (scratch_bo && scratch_bo != queue->scratch_bo)
2907 queue->device->ws->buffer_destroy(scratch_bo);
2908 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2909 queue->device->ws->buffer_destroy(compute_scratch_bo);
2910 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2911 queue->device->ws->buffer_destroy(esgs_ring_bo);
2912 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2913 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2914 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2915 queue->device->ws->buffer_destroy(tess_rings_bo);
2916 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2917 }
2918
2919 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2920 struct radv_winsys_sem_counts *counts,
2921 int num_sems,
2922 const VkSemaphore *sems,
2923 VkFence _fence,
2924 bool reset_temp)
2925 {
2926 int syncobj_idx = 0, sem_idx = 0;
2927
2928 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2929 return VK_SUCCESS;
2930
2931 for (uint32_t i = 0; i < num_sems; i++) {
2932 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2933
2934 if (sem->temp_syncobj || sem->syncobj)
2935 counts->syncobj_count++;
2936 else
2937 counts->sem_count++;
2938 }
2939
2940 if (_fence != VK_NULL_HANDLE) {
2941 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2942 if (fence->temp_syncobj || fence->syncobj)
2943 counts->syncobj_count++;
2944 }
2945
2946 if (counts->syncobj_count) {
2947 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2948 if (!counts->syncobj)
2949 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2950 }
2951
2952 if (counts->sem_count) {
2953 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2954 if (!counts->sem) {
2955 free(counts->syncobj);
2956 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2957 }
2958 }
2959
2960 for (uint32_t i = 0; i < num_sems; i++) {
2961 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2962
2963 if (sem->temp_syncobj) {
2964 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2965 }
2966 else if (sem->syncobj)
2967 counts->syncobj[syncobj_idx++] = sem->syncobj;
2968 else {
2969 assert(sem->sem);
2970 counts->sem[sem_idx++] = sem->sem;
2971 }
2972 }
2973
2974 if (_fence != VK_NULL_HANDLE) {
2975 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2976 if (fence->temp_syncobj)
2977 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2978 else if (fence->syncobj)
2979 counts->syncobj[syncobj_idx++] = fence->syncobj;
2980 }
2981
2982 return VK_SUCCESS;
2983 }
2984
2985 static void
2986 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2987 {
2988 free(sem_info->wait.syncobj);
2989 free(sem_info->wait.sem);
2990 free(sem_info->signal.syncobj);
2991 free(sem_info->signal.sem);
2992 }
2993
2994
2995 static void radv_free_temp_syncobjs(struct radv_device *device,
2996 int num_sems,
2997 const VkSemaphore *sems)
2998 {
2999 for (uint32_t i = 0; i < num_sems; i++) {
3000 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3001
3002 if (sem->temp_syncobj) {
3003 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
3004 sem->temp_syncobj = 0;
3005 }
3006 }
3007 }
3008
3009 static VkResult
3010 radv_alloc_sem_info(struct radv_instance *instance,
3011 struct radv_winsys_sem_info *sem_info,
3012 int num_wait_sems,
3013 const VkSemaphore *wait_sems,
3014 int num_signal_sems,
3015 const VkSemaphore *signal_sems,
3016 VkFence fence)
3017 {
3018 VkResult ret;
3019 memset(sem_info, 0, sizeof(*sem_info));
3020
3021 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3022 if (ret)
3023 return ret;
3024 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3025 if (ret)
3026 radv_free_sem_info(sem_info);
3027
3028 /* caller can override these */
3029 sem_info->cs_emit_wait = true;
3030 sem_info->cs_emit_signal = true;
3031 return ret;
3032 }
3033
3034 /* Signals fence as soon as all the work currently put on queue is done. */
3035 static VkResult radv_signal_fence(struct radv_queue *queue,
3036 struct radv_fence *fence)
3037 {
3038 int ret;
3039 VkResult result;
3040 struct radv_winsys_sem_info sem_info;
3041
3042 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3043 radv_fence_to_handle(fence));
3044 if (result != VK_SUCCESS)
3045 return result;
3046
3047 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3048 &queue->device->empty_cs[queue->queue_family_index],
3049 1, NULL, NULL, &sem_info, NULL,
3050 false, fence->fence);
3051 radv_free_sem_info(&sem_info);
3052
3053 if (ret)
3054 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3055
3056 return VK_SUCCESS;
3057 }
3058
3059 VkResult radv_QueueSubmit(
3060 VkQueue _queue,
3061 uint32_t submitCount,
3062 const VkSubmitInfo* pSubmits,
3063 VkFence _fence)
3064 {
3065 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3066 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3067 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3068 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3069 int ret;
3070 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3071 uint32_t scratch_size = 0;
3072 uint32_t compute_scratch_size = 0;
3073 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3074 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3075 VkResult result;
3076 bool fence_emitted = false;
3077 bool tess_rings_needed = false;
3078 bool sample_positions_needed = false;
3079
3080 /* Do this first so failing to allocate scratch buffers can't result in
3081 * partially executed submissions. */
3082 for (uint32_t i = 0; i < submitCount; i++) {
3083 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3084 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3085 pSubmits[i].pCommandBuffers[j]);
3086
3087 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3088 compute_scratch_size = MAX2(compute_scratch_size,
3089 cmd_buffer->compute_scratch_size_needed);
3090 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3091 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3092 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3093 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3094 }
3095 }
3096
3097 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3098 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3099 sample_positions_needed, &initial_flush_preamble_cs,
3100 &initial_preamble_cs, &continue_preamble_cs);
3101 if (result != VK_SUCCESS)
3102 return result;
3103
3104 for (uint32_t i = 0; i < submitCount; i++) {
3105 struct radeon_cmdbuf **cs_array;
3106 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3107 bool can_patch = true;
3108 uint32_t advance;
3109 struct radv_winsys_sem_info sem_info;
3110
3111 result = radv_alloc_sem_info(queue->device->instance,
3112 &sem_info,
3113 pSubmits[i].waitSemaphoreCount,
3114 pSubmits[i].pWaitSemaphores,
3115 pSubmits[i].signalSemaphoreCount,
3116 pSubmits[i].pSignalSemaphores,
3117 _fence);
3118 if (result != VK_SUCCESS)
3119 return result;
3120
3121 if (!pSubmits[i].commandBufferCount) {
3122 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3123 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3124 &queue->device->empty_cs[queue->queue_family_index],
3125 1, NULL, NULL,
3126 &sem_info, NULL,
3127 false, base_fence);
3128 if (ret) {
3129 radv_loge("failed to submit CS %d\n", i);
3130 abort();
3131 }
3132 fence_emitted = true;
3133 }
3134 radv_free_sem_info(&sem_info);
3135 continue;
3136 }
3137
3138 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3139 (pSubmits[i].commandBufferCount));
3140
3141 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3143 pSubmits[i].pCommandBuffers[j]);
3144 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3145
3146 cs_array[j] = cmd_buffer->cs;
3147 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3148 can_patch = false;
3149
3150 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3151 }
3152
3153 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3154 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3155 const struct radv_winsys_bo_list *bo_list = NULL;
3156
3157 advance = MIN2(max_cs_submission,
3158 pSubmits[i].commandBufferCount - j);
3159
3160 if (queue->device->trace_bo)
3161 *queue->device->trace_id_ptr = 0;
3162
3163 sem_info.cs_emit_wait = j == 0;
3164 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3165
3166 if (unlikely(queue->device->use_global_bo_list)) {
3167 pthread_mutex_lock(&queue->device->bo_list.mutex);
3168 bo_list = &queue->device->bo_list.list;
3169 }
3170
3171 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3172 advance, initial_preamble, continue_preamble_cs,
3173 &sem_info, bo_list,
3174 can_patch, base_fence);
3175
3176 if (unlikely(queue->device->use_global_bo_list))
3177 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3178
3179 if (ret) {
3180 radv_loge("failed to submit CS %d\n", i);
3181 abort();
3182 }
3183 fence_emitted = true;
3184 if (queue->device->trace_bo) {
3185 radv_check_gpu_hangs(queue, cs_array[j]);
3186 }
3187 }
3188
3189 radv_free_temp_syncobjs(queue->device,
3190 pSubmits[i].waitSemaphoreCount,
3191 pSubmits[i].pWaitSemaphores);
3192 radv_free_sem_info(&sem_info);
3193 free(cs_array);
3194 }
3195
3196 if (fence) {
3197 if (!fence_emitted) {
3198 result = radv_signal_fence(queue, fence);
3199 if (result != VK_SUCCESS)
3200 return result;
3201 }
3202 }
3203
3204 return VK_SUCCESS;
3205 }
3206
3207 VkResult radv_QueueWaitIdle(
3208 VkQueue _queue)
3209 {
3210 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3211
3212 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3213 radv_queue_family_to_ring(queue->queue_family_index),
3214 queue->queue_idx);
3215 return VK_SUCCESS;
3216 }
3217
3218 VkResult radv_DeviceWaitIdle(
3219 VkDevice _device)
3220 {
3221 RADV_FROM_HANDLE(radv_device, device, _device);
3222
3223 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3224 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3225 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3226 }
3227 }
3228 return VK_SUCCESS;
3229 }
3230
3231 VkResult radv_EnumerateInstanceExtensionProperties(
3232 const char* pLayerName,
3233 uint32_t* pPropertyCount,
3234 VkExtensionProperties* pProperties)
3235 {
3236 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3237
3238 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3239 if (radv_supported_instance_extensions.extensions[i]) {
3240 vk_outarray_append(&out, prop) {
3241 *prop = radv_instance_extensions[i];
3242 }
3243 }
3244 }
3245
3246 return vk_outarray_status(&out);
3247 }
3248
3249 VkResult radv_EnumerateDeviceExtensionProperties(
3250 VkPhysicalDevice physicalDevice,
3251 const char* pLayerName,
3252 uint32_t* pPropertyCount,
3253 VkExtensionProperties* pProperties)
3254 {
3255 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3256 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3257
3258 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3259 if (device->supported_extensions.extensions[i]) {
3260 vk_outarray_append(&out, prop) {
3261 *prop = radv_device_extensions[i];
3262 }
3263 }
3264 }
3265
3266 return vk_outarray_status(&out);
3267 }
3268
3269 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3270 VkInstance _instance,
3271 const char* pName)
3272 {
3273 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3274 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3275
3276 if (unchecked) {
3277 return radv_lookup_entrypoint_unchecked(pName);
3278 } else {
3279 return radv_lookup_entrypoint_checked(pName,
3280 instance ? instance->apiVersion : 0,
3281 instance ? &instance->enabled_extensions : NULL,
3282 NULL);
3283 }
3284 }
3285
3286 /* The loader wants us to expose a second GetInstanceProcAddr function
3287 * to work around certain LD_PRELOAD issues seen in apps.
3288 */
3289 PUBLIC
3290 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3291 VkInstance instance,
3292 const char* pName);
3293
3294 PUBLIC
3295 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3296 VkInstance instance,
3297 const char* pName)
3298 {
3299 return radv_GetInstanceProcAddr(instance, pName);
3300 }
3301
3302 PUBLIC
3303 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3304 VkInstance _instance,
3305 const char* pName);
3306
3307 PUBLIC
3308 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3309 VkInstance _instance,
3310 const char* pName)
3311 {
3312 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3313
3314 return radv_lookup_physical_device_entrypoint_checked(pName,
3315 instance ? instance->apiVersion : 0,
3316 instance ? &instance->enabled_extensions : NULL);
3317 }
3318
3319 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3320 VkDevice _device,
3321 const char* pName)
3322 {
3323 RADV_FROM_HANDLE(radv_device, device, _device);
3324 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3325
3326 if (unchecked) {
3327 return radv_lookup_entrypoint_unchecked(pName);
3328 } else {
3329 return radv_lookup_entrypoint_checked(pName,
3330 device->instance->apiVersion,
3331 &device->instance->enabled_extensions,
3332 &device->enabled_extensions);
3333 }
3334 }
3335
3336 bool radv_get_memory_fd(struct radv_device *device,
3337 struct radv_device_memory *memory,
3338 int *pFD)
3339 {
3340 struct radeon_bo_metadata metadata;
3341
3342 if (memory->image) {
3343 radv_init_metadata(device, memory->image, &metadata);
3344 device->ws->buffer_set_metadata(memory->bo, &metadata);
3345 }
3346
3347 return device->ws->buffer_get_fd(device->ws, memory->bo,
3348 pFD);
3349 }
3350
3351 static VkResult radv_alloc_memory(struct radv_device *device,
3352 const VkMemoryAllocateInfo* pAllocateInfo,
3353 const VkAllocationCallbacks* pAllocator,
3354 VkDeviceMemory* pMem)
3355 {
3356 struct radv_device_memory *mem;
3357 VkResult result;
3358 enum radeon_bo_domain domain;
3359 uint32_t flags = 0;
3360 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3361
3362 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3363
3364 if (pAllocateInfo->allocationSize == 0) {
3365 /* Apparently, this is allowed */
3366 *pMem = VK_NULL_HANDLE;
3367 return VK_SUCCESS;
3368 }
3369
3370 const VkImportMemoryFdInfoKHR *import_info =
3371 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3372 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3373 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3374 const VkExportMemoryAllocateInfo *export_info =
3375 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3376 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3377 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3378
3379 const struct wsi_memory_allocate_info *wsi_info =
3380 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3381
3382 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3383 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3384 if (mem == NULL)
3385 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3386
3387 if (wsi_info && wsi_info->implicit_sync)
3388 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3389
3390 if (dedicate_info) {
3391 mem->image = radv_image_from_handle(dedicate_info->image);
3392 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3393 } else {
3394 mem->image = NULL;
3395 mem->buffer = NULL;
3396 }
3397
3398 float priority_float = 0.5;
3399 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3400 vk_find_struct_const(pAllocateInfo->pNext,
3401 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3402 if (priority_ext)
3403 priority_float = priority_ext->priority;
3404
3405 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3406 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3407
3408 mem->user_ptr = NULL;
3409
3410 if (import_info) {
3411 assert(import_info->handleType ==
3412 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3413 import_info->handleType ==
3414 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3415 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3416 priority, NULL, NULL);
3417 if (!mem->bo) {
3418 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3419 goto fail;
3420 } else {
3421 close(import_info->fd);
3422 }
3423 } else if (host_ptr_info) {
3424 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3425 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3426 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3427 pAllocateInfo->allocationSize,
3428 priority);
3429 if (!mem->bo) {
3430 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3431 goto fail;
3432 } else {
3433 mem->user_ptr = host_ptr_info->pHostPointer;
3434 }
3435 } else {
3436 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3437 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3438 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3439 domain = RADEON_DOMAIN_GTT;
3440 else
3441 domain = RADEON_DOMAIN_VRAM;
3442
3443 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3444 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3445 else
3446 flags |= RADEON_FLAG_CPU_ACCESS;
3447
3448 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3449 flags |= RADEON_FLAG_GTT_WC;
3450
3451 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3452 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3453 if (device->use_global_bo_list) {
3454 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3455 }
3456 }
3457
3458 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3459 domain, flags, priority);
3460
3461 if (!mem->bo) {
3462 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3463 goto fail;
3464 }
3465 mem->type_index = mem_type_index;
3466 }
3467
3468 result = radv_bo_list_add(device, mem->bo);
3469 if (result != VK_SUCCESS)
3470 goto fail_bo;
3471
3472 *pMem = radv_device_memory_to_handle(mem);
3473
3474 return VK_SUCCESS;
3475
3476 fail_bo:
3477 device->ws->buffer_destroy(mem->bo);
3478 fail:
3479 vk_free2(&device->alloc, pAllocator, mem);
3480
3481 return result;
3482 }
3483
3484 VkResult radv_AllocateMemory(
3485 VkDevice _device,
3486 const VkMemoryAllocateInfo* pAllocateInfo,
3487 const VkAllocationCallbacks* pAllocator,
3488 VkDeviceMemory* pMem)
3489 {
3490 RADV_FROM_HANDLE(radv_device, device, _device);
3491 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3492 }
3493
3494 void radv_FreeMemory(
3495 VkDevice _device,
3496 VkDeviceMemory _mem,
3497 const VkAllocationCallbacks* pAllocator)
3498 {
3499 RADV_FROM_HANDLE(radv_device, device, _device);
3500 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3501
3502 if (mem == NULL)
3503 return;
3504
3505 radv_bo_list_remove(device, mem->bo);
3506 device->ws->buffer_destroy(mem->bo);
3507 mem->bo = NULL;
3508
3509 vk_free2(&device->alloc, pAllocator, mem);
3510 }
3511
3512 VkResult radv_MapMemory(
3513 VkDevice _device,
3514 VkDeviceMemory _memory,
3515 VkDeviceSize offset,
3516 VkDeviceSize size,
3517 VkMemoryMapFlags flags,
3518 void** ppData)
3519 {
3520 RADV_FROM_HANDLE(radv_device, device, _device);
3521 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3522
3523 if (mem == NULL) {
3524 *ppData = NULL;
3525 return VK_SUCCESS;
3526 }
3527
3528 if (mem->user_ptr)
3529 *ppData = mem->user_ptr;
3530 else
3531 *ppData = device->ws->buffer_map(mem->bo);
3532
3533 if (*ppData) {
3534 *ppData += offset;
3535 return VK_SUCCESS;
3536 }
3537
3538 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3539 }
3540
3541 void radv_UnmapMemory(
3542 VkDevice _device,
3543 VkDeviceMemory _memory)
3544 {
3545 RADV_FROM_HANDLE(radv_device, device, _device);
3546 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3547
3548 if (mem == NULL)
3549 return;
3550
3551 if (mem->user_ptr == NULL)
3552 device->ws->buffer_unmap(mem->bo);
3553 }
3554
3555 VkResult radv_FlushMappedMemoryRanges(
3556 VkDevice _device,
3557 uint32_t memoryRangeCount,
3558 const VkMappedMemoryRange* pMemoryRanges)
3559 {
3560 return VK_SUCCESS;
3561 }
3562
3563 VkResult radv_InvalidateMappedMemoryRanges(
3564 VkDevice _device,
3565 uint32_t memoryRangeCount,
3566 const VkMappedMemoryRange* pMemoryRanges)
3567 {
3568 return VK_SUCCESS;
3569 }
3570
3571 void radv_GetBufferMemoryRequirements(
3572 VkDevice _device,
3573 VkBuffer _buffer,
3574 VkMemoryRequirements* pMemoryRequirements)
3575 {
3576 RADV_FROM_HANDLE(radv_device, device, _device);
3577 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3578
3579 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3580
3581 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3582 pMemoryRequirements->alignment = 4096;
3583 else
3584 pMemoryRequirements->alignment = 16;
3585
3586 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3587 }
3588
3589 void radv_GetBufferMemoryRequirements2(
3590 VkDevice device,
3591 const VkBufferMemoryRequirementsInfo2 *pInfo,
3592 VkMemoryRequirements2 *pMemoryRequirements)
3593 {
3594 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3595 &pMemoryRequirements->memoryRequirements);
3596 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3597 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3598 switch (ext->sType) {
3599 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3600 VkMemoryDedicatedRequirements *req =
3601 (VkMemoryDedicatedRequirements *) ext;
3602 req->requiresDedicatedAllocation = buffer->shareable;
3603 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3604 break;
3605 }
3606 default:
3607 break;
3608 }
3609 }
3610 }
3611
3612 void radv_GetImageMemoryRequirements(
3613 VkDevice _device,
3614 VkImage _image,
3615 VkMemoryRequirements* pMemoryRequirements)
3616 {
3617 RADV_FROM_HANDLE(radv_device, device, _device);
3618 RADV_FROM_HANDLE(radv_image, image, _image);
3619
3620 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3621
3622 pMemoryRequirements->size = image->size;
3623 pMemoryRequirements->alignment = image->alignment;
3624 }
3625
3626 void radv_GetImageMemoryRequirements2(
3627 VkDevice device,
3628 const VkImageMemoryRequirementsInfo2 *pInfo,
3629 VkMemoryRequirements2 *pMemoryRequirements)
3630 {
3631 radv_GetImageMemoryRequirements(device, pInfo->image,
3632 &pMemoryRequirements->memoryRequirements);
3633
3634 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3635
3636 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3637 switch (ext->sType) {
3638 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3639 VkMemoryDedicatedRequirements *req =
3640 (VkMemoryDedicatedRequirements *) ext;
3641 req->requiresDedicatedAllocation = image->shareable;
3642 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3643 break;
3644 }
3645 default:
3646 break;
3647 }
3648 }
3649 }
3650
3651 void radv_GetImageSparseMemoryRequirements(
3652 VkDevice device,
3653 VkImage image,
3654 uint32_t* pSparseMemoryRequirementCount,
3655 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3656 {
3657 stub();
3658 }
3659
3660 void radv_GetImageSparseMemoryRequirements2(
3661 VkDevice device,
3662 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3663 uint32_t* pSparseMemoryRequirementCount,
3664 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3665 {
3666 stub();
3667 }
3668
3669 void radv_GetDeviceMemoryCommitment(
3670 VkDevice device,
3671 VkDeviceMemory memory,
3672 VkDeviceSize* pCommittedMemoryInBytes)
3673 {
3674 *pCommittedMemoryInBytes = 0;
3675 }
3676
3677 VkResult radv_BindBufferMemory2(VkDevice device,
3678 uint32_t bindInfoCount,
3679 const VkBindBufferMemoryInfo *pBindInfos)
3680 {
3681 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3682 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3683 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3684
3685 if (mem) {
3686 buffer->bo = mem->bo;
3687 buffer->offset = pBindInfos[i].memoryOffset;
3688 } else {
3689 buffer->bo = NULL;
3690 }
3691 }
3692 return VK_SUCCESS;
3693 }
3694
3695 VkResult radv_BindBufferMemory(
3696 VkDevice device,
3697 VkBuffer buffer,
3698 VkDeviceMemory memory,
3699 VkDeviceSize memoryOffset)
3700 {
3701 const VkBindBufferMemoryInfo info = {
3702 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3703 .buffer = buffer,
3704 .memory = memory,
3705 .memoryOffset = memoryOffset
3706 };
3707
3708 return radv_BindBufferMemory2(device, 1, &info);
3709 }
3710
3711 VkResult radv_BindImageMemory2(VkDevice device,
3712 uint32_t bindInfoCount,
3713 const VkBindImageMemoryInfo *pBindInfos)
3714 {
3715 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3716 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3717 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3718
3719 if (mem) {
3720 image->bo = mem->bo;
3721 image->offset = pBindInfos[i].memoryOffset;
3722 } else {
3723 image->bo = NULL;
3724 image->offset = 0;
3725 }
3726 }
3727 return VK_SUCCESS;
3728 }
3729
3730
3731 VkResult radv_BindImageMemory(
3732 VkDevice device,
3733 VkImage image,
3734 VkDeviceMemory memory,
3735 VkDeviceSize memoryOffset)
3736 {
3737 const VkBindImageMemoryInfo info = {
3738 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3739 .image = image,
3740 .memory = memory,
3741 .memoryOffset = memoryOffset
3742 };
3743
3744 return radv_BindImageMemory2(device, 1, &info);
3745 }
3746
3747
3748 static void
3749 radv_sparse_buffer_bind_memory(struct radv_device *device,
3750 const VkSparseBufferMemoryBindInfo *bind)
3751 {
3752 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3753
3754 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3755 struct radv_device_memory *mem = NULL;
3756
3757 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3758 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3759
3760 device->ws->buffer_virtual_bind(buffer->bo,
3761 bind->pBinds[i].resourceOffset,
3762 bind->pBinds[i].size,
3763 mem ? mem->bo : NULL,
3764 bind->pBinds[i].memoryOffset);
3765 }
3766 }
3767
3768 static void
3769 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3770 const VkSparseImageOpaqueMemoryBindInfo *bind)
3771 {
3772 RADV_FROM_HANDLE(radv_image, image, bind->image);
3773
3774 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3775 struct radv_device_memory *mem = NULL;
3776
3777 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3778 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3779
3780 device->ws->buffer_virtual_bind(image->bo,
3781 bind->pBinds[i].resourceOffset,
3782 bind->pBinds[i].size,
3783 mem ? mem->bo : NULL,
3784 bind->pBinds[i].memoryOffset);
3785 }
3786 }
3787
3788 VkResult radv_QueueBindSparse(
3789 VkQueue _queue,
3790 uint32_t bindInfoCount,
3791 const VkBindSparseInfo* pBindInfo,
3792 VkFence _fence)
3793 {
3794 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3795 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3796 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3797 bool fence_emitted = false;
3798 VkResult result;
3799 int ret;
3800
3801 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3802 struct radv_winsys_sem_info sem_info;
3803 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3804 radv_sparse_buffer_bind_memory(queue->device,
3805 pBindInfo[i].pBufferBinds + j);
3806 }
3807
3808 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3809 radv_sparse_image_opaque_bind_memory(queue->device,
3810 pBindInfo[i].pImageOpaqueBinds + j);
3811 }
3812
3813 VkResult result;
3814 result = radv_alloc_sem_info(queue->device->instance,
3815 &sem_info,
3816 pBindInfo[i].waitSemaphoreCount,
3817 pBindInfo[i].pWaitSemaphores,
3818 pBindInfo[i].signalSemaphoreCount,
3819 pBindInfo[i].pSignalSemaphores,
3820 _fence);
3821 if (result != VK_SUCCESS)
3822 return result;
3823
3824 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3825 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3826 &queue->device->empty_cs[queue->queue_family_index],
3827 1, NULL, NULL,
3828 &sem_info, NULL,
3829 false, base_fence);
3830 if (ret) {
3831 radv_loge("failed to submit CS %d\n", i);
3832 abort();
3833 }
3834
3835 fence_emitted = true;
3836 }
3837
3838 radv_free_sem_info(&sem_info);
3839
3840 }
3841
3842 if (fence) {
3843 if (!fence_emitted) {
3844 result = radv_signal_fence(queue, fence);
3845 if (result != VK_SUCCESS)
3846 return result;
3847 }
3848 }
3849
3850 return VK_SUCCESS;
3851 }
3852
3853 VkResult radv_CreateFence(
3854 VkDevice _device,
3855 const VkFenceCreateInfo* pCreateInfo,
3856 const VkAllocationCallbacks* pAllocator,
3857 VkFence* pFence)
3858 {
3859 RADV_FROM_HANDLE(radv_device, device, _device);
3860 const VkExportFenceCreateInfo *export =
3861 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3862 VkExternalFenceHandleTypeFlags handleTypes =
3863 export ? export->handleTypes : 0;
3864
3865 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3866 sizeof(*fence), 8,
3867 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3868
3869 if (!fence)
3870 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3871
3872 fence->fence_wsi = NULL;
3873 fence->temp_syncobj = 0;
3874 if (device->always_use_syncobj || handleTypes) {
3875 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3876 if (ret) {
3877 vk_free2(&device->alloc, pAllocator, fence);
3878 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3879 }
3880 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3881 device->ws->signal_syncobj(device->ws, fence->syncobj);
3882 }
3883 fence->fence = NULL;
3884 } else {
3885 fence->fence = device->ws->create_fence();
3886 if (!fence->fence) {
3887 vk_free2(&device->alloc, pAllocator, fence);
3888 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3889 }
3890 fence->syncobj = 0;
3891 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3892 device->ws->signal_fence(fence->fence);
3893 }
3894
3895 *pFence = radv_fence_to_handle(fence);
3896
3897 return VK_SUCCESS;
3898 }
3899
3900 void radv_DestroyFence(
3901 VkDevice _device,
3902 VkFence _fence,
3903 const VkAllocationCallbacks* pAllocator)
3904 {
3905 RADV_FROM_HANDLE(radv_device, device, _device);
3906 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3907
3908 if (!fence)
3909 return;
3910
3911 if (fence->temp_syncobj)
3912 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3913 if (fence->syncobj)
3914 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3915 if (fence->fence)
3916 device->ws->destroy_fence(fence->fence);
3917 if (fence->fence_wsi)
3918 fence->fence_wsi->destroy(fence->fence_wsi);
3919 vk_free2(&device->alloc, pAllocator, fence);
3920 }
3921
3922
3923 uint64_t radv_get_current_time(void)
3924 {
3925 struct timespec tv;
3926 clock_gettime(CLOCK_MONOTONIC, &tv);
3927 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3928 }
3929
3930 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3931 {
3932 uint64_t current_time = radv_get_current_time();
3933
3934 timeout = MIN2(UINT64_MAX - current_time, timeout);
3935
3936 return current_time + timeout;
3937 }
3938
3939
3940 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3941 uint32_t fenceCount, const VkFence *pFences)
3942 {
3943 for (uint32_t i = 0; i < fenceCount; ++i) {
3944 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3945 if (fence->fence == NULL || fence->syncobj ||
3946 fence->temp_syncobj || fence->fence_wsi ||
3947 (!device->ws->is_fence_waitable(fence->fence)))
3948 return false;
3949 }
3950 return true;
3951 }
3952
3953 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3954 {
3955 for (uint32_t i = 0; i < fenceCount; ++i) {
3956 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3957 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3958 return false;
3959 }
3960 return true;
3961 }
3962
3963 VkResult radv_WaitForFences(
3964 VkDevice _device,
3965 uint32_t fenceCount,
3966 const VkFence* pFences,
3967 VkBool32 waitAll,
3968 uint64_t timeout)
3969 {
3970 RADV_FROM_HANDLE(radv_device, device, _device);
3971 timeout = radv_get_absolute_timeout(timeout);
3972
3973 if (device->always_use_syncobj &&
3974 radv_all_fences_syncobj(fenceCount, pFences))
3975 {
3976 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3977 if (!handles)
3978 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3979
3980 for (uint32_t i = 0; i < fenceCount; ++i) {
3981 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3982 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3983 }
3984
3985 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3986
3987 free(handles);
3988 return success ? VK_SUCCESS : VK_TIMEOUT;
3989 }
3990
3991 if (!waitAll && fenceCount > 1) {
3992 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3993 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3994 uint32_t wait_count = 0;
3995 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3996 if (!fences)
3997 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3998
3999 for (uint32_t i = 0; i < fenceCount; ++i) {
4000 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4001
4002 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
4003 free(fences);
4004 return VK_SUCCESS;
4005 }
4006
4007 fences[wait_count++] = fence->fence;
4008 }
4009
4010 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
4011 waitAll, timeout - radv_get_current_time());
4012
4013 free(fences);
4014 return success ? VK_SUCCESS : VK_TIMEOUT;
4015 }
4016
4017 while(radv_get_current_time() <= timeout) {
4018 for (uint32_t i = 0; i < fenceCount; ++i) {
4019 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4020 return VK_SUCCESS;
4021 }
4022 }
4023 return VK_TIMEOUT;
4024 }
4025
4026 for (uint32_t i = 0; i < fenceCount; ++i) {
4027 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4028 bool expired = false;
4029
4030 if (fence->temp_syncobj) {
4031 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4032 return VK_TIMEOUT;
4033 continue;
4034 }
4035
4036 if (fence->syncobj) {
4037 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4038 return VK_TIMEOUT;
4039 continue;
4040 }
4041
4042 if (fence->fence) {
4043 if (!device->ws->is_fence_waitable(fence->fence)) {
4044 while(!device->ws->is_fence_waitable(fence->fence) &&
4045 radv_get_current_time() <= timeout)
4046 /* Do nothing */;
4047 }
4048
4049 expired = device->ws->fence_wait(device->ws,
4050 fence->fence,
4051 true, timeout);
4052 if (!expired)
4053 return VK_TIMEOUT;
4054 }
4055
4056 if (fence->fence_wsi) {
4057 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4058 if (result != VK_SUCCESS)
4059 return result;
4060 }
4061 }
4062
4063 return VK_SUCCESS;
4064 }
4065
4066 VkResult radv_ResetFences(VkDevice _device,
4067 uint32_t fenceCount,
4068 const VkFence *pFences)
4069 {
4070 RADV_FROM_HANDLE(radv_device, device, _device);
4071
4072 for (unsigned i = 0; i < fenceCount; ++i) {
4073 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4074 if (fence->fence)
4075 device->ws->reset_fence(fence->fence);
4076
4077 /* Per spec, we first restore the permanent payload, and then reset, so
4078 * having a temp syncobj should not skip resetting the permanent syncobj. */
4079 if (fence->temp_syncobj) {
4080 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4081 fence->temp_syncobj = 0;
4082 }
4083
4084 if (fence->syncobj) {
4085 device->ws->reset_syncobj(device->ws, fence->syncobj);
4086 }
4087 }
4088
4089 return VK_SUCCESS;
4090 }
4091
4092 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4093 {
4094 RADV_FROM_HANDLE(radv_device, device, _device);
4095 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4096
4097 if (fence->temp_syncobj) {
4098 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4099 return success ? VK_SUCCESS : VK_NOT_READY;
4100 }
4101
4102 if (fence->syncobj) {
4103 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4104 return success ? VK_SUCCESS : VK_NOT_READY;
4105 }
4106
4107 if (fence->fence) {
4108 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4109 return VK_NOT_READY;
4110 }
4111 if (fence->fence_wsi) {
4112 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4113
4114 if (result != VK_SUCCESS) {
4115 if (result == VK_TIMEOUT)
4116 return VK_NOT_READY;
4117 return result;
4118 }
4119 }
4120 return VK_SUCCESS;
4121 }
4122
4123
4124 // Queue semaphore functions
4125
4126 VkResult radv_CreateSemaphore(
4127 VkDevice _device,
4128 const VkSemaphoreCreateInfo* pCreateInfo,
4129 const VkAllocationCallbacks* pAllocator,
4130 VkSemaphore* pSemaphore)
4131 {
4132 RADV_FROM_HANDLE(radv_device, device, _device);
4133 const VkExportSemaphoreCreateInfo *export =
4134 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4135 VkExternalSemaphoreHandleTypeFlags handleTypes =
4136 export ? export->handleTypes : 0;
4137
4138 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4139 sizeof(*sem), 8,
4140 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4141 if (!sem)
4142 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4143
4144 sem->temp_syncobj = 0;
4145 /* create a syncobject if we are going to export this semaphore */
4146 if (device->always_use_syncobj || handleTypes) {
4147 assert (device->physical_device->rad_info.has_syncobj);
4148 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4149 if (ret) {
4150 vk_free2(&device->alloc, pAllocator, sem);
4151 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4152 }
4153 sem->sem = NULL;
4154 } else {
4155 sem->sem = device->ws->create_sem(device->ws);
4156 if (!sem->sem) {
4157 vk_free2(&device->alloc, pAllocator, sem);
4158 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4159 }
4160 sem->syncobj = 0;
4161 }
4162
4163 *pSemaphore = radv_semaphore_to_handle(sem);
4164 return VK_SUCCESS;
4165 }
4166
4167 void radv_DestroySemaphore(
4168 VkDevice _device,
4169 VkSemaphore _semaphore,
4170 const VkAllocationCallbacks* pAllocator)
4171 {
4172 RADV_FROM_HANDLE(radv_device, device, _device);
4173 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4174 if (!_semaphore)
4175 return;
4176
4177 if (sem->syncobj)
4178 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4179 else
4180 device->ws->destroy_sem(sem->sem);
4181 vk_free2(&device->alloc, pAllocator, sem);
4182 }
4183
4184 VkResult radv_CreateEvent(
4185 VkDevice _device,
4186 const VkEventCreateInfo* pCreateInfo,
4187 const VkAllocationCallbacks* pAllocator,
4188 VkEvent* pEvent)
4189 {
4190 RADV_FROM_HANDLE(radv_device, device, _device);
4191 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4192 sizeof(*event), 8,
4193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4194
4195 if (!event)
4196 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4197
4198 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4199 RADEON_DOMAIN_GTT,
4200 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4201 RADV_BO_PRIORITY_FENCE);
4202 if (!event->bo) {
4203 vk_free2(&device->alloc, pAllocator, event);
4204 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4205 }
4206
4207 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4208
4209 *pEvent = radv_event_to_handle(event);
4210
4211 return VK_SUCCESS;
4212 }
4213
4214 void radv_DestroyEvent(
4215 VkDevice _device,
4216 VkEvent _event,
4217 const VkAllocationCallbacks* pAllocator)
4218 {
4219 RADV_FROM_HANDLE(radv_device, device, _device);
4220 RADV_FROM_HANDLE(radv_event, event, _event);
4221
4222 if (!event)
4223 return;
4224 device->ws->buffer_destroy(event->bo);
4225 vk_free2(&device->alloc, pAllocator, event);
4226 }
4227
4228 VkResult radv_GetEventStatus(
4229 VkDevice _device,
4230 VkEvent _event)
4231 {
4232 RADV_FROM_HANDLE(radv_event, event, _event);
4233
4234 if (*event->map == 1)
4235 return VK_EVENT_SET;
4236 return VK_EVENT_RESET;
4237 }
4238
4239 VkResult radv_SetEvent(
4240 VkDevice _device,
4241 VkEvent _event)
4242 {
4243 RADV_FROM_HANDLE(radv_event, event, _event);
4244 *event->map = 1;
4245
4246 return VK_SUCCESS;
4247 }
4248
4249 VkResult radv_ResetEvent(
4250 VkDevice _device,
4251 VkEvent _event)
4252 {
4253 RADV_FROM_HANDLE(radv_event, event, _event);
4254 *event->map = 0;
4255
4256 return VK_SUCCESS;
4257 }
4258
4259 VkResult radv_CreateBuffer(
4260 VkDevice _device,
4261 const VkBufferCreateInfo* pCreateInfo,
4262 const VkAllocationCallbacks* pAllocator,
4263 VkBuffer* pBuffer)
4264 {
4265 RADV_FROM_HANDLE(radv_device, device, _device);
4266 struct radv_buffer *buffer;
4267
4268 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4269
4270 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4271 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4272 if (buffer == NULL)
4273 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4274
4275 buffer->size = pCreateInfo->size;
4276 buffer->usage = pCreateInfo->usage;
4277 buffer->bo = NULL;
4278 buffer->offset = 0;
4279 buffer->flags = pCreateInfo->flags;
4280
4281 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4282 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4283
4284 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4285 buffer->bo = device->ws->buffer_create(device->ws,
4286 align64(buffer->size, 4096),
4287 4096, 0, RADEON_FLAG_VIRTUAL,
4288 RADV_BO_PRIORITY_VIRTUAL);
4289 if (!buffer->bo) {
4290 vk_free2(&device->alloc, pAllocator, buffer);
4291 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4292 }
4293 }
4294
4295 *pBuffer = radv_buffer_to_handle(buffer);
4296
4297 return VK_SUCCESS;
4298 }
4299
4300 void radv_DestroyBuffer(
4301 VkDevice _device,
4302 VkBuffer _buffer,
4303 const VkAllocationCallbacks* pAllocator)
4304 {
4305 RADV_FROM_HANDLE(radv_device, device, _device);
4306 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4307
4308 if (!buffer)
4309 return;
4310
4311 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4312 device->ws->buffer_destroy(buffer->bo);
4313
4314 vk_free2(&device->alloc, pAllocator, buffer);
4315 }
4316
4317 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4318 VkDevice device,
4319 const VkBufferDeviceAddressInfoEXT* pInfo)
4320 {
4321 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4322 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4323 }
4324
4325
4326 static inline unsigned
4327 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4328 {
4329 if (stencil)
4330 return plane->surface.u.legacy.stencil_tiling_index[level];
4331 else
4332 return plane->surface.u.legacy.tiling_index[level];
4333 }
4334
4335 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4336 {
4337 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4338 }
4339
4340 static uint32_t
4341 radv_init_dcc_control_reg(struct radv_device *device,
4342 struct radv_image_view *iview)
4343 {
4344 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4345 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4346 unsigned max_compressed_block_size;
4347 unsigned independent_128b_blocks;
4348 unsigned independent_64b_blocks;
4349
4350 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4351 return 0;
4352
4353 if (!device->physical_device->rad_info.has_dedicated_vram) {
4354 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4355 * dGPU and 64 for APU because all of our APUs to date use
4356 * DIMMs which have a request granularity size of 64B while all
4357 * other chips have a 32B request size.
4358 */
4359 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4360 }
4361
4362 if (device->physical_device->rad_info.chip_class >= GFX10) {
4363 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4364 independent_64b_blocks = 0;
4365 independent_128b_blocks = 1;
4366 } else {
4367 independent_128b_blocks = 0;
4368
4369 if (iview->image->info.samples > 1) {
4370 if (iview->image->planes[0].surface.bpe == 1)
4371 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4372 else if (iview->image->planes[0].surface.bpe == 2)
4373 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4374 }
4375
4376 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4377 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4378 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4379 /* If this DCC image is potentially going to be used in texture
4380 * fetches, we need some special settings.
4381 */
4382 independent_64b_blocks = 1;
4383 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4384 } else {
4385 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4386 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4387 * big as possible for better compression state.
4388 */
4389 independent_64b_blocks = 0;
4390 max_compressed_block_size = max_uncompressed_block_size;
4391 }
4392 }
4393
4394 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4395 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4396 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4397 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4398 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4399 }
4400
4401 void
4402 radv_initialise_color_surface(struct radv_device *device,
4403 struct radv_color_buffer_info *cb,
4404 struct radv_image_view *iview)
4405 {
4406 const struct vk_format_description *desc;
4407 unsigned ntype, format, swap, endian;
4408 unsigned blend_clamp = 0, blend_bypass = 0;
4409 uint64_t va;
4410 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4411 const struct radeon_surf *surf = &plane->surface;
4412
4413 desc = vk_format_description(iview->vk_format);
4414
4415 memset(cb, 0, sizeof(*cb));
4416
4417 /* Intensity is implemented as Red, so treat it that way. */
4418 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4419
4420 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4421
4422 cb->cb_color_base = va >> 8;
4423
4424 if (device->physical_device->rad_info.chip_class >= GFX9) {
4425 struct gfx9_surf_meta_flags meta;
4426 if (iview->image->dcc_offset)
4427 meta = surf->u.gfx9.dcc;
4428 else
4429 meta = surf->u.gfx9.cmask;
4430
4431 if (device->physical_device->rad_info.chip_class >= GFX10) {
4432 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4433 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4434 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4435 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4436 } else {
4437 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4438 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4439 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4440 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4441 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4442 }
4443
4444 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4445 cb->cb_color_base |= surf->tile_swizzle;
4446 } else {
4447 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4448 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4449
4450 cb->cb_color_base += level_info->offset >> 8;
4451 if (level_info->mode == RADEON_SURF_MODE_2D)
4452 cb->cb_color_base |= surf->tile_swizzle;
4453
4454 pitch_tile_max = level_info->nblk_x / 8 - 1;
4455 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4456 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4457
4458 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4459 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4460 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4461
4462 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4463
4464 if (radv_image_has_fmask(iview->image)) {
4465 if (device->physical_device->rad_info.chip_class >= GFX7)
4466 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4467 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4468 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4469 } else {
4470 /* This must be set for fast clear to work without FMASK. */
4471 if (device->physical_device->rad_info.chip_class >= GFX7)
4472 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4473 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4474 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4475 }
4476 }
4477
4478 /* CMASK variables */
4479 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4480 va += iview->image->cmask_offset;
4481 cb->cb_color_cmask = va >> 8;
4482
4483 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4484 va += iview->image->dcc_offset;
4485
4486 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4487 device->physical_device->rad_info.chip_class <= GFX8)
4488 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4489
4490 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4491 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4492
4493 cb->cb_dcc_base = va >> 8;
4494 cb->cb_dcc_base |= dcc_tile_swizzle;
4495
4496 /* GFX10 field has the same base shift as the GFX6 field. */
4497 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4498 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4499 S_028C6C_SLICE_MAX_GFX10(max_slice);
4500
4501 if (iview->image->info.samples > 1) {
4502 unsigned log_samples = util_logbase2(iview->image->info.samples);
4503
4504 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4505 S_028C74_NUM_FRAGMENTS(log_samples);
4506 }
4507
4508 if (radv_image_has_fmask(iview->image)) {
4509 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4510 cb->cb_color_fmask = va >> 8;
4511 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4512 } else {
4513 cb->cb_color_fmask = cb->cb_color_base;
4514 }
4515
4516 ntype = radv_translate_color_numformat(iview->vk_format,
4517 desc,
4518 vk_format_get_first_non_void_channel(iview->vk_format));
4519 format = radv_translate_colorformat(iview->vk_format);
4520 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4521 radv_finishme("Illegal color\n");
4522 swap = radv_translate_colorswap(iview->vk_format, false);
4523 endian = radv_colorformat_endian_swap(format);
4524
4525 /* blend clamp should be set for all NORM/SRGB types */
4526 if (ntype == V_028C70_NUMBER_UNORM ||
4527 ntype == V_028C70_NUMBER_SNORM ||
4528 ntype == V_028C70_NUMBER_SRGB)
4529 blend_clamp = 1;
4530
4531 /* set blend bypass according to docs if SINT/UINT or
4532 8/24 COLOR variants */
4533 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4534 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4535 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4536 blend_clamp = 0;
4537 blend_bypass = 1;
4538 }
4539 #if 0
4540 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4541 (format == V_028C70_COLOR_8 ||
4542 format == V_028C70_COLOR_8_8 ||
4543 format == V_028C70_COLOR_8_8_8_8))
4544 ->color_is_int8 = true;
4545 #endif
4546 cb->cb_color_info = S_028C70_FORMAT(format) |
4547 S_028C70_COMP_SWAP(swap) |
4548 S_028C70_BLEND_CLAMP(blend_clamp) |
4549 S_028C70_BLEND_BYPASS(blend_bypass) |
4550 S_028C70_SIMPLE_FLOAT(1) |
4551 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4552 ntype != V_028C70_NUMBER_SNORM &&
4553 ntype != V_028C70_NUMBER_SRGB &&
4554 format != V_028C70_COLOR_8_24 &&
4555 format != V_028C70_COLOR_24_8) |
4556 S_028C70_NUMBER_TYPE(ntype) |
4557 S_028C70_ENDIAN(endian);
4558 if (radv_image_has_fmask(iview->image)) {
4559 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4560 if (device->physical_device->rad_info.chip_class == GFX6) {
4561 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4562 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4563 }
4564
4565 if (radv_image_is_tc_compat_cmask(iview->image)) {
4566 /* Allow the texture block to read FMASK directly
4567 * without decompressing it. This bit must be cleared
4568 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4569 * otherwise the operation doesn't happen.
4570 */
4571 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4572
4573 /* Set CMASK into a tiling format that allows the
4574 * texture block to read it.
4575 */
4576 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4577 }
4578 }
4579
4580 if (radv_image_has_cmask(iview->image) &&
4581 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4582 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4583
4584 if (radv_dcc_enabled(iview->image, iview->base_mip))
4585 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4586
4587 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4588
4589 /* This must be set for fast clear to work without FMASK. */
4590 if (!radv_image_has_fmask(iview->image) &&
4591 device->physical_device->rad_info.chip_class == GFX6) {
4592 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4593 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4594 }
4595
4596 if (device->physical_device->rad_info.chip_class >= GFX9) {
4597 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4598
4599 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4600 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4601 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4602 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4603
4604 if (device->physical_device->rad_info.chip_class >= GFX10) {
4605 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4606
4607 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4608 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4609 S_028EE0_RESOURCE_LEVEL(1);
4610 } else {
4611 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4612 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4613 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4614 }
4615
4616 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4617 S_028C68_MIP0_HEIGHT(height - 1) |
4618 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4619 }
4620 }
4621
4622 static unsigned
4623 radv_calc_decompress_on_z_planes(struct radv_device *device,
4624 struct radv_image_view *iview)
4625 {
4626 unsigned max_zplanes = 0;
4627
4628 assert(radv_image_is_tc_compat_htile(iview->image));
4629
4630 if (device->physical_device->rad_info.chip_class >= GFX9) {
4631 /* Default value for 32-bit depth surfaces. */
4632 max_zplanes = 4;
4633
4634 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4635 iview->image->info.samples > 1)
4636 max_zplanes = 2;
4637
4638 max_zplanes = max_zplanes + 1;
4639 } else {
4640 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4641 /* Do not enable Z plane compression for 16-bit depth
4642 * surfaces because isn't supported on GFX8. Only
4643 * 32-bit depth surfaces are supported by the hardware.
4644 * This allows to maintain shader compatibility and to
4645 * reduce the number of depth decompressions.
4646 */
4647 max_zplanes = 1;
4648 } else {
4649 if (iview->image->info.samples <= 1)
4650 max_zplanes = 5;
4651 else if (iview->image->info.samples <= 4)
4652 max_zplanes = 3;
4653 else
4654 max_zplanes = 2;
4655 }
4656 }
4657
4658 return max_zplanes;
4659 }
4660
4661 void
4662 radv_initialise_ds_surface(struct radv_device *device,
4663 struct radv_ds_buffer_info *ds,
4664 struct radv_image_view *iview)
4665 {
4666 unsigned level = iview->base_mip;
4667 unsigned format, stencil_format;
4668 uint64_t va, s_offs, z_offs;
4669 bool stencil_only = false;
4670 const struct radv_image_plane *plane = &iview->image->planes[0];
4671 const struct radeon_surf *surf = &plane->surface;
4672
4673 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4674
4675 memset(ds, 0, sizeof(*ds));
4676 switch (iview->image->vk_format) {
4677 case VK_FORMAT_D24_UNORM_S8_UINT:
4678 case VK_FORMAT_X8_D24_UNORM_PACK32:
4679 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4680 ds->offset_scale = 2.0f;
4681 break;
4682 case VK_FORMAT_D16_UNORM:
4683 case VK_FORMAT_D16_UNORM_S8_UINT:
4684 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4685 ds->offset_scale = 4.0f;
4686 break;
4687 case VK_FORMAT_D32_SFLOAT:
4688 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4689 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4690 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4691 ds->offset_scale = 1.0f;
4692 break;
4693 case VK_FORMAT_S8_UINT:
4694 stencil_only = true;
4695 break;
4696 default:
4697 break;
4698 }
4699
4700 format = radv_translate_dbformat(iview->image->vk_format);
4701 stencil_format = surf->has_stencil ?
4702 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4703
4704 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4705 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4706 S_028008_SLICE_MAX(max_slice);
4707 if (device->physical_device->rad_info.chip_class >= GFX10) {
4708 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4709 S_028008_SLICE_MAX_HI(max_slice >> 11);
4710 }
4711
4712 ds->db_htile_data_base = 0;
4713 ds->db_htile_surface = 0;
4714
4715 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4716 s_offs = z_offs = va;
4717
4718 if (device->physical_device->rad_info.chip_class >= GFX9) {
4719 assert(surf->u.gfx9.surf_offset == 0);
4720 s_offs += surf->u.gfx9.stencil_offset;
4721
4722 ds->db_z_info = S_028038_FORMAT(format) |
4723 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4724 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4725 S_028038_MAXMIP(iview->image->info.levels - 1) |
4726 S_028038_ZRANGE_PRECISION(1);
4727 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4728 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4729
4730 if (device->physical_device->rad_info.chip_class == GFX9) {
4731 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4732 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4733 }
4734
4735 ds->db_depth_view |= S_028008_MIPID(level);
4736 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4737 S_02801C_Y_MAX(iview->image->info.height - 1);
4738
4739 if (radv_htile_enabled(iview->image, level)) {
4740 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4741
4742 if (radv_image_is_tc_compat_htile(iview->image)) {
4743 unsigned max_zplanes =
4744 radv_calc_decompress_on_z_planes(device, iview);
4745
4746 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4747
4748 if (device->physical_device->rad_info.chip_class >= GFX10) {
4749 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4750 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4751 } else {
4752 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4753 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4754 }
4755 }
4756
4757 if (!surf->has_stencil)
4758 /* Use all of the htile_buffer for depth if there's no stencil. */
4759 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4760 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4761 iview->image->htile_offset;
4762 ds->db_htile_data_base = va >> 8;
4763 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4764 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4765
4766 if (device->physical_device->rad_info.chip_class == GFX9) {
4767 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4768 }
4769 }
4770 } else {
4771 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4772
4773 if (stencil_only)
4774 level_info = &surf->u.legacy.stencil_level[level];
4775
4776 z_offs += surf->u.legacy.level[level].offset;
4777 s_offs += surf->u.legacy.stencil_level[level].offset;
4778
4779 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4780 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4781 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4782
4783 if (iview->image->info.samples > 1)
4784 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4785
4786 if (device->physical_device->rad_info.chip_class >= GFX7) {
4787 struct radeon_info *info = &device->physical_device->rad_info;
4788 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4789 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4790 unsigned macro_index = surf->u.legacy.macro_tile_index;
4791 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4792 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4793 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4794
4795 if (stencil_only)
4796 tile_mode = stencil_tile_mode;
4797
4798 ds->db_depth_info |=
4799 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4800 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4801 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4802 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4803 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4804 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4805 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4806 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4807 } else {
4808 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4809 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4810 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4811 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4812 if (stencil_only)
4813 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4814 }
4815
4816 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4817 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4818 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4819
4820 if (radv_htile_enabled(iview->image, level)) {
4821 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4822
4823 if (!surf->has_stencil &&
4824 !radv_image_is_tc_compat_htile(iview->image))
4825 /* Use all of the htile_buffer for depth if there's no stencil. */
4826 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4827
4828 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4829 iview->image->htile_offset;
4830 ds->db_htile_data_base = va >> 8;
4831 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4832
4833 if (radv_image_is_tc_compat_htile(iview->image)) {
4834 unsigned max_zplanes =
4835 radv_calc_decompress_on_z_planes(device, iview);
4836
4837 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4838 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4839 }
4840 }
4841 }
4842
4843 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4844 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4845 }
4846
4847 VkResult radv_CreateFramebuffer(
4848 VkDevice _device,
4849 const VkFramebufferCreateInfo* pCreateInfo,
4850 const VkAllocationCallbacks* pAllocator,
4851 VkFramebuffer* pFramebuffer)
4852 {
4853 RADV_FROM_HANDLE(radv_device, device, _device);
4854 struct radv_framebuffer *framebuffer;
4855 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4856 vk_find_struct_const(pCreateInfo->pNext,
4857 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4858
4859 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4860
4861 size_t size = sizeof(*framebuffer);
4862 if (!imageless_create_info)
4863 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4864 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4865 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4866 if (framebuffer == NULL)
4867 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4868
4869 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4870 framebuffer->width = pCreateInfo->width;
4871 framebuffer->height = pCreateInfo->height;
4872 framebuffer->layers = pCreateInfo->layers;
4873 if (imageless_create_info) {
4874 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4875 const VkFramebufferAttachmentImageInfoKHR *attachment =
4876 imageless_create_info->pAttachmentImageInfos + i;
4877 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4878 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4879 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4880 }
4881 } else {
4882 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4883 VkImageView _iview = pCreateInfo->pAttachments[i];
4884 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4885 framebuffer->attachments[i] = iview;
4886 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4887 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4888 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4889 }
4890 }
4891
4892 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4893 return VK_SUCCESS;
4894 }
4895
4896 void radv_DestroyFramebuffer(
4897 VkDevice _device,
4898 VkFramebuffer _fb,
4899 const VkAllocationCallbacks* pAllocator)
4900 {
4901 RADV_FROM_HANDLE(radv_device, device, _device);
4902 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4903
4904 if (!fb)
4905 return;
4906 vk_free2(&device->alloc, pAllocator, fb);
4907 }
4908
4909 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4910 {
4911 switch (address_mode) {
4912 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4913 return V_008F30_SQ_TEX_WRAP;
4914 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4915 return V_008F30_SQ_TEX_MIRROR;
4916 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4917 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4918 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4919 return V_008F30_SQ_TEX_CLAMP_BORDER;
4920 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4921 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4922 default:
4923 unreachable("illegal tex wrap mode");
4924 break;
4925 }
4926 }
4927
4928 static unsigned
4929 radv_tex_compare(VkCompareOp op)
4930 {
4931 switch (op) {
4932 case VK_COMPARE_OP_NEVER:
4933 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4934 case VK_COMPARE_OP_LESS:
4935 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4936 case VK_COMPARE_OP_EQUAL:
4937 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4938 case VK_COMPARE_OP_LESS_OR_EQUAL:
4939 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4940 case VK_COMPARE_OP_GREATER:
4941 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4942 case VK_COMPARE_OP_NOT_EQUAL:
4943 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4944 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4945 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4946 case VK_COMPARE_OP_ALWAYS:
4947 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4948 default:
4949 unreachable("illegal compare mode");
4950 break;
4951 }
4952 }
4953
4954 static unsigned
4955 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4956 {
4957 switch (filter) {
4958 case VK_FILTER_NEAREST:
4959 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4960 V_008F38_SQ_TEX_XY_FILTER_POINT);
4961 case VK_FILTER_LINEAR:
4962 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4963 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4964 case VK_FILTER_CUBIC_IMG:
4965 default:
4966 fprintf(stderr, "illegal texture filter");
4967 return 0;
4968 }
4969 }
4970
4971 static unsigned
4972 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4973 {
4974 switch (mode) {
4975 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4976 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4977 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4978 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4979 default:
4980 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4981 }
4982 }
4983
4984 static unsigned
4985 radv_tex_bordercolor(VkBorderColor bcolor)
4986 {
4987 switch (bcolor) {
4988 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4989 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4990 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4991 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4992 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4993 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4994 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4995 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4996 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4997 default:
4998 break;
4999 }
5000 return 0;
5001 }
5002
5003 static unsigned
5004 radv_tex_aniso_filter(unsigned filter)
5005 {
5006 if (filter < 2)
5007 return 0;
5008 if (filter < 4)
5009 return 1;
5010 if (filter < 8)
5011 return 2;
5012 if (filter < 16)
5013 return 3;
5014 return 4;
5015 }
5016
5017 static unsigned
5018 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5019 {
5020 switch (mode) {
5021 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5022 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5023 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5024 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5025 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5026 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5027 default:
5028 break;
5029 }
5030 return 0;
5031 }
5032
5033 static uint32_t
5034 radv_get_max_anisotropy(struct radv_device *device,
5035 const VkSamplerCreateInfo *pCreateInfo)
5036 {
5037 if (device->force_aniso >= 0)
5038 return device->force_aniso;
5039
5040 if (pCreateInfo->anisotropyEnable &&
5041 pCreateInfo->maxAnisotropy > 1.0f)
5042 return (uint32_t)pCreateInfo->maxAnisotropy;
5043
5044 return 0;
5045 }
5046
5047 static void
5048 radv_init_sampler(struct radv_device *device,
5049 struct radv_sampler *sampler,
5050 const VkSamplerCreateInfo *pCreateInfo)
5051 {
5052 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5053 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5054 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5055 device->physical_device->rad_info.chip_class == GFX9;
5056 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5057
5058 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5059 vk_find_struct_const(pCreateInfo->pNext,
5060 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5061 if (sampler_reduction)
5062 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5063
5064 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5065 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5066 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5067 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5068 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5069 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5070 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5071 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5072 S_008F30_DISABLE_CUBE_WRAP(0) |
5073 S_008F30_COMPAT_MODE(compat_mode) |
5074 S_008F30_FILTER_MODE(filter_mode));
5075 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5076 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5077 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5078 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5079 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5080 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5081 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5082 S_008F38_MIP_POINT_PRECLAMP(0));
5083 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5084 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5085
5086 if (device->physical_device->rad_info.chip_class >= GFX10) {
5087 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5088 } else {
5089 sampler->state[2] |=
5090 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5091 S_008F38_FILTER_PREC_FIX(1) |
5092 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5093 }
5094 }
5095
5096 VkResult radv_CreateSampler(
5097 VkDevice _device,
5098 const VkSamplerCreateInfo* pCreateInfo,
5099 const VkAllocationCallbacks* pAllocator,
5100 VkSampler* pSampler)
5101 {
5102 RADV_FROM_HANDLE(radv_device, device, _device);
5103 struct radv_sampler *sampler;
5104
5105 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5106 vk_find_struct_const(pCreateInfo->pNext,
5107 SAMPLER_YCBCR_CONVERSION_INFO);
5108
5109 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5110
5111 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5112 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5113 if (!sampler)
5114 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5115
5116 radv_init_sampler(device, sampler, pCreateInfo);
5117
5118 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5119 *pSampler = radv_sampler_to_handle(sampler);
5120
5121 return VK_SUCCESS;
5122 }
5123
5124 void radv_DestroySampler(
5125 VkDevice _device,
5126 VkSampler _sampler,
5127 const VkAllocationCallbacks* pAllocator)
5128 {
5129 RADV_FROM_HANDLE(radv_device, device, _device);
5130 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5131
5132 if (!sampler)
5133 return;
5134 vk_free2(&device->alloc, pAllocator, sampler);
5135 }
5136
5137 /* vk_icd.h does not declare this function, so we declare it here to
5138 * suppress Wmissing-prototypes.
5139 */
5140 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5141 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5142
5143 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5144 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5145 {
5146 /* For the full details on loader interface versioning, see
5147 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5148 * What follows is a condensed summary, to help you navigate the large and
5149 * confusing official doc.
5150 *
5151 * - Loader interface v0 is incompatible with later versions. We don't
5152 * support it.
5153 *
5154 * - In loader interface v1:
5155 * - The first ICD entrypoint called by the loader is
5156 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5157 * entrypoint.
5158 * - The ICD must statically expose no other Vulkan symbol unless it is
5159 * linked with -Bsymbolic.
5160 * - Each dispatchable Vulkan handle created by the ICD must be
5161 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5162 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5163 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5164 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5165 * such loader-managed surfaces.
5166 *
5167 * - Loader interface v2 differs from v1 in:
5168 * - The first ICD entrypoint called by the loader is
5169 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5170 * statically expose this entrypoint.
5171 *
5172 * - Loader interface v3 differs from v2 in:
5173 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5174 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5175 * because the loader no longer does so.
5176 */
5177 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5178 return VK_SUCCESS;
5179 }
5180
5181 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5182 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5183 int *pFD)
5184 {
5185 RADV_FROM_HANDLE(radv_device, device, _device);
5186 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5187
5188 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5189
5190 /* At the moment, we support only the below handle types. */
5191 assert(pGetFdInfo->handleType ==
5192 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5193 pGetFdInfo->handleType ==
5194 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5195
5196 bool ret = radv_get_memory_fd(device, memory, pFD);
5197 if (ret == false)
5198 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5199 return VK_SUCCESS;
5200 }
5201
5202 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5203 VkExternalMemoryHandleTypeFlagBits handleType,
5204 int fd,
5205 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5206 {
5207 RADV_FROM_HANDLE(radv_device, device, _device);
5208
5209 switch (handleType) {
5210 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5211 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5212 return VK_SUCCESS;
5213
5214 default:
5215 /* The valid usage section for this function says:
5216 *
5217 * "handleType must not be one of the handle types defined as
5218 * opaque."
5219 *
5220 * So opaque handle types fall into the default "unsupported" case.
5221 */
5222 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5223 }
5224 }
5225
5226 static VkResult radv_import_opaque_fd(struct radv_device *device,
5227 int fd,
5228 uint32_t *syncobj)
5229 {
5230 uint32_t syncobj_handle = 0;
5231 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5232 if (ret != 0)
5233 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5234
5235 if (*syncobj)
5236 device->ws->destroy_syncobj(device->ws, *syncobj);
5237
5238 *syncobj = syncobj_handle;
5239 close(fd);
5240
5241 return VK_SUCCESS;
5242 }
5243
5244 static VkResult radv_import_sync_fd(struct radv_device *device,
5245 int fd,
5246 uint32_t *syncobj)
5247 {
5248 /* If we create a syncobj we do it locally so that if we have an error, we don't
5249 * leave a syncobj in an undetermined state in the fence. */
5250 uint32_t syncobj_handle = *syncobj;
5251 if (!syncobj_handle) {
5252 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5253 if (ret) {
5254 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5255 }
5256 }
5257
5258 if (fd == -1) {
5259 device->ws->signal_syncobj(device->ws, syncobj_handle);
5260 } else {
5261 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5262 if (ret != 0)
5263 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5264 }
5265
5266 *syncobj = syncobj_handle;
5267 if (fd != -1)
5268 close(fd);
5269
5270 return VK_SUCCESS;
5271 }
5272
5273 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5274 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5275 {
5276 RADV_FROM_HANDLE(radv_device, device, _device);
5277 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5278 uint32_t *syncobj_dst = NULL;
5279
5280 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5281 syncobj_dst = &sem->temp_syncobj;
5282 } else {
5283 syncobj_dst = &sem->syncobj;
5284 }
5285
5286 switch(pImportSemaphoreFdInfo->handleType) {
5287 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5288 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5289 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5290 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5291 default:
5292 unreachable("Unhandled semaphore handle type");
5293 }
5294 }
5295
5296 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5297 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5298 int *pFd)
5299 {
5300 RADV_FROM_HANDLE(radv_device, device, _device);
5301 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5302 int ret;
5303 uint32_t syncobj_handle;
5304
5305 if (sem->temp_syncobj)
5306 syncobj_handle = sem->temp_syncobj;
5307 else
5308 syncobj_handle = sem->syncobj;
5309
5310 switch(pGetFdInfo->handleType) {
5311 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5312 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5313 break;
5314 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5315 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5316 if (!ret) {
5317 if (sem->temp_syncobj) {
5318 close (sem->temp_syncobj);
5319 sem->temp_syncobj = 0;
5320 } else {
5321 device->ws->reset_syncobj(device->ws, syncobj_handle);
5322 }
5323 }
5324 break;
5325 default:
5326 unreachable("Unhandled semaphore handle type");
5327 }
5328
5329 if (ret)
5330 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5331 return VK_SUCCESS;
5332 }
5333
5334 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5335 VkPhysicalDevice physicalDevice,
5336 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5337 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5338 {
5339 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5340
5341 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5342 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5343 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5344 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5345 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5346 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5347 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5348 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5349 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5350 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5351 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5352 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5353 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5354 } else {
5355 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5356 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5357 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5358 }
5359 }
5360
5361 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5362 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5363 {
5364 RADV_FROM_HANDLE(radv_device, device, _device);
5365 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5366 uint32_t *syncobj_dst = NULL;
5367
5368
5369 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5370 syncobj_dst = &fence->temp_syncobj;
5371 } else {
5372 syncobj_dst = &fence->syncobj;
5373 }
5374
5375 switch(pImportFenceFdInfo->handleType) {
5376 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5377 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5378 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5379 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5380 default:
5381 unreachable("Unhandled fence handle type");
5382 }
5383 }
5384
5385 VkResult radv_GetFenceFdKHR(VkDevice _device,
5386 const VkFenceGetFdInfoKHR *pGetFdInfo,
5387 int *pFd)
5388 {
5389 RADV_FROM_HANDLE(radv_device, device, _device);
5390 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5391 int ret;
5392 uint32_t syncobj_handle;
5393
5394 if (fence->temp_syncobj)
5395 syncobj_handle = fence->temp_syncobj;
5396 else
5397 syncobj_handle = fence->syncobj;
5398
5399 switch(pGetFdInfo->handleType) {
5400 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5401 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5402 break;
5403 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5404 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5405 if (!ret) {
5406 if (fence->temp_syncobj) {
5407 close (fence->temp_syncobj);
5408 fence->temp_syncobj = 0;
5409 } else {
5410 device->ws->reset_syncobj(device->ws, syncobj_handle);
5411 }
5412 }
5413 break;
5414 default:
5415 unreachable("Unhandled fence handle type");
5416 }
5417
5418 if (ret)
5419 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5420 return VK_SUCCESS;
5421 }
5422
5423 void radv_GetPhysicalDeviceExternalFenceProperties(
5424 VkPhysicalDevice physicalDevice,
5425 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5426 VkExternalFenceProperties *pExternalFenceProperties)
5427 {
5428 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5429
5430 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5431 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5432 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5433 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5434 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5435 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5436 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5437 } else {
5438 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5439 pExternalFenceProperties->compatibleHandleTypes = 0;
5440 pExternalFenceProperties->externalFenceFeatures = 0;
5441 }
5442 }
5443
5444 VkResult
5445 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5446 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5447 const VkAllocationCallbacks* pAllocator,
5448 VkDebugReportCallbackEXT* pCallback)
5449 {
5450 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5451 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5452 pCreateInfo, pAllocator, &instance->alloc,
5453 pCallback);
5454 }
5455
5456 void
5457 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5458 VkDebugReportCallbackEXT _callback,
5459 const VkAllocationCallbacks* pAllocator)
5460 {
5461 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5462 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5463 _callback, pAllocator, &instance->alloc);
5464 }
5465
5466 void
5467 radv_DebugReportMessageEXT(VkInstance _instance,
5468 VkDebugReportFlagsEXT flags,
5469 VkDebugReportObjectTypeEXT objectType,
5470 uint64_t object,
5471 size_t location,
5472 int32_t messageCode,
5473 const char* pLayerPrefix,
5474 const char* pMessage)
5475 {
5476 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5477 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5478 object, location, messageCode, pLayerPrefix, pMessage);
5479 }
5480
5481 void
5482 radv_GetDeviceGroupPeerMemoryFeatures(
5483 VkDevice device,
5484 uint32_t heapIndex,
5485 uint32_t localDeviceIndex,
5486 uint32_t remoteDeviceIndex,
5487 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5488 {
5489 assert(localDeviceIndex == remoteDeviceIndex);
5490
5491 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5492 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5493 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5494 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5495 }
5496
5497 static const VkTimeDomainEXT radv_time_domains[] = {
5498 VK_TIME_DOMAIN_DEVICE_EXT,
5499 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5500 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5501 };
5502
5503 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5504 VkPhysicalDevice physicalDevice,
5505 uint32_t *pTimeDomainCount,
5506 VkTimeDomainEXT *pTimeDomains)
5507 {
5508 int d;
5509 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5510
5511 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5512 vk_outarray_append(&out, i) {
5513 *i = radv_time_domains[d];
5514 }
5515 }
5516
5517 return vk_outarray_status(&out);
5518 }
5519
5520 static uint64_t
5521 radv_clock_gettime(clockid_t clock_id)
5522 {
5523 struct timespec current;
5524 int ret;
5525
5526 ret = clock_gettime(clock_id, &current);
5527 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5528 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5529 if (ret < 0)
5530 return 0;
5531
5532 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5533 }
5534
5535 VkResult radv_GetCalibratedTimestampsEXT(
5536 VkDevice _device,
5537 uint32_t timestampCount,
5538 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5539 uint64_t *pTimestamps,
5540 uint64_t *pMaxDeviation)
5541 {
5542 RADV_FROM_HANDLE(radv_device, device, _device);
5543 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5544 int d;
5545 uint64_t begin, end;
5546 uint64_t max_clock_period = 0;
5547
5548 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5549
5550 for (d = 0; d < timestampCount; d++) {
5551 switch (pTimestampInfos[d].timeDomain) {
5552 case VK_TIME_DOMAIN_DEVICE_EXT:
5553 pTimestamps[d] = device->ws->query_value(device->ws,
5554 RADEON_TIMESTAMP);
5555 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5556 max_clock_period = MAX2(max_clock_period, device_period);
5557 break;
5558 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5559 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5560 max_clock_period = MAX2(max_clock_period, 1);
5561 break;
5562
5563 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5564 pTimestamps[d] = begin;
5565 break;
5566 default:
5567 pTimestamps[d] = 0;
5568 break;
5569 }
5570 }
5571
5572 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5573
5574 /*
5575 * The maximum deviation is the sum of the interval over which we
5576 * perform the sampling and the maximum period of any sampled
5577 * clock. That's because the maximum skew between any two sampled
5578 * clock edges is when the sampled clock with the largest period is
5579 * sampled at the end of that period but right at the beginning of the
5580 * sampling interval and some other clock is sampled right at the
5581 * begining of its sampling period and right at the end of the
5582 * sampling interval. Let's assume the GPU has the longest clock
5583 * period and that the application is sampling GPU and monotonic:
5584 *
5585 * s e
5586 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5587 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5588 *
5589 * g
5590 * 0 1 2 3
5591 * GPU -----_____-----_____-----_____-----_____
5592 *
5593 * m
5594 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5595 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5596 *
5597 * Interval <----------------->
5598 * Deviation <-------------------------->
5599 *
5600 * s = read(raw) 2
5601 * g = read(GPU) 1
5602 * m = read(monotonic) 2
5603 * e = read(raw) b
5604 *
5605 * We round the sample interval up by one tick to cover sampling error
5606 * in the interval clock
5607 */
5608
5609 uint64_t sample_interval = end - begin + 1;
5610
5611 *pMaxDeviation = sample_interval + max_clock_period;
5612
5613 return VK_SUCCESS;
5614 }
5615
5616 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5617 VkPhysicalDevice physicalDevice,
5618 VkSampleCountFlagBits samples,
5619 VkMultisamplePropertiesEXT* pMultisampleProperties)
5620 {
5621 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5622 VK_SAMPLE_COUNT_4_BIT |
5623 VK_SAMPLE_COUNT_8_BIT)) {
5624 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5625 } else {
5626 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5627 }
5628 }