2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "radv_private.h"
36 #include "util/strtod.h"
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable
;
50 radv_get_function_timestamp(void *ptr
, uint32_t* timestamp
)
54 if (!dladdr(ptr
, &info
) || !info
.dli_fname
) {
57 if (stat(info
.dli_fname
, &st
)) {
60 *timestamp
= st
.st_mtim
.tv_sec
;
65 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
67 uint32_t mesa_timestamp
, llvm_timestamp
;
69 memset(uuid
, 0, VK_UUID_SIZE
);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
74 memcpy(uuid
, &mesa_timestamp
, 4);
75 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
76 memcpy((char*)uuid
+ 8, &f
, 2);
77 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
81 static const VkExtensionProperties instance_extensions
[] = {
83 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
86 #ifdef VK_USE_PLATFORM_XCB_KHR
88 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
94 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
100 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
106 static const VkExtensionProperties common_device_extensions
[] = {
108 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
112 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
116 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
120 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
124 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
130 radv_extensions_register(struct radv_instance
*instance
,
131 struct radv_extensions
*extensions
,
132 const VkExtensionProperties
*new_ext
,
136 VkExtensionProperties
*new_ptr
;
138 assert(new_ext
&& num_ext
> 0);
141 return VK_ERROR_INITIALIZATION_FAILED
;
143 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
144 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
145 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
147 /* Old array continues to be valid, update nothing */
149 return VK_ERROR_OUT_OF_HOST_MEMORY
;
151 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
152 num_ext
* sizeof(VkExtensionProperties
));
153 extensions
->ext_array
= new_ptr
;
154 extensions
->num_ext
+= num_ext
;
160 radv_extensions_finish(struct radv_instance
*instance
,
161 struct radv_extensions
*extensions
)
166 radv_loge("Attemted to free invalid extension struct\n");
168 if (extensions
->ext_array
)
169 vk_free(&instance
->alloc
, extensions
->ext_array
);
173 is_extension_enabled(const VkExtensionProperties
*extensions
,
177 assert(extensions
&& name
);
179 for (uint32_t i
= 0; i
< num_ext
; i
++) {
180 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
188 radv_physical_device_init(struct radv_physical_device
*device
,
189 struct radv_instance
*instance
,
193 drmVersionPtr version
;
196 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
198 return VK_ERROR_INCOMPATIBLE_DRIVER
;
200 version
= drmGetVersion(fd
);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
204 "failed to get version %s: %m", path
);
207 if (strcmp(version
->name
, "amdgpu")) {
208 drmFreeVersion(version
);
210 return VK_ERROR_INCOMPATIBLE_DRIVER
;
212 drmFreeVersion(version
);
214 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
215 device
->instance
= instance
;
216 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
217 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
219 device
->ws
= radv_amdgpu_winsys_create(fd
);
221 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
224 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
225 result
= radv_init_wsi(device
);
226 if (result
!= VK_SUCCESS
) {
227 device
->ws
->destroy(device
->ws
);
231 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
232 radv_finish_wsi(device
);
233 device
->ws
->destroy(device
->ws
);
234 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
235 "cannot generate UUID");
239 result
= radv_extensions_register(instance
,
241 common_device_extensions
,
242 ARRAY_SIZE(common_device_extensions
));
243 if (result
!= VK_SUCCESS
)
246 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
247 device
->name
= device
->rad_info
.name
;
257 radv_physical_device_finish(struct radv_physical_device
*device
)
259 radv_extensions_finish(device
->instance
, &device
->extensions
);
260 radv_finish_wsi(device
);
261 device
->ws
->destroy(device
->ws
);
266 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
267 VkSystemAllocationScope allocationScope
)
273 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
274 size_t align
, VkSystemAllocationScope allocationScope
)
276 return realloc(pOriginal
, size
);
280 default_free_func(void *pUserData
, void *pMemory
)
285 static const VkAllocationCallbacks default_alloc
= {
287 .pfnAllocation
= default_alloc_func
,
288 .pfnReallocation
= default_realloc_func
,
289 .pfnFree
= default_free_func
,
292 static const struct debug_control radv_debug_options
[] = {
293 {"fastclears", RADV_DEBUG_FAST_CLEARS
},
294 {"nodcc", RADV_DEBUG_NO_DCC
},
295 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
296 {"nocache", RADV_DEBUG_NO_CACHE
},
297 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
298 {"nohiz", RADV_DEBUG_NO_HIZ
},
299 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
300 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
304 VkResult
radv_CreateInstance(
305 const VkInstanceCreateInfo
* pCreateInfo
,
306 const VkAllocationCallbacks
* pAllocator
,
307 VkInstance
* pInstance
)
309 struct radv_instance
*instance
;
311 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
313 uint32_t client_version
;
314 if (pCreateInfo
->pApplicationInfo
&&
315 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
316 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
318 client_version
= VK_MAKE_VERSION(1, 0, 0);
321 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
322 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
323 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
324 "Client requested version %d.%d.%d",
325 VK_VERSION_MAJOR(client_version
),
326 VK_VERSION_MINOR(client_version
),
327 VK_VERSION_PATCH(client_version
));
330 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
331 if (!is_extension_enabled(instance_extensions
,
332 ARRAY_SIZE(instance_extensions
),
333 pCreateInfo
->ppEnabledExtensionNames
[i
]))
334 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
337 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
338 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
340 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
342 memset(instance
, 0, sizeof(*instance
));
344 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
347 instance
->alloc
= *pAllocator
;
349 instance
->alloc
= default_alloc
;
351 instance
->apiVersion
= client_version
;
352 instance
->physicalDeviceCount
= -1;
356 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
358 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
361 *pInstance
= radv_instance_to_handle(instance
);
366 void radv_DestroyInstance(
367 VkInstance _instance
,
368 const VkAllocationCallbacks
* pAllocator
)
370 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
372 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
373 radv_physical_device_finish(instance
->physicalDevices
+ i
);
376 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
380 vk_free(&instance
->alloc
, instance
);
383 VkResult
radv_EnumeratePhysicalDevices(
384 VkInstance _instance
,
385 uint32_t* pPhysicalDeviceCount
,
386 VkPhysicalDevice
* pPhysicalDevices
)
388 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
391 if (instance
->physicalDeviceCount
< 0) {
393 instance
->physicalDeviceCount
= 0;
394 for (unsigned i
= 0; i
< RADV_MAX_DRM_DEVICES
; i
++) {
395 snprintf(path
, sizeof(path
), "/dev/dri/renderD%d", 128 + i
);
396 result
= radv_physical_device_init(instance
->physicalDevices
+
397 instance
->physicalDeviceCount
,
399 if (result
== VK_SUCCESS
)
400 ++instance
->physicalDeviceCount
;
401 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
406 if (!pPhysicalDevices
) {
407 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
409 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
410 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
411 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
414 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
418 void radv_GetPhysicalDeviceFeatures(
419 VkPhysicalDevice physicalDevice
,
420 VkPhysicalDeviceFeatures
* pFeatures
)
422 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
424 memset(pFeatures
, 0, sizeof(*pFeatures
));
426 *pFeatures
= (VkPhysicalDeviceFeatures
) {
427 .robustBufferAccess
= true,
428 .fullDrawIndexUint32
= true,
429 .imageCubeArray
= true,
430 .independentBlend
= true,
431 .geometryShader
= false,
432 .tessellationShader
= false,
433 .sampleRateShading
= false,
434 .dualSrcBlend
= true,
436 .multiDrawIndirect
= true,
437 .drawIndirectFirstInstance
= true,
439 .depthBiasClamp
= true,
440 .fillModeNonSolid
= true,
445 .multiViewport
= false,
446 .samplerAnisotropy
= true,
447 .textureCompressionETC2
= false,
448 .textureCompressionASTC_LDR
= false,
449 .textureCompressionBC
= true,
450 .occlusionQueryPrecise
= true,
451 .pipelineStatisticsQuery
= false,
452 .vertexPipelineStoresAndAtomics
= true,
453 .fragmentStoresAndAtomics
= true,
454 .shaderTessellationAndGeometryPointSize
= true,
455 .shaderImageGatherExtended
= true,
456 .shaderStorageImageExtendedFormats
= true,
457 .shaderStorageImageMultisample
= false,
458 .shaderUniformBufferArrayDynamicIndexing
= true,
459 .shaderSampledImageArrayDynamicIndexing
= true,
460 .shaderStorageBufferArrayDynamicIndexing
= true,
461 .shaderStorageImageArrayDynamicIndexing
= true,
462 .shaderStorageImageReadWithoutFormat
= false,
463 .shaderStorageImageWriteWithoutFormat
= false,
464 .shaderClipDistance
= true,
465 .shaderCullDistance
= true,
466 .shaderFloat64
= false,
467 .shaderInt64
= false,
468 .shaderInt16
= false,
470 .variableMultisampleRate
= false,
471 .inheritedQueries
= false,
475 void radv_GetPhysicalDeviceFeatures2KHR(
476 VkPhysicalDevice physicalDevice
,
477 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
479 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
482 void radv_GetPhysicalDeviceProperties(
483 VkPhysicalDevice physicalDevice
,
484 VkPhysicalDeviceProperties
* pProperties
)
486 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
487 VkSampleCountFlags sample_counts
= 0xf;
488 VkPhysicalDeviceLimits limits
= {
489 .maxImageDimension1D
= (1 << 14),
490 .maxImageDimension2D
= (1 << 14),
491 .maxImageDimension3D
= (1 << 11),
492 .maxImageDimensionCube
= (1 << 14),
493 .maxImageArrayLayers
= (1 << 11),
494 .maxTexelBufferElements
= 128 * 1024 * 1024,
495 .maxUniformBufferRange
= UINT32_MAX
,
496 .maxStorageBufferRange
= UINT32_MAX
,
497 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
498 .maxMemoryAllocationCount
= UINT32_MAX
,
499 .maxSamplerAllocationCount
= 64 * 1024,
500 .bufferImageGranularity
= 64, /* A cache line */
501 .sparseAddressSpaceSize
= 0,
502 .maxBoundDescriptorSets
= MAX_SETS
,
503 .maxPerStageDescriptorSamplers
= 64,
504 .maxPerStageDescriptorUniformBuffers
= 64,
505 .maxPerStageDescriptorStorageBuffers
= 64,
506 .maxPerStageDescriptorSampledImages
= 64,
507 .maxPerStageDescriptorStorageImages
= 64,
508 .maxPerStageDescriptorInputAttachments
= 64,
509 .maxPerStageResources
= 128,
510 .maxDescriptorSetSamplers
= 256,
511 .maxDescriptorSetUniformBuffers
= 256,
512 .maxDescriptorSetUniformBuffersDynamic
= 256,
513 .maxDescriptorSetStorageBuffers
= 256,
514 .maxDescriptorSetStorageBuffersDynamic
= 256,
515 .maxDescriptorSetSampledImages
= 256,
516 .maxDescriptorSetStorageImages
= 256,
517 .maxDescriptorSetInputAttachments
= 256,
518 .maxVertexInputAttributes
= 32,
519 .maxVertexInputBindings
= 32,
520 .maxVertexInputAttributeOffset
= 2047,
521 .maxVertexInputBindingStride
= 2048,
522 .maxVertexOutputComponents
= 128,
523 .maxTessellationGenerationLevel
= 0,
524 .maxTessellationPatchSize
= 0,
525 .maxTessellationControlPerVertexInputComponents
= 0,
526 .maxTessellationControlPerVertexOutputComponents
= 0,
527 .maxTessellationControlPerPatchOutputComponents
= 0,
528 .maxTessellationControlTotalOutputComponents
= 0,
529 .maxTessellationEvaluationInputComponents
= 0,
530 .maxTessellationEvaluationOutputComponents
= 0,
531 .maxGeometryShaderInvocations
= 32,
532 .maxGeometryInputComponents
= 64,
533 .maxGeometryOutputComponents
= 128,
534 .maxGeometryOutputVertices
= 256,
535 .maxGeometryTotalOutputComponents
= 1024,
536 .maxFragmentInputComponents
= 128,
537 .maxFragmentOutputAttachments
= 8,
538 .maxFragmentDualSrcAttachments
= 1,
539 .maxFragmentCombinedOutputResources
= 8,
540 .maxComputeSharedMemorySize
= 32768,
541 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
542 .maxComputeWorkGroupInvocations
= 2048,
543 .maxComputeWorkGroupSize
= {
548 .subPixelPrecisionBits
= 4 /* FIXME */,
549 .subTexelPrecisionBits
= 4 /* FIXME */,
550 .mipmapPrecisionBits
= 4 /* FIXME */,
551 .maxDrawIndexedIndexValue
= UINT32_MAX
,
552 .maxDrawIndirectCount
= UINT32_MAX
,
553 .maxSamplerLodBias
= 16,
554 .maxSamplerAnisotropy
= 16,
555 .maxViewports
= MAX_VIEWPORTS
,
556 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
557 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
558 .viewportSubPixelBits
= 13, /* We take a float? */
559 .minMemoryMapAlignment
= 4096, /* A page */
560 .minTexelBufferOffsetAlignment
= 1,
561 .minUniformBufferOffsetAlignment
= 4,
562 .minStorageBufferOffsetAlignment
= 4,
563 .minTexelOffset
= -32,
564 .maxTexelOffset
= 31,
565 .minTexelGatherOffset
= -32,
566 .maxTexelGatherOffset
= 31,
567 .minInterpolationOffset
= -2,
568 .maxInterpolationOffset
= 2,
569 .subPixelInterpolationOffsetBits
= 8,
570 .maxFramebufferWidth
= (1 << 14),
571 .maxFramebufferHeight
= (1 << 14),
572 .maxFramebufferLayers
= (1 << 10),
573 .framebufferColorSampleCounts
= sample_counts
,
574 .framebufferDepthSampleCounts
= sample_counts
,
575 .framebufferStencilSampleCounts
= sample_counts
,
576 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
577 .maxColorAttachments
= MAX_RTS
,
578 .sampledImageColorSampleCounts
= sample_counts
,
579 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
580 .sampledImageDepthSampleCounts
= sample_counts
,
581 .sampledImageStencilSampleCounts
= sample_counts
,
582 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
583 .maxSampleMaskWords
= 1,
584 .timestampComputeAndGraphics
= false,
585 .timestampPeriod
= 100000.0 / pdevice
->rad_info
.clock_crystal_freq
,
586 .maxClipDistances
= 8,
587 .maxCullDistances
= 8,
588 .maxCombinedClipAndCullDistances
= 8,
589 .discreteQueuePriorities
= 1,
590 .pointSizeRange
= { 0.125, 255.875 },
591 .lineWidthRange
= { 0.0, 7.9921875 },
592 .pointSizeGranularity
= (1.0 / 8.0),
593 .lineWidthGranularity
= (1.0 / 128.0),
594 .strictLines
= false, /* FINISHME */
595 .standardSampleLocations
= true,
596 .optimalBufferCopyOffsetAlignment
= 128,
597 .optimalBufferCopyRowPitchAlignment
= 128,
598 .nonCoherentAtomSize
= 64,
601 *pProperties
= (VkPhysicalDeviceProperties
) {
602 .apiVersion
= VK_MAKE_VERSION(1, 0, 5),
605 .deviceID
= pdevice
->rad_info
.pci_id
,
606 .deviceType
= VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
,
608 .sparseProperties
= {0}, /* Broadwell doesn't do sparse. */
611 strcpy(pProperties
->deviceName
, pdevice
->name
);
612 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
615 void radv_GetPhysicalDeviceProperties2KHR(
616 VkPhysicalDevice physicalDevice
,
617 VkPhysicalDeviceProperties2KHR
*pProperties
)
619 return radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
622 void radv_GetPhysicalDeviceQueueFamilyProperties(
623 VkPhysicalDevice physicalDevice
,
625 VkQueueFamilyProperties
* pQueueFamilyProperties
)
627 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
628 int num_queue_families
= 1;
630 if (pdevice
->rad_info
.compute_rings
> 0 &&
631 pdevice
->rad_info
.chip_class
>= CIK
&&
632 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
633 num_queue_families
++;
635 if (pQueueFamilyProperties
== NULL
) {
636 *pCount
= num_queue_families
;
645 pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
646 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
647 VK_QUEUE_COMPUTE_BIT
|
648 VK_QUEUE_TRANSFER_BIT
,
650 .timestampValidBits
= 64,
651 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
656 if (pdevice
->rad_info
.compute_rings
> 0 &&
657 pdevice
->rad_info
.chip_class
>= CIK
&&
658 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
660 pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
661 .queueFlags
= VK_QUEUE_COMPUTE_BIT
| VK_QUEUE_TRANSFER_BIT
,
662 .queueCount
= pdevice
->rad_info
.compute_rings
,
663 .timestampValidBits
= 64,
664 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
672 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
673 VkPhysicalDevice physicalDevice
,
675 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
677 return radv_GetPhysicalDeviceQueueFamilyProperties(physicalDevice
,
679 &pQueueFamilyProperties
->queueFamilyProperties
);
682 void radv_GetPhysicalDeviceMemoryProperties(
683 VkPhysicalDevice physicalDevice
,
684 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
686 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
688 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
690 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
691 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
692 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
693 .heapIndex
= RADV_MEM_HEAP_VRAM
,
695 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
696 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
697 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
698 .heapIndex
= RADV_MEM_HEAP_GTT
,
700 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
701 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
702 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
703 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
704 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
706 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
707 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
708 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
709 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
710 .heapIndex
= RADV_MEM_HEAP_GTT
,
713 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
715 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
716 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
717 .size
= physical_device
->rad_info
.vram_size
-
718 physical_device
->rad_info
.visible_vram_size
,
719 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
721 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
722 .size
= physical_device
->rad_info
.visible_vram_size
,
723 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
725 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
726 .size
= physical_device
->rad_info
.gart_size
,
731 void radv_GetPhysicalDeviceMemoryProperties2KHR(
732 VkPhysicalDevice physicalDevice
,
733 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
735 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
736 &pMemoryProperties
->memoryProperties
);
740 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
741 int queue_family_index
, int idx
)
743 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
744 queue
->device
= device
;
745 queue
->queue_family_index
= queue_family_index
;
746 queue
->queue_idx
= idx
;
748 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
750 return VK_ERROR_OUT_OF_HOST_MEMORY
;
756 radv_queue_finish(struct radv_queue
*queue
)
759 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
761 if (queue
->preamble_cs
)
762 queue
->device
->ws
->cs_destroy(queue
->preamble_cs
);
763 if (queue
->descriptor_bo
)
764 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
765 if (queue
->scratch_bo
)
766 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
767 if (queue
->compute_scratch_bo
)
768 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
772 radv_device_init_gs_info(struct radv_device
*device
)
774 switch (device
->physical_device
->rad_info
.family
) {
783 device
->gs_table_depth
= 16;
794 device
->gs_table_depth
= 32;
797 unreachable("unknown GPU");
801 VkResult
radv_CreateDevice(
802 VkPhysicalDevice physicalDevice
,
803 const VkDeviceCreateInfo
* pCreateInfo
,
804 const VkAllocationCallbacks
* pAllocator
,
807 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
809 struct radv_device
*device
;
811 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
812 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
813 physical_device
->extensions
.num_ext
,
814 pCreateInfo
->ppEnabledExtensionNames
[i
]))
815 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
818 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
820 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
822 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
824 memset(device
, 0, sizeof(*device
));
826 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
827 device
->instance
= physical_device
->instance
;
828 device
->physical_device
= physical_device
;
830 device
->debug_flags
= device
->instance
->debug_flags
;
832 device
->ws
= physical_device
->ws
;
834 device
->alloc
= *pAllocator
;
836 device
->alloc
= physical_device
->instance
->alloc
;
838 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
839 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
840 uint32_t qfi
= queue_create
->queueFamilyIndex
;
842 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
843 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
844 if (!device
->queues
[qfi
]) {
845 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
849 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
851 device
->queue_count
[qfi
] = queue_create
->queueCount
;
853 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
854 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
855 if (result
!= VK_SUCCESS
)
860 #if HAVE_LLVM < 0x0400
861 device
->llvm_supports_spill
= false;
863 device
->llvm_supports_spill
= true;
866 /* The maximum number of scratch waves. Scratch space isn't divided
867 * evenly between CUs. The number is only a function of the number of CUs.
868 * We can decrease the constant to decrease the scratch buffer size.
870 * sctx->scratch_waves must be >= the maximum posible size of
871 * 1 threadgroup, so that the hw doesn't hang from being unable
874 * The recommended value is 4 per CU at most. Higher numbers don't
875 * bring much benefit, but they still occupy chip resources (think
876 * async compute). I've seen ~2% performance difference between 4 and 32.
878 uint32_t max_threads_per_block
= 2048;
879 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
880 max_threads_per_block
/ 64);
882 radv_device_init_gs_info(device
);
884 result
= radv_device_init_meta(device
);
885 if (result
!= VK_SUCCESS
)
888 radv_device_init_msaa(device
);
890 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
891 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
893 case RADV_QUEUE_GENERAL
:
894 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
895 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
896 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
898 case RADV_QUEUE_COMPUTE
:
899 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
900 radeon_emit(device
->empty_cs
[family
], 0);
903 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
906 if (getenv("RADV_TRACE_FILE")) {
907 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
908 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
909 if (!device
->trace_bo
)
912 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
913 if (!device
->trace_id_ptr
)
917 *pDevice
= radv_device_to_handle(device
);
921 if (device
->trace_bo
)
922 device
->ws
->buffer_destroy(device
->trace_bo
);
924 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
925 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
926 radv_queue_finish(&device
->queues
[i
][q
]);
927 if (device
->queue_count
[i
])
928 vk_free(&device
->alloc
, device
->queues
[i
]);
931 vk_free(&device
->alloc
, device
);
935 void radv_DestroyDevice(
937 const VkAllocationCallbacks
* pAllocator
)
939 RADV_FROM_HANDLE(radv_device
, device
, _device
);
941 if (device
->trace_bo
)
942 device
->ws
->buffer_destroy(device
->trace_bo
);
944 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
945 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
946 radv_queue_finish(&device
->queues
[i
][q
]);
947 if (device
->queue_count
[i
])
948 vk_free(&device
->alloc
, device
->queues
[i
]);
950 radv_device_finish_meta(device
);
952 vk_free(&device
->alloc
, device
);
955 VkResult
radv_EnumerateInstanceExtensionProperties(
956 const char* pLayerName
,
957 uint32_t* pPropertyCount
,
958 VkExtensionProperties
* pProperties
)
960 if (pProperties
== NULL
) {
961 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
965 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
966 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
968 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
969 return VK_INCOMPLETE
;
974 VkResult
radv_EnumerateDeviceExtensionProperties(
975 VkPhysicalDevice physicalDevice
,
976 const char* pLayerName
,
977 uint32_t* pPropertyCount
,
978 VkExtensionProperties
* pProperties
)
980 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
982 if (pProperties
== NULL
) {
983 *pPropertyCount
= pdevice
->extensions
.num_ext
;
987 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
988 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
990 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
991 return VK_INCOMPLETE
;
996 VkResult
radv_EnumerateInstanceLayerProperties(
997 uint32_t* pPropertyCount
,
998 VkLayerProperties
* pProperties
)
1000 if (pProperties
== NULL
) {
1001 *pPropertyCount
= 0;
1005 /* None supported at this time */
1006 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1009 VkResult
radv_EnumerateDeviceLayerProperties(
1010 VkPhysicalDevice physicalDevice
,
1011 uint32_t* pPropertyCount
,
1012 VkLayerProperties
* pProperties
)
1014 if (pProperties
== NULL
) {
1015 *pPropertyCount
= 0;
1019 /* None supported at this time */
1020 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1023 void radv_GetDeviceQueue(
1025 uint32_t queueFamilyIndex
,
1026 uint32_t queueIndex
,
1029 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1031 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1034 static void radv_dump_trace(struct radv_device
*device
,
1035 struct radeon_winsys_cs
*cs
)
1037 const char *filename
= getenv("RADV_TRACE_FILE");
1038 FILE *f
= fopen(filename
, "w");
1040 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1044 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1045 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1050 radv_get_preamble_cs(struct radv_queue
*queue
,
1051 uint32_t scratch_size
,
1052 uint32_t compute_scratch_size
,
1053 struct radeon_winsys_cs
**preamble_cs
)
1055 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1056 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1057 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1058 struct radeon_winsys_cs
*cs
= NULL
;
1060 if (!scratch_size
&& !compute_scratch_size
) {
1061 *preamble_cs
= NULL
;
1065 if (scratch_size
<= queue
->scratch_size
&&
1066 compute_scratch_size
<= queue
->compute_scratch_size
) {
1067 *preamble_cs
= queue
->preamble_cs
;
1071 if (scratch_size
> queue
->scratch_size
) {
1072 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1076 RADEON_FLAG_NO_CPU_ACCESS
);
1080 scratch_bo
= queue
->scratch_bo
;
1082 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1083 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1084 compute_scratch_size
,
1087 RADEON_FLAG_NO_CPU_ACCESS
);
1088 if (!compute_scratch_bo
)
1092 compute_scratch_bo
= queue
->compute_scratch_bo
;
1094 if (scratch_bo
!= queue
->scratch_bo
) {
1095 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1099 RADEON_FLAG_CPU_ACCESS
);
1103 descriptor_bo
= queue
->descriptor_bo
;
1105 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1106 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1112 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1115 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1117 if (descriptor_bo
!= queue
->descriptor_bo
) {
1118 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1119 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1120 S_008F04_SWIZZLE_ENABLE(1);
1122 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1124 map
[0] = scratch_va
;
1127 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1130 if (descriptor_bo
) {
1131 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1132 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1133 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1134 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1135 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1136 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1138 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1140 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1141 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1142 radeon_emit(cs
, va
);
1143 radeon_emit(cs
, va
>> 32);
1147 if (compute_scratch_bo
) {
1148 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1149 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1150 S_008F04_SWIZZLE_ENABLE(1);
1152 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1154 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1155 radeon_emit(cs
, scratch_va
);
1156 radeon_emit(cs
, rsrc1
);
1159 if (!queue
->device
->ws
->cs_finalize(cs
))
1162 if (queue
->preamble_cs
)
1163 queue
->device
->ws
->cs_destroy(queue
->preamble_cs
);
1165 queue
->preamble_cs
= cs
;
1167 if (scratch_bo
!= queue
->scratch_bo
) {
1168 if (queue
->scratch_bo
)
1169 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1170 queue
->scratch_bo
= scratch_bo
;
1171 queue
->scratch_size
= scratch_size
;
1174 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1175 if (queue
->compute_scratch_bo
)
1176 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1177 queue
->compute_scratch_bo
= compute_scratch_bo
;
1178 queue
->compute_scratch_size
= compute_scratch_size
;
1181 if (descriptor_bo
!= queue
->descriptor_bo
) {
1182 if (queue
->descriptor_bo
)
1183 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1185 queue
->descriptor_bo
= descriptor_bo
;
1192 queue
->device
->ws
->cs_destroy(cs
);
1193 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1194 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1195 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1196 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1197 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1198 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1199 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1202 VkResult
radv_QueueSubmit(
1204 uint32_t submitCount
,
1205 const VkSubmitInfo
* pSubmits
,
1208 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1209 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1210 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1211 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1213 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1214 uint32_t scratch_size
= 0;
1215 uint32_t compute_scratch_size
= 0;
1216 struct radeon_winsys_cs
*preamble_cs
= NULL
;
1219 /* Do this first so failing to allocate scratch buffers can't result in
1220 * partially executed submissions. */
1221 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1222 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1223 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1224 pSubmits
[i
].pCommandBuffers
[j
]);
1226 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1227 compute_scratch_size
= MAX2(compute_scratch_size
,
1228 cmd_buffer
->compute_scratch_size_needed
);
1232 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
, &preamble_cs
);
1233 if (result
!= VK_SUCCESS
)
1236 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1237 struct radeon_winsys_cs
**cs_array
;
1238 bool can_patch
= true;
1241 if (!pSubmits
[i
].commandBufferCount
)
1244 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1245 pSubmits
[i
].commandBufferCount
);
1247 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1248 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1249 pSubmits
[i
].pCommandBuffers
[j
]);
1250 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1252 cs_array
[j
] = cmd_buffer
->cs
;
1253 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1257 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
1258 advance
= MIN2(max_cs_submission
,
1259 pSubmits
[i
].commandBufferCount
- j
);
1261 bool e
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
1263 if (queue
->device
->trace_bo
)
1264 *queue
->device
->trace_id_ptr
= 0;
1266 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1267 advance
, preamble_cs
,
1268 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1269 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1270 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1271 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1272 can_patch
, base_fence
);
1275 radv_loge("failed to submit CS %d\n", i
);
1278 if (queue
->device
->trace_bo
) {
1279 bool success
= queue
->device
->ws
->ctx_wait_idle(
1281 radv_queue_family_to_ring(
1282 queue
->queue_family_index
),
1285 if (!success
) { /* Hang */
1286 radv_dump_trace(queue
->device
, cs_array
[j
]);
1296 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1297 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1298 1, NULL
, NULL
, 0, NULL
, 0,
1301 fence
->submitted
= true;
1307 VkResult
radv_QueueWaitIdle(
1310 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1312 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
1313 radv_queue_family_to_ring(queue
->queue_family_index
),
1318 VkResult
radv_DeviceWaitIdle(
1321 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1323 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1324 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
1325 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
1331 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
1332 VkInstance instance
,
1335 return radv_lookup_entrypoint(pName
);
1338 /* The loader wants us to expose a second GetInstanceProcAddr function
1339 * to work around certain LD_PRELOAD issues seen in apps.
1342 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1343 VkInstance instance
,
1347 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1348 VkInstance instance
,
1351 return radv_GetInstanceProcAddr(instance
, pName
);
1354 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
1358 return radv_lookup_entrypoint(pName
);
1361 VkResult
radv_AllocateMemory(
1363 const VkMemoryAllocateInfo
* pAllocateInfo
,
1364 const VkAllocationCallbacks
* pAllocator
,
1365 VkDeviceMemory
* pMem
)
1367 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1368 struct radv_device_memory
*mem
;
1370 enum radeon_bo_domain domain
;
1372 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
1374 if (pAllocateInfo
->allocationSize
== 0) {
1375 /* Apparently, this is allowed */
1376 *pMem
= VK_NULL_HANDLE
;
1380 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
1381 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1383 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1385 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
1386 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
1387 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
1388 domain
= RADEON_DOMAIN_GTT
;
1390 domain
= RADEON_DOMAIN_VRAM
;
1392 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
1393 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1395 flags
|= RADEON_FLAG_CPU_ACCESS
;
1397 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
1398 flags
|= RADEON_FLAG_GTT_WC
;
1400 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, 32768,
1404 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1407 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
1409 *pMem
= radv_device_memory_to_handle(mem
);
1414 vk_free2(&device
->alloc
, pAllocator
, mem
);
1419 void radv_FreeMemory(
1421 VkDeviceMemory _mem
,
1422 const VkAllocationCallbacks
* pAllocator
)
1424 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1425 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
1430 device
->ws
->buffer_destroy(mem
->bo
);
1433 vk_free2(&device
->alloc
, pAllocator
, mem
);
1436 VkResult
radv_MapMemory(
1438 VkDeviceMemory _memory
,
1439 VkDeviceSize offset
,
1441 VkMemoryMapFlags flags
,
1444 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1445 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1452 *ppData
= device
->ws
->buffer_map(mem
->bo
);
1458 return VK_ERROR_MEMORY_MAP_FAILED
;
1461 void radv_UnmapMemory(
1463 VkDeviceMemory _memory
)
1465 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1466 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1471 device
->ws
->buffer_unmap(mem
->bo
);
1474 VkResult
radv_FlushMappedMemoryRanges(
1476 uint32_t memoryRangeCount
,
1477 const VkMappedMemoryRange
* pMemoryRanges
)
1482 VkResult
radv_InvalidateMappedMemoryRanges(
1484 uint32_t memoryRangeCount
,
1485 const VkMappedMemoryRange
* pMemoryRanges
)
1490 void radv_GetBufferMemoryRequirements(
1493 VkMemoryRequirements
* pMemoryRequirements
)
1495 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1497 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
1499 pMemoryRequirements
->size
= buffer
->size
;
1500 pMemoryRequirements
->alignment
= 16;
1503 void radv_GetImageMemoryRequirements(
1506 VkMemoryRequirements
* pMemoryRequirements
)
1508 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1510 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
1512 pMemoryRequirements
->size
= image
->size
;
1513 pMemoryRequirements
->alignment
= image
->alignment
;
1516 void radv_GetImageSparseMemoryRequirements(
1519 uint32_t* pSparseMemoryRequirementCount
,
1520 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
1525 void radv_GetDeviceMemoryCommitment(
1527 VkDeviceMemory memory
,
1528 VkDeviceSize
* pCommittedMemoryInBytes
)
1530 *pCommittedMemoryInBytes
= 0;
1533 VkResult
radv_BindBufferMemory(
1536 VkDeviceMemory _memory
,
1537 VkDeviceSize memoryOffset
)
1539 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1540 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1543 buffer
->bo
= mem
->bo
;
1544 buffer
->offset
= memoryOffset
;
1553 VkResult
radv_BindImageMemory(
1556 VkDeviceMemory _memory
,
1557 VkDeviceSize memoryOffset
)
1559 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1560 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1563 image
->bo
= mem
->bo
;
1564 image
->offset
= memoryOffset
;
1573 VkResult
radv_QueueBindSparse(
1575 uint32_t bindInfoCount
,
1576 const VkBindSparseInfo
* pBindInfo
,
1579 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER
);
1582 VkResult
radv_CreateFence(
1584 const VkFenceCreateInfo
* pCreateInfo
,
1585 const VkAllocationCallbacks
* pAllocator
,
1588 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1589 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
1591 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1594 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1596 memset(fence
, 0, sizeof(*fence
));
1597 fence
->submitted
= false;
1598 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
1599 fence
->fence
= device
->ws
->create_fence();
1600 if (!fence
->fence
) {
1601 vk_free2(&device
->alloc
, pAllocator
, fence
);
1602 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1605 *pFence
= radv_fence_to_handle(fence
);
1610 void radv_DestroyFence(
1613 const VkAllocationCallbacks
* pAllocator
)
1615 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1616 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1620 device
->ws
->destroy_fence(fence
->fence
);
1621 vk_free2(&device
->alloc
, pAllocator
, fence
);
1624 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
1626 uint64_t current_time
;
1629 clock_gettime(CLOCK_MONOTONIC
, &tv
);
1630 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
1632 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
1634 return current_time
+ timeout
;
1637 VkResult
radv_WaitForFences(
1639 uint32_t fenceCount
,
1640 const VkFence
* pFences
,
1644 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1645 timeout
= radv_get_absolute_timeout(timeout
);
1647 if (!waitAll
&& fenceCount
> 1) {
1648 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
1651 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
1652 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
1653 bool expired
= false;
1655 if (fence
->signalled
)
1658 if (!fence
->submitted
)
1661 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
1665 fence
->signalled
= true;
1671 VkResult
radv_ResetFences(VkDevice device
,
1672 uint32_t fenceCount
,
1673 const VkFence
*pFences
)
1675 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
1676 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
1677 fence
->submitted
= fence
->signalled
= false;
1683 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
1685 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1686 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1688 if (fence
->signalled
)
1690 if (!fence
->submitted
)
1691 return VK_NOT_READY
;
1693 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
1694 return VK_NOT_READY
;
1700 // Queue semaphore functions
1702 VkResult
radv_CreateSemaphore(
1704 const VkSemaphoreCreateInfo
* pCreateInfo
,
1705 const VkAllocationCallbacks
* pAllocator
,
1706 VkSemaphore
* pSemaphore
)
1708 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1709 struct radeon_winsys_sem
*sem
;
1711 sem
= device
->ws
->create_sem(device
->ws
);
1713 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1715 *pSemaphore
= (VkSemaphore
)sem
;
1719 void radv_DestroySemaphore(
1721 VkSemaphore _semaphore
,
1722 const VkAllocationCallbacks
* pAllocator
)
1724 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1725 struct radeon_winsys_sem
*sem
;
1729 sem
= (struct radeon_winsys_sem
*)_semaphore
;
1730 device
->ws
->destroy_sem(sem
);
1733 VkResult
radv_CreateEvent(
1735 const VkEventCreateInfo
* pCreateInfo
,
1736 const VkAllocationCallbacks
* pAllocator
,
1739 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1740 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
1742 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1745 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1747 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
1749 RADEON_FLAG_CPU_ACCESS
);
1751 vk_free2(&device
->alloc
, pAllocator
, event
);
1752 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1755 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
1757 *pEvent
= radv_event_to_handle(event
);
1762 void radv_DestroyEvent(
1765 const VkAllocationCallbacks
* pAllocator
)
1767 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1768 RADV_FROM_HANDLE(radv_event
, event
, _event
);
1772 device
->ws
->buffer_destroy(event
->bo
);
1773 vk_free2(&device
->alloc
, pAllocator
, event
);
1776 VkResult
radv_GetEventStatus(
1780 RADV_FROM_HANDLE(radv_event
, event
, _event
);
1782 if (*event
->map
== 1)
1783 return VK_EVENT_SET
;
1784 return VK_EVENT_RESET
;
1787 VkResult
radv_SetEvent(
1791 RADV_FROM_HANDLE(radv_event
, event
, _event
);
1797 VkResult
radv_ResetEvent(
1801 RADV_FROM_HANDLE(radv_event
, event
, _event
);
1807 VkResult
radv_CreateBuffer(
1809 const VkBufferCreateInfo
* pCreateInfo
,
1810 const VkAllocationCallbacks
* pAllocator
,
1813 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1814 struct radv_buffer
*buffer
;
1816 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
1818 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
1819 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1821 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1823 buffer
->size
= pCreateInfo
->size
;
1824 buffer
->usage
= pCreateInfo
->usage
;
1828 *pBuffer
= radv_buffer_to_handle(buffer
);
1833 void radv_DestroyBuffer(
1836 const VkAllocationCallbacks
* pAllocator
)
1838 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1839 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1844 vk_free2(&device
->alloc
, pAllocator
, buffer
);
1847 static inline unsigned
1848 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
1851 return image
->surface
.stencil_tiling_index
[level
];
1853 return image
->surface
.tiling_index
[level
];
1857 radv_initialise_color_surface(struct radv_device
*device
,
1858 struct radv_color_buffer_info
*cb
,
1859 struct radv_image_view
*iview
)
1861 const struct vk_format_description
*desc
;
1862 unsigned ntype
, format
, swap
, endian
;
1863 unsigned blend_clamp
= 0, blend_bypass
= 0;
1864 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
1866 const struct radeon_surf
*surf
= &iview
->image
->surface
;
1867 const struct radeon_surf_level
*level_info
= &surf
->level
[iview
->base_mip
];
1869 desc
= vk_format_description(iview
->vk_format
);
1871 memset(cb
, 0, sizeof(*cb
));
1873 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
1874 va
+= level_info
->offset
;
1875 cb
->cb_color_base
= va
>> 8;
1877 /* CMASK variables */
1878 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
1879 va
+= iview
->image
->cmask
.offset
;
1880 cb
->cb_color_cmask
= va
>> 8;
1881 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
1883 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
1884 va
+= iview
->image
->dcc_offset
;
1885 cb
->cb_dcc_base
= va
>> 8;
1887 uint32_t max_slice
= iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
1888 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
1889 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
1891 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
1892 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
1893 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
1894 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
1896 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
1897 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
1899 /* Intensity is implemented as Red, so treat it that way. */
1900 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
) |
1901 S_028C74_TILE_MODE_INDEX(tile_mode_index
);
1903 if (iview
->image
->samples
> 1) {
1904 unsigned log_samples
= util_logbase2(iview
->image
->samples
);
1906 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1907 S_028C74_NUM_FRAGMENTS(log_samples
);
1910 if (iview
->image
->fmask
.size
) {
1911 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
1912 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1913 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
1914 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
1915 cb
->cb_color_fmask
= va
>> 8;
1916 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
1918 /* This must be set for fast clear to work without FMASK. */
1919 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1920 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
1921 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
1922 cb
->cb_color_fmask
= cb
->cb_color_base
;
1923 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
1926 ntype
= radv_translate_color_numformat(iview
->vk_format
,
1928 vk_format_get_first_non_void_channel(iview
->vk_format
));
1929 format
= radv_translate_colorformat(iview
->vk_format
);
1930 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
1931 radv_finishme("Illegal color\n");
1932 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
1933 endian
= radv_colorformat_endian_swap(format
);
1935 /* blend clamp should be set for all NORM/SRGB types */
1936 if (ntype
== V_028C70_NUMBER_UNORM
||
1937 ntype
== V_028C70_NUMBER_SNORM
||
1938 ntype
== V_028C70_NUMBER_SRGB
)
1941 /* set blend bypass according to docs if SINT/UINT or
1942 8/24 COLOR variants */
1943 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1944 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1945 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1950 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
1951 (format
== V_028C70_COLOR_8
||
1952 format
== V_028C70_COLOR_8_8
||
1953 format
== V_028C70_COLOR_8_8_8_8
))
1954 ->color_is_int8
= true;
1956 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
1957 S_028C70_COMP_SWAP(swap
) |
1958 S_028C70_BLEND_CLAMP(blend_clamp
) |
1959 S_028C70_BLEND_BYPASS(blend_bypass
) |
1960 S_028C70_SIMPLE_FLOAT(1) |
1961 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
1962 ntype
!= V_028C70_NUMBER_SNORM
&&
1963 ntype
!= V_028C70_NUMBER_SRGB
&&
1964 format
!= V_028C70_COLOR_8_24
&&
1965 format
!= V_028C70_COLOR_24_8
) |
1966 S_028C70_NUMBER_TYPE(ntype
) |
1967 S_028C70_ENDIAN(endian
);
1968 if (iview
->image
->samples
> 1)
1969 if (iview
->image
->fmask
.size
)
1970 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
1972 if (iview
->image
->cmask
.size
&&
1973 (device
->debug_flags
& RADV_DEBUG_FAST_CLEARS
))
1974 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1976 if (iview
->image
->surface
.dcc_size
&& level_info
->dcc_enabled
)
1977 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
1979 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
1980 unsigned max_uncompressed_block_size
= 2;
1981 if (iview
->image
->samples
> 1) {
1982 if (iview
->image
->surface
.bpe
== 1)
1983 max_uncompressed_block_size
= 0;
1984 else if (iview
->image
->surface
.bpe
== 2)
1985 max_uncompressed_block_size
= 1;
1988 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
1989 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1992 /* This must be set for fast clear to work without FMASK. */
1993 if (!iview
->image
->fmask
.size
&&
1994 device
->physical_device
->rad_info
.chip_class
== SI
) {
1995 unsigned bankh
= util_logbase2(iview
->image
->surface
.bankh
);
1996 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2001 radv_initialise_ds_surface(struct radv_device
*device
,
2002 struct radv_ds_buffer_info
*ds
,
2003 struct radv_image_view
*iview
)
2005 unsigned level
= iview
->base_mip
;
2007 uint64_t va
, s_offs
, z_offs
;
2008 const struct radeon_surf_level
*level_info
= &iview
->image
->surface
.level
[level
];
2009 memset(ds
, 0, sizeof(*ds
));
2010 switch (iview
->vk_format
) {
2011 case VK_FORMAT_D24_UNORM_S8_UINT
:
2012 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2013 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2014 ds
->offset_scale
= 2.0f
;
2016 case VK_FORMAT_D16_UNORM
:
2017 case VK_FORMAT_D16_UNORM_S8_UINT
:
2018 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2019 ds
->offset_scale
= 4.0f
;
2021 case VK_FORMAT_D32_SFLOAT
:
2022 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2023 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2024 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2025 ds
->offset_scale
= 1.0f
;
2031 format
= radv_translate_dbformat(iview
->vk_format
);
2032 if (format
== V_028040_Z_INVALID
) {
2033 fprintf(stderr
, "Invalid DB format: %d, disabling DB.\n", iview
->vk_format
);
2036 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2037 s_offs
= z_offs
= va
;
2038 z_offs
+= iview
->image
->surface
.level
[level
].offset
;
2039 s_offs
+= iview
->image
->surface
.stencil_level
[level
].offset
;
2041 uint32_t max_slice
= iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2042 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2043 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2044 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2045 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2047 if (iview
->image
->samples
> 1)
2048 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->samples
));
2050 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
)
2051 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2053 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2055 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2056 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2057 unsigned tiling_index
= iview
->image
->surface
.tiling_index
[level
];
2058 unsigned stencil_index
= iview
->image
->surface
.stencil_tiling_index
[level
];
2059 unsigned macro_index
= iview
->image
->surface
.macro_tile_index
;
2060 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2061 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2062 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2064 ds
->db_depth_info
|=
2065 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2066 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2067 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2068 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2069 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2070 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2071 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2072 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2074 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2075 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2076 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2077 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2080 if (iview
->image
->htile
.size
&& !level
) {
2081 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2082 S_028040_ALLOW_EXPCLEAR(1);
2084 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2085 /* Workaround: For a not yet understood reason, the
2086 * combination of MSAA, fast stencil clear and stencil
2087 * decompress messes with subsequent stencil buffer
2088 * uses. Problem was reproduced on Verde, Bonaire,
2089 * Tonga, and Carrizo.
2091 * Disabling EXPCLEAR works around the problem.
2093 * Check piglit's arb_texture_multisample-stencil-clear
2094 * test if you want to try changing this.
2096 if (iview
->image
->samples
<= 1)
2097 ds
->db_stencil_info
|= S_028044_ALLOW_EXPCLEAR(1);
2099 /* Use all of the htile_buffer for depth if there's no stencil. */
2100 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2102 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2103 iview
->image
->htile
.offset
;
2104 ds
->db_htile_data_base
= va
>> 8;
2105 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2107 ds
->db_htile_data_base
= 0;
2108 ds
->db_htile_surface
= 0;
2111 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
2112 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
2114 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2115 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2116 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
2119 VkResult
radv_CreateFramebuffer(
2121 const VkFramebufferCreateInfo
* pCreateInfo
,
2122 const VkAllocationCallbacks
* pAllocator
,
2123 VkFramebuffer
* pFramebuffer
)
2125 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2126 struct radv_framebuffer
*framebuffer
;
2128 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
2130 size_t size
= sizeof(*framebuffer
) +
2131 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
2132 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
2133 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2134 if (framebuffer
== NULL
)
2135 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2137 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
2138 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
2139 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
2140 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
2141 framebuffer
->attachments
[i
].attachment
= iview
;
2142 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
2143 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
2144 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2145 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
2149 framebuffer
->width
= pCreateInfo
->width
;
2150 framebuffer
->height
= pCreateInfo
->height
;
2151 framebuffer
->layers
= pCreateInfo
->layers
;
2153 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
2157 void radv_DestroyFramebuffer(
2160 const VkAllocationCallbacks
* pAllocator
)
2162 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2163 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
2167 vk_free2(&device
->alloc
, pAllocator
, fb
);
2170 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
2172 switch (address_mode
) {
2173 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
2174 return V_008F30_SQ_TEX_WRAP
;
2175 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
2176 return V_008F30_SQ_TEX_MIRROR
;
2177 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
2178 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
2179 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
2180 return V_008F30_SQ_TEX_CLAMP_BORDER
;
2181 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
2182 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2184 unreachable("illegal tex wrap mode");
2190 radv_tex_compare(VkCompareOp op
)
2193 case VK_COMPARE_OP_NEVER
:
2194 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
2195 case VK_COMPARE_OP_LESS
:
2196 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
2197 case VK_COMPARE_OP_EQUAL
:
2198 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2199 case VK_COMPARE_OP_LESS_OR_EQUAL
:
2200 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2201 case VK_COMPARE_OP_GREATER
:
2202 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
2203 case VK_COMPARE_OP_NOT_EQUAL
:
2204 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2205 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
2206 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2207 case VK_COMPARE_OP_ALWAYS
:
2208 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2210 unreachable("illegal compare mode");
2216 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
2219 case VK_FILTER_NEAREST
:
2220 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
2221 V_008F38_SQ_TEX_XY_FILTER_POINT
);
2222 case VK_FILTER_LINEAR
:
2223 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
2224 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
2225 case VK_FILTER_CUBIC_IMG
:
2227 fprintf(stderr
, "illegal texture filter");
2233 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
2236 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
2237 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
2238 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
2239 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
2241 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
2246 radv_tex_bordercolor(VkBorderColor bcolor
)
2249 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
2250 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
2251 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2252 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
2253 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
2254 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
2255 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
2256 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
2257 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
2265 radv_tex_aniso_filter(unsigned filter
)
2279 radv_init_sampler(struct radv_device
*device
,
2280 struct radv_sampler
*sampler
,
2281 const VkSamplerCreateInfo
*pCreateInfo
)
2283 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
2284 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
2285 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
2286 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
2288 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
2289 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
2290 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
2291 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
2292 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
2293 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
2294 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
2295 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
2296 S_008F30_DISABLE_CUBE_WRAP(0) |
2297 S_008F30_COMPAT_MODE(is_vi
));
2298 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
2299 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
2300 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
2301 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
2302 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
2303 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
2304 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
2305 S_008F38_MIP_POINT_PRECLAMP(1) |
2306 S_008F38_DISABLE_LSB_CEIL(1) |
2307 S_008F38_FILTER_PREC_FIX(1) |
2308 S_008F38_ANISO_OVERRIDE(is_vi
));
2309 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2310 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
2313 VkResult
radv_CreateSampler(
2315 const VkSamplerCreateInfo
* pCreateInfo
,
2316 const VkAllocationCallbacks
* pAllocator
,
2317 VkSampler
* pSampler
)
2319 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2320 struct radv_sampler
*sampler
;
2322 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
2324 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
2325 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2327 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2329 radv_init_sampler(device
, sampler
, pCreateInfo
);
2330 *pSampler
= radv_sampler_to_handle(sampler
);
2335 void radv_DestroySampler(
2338 const VkAllocationCallbacks
* pAllocator
)
2340 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2341 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
2345 vk_free2(&device
->alloc
, pAllocator
, sampler
);
2349 /* vk_icd.h does not declare this function, so we declare it here to
2350 * suppress Wmissing-prototypes.
2352 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2353 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
2355 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2356 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
2358 /* For the full details on loader interface versioning, see
2359 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2360 * What follows is a condensed summary, to help you navigate the large and
2361 * confusing official doc.
2363 * - Loader interface v0 is incompatible with later versions. We don't
2366 * - In loader interface v1:
2367 * - The first ICD entrypoint called by the loader is
2368 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2370 * - The ICD must statically expose no other Vulkan symbol unless it is
2371 * linked with -Bsymbolic.
2372 * - Each dispatchable Vulkan handle created by the ICD must be
2373 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2374 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2375 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2376 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2377 * such loader-managed surfaces.
2379 * - Loader interface v2 differs from v1 in:
2380 * - The first ICD entrypoint called by the loader is
2381 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2382 * statically expose this entrypoint.
2384 * - Loader interface v3 differs from v2 in:
2385 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2386 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2387 * because the loader no longer does so.
2389 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);