projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/gfx10: double the number of tessellation offchip buffers per SE
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 /* Out-of-order primitive rasterization. */
367 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
368 device->rad_info.max_se >= 2;
369 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
370 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
371
372 device->dcc_msaa_allowed =
373 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
374
375 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
376 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
377 (device->rad_info.chip_class >= GFX8 &&
378 device->rad_info.me_fw_feature >= 41);
379
380 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
381 device->rad_info.chip_class >= GFX10;
382
383 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
384
385 radv_physical_device_init_mem_types(device);
386 radv_fill_device_extension_table(device, &device->supported_extensions);
387
388 device->bus_info = *drm_device->businfo.pci;
389
390 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
391 ac_print_gpu_info(&device->rad_info);
392
393 /* The WSI is structured as a layer on top of the driver, so this has
394 * to be the last part of initialization (at least until we get other
395 * semi-layers).
396 */
397 result = radv_init_wsi(device);
398 if (result != VK_SUCCESS) {
399 device->ws->destroy(device->ws);
400 vk_error(instance, result);
401 goto fail;
402 }
403
404 return VK_SUCCESS;
405
406 fail:
407 close(fd);
408 if (master_fd != -1)
409 close(master_fd);
410 return result;
411 }
412
413 static void
414 radv_physical_device_finish(struct radv_physical_device *device)
415 {
416 radv_finish_wsi(device);
417 device->ws->destroy(device->ws);
418 disk_cache_destroy(device->disk_cache);
419 close(device->local_fd);
420 if (device->master_fd != -1)
421 close(device->master_fd);
422 }
423
424 static void *
425 default_alloc_func(void *pUserData, size_t size, size_t align,
426 VkSystemAllocationScope allocationScope)
427 {
428 return malloc(size);
429 }
430
431 static void *
432 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
433 size_t align, VkSystemAllocationScope allocationScope)
434 {
435 return realloc(pOriginal, size);
436 }
437
438 static void
439 default_free_func(void *pUserData, void *pMemory)
440 {
441 free(pMemory);
442 }
443
444 static const VkAllocationCallbacks default_alloc = {
445 .pUserData = NULL,
446 .pfnAllocation = default_alloc_func,
447 .pfnReallocation = default_realloc_func,
448 .pfnFree = default_free_func,
449 };
450
451 static const struct debug_control radv_debug_options[] = {
452 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
453 {"nodcc", RADV_DEBUG_NO_DCC},
454 {"shaders", RADV_DEBUG_DUMP_SHADERS},
455 {"nocache", RADV_DEBUG_NO_CACHE},
456 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
457 {"nohiz", RADV_DEBUG_NO_HIZ},
458 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
459 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
460 {"allbos", RADV_DEBUG_ALL_BOS},
461 {"noibs", RADV_DEBUG_NO_IBS},
462 {"spirv", RADV_DEBUG_DUMP_SPIRV},
463 {"vmfaults", RADV_DEBUG_VM_FAULTS},
464 {"zerovram", RADV_DEBUG_ZERO_VRAM},
465 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
466 {"nosisched", RADV_DEBUG_NO_SISCHED},
467 {"preoptir", RADV_DEBUG_PREOPTIR},
468 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
469 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
470 {"info", RADV_DEBUG_INFO},
471 {"errors", RADV_DEBUG_ERRORS},
472 {"startup", RADV_DEBUG_STARTUP},
473 {"checkir", RADV_DEBUG_CHECKIR},
474 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
475 {"nobinning", RADV_DEBUG_NOBINNING},
476 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
477 {NULL, 0}
478 };
479
480 const char *
481 radv_get_debug_option_name(int id)
482 {
483 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
484 return radv_debug_options[id].string;
485 }
486
487 static const struct debug_control radv_perftest_options[] = {
488 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
489 {"sisched", RADV_PERFTEST_SISCHED},
490 {"localbos", RADV_PERFTEST_LOCAL_BOS},
491 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
492 {"bolist", RADV_PERFTEST_BO_LIST},
493 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
494 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
495 {NULL, 0}
496 };
497
498 const char *
499 radv_get_perftest_option_name(int id)
500 {
501 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
502 return radv_perftest_options[id].string;
503 }
504
505 static void
506 radv_handle_per_app_options(struct radv_instance *instance,
507 const VkApplicationInfo *info)
508 {
509 const char *name = info ? info->pApplicationName : NULL;
510
511 if (!name)
512 return;
513
514 if (!strcmp(name, "Talos - Linux - 32bit") ||
515 !strcmp(name, "Talos - Linux - 64bit")) {
516 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
517 /* Force enable LLVM sisched for Talos because it looks
518 * safe and it gives few more FPS.
519 */
520 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
521 }
522 } else if (!strcmp(name, "DOOM_VFR")) {
523 /* Work around a Doom VFR game bug */
524 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
525 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
526 /* Workaround for a WaW hazard when LLVM moves/merges
527 * load/store memory operations.
528 * See https://reviews.llvm.org/D61313
529 */
530 if (HAVE_LLVM < 0x900)
531 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
532 }
533 }
534
535 static int radv_get_instance_extension_index(const char *name)
536 {
537 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
538 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
539 return i;
540 }
541 return -1;
542 }
543
544 static const char radv_dri_options_xml[] =
545 DRI_CONF_BEGIN
546 DRI_CONF_SECTION_QUALITY
547 DRI_CONF_ADAPTIVE_SYNC("true")
548 DRI_CONF_SECTION_END
549 DRI_CONF_END;
550
551 static void radv_init_dri_options(struct radv_instance *instance)
552 {
553 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
554 driParseConfigFiles(&instance->dri_options,
555 &instance->available_dri_options,
556 0, "radv", NULL);
557 }
558
559 VkResult radv_CreateInstance(
560 const VkInstanceCreateInfo* pCreateInfo,
561 const VkAllocationCallbacks* pAllocator,
562 VkInstance* pInstance)
563 {
564 struct radv_instance *instance;
565 VkResult result;
566
567 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
568
569 uint32_t client_version;
570 if (pCreateInfo->pApplicationInfo &&
571 pCreateInfo->pApplicationInfo->apiVersion != 0) {
572 client_version = pCreateInfo->pApplicationInfo->apiVersion;
573 } else {
574 client_version = VK_API_VERSION_1_0;
575 }
576
577 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
578 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
579 if (!instance)
580 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
581
582 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
583
584 if (pAllocator)
585 instance->alloc = *pAllocator;
586 else
587 instance->alloc = default_alloc;
588
589 instance->apiVersion = client_version;
590 instance->physicalDeviceCount = -1;
591
592 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
593 radv_debug_options);
594
595 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
596 radv_perftest_options);
597
598
599 if (instance->debug_flags & RADV_DEBUG_STARTUP)
600 radv_logi("Created an instance");
601
602 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
603 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
604 int index = radv_get_instance_extension_index(ext_name);
605
606 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
607 vk_free2(&default_alloc, pAllocator, instance);
608 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
609 }
610
611 instance->enabled_extensions.extensions[index] = true;
612 }
613
614 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
615 if (result != VK_SUCCESS) {
616 vk_free2(&default_alloc, pAllocator, instance);
617 return vk_error(instance, result);
618 }
619
620 _mesa_locale_init();
621 glsl_type_singleton_init_or_ref();
622
623 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
624
625 radv_init_dri_options(instance);
626 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
627
628 *pInstance = radv_instance_to_handle(instance);
629
630 return VK_SUCCESS;
631 }
632
633 void radv_DestroyInstance(
634 VkInstance _instance,
635 const VkAllocationCallbacks* pAllocator)
636 {
637 RADV_FROM_HANDLE(radv_instance, instance, _instance);
638
639 if (!instance)
640 return;
641
642 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
643 radv_physical_device_finish(instance->physicalDevices + i);
644 }
645
646 VG(VALGRIND_DESTROY_MEMPOOL(instance));
647
648 glsl_type_singleton_decref();
649 _mesa_locale_fini();
650
651 driDestroyOptionCache(&instance->dri_options);
652 driDestroyOptionInfo(&instance->available_dri_options);
653
654 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
655
656 vk_free(&instance->alloc, instance);
657 }
658
659 static VkResult
660 radv_enumerate_devices(struct radv_instance *instance)
661 {
662 /* TODO: Check for more devices ? */
663 drmDevicePtr devices[8];
664 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
665 int max_devices;
666
667 instance->physicalDeviceCount = 0;
668
669 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
670
671 if (instance->debug_flags & RADV_DEBUG_STARTUP)
672 radv_logi("Found %d drm nodes", max_devices);
673
674 if (max_devices < 1)
675 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
676
677 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
678 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
679 devices[i]->bustype == DRM_BUS_PCI &&
680 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
681
682 result = radv_physical_device_init(instance->physicalDevices +
683 instance->physicalDeviceCount,
684 instance,
685 devices[i]);
686 if (result == VK_SUCCESS)
687 ++instance->physicalDeviceCount;
688 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
689 break;
690 }
691 }
692 drmFreeDevices(devices, max_devices);
693
694 return result;
695 }
696
697 VkResult radv_EnumeratePhysicalDevices(
698 VkInstance _instance,
699 uint32_t* pPhysicalDeviceCount,
700 VkPhysicalDevice* pPhysicalDevices)
701 {
702 RADV_FROM_HANDLE(radv_instance, instance, _instance);
703 VkResult result;
704
705 if (instance->physicalDeviceCount < 0) {
706 result = radv_enumerate_devices(instance);
707 if (result != VK_SUCCESS &&
708 result != VK_ERROR_INCOMPATIBLE_DRIVER)
709 return result;
710 }
711
712 if (!pPhysicalDevices) {
713 *pPhysicalDeviceCount = instance->physicalDeviceCount;
714 } else {
715 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
716 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
717 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
718 }
719
720 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
721 : VK_SUCCESS;
722 }
723
724 VkResult radv_EnumeratePhysicalDeviceGroups(
725 VkInstance _instance,
726 uint32_t* pPhysicalDeviceGroupCount,
727 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
728 {
729 RADV_FROM_HANDLE(radv_instance, instance, _instance);
730 VkResult result;
731
732 if (instance->physicalDeviceCount < 0) {
733 result = radv_enumerate_devices(instance);
734 if (result != VK_SUCCESS &&
735 result != VK_ERROR_INCOMPATIBLE_DRIVER)
736 return result;
737 }
738
739 if (!pPhysicalDeviceGroupProperties) {
740 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
741 } else {
742 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
743 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
744 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
745 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
746 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
747 }
748 }
749 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
750 : VK_SUCCESS;
751 }
752
753 void radv_GetPhysicalDeviceFeatures(
754 VkPhysicalDevice physicalDevice,
755 VkPhysicalDeviceFeatures* pFeatures)
756 {
757 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
758 memset(pFeatures, 0, sizeof(*pFeatures));
759
760 *pFeatures = (VkPhysicalDeviceFeatures) {
761 .robustBufferAccess = true,
762 .fullDrawIndexUint32 = true,
763 .imageCubeArray = true,
764 .independentBlend = true,
765 .geometryShader = pdevice->rad_info.chip_class < GFX10,
766 .tessellationShader = pdevice->rad_info.chip_class < GFX10,
767 .sampleRateShading = true,
768 .dualSrcBlend = true,
769 .logicOp = true,
770 .multiDrawIndirect = true,
771 .drawIndirectFirstInstance = true,
772 .depthClamp = true,
773 .depthBiasClamp = true,
774 .fillModeNonSolid = true,
775 .depthBounds = true,
776 .wideLines = true,
777 .largePoints = true,
778 .alphaToOne = true,
779 .multiViewport = true,
780 .samplerAnisotropy = true,
781 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
782 .textureCompressionASTC_LDR = false,
783 .textureCompressionBC = true,
784 .occlusionQueryPrecise = true,
785 .pipelineStatisticsQuery = true,
786 .vertexPipelineStoresAndAtomics = true,
787 .fragmentStoresAndAtomics = true,
788 .shaderTessellationAndGeometryPointSize = true,
789 .shaderImageGatherExtended = true,
790 .shaderStorageImageExtendedFormats = true,
791 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
792 .shaderUniformBufferArrayDynamicIndexing = true,
793 .shaderSampledImageArrayDynamicIndexing = true,
794 .shaderStorageBufferArrayDynamicIndexing = true,
795 .shaderStorageImageArrayDynamicIndexing = true,
796 .shaderStorageImageReadWithoutFormat = true,
797 .shaderStorageImageWriteWithoutFormat = true,
798 .shaderClipDistance = true,
799 .shaderCullDistance = true,
800 .shaderFloat64 = true,
801 .shaderInt64 = true,
802 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
803 .sparseBinding = true,
804 .variableMultisampleRate = true,
805 .inheritedQueries = true,
806 };
807 }
808
809 void radv_GetPhysicalDeviceFeatures2(
810 VkPhysicalDevice physicalDevice,
811 VkPhysicalDeviceFeatures2 *pFeatures)
812 {
813 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
814 vk_foreach_struct(ext, pFeatures->pNext) {
815 switch (ext->sType) {
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
817 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
818 features->variablePointersStorageBuffer = true;
819 features->variablePointers = true;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
823 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
824 features->multiview = true;
825 features->multiviewGeometryShader = true;
826 features->multiviewTessellationShader = true;
827 break;
828 }
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
830 VkPhysicalDeviceShaderDrawParametersFeatures *features =
831 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
832 features->shaderDrawParameters = true;
833 break;
834 }
835 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
836 VkPhysicalDeviceProtectedMemoryFeatures *features =
837 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
838 features->protectedMemory = false;
839 break;
840 }
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
842 VkPhysicalDevice16BitStorageFeatures *features =
843 (VkPhysicalDevice16BitStorageFeatures*)ext;
844 bool enabled = pdevice->rad_info.chip_class >= GFX8;
845 features->storageBuffer16BitAccess = enabled;
846 features->uniformAndStorageBuffer16BitAccess = enabled;
847 features->storagePushConstant16 = enabled;
848 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
852 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
853 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
854 features->samplerYcbcrConversion = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
858 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
859 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
860 features->shaderInputAttachmentArrayDynamicIndexing = true;
861 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
862 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
863 features->shaderUniformBufferArrayNonUniformIndexing = true;
864 features->shaderSampledImageArrayNonUniformIndexing = true;
865 features->shaderStorageBufferArrayNonUniformIndexing = true;
866 features->shaderStorageImageArrayNonUniformIndexing = true;
867 features->shaderInputAttachmentArrayNonUniformIndexing = true;
868 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
869 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
870 features->descriptorBindingUniformBufferUpdateAfterBind = true;
871 features->descriptorBindingSampledImageUpdateAfterBind = true;
872 features->descriptorBindingStorageImageUpdateAfterBind = true;
873 features->descriptorBindingStorageBufferUpdateAfterBind = true;
874 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
875 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
876 features->descriptorBindingUpdateUnusedWhilePending = true;
877 features->descriptorBindingPartiallyBound = true;
878 features->descriptorBindingVariableDescriptorCount = true;
879 features->runtimeDescriptorArray = true;
880 break;
881 }
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
883 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
884 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
885 features->conditionalRendering = true;
886 features->inheritedConditionalRendering = false;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
890 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
891 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
892 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
893 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
897 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
898 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
899 features->transformFeedback = true;
900 features->geometryStreams = true;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
904 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
905 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
906 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
910 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
911 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
912 features->memoryPriority = VK_TRUE;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
916 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
917 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
918 features->bufferDeviceAddress = true;
919 features->bufferDeviceAddressCaptureReplay = false;
920 features->bufferDeviceAddressMultiDevice = false;
921 break;
922 }
923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
924 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
925 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
926 features->depthClipEnable = true;
927 break;
928 }
929 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
930 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
931 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
932 features->hostQueryReset = true;
933 break;
934 }
935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
936 VkPhysicalDevice8BitStorageFeaturesKHR *features =
937 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
938 bool enabled = pdevice->rad_info.chip_class >= GFX8;
939 features->storageBuffer8BitAccess = enabled;
940 features->uniformAndStorageBuffer8BitAccess = enabled;
941 features->storagePushConstant8 = enabled;
942 break;
943 }
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
945 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
946 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
947 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
948 features->shaderInt8 = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
952 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
953 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
954 /* TODO: Enable this once the driver supports 64-bit
955 * compare&swap atomic operations.
956 */
957 features->shaderBufferInt64Atomics = false;
958 features->shaderSharedInt64Atomics = false;
959 break;
960 }
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
962 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
963 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
964
965 features->inlineUniformBlock = true;
966 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
970 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
971 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
972 features->computeDerivativeGroupQuads = false;
973 features->computeDerivativeGroupLinear = true;
974 break;
975 }
976 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
977 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
978 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
979 features->ycbcrImageArrays = true;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
983 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
984 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
985 features->uniformBufferStandardLayout = true;
986 break;
987 }
988 default:
989 break;
990 }
991 }
992 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
993 }
994
995 void radv_GetPhysicalDeviceProperties(
996 VkPhysicalDevice physicalDevice,
997 VkPhysicalDeviceProperties* pProperties)
998 {
999 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1000 VkSampleCountFlags sample_counts = 0xf;
1001
1002 /* make sure that the entire descriptor set is addressable with a signed
1003 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1004 * be at most 2 GiB. the combined image & samples object count as one of
1005 * both. This limit is for the pipeline layout, not for the set layout, but
1006 * there is no set limit, so we just set a pipeline limit. I don't think
1007 * any app is going to hit this soon. */
1008 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1009 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1010 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1011 32 /* sampler, largest when combined with image */ +
1012 64 /* sampled image */ +
1013 64 /* storage image */);
1014
1015 VkPhysicalDeviceLimits limits = {
1016 .maxImageDimension1D = (1 << 14),
1017 .maxImageDimension2D = (1 << 14),
1018 .maxImageDimension3D = (1 << 11),
1019 .maxImageDimensionCube = (1 << 14),
1020 .maxImageArrayLayers = (1 << 11),
1021 .maxTexelBufferElements = 128 * 1024 * 1024,
1022 .maxUniformBufferRange = UINT32_MAX,
1023 .maxStorageBufferRange = UINT32_MAX,
1024 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1025 .maxMemoryAllocationCount = UINT32_MAX,
1026 .maxSamplerAllocationCount = 64 * 1024,
1027 .bufferImageGranularity = 64, /* A cache line */
1028 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1029 .maxBoundDescriptorSets = MAX_SETS,
1030 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1031 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1032 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1033 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1034 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1035 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1036 .maxPerStageResources = max_descriptor_set_size,
1037 .maxDescriptorSetSamplers = max_descriptor_set_size,
1038 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1039 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1040 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1041 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1042 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1043 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1044 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1045 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1046 .maxVertexInputBindings = MAX_VBS,
1047 .maxVertexInputAttributeOffset = 2047,
1048 .maxVertexInputBindingStride = 2048,
1049 .maxVertexOutputComponents = 128,
1050 .maxTessellationGenerationLevel = 64,
1051 .maxTessellationPatchSize = 32,
1052 .maxTessellationControlPerVertexInputComponents = 128,
1053 .maxTessellationControlPerVertexOutputComponents = 128,
1054 .maxTessellationControlPerPatchOutputComponents = 120,
1055 .maxTessellationControlTotalOutputComponents = 4096,
1056 .maxTessellationEvaluationInputComponents = 128,
1057 .maxTessellationEvaluationOutputComponents = 128,
1058 .maxGeometryShaderInvocations = 127,
1059 .maxGeometryInputComponents = 64,
1060 .maxGeometryOutputComponents = 128,
1061 .maxGeometryOutputVertices = 256,
1062 .maxGeometryTotalOutputComponents = 1024,
1063 .maxFragmentInputComponents = 128,
1064 .maxFragmentOutputAttachments = 8,
1065 .maxFragmentDualSrcAttachments = 1,
1066 .maxFragmentCombinedOutputResources = 8,
1067 .maxComputeSharedMemorySize = 32768,
1068 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1069 .maxComputeWorkGroupInvocations = 2048,
1070 .maxComputeWorkGroupSize = {
1071 2048,
1072 2048,
1073 2048
1074 },
1075 .subPixelPrecisionBits = 8,
1076 .subTexelPrecisionBits = 8,
1077 .mipmapPrecisionBits = 8,
1078 .maxDrawIndexedIndexValue = UINT32_MAX,
1079 .maxDrawIndirectCount = UINT32_MAX,
1080 .maxSamplerLodBias = 16,
1081 .maxSamplerAnisotropy = 16,
1082 .maxViewports = MAX_VIEWPORTS,
1083 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1084 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1085 .viewportSubPixelBits = 8,
1086 .minMemoryMapAlignment = 4096, /* A page */
1087 .minTexelBufferOffsetAlignment = 1,
1088 .minUniformBufferOffsetAlignment = 4,
1089 .minStorageBufferOffsetAlignment = 4,
1090 .minTexelOffset = -32,
1091 .maxTexelOffset = 31,
1092 .minTexelGatherOffset = -32,
1093 .maxTexelGatherOffset = 31,
1094 .minInterpolationOffset = -2,
1095 .maxInterpolationOffset = 2,
1096 .subPixelInterpolationOffsetBits = 8,
1097 .maxFramebufferWidth = (1 << 14),
1098 .maxFramebufferHeight = (1 << 14),
1099 .maxFramebufferLayers = (1 << 10),
1100 .framebufferColorSampleCounts = sample_counts,
1101 .framebufferDepthSampleCounts = sample_counts,
1102 .framebufferStencilSampleCounts = sample_counts,
1103 .framebufferNoAttachmentsSampleCounts = sample_counts,
1104 .maxColorAttachments = MAX_RTS,
1105 .sampledImageColorSampleCounts = sample_counts,
1106 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1107 .sampledImageDepthSampleCounts = sample_counts,
1108 .sampledImageStencilSampleCounts = sample_counts,
1109 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1110 .maxSampleMaskWords = 1,
1111 .timestampComputeAndGraphics = true,
1112 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1113 .maxClipDistances = 8,
1114 .maxCullDistances = 8,
1115 .maxCombinedClipAndCullDistances = 8,
1116 .discreteQueuePriorities = 2,
1117 .pointSizeRange = { 0.0, 8192.0 },
1118 .lineWidthRange = { 0.0, 7.9921875 },
1119 .pointSizeGranularity = (1.0 / 8.0),
1120 .lineWidthGranularity = (1.0 / 128.0),
1121 .strictLines = false, /* FINISHME */
1122 .standardSampleLocations = true,
1123 .optimalBufferCopyOffsetAlignment = 128,
1124 .optimalBufferCopyRowPitchAlignment = 128,
1125 .nonCoherentAtomSize = 64,
1126 };
1127
1128 *pProperties = (VkPhysicalDeviceProperties) {
1129 .apiVersion = radv_physical_device_api_version(pdevice),
1130 .driverVersion = vk_get_driver_version(),
1131 .vendorID = ATI_VENDOR_ID,
1132 .deviceID = pdevice->rad_info.pci_id,
1133 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1134 .limits = limits,
1135 .sparseProperties = {0},
1136 };
1137
1138 strcpy(pProperties->deviceName, pdevice->name);
1139 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1140 }
1141
1142 void radv_GetPhysicalDeviceProperties2(
1143 VkPhysicalDevice physicalDevice,
1144 VkPhysicalDeviceProperties2 *pProperties)
1145 {
1146 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1147 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1148
1149 vk_foreach_struct(ext, pProperties->pNext) {
1150 switch (ext->sType) {
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1152 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1153 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1154 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1158 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1159 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1160 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1161 properties->deviceLUIDValid = false;
1162 break;
1163 }
1164 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1165 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1166 properties->maxMultiviewViewCount = MAX_VIEWS;
1167 properties->maxMultiviewInstanceIndex = INT_MAX;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1171 VkPhysicalDevicePointClippingProperties *properties =
1172 (VkPhysicalDevicePointClippingProperties*)ext;
1173 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1177 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1178 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1179 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1183 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1184 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1185 properties->minImportedHostPointerAlignment = 4096;
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1189 VkPhysicalDeviceSubgroupProperties *properties =
1190 (VkPhysicalDeviceSubgroupProperties*)ext;
1191 properties->subgroupSize = 64;
1192 properties->supportedStages = VK_SHADER_STAGE_ALL;
1193 properties->supportedOperations =
1194 VK_SUBGROUP_FEATURE_BASIC_BIT |
1195 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1196 VK_SUBGROUP_FEATURE_QUAD_BIT |
1197 VK_SUBGROUP_FEATURE_VOTE_BIT;
1198 if (pdevice->rad_info.chip_class >= GFX8) {
1199 properties->supportedOperations |=
1200 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1201 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1202 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1203 }
1204 properties->quadOperationsInAllStages = true;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1208 VkPhysicalDeviceMaintenance3Properties *properties =
1209 (VkPhysicalDeviceMaintenance3Properties*)ext;
1210 /* Make sure everything is addressable by a signed 32-bit int, and
1211 * our largest descriptors are 96 bytes. */
1212 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1213 /* Our buffer size fields allow only this much */
1214 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1218 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1219 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1220 /* GFX6-8 only support single channel min/max filter. */
1221 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1222 properties->filterMinmaxSingleComponentFormats = true;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1226 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1227 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1228
1229 /* Shader engines. */
1230 properties->shaderEngineCount =
1231 pdevice->rad_info.max_se;
1232 properties->shaderArraysPerEngineCount =
1233 pdevice->rad_info.max_sh_per_se;
1234 properties->computeUnitsPerShaderArray =
1235 pdevice->rad_info.num_good_cu_per_sh;
1236 properties->simdPerComputeUnit = 4;
1237 properties->wavefrontsPerSimd =
1238 pdevice->rad_info.family == CHIP_TONGA ||
1239 pdevice->rad_info.family == CHIP_ICELAND ||
1240 pdevice->rad_info.family == CHIP_POLARIS10 ||
1241 pdevice->rad_info.family == CHIP_POLARIS11 ||
1242 pdevice->rad_info.family == CHIP_POLARIS12 ||
1243 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1244 properties->wavefrontSize = 64;
1245
1246 /* SGPR. */
1247 properties->sgprsPerSimd =
1248 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1249 properties->minSgprAllocation =
1250 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1251 properties->maxSgprAllocation =
1252 pdevice->rad_info.family == CHIP_TONGA ||
1253 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1254 properties->sgprAllocationGranularity =
1255 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1256
1257 /* VGPR. */
1258 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1259 properties->minVgprAllocation = 4;
1260 properties->maxVgprAllocation = 256;
1261 properties->vgprAllocationGranularity = 4;
1262 break;
1263 }
1264 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1265 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1266 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1267 properties->maxVertexAttribDivisor = UINT32_MAX;
1268 break;
1269 }
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1271 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1272 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1273 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1274 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1275 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1276 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1277 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1278 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1279 properties->robustBufferAccessUpdateAfterBind = false;
1280 properties->quadDivergentImplicitLod = false;
1281
1282 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1283 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1284 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1285 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1286 32 /* sampler, largest when combined with image */ +
1287 64 /* sampled image */ +
1288 64 /* storage image */);
1289 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1290 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1291 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1292 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1295 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1296 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1297 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1299 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1301 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1302 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1303 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1304 break;
1305 }
1306 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1307 VkPhysicalDeviceProtectedMemoryProperties *properties =
1308 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1309 properties->protectedNoFault = false;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1313 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1314 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1315 properties->primitiveOverestimationSize = 0;
1316 properties->maxExtraPrimitiveOverestimationSize = 0;
1317 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1318 properties->primitiveUnderestimation = VK_FALSE;
1319 properties->conservativePointAndLineRasterization = VK_FALSE;
1320 properties->degenerateTrianglesRasterized = VK_FALSE;
1321 properties->degenerateLinesRasterized = VK_FALSE;
1322 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1323 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1324 break;
1325 }
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1327 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1328 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1329 properties->pciDomain = pdevice->bus_info.domain;
1330 properties->pciBus = pdevice->bus_info.bus;
1331 properties->pciDevice = pdevice->bus_info.dev;
1332 properties->pciFunction = pdevice->bus_info.func;
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1336 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1337 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1338
1339 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1340 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1341 strcpy(driver_props->driverName, "radv");
1342
1343 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1344 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1345 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1346 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1347
1348 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1349 .major = 1,
1350 .minor = 1,
1351 .subminor = 2,
1352 .patch = 0,
1353 };
1354 break;
1355 }
1356 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1357 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1358 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1359 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1360 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1361 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1362 properties->maxTransformFeedbackStreamDataSize = 512;
1363 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1364 properties->maxTransformFeedbackBufferDataStride = 512;
1365 properties->transformFeedbackQueries = true;
1366 properties->transformFeedbackStreamsLinesTriangles = true;
1367 properties->transformFeedbackRasterizationStreamSelect = false;
1368 properties->transformFeedbackDraw = true;
1369 break;
1370 }
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1372 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1373 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1374
1375 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1376 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1377 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1378 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1379 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1380 break;
1381 }
1382 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1383 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1384 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1385 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1386 VK_SAMPLE_COUNT_4_BIT |
1387 VK_SAMPLE_COUNT_8_BIT;
1388 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1389 properties->sampleLocationCoordinateRange[0] = 0.0f;
1390 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1391 properties->sampleLocationSubPixelBits = 4;
1392 properties->variableSampleLocations = VK_FALSE;
1393 break;
1394 }
1395 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1396 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1397 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1398
1399 /* We support all of the depth resolve modes */
1400 properties->supportedDepthResolveModes =
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1402 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1403 VK_RESOLVE_MODE_MIN_BIT_KHR |
1404 VK_RESOLVE_MODE_MAX_BIT_KHR;
1405
1406 /* Average doesn't make sense for stencil so we don't support that */
1407 properties->supportedStencilResolveModes =
1408 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1409 VK_RESOLVE_MODE_MIN_BIT_KHR |
1410 VK_RESOLVE_MODE_MAX_BIT_KHR;
1411
1412 properties->independentResolveNone = VK_TRUE;
1413 properties->independentResolve = VK_TRUE;
1414 break;
1415 }
1416 default:
1417 break;
1418 }
1419 }
1420 }
1421
1422 static void radv_get_physical_device_queue_family_properties(
1423 struct radv_physical_device* pdevice,
1424 uint32_t* pCount,
1425 VkQueueFamilyProperties** pQueueFamilyProperties)
1426 {
1427 int num_queue_families = 1;
1428 int idx;
1429 if (pdevice->rad_info.num_compute_rings > 0 &&
1430 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1431 num_queue_families++;
1432
1433 if (pQueueFamilyProperties == NULL) {
1434 *pCount = num_queue_families;
1435 return;
1436 }
1437
1438 if (!*pCount)
1439 return;
1440
1441 idx = 0;
1442 if (*pCount >= 1) {
1443 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1444 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1445 VK_QUEUE_COMPUTE_BIT |
1446 VK_QUEUE_TRANSFER_BIT |
1447 VK_QUEUE_SPARSE_BINDING_BIT,
1448 .queueCount = 1,
1449 .timestampValidBits = 64,
1450 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1451 };
1452 idx++;
1453 }
1454
1455 if (pdevice->rad_info.num_compute_rings > 0 &&
1456 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1457 if (*pCount > idx) {
1458 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1459 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1460 VK_QUEUE_TRANSFER_BIT |
1461 VK_QUEUE_SPARSE_BINDING_BIT,
1462 .queueCount = pdevice->rad_info.num_compute_rings,
1463 .timestampValidBits = 64,
1464 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1465 };
1466 idx++;
1467 }
1468 }
1469 *pCount = idx;
1470 }
1471
1472 void radv_GetPhysicalDeviceQueueFamilyProperties(
1473 VkPhysicalDevice physicalDevice,
1474 uint32_t* pCount,
1475 VkQueueFamilyProperties* pQueueFamilyProperties)
1476 {
1477 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1478 if (!pQueueFamilyProperties) {
1479 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1480 return;
1481 }
1482 VkQueueFamilyProperties *properties[] = {
1483 pQueueFamilyProperties + 0,
1484 pQueueFamilyProperties + 1,
1485 pQueueFamilyProperties + 2,
1486 };
1487 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1488 assert(*pCount <= 3);
1489 }
1490
1491 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1492 VkPhysicalDevice physicalDevice,
1493 uint32_t* pCount,
1494 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1495 {
1496 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1497 if (!pQueueFamilyProperties) {
1498 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1499 return;
1500 }
1501 VkQueueFamilyProperties *properties[] = {
1502 &pQueueFamilyProperties[0].queueFamilyProperties,
1503 &pQueueFamilyProperties[1].queueFamilyProperties,
1504 &pQueueFamilyProperties[2].queueFamilyProperties,
1505 };
1506 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1507 assert(*pCount <= 3);
1508 }
1509
1510 void radv_GetPhysicalDeviceMemoryProperties(
1511 VkPhysicalDevice physicalDevice,
1512 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1513 {
1514 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1515
1516 *pMemoryProperties = physical_device->memory_properties;
1517 }
1518
1519 static void
1520 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1521 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1522 {
1523 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1524 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1525 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1526 uint64_t vram_size = radv_get_vram_size(device);
1527 uint64_t gtt_size = device->rad_info.gart_size;
1528 uint64_t heap_budget, heap_usage;
1529
1530 /* For all memory heaps, the computation of budget is as follow:
1531 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1532 *
1533 * The Vulkan spec 1.1.97 says that the budget should include any
1534 * currently allocated device memory.
1535 *
1536 * Note that the application heap usages are not really accurate (eg.
1537 * in presence of shared buffers).
1538 */
1539 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1540 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1541
1542 switch (device->mem_type_indices[i]) {
1543 case RADV_MEM_TYPE_VRAM:
1544 heap_usage = device->ws->query_value(device->ws,
1545 RADEON_ALLOCATED_VRAM);
1546
1547 heap_budget = vram_size -
1548 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1549 heap_usage;
1550
1551 memoryBudget->heapBudget[heap_index] = heap_budget;
1552 memoryBudget->heapUsage[heap_index] = heap_usage;
1553 break;
1554 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1555 heap_usage = device->ws->query_value(device->ws,
1556 RADEON_ALLOCATED_VRAM_VIS);
1557
1558 heap_budget = visible_vram_size -
1559 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1560 heap_usage;
1561
1562 memoryBudget->heapBudget[heap_index] = heap_budget;
1563 memoryBudget->heapUsage[heap_index] = heap_usage;
1564 break;
1565 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1566 heap_usage = device->ws->query_value(device->ws,
1567 RADEON_ALLOCATED_GTT);
1568
1569 heap_budget = gtt_size -
1570 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1571 heap_usage;
1572
1573 memoryBudget->heapBudget[heap_index] = heap_budget;
1574 memoryBudget->heapUsage[heap_index] = heap_usage;
1575 break;
1576 default:
1577 break;
1578 }
1579 }
1580
1581 /* The heapBudget and heapUsage values must be zero for array elements
1582 * greater than or equal to
1583 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1584 */
1585 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1586 memoryBudget->heapBudget[i] = 0;
1587 memoryBudget->heapUsage[i] = 0;
1588 }
1589 }
1590
1591 void radv_GetPhysicalDeviceMemoryProperties2(
1592 VkPhysicalDevice physicalDevice,
1593 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1594 {
1595 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1596 &pMemoryProperties->memoryProperties);
1597
1598 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1599 vk_find_struct(pMemoryProperties->pNext,
1600 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1601 if (memory_budget)
1602 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1603 }
1604
1605 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1606 VkDevice _device,
1607 VkExternalMemoryHandleTypeFlagBits handleType,
1608 const void *pHostPointer,
1609 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612
1613 switch (handleType)
1614 {
1615 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1616 const struct radv_physical_device *physical_device = device->physical_device;
1617 uint32_t memoryTypeBits = 0;
1618 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1619 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1620 memoryTypeBits = (1 << i);
1621 break;
1622 }
1623 }
1624 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1625 return VK_SUCCESS;
1626 }
1627 default:
1628 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1629 }
1630 }
1631
1632 static enum radeon_ctx_priority
1633 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1634 {
1635 /* Default to MEDIUM when a specific global priority isn't requested */
1636 if (!pObj)
1637 return RADEON_CTX_PRIORITY_MEDIUM;
1638
1639 switch(pObj->globalPriority) {
1640 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1641 return RADEON_CTX_PRIORITY_REALTIME;
1642 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1643 return RADEON_CTX_PRIORITY_HIGH;
1644 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1645 return RADEON_CTX_PRIORITY_MEDIUM;
1646 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1647 return RADEON_CTX_PRIORITY_LOW;
1648 default:
1649 unreachable("Illegal global priority value");
1650 return RADEON_CTX_PRIORITY_INVALID;
1651 }
1652 }
1653
1654 static int
1655 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1656 uint32_t queue_family_index, int idx,
1657 VkDeviceQueueCreateFlags flags,
1658 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1659 {
1660 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1661 queue->device = device;
1662 queue->queue_family_index = queue_family_index;
1663 queue->queue_idx = idx;
1664 queue->priority = radv_get_queue_global_priority(global_priority);
1665 queue->flags = flags;
1666
1667 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1668 if (!queue->hw_ctx)
1669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1670
1671 return VK_SUCCESS;
1672 }
1673
1674 static void
1675 radv_queue_finish(struct radv_queue *queue)
1676 {
1677 if (queue->hw_ctx)
1678 queue->device->ws->ctx_destroy(queue->hw_ctx);
1679
1680 if (queue->initial_full_flush_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1682 if (queue->initial_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1684 if (queue->continue_preamble_cs)
1685 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1686 if (queue->descriptor_bo)
1687 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1688 if (queue->scratch_bo)
1689 queue->device->ws->buffer_destroy(queue->scratch_bo);
1690 if (queue->esgs_ring_bo)
1691 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1692 if (queue->gsvs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1694 if (queue->tess_rings_bo)
1695 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1696 if (queue->compute_scratch_bo)
1697 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1698 }
1699
1700 static void
1701 radv_bo_list_init(struct radv_bo_list *bo_list)
1702 {
1703 pthread_mutex_init(&bo_list->mutex, NULL);
1704 bo_list->list.count = bo_list->capacity = 0;
1705 bo_list->list.bos = NULL;
1706 }
1707
1708 static void
1709 radv_bo_list_finish(struct radv_bo_list *bo_list)
1710 {
1711 free(bo_list->list.bos);
1712 pthread_mutex_destroy(&bo_list->mutex);
1713 }
1714
1715 static VkResult radv_bo_list_add(struct radv_device *device,
1716 struct radeon_winsys_bo *bo)
1717 {
1718 struct radv_bo_list *bo_list = &device->bo_list;
1719
1720 if (bo->is_local)
1721 return VK_SUCCESS;
1722
1723 if (unlikely(!device->use_global_bo_list))
1724 return VK_SUCCESS;
1725
1726 pthread_mutex_lock(&bo_list->mutex);
1727 if (bo_list->list.count == bo_list->capacity) {
1728 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1729 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1730
1731 if (!data) {
1732 pthread_mutex_unlock(&bo_list->mutex);
1733 return VK_ERROR_OUT_OF_HOST_MEMORY;
1734 }
1735
1736 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1737 bo_list->capacity = capacity;
1738 }
1739
1740 bo_list->list.bos[bo_list->list.count++] = bo;
1741 pthread_mutex_unlock(&bo_list->mutex);
1742 return VK_SUCCESS;
1743 }
1744
1745 static void radv_bo_list_remove(struct radv_device *device,
1746 struct radeon_winsys_bo *bo)
1747 {
1748 struct radv_bo_list *bo_list = &device->bo_list;
1749
1750 if (bo->is_local)
1751 return;
1752
1753 if (unlikely(!device->use_global_bo_list))
1754 return;
1755
1756 pthread_mutex_lock(&bo_list->mutex);
1757 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1758 if (bo_list->list.bos[i] == bo) {
1759 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1760 --bo_list->list.count;
1761 break;
1762 }
1763 }
1764 pthread_mutex_unlock(&bo_list->mutex);
1765 }
1766
1767 static void
1768 radv_device_init_gs_info(struct radv_device *device)
1769 {
1770 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1771 device->physical_device->rad_info.family);
1772 }
1773
1774 static int radv_get_device_extension_index(const char *name)
1775 {
1776 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1777 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1778 return i;
1779 }
1780 return -1;
1781 }
1782
1783 static int
1784 radv_get_int_debug_option(const char *name, int default_value)
1785 {
1786 const char *str;
1787 int result;
1788
1789 str = getenv(name);
1790 if (!str) {
1791 result = default_value;
1792 } else {
1793 char *endptr;
1794
1795 result = strtol(str, &endptr, 0);
1796 if (str == endptr) {
1797 /* No digits founs. */
1798 result = default_value;
1799 }
1800 }
1801
1802 return result;
1803 }
1804
1805 VkResult radv_CreateDevice(
1806 VkPhysicalDevice physicalDevice,
1807 const VkDeviceCreateInfo* pCreateInfo,
1808 const VkAllocationCallbacks* pAllocator,
1809 VkDevice* pDevice)
1810 {
1811 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1812 VkResult result;
1813 struct radv_device *device;
1814
1815 bool keep_shader_info = false;
1816
1817 /* Check enabled features */
1818 if (pCreateInfo->pEnabledFeatures) {
1819 VkPhysicalDeviceFeatures supported_features;
1820 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1821 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1822 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1823 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1824 for (uint32_t i = 0; i < num_features; i++) {
1825 if (enabled_feature[i] && !supported_feature[i])
1826 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1827 }
1828 }
1829
1830 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1831 sizeof(*device), 8,
1832 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1833 if (!device)
1834 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1835
1836 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1837 device->instance = physical_device->instance;
1838 device->physical_device = physical_device;
1839
1840 device->ws = physical_device->ws;
1841 if (pAllocator)
1842 device->alloc = *pAllocator;
1843 else
1844 device->alloc = physical_device->instance->alloc;
1845
1846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1847 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1848 int index = radv_get_device_extension_index(ext_name);
1849 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1850 vk_free(&device->alloc, device);
1851 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1852 }
1853
1854 device->enabled_extensions.extensions[index] = true;
1855 }
1856
1857 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1858
1859 /* With update after bind we can't attach bo's to the command buffer
1860 * from the descriptor set anymore, so we have to use a global BO list.
1861 */
1862 device->use_global_bo_list =
1863 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1864 device->enabled_extensions.EXT_descriptor_indexing ||
1865 device->enabled_extensions.EXT_buffer_device_address;
1866
1867 mtx_init(&device->shader_slab_mutex, mtx_plain);
1868 list_inithead(&device->shader_slabs);
1869
1870 radv_bo_list_init(&device->bo_list);
1871
1872 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1873 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1874 uint32_t qfi = queue_create->queueFamilyIndex;
1875 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1876 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1877
1878 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1879
1880 device->queues[qfi] = vk_alloc(&device->alloc,
1881 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1882 if (!device->queues[qfi]) {
1883 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1884 goto fail;
1885 }
1886
1887 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1888
1889 device->queue_count[qfi] = queue_create->queueCount;
1890
1891 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1892 result = radv_queue_init(device, &device->queues[qfi][q],
1893 qfi, q, queue_create->flags,
1894 global_priority);
1895 if (result != VK_SUCCESS)
1896 goto fail;
1897 }
1898 }
1899
1900 /* TODO: Enable binning for GFX10. */
1901 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1902 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1903
1904 /* Disabled and not implemented for now. */
1905 device->dfsm_allowed = device->pbb_allowed &&
1906 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1907 device->physical_device->rad_info.family == CHIP_RAVEN2);
1908
1909 #ifdef ANDROID
1910 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1911 #endif
1912
1913 /* The maximum number of scratch waves. Scratch space isn't divided
1914 * evenly between CUs. The number is only a function of the number of CUs.
1915 * We can decrease the constant to decrease the scratch buffer size.
1916 *
1917 * sctx->scratch_waves must be >= the maximum possible size of
1918 * 1 threadgroup, so that the hw doesn't hang from being unable
1919 * to start any.
1920 *
1921 * The recommended value is 4 per CU at most. Higher numbers don't
1922 * bring much benefit, but they still occupy chip resources (think
1923 * async compute). I've seen ~2% performance difference between 4 and 32.
1924 */
1925 uint32_t max_threads_per_block = 2048;
1926 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1927 max_threads_per_block / 64);
1928
1929 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1930
1931 if (device->physical_device->rad_info.chip_class >= GFX7) {
1932 /* If the KMD allows it (there is a KMD hw register for it),
1933 * allow launching waves out-of-order.
1934 */
1935 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1936 }
1937
1938 radv_device_init_gs_info(device);
1939
1940 device->tess_offchip_block_dw_size =
1941 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1942 device->has_distributed_tess =
1943 device->physical_device->rad_info.chip_class >= GFX8 &&
1944 device->physical_device->rad_info.max_se >= 2;
1945
1946 if (getenv("RADV_TRACE_FILE")) {
1947 const char *filename = getenv("RADV_TRACE_FILE");
1948
1949 keep_shader_info = true;
1950
1951 if (!radv_init_trace(device))
1952 goto fail;
1953
1954 fprintf(stderr, "*****************************************************************************\n");
1955 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1956 fprintf(stderr, "*****************************************************************************\n");
1957
1958 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1959 radv_dump_enabled_options(device, stderr);
1960 }
1961
1962 device->keep_shader_info = keep_shader_info;
1963
1964 result = radv_device_init_meta(device);
1965 if (result != VK_SUCCESS)
1966 goto fail;
1967
1968 radv_device_init_msaa(device);
1969
1970 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1971 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1972 switch (family) {
1973 case RADV_QUEUE_GENERAL:
1974 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1975 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1976 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1977 break;
1978 case RADV_QUEUE_COMPUTE:
1979 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(device->empty_cs[family], 0);
1981 break;
1982 }
1983 device->ws->cs_finalize(device->empty_cs[family]);
1984 }
1985
1986 if (device->physical_device->rad_info.chip_class >= GFX7)
1987 cik_create_gfx_config(device);
1988
1989 VkPipelineCacheCreateInfo ci;
1990 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1991 ci.pNext = NULL;
1992 ci.flags = 0;
1993 ci.pInitialData = NULL;
1994 ci.initialDataSize = 0;
1995 VkPipelineCache pc;
1996 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1997 &ci, NULL, &pc);
1998 if (result != VK_SUCCESS)
1999 goto fail_meta;
2000
2001 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2002
2003 device->force_aniso =
2004 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2005 if (device->force_aniso >= 0) {
2006 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2007 1 << util_logbase2(device->force_aniso));
2008 }
2009
2010 *pDevice = radv_device_to_handle(device);
2011 return VK_SUCCESS;
2012
2013 fail_meta:
2014 radv_device_finish_meta(device);
2015 fail:
2016 radv_bo_list_finish(&device->bo_list);
2017
2018 if (device->trace_bo)
2019 device->ws->buffer_destroy(device->trace_bo);
2020
2021 if (device->gfx_init)
2022 device->ws->buffer_destroy(device->gfx_init);
2023
2024 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2025 for (unsigned q = 0; q < device->queue_count[i]; q++)
2026 radv_queue_finish(&device->queues[i][q]);
2027 if (device->queue_count[i])
2028 vk_free(&device->alloc, device->queues[i]);
2029 }
2030
2031 vk_free(&device->alloc, device);
2032 return result;
2033 }
2034
2035 void radv_DestroyDevice(
2036 VkDevice _device,
2037 const VkAllocationCallbacks* pAllocator)
2038 {
2039 RADV_FROM_HANDLE(radv_device, device, _device);
2040
2041 if (!device)
2042 return;
2043
2044 if (device->trace_bo)
2045 device->ws->buffer_destroy(device->trace_bo);
2046
2047 if (device->gfx_init)
2048 device->ws->buffer_destroy(device->gfx_init);
2049
2050 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2051 for (unsigned q = 0; q < device->queue_count[i]; q++)
2052 radv_queue_finish(&device->queues[i][q]);
2053 if (device->queue_count[i])
2054 vk_free(&device->alloc, device->queues[i]);
2055 if (device->empty_cs[i])
2056 device->ws->cs_destroy(device->empty_cs[i]);
2057 }
2058 radv_device_finish_meta(device);
2059
2060 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2061 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2062
2063 radv_destroy_shader_slabs(device);
2064
2065 radv_bo_list_finish(&device->bo_list);
2066 vk_free(&device->alloc, device);
2067 }
2068
2069 VkResult radv_EnumerateInstanceLayerProperties(
2070 uint32_t* pPropertyCount,
2071 VkLayerProperties* pProperties)
2072 {
2073 if (pProperties == NULL) {
2074 *pPropertyCount = 0;
2075 return VK_SUCCESS;
2076 }
2077
2078 /* None supported at this time */
2079 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2080 }
2081
2082 VkResult radv_EnumerateDeviceLayerProperties(
2083 VkPhysicalDevice physicalDevice,
2084 uint32_t* pPropertyCount,
2085 VkLayerProperties* pProperties)
2086 {
2087 if (pProperties == NULL) {
2088 *pPropertyCount = 0;
2089 return VK_SUCCESS;
2090 }
2091
2092 /* None supported at this time */
2093 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2094 }
2095
2096 void radv_GetDeviceQueue2(
2097 VkDevice _device,
2098 const VkDeviceQueueInfo2* pQueueInfo,
2099 VkQueue* pQueue)
2100 {
2101 RADV_FROM_HANDLE(radv_device, device, _device);
2102 struct radv_queue *queue;
2103
2104 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2105 if (pQueueInfo->flags != queue->flags) {
2106 /* From the Vulkan 1.1.70 spec:
2107 *
2108 * "The queue returned by vkGetDeviceQueue2 must have the same
2109 * flags value from this structure as that used at device
2110 * creation time in a VkDeviceQueueCreateInfo instance. If no
2111 * matching flags were specified at device creation time then
2112 * pQueue will return VK_NULL_HANDLE."
2113 */
2114 *pQueue = VK_NULL_HANDLE;
2115 return;
2116 }
2117
2118 *pQueue = radv_queue_to_handle(queue);
2119 }
2120
2121 void radv_GetDeviceQueue(
2122 VkDevice _device,
2123 uint32_t queueFamilyIndex,
2124 uint32_t queueIndex,
2125 VkQueue* pQueue)
2126 {
2127 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2128 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2129 .queueFamilyIndex = queueFamilyIndex,
2130 .queueIndex = queueIndex
2131 };
2132
2133 radv_GetDeviceQueue2(_device, &info, pQueue);
2134 }
2135
2136 static void
2137 fill_geom_tess_rings(struct radv_queue *queue,
2138 uint32_t *map,
2139 bool add_sample_positions,
2140 uint32_t esgs_ring_size,
2141 struct radeon_winsys_bo *esgs_ring_bo,
2142 uint32_t gsvs_ring_size,
2143 struct radeon_winsys_bo *gsvs_ring_bo,
2144 uint32_t tess_factor_ring_size,
2145 uint32_t tess_offchip_ring_offset,
2146 uint32_t tess_offchip_ring_size,
2147 struct radeon_winsys_bo *tess_rings_bo)
2148 {
2149 uint32_t *desc = &map[4];
2150
2151 if (esgs_ring_bo) {
2152 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2153
2154 /* stride 0, num records - size, add tid, swizzle, elsize4,
2155 index stride 64 */
2156 desc[0] = esgs_va;
2157 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2158 S_008F04_STRIDE(0) |
2159 S_008F04_SWIZZLE_ENABLE(true);
2160 desc[2] = esgs_ring_size;
2161 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2165 S_008F0C_ELEMENT_SIZE(1) |
2166 S_008F0C_INDEX_STRIDE(3) |
2167 S_008F0C_ADD_TID_ENABLE(true);
2168
2169 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2170 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2171 S_008F0C_OOB_SELECT(2) |
2172 S_008F0C_RESOURCE_LEVEL(1);
2173 } else {
2174 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2176 }
2177
2178 /* GS entry for ES->GS ring */
2179 /* stride 0, num records - size, elsize0,
2180 index stride 0 */
2181 desc[4] = esgs_va;
2182 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2183 S_008F04_STRIDE(0) |
2184 S_008F04_SWIZZLE_ENABLE(false);
2185 desc[6] = esgs_ring_size;
2186 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2187 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2188 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2189 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2190 S_008F0C_ELEMENT_SIZE(0) |
2191 S_008F0C_INDEX_STRIDE(0) |
2192 S_008F0C_ADD_TID_ENABLE(false);
2193
2194 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2195 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2196 S_008F0C_OOB_SELECT(2) |
2197 S_008F0C_RESOURCE_LEVEL(1);
2198 } else {
2199 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2201 }
2202 }
2203
2204 desc += 8;
2205
2206 if (gsvs_ring_bo) {
2207 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2208
2209 /* VS entry for GS->VS ring */
2210 /* stride 0, num records - size, elsize0,
2211 index stride 0 */
2212 desc[0] = gsvs_va;
2213 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2214 S_008F04_STRIDE(0) |
2215 S_008F04_SWIZZLE_ENABLE(false);
2216 desc[2] = gsvs_ring_size;
2217 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2218 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2219 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2220 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2221 S_008F0C_ELEMENT_SIZE(0) |
2222 S_008F0C_INDEX_STRIDE(0) |
2223 S_008F0C_ADD_TID_ENABLE(false);
2224
2225 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2226 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2227 S_008F0C_OOB_SELECT(2) |
2228 S_008F0C_RESOURCE_LEVEL(1);
2229 } else {
2230 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2232 }
2233
2234 /* stride gsvs_itemsize, num records 64
2235 elsize 4, index stride 16 */
2236 /* shader will patch stride and desc[2] */
2237 desc[4] = gsvs_va;
2238 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2239 S_008F04_STRIDE(0) |
2240 S_008F04_SWIZZLE_ENABLE(true);
2241 desc[6] = 0;
2242 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2246 S_008F0C_ELEMENT_SIZE(1) |
2247 S_008F0C_INDEX_STRIDE(1) |
2248 S_008F0C_ADD_TID_ENABLE(true);
2249
2250 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2251 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2254 } else {
2255 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2257 }
2258
2259 }
2260
2261 desc += 8;
2262
2263 if (tess_rings_bo) {
2264 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2265 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2266
2267 desc[0] = tess_va;
2268 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2269 S_008F04_STRIDE(0) |
2270 S_008F04_SWIZZLE_ENABLE(false);
2271 desc[2] = tess_factor_ring_size;
2272 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2273 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2274 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2275 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2276
2277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2278 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2279 S_008F0C_OOB_SELECT(3) |
2280 S_008F0C_RESOURCE_LEVEL(1);
2281 } else {
2282 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2284 }
2285
2286 desc[4] = tess_offchip_va;
2287 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2288 S_008F04_STRIDE(0) |
2289 S_008F04_SWIZZLE_ENABLE(false);
2290 desc[6] = tess_offchip_ring_size;
2291 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2292 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2293 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2294 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2295
2296 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2297 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2298 S_008F0C_OOB_SELECT(3) |
2299 S_008F0C_RESOURCE_LEVEL(1);
2300 } else {
2301 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2302 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2303 }
2304 }
2305
2306 desc += 8;
2307
2308 if (add_sample_positions) {
2309 /* add sample positions after all rings */
2310 memcpy(desc, queue->device->sample_locations_1x, 8);
2311 desc += 2;
2312 memcpy(desc, queue->device->sample_locations_2x, 16);
2313 desc += 4;
2314 memcpy(desc, queue->device->sample_locations_4x, 32);
2315 desc += 8;
2316 memcpy(desc, queue->device->sample_locations_8x, 64);
2317 }
2318 }
2319
2320 static unsigned
2321 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2322 {
2323 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2324 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2325 device->physical_device->rad_info.family != CHIP_STONEY;
2326 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2327 unsigned max_offchip_buffers;
2328 unsigned offchip_granularity;
2329 unsigned hs_offchip_param;
2330
2331 /*
2332 * Per RadeonSI:
2333 * This must be one less than the maximum number due to a hw limitation.
2334 * Various hardware bugs need thGFX7
2335 *
2336 * Per AMDVLK:
2337 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2338 * Gfx7 should limit max_offchip_buffers to 508
2339 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2340 *
2341 * Follow AMDVLK here.
2342 */
2343 if (device->physical_device->rad_info.chip_class >= GFX10) {
2344 max_offchip_buffers_per_se = 256;
2345 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2346 device->physical_device->rad_info.chip_class == GFX7 ||
2347 device->physical_device->rad_info.chip_class == GFX6)
2348 --max_offchip_buffers_per_se;
2349
2350 max_offchip_buffers = max_offchip_buffers_per_se *
2351 device->physical_device->rad_info.max_se;
2352
2353 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2354 * around by setting 4K granularity.
2355 */
2356 if (device->tess_offchip_block_dw_size == 4096) {
2357 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2358 offchip_granularity = V_03093C_X_4K_DWORDS;
2359 } else {
2360 assert(device->tess_offchip_block_dw_size == 8192);
2361 offchip_granularity = V_03093C_X_8K_DWORDS;
2362 }
2363
2364 switch (device->physical_device->rad_info.chip_class) {
2365 case GFX6:
2366 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2367 break;
2368 case GFX7:
2369 case GFX8:
2370 case GFX9:
2371 default:
2372 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2373 break;
2374 }
2375
2376 *max_offchip_buffers_p = max_offchip_buffers;
2377 if (device->physical_device->rad_info.chip_class >= GFX7) {
2378 if (device->physical_device->rad_info.chip_class >= GFX8)
2379 --max_offchip_buffers;
2380 hs_offchip_param =
2381 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2382 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2383 } else {
2384 hs_offchip_param =
2385 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2386 }
2387 return hs_offchip_param;
2388 }
2389
2390 static void
2391 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2392 struct radeon_winsys_bo *esgs_ring_bo,
2393 uint32_t esgs_ring_size,
2394 struct radeon_winsys_bo *gsvs_ring_bo,
2395 uint32_t gsvs_ring_size)
2396 {
2397 if (!esgs_ring_bo && !gsvs_ring_bo)
2398 return;
2399
2400 if (esgs_ring_bo)
2401 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2402
2403 if (gsvs_ring_bo)
2404 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2405
2406 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2407 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2408 radeon_emit(cs, esgs_ring_size >> 8);
2409 radeon_emit(cs, gsvs_ring_size >> 8);
2410 } else {
2411 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2412 radeon_emit(cs, esgs_ring_size >> 8);
2413 radeon_emit(cs, gsvs_ring_size >> 8);
2414 }
2415 }
2416
2417 static void
2418 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2419 unsigned hs_offchip_param, unsigned tf_ring_size,
2420 struct radeon_winsys_bo *tess_rings_bo)
2421 {
2422 uint64_t tf_va;
2423
2424 if (!tess_rings_bo)
2425 return;
2426
2427 tf_va = radv_buffer_get_va(tess_rings_bo);
2428
2429 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2430
2431 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2432 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2433 S_030938_SIZE(tf_ring_size / 4));
2434 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2435 tf_va >> 8);
2436
2437 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2438 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2439 S_030984_BASE_HI(tf_va >> 40));
2440 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2441 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2442 S_030944_BASE_HI(tf_va >> 40));
2443 }
2444 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2445 hs_offchip_param);
2446 } else {
2447 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2448 S_008988_SIZE(tf_ring_size / 4));
2449 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2450 tf_va >> 8);
2451 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2452 hs_offchip_param);
2453 }
2454 }
2455
2456 static void
2457 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2458 struct radeon_winsys_bo *compute_scratch_bo)
2459 {
2460 uint64_t scratch_va;
2461
2462 if (!compute_scratch_bo)
2463 return;
2464
2465 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2466
2467 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2468
2469 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2470 radeon_emit(cs, scratch_va);
2471 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2472 S_008F04_SWIZZLE_ENABLE(1));
2473 }
2474
2475 static void
2476 radv_emit_global_shader_pointers(struct radv_queue *queue,
2477 struct radeon_cmdbuf *cs,
2478 struct radeon_winsys_bo *descriptor_bo)
2479 {
2480 uint64_t va;
2481
2482 if (!descriptor_bo)
2483 return;
2484
2485 va = radv_buffer_get_va(descriptor_bo);
2486
2487 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2488
2489 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2490 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2491 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2492 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2493 R_00B430_SPI_SHADER_USER_DATA_HS_0};
2494
2495 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2496 radv_emit_shader_pointer(queue->device, cs, regs[i],
2497 va, true);
2498 }
2499 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2500 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2501 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2502 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2503 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2504
2505 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2506 radv_emit_shader_pointer(queue->device, cs, regs[i],
2507 va, true);
2508 }
2509 } else {
2510 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2511 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2512 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2513 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2514 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2515 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2516
2517 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2518 radv_emit_shader_pointer(queue->device, cs, regs[i],
2519 va, true);
2520 }
2521 }
2522 }
2523
2524 static void
2525 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2526 {
2527 struct radv_device *device = queue->device;
2528
2529 if (device->gfx_init) {
2530 uint64_t va = radv_buffer_get_va(device->gfx_init);
2531
2532 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2533 radeon_emit(cs, va);
2534 radeon_emit(cs, va >> 32);
2535 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2536
2537 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2538 } else {
2539 struct radv_physical_device *physical_device = device->physical_device;
2540 si_emit_graphics(physical_device, cs);
2541 }
2542 }
2543
2544 static void
2545 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2546 {
2547 struct radv_physical_device *physical_device = queue->device->physical_device;
2548 si_emit_compute(physical_device, cs);
2549 }
2550
2551 static VkResult
2552 radv_get_preamble_cs(struct radv_queue *queue,
2553 uint32_t scratch_size,
2554 uint32_t compute_scratch_size,
2555 uint32_t esgs_ring_size,
2556 uint32_t gsvs_ring_size,
2557 bool needs_tess_rings,
2558 bool needs_sample_positions,
2559 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2560 struct radeon_cmdbuf **initial_preamble_cs,
2561 struct radeon_cmdbuf **continue_preamble_cs)
2562 {
2563 struct radeon_winsys_bo *scratch_bo = NULL;
2564 struct radeon_winsys_bo *descriptor_bo = NULL;
2565 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2566 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2567 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2568 struct radeon_winsys_bo *tess_rings_bo = NULL;
2569 struct radeon_cmdbuf *dest_cs[3] = {0};
2570 bool add_tess_rings = false, add_sample_positions = false;
2571 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2572 unsigned max_offchip_buffers;
2573 unsigned hs_offchip_param = 0;
2574 unsigned tess_offchip_ring_offset;
2575 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2576 if (!queue->has_tess_rings) {
2577 if (needs_tess_rings)
2578 add_tess_rings = true;
2579 }
2580 if (!queue->has_sample_positions) {
2581 if (needs_sample_positions)
2582 add_sample_positions = true;
2583 }
2584 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2585 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2586 &max_offchip_buffers);
2587 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2588 tess_offchip_ring_size = max_offchip_buffers *
2589 queue->device->tess_offchip_block_dw_size * 4;
2590
2591 if (scratch_size <= queue->scratch_size &&
2592 compute_scratch_size <= queue->compute_scratch_size &&
2593 esgs_ring_size <= queue->esgs_ring_size &&
2594 gsvs_ring_size <= queue->gsvs_ring_size &&
2595 !add_tess_rings && !add_sample_positions &&
2596 queue->initial_preamble_cs) {
2597 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2598 *initial_preamble_cs = queue->initial_preamble_cs;
2599 *continue_preamble_cs = queue->continue_preamble_cs;
2600 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2601 *continue_preamble_cs = NULL;
2602 return VK_SUCCESS;
2603 }
2604
2605 if (scratch_size > queue->scratch_size) {
2606 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2607 scratch_size,
2608 4096,
2609 RADEON_DOMAIN_VRAM,
2610 ring_bo_flags,
2611 RADV_BO_PRIORITY_SCRATCH);
2612 if (!scratch_bo)
2613 goto fail;
2614 } else
2615 scratch_bo = queue->scratch_bo;
2616
2617 if (compute_scratch_size > queue->compute_scratch_size) {
2618 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2619 compute_scratch_size,
2620 4096,
2621 RADEON_DOMAIN_VRAM,
2622 ring_bo_flags,
2623 RADV_BO_PRIORITY_SCRATCH);
2624 if (!compute_scratch_bo)
2625 goto fail;
2626
2627 } else
2628 compute_scratch_bo = queue->compute_scratch_bo;
2629
2630 if (esgs_ring_size > queue->esgs_ring_size) {
2631 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2632 esgs_ring_size,
2633 4096,
2634 RADEON_DOMAIN_VRAM,
2635 ring_bo_flags,
2636 RADV_BO_PRIORITY_SCRATCH);
2637 if (!esgs_ring_bo)
2638 goto fail;
2639 } else {
2640 esgs_ring_bo = queue->esgs_ring_bo;
2641 esgs_ring_size = queue->esgs_ring_size;
2642 }
2643
2644 if (gsvs_ring_size > queue->gsvs_ring_size) {
2645 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2646 gsvs_ring_size,
2647 4096,
2648 RADEON_DOMAIN_VRAM,
2649 ring_bo_flags,
2650 RADV_BO_PRIORITY_SCRATCH);
2651 if (!gsvs_ring_bo)
2652 goto fail;
2653 } else {
2654 gsvs_ring_bo = queue->gsvs_ring_bo;
2655 gsvs_ring_size = queue->gsvs_ring_size;
2656 }
2657
2658 if (add_tess_rings) {
2659 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2660 tess_offchip_ring_offset + tess_offchip_ring_size,
2661 256,
2662 RADEON_DOMAIN_VRAM,
2663 ring_bo_flags,
2664 RADV_BO_PRIORITY_SCRATCH);
2665 if (!tess_rings_bo)
2666 goto fail;
2667 } else {
2668 tess_rings_bo = queue->tess_rings_bo;
2669 }
2670
2671 if (scratch_bo != queue->scratch_bo ||
2672 esgs_ring_bo != queue->esgs_ring_bo ||
2673 gsvs_ring_bo != queue->gsvs_ring_bo ||
2674 tess_rings_bo != queue->tess_rings_bo ||
2675 add_sample_positions) {
2676 uint32_t size = 0;
2677 if (gsvs_ring_bo || esgs_ring_bo ||
2678 tess_rings_bo || add_sample_positions) {
2679 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2680 if (add_sample_positions)
2681 size += 128; /* 64+32+16+8 = 120 bytes */
2682 }
2683 else if (scratch_bo)
2684 size = 8; /* 2 dword */
2685
2686 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2687 size,
2688 4096,
2689 RADEON_DOMAIN_VRAM,
2690 RADEON_FLAG_CPU_ACCESS |
2691 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2692 RADEON_FLAG_READ_ONLY,
2693 RADV_BO_PRIORITY_DESCRIPTOR);
2694 if (!descriptor_bo)
2695 goto fail;
2696 } else
2697 descriptor_bo = queue->descriptor_bo;
2698
2699 if (descriptor_bo != queue->descriptor_bo) {
2700 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2701
2702 if (scratch_bo) {
2703 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2704 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2705 S_008F04_SWIZZLE_ENABLE(1);
2706 map[0] = scratch_va;
2707 map[1] = rsrc1;
2708 }
2709
2710 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2711 fill_geom_tess_rings(queue, map, add_sample_positions,
2712 esgs_ring_size, esgs_ring_bo,
2713 gsvs_ring_size, gsvs_ring_bo,
2714 tess_factor_ring_size,
2715 tess_offchip_ring_offset,
2716 tess_offchip_ring_size,
2717 tess_rings_bo);
2718
2719 queue->device->ws->buffer_unmap(descriptor_bo);
2720 }
2721
2722 for(int i = 0; i < 3; ++i) {
2723 struct radeon_cmdbuf *cs = NULL;
2724 cs = queue->device->ws->cs_create(queue->device->ws,
2725 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2726 if (!cs)
2727 goto fail;
2728
2729 dest_cs[i] = cs;
2730
2731 if (scratch_bo)
2732 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2733
2734 /* Emit initial configuration. */
2735 switch (queue->queue_family_index) {
2736 case RADV_QUEUE_GENERAL:
2737 radv_init_graphics_state(cs, queue);
2738 break;
2739 case RADV_QUEUE_COMPUTE:
2740 radv_init_compute_state(cs, queue);
2741 break;
2742 case RADV_QUEUE_TRANSFER:
2743 break;
2744 }
2745
2746 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2747 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2748 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2749 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2750 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2751 }
2752
2753 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2754 gsvs_ring_bo, gsvs_ring_size);
2755 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2756 tess_factor_ring_size, tess_rings_bo);
2757 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2758 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2759
2760 if (i == 0) {
2761 si_cs_emit_cache_flush(cs,
2762 queue->device->physical_device->rad_info.chip_class,
2763 NULL, 0,
2764 queue->queue_family_index == RING_COMPUTE &&
2765 queue->device->physical_device->rad_info.chip_class >= GFX7,
2766 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2767 RADV_CMD_FLAG_INV_ICACHE |
2768 RADV_CMD_FLAG_INV_SCACHE |
2769 RADV_CMD_FLAG_INV_VCACHE |
2770 RADV_CMD_FLAG_INV_L2 |
2771 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2772 } else if (i == 1) {
2773 si_cs_emit_cache_flush(cs,
2774 queue->device->physical_device->rad_info.chip_class,
2775 NULL, 0,
2776 queue->queue_family_index == RING_COMPUTE &&
2777 queue->device->physical_device->rad_info.chip_class >= GFX7,
2778 RADV_CMD_FLAG_INV_ICACHE |
2779 RADV_CMD_FLAG_INV_SCACHE |
2780 RADV_CMD_FLAG_INV_VCACHE |
2781 RADV_CMD_FLAG_INV_L2 |
2782 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2783 }
2784
2785 if (!queue->device->ws->cs_finalize(cs))
2786 goto fail;
2787 }
2788
2789 if (queue->initial_full_flush_preamble_cs)
2790 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2791
2792 if (queue->initial_preamble_cs)
2793 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2794
2795 if (queue->continue_preamble_cs)
2796 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2797
2798 queue->initial_full_flush_preamble_cs = dest_cs[0];
2799 queue->initial_preamble_cs = dest_cs[1];
2800 queue->continue_preamble_cs = dest_cs[2];
2801
2802 if (scratch_bo != queue->scratch_bo) {
2803 if (queue->scratch_bo)
2804 queue->device->ws->buffer_destroy(queue->scratch_bo);
2805 queue->scratch_bo = scratch_bo;
2806 queue->scratch_size = scratch_size;
2807 }
2808
2809 if (compute_scratch_bo != queue->compute_scratch_bo) {
2810 if (queue->compute_scratch_bo)
2811 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2812 queue->compute_scratch_bo = compute_scratch_bo;
2813 queue->compute_scratch_size = compute_scratch_size;
2814 }
2815
2816 if (esgs_ring_bo != queue->esgs_ring_bo) {
2817 if (queue->esgs_ring_bo)
2818 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2819 queue->esgs_ring_bo = esgs_ring_bo;
2820 queue->esgs_ring_size = esgs_ring_size;
2821 }
2822
2823 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2824 if (queue->gsvs_ring_bo)
2825 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2826 queue->gsvs_ring_bo = gsvs_ring_bo;
2827 queue->gsvs_ring_size = gsvs_ring_size;
2828 }
2829
2830 if (tess_rings_bo != queue->tess_rings_bo) {
2831 queue->tess_rings_bo = tess_rings_bo;
2832 queue->has_tess_rings = true;
2833 }
2834
2835 if (descriptor_bo != queue->descriptor_bo) {
2836 if (queue->descriptor_bo)
2837 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2838
2839 queue->descriptor_bo = descriptor_bo;
2840 }
2841
2842 if (add_sample_positions)
2843 queue->has_sample_positions = true;
2844
2845 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2846 *initial_preamble_cs = queue->initial_preamble_cs;
2847 *continue_preamble_cs = queue->continue_preamble_cs;
2848 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2849 *continue_preamble_cs = NULL;
2850 return VK_SUCCESS;
2851 fail:
2852 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2853 if (dest_cs[i])
2854 queue->device->ws->cs_destroy(dest_cs[i]);
2855 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2856 queue->device->ws->buffer_destroy(descriptor_bo);
2857 if (scratch_bo && scratch_bo != queue->scratch_bo)
2858 queue->device->ws->buffer_destroy(scratch_bo);
2859 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2860 queue->device->ws->buffer_destroy(compute_scratch_bo);
2861 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2862 queue->device->ws->buffer_destroy(esgs_ring_bo);
2863 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2864 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2865 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2866 queue->device->ws->buffer_destroy(tess_rings_bo);
2867 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2868 }
2869
2870 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2871 struct radv_winsys_sem_counts *counts,
2872 int num_sems,
2873 const VkSemaphore *sems,
2874 VkFence _fence,
2875 bool reset_temp)
2876 {
2877 int syncobj_idx = 0, sem_idx = 0;
2878
2879 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2880 return VK_SUCCESS;
2881
2882 for (uint32_t i = 0; i < num_sems; i++) {
2883 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2884
2885 if (sem->temp_syncobj || sem->syncobj)
2886 counts->syncobj_count++;
2887 else
2888 counts->sem_count++;
2889 }
2890
2891 if (_fence != VK_NULL_HANDLE) {
2892 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2893 if (fence->temp_syncobj || fence->syncobj)
2894 counts->syncobj_count++;
2895 }
2896
2897 if (counts->syncobj_count) {
2898 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2899 if (!counts->syncobj)
2900 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2901 }
2902
2903 if (counts->sem_count) {
2904 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2905 if (!counts->sem) {
2906 free(counts->syncobj);
2907 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2908 }
2909 }
2910
2911 for (uint32_t i = 0; i < num_sems; i++) {
2912 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2913
2914 if (sem->temp_syncobj) {
2915 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2916 }
2917 else if (sem->syncobj)
2918 counts->syncobj[syncobj_idx++] = sem->syncobj;
2919 else {
2920 assert(sem->sem);
2921 counts->sem[sem_idx++] = sem->sem;
2922 }
2923 }
2924
2925 if (_fence != VK_NULL_HANDLE) {
2926 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2927 if (fence->temp_syncobj)
2928 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2929 else if (fence->syncobj)
2930 counts->syncobj[syncobj_idx++] = fence->syncobj;
2931 }
2932
2933 return VK_SUCCESS;
2934 }
2935
2936 static void
2937 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2938 {
2939 free(sem_info->wait.syncobj);
2940 free(sem_info->wait.sem);
2941 free(sem_info->signal.syncobj);
2942 free(sem_info->signal.sem);
2943 }
2944
2945
2946 static void radv_free_temp_syncobjs(struct radv_device *device,
2947 int num_sems,
2948 const VkSemaphore *sems)
2949 {
2950 for (uint32_t i = 0; i < num_sems; i++) {
2951 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2952
2953 if (sem->temp_syncobj) {
2954 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2955 sem->temp_syncobj = 0;
2956 }
2957 }
2958 }
2959
2960 static VkResult
2961 radv_alloc_sem_info(struct radv_instance *instance,
2962 struct radv_winsys_sem_info *sem_info,
2963 int num_wait_sems,
2964 const VkSemaphore *wait_sems,
2965 int num_signal_sems,
2966 const VkSemaphore *signal_sems,
2967 VkFence fence)
2968 {
2969 VkResult ret;
2970 memset(sem_info, 0, sizeof(*sem_info));
2971
2972 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2973 if (ret)
2974 return ret;
2975 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2976 if (ret)
2977 radv_free_sem_info(sem_info);
2978
2979 /* caller can override these */
2980 sem_info->cs_emit_wait = true;
2981 sem_info->cs_emit_signal = true;
2982 return ret;
2983 }
2984
2985 /* Signals fence as soon as all the work currently put on queue is done. */
2986 static VkResult radv_signal_fence(struct radv_queue *queue,
2987 struct radv_fence *fence)
2988 {
2989 int ret;
2990 VkResult result;
2991 struct radv_winsys_sem_info sem_info;
2992
2993 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2994 radv_fence_to_handle(fence));
2995 if (result != VK_SUCCESS)
2996 return result;
2997
2998 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2999 &queue->device->empty_cs[queue->queue_family_index],
3000 1, NULL, NULL, &sem_info, NULL,
3001 false, fence->fence);
3002 radv_free_sem_info(&sem_info);
3003
3004 if (ret)
3005 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3006
3007 return VK_SUCCESS;
3008 }
3009
3010 VkResult radv_QueueSubmit(
3011 VkQueue _queue,
3012 uint32_t submitCount,
3013 const VkSubmitInfo* pSubmits,
3014 VkFence _fence)
3015 {
3016 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3017 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3018 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3019 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3020 int ret;
3021 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3022 uint32_t scratch_size = 0;
3023 uint32_t compute_scratch_size = 0;
3024 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3025 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3026 VkResult result;
3027 bool fence_emitted = false;
3028 bool tess_rings_needed = false;
3029 bool sample_positions_needed = false;
3030
3031 /* Do this first so failing to allocate scratch buffers can't result in
3032 * partially executed submissions. */
3033 for (uint32_t i = 0; i < submitCount; i++) {
3034 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3036 pSubmits[i].pCommandBuffers[j]);
3037
3038 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3039 compute_scratch_size = MAX2(compute_scratch_size,
3040 cmd_buffer->compute_scratch_size_needed);
3041 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3042 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3043 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3044 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3045 }
3046 }
3047
3048 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3049 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3050 sample_positions_needed, &initial_flush_preamble_cs,
3051 &initial_preamble_cs, &continue_preamble_cs);
3052 if (result != VK_SUCCESS)
3053 return result;
3054
3055 for (uint32_t i = 0; i < submitCount; i++) {
3056 struct radeon_cmdbuf **cs_array;
3057 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3058 bool can_patch = true;
3059 uint32_t advance;
3060 struct radv_winsys_sem_info sem_info;
3061
3062 result = radv_alloc_sem_info(queue->device->instance,
3063 &sem_info,
3064 pSubmits[i].waitSemaphoreCount,
3065 pSubmits[i].pWaitSemaphores,
3066 pSubmits[i].signalSemaphoreCount,
3067 pSubmits[i].pSignalSemaphores,
3068 _fence);
3069 if (result != VK_SUCCESS)
3070 return result;
3071
3072 if (!pSubmits[i].commandBufferCount) {
3073 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3074 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3075 &queue->device->empty_cs[queue->queue_family_index],
3076 1, NULL, NULL,
3077 &sem_info, NULL,
3078 false, base_fence);
3079 if (ret) {
3080 radv_loge("failed to submit CS %d\n", i);
3081 abort();
3082 }
3083 fence_emitted = true;
3084 }
3085 radv_free_sem_info(&sem_info);
3086 continue;
3087 }
3088
3089 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3090 (pSubmits[i].commandBufferCount));
3091
3092 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3093 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3094 pSubmits[i].pCommandBuffers[j]);
3095 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3096
3097 cs_array[j] = cmd_buffer->cs;
3098 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3099 can_patch = false;
3100
3101 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3102 }
3103
3104 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3105 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3106 const struct radv_winsys_bo_list *bo_list = NULL;
3107
3108 advance = MIN2(max_cs_submission,
3109 pSubmits[i].commandBufferCount - j);
3110
3111 if (queue->device->trace_bo)
3112 *queue->device->trace_id_ptr = 0;
3113
3114 sem_info.cs_emit_wait = j == 0;
3115 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3116
3117 if (unlikely(queue->device->use_global_bo_list)) {
3118 pthread_mutex_lock(&queue->device->bo_list.mutex);
3119 bo_list = &queue->device->bo_list.list;
3120 }
3121
3122 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3123 advance, initial_preamble, continue_preamble_cs,
3124 &sem_info, bo_list,
3125 can_patch, base_fence);
3126
3127 if (unlikely(queue->device->use_global_bo_list))
3128 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3129
3130 if (ret) {
3131 radv_loge("failed to submit CS %d\n", i);
3132 abort();
3133 }
3134 fence_emitted = true;
3135 if (queue->device->trace_bo) {
3136 radv_check_gpu_hangs(queue, cs_array[j]);
3137 }
3138 }
3139
3140 radv_free_temp_syncobjs(queue->device,
3141 pSubmits[i].waitSemaphoreCount,
3142 pSubmits[i].pWaitSemaphores);
3143 radv_free_sem_info(&sem_info);
3144 free(cs_array);
3145 }
3146
3147 if (fence) {
3148 if (!fence_emitted) {
3149 result = radv_signal_fence(queue, fence);
3150 if (result != VK_SUCCESS)
3151 return result;
3152 }
3153 }
3154
3155 return VK_SUCCESS;
3156 }
3157
3158 VkResult radv_QueueWaitIdle(
3159 VkQueue _queue)
3160 {
3161 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3162
3163 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3164 radv_queue_family_to_ring(queue->queue_family_index),
3165 queue->queue_idx);
3166 return VK_SUCCESS;
3167 }
3168
3169 VkResult radv_DeviceWaitIdle(
3170 VkDevice _device)
3171 {
3172 RADV_FROM_HANDLE(radv_device, device, _device);
3173
3174 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3175 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3176 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3177 }
3178 }
3179 return VK_SUCCESS;
3180 }
3181
3182 VkResult radv_EnumerateInstanceExtensionProperties(
3183 const char* pLayerName,
3184 uint32_t* pPropertyCount,
3185 VkExtensionProperties* pProperties)
3186 {
3187 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3188
3189 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3190 if (radv_supported_instance_extensions.extensions[i]) {
3191 vk_outarray_append(&out, prop) {
3192 *prop = radv_instance_extensions[i];
3193 }
3194 }
3195 }
3196
3197 return vk_outarray_status(&out);
3198 }
3199
3200 VkResult radv_EnumerateDeviceExtensionProperties(
3201 VkPhysicalDevice physicalDevice,
3202 const char* pLayerName,
3203 uint32_t* pPropertyCount,
3204 VkExtensionProperties* pProperties)
3205 {
3206 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3207 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3208
3209 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3210 if (device->supported_extensions.extensions[i]) {
3211 vk_outarray_append(&out, prop) {
3212 *prop = radv_device_extensions[i];
3213 }
3214 }
3215 }
3216
3217 return vk_outarray_status(&out);
3218 }
3219
3220 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3221 VkInstance _instance,
3222 const char* pName)
3223 {
3224 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3225
3226 return radv_lookup_entrypoint_checked(pName,
3227 instance ? instance->apiVersion : 0,
3228 instance ? &instance->enabled_extensions : NULL,
3229 NULL);
3230 }
3231
3232 /* The loader wants us to expose a second GetInstanceProcAddr function
3233 * to work around certain LD_PRELOAD issues seen in apps.
3234 */
3235 PUBLIC
3236 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3237 VkInstance instance,
3238 const char* pName);
3239
3240 PUBLIC
3241 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3242 VkInstance instance,
3243 const char* pName)
3244 {
3245 return radv_GetInstanceProcAddr(instance, pName);
3246 }
3247
3248 PUBLIC
3249 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3250 VkInstance _instance,
3251 const char* pName);
3252
3253 PUBLIC
3254 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3255 VkInstance _instance,
3256 const char* pName)
3257 {
3258 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3259
3260 return radv_lookup_physical_device_entrypoint_checked(pName,
3261 instance ? instance->apiVersion : 0,
3262 instance ? &instance->enabled_extensions : NULL);
3263 }
3264
3265 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3266 VkDevice _device,
3267 const char* pName)
3268 {
3269 RADV_FROM_HANDLE(radv_device, device, _device);
3270
3271 return radv_lookup_entrypoint_checked(pName,
3272 device->instance->apiVersion,
3273 &device->instance->enabled_extensions,
3274 &device->enabled_extensions);
3275 }
3276
3277 bool radv_get_memory_fd(struct radv_device *device,
3278 struct radv_device_memory *memory,
3279 int *pFD)
3280 {
3281 struct radeon_bo_metadata metadata;
3282
3283 if (memory->image) {
3284 radv_init_metadata(device, memory->image, &metadata);
3285 device->ws->buffer_set_metadata(memory->bo, &metadata);
3286 }
3287
3288 return device->ws->buffer_get_fd(device->ws, memory->bo,
3289 pFD);
3290 }
3291
3292 static VkResult radv_alloc_memory(struct radv_device *device,
3293 const VkMemoryAllocateInfo* pAllocateInfo,
3294 const VkAllocationCallbacks* pAllocator,
3295 VkDeviceMemory* pMem)
3296 {
3297 struct radv_device_memory *mem;
3298 VkResult result;
3299 enum radeon_bo_domain domain;
3300 uint32_t flags = 0;
3301 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3302
3303 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3304
3305 if (pAllocateInfo->allocationSize == 0) {
3306 /* Apparently, this is allowed */
3307 *pMem = VK_NULL_HANDLE;
3308 return VK_SUCCESS;
3309 }
3310
3311 const VkImportMemoryFdInfoKHR *import_info =
3312 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3313 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3314 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3315 const VkExportMemoryAllocateInfo *export_info =
3316 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3317 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3318 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3319
3320 const struct wsi_memory_allocate_info *wsi_info =
3321 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3322
3323 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3324 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3325 if (mem == NULL)
3326 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3327
3328 if (wsi_info && wsi_info->implicit_sync)
3329 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3330
3331 if (dedicate_info) {
3332 mem->image = radv_image_from_handle(dedicate_info->image);
3333 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3334 } else {
3335 mem->image = NULL;
3336 mem->buffer = NULL;
3337 }
3338
3339 float priority_float = 0.5;
3340 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3341 vk_find_struct_const(pAllocateInfo->pNext,
3342 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3343 if (priority_ext)
3344 priority_float = priority_ext->priority;
3345
3346 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3347 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3348
3349 mem->user_ptr = NULL;
3350
3351 if (import_info) {
3352 assert(import_info->handleType ==
3353 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3354 import_info->handleType ==
3355 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3356 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3357 priority, NULL, NULL);
3358 if (!mem->bo) {
3359 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3360 goto fail;
3361 } else {
3362 close(import_info->fd);
3363 }
3364 } else if (host_ptr_info) {
3365 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3366 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3367 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3368 pAllocateInfo->allocationSize,
3369 priority);
3370 if (!mem->bo) {
3371 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3372 goto fail;
3373 } else {
3374 mem->user_ptr = host_ptr_info->pHostPointer;
3375 }
3376 } else {
3377 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3378 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3379 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3380 domain = RADEON_DOMAIN_GTT;
3381 else
3382 domain = RADEON_DOMAIN_VRAM;
3383
3384 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3385 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3386 else
3387 flags |= RADEON_FLAG_CPU_ACCESS;
3388
3389 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3390 flags |= RADEON_FLAG_GTT_WC;
3391
3392 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3393 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3394 if (device->use_global_bo_list) {
3395 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3396 }
3397 }
3398
3399 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3400 domain, flags, priority);
3401
3402 if (!mem->bo) {
3403 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3404 goto fail;
3405 }
3406 mem->type_index = mem_type_index;
3407 }
3408
3409 result = radv_bo_list_add(device, mem->bo);
3410 if (result != VK_SUCCESS)
3411 goto fail_bo;
3412
3413 *pMem = radv_device_memory_to_handle(mem);
3414
3415 return VK_SUCCESS;
3416
3417 fail_bo:
3418 device->ws->buffer_destroy(mem->bo);
3419 fail:
3420 vk_free2(&device->alloc, pAllocator, mem);
3421
3422 return result;
3423 }
3424
3425 VkResult radv_AllocateMemory(
3426 VkDevice _device,
3427 const VkMemoryAllocateInfo* pAllocateInfo,
3428 const VkAllocationCallbacks* pAllocator,
3429 VkDeviceMemory* pMem)
3430 {
3431 RADV_FROM_HANDLE(radv_device, device, _device);
3432 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3433 }
3434
3435 void radv_FreeMemory(
3436 VkDevice _device,
3437 VkDeviceMemory _mem,
3438 const VkAllocationCallbacks* pAllocator)
3439 {
3440 RADV_FROM_HANDLE(radv_device, device, _device);
3441 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3442
3443 if (mem == NULL)
3444 return;
3445
3446 radv_bo_list_remove(device, mem->bo);
3447 device->ws->buffer_destroy(mem->bo);
3448 mem->bo = NULL;
3449
3450 vk_free2(&device->alloc, pAllocator, mem);
3451 }
3452
3453 VkResult radv_MapMemory(
3454 VkDevice _device,
3455 VkDeviceMemory _memory,
3456 VkDeviceSize offset,
3457 VkDeviceSize size,
3458 VkMemoryMapFlags flags,
3459 void** ppData)
3460 {
3461 RADV_FROM_HANDLE(radv_device, device, _device);
3462 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3463
3464 if (mem == NULL) {
3465 *ppData = NULL;
3466 return VK_SUCCESS;
3467 }
3468
3469 if (mem->user_ptr)
3470 *ppData = mem->user_ptr;
3471 else
3472 *ppData = device->ws->buffer_map(mem->bo);
3473
3474 if (*ppData) {
3475 *ppData += offset;
3476 return VK_SUCCESS;
3477 }
3478
3479 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3480 }
3481
3482 void radv_UnmapMemory(
3483 VkDevice _device,
3484 VkDeviceMemory _memory)
3485 {
3486 RADV_FROM_HANDLE(radv_device, device, _device);
3487 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3488
3489 if (mem == NULL)
3490 return;
3491
3492 if (mem->user_ptr == NULL)
3493 device->ws->buffer_unmap(mem->bo);
3494 }
3495
3496 VkResult radv_FlushMappedMemoryRanges(
3497 VkDevice _device,
3498 uint32_t memoryRangeCount,
3499 const VkMappedMemoryRange* pMemoryRanges)
3500 {
3501 return VK_SUCCESS;
3502 }
3503
3504 VkResult radv_InvalidateMappedMemoryRanges(
3505 VkDevice _device,
3506 uint32_t memoryRangeCount,
3507 const VkMappedMemoryRange* pMemoryRanges)
3508 {
3509 return VK_SUCCESS;
3510 }
3511
3512 void radv_GetBufferMemoryRequirements(
3513 VkDevice _device,
3514 VkBuffer _buffer,
3515 VkMemoryRequirements* pMemoryRequirements)
3516 {
3517 RADV_FROM_HANDLE(radv_device, device, _device);
3518 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3519
3520 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3521
3522 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3523 pMemoryRequirements->alignment = 4096;
3524 else
3525 pMemoryRequirements->alignment = 16;
3526
3527 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3528 }
3529
3530 void radv_GetBufferMemoryRequirements2(
3531 VkDevice device,
3532 const VkBufferMemoryRequirementsInfo2 *pInfo,
3533 VkMemoryRequirements2 *pMemoryRequirements)
3534 {
3535 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3536 &pMemoryRequirements->memoryRequirements);
3537 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3538 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3539 switch (ext->sType) {
3540 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3541 VkMemoryDedicatedRequirements *req =
3542 (VkMemoryDedicatedRequirements *) ext;
3543 req->requiresDedicatedAllocation = buffer->shareable;
3544 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3545 break;
3546 }
3547 default:
3548 break;
3549 }
3550 }
3551 }
3552
3553 void radv_GetImageMemoryRequirements(
3554 VkDevice _device,
3555 VkImage _image,
3556 VkMemoryRequirements* pMemoryRequirements)
3557 {
3558 RADV_FROM_HANDLE(radv_device, device, _device);
3559 RADV_FROM_HANDLE(radv_image, image, _image);
3560
3561 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3562
3563 pMemoryRequirements->size = image->size;
3564 pMemoryRequirements->alignment = image->alignment;
3565 }
3566
3567 void radv_GetImageMemoryRequirements2(
3568 VkDevice device,
3569 const VkImageMemoryRequirementsInfo2 *pInfo,
3570 VkMemoryRequirements2 *pMemoryRequirements)
3571 {
3572 radv_GetImageMemoryRequirements(device, pInfo->image,
3573 &pMemoryRequirements->memoryRequirements);
3574
3575 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3576
3577 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3578 switch (ext->sType) {
3579 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3580 VkMemoryDedicatedRequirements *req =
3581 (VkMemoryDedicatedRequirements *) ext;
3582 req->requiresDedicatedAllocation = image->shareable;
3583 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3584 break;
3585 }
3586 default:
3587 break;
3588 }
3589 }
3590 }
3591
3592 void radv_GetImageSparseMemoryRequirements(
3593 VkDevice device,
3594 VkImage image,
3595 uint32_t* pSparseMemoryRequirementCount,
3596 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3597 {
3598 stub();
3599 }
3600
3601 void radv_GetImageSparseMemoryRequirements2(
3602 VkDevice device,
3603 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3604 uint32_t* pSparseMemoryRequirementCount,
3605 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3606 {
3607 stub();
3608 }
3609
3610 void radv_GetDeviceMemoryCommitment(
3611 VkDevice device,
3612 VkDeviceMemory memory,
3613 VkDeviceSize* pCommittedMemoryInBytes)
3614 {
3615 *pCommittedMemoryInBytes = 0;
3616 }
3617
3618 VkResult radv_BindBufferMemory2(VkDevice device,
3619 uint32_t bindInfoCount,
3620 const VkBindBufferMemoryInfo *pBindInfos)
3621 {
3622 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3623 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3624 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3625
3626 if (mem) {
3627 buffer->bo = mem->bo;
3628 buffer->offset = pBindInfos[i].memoryOffset;
3629 } else {
3630 buffer->bo = NULL;
3631 }
3632 }
3633 return VK_SUCCESS;
3634 }
3635
3636 VkResult radv_BindBufferMemory(
3637 VkDevice device,
3638 VkBuffer buffer,
3639 VkDeviceMemory memory,
3640 VkDeviceSize memoryOffset)
3641 {
3642 const VkBindBufferMemoryInfo info = {
3643 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3644 .buffer = buffer,
3645 .memory = memory,
3646 .memoryOffset = memoryOffset
3647 };
3648
3649 return radv_BindBufferMemory2(device, 1, &info);
3650 }
3651
3652 VkResult radv_BindImageMemory2(VkDevice device,
3653 uint32_t bindInfoCount,
3654 const VkBindImageMemoryInfo *pBindInfos)
3655 {
3656 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3657 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3658 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3659
3660 if (mem) {
3661 image->bo = mem->bo;
3662 image->offset = pBindInfos[i].memoryOffset;
3663 } else {
3664 image->bo = NULL;
3665 image->offset = 0;
3666 }
3667 }
3668 return VK_SUCCESS;
3669 }
3670
3671
3672 VkResult radv_BindImageMemory(
3673 VkDevice device,
3674 VkImage image,
3675 VkDeviceMemory memory,
3676 VkDeviceSize memoryOffset)
3677 {
3678 const VkBindImageMemoryInfo info = {
3679 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3680 .image = image,
3681 .memory = memory,
3682 .memoryOffset = memoryOffset
3683 };
3684
3685 return radv_BindImageMemory2(device, 1, &info);
3686 }
3687
3688
3689 static void
3690 radv_sparse_buffer_bind_memory(struct radv_device *device,
3691 const VkSparseBufferMemoryBindInfo *bind)
3692 {
3693 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3694
3695 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3696 struct radv_device_memory *mem = NULL;
3697
3698 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3699 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3700
3701 device->ws->buffer_virtual_bind(buffer->bo,
3702 bind->pBinds[i].resourceOffset,
3703 bind->pBinds[i].size,
3704 mem ? mem->bo : NULL,
3705 bind->pBinds[i].memoryOffset);
3706 }
3707 }
3708
3709 static void
3710 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3711 const VkSparseImageOpaqueMemoryBindInfo *bind)
3712 {
3713 RADV_FROM_HANDLE(radv_image, image, bind->image);
3714
3715 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3716 struct radv_device_memory *mem = NULL;
3717
3718 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3719 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3720
3721 device->ws->buffer_virtual_bind(image->bo,
3722 bind->pBinds[i].resourceOffset,
3723 bind->pBinds[i].size,
3724 mem ? mem->bo : NULL,
3725 bind->pBinds[i].memoryOffset);
3726 }
3727 }
3728
3729 VkResult radv_QueueBindSparse(
3730 VkQueue _queue,
3731 uint32_t bindInfoCount,
3732 const VkBindSparseInfo* pBindInfo,
3733 VkFence _fence)
3734 {
3735 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3736 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3737 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3738 bool fence_emitted = false;
3739 VkResult result;
3740 int ret;
3741
3742 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3743 struct radv_winsys_sem_info sem_info;
3744 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3745 radv_sparse_buffer_bind_memory(queue->device,
3746 pBindInfo[i].pBufferBinds + j);
3747 }
3748
3749 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3750 radv_sparse_image_opaque_bind_memory(queue->device,
3751 pBindInfo[i].pImageOpaqueBinds + j);
3752 }
3753
3754 VkResult result;
3755 result = radv_alloc_sem_info(queue->device->instance,
3756 &sem_info,
3757 pBindInfo[i].waitSemaphoreCount,
3758 pBindInfo[i].pWaitSemaphores,
3759 pBindInfo[i].signalSemaphoreCount,
3760 pBindInfo[i].pSignalSemaphores,
3761 _fence);
3762 if (result != VK_SUCCESS)
3763 return result;
3764
3765 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3766 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3767 &queue->device->empty_cs[queue->queue_family_index],
3768 1, NULL, NULL,
3769 &sem_info, NULL,
3770 false, base_fence);
3771 if (ret) {
3772 radv_loge("failed to submit CS %d\n", i);
3773 abort();
3774 }
3775
3776 fence_emitted = true;
3777 }
3778
3779 radv_free_sem_info(&sem_info);
3780
3781 }
3782
3783 if (fence) {
3784 if (!fence_emitted) {
3785 result = radv_signal_fence(queue, fence);
3786 if (result != VK_SUCCESS)
3787 return result;
3788 }
3789 }
3790
3791 return VK_SUCCESS;
3792 }
3793
3794 VkResult radv_CreateFence(
3795 VkDevice _device,
3796 const VkFenceCreateInfo* pCreateInfo,
3797 const VkAllocationCallbacks* pAllocator,
3798 VkFence* pFence)
3799 {
3800 RADV_FROM_HANDLE(radv_device, device, _device);
3801 const VkExportFenceCreateInfo *export =
3802 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3803 VkExternalFenceHandleTypeFlags handleTypes =
3804 export ? export->handleTypes : 0;
3805
3806 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3807 sizeof(*fence), 8,
3808 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3809
3810 if (!fence)
3811 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3812
3813 fence->fence_wsi = NULL;
3814 fence->temp_syncobj = 0;
3815 if (device->always_use_syncobj || handleTypes) {
3816 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3817 if (ret) {
3818 vk_free2(&device->alloc, pAllocator, fence);
3819 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3820 }
3821 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3822 device->ws->signal_syncobj(device->ws, fence->syncobj);
3823 }
3824 fence->fence = NULL;
3825 } else {
3826 fence->fence = device->ws->create_fence();
3827 if (!fence->fence) {
3828 vk_free2(&device->alloc, pAllocator, fence);
3829 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3830 }
3831 fence->syncobj = 0;
3832 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3833 device->ws->signal_fence(fence->fence);
3834 }
3835
3836 *pFence = radv_fence_to_handle(fence);
3837
3838 return VK_SUCCESS;
3839 }
3840
3841 void radv_DestroyFence(
3842 VkDevice _device,
3843 VkFence _fence,
3844 const VkAllocationCallbacks* pAllocator)
3845 {
3846 RADV_FROM_HANDLE(radv_device, device, _device);
3847 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3848
3849 if (!fence)
3850 return;
3851
3852 if (fence->temp_syncobj)
3853 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3854 if (fence->syncobj)
3855 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3856 if (fence->fence)
3857 device->ws->destroy_fence(fence->fence);
3858 if (fence->fence_wsi)
3859 fence->fence_wsi->destroy(fence->fence_wsi);
3860 vk_free2(&device->alloc, pAllocator, fence);
3861 }
3862
3863
3864 uint64_t radv_get_current_time(void)
3865 {
3866 struct timespec tv;
3867 clock_gettime(CLOCK_MONOTONIC, &tv);
3868 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3869 }
3870
3871 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3872 {
3873 uint64_t current_time = radv_get_current_time();
3874
3875 timeout = MIN2(UINT64_MAX - current_time, timeout);
3876
3877 return current_time + timeout;
3878 }
3879
3880
3881 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3882 uint32_t fenceCount, const VkFence *pFences)
3883 {
3884 for (uint32_t i = 0; i < fenceCount; ++i) {
3885 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3886 if (fence->fence == NULL || fence->syncobj ||
3887 fence->temp_syncobj || fence->fence_wsi ||
3888 (!device->ws->is_fence_waitable(fence->fence)))
3889 return false;
3890 }
3891 return true;
3892 }
3893
3894 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3895 {
3896 for (uint32_t i = 0; i < fenceCount; ++i) {
3897 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3898 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3899 return false;
3900 }
3901 return true;
3902 }
3903
3904 VkResult radv_WaitForFences(
3905 VkDevice _device,
3906 uint32_t fenceCount,
3907 const VkFence* pFences,
3908 VkBool32 waitAll,
3909 uint64_t timeout)
3910 {
3911 RADV_FROM_HANDLE(radv_device, device, _device);
3912 timeout = radv_get_absolute_timeout(timeout);
3913
3914 if (device->always_use_syncobj &&
3915 radv_all_fences_syncobj(fenceCount, pFences))
3916 {
3917 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3918 if (!handles)
3919 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3920
3921 for (uint32_t i = 0; i < fenceCount; ++i) {
3922 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3923 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3924 }
3925
3926 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3927
3928 free(handles);
3929 return success ? VK_SUCCESS : VK_TIMEOUT;
3930 }
3931
3932 if (!waitAll && fenceCount > 1) {
3933 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3934 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3935 uint32_t wait_count = 0;
3936 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3937 if (!fences)
3938 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3939
3940 for (uint32_t i = 0; i < fenceCount; ++i) {
3941 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3942
3943 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3944 free(fences);
3945 return VK_SUCCESS;
3946 }
3947
3948 fences[wait_count++] = fence->fence;
3949 }
3950
3951 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3952 waitAll, timeout - radv_get_current_time());
3953
3954 free(fences);
3955 return success ? VK_SUCCESS : VK_TIMEOUT;
3956 }
3957
3958 while(radv_get_current_time() <= timeout) {
3959 for (uint32_t i = 0; i < fenceCount; ++i) {
3960 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3961 return VK_SUCCESS;
3962 }
3963 }
3964 return VK_TIMEOUT;
3965 }
3966
3967 for (uint32_t i = 0; i < fenceCount; ++i) {
3968 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3969 bool expired = false;
3970
3971 if (fence->temp_syncobj) {
3972 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3973 return VK_TIMEOUT;
3974 continue;
3975 }
3976
3977 if (fence->syncobj) {
3978 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3979 return VK_TIMEOUT;
3980 continue;
3981 }
3982
3983 if (fence->fence) {
3984 if (!device->ws->is_fence_waitable(fence->fence)) {
3985 while(!device->ws->is_fence_waitable(fence->fence) &&
3986 radv_get_current_time() <= timeout)
3987 /* Do nothing */;
3988 }
3989
3990 expired = device->ws->fence_wait(device->ws,
3991 fence->fence,
3992 true, timeout);
3993 if (!expired)
3994 return VK_TIMEOUT;
3995 }
3996
3997 if (fence->fence_wsi) {
3998 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3999 if (result != VK_SUCCESS)
4000 return result;
4001 }
4002 }
4003
4004 return VK_SUCCESS;
4005 }
4006
4007 VkResult radv_ResetFences(VkDevice _device,
4008 uint32_t fenceCount,
4009 const VkFence *pFences)
4010 {
4011 RADV_FROM_HANDLE(radv_device, device, _device);
4012
4013 for (unsigned i = 0; i < fenceCount; ++i) {
4014 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4015 if (fence->fence)
4016 device->ws->reset_fence(fence->fence);
4017
4018 /* Per spec, we first restore the permanent payload, and then reset, so
4019 * having a temp syncobj should not skip resetting the permanent syncobj. */
4020 if (fence->temp_syncobj) {
4021 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4022 fence->temp_syncobj = 0;
4023 }
4024
4025 if (fence->syncobj) {
4026 device->ws->reset_syncobj(device->ws, fence->syncobj);
4027 }
4028 }
4029
4030 return VK_SUCCESS;
4031 }
4032
4033 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4034 {
4035 RADV_FROM_HANDLE(radv_device, device, _device);
4036 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4037
4038 if (fence->temp_syncobj) {
4039 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4040 return success ? VK_SUCCESS : VK_NOT_READY;
4041 }
4042
4043 if (fence->syncobj) {
4044 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4045 return success ? VK_SUCCESS : VK_NOT_READY;
4046 }
4047
4048 if (fence->fence) {
4049 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4050 return VK_NOT_READY;
4051 }
4052 if (fence->fence_wsi) {
4053 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4054
4055 if (result != VK_SUCCESS) {
4056 if (result == VK_TIMEOUT)
4057 return VK_NOT_READY;
4058 return result;
4059 }
4060 }
4061 return VK_SUCCESS;
4062 }
4063
4064
4065 // Queue semaphore functions
4066
4067 VkResult radv_CreateSemaphore(
4068 VkDevice _device,
4069 const VkSemaphoreCreateInfo* pCreateInfo,
4070 const VkAllocationCallbacks* pAllocator,
4071 VkSemaphore* pSemaphore)
4072 {
4073 RADV_FROM_HANDLE(radv_device, device, _device);
4074 const VkExportSemaphoreCreateInfo *export =
4075 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4076 VkExternalSemaphoreHandleTypeFlags handleTypes =
4077 export ? export->handleTypes : 0;
4078
4079 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4080 sizeof(*sem), 8,
4081 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4082 if (!sem)
4083 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4084
4085 sem->temp_syncobj = 0;
4086 /* create a syncobject if we are going to export this semaphore */
4087 if (device->always_use_syncobj || handleTypes) {
4088 assert (device->physical_device->rad_info.has_syncobj);
4089 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4090 if (ret) {
4091 vk_free2(&device->alloc, pAllocator, sem);
4092 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4093 }
4094 sem->sem = NULL;
4095 } else {
4096 sem->sem = device->ws->create_sem(device->ws);
4097 if (!sem->sem) {
4098 vk_free2(&device->alloc, pAllocator, sem);
4099 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4100 }
4101 sem->syncobj = 0;
4102 }
4103
4104 *pSemaphore = radv_semaphore_to_handle(sem);
4105 return VK_SUCCESS;
4106 }
4107
4108 void radv_DestroySemaphore(
4109 VkDevice _device,
4110 VkSemaphore _semaphore,
4111 const VkAllocationCallbacks* pAllocator)
4112 {
4113 RADV_FROM_HANDLE(radv_device, device, _device);
4114 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4115 if (!_semaphore)
4116 return;
4117
4118 if (sem->syncobj)
4119 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4120 else
4121 device->ws->destroy_sem(sem->sem);
4122 vk_free2(&device->alloc, pAllocator, sem);
4123 }
4124
4125 VkResult radv_CreateEvent(
4126 VkDevice _device,
4127 const VkEventCreateInfo* pCreateInfo,
4128 const VkAllocationCallbacks* pAllocator,
4129 VkEvent* pEvent)
4130 {
4131 RADV_FROM_HANDLE(radv_device, device, _device);
4132 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4133 sizeof(*event), 8,
4134 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4135
4136 if (!event)
4137 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4138
4139 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4140 RADEON_DOMAIN_GTT,
4141 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4142 RADV_BO_PRIORITY_FENCE);
4143 if (!event->bo) {
4144 vk_free2(&device->alloc, pAllocator, event);
4145 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4146 }
4147
4148 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4149
4150 *pEvent = radv_event_to_handle(event);
4151
4152 return VK_SUCCESS;
4153 }
4154
4155 void radv_DestroyEvent(
4156 VkDevice _device,
4157 VkEvent _event,
4158 const VkAllocationCallbacks* pAllocator)
4159 {
4160 RADV_FROM_HANDLE(radv_device, device, _device);
4161 RADV_FROM_HANDLE(radv_event, event, _event);
4162
4163 if (!event)
4164 return;
4165 device->ws->buffer_destroy(event->bo);
4166 vk_free2(&device->alloc, pAllocator, event);
4167 }
4168
4169 VkResult radv_GetEventStatus(
4170 VkDevice _device,
4171 VkEvent _event)
4172 {
4173 RADV_FROM_HANDLE(radv_event, event, _event);
4174
4175 if (*event->map == 1)
4176 return VK_EVENT_SET;
4177 return VK_EVENT_RESET;
4178 }
4179
4180 VkResult radv_SetEvent(
4181 VkDevice _device,
4182 VkEvent _event)
4183 {
4184 RADV_FROM_HANDLE(radv_event, event, _event);
4185 *event->map = 1;
4186
4187 return VK_SUCCESS;
4188 }
4189
4190 VkResult radv_ResetEvent(
4191 VkDevice _device,
4192 VkEvent _event)
4193 {
4194 RADV_FROM_HANDLE(radv_event, event, _event);
4195 *event->map = 0;
4196
4197 return VK_SUCCESS;
4198 }
4199
4200 VkResult radv_CreateBuffer(
4201 VkDevice _device,
4202 const VkBufferCreateInfo* pCreateInfo,
4203 const VkAllocationCallbacks* pAllocator,
4204 VkBuffer* pBuffer)
4205 {
4206 RADV_FROM_HANDLE(radv_device, device, _device);
4207 struct radv_buffer *buffer;
4208
4209 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4210
4211 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4212 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4213 if (buffer == NULL)
4214 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4215
4216 buffer->size = pCreateInfo->size;
4217 buffer->usage = pCreateInfo->usage;
4218 buffer->bo = NULL;
4219 buffer->offset = 0;
4220 buffer->flags = pCreateInfo->flags;
4221
4222 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4223 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4224
4225 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4226 buffer->bo = device->ws->buffer_create(device->ws,
4227 align64(buffer->size, 4096),
4228 4096, 0, RADEON_FLAG_VIRTUAL,
4229 RADV_BO_PRIORITY_VIRTUAL);
4230 if (!buffer->bo) {
4231 vk_free2(&device->alloc, pAllocator, buffer);
4232 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4233 }
4234 }
4235
4236 *pBuffer = radv_buffer_to_handle(buffer);
4237
4238 return VK_SUCCESS;
4239 }
4240
4241 void radv_DestroyBuffer(
4242 VkDevice _device,
4243 VkBuffer _buffer,
4244 const VkAllocationCallbacks* pAllocator)
4245 {
4246 RADV_FROM_HANDLE(radv_device, device, _device);
4247 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4248
4249 if (!buffer)
4250 return;
4251
4252 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4253 device->ws->buffer_destroy(buffer->bo);
4254
4255 vk_free2(&device->alloc, pAllocator, buffer);
4256 }
4257
4258 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4259 VkDevice device,
4260 const VkBufferDeviceAddressInfoEXT* pInfo)
4261 {
4262 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4263 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4264 }
4265
4266
4267 static inline unsigned
4268 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4269 {
4270 if (stencil)
4271 return plane->surface.u.legacy.stencil_tiling_index[level];
4272 else
4273 return plane->surface.u.legacy.tiling_index[level];
4274 }
4275
4276 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4277 {
4278 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4279 }
4280
4281 static uint32_t
4282 radv_init_dcc_control_reg(struct radv_device *device,
4283 struct radv_image_view *iview)
4284 {
4285 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4286 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4287 unsigned max_compressed_block_size;
4288 unsigned independent_128b_blocks;
4289 unsigned independent_64b_blocks;
4290
4291 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4292 return 0;
4293
4294 if (!device->physical_device->rad_info.has_dedicated_vram) {
4295 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4296 * dGPU and 64 for APU because all of our APUs to date use
4297 * DIMMs which have a request granularity size of 64B while all
4298 * other chips have a 32B request size.
4299 */
4300 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4301 }
4302
4303 if (device->physical_device->rad_info.chip_class >= GFX10) {
4304 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4305 independent_64b_blocks = 0;
4306 independent_128b_blocks = 1;
4307 } else {
4308 independent_128b_blocks = 0;
4309
4310 if (iview->image->info.samples > 1) {
4311 if (iview->image->planes[0].surface.bpe == 1)
4312 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4313 else if (iview->image->planes[0].surface.bpe == 2)
4314 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4315 }
4316
4317 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4318 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4319 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4320 /* If this DCC image is potentially going to be used in texture
4321 * fetches, we need some special settings.
4322 */
4323 independent_64b_blocks = 1;
4324 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4325 } else {
4326 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4327 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4328 * big as possible for better compression state.
4329 */
4330 independent_64b_blocks = 0;
4331 max_compressed_block_size = max_uncompressed_block_size;
4332 }
4333 }
4334
4335 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4336 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4337 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4338 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4339 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4340 }
4341
4342 static void
4343 radv_initialise_color_surface(struct radv_device *device,
4344 struct radv_color_buffer_info *cb,
4345 struct radv_image_view *iview)
4346 {
4347 const struct vk_format_description *desc;
4348 unsigned ntype, format, swap, endian;
4349 unsigned blend_clamp = 0, blend_bypass = 0;
4350 uint64_t va;
4351 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4352 const struct radeon_surf *surf = &plane->surface;
4353
4354 desc = vk_format_description(iview->vk_format);
4355
4356 memset(cb, 0, sizeof(*cb));
4357
4358 /* Intensity is implemented as Red, so treat it that way. */
4359 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4360
4361 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4362
4363 cb->cb_color_base = va >> 8;
4364
4365 if (device->physical_device->rad_info.chip_class >= GFX9) {
4366 struct gfx9_surf_meta_flags meta;
4367 if (iview->image->dcc_offset)
4368 meta = surf->u.gfx9.dcc;
4369 else
4370 meta = surf->u.gfx9.cmask;
4371
4372 if (device->physical_device->rad_info.chip_class >= GFX10) {
4373 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4374 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4375 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4376 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4377 } else {
4378 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4379 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4380 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4381 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4382 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4383 }
4384
4385 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4386 cb->cb_color_base |= surf->tile_swizzle;
4387 } else {
4388 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4389 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4390
4391 cb->cb_color_base += level_info->offset >> 8;
4392 if (level_info->mode == RADEON_SURF_MODE_2D)
4393 cb->cb_color_base |= surf->tile_swizzle;
4394
4395 pitch_tile_max = level_info->nblk_x / 8 - 1;
4396 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4397 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4398
4399 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4400 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4401 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4402
4403 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4404
4405 if (radv_image_has_fmask(iview->image)) {
4406 if (device->physical_device->rad_info.chip_class >= GFX7)
4407 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4408 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4409 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4410 } else {
4411 /* This must be set for fast clear to work without FMASK. */
4412 if (device->physical_device->rad_info.chip_class >= GFX7)
4413 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4414 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4415 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4416 }
4417 }
4418
4419 /* CMASK variables */
4420 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4421 va += iview->image->cmask.offset;
4422 cb->cb_color_cmask = va >> 8;
4423
4424 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4425 va += iview->image->dcc_offset;
4426
4427 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4428 device->physical_device->rad_info.chip_class <= GFX8)
4429 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4430
4431 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4432 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4433
4434 cb->cb_dcc_base = va >> 8;
4435 cb->cb_dcc_base |= dcc_tile_swizzle;
4436
4437 /* GFX10 field has the same base shift as the GFX6 field. */
4438 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4439 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4440 S_028C6C_SLICE_MAX_GFX10(max_slice);
4441
4442 if (iview->image->info.samples > 1) {
4443 unsigned log_samples = util_logbase2(iview->image->info.samples);
4444
4445 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4446 S_028C74_NUM_FRAGMENTS(log_samples);
4447 }
4448
4449 if (radv_image_has_fmask(iview->image)) {
4450 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4451 cb->cb_color_fmask = va >> 8;
4452 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4453 } else {
4454 cb->cb_color_fmask = cb->cb_color_base;
4455 }
4456
4457 ntype = radv_translate_color_numformat(iview->vk_format,
4458 desc,
4459 vk_format_get_first_non_void_channel(iview->vk_format));
4460 format = radv_translate_colorformat(iview->vk_format);
4461 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4462 radv_finishme("Illegal color\n");
4463 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4464 endian = radv_colorformat_endian_swap(format);
4465
4466 /* blend clamp should be set for all NORM/SRGB types */
4467 if (ntype == V_028C70_NUMBER_UNORM ||
4468 ntype == V_028C70_NUMBER_SNORM ||
4469 ntype == V_028C70_NUMBER_SRGB)
4470 blend_clamp = 1;
4471
4472 /* set blend bypass according to docs if SINT/UINT or
4473 8/24 COLOR variants */
4474 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4475 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4476 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4477 blend_clamp = 0;
4478 blend_bypass = 1;
4479 }
4480 #if 0
4481 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4482 (format == V_028C70_COLOR_8 ||
4483 format == V_028C70_COLOR_8_8 ||
4484 format == V_028C70_COLOR_8_8_8_8))
4485 ->color_is_int8 = true;
4486 #endif
4487 cb->cb_color_info = S_028C70_FORMAT(format) |
4488 S_028C70_COMP_SWAP(swap) |
4489 S_028C70_BLEND_CLAMP(blend_clamp) |
4490 S_028C70_BLEND_BYPASS(blend_bypass) |
4491 S_028C70_SIMPLE_FLOAT(1) |
4492 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4493 ntype != V_028C70_NUMBER_SNORM &&
4494 ntype != V_028C70_NUMBER_SRGB &&
4495 format != V_028C70_COLOR_8_24 &&
4496 format != V_028C70_COLOR_24_8) |
4497 S_028C70_NUMBER_TYPE(ntype) |
4498 S_028C70_ENDIAN(endian);
4499 if (radv_image_has_fmask(iview->image)) {
4500 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4501 if (device->physical_device->rad_info.chip_class == GFX6) {
4502 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4503 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4504 }
4505
4506 if (radv_image_is_tc_compat_cmask(iview->image)) {
4507 /* Allow the texture block to read FMASK directly
4508 * without decompressing it. This bit must be cleared
4509 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4510 * otherwise the operation doesn't happen.
4511 */
4512 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4513
4514 /* Set CMASK into a tiling format that allows the
4515 * texture block to read it.
4516 */
4517 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4518 }
4519 }
4520
4521 if (radv_image_has_cmask(iview->image) &&
4522 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4523 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4524
4525 if (radv_dcc_enabled(iview->image, iview->base_mip))
4526 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4527
4528 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4529
4530 /* This must be set for fast clear to work without FMASK. */
4531 if (!radv_image_has_fmask(iview->image) &&
4532 device->physical_device->rad_info.chip_class == GFX6) {
4533 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4534 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4535 }
4536
4537 if (device->physical_device->rad_info.chip_class >= GFX9) {
4538 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4539
4540 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4541 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4542 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4543 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4544
4545 if (device->physical_device->rad_info.chip_class >= GFX10) {
4546 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4547
4548 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4549 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4550 S_028EE0_RESOURCE_LEVEL(1);
4551 } else {
4552 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4553 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4554 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4555 }
4556
4557 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4558 S_028C68_MIP0_HEIGHT(height - 1) |
4559 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4560 }
4561 }
4562
4563 static unsigned
4564 radv_calc_decompress_on_z_planes(struct radv_device *device,
4565 struct radv_image_view *iview)
4566 {
4567 unsigned max_zplanes = 0;
4568
4569 assert(radv_image_is_tc_compat_htile(iview->image));
4570
4571 if (device->physical_device->rad_info.chip_class >= GFX9) {
4572 /* Default value for 32-bit depth surfaces. */
4573 max_zplanes = 4;
4574
4575 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4576 iview->image->info.samples > 1)
4577 max_zplanes = 2;
4578
4579 max_zplanes = max_zplanes + 1;
4580 } else {
4581 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4582 /* Do not enable Z plane compression for 16-bit depth
4583 * surfaces because isn't supported on GFX8. Only
4584 * 32-bit depth surfaces are supported by the hardware.
4585 * This allows to maintain shader compatibility and to
4586 * reduce the number of depth decompressions.
4587 */
4588 max_zplanes = 1;
4589 } else {
4590 if (iview->image->info.samples <= 1)
4591 max_zplanes = 5;
4592 else if (iview->image->info.samples <= 4)
4593 max_zplanes = 3;
4594 else
4595 max_zplanes = 2;
4596 }
4597 }
4598
4599 return max_zplanes;
4600 }
4601
4602 static void
4603 radv_initialise_ds_surface(struct radv_device *device,
4604 struct radv_ds_buffer_info *ds,
4605 struct radv_image_view *iview)
4606 {
4607 unsigned level = iview->base_mip;
4608 unsigned format, stencil_format;
4609 uint64_t va, s_offs, z_offs;
4610 bool stencil_only = false;
4611 const struct radv_image_plane *plane = &iview->image->planes[0];
4612 const struct radeon_surf *surf = &plane->surface;
4613
4614 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4615
4616 memset(ds, 0, sizeof(*ds));
4617 switch (iview->image->vk_format) {
4618 case VK_FORMAT_D24_UNORM_S8_UINT:
4619 case VK_FORMAT_X8_D24_UNORM_PACK32:
4620 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4621 ds->offset_scale = 2.0f;
4622 break;
4623 case VK_FORMAT_D16_UNORM:
4624 case VK_FORMAT_D16_UNORM_S8_UINT:
4625 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4626 ds->offset_scale = 4.0f;
4627 break;
4628 case VK_FORMAT_D32_SFLOAT:
4629 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4630 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4631 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4632 ds->offset_scale = 1.0f;
4633 break;
4634 case VK_FORMAT_S8_UINT:
4635 stencil_only = true;
4636 break;
4637 default:
4638 break;
4639 }
4640
4641 format = radv_translate_dbformat(iview->image->vk_format);
4642 stencil_format = surf->has_stencil ?
4643 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4644
4645 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4646 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4647 S_028008_SLICE_MAX(max_slice);
4648 if (device->physical_device->rad_info.chip_class >= GFX10) {
4649 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4650 S_028008_SLICE_MAX_HI(max_slice >> 11);
4651 }
4652
4653 ds->db_htile_data_base = 0;
4654 ds->db_htile_surface = 0;
4655
4656 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4657 s_offs = z_offs = va;
4658
4659 if (device->physical_device->rad_info.chip_class >= GFX9) {
4660 assert(surf->u.gfx9.surf_offset == 0);
4661 s_offs += surf->u.gfx9.stencil_offset;
4662
4663 ds->db_z_info = S_028038_FORMAT(format) |
4664 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4665 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4666 S_028038_MAXMIP(iview->image->info.levels - 1) |
4667 S_028038_ZRANGE_PRECISION(1);
4668 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4669 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4670
4671 if (device->physical_device->rad_info.chip_class == GFX9) {
4672 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4673 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4674 }
4675
4676 ds->db_depth_view |= S_028008_MIPID(level);
4677 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4678 S_02801C_Y_MAX(iview->image->info.height - 1);
4679
4680 if (radv_htile_enabled(iview->image, level)) {
4681 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4682
4683 if (radv_image_is_tc_compat_htile(iview->image)) {
4684 unsigned max_zplanes =
4685 radv_calc_decompress_on_z_planes(device, iview);
4686
4687 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4688
4689 if (device->physical_device->rad_info.chip_class >= GFX10) {
4690 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4691 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4692 } else {
4693 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4694 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4695 }
4696 }
4697
4698 if (!surf->has_stencil)
4699 /* Use all of the htile_buffer for depth if there's no stencil. */
4700 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4701 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4702 iview->image->htile_offset;
4703 ds->db_htile_data_base = va >> 8;
4704 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4705 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4706
4707 if (device->physical_device->rad_info.chip_class == GFX9) {
4708 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4709 }
4710 }
4711 } else {
4712 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4713
4714 if (stencil_only)
4715 level_info = &surf->u.legacy.stencil_level[level];
4716
4717 z_offs += surf->u.legacy.level[level].offset;
4718 s_offs += surf->u.legacy.stencil_level[level].offset;
4719
4720 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4721 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4722 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4723
4724 if (iview->image->info.samples > 1)
4725 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4726
4727 if (device->physical_device->rad_info.chip_class >= GFX7) {
4728 struct radeon_info *info = &device->physical_device->rad_info;
4729 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4730 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4731 unsigned macro_index = surf->u.legacy.macro_tile_index;
4732 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4733 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4734 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4735
4736 if (stencil_only)
4737 tile_mode = stencil_tile_mode;
4738
4739 ds->db_depth_info |=
4740 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4741 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4742 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4743 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4744 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4745 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4746 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4747 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4748 } else {
4749 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4750 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4751 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4752 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4753 if (stencil_only)
4754 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4755 }
4756
4757 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4758 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4759 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4760
4761 if (radv_htile_enabled(iview->image, level)) {
4762 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4763
4764 if (!surf->has_stencil &&
4765 !radv_image_is_tc_compat_htile(iview->image))
4766 /* Use all of the htile_buffer for depth if there's no stencil. */
4767 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4768
4769 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4770 iview->image->htile_offset;
4771 ds->db_htile_data_base = va >> 8;
4772 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4773
4774 if (radv_image_is_tc_compat_htile(iview->image)) {
4775 unsigned max_zplanes =
4776 radv_calc_decompress_on_z_planes(device, iview);
4777
4778 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4779 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4780 }
4781 }
4782 }
4783
4784 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4785 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4786 }
4787
4788 VkResult radv_CreateFramebuffer(
4789 VkDevice _device,
4790 const VkFramebufferCreateInfo* pCreateInfo,
4791 const VkAllocationCallbacks* pAllocator,
4792 VkFramebuffer* pFramebuffer)
4793 {
4794 RADV_FROM_HANDLE(radv_device, device, _device);
4795 struct radv_framebuffer *framebuffer;
4796
4797 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4798
4799 size_t size = sizeof(*framebuffer) +
4800 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4801 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4802 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4803 if (framebuffer == NULL)
4804 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4805
4806 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4807 framebuffer->width = pCreateInfo->width;
4808 framebuffer->height = pCreateInfo->height;
4809 framebuffer->layers = pCreateInfo->layers;
4810 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4811 VkImageView _iview = pCreateInfo->pAttachments[i];
4812 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4813 framebuffer->attachments[i].attachment = iview;
4814 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4815 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4816 } else {
4817 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4818 }
4819 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4820 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4821 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4822 }
4823
4824 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4825 return VK_SUCCESS;
4826 }
4827
4828 void radv_DestroyFramebuffer(
4829 VkDevice _device,
4830 VkFramebuffer _fb,
4831 const VkAllocationCallbacks* pAllocator)
4832 {
4833 RADV_FROM_HANDLE(radv_device, device, _device);
4834 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4835
4836 if (!fb)
4837 return;
4838 vk_free2(&device->alloc, pAllocator, fb);
4839 }
4840
4841 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4842 {
4843 switch (address_mode) {
4844 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4845 return V_008F30_SQ_TEX_WRAP;
4846 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4847 return V_008F30_SQ_TEX_MIRROR;
4848 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4849 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4850 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4851 return V_008F30_SQ_TEX_CLAMP_BORDER;
4852 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4853 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4854 default:
4855 unreachable("illegal tex wrap mode");
4856 break;
4857 }
4858 }
4859
4860 static unsigned
4861 radv_tex_compare(VkCompareOp op)
4862 {
4863 switch (op) {
4864 case VK_COMPARE_OP_NEVER:
4865 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4866 case VK_COMPARE_OP_LESS:
4867 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4868 case VK_COMPARE_OP_EQUAL:
4869 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4870 case VK_COMPARE_OP_LESS_OR_EQUAL:
4871 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4872 case VK_COMPARE_OP_GREATER:
4873 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4874 case VK_COMPARE_OP_NOT_EQUAL:
4875 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4876 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4877 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4878 case VK_COMPARE_OP_ALWAYS:
4879 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4880 default:
4881 unreachable("illegal compare mode");
4882 break;
4883 }
4884 }
4885
4886 static unsigned
4887 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4888 {
4889 switch (filter) {
4890 case VK_FILTER_NEAREST:
4891 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4892 V_008F38_SQ_TEX_XY_FILTER_POINT);
4893 case VK_FILTER_LINEAR:
4894 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4895 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4896 case VK_FILTER_CUBIC_IMG:
4897 default:
4898 fprintf(stderr, "illegal texture filter");
4899 return 0;
4900 }
4901 }
4902
4903 static unsigned
4904 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4905 {
4906 switch (mode) {
4907 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4908 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4909 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4910 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4911 default:
4912 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4913 }
4914 }
4915
4916 static unsigned
4917 radv_tex_bordercolor(VkBorderColor bcolor)
4918 {
4919 switch (bcolor) {
4920 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4921 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4922 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4923 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4924 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4925 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4926 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4927 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4928 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4929 default:
4930 break;
4931 }
4932 return 0;
4933 }
4934
4935 static unsigned
4936 radv_tex_aniso_filter(unsigned filter)
4937 {
4938 if (filter < 2)
4939 return 0;
4940 if (filter < 4)
4941 return 1;
4942 if (filter < 8)
4943 return 2;
4944 if (filter < 16)
4945 return 3;
4946 return 4;
4947 }
4948
4949 static unsigned
4950 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4951 {
4952 switch (mode) {
4953 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4954 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4955 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4956 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4957 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4958 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4959 default:
4960 break;
4961 }
4962 return 0;
4963 }
4964
4965 static uint32_t
4966 radv_get_max_anisotropy(struct radv_device *device,
4967 const VkSamplerCreateInfo *pCreateInfo)
4968 {
4969 if (device->force_aniso >= 0)
4970 return device->force_aniso;
4971
4972 if (pCreateInfo->anisotropyEnable &&
4973 pCreateInfo->maxAnisotropy > 1.0f)
4974 return (uint32_t)pCreateInfo->maxAnisotropy;
4975
4976 return 0;
4977 }
4978
4979 static void
4980 radv_init_sampler(struct radv_device *device,
4981 struct radv_sampler *sampler,
4982 const VkSamplerCreateInfo *pCreateInfo)
4983 {
4984 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4985 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4986 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4987 device->physical_device->rad_info.chip_class == GFX9;
4988 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4989
4990 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4991 vk_find_struct_const(pCreateInfo->pNext,
4992 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4993 if (sampler_reduction)
4994 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4995
4996 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4997 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4998 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4999 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5000 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5001 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5002 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5003 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5004 S_008F30_DISABLE_CUBE_WRAP(0) |
5005 S_008F30_COMPAT_MODE(compat_mode) |
5006 S_008F30_FILTER_MODE(filter_mode));
5007 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5008 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5009 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5010 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5011 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5012 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5013 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5014 S_008F38_MIP_POINT_PRECLAMP(0));
5015 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5016 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5017
5018 if (device->physical_device->rad_info.chip_class >= GFX10) {
5019 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5020 } else {
5021 sampler->state[2] |=
5022 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5023 S_008F38_FILTER_PREC_FIX(1) |
5024 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5025 }
5026 }
5027
5028 VkResult radv_CreateSampler(
5029 VkDevice _device,
5030 const VkSamplerCreateInfo* pCreateInfo,
5031 const VkAllocationCallbacks* pAllocator,
5032 VkSampler* pSampler)
5033 {
5034 RADV_FROM_HANDLE(radv_device, device, _device);
5035 struct radv_sampler *sampler;
5036
5037 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5038 vk_find_struct_const(pCreateInfo->pNext,
5039 SAMPLER_YCBCR_CONVERSION_INFO);
5040
5041 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5042
5043 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5044 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5045 if (!sampler)
5046 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5047
5048 radv_init_sampler(device, sampler, pCreateInfo);
5049
5050 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5051 *pSampler = radv_sampler_to_handle(sampler);
5052
5053 return VK_SUCCESS;
5054 }
5055
5056 void radv_DestroySampler(
5057 VkDevice _device,
5058 VkSampler _sampler,
5059 const VkAllocationCallbacks* pAllocator)
5060 {
5061 RADV_FROM_HANDLE(radv_device, device, _device);
5062 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5063
5064 if (!sampler)
5065 return;
5066 vk_free2(&device->alloc, pAllocator, sampler);
5067 }
5068
5069 /* vk_icd.h does not declare this function, so we declare it here to
5070 * suppress Wmissing-prototypes.
5071 */
5072 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5073 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5074
5075 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5076 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5077 {
5078 /* For the full details on loader interface versioning, see
5079 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5080 * What follows is a condensed summary, to help you navigate the large and
5081 * confusing official doc.
5082 *
5083 * - Loader interface v0 is incompatible with later versions. We don't
5084 * support it.
5085 *
5086 * - In loader interface v1:
5087 * - The first ICD entrypoint called by the loader is
5088 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5089 * entrypoint.
5090 * - The ICD must statically expose no other Vulkan symbol unless it is
5091 * linked with -Bsymbolic.
5092 * - Each dispatchable Vulkan handle created by the ICD must be
5093 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5094 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5095 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5096 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5097 * such loader-managed surfaces.
5098 *
5099 * - Loader interface v2 differs from v1 in:
5100 * - The first ICD entrypoint called by the loader is
5101 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5102 * statically expose this entrypoint.
5103 *
5104 * - Loader interface v3 differs from v2 in:
5105 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5106 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5107 * because the loader no longer does so.
5108 */
5109 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5110 return VK_SUCCESS;
5111 }
5112
5113 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5114 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5115 int *pFD)
5116 {
5117 RADV_FROM_HANDLE(radv_device, device, _device);
5118 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5119
5120 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5121
5122 /* At the moment, we support only the below handle types. */
5123 assert(pGetFdInfo->handleType ==
5124 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5125 pGetFdInfo->handleType ==
5126 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5127
5128 bool ret = radv_get_memory_fd(device, memory, pFD);
5129 if (ret == false)
5130 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5131 return VK_SUCCESS;
5132 }
5133
5134 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5135 VkExternalMemoryHandleTypeFlagBits handleType,
5136 int fd,
5137 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5138 {
5139 RADV_FROM_HANDLE(radv_device, device, _device);
5140
5141 switch (handleType) {
5142 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5143 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5144 return VK_SUCCESS;
5145
5146 default:
5147 /* The valid usage section for this function says:
5148 *
5149 * "handleType must not be one of the handle types defined as
5150 * opaque."
5151 *
5152 * So opaque handle types fall into the default "unsupported" case.
5153 */
5154 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5155 }
5156 }
5157
5158 static VkResult radv_import_opaque_fd(struct radv_device *device,
5159 int fd,
5160 uint32_t *syncobj)
5161 {
5162 uint32_t syncobj_handle = 0;
5163 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5164 if (ret != 0)
5165 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5166
5167 if (*syncobj)
5168 device->ws->destroy_syncobj(device->ws, *syncobj);
5169
5170 *syncobj = syncobj_handle;
5171 close(fd);
5172
5173 return VK_SUCCESS;
5174 }
5175
5176 static VkResult radv_import_sync_fd(struct radv_device *device,
5177 int fd,
5178 uint32_t *syncobj)
5179 {
5180 /* If we create a syncobj we do it locally so that if we have an error, we don't
5181 * leave a syncobj in an undetermined state in the fence. */
5182 uint32_t syncobj_handle = *syncobj;
5183 if (!syncobj_handle) {
5184 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5185 if (ret) {
5186 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5187 }
5188 }
5189
5190 if (fd == -1) {
5191 device->ws->signal_syncobj(device->ws, syncobj_handle);
5192 } else {
5193 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5194 if (ret != 0)
5195 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5196 }
5197
5198 *syncobj = syncobj_handle;
5199 if (fd != -1)
5200 close(fd);
5201
5202 return VK_SUCCESS;
5203 }
5204
5205 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5206 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5207 {
5208 RADV_FROM_HANDLE(radv_device, device, _device);
5209 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5210 uint32_t *syncobj_dst = NULL;
5211
5212 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5213 syncobj_dst = &sem->temp_syncobj;
5214 } else {
5215 syncobj_dst = &sem->syncobj;
5216 }
5217
5218 switch(pImportSemaphoreFdInfo->handleType) {
5219 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5220 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5221 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5222 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5223 default:
5224 unreachable("Unhandled semaphore handle type");
5225 }
5226 }
5227
5228 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5229 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5230 int *pFd)
5231 {
5232 RADV_FROM_HANDLE(radv_device, device, _device);
5233 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5234 int ret;
5235 uint32_t syncobj_handle;
5236
5237 if (sem->temp_syncobj)
5238 syncobj_handle = sem->temp_syncobj;
5239 else
5240 syncobj_handle = sem->syncobj;
5241
5242 switch(pGetFdInfo->handleType) {
5243 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5244 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5245 break;
5246 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5247 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5248 if (!ret) {
5249 if (sem->temp_syncobj) {
5250 close (sem->temp_syncobj);
5251 sem->temp_syncobj = 0;
5252 } else {
5253 device->ws->reset_syncobj(device->ws, syncobj_handle);
5254 }
5255 }
5256 break;
5257 default:
5258 unreachable("Unhandled semaphore handle type");
5259 }
5260
5261 if (ret)
5262 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5263 return VK_SUCCESS;
5264 }
5265
5266 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5267 VkPhysicalDevice physicalDevice,
5268 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5269 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5270 {
5271 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5272
5273 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5274 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5275 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5276 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5277 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5278 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5279 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5280 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5281 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5282 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5283 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5284 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5285 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5286 } else {
5287 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5288 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5289 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5290 }
5291 }
5292
5293 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5294 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5295 {
5296 RADV_FROM_HANDLE(radv_device, device, _device);
5297 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5298 uint32_t *syncobj_dst = NULL;
5299
5300
5301 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5302 syncobj_dst = &fence->temp_syncobj;
5303 } else {
5304 syncobj_dst = &fence->syncobj;
5305 }
5306
5307 switch(pImportFenceFdInfo->handleType) {
5308 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5309 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5310 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5311 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5312 default:
5313 unreachable("Unhandled fence handle type");
5314 }
5315 }
5316
5317 VkResult radv_GetFenceFdKHR(VkDevice _device,
5318 const VkFenceGetFdInfoKHR *pGetFdInfo,
5319 int *pFd)
5320 {
5321 RADV_FROM_HANDLE(radv_device, device, _device);
5322 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5323 int ret;
5324 uint32_t syncobj_handle;
5325
5326 if (fence->temp_syncobj)
5327 syncobj_handle = fence->temp_syncobj;
5328 else
5329 syncobj_handle = fence->syncobj;
5330
5331 switch(pGetFdInfo->handleType) {
5332 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5333 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5334 break;
5335 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5336 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5337 if (!ret) {
5338 if (fence->temp_syncobj) {
5339 close (fence->temp_syncobj);
5340 fence->temp_syncobj = 0;
5341 } else {
5342 device->ws->reset_syncobj(device->ws, syncobj_handle);
5343 }
5344 }
5345 break;
5346 default:
5347 unreachable("Unhandled fence handle type");
5348 }
5349
5350 if (ret)
5351 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5352 return VK_SUCCESS;
5353 }
5354
5355 void radv_GetPhysicalDeviceExternalFenceProperties(
5356 VkPhysicalDevice physicalDevice,
5357 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5358 VkExternalFenceProperties *pExternalFenceProperties)
5359 {
5360 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5361
5362 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5363 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5364 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5365 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5366 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5367 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5368 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5369 } else {
5370 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5371 pExternalFenceProperties->compatibleHandleTypes = 0;
5372 pExternalFenceProperties->externalFenceFeatures = 0;
5373 }
5374 }
5375
5376 VkResult
5377 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5378 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5379 const VkAllocationCallbacks* pAllocator,
5380 VkDebugReportCallbackEXT* pCallback)
5381 {
5382 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5383 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5384 pCreateInfo, pAllocator, &instance->alloc,
5385 pCallback);
5386 }
5387
5388 void
5389 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5390 VkDebugReportCallbackEXT _callback,
5391 const VkAllocationCallbacks* pAllocator)
5392 {
5393 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5394 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5395 _callback, pAllocator, &instance->alloc);
5396 }
5397
5398 void
5399 radv_DebugReportMessageEXT(VkInstance _instance,
5400 VkDebugReportFlagsEXT flags,
5401 VkDebugReportObjectTypeEXT objectType,
5402 uint64_t object,
5403 size_t location,
5404 int32_t messageCode,
5405 const char* pLayerPrefix,
5406 const char* pMessage)
5407 {
5408 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5409 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5410 object, location, messageCode, pLayerPrefix, pMessage);
5411 }
5412
5413 void
5414 radv_GetDeviceGroupPeerMemoryFeatures(
5415 VkDevice device,
5416 uint32_t heapIndex,
5417 uint32_t localDeviceIndex,
5418 uint32_t remoteDeviceIndex,
5419 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5420 {
5421 assert(localDeviceIndex == remoteDeviceIndex);
5422
5423 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5424 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5425 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5426 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5427 }
5428
5429 static const VkTimeDomainEXT radv_time_domains[] = {
5430 VK_TIME_DOMAIN_DEVICE_EXT,
5431 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5432 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5433 };
5434
5435 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5436 VkPhysicalDevice physicalDevice,
5437 uint32_t *pTimeDomainCount,
5438 VkTimeDomainEXT *pTimeDomains)
5439 {
5440 int d;
5441 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5442
5443 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5444 vk_outarray_append(&out, i) {
5445 *i = radv_time_domains[d];
5446 }
5447 }
5448
5449 return vk_outarray_status(&out);
5450 }
5451
5452 static uint64_t
5453 radv_clock_gettime(clockid_t clock_id)
5454 {
5455 struct timespec current;
5456 int ret;
5457
5458 ret = clock_gettime(clock_id, &current);
5459 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5460 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5461 if (ret < 0)
5462 return 0;
5463
5464 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5465 }
5466
5467 VkResult radv_GetCalibratedTimestampsEXT(
5468 VkDevice _device,
5469 uint32_t timestampCount,
5470 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5471 uint64_t *pTimestamps,
5472 uint64_t *pMaxDeviation)
5473 {
5474 RADV_FROM_HANDLE(radv_device, device, _device);
5475 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5476 int d;
5477 uint64_t begin, end;
5478 uint64_t max_clock_period = 0;
5479
5480 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5481
5482 for (d = 0; d < timestampCount; d++) {
5483 switch (pTimestampInfos[d].timeDomain) {
5484 case VK_TIME_DOMAIN_DEVICE_EXT:
5485 pTimestamps[d] = device->ws->query_value(device->ws,
5486 RADEON_TIMESTAMP);
5487 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5488 max_clock_period = MAX2(max_clock_period, device_period);
5489 break;
5490 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5491 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5492 max_clock_period = MAX2(max_clock_period, 1);
5493 break;
5494
5495 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5496 pTimestamps[d] = begin;
5497 break;
5498 default:
5499 pTimestamps[d] = 0;
5500 break;
5501 }
5502 }
5503
5504 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5505
5506 /*
5507 * The maximum deviation is the sum of the interval over which we
5508 * perform the sampling and the maximum period of any sampled
5509 * clock. That's because the maximum skew between any two sampled
5510 * clock edges is when the sampled clock with the largest period is
5511 * sampled at the end of that period but right at the beginning of the
5512 * sampling interval and some other clock is sampled right at the
5513 * begining of its sampling period and right at the end of the
5514 * sampling interval. Let's assume the GPU has the longest clock
5515 * period and that the application is sampling GPU and monotonic:
5516 *
5517 * s e
5518 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5519 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5520 *
5521 * g
5522 * 0 1 2 3
5523 * GPU -----_____-----_____-----_____-----_____
5524 *
5525 * m
5526 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5527 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5528 *
5529 * Interval <----------------->
5530 * Deviation <-------------------------->
5531 *
5532 * s = read(raw) 2
5533 * g = read(GPU) 1
5534 * m = read(monotonic) 2
5535 * e = read(raw) b
5536 *
5537 * We round the sample interval up by one tick to cover sampling error
5538 * in the interval clock
5539 */
5540
5541 uint64_t sample_interval = end - begin + 1;
5542
5543 *pMaxDeviation = sample_interval + max_clock_period;
5544
5545 return VK_SUCCESS;
5546 }
5547
5548 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5549 VkPhysicalDevice physicalDevice,
5550 VkSampleCountFlagBits samples,
5551 VkMultisamplePropertiesEXT* pMultisampleProperties)
5552 {
5553 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5554 VK_SAMPLE_COUNT_4_BIT |
5555 VK_SAMPLE_COUNT_8_BIT)) {
5556 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5557 } else {
5558 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5559 }
5560 }