projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: move some image info into a separate struct.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 {
88 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
89 .specVersion = 1,
90 },
91 };
92
93 static const VkExtensionProperties common_device_extensions[] = {
94 {
95 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
100 .specVersion = 1,
101 },
102 {
103 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
116 .specVersion = 68,
117 },
118 {
119 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 {
123 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
124 .specVersion = 1,
125 },
126 {
127 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
128 .specVersion = 1,
129 },
130 };
131
132 static VkResult
133 radv_extensions_register(struct radv_instance *instance,
134 struct radv_extensions *extensions,
135 const VkExtensionProperties *new_ext,
136 uint32_t num_ext)
137 {
138 size_t new_size;
139 VkExtensionProperties *new_ptr;
140
141 assert(new_ext && num_ext > 0);
142
143 if (!new_ext)
144 return VK_ERROR_INITIALIZATION_FAILED;
145
146 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
147 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
148 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
149
150 /* Old array continues to be valid, update nothing */
151 if (!new_ptr)
152 return VK_ERROR_OUT_OF_HOST_MEMORY;
153
154 memcpy(&new_ptr[extensions->num_ext], new_ext,
155 num_ext * sizeof(VkExtensionProperties));
156 extensions->ext_array = new_ptr;
157 extensions->num_ext += num_ext;
158
159 return VK_SUCCESS;
160 }
161
162 static void
163 radv_extensions_finish(struct radv_instance *instance,
164 struct radv_extensions *extensions)
165 {
166 assert(extensions);
167
168 if (!extensions)
169 radv_loge("Attemted to free invalid extension struct\n");
170
171 if (extensions->ext_array)
172 vk_free(&instance->alloc, extensions->ext_array);
173 }
174
175 static bool
176 is_extension_enabled(const VkExtensionProperties *extensions,
177 size_t num_ext,
178 const char *name)
179 {
180 assert(extensions && name);
181
182 for (uint32_t i = 0; i < num_ext; i++) {
183 if (strcmp(name, extensions[i].extensionName) == 0)
184 return true;
185 }
186
187 return false;
188 }
189
190 static VkResult
191 radv_physical_device_init(struct radv_physical_device *device,
192 struct radv_instance *instance,
193 const char *path)
194 {
195 VkResult result;
196 drmVersionPtr version;
197 int fd;
198
199 fd = open(path, O_RDWR | O_CLOEXEC);
200 if (fd < 0)
201 return VK_ERROR_INCOMPATIBLE_DRIVER;
202
203 version = drmGetVersion(fd);
204 if (!version) {
205 close(fd);
206 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
207 "failed to get version %s: %m", path);
208 }
209
210 if (strcmp(version->name, "amdgpu")) {
211 drmFreeVersion(version);
212 close(fd);
213 return VK_ERROR_INCOMPATIBLE_DRIVER;
214 }
215 drmFreeVersion(version);
216
217 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 device->instance = instance;
219 assert(strlen(path) < ARRAY_SIZE(device->path));
220 strncpy(device->path, path, ARRAY_SIZE(device->path));
221
222 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
223 if (!device->ws) {
224 result = VK_ERROR_INCOMPATIBLE_DRIVER;
225 goto fail;
226 }
227
228 device->local_fd = fd;
229 device->ws->query_info(device->ws, &device->rad_info);
230 result = radv_init_wsi(device);
231 if (result != VK_SUCCESS) {
232 device->ws->destroy(device->ws);
233 goto fail;
234 }
235
236 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
237 radv_finish_wsi(device);
238 device->ws->destroy(device->ws);
239 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
240 "cannot generate UUID");
241 goto fail;
242 }
243
244 result = radv_extensions_register(instance,
245 &device->extensions,
246 common_device_extensions,
247 ARRAY_SIZE(common_device_extensions));
248 if (result != VK_SUCCESS)
249 goto fail;
250
251 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 device->name = device->rad_info.name;
253
254 return VK_SUCCESS;
255
256 fail:
257 close(fd);
258 return result;
259 }
260
261 static void
262 radv_physical_device_finish(struct radv_physical_device *device)
263 {
264 radv_extensions_finish(device->instance, &device->extensions);
265 radv_finish_wsi(device);
266 device->ws->destroy(device->ws);
267 close(device->local_fd);
268 }
269
270
271 static void *
272 default_alloc_func(void *pUserData, size_t size, size_t align,
273 VkSystemAllocationScope allocationScope)
274 {
275 return malloc(size);
276 }
277
278 static void *
279 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
280 size_t align, VkSystemAllocationScope allocationScope)
281 {
282 return realloc(pOriginal, size);
283 }
284
285 static void
286 default_free_func(void *pUserData, void *pMemory)
287 {
288 free(pMemory);
289 }
290
291 static const VkAllocationCallbacks default_alloc = {
292 .pUserData = NULL,
293 .pfnAllocation = default_alloc_func,
294 .pfnReallocation = default_realloc_func,
295 .pfnFree = default_free_func,
296 };
297
298 static const struct debug_control radv_debug_options[] = {
299 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
300 {"nodcc", RADV_DEBUG_NO_DCC},
301 {"shaders", RADV_DEBUG_DUMP_SHADERS},
302 {"nocache", RADV_DEBUG_NO_CACHE},
303 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
304 {"nohiz", RADV_DEBUG_NO_HIZ},
305 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
306 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
307 {"allbos", RADV_DEBUG_ALL_BOS},
308 {"noibs", RADV_DEBUG_NO_IBS},
309 {NULL, 0}
310 };
311
312 VkResult radv_CreateInstance(
313 const VkInstanceCreateInfo* pCreateInfo,
314 const VkAllocationCallbacks* pAllocator,
315 VkInstance* pInstance)
316 {
317 struct radv_instance *instance;
318
319 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
320
321 uint32_t client_version;
322 if (pCreateInfo->pApplicationInfo &&
323 pCreateInfo->pApplicationInfo->apiVersion != 0) {
324 client_version = pCreateInfo->pApplicationInfo->apiVersion;
325 } else {
326 client_version = VK_MAKE_VERSION(1, 0, 0);
327 }
328
329 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
330 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
331 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
332 "Client requested version %d.%d.%d",
333 VK_VERSION_MAJOR(client_version),
334 VK_VERSION_MINOR(client_version),
335 VK_VERSION_PATCH(client_version));
336 }
337
338 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
339 if (!is_extension_enabled(instance_extensions,
340 ARRAY_SIZE(instance_extensions),
341 pCreateInfo->ppEnabledExtensionNames[i]))
342 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
343 }
344
345 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
346 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
347 if (!instance)
348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
349
350 memset(instance, 0, sizeof(*instance));
351
352 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
353
354 if (pAllocator)
355 instance->alloc = *pAllocator;
356 else
357 instance->alloc = default_alloc;
358
359 instance->apiVersion = client_version;
360 instance->physicalDeviceCount = -1;
361
362 _mesa_locale_init();
363
364 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
365
366 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
367 radv_debug_options);
368
369 *pInstance = radv_instance_to_handle(instance);
370
371 return VK_SUCCESS;
372 }
373
374 void radv_DestroyInstance(
375 VkInstance _instance,
376 const VkAllocationCallbacks* pAllocator)
377 {
378 RADV_FROM_HANDLE(radv_instance, instance, _instance);
379
380 if (!instance)
381 return;
382
383 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
384 radv_physical_device_finish(instance->physicalDevices + i);
385 }
386
387 VG(VALGRIND_DESTROY_MEMPOOL(instance));
388
389 _mesa_locale_fini();
390
391 vk_free(&instance->alloc, instance);
392 }
393
394 static VkResult
395 radv_enumerate_devices(struct radv_instance *instance)
396 {
397 /* TODO: Check for more devices ? */
398 drmDevicePtr devices[8];
399 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
400 int max_devices;
401
402 instance->physicalDeviceCount = 0;
403
404 max_devices = drmGetDevices2(0, devices, sizeof(devices));
405 if (max_devices < 1)
406 return VK_ERROR_INCOMPATIBLE_DRIVER;
407
408 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
409 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
410 devices[i]->bustype == DRM_BUS_PCI &&
411 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
412
413 result = radv_physical_device_init(instance->physicalDevices +
414 instance->physicalDeviceCount,
415 instance,
416 devices[i]->nodes[DRM_NODE_RENDER]);
417 if (result == VK_SUCCESS)
418 ++instance->physicalDeviceCount;
419 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
420 return result;
421 }
422 }
423 return result;
424 }
425
426 VkResult radv_EnumeratePhysicalDevices(
427 VkInstance _instance,
428 uint32_t* pPhysicalDeviceCount,
429 VkPhysicalDevice* pPhysicalDevices)
430 {
431 RADV_FROM_HANDLE(radv_instance, instance, _instance);
432 VkResult result;
433
434 if (instance->physicalDeviceCount < 0) {
435 result = radv_enumerate_devices(instance);
436 if (result != VK_SUCCESS &&
437 result != VK_ERROR_INCOMPATIBLE_DRIVER)
438 return result;
439 }
440
441 if (!pPhysicalDevices) {
442 *pPhysicalDeviceCount = instance->physicalDeviceCount;
443 } else {
444 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
445 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
446 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
447 }
448
449 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
450 : VK_SUCCESS;
451 }
452
453 void radv_GetPhysicalDeviceFeatures(
454 VkPhysicalDevice physicalDevice,
455 VkPhysicalDeviceFeatures* pFeatures)
456 {
457 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
458
459 memset(pFeatures, 0, sizeof(*pFeatures));
460
461 *pFeatures = (VkPhysicalDeviceFeatures) {
462 .robustBufferAccess = true,
463 .fullDrawIndexUint32 = true,
464 .imageCubeArray = true,
465 .independentBlend = true,
466 .geometryShader = true,
467 .tessellationShader = true,
468 .sampleRateShading = false,
469 .dualSrcBlend = true,
470 .logicOp = true,
471 .multiDrawIndirect = true,
472 .drawIndirectFirstInstance = true,
473 .depthClamp = true,
474 .depthBiasClamp = true,
475 .fillModeNonSolid = true,
476 .depthBounds = true,
477 .wideLines = true,
478 .largePoints = true,
479 .alphaToOne = true,
480 .multiViewport = true,
481 .samplerAnisotropy = true,
482 .textureCompressionETC2 = false,
483 .textureCompressionASTC_LDR = false,
484 .textureCompressionBC = true,
485 .occlusionQueryPrecise = true,
486 .pipelineStatisticsQuery = true,
487 .vertexPipelineStoresAndAtomics = true,
488 .fragmentStoresAndAtomics = true,
489 .shaderTessellationAndGeometryPointSize = true,
490 .shaderImageGatherExtended = true,
491 .shaderStorageImageExtendedFormats = true,
492 .shaderStorageImageMultisample = false,
493 .shaderUniformBufferArrayDynamicIndexing = true,
494 .shaderSampledImageArrayDynamicIndexing = true,
495 .shaderStorageBufferArrayDynamicIndexing = true,
496 .shaderStorageImageArrayDynamicIndexing = true,
497 .shaderStorageImageReadWithoutFormat = true,
498 .shaderStorageImageWriteWithoutFormat = true,
499 .shaderClipDistance = true,
500 .shaderCullDistance = true,
501 .shaderFloat64 = true,
502 .shaderInt64 = false,
503 .shaderInt16 = false,
504 .sparseBinding = true,
505 .variableMultisampleRate = true,
506 .inheritedQueries = true,
507 };
508 }
509
510 void radv_GetPhysicalDeviceFeatures2KHR(
511 VkPhysicalDevice physicalDevice,
512 VkPhysicalDeviceFeatures2KHR *pFeatures)
513 {
514 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
515 }
516
517 static uint32_t radv_get_driver_version()
518 {
519 const char *minor_string = strchr(VERSION, '.');
520 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
521 int major = atoi(VERSION);
522 int minor = minor_string ? atoi(minor_string + 1) : 0;
523 int patch = patch_string ? atoi(patch_string + 1) : 0;
524 if (strstr(VERSION, "devel")) {
525 if (patch == 0) {
526 patch = 99;
527 if (minor == 0) {
528 minor = 99;
529 --major;
530 } else
531 --minor;
532 } else
533 --patch;
534 }
535 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
536 return version;
537 }
538
539 void radv_GetPhysicalDeviceProperties(
540 VkPhysicalDevice physicalDevice,
541 VkPhysicalDeviceProperties* pProperties)
542 {
543 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
544 VkSampleCountFlags sample_counts = 0xf;
545
546 /* make sure that the entire descriptor set is addressable with a signed
547 * 32-bit int. So the sum of all limits scaled by descriptor size has to
548 * be at most 2 GiB. the combined image & samples object count as one of
549 * both. This limit is for the pipeline layout, not for the set layout, but
550 * there is no set limit, so we just set a pipeline limit. I don't think
551 * any app is going to hit this soon. */
552 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
553 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
554 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
555 32 /* sampler, largest when combined with image */ +
556 64 /* sampled image */ +
557 64 /* storage image */);
558
559 VkPhysicalDeviceLimits limits = {
560 .maxImageDimension1D = (1 << 14),
561 .maxImageDimension2D = (1 << 14),
562 .maxImageDimension3D = (1 << 11),
563 .maxImageDimensionCube = (1 << 14),
564 .maxImageArrayLayers = (1 << 11),
565 .maxTexelBufferElements = 128 * 1024 * 1024,
566 .maxUniformBufferRange = UINT32_MAX,
567 .maxStorageBufferRange = UINT32_MAX,
568 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
569 .maxMemoryAllocationCount = UINT32_MAX,
570 .maxSamplerAllocationCount = 64 * 1024,
571 .bufferImageGranularity = 64, /* A cache line */
572 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
573 .maxBoundDescriptorSets = MAX_SETS,
574 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
575 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
576 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
577 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
578 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
579 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
580 .maxPerStageResources = max_descriptor_set_size,
581 .maxDescriptorSetSamplers = max_descriptor_set_size,
582 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
583 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
584 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
585 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
586 .maxDescriptorSetSampledImages = max_descriptor_set_size,
587 .maxDescriptorSetStorageImages = max_descriptor_set_size,
588 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
589 .maxVertexInputAttributes = 32,
590 .maxVertexInputBindings = 32,
591 .maxVertexInputAttributeOffset = 2047,
592 .maxVertexInputBindingStride = 2048,
593 .maxVertexOutputComponents = 128,
594 .maxTessellationGenerationLevel = 64,
595 .maxTessellationPatchSize = 32,
596 .maxTessellationControlPerVertexInputComponents = 128,
597 .maxTessellationControlPerVertexOutputComponents = 128,
598 .maxTessellationControlPerPatchOutputComponents = 120,
599 .maxTessellationControlTotalOutputComponents = 4096,
600 .maxTessellationEvaluationInputComponents = 128,
601 .maxTessellationEvaluationOutputComponents = 128,
602 .maxGeometryShaderInvocations = 127,
603 .maxGeometryInputComponents = 64,
604 .maxGeometryOutputComponents = 128,
605 .maxGeometryOutputVertices = 256,
606 .maxGeometryTotalOutputComponents = 1024,
607 .maxFragmentInputComponents = 128,
608 .maxFragmentOutputAttachments = 8,
609 .maxFragmentDualSrcAttachments = 1,
610 .maxFragmentCombinedOutputResources = 8,
611 .maxComputeSharedMemorySize = 32768,
612 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
613 .maxComputeWorkGroupInvocations = 2048,
614 .maxComputeWorkGroupSize = {
615 2048,
616 2048,
617 2048
618 },
619 .subPixelPrecisionBits = 4 /* FIXME */,
620 .subTexelPrecisionBits = 4 /* FIXME */,
621 .mipmapPrecisionBits = 4 /* FIXME */,
622 .maxDrawIndexedIndexValue = UINT32_MAX,
623 .maxDrawIndirectCount = UINT32_MAX,
624 .maxSamplerLodBias = 16,
625 .maxSamplerAnisotropy = 16,
626 .maxViewports = MAX_VIEWPORTS,
627 .maxViewportDimensions = { (1 << 14), (1 << 14) },
628 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
629 .viewportSubPixelBits = 13, /* We take a float? */
630 .minMemoryMapAlignment = 4096, /* A page */
631 .minTexelBufferOffsetAlignment = 1,
632 .minUniformBufferOffsetAlignment = 4,
633 .minStorageBufferOffsetAlignment = 4,
634 .minTexelOffset = -32,
635 .maxTexelOffset = 31,
636 .minTexelGatherOffset = -32,
637 .maxTexelGatherOffset = 31,
638 .minInterpolationOffset = -2,
639 .maxInterpolationOffset = 2,
640 .subPixelInterpolationOffsetBits = 8,
641 .maxFramebufferWidth = (1 << 14),
642 .maxFramebufferHeight = (1 << 14),
643 .maxFramebufferLayers = (1 << 10),
644 .framebufferColorSampleCounts = sample_counts,
645 .framebufferDepthSampleCounts = sample_counts,
646 .framebufferStencilSampleCounts = sample_counts,
647 .framebufferNoAttachmentsSampleCounts = sample_counts,
648 .maxColorAttachments = MAX_RTS,
649 .sampledImageColorSampleCounts = sample_counts,
650 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
651 .sampledImageDepthSampleCounts = sample_counts,
652 .sampledImageStencilSampleCounts = sample_counts,
653 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
654 .maxSampleMaskWords = 1,
655 .timestampComputeAndGraphics = true,
656 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
657 .maxClipDistances = 8,
658 .maxCullDistances = 8,
659 .maxCombinedClipAndCullDistances = 8,
660 .discreteQueuePriorities = 1,
661 .pointSizeRange = { 0.125, 255.875 },
662 .lineWidthRange = { 0.0, 7.9921875 },
663 .pointSizeGranularity = (1.0 / 8.0),
664 .lineWidthGranularity = (1.0 / 128.0),
665 .strictLines = false, /* FINISHME */
666 .standardSampleLocations = true,
667 .optimalBufferCopyOffsetAlignment = 128,
668 .optimalBufferCopyRowPitchAlignment = 128,
669 .nonCoherentAtomSize = 64,
670 };
671
672 *pProperties = (VkPhysicalDeviceProperties) {
673 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
674 .driverVersion = radv_get_driver_version(),
675 .vendorID = 0x1002,
676 .deviceID = pdevice->rad_info.pci_id,
677 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
678 .limits = limits,
679 .sparseProperties = {0},
680 };
681
682 strcpy(pProperties->deviceName, pdevice->name);
683 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
684 }
685
686 void radv_GetPhysicalDeviceProperties2KHR(
687 VkPhysicalDevice physicalDevice,
688 VkPhysicalDeviceProperties2KHR *pProperties)
689 {
690 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
691
692 vk_foreach_struct(ext, pProperties->pNext) {
693 switch (ext->sType) {
694 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
695 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
696 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
697 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
698 break;
699 }
700 default:
701 break;
702 }
703 }
704 }
705
706 static void radv_get_physical_device_queue_family_properties(
707 struct radv_physical_device* pdevice,
708 uint32_t* pCount,
709 VkQueueFamilyProperties** pQueueFamilyProperties)
710 {
711 int num_queue_families = 1;
712 int idx;
713 if (pdevice->rad_info.compute_rings > 0 &&
714 pdevice->rad_info.chip_class >= CIK &&
715 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
716 num_queue_families++;
717
718 if (pQueueFamilyProperties == NULL) {
719 *pCount = num_queue_families;
720 return;
721 }
722
723 if (!*pCount)
724 return;
725
726 idx = 0;
727 if (*pCount >= 1) {
728 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
729 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
730 VK_QUEUE_COMPUTE_BIT |
731 VK_QUEUE_TRANSFER_BIT |
732 VK_QUEUE_SPARSE_BINDING_BIT,
733 .queueCount = 1,
734 .timestampValidBits = 64,
735 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
736 };
737 idx++;
738 }
739
740 if (pdevice->rad_info.compute_rings > 0 &&
741 pdevice->rad_info.chip_class >= CIK &&
742 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
743 if (*pCount > idx) {
744 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
745 .queueFlags = VK_QUEUE_COMPUTE_BIT |
746 VK_QUEUE_TRANSFER_BIT |
747 VK_QUEUE_SPARSE_BINDING_BIT,
748 .queueCount = pdevice->rad_info.compute_rings,
749 .timestampValidBits = 64,
750 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
751 };
752 idx++;
753 }
754 }
755 *pCount = idx;
756 }
757
758 void radv_GetPhysicalDeviceQueueFamilyProperties(
759 VkPhysicalDevice physicalDevice,
760 uint32_t* pCount,
761 VkQueueFamilyProperties* pQueueFamilyProperties)
762 {
763 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
764 if (!pQueueFamilyProperties) {
765 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
766 return;
767 }
768 VkQueueFamilyProperties *properties[] = {
769 pQueueFamilyProperties + 0,
770 pQueueFamilyProperties + 1,
771 pQueueFamilyProperties + 2,
772 };
773 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
774 assert(*pCount <= 3);
775 }
776
777 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
778 VkPhysicalDevice physicalDevice,
779 uint32_t* pCount,
780 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
781 {
782 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
783 if (!pQueueFamilyProperties) {
784 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
785 return;
786 }
787 VkQueueFamilyProperties *properties[] = {
788 &pQueueFamilyProperties[0].queueFamilyProperties,
789 &pQueueFamilyProperties[1].queueFamilyProperties,
790 &pQueueFamilyProperties[2].queueFamilyProperties,
791 };
792 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
793 assert(*pCount <= 3);
794 }
795
796 void radv_GetPhysicalDeviceMemoryProperties(
797 VkPhysicalDevice physicalDevice,
798 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
799 {
800 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
801
802 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
803
804 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
805 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
806 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
807 .heapIndex = RADV_MEM_HEAP_VRAM,
808 };
809 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
810 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
811 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
812 .heapIndex = RADV_MEM_HEAP_GTT,
813 };
814 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
815 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
816 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
817 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
818 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
819 };
820 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
821 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
822 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
823 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
824 .heapIndex = RADV_MEM_HEAP_GTT,
825 };
826
827 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
828
829 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
830 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
831 .size = physical_device->rad_info.vram_size -
832 physical_device->rad_info.visible_vram_size,
833 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
834 };
835 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
836 .size = physical_device->rad_info.visible_vram_size,
837 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
838 };
839 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
840 .size = physical_device->rad_info.gart_size,
841 .flags = 0,
842 };
843 }
844
845 void radv_GetPhysicalDeviceMemoryProperties2KHR(
846 VkPhysicalDevice physicalDevice,
847 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
848 {
849 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
850 &pMemoryProperties->memoryProperties);
851 }
852
853 static int
854 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
855 int queue_family_index, int idx)
856 {
857 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
858 queue->device = device;
859 queue->queue_family_index = queue_family_index;
860 queue->queue_idx = idx;
861
862 queue->hw_ctx = device->ws->ctx_create(device->ws);
863 if (!queue->hw_ctx)
864 return VK_ERROR_OUT_OF_HOST_MEMORY;
865
866 return VK_SUCCESS;
867 }
868
869 static void
870 radv_queue_finish(struct radv_queue *queue)
871 {
872 if (queue->hw_ctx)
873 queue->device->ws->ctx_destroy(queue->hw_ctx);
874
875 if (queue->initial_preamble_cs)
876 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
877 if (queue->continue_preamble_cs)
878 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
879 if (queue->descriptor_bo)
880 queue->device->ws->buffer_destroy(queue->descriptor_bo);
881 if (queue->scratch_bo)
882 queue->device->ws->buffer_destroy(queue->scratch_bo);
883 if (queue->esgs_ring_bo)
884 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
885 if (queue->gsvs_ring_bo)
886 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
887 if (queue->tess_factor_ring_bo)
888 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
889 if (queue->tess_offchip_ring_bo)
890 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
891 if (queue->compute_scratch_bo)
892 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
893 }
894
895 static void
896 radv_device_init_gs_info(struct radv_device *device)
897 {
898 switch (device->physical_device->rad_info.family) {
899 case CHIP_OLAND:
900 case CHIP_HAINAN:
901 case CHIP_KAVERI:
902 case CHIP_KABINI:
903 case CHIP_MULLINS:
904 case CHIP_ICELAND:
905 case CHIP_CARRIZO:
906 case CHIP_STONEY:
907 device->gs_table_depth = 16;
908 return;
909 case CHIP_TAHITI:
910 case CHIP_PITCAIRN:
911 case CHIP_VERDE:
912 case CHIP_BONAIRE:
913 case CHIP_HAWAII:
914 case CHIP_TONGA:
915 case CHIP_FIJI:
916 case CHIP_POLARIS10:
917 case CHIP_POLARIS11:
918 device->gs_table_depth = 32;
919 return;
920 default:
921 unreachable("unknown GPU");
922 }
923 }
924
925 VkResult radv_CreateDevice(
926 VkPhysicalDevice physicalDevice,
927 const VkDeviceCreateInfo* pCreateInfo,
928 const VkAllocationCallbacks* pAllocator,
929 VkDevice* pDevice)
930 {
931 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
932 VkResult result;
933 struct radv_device *device;
934
935 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
936 if (!is_extension_enabled(physical_device->extensions.ext_array,
937 physical_device->extensions.num_ext,
938 pCreateInfo->ppEnabledExtensionNames[i]))
939 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
940 }
941
942 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
943 sizeof(*device), 8,
944 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
945 if (!device)
946 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
947
948 memset(device, 0, sizeof(*device));
949
950 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
951 device->instance = physical_device->instance;
952 device->physical_device = physical_device;
953
954 device->debug_flags = device->instance->debug_flags;
955
956 device->ws = physical_device->ws;
957 if (pAllocator)
958 device->alloc = *pAllocator;
959 else
960 device->alloc = physical_device->instance->alloc;
961
962 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
963 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
964 uint32_t qfi = queue_create->queueFamilyIndex;
965
966 device->queues[qfi] = vk_alloc(&device->alloc,
967 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
968 if (!device->queues[qfi]) {
969 result = VK_ERROR_OUT_OF_HOST_MEMORY;
970 goto fail;
971 }
972
973 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
974
975 device->queue_count[qfi] = queue_create->queueCount;
976
977 for (unsigned q = 0; q < queue_create->queueCount; q++) {
978 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
979 if (result != VK_SUCCESS)
980 goto fail;
981 }
982 }
983
984 #if HAVE_LLVM < 0x0400
985 device->llvm_supports_spill = false;
986 #else
987 device->llvm_supports_spill = true;
988 #endif
989
990 /* The maximum number of scratch waves. Scratch space isn't divided
991 * evenly between CUs. The number is only a function of the number of CUs.
992 * We can decrease the constant to decrease the scratch buffer size.
993 *
994 * sctx->scratch_waves must be >= the maximum posible size of
995 * 1 threadgroup, so that the hw doesn't hang from being unable
996 * to start any.
997 *
998 * The recommended value is 4 per CU at most. Higher numbers don't
999 * bring much benefit, but they still occupy chip resources (think
1000 * async compute). I've seen ~2% performance difference between 4 and 32.
1001 */
1002 uint32_t max_threads_per_block = 2048;
1003 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1004 max_threads_per_block / 64);
1005
1006 radv_device_init_gs_info(device);
1007
1008 device->tess_offchip_block_dw_size =
1009 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1010 device->has_distributed_tess =
1011 device->physical_device->rad_info.chip_class >= VI &&
1012 device->physical_device->rad_info.max_se >= 2;
1013
1014 result = radv_device_init_meta(device);
1015 if (result != VK_SUCCESS)
1016 goto fail;
1017
1018 radv_device_init_msaa(device);
1019
1020 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1021 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1022 switch (family) {
1023 case RADV_QUEUE_GENERAL:
1024 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1025 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1026 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1027 break;
1028 case RADV_QUEUE_COMPUTE:
1029 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1030 radeon_emit(device->empty_cs[family], 0);
1031 break;
1032 }
1033 device->ws->cs_finalize(device->empty_cs[family]);
1034
1035 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1036 switch (family) {
1037 case RADV_QUEUE_GENERAL:
1038 case RADV_QUEUE_COMPUTE:
1039 si_cs_emit_cache_flush(device->flush_cs[family],
1040 device->physical_device->rad_info.chip_class,
1041 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1042 RADV_CMD_FLAG_INV_ICACHE |
1043 RADV_CMD_FLAG_INV_SMEM_L1 |
1044 RADV_CMD_FLAG_INV_VMEM_L1 |
1045 RADV_CMD_FLAG_INV_GLOBAL_L2);
1046 break;
1047 }
1048 device->ws->cs_finalize(device->flush_cs[family]);
1049 }
1050
1051 if (getenv("RADV_TRACE_FILE")) {
1052 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1053 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1054 if (!device->trace_bo)
1055 goto fail;
1056
1057 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1058 if (!device->trace_id_ptr)
1059 goto fail;
1060 }
1061
1062 if (device->physical_device->rad_info.chip_class >= CIK)
1063 cik_create_gfx_config(device);
1064
1065 VkPipelineCacheCreateInfo ci;
1066 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1067 ci.pNext = NULL;
1068 ci.flags = 0;
1069 ci.pInitialData = NULL;
1070 ci.initialDataSize = 0;
1071 VkPipelineCache pc;
1072 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1073 &ci, NULL, &pc);
1074 if (result != VK_SUCCESS)
1075 goto fail;
1076
1077 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1078
1079 *pDevice = radv_device_to_handle(device);
1080 return VK_SUCCESS;
1081
1082 fail:
1083 if (device->trace_bo)
1084 device->ws->buffer_destroy(device->trace_bo);
1085
1086 if (device->gfx_init)
1087 device->ws->buffer_destroy(device->gfx_init);
1088
1089 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1090 for (unsigned q = 0; q < device->queue_count[i]; q++)
1091 radv_queue_finish(&device->queues[i][q]);
1092 if (device->queue_count[i])
1093 vk_free(&device->alloc, device->queues[i]);
1094 }
1095
1096 vk_free(&device->alloc, device);
1097 return result;
1098 }
1099
1100 void radv_DestroyDevice(
1101 VkDevice _device,
1102 const VkAllocationCallbacks* pAllocator)
1103 {
1104 RADV_FROM_HANDLE(radv_device, device, _device);
1105
1106 if (!device)
1107 return;
1108
1109 if (device->trace_bo)
1110 device->ws->buffer_destroy(device->trace_bo);
1111
1112 if (device->gfx_init)
1113 device->ws->buffer_destroy(device->gfx_init);
1114
1115 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1116 for (unsigned q = 0; q < device->queue_count[i]; q++)
1117 radv_queue_finish(&device->queues[i][q]);
1118 if (device->queue_count[i])
1119 vk_free(&device->alloc, device->queues[i]);
1120 if (device->empty_cs[i])
1121 device->ws->cs_destroy(device->empty_cs[i]);
1122 if (device->flush_cs[i])
1123 device->ws->cs_destroy(device->flush_cs[i]);
1124 }
1125 radv_device_finish_meta(device);
1126
1127 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1128 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1129
1130 vk_free(&device->alloc, device);
1131 }
1132
1133 VkResult radv_EnumerateInstanceExtensionProperties(
1134 const char* pLayerName,
1135 uint32_t* pPropertyCount,
1136 VkExtensionProperties* pProperties)
1137 {
1138 if (pProperties == NULL) {
1139 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1140 return VK_SUCCESS;
1141 }
1142
1143 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1144 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1145
1146 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1147 return VK_INCOMPLETE;
1148
1149 return VK_SUCCESS;
1150 }
1151
1152 VkResult radv_EnumerateDeviceExtensionProperties(
1153 VkPhysicalDevice physicalDevice,
1154 const char* pLayerName,
1155 uint32_t* pPropertyCount,
1156 VkExtensionProperties* pProperties)
1157 {
1158 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1159
1160 if (pProperties == NULL) {
1161 *pPropertyCount = pdevice->extensions.num_ext;
1162 return VK_SUCCESS;
1163 }
1164
1165 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1166 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1167
1168 if (*pPropertyCount < pdevice->extensions.num_ext)
1169 return VK_INCOMPLETE;
1170
1171 return VK_SUCCESS;
1172 }
1173
1174 VkResult radv_EnumerateInstanceLayerProperties(
1175 uint32_t* pPropertyCount,
1176 VkLayerProperties* pProperties)
1177 {
1178 if (pProperties == NULL) {
1179 *pPropertyCount = 0;
1180 return VK_SUCCESS;
1181 }
1182
1183 /* None supported at this time */
1184 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1185 }
1186
1187 VkResult radv_EnumerateDeviceLayerProperties(
1188 VkPhysicalDevice physicalDevice,
1189 uint32_t* pPropertyCount,
1190 VkLayerProperties* pProperties)
1191 {
1192 if (pProperties == NULL) {
1193 *pPropertyCount = 0;
1194 return VK_SUCCESS;
1195 }
1196
1197 /* None supported at this time */
1198 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1199 }
1200
1201 void radv_GetDeviceQueue(
1202 VkDevice _device,
1203 uint32_t queueFamilyIndex,
1204 uint32_t queueIndex,
1205 VkQueue* pQueue)
1206 {
1207 RADV_FROM_HANDLE(radv_device, device, _device);
1208
1209 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1210 }
1211
1212 static void radv_dump_trace(struct radv_device *device,
1213 struct radeon_winsys_cs *cs)
1214 {
1215 const char *filename = getenv("RADV_TRACE_FILE");
1216 FILE *f = fopen(filename, "w");
1217 if (!f) {
1218 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1219 return;
1220 }
1221
1222 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1223 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1224 fclose(f);
1225 }
1226
1227 static void
1228 fill_geom_tess_rings(struct radv_queue *queue,
1229 uint32_t *map,
1230 bool add_sample_positions,
1231 uint32_t esgs_ring_size,
1232 struct radeon_winsys_bo *esgs_ring_bo,
1233 uint32_t gsvs_ring_size,
1234 struct radeon_winsys_bo *gsvs_ring_bo,
1235 uint32_t tess_factor_ring_size,
1236 struct radeon_winsys_bo *tess_factor_ring_bo,
1237 uint32_t tess_offchip_ring_size,
1238 struct radeon_winsys_bo *tess_offchip_ring_bo)
1239 {
1240 uint64_t esgs_va = 0, gsvs_va = 0;
1241 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1242 uint32_t *desc = &map[4];
1243
1244 if (esgs_ring_bo)
1245 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1246 if (gsvs_ring_bo)
1247 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1248 if (tess_factor_ring_bo)
1249 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1250 if (tess_offchip_ring_bo)
1251 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1252
1253 /* stride 0, num records - size, add tid, swizzle, elsize4,
1254 index stride 64 */
1255 desc[0] = esgs_va;
1256 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1257 S_008F04_STRIDE(0) |
1258 S_008F04_SWIZZLE_ENABLE(true);
1259 desc[2] = esgs_ring_size;
1260 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1261 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1262 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1263 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1264 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1265 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1266 S_008F0C_ELEMENT_SIZE(1) |
1267 S_008F0C_INDEX_STRIDE(3) |
1268 S_008F0C_ADD_TID_ENABLE(true);
1269
1270 desc += 4;
1271 /* GS entry for ES->GS ring */
1272 /* stride 0, num records - size, elsize0,
1273 index stride 0 */
1274 desc[0] = esgs_va;
1275 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1276 S_008F04_STRIDE(0) |
1277 S_008F04_SWIZZLE_ENABLE(false);
1278 desc[2] = esgs_ring_size;
1279 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1280 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1281 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1282 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1283 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1284 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1285 S_008F0C_ELEMENT_SIZE(0) |
1286 S_008F0C_INDEX_STRIDE(0) |
1287 S_008F0C_ADD_TID_ENABLE(false);
1288
1289 desc += 4;
1290 /* VS entry for GS->VS ring */
1291 /* stride 0, num records - size, elsize0,
1292 index stride 0 */
1293 desc[0] = gsvs_va;
1294 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1295 S_008F04_STRIDE(0) |
1296 S_008F04_SWIZZLE_ENABLE(false);
1297 desc[2] = gsvs_ring_size;
1298 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1299 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1300 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1301 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1302 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1303 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1304 S_008F0C_ELEMENT_SIZE(0) |
1305 S_008F0C_INDEX_STRIDE(0) |
1306 S_008F0C_ADD_TID_ENABLE(false);
1307 desc += 4;
1308
1309 /* stride gsvs_itemsize, num records 64
1310 elsize 4, index stride 16 */
1311 /* shader will patch stride and desc[2] */
1312 desc[0] = gsvs_va;
1313 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1314 S_008F04_STRIDE(0) |
1315 S_008F04_SWIZZLE_ENABLE(true);
1316 desc[2] = 0;
1317 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1318 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1319 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1320 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1321 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1322 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1323 S_008F0C_ELEMENT_SIZE(1) |
1324 S_008F0C_INDEX_STRIDE(1) |
1325 S_008F0C_ADD_TID_ENABLE(true);
1326 desc += 4;
1327
1328 desc[0] = tess_factor_va;
1329 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1330 S_008F04_STRIDE(0) |
1331 S_008F04_SWIZZLE_ENABLE(false);
1332 desc[2] = tess_factor_ring_size;
1333 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1334 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1335 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1336 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1337 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1338 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1339 S_008F0C_ELEMENT_SIZE(0) |
1340 S_008F0C_INDEX_STRIDE(0) |
1341 S_008F0C_ADD_TID_ENABLE(false);
1342 desc += 4;
1343
1344 desc[0] = tess_offchip_va;
1345 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1346 S_008F04_STRIDE(0) |
1347 S_008F04_SWIZZLE_ENABLE(false);
1348 desc[2] = tess_offchip_ring_size;
1349 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1350 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1351 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1352 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1353 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1354 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1355 S_008F0C_ELEMENT_SIZE(0) |
1356 S_008F0C_INDEX_STRIDE(0) |
1357 S_008F0C_ADD_TID_ENABLE(false);
1358 desc += 4;
1359
1360 /* add sample positions after all rings */
1361 memcpy(desc, queue->device->sample_locations_1x, 8);
1362 desc += 2;
1363 memcpy(desc, queue->device->sample_locations_2x, 16);
1364 desc += 4;
1365 memcpy(desc, queue->device->sample_locations_4x, 32);
1366 desc += 8;
1367 memcpy(desc, queue->device->sample_locations_8x, 64);
1368 desc += 16;
1369 memcpy(desc, queue->device->sample_locations_16x, 128);
1370 }
1371
1372 static unsigned
1373 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1374 {
1375 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1376 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1377 device->physical_device->rad_info.family != CHIP_STONEY;
1378 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1379 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1380 device->physical_device->rad_info.max_se;
1381 unsigned offchip_granularity;
1382 unsigned hs_offchip_param;
1383 switch (device->tess_offchip_block_dw_size) {
1384 default:
1385 assert(0);
1386 /* fall through */
1387 case 8192:
1388 offchip_granularity = V_03093C_X_8K_DWORDS;
1389 break;
1390 case 4096:
1391 offchip_granularity = V_03093C_X_4K_DWORDS;
1392 break;
1393 }
1394
1395 switch (device->physical_device->rad_info.chip_class) {
1396 case SI:
1397 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1398 break;
1399 case CIK:
1400 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1401 break;
1402 case VI:
1403 default:
1404 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
1405 break;
1406 }
1407
1408 *max_offchip_buffers_p = max_offchip_buffers;
1409 if (device->physical_device->rad_info.chip_class >= CIK) {
1410 if (device->physical_device->rad_info.chip_class >= VI)
1411 --max_offchip_buffers;
1412 hs_offchip_param =
1413 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1414 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1415 } else {
1416 hs_offchip_param =
1417 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1418 }
1419 return hs_offchip_param;
1420 }
1421
1422 static VkResult
1423 radv_get_preamble_cs(struct radv_queue *queue,
1424 uint32_t scratch_size,
1425 uint32_t compute_scratch_size,
1426 uint32_t esgs_ring_size,
1427 uint32_t gsvs_ring_size,
1428 bool needs_tess_rings,
1429 bool needs_sample_positions,
1430 struct radeon_winsys_cs **initial_preamble_cs,
1431 struct radeon_winsys_cs **continue_preamble_cs)
1432 {
1433 struct radeon_winsys_bo *scratch_bo = NULL;
1434 struct radeon_winsys_bo *descriptor_bo = NULL;
1435 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1436 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1437 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1438 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1439 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1440 struct radeon_winsys_cs *dest_cs[2] = {0};
1441 bool add_tess_rings = false, add_sample_positions = false;
1442 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1443 unsigned max_offchip_buffers;
1444 unsigned hs_offchip_param = 0;
1445 if (!queue->has_tess_rings) {
1446 if (needs_tess_rings)
1447 add_tess_rings = true;
1448 }
1449 if (!queue->has_sample_positions) {
1450 if (needs_sample_positions)
1451 add_sample_positions = true;
1452 }
1453 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1454 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1455 &max_offchip_buffers);
1456 tess_offchip_ring_size = max_offchip_buffers *
1457 queue->device->tess_offchip_block_dw_size * 4;
1458
1459 if (scratch_size <= queue->scratch_size &&
1460 compute_scratch_size <= queue->compute_scratch_size &&
1461 esgs_ring_size <= queue->esgs_ring_size &&
1462 gsvs_ring_size <= queue->gsvs_ring_size &&
1463 !add_tess_rings && !add_sample_positions &&
1464 queue->initial_preamble_cs) {
1465 *initial_preamble_cs = queue->initial_preamble_cs;
1466 *continue_preamble_cs = queue->continue_preamble_cs;
1467 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1468 *continue_preamble_cs = NULL;
1469 return VK_SUCCESS;
1470 }
1471
1472 if (scratch_size > queue->scratch_size) {
1473 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1474 scratch_size,
1475 4096,
1476 RADEON_DOMAIN_VRAM,
1477 RADEON_FLAG_NO_CPU_ACCESS);
1478 if (!scratch_bo)
1479 goto fail;
1480 } else
1481 scratch_bo = queue->scratch_bo;
1482
1483 if (compute_scratch_size > queue->compute_scratch_size) {
1484 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1485 compute_scratch_size,
1486 4096,
1487 RADEON_DOMAIN_VRAM,
1488 RADEON_FLAG_NO_CPU_ACCESS);
1489 if (!compute_scratch_bo)
1490 goto fail;
1491
1492 } else
1493 compute_scratch_bo = queue->compute_scratch_bo;
1494
1495 if (esgs_ring_size > queue->esgs_ring_size) {
1496 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1497 esgs_ring_size,
1498 4096,
1499 RADEON_DOMAIN_VRAM,
1500 RADEON_FLAG_NO_CPU_ACCESS);
1501 if (!esgs_ring_bo)
1502 goto fail;
1503 } else {
1504 esgs_ring_bo = queue->esgs_ring_bo;
1505 esgs_ring_size = queue->esgs_ring_size;
1506 }
1507
1508 if (gsvs_ring_size > queue->gsvs_ring_size) {
1509 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1510 gsvs_ring_size,
1511 4096,
1512 RADEON_DOMAIN_VRAM,
1513 RADEON_FLAG_NO_CPU_ACCESS);
1514 if (!gsvs_ring_bo)
1515 goto fail;
1516 } else {
1517 gsvs_ring_bo = queue->gsvs_ring_bo;
1518 gsvs_ring_size = queue->gsvs_ring_size;
1519 }
1520
1521 if (add_tess_rings) {
1522 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1523 tess_factor_ring_size,
1524 256,
1525 RADEON_DOMAIN_VRAM,
1526 RADEON_FLAG_NO_CPU_ACCESS);
1527 if (!tess_factor_ring_bo)
1528 goto fail;
1529 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1530 tess_offchip_ring_size,
1531 256,
1532 RADEON_DOMAIN_VRAM,
1533 RADEON_FLAG_NO_CPU_ACCESS);
1534 if (!tess_offchip_ring_bo)
1535 goto fail;
1536 } else {
1537 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1538 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1539 }
1540
1541 if (scratch_bo != queue->scratch_bo ||
1542 esgs_ring_bo != queue->esgs_ring_bo ||
1543 gsvs_ring_bo != queue->gsvs_ring_bo ||
1544 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1545 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1546 uint32_t size = 0;
1547 if (gsvs_ring_bo || esgs_ring_bo ||
1548 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1549 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1550 if (add_sample_positions)
1551 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1552 }
1553 else if (scratch_bo)
1554 size = 8; /* 2 dword */
1555
1556 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1557 size,
1558 4096,
1559 RADEON_DOMAIN_VRAM,
1560 RADEON_FLAG_CPU_ACCESS);
1561 if (!descriptor_bo)
1562 goto fail;
1563 } else
1564 descriptor_bo = queue->descriptor_bo;
1565
1566 for(int i = 0; i < 2; ++i) {
1567 struct radeon_winsys_cs *cs = NULL;
1568 cs = queue->device->ws->cs_create(queue->device->ws,
1569 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1570 if (!cs)
1571 goto fail;
1572
1573 dest_cs[i] = cs;
1574
1575 if (scratch_bo)
1576 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1577
1578 if (esgs_ring_bo)
1579 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1580
1581 if (gsvs_ring_bo)
1582 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1583
1584 if (tess_factor_ring_bo)
1585 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1586
1587 if (tess_offchip_ring_bo)
1588 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1589
1590 if (descriptor_bo)
1591 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1592
1593 if (descriptor_bo != queue->descriptor_bo) {
1594 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1595
1596 if (scratch_bo) {
1597 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1598 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1599 S_008F04_SWIZZLE_ENABLE(1);
1600 map[0] = scratch_va;
1601 map[1] = rsrc1;
1602 }
1603
1604 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1605 add_sample_positions)
1606 fill_geom_tess_rings(queue, map, add_sample_positions,
1607 esgs_ring_size, esgs_ring_bo,
1608 gsvs_ring_size, gsvs_ring_bo,
1609 tess_factor_ring_size, tess_factor_ring_bo,
1610 tess_offchip_ring_size, tess_offchip_ring_bo);
1611
1612 queue->device->ws->buffer_unmap(descriptor_bo);
1613 }
1614
1615 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1616 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1617 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1618 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1619 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1620 }
1621
1622 if (esgs_ring_bo || gsvs_ring_bo) {
1623 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1624 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1625 radeon_emit(cs, esgs_ring_size >> 8);
1626 radeon_emit(cs, gsvs_ring_size >> 8);
1627 } else {
1628 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1629 radeon_emit(cs, esgs_ring_size >> 8);
1630 radeon_emit(cs, gsvs_ring_size >> 8);
1631 }
1632 }
1633
1634 if (tess_factor_ring_bo) {
1635 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1636 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1637 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1638 S_030938_SIZE(tess_factor_ring_size / 4));
1639 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1640 tf_va >> 8);
1641 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1642 } else {
1643 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1644 S_008988_SIZE(tess_factor_ring_size / 4));
1645 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1646 tf_va >> 8);
1647 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1648 hs_offchip_param);
1649 }
1650 }
1651
1652 if (descriptor_bo) {
1653 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1654 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1655 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1656 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1657 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1658 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1659
1660 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1661
1662 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1663 radeon_set_sh_reg_seq(cs, regs[i], 2);
1664 radeon_emit(cs, va);
1665 radeon_emit(cs, va >> 32);
1666 }
1667 }
1668
1669 if (compute_scratch_bo) {
1670 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1671 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1672 S_008F04_SWIZZLE_ENABLE(1);
1673
1674 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1675
1676 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1677 radeon_emit(cs, scratch_va);
1678 radeon_emit(cs, rsrc1);
1679 }
1680
1681 if (!i) {
1682 si_cs_emit_cache_flush(cs,
1683 queue->device->physical_device->rad_info.chip_class,
1684 queue->queue_family_index == RING_COMPUTE &&
1685 queue->device->physical_device->rad_info.chip_class >= CIK,
1686 RADV_CMD_FLAG_INV_ICACHE |
1687 RADV_CMD_FLAG_INV_SMEM_L1 |
1688 RADV_CMD_FLAG_INV_VMEM_L1 |
1689 RADV_CMD_FLAG_INV_GLOBAL_L2);
1690 }
1691
1692 if (!queue->device->ws->cs_finalize(cs))
1693 goto fail;
1694 }
1695
1696 if (queue->initial_preamble_cs)
1697 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1698
1699 if (queue->continue_preamble_cs)
1700 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1701
1702 queue->initial_preamble_cs = dest_cs[0];
1703 queue->continue_preamble_cs = dest_cs[1];
1704
1705 if (scratch_bo != queue->scratch_bo) {
1706 if (queue->scratch_bo)
1707 queue->device->ws->buffer_destroy(queue->scratch_bo);
1708 queue->scratch_bo = scratch_bo;
1709 queue->scratch_size = scratch_size;
1710 }
1711
1712 if (compute_scratch_bo != queue->compute_scratch_bo) {
1713 if (queue->compute_scratch_bo)
1714 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1715 queue->compute_scratch_bo = compute_scratch_bo;
1716 queue->compute_scratch_size = compute_scratch_size;
1717 }
1718
1719 if (esgs_ring_bo != queue->esgs_ring_bo) {
1720 if (queue->esgs_ring_bo)
1721 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1722 queue->esgs_ring_bo = esgs_ring_bo;
1723 queue->esgs_ring_size = esgs_ring_size;
1724 }
1725
1726 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1727 if (queue->gsvs_ring_bo)
1728 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1729 queue->gsvs_ring_bo = gsvs_ring_bo;
1730 queue->gsvs_ring_size = gsvs_ring_size;
1731 }
1732
1733 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1734 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1735 }
1736
1737 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1738 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1739 queue->has_tess_rings = true;
1740 }
1741
1742 if (descriptor_bo != queue->descriptor_bo) {
1743 if (queue->descriptor_bo)
1744 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1745
1746 queue->descriptor_bo = descriptor_bo;
1747 }
1748
1749 if (add_sample_positions)
1750 queue->has_sample_positions = true;
1751
1752 *initial_preamble_cs = queue->initial_preamble_cs;
1753 *continue_preamble_cs = queue->continue_preamble_cs;
1754 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1755 *continue_preamble_cs = NULL;
1756 return VK_SUCCESS;
1757 fail:
1758 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1759 if (dest_cs[i])
1760 queue->device->ws->cs_destroy(dest_cs[i]);
1761 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1762 queue->device->ws->buffer_destroy(descriptor_bo);
1763 if (scratch_bo && scratch_bo != queue->scratch_bo)
1764 queue->device->ws->buffer_destroy(scratch_bo);
1765 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1766 queue->device->ws->buffer_destroy(compute_scratch_bo);
1767 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1768 queue->device->ws->buffer_destroy(esgs_ring_bo);
1769 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1770 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1771 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1772 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1773 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1774 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1775 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1776 }
1777
1778 VkResult radv_QueueSubmit(
1779 VkQueue _queue,
1780 uint32_t submitCount,
1781 const VkSubmitInfo* pSubmits,
1782 VkFence _fence)
1783 {
1784 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1785 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1786 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1787 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1788 int ret;
1789 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1790 uint32_t scratch_size = 0;
1791 uint32_t compute_scratch_size = 0;
1792 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1793 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1794 VkResult result;
1795 bool fence_emitted = false;
1796 bool tess_rings_needed = false;
1797 bool sample_positions_needed = false;
1798
1799 /* Do this first so failing to allocate scratch buffers can't result in
1800 * partially executed submissions. */
1801 for (uint32_t i = 0; i < submitCount; i++) {
1802 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1804 pSubmits[i].pCommandBuffers[j]);
1805
1806 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1807 compute_scratch_size = MAX2(compute_scratch_size,
1808 cmd_buffer->compute_scratch_size_needed);
1809 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1810 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1811 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1812 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1813 }
1814 }
1815
1816 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1817 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1818 sample_positions_needed,
1819 &initial_preamble_cs, &continue_preamble_cs);
1820 if (result != VK_SUCCESS)
1821 return result;
1822
1823 for (uint32_t i = 0; i < submitCount; i++) {
1824 struct radeon_winsys_cs **cs_array;
1825 bool do_flush = !i;
1826 bool can_patch = !do_flush;
1827 uint32_t advance;
1828
1829 if (!pSubmits[i].commandBufferCount) {
1830 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1831 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1832 &queue->device->empty_cs[queue->queue_family_index],
1833 1, NULL, NULL,
1834 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1835 pSubmits[i].waitSemaphoreCount,
1836 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1837 pSubmits[i].signalSemaphoreCount,
1838 false, base_fence);
1839 if (ret) {
1840 radv_loge("failed to submit CS %d\n", i);
1841 abort();
1842 }
1843 fence_emitted = true;
1844 }
1845 continue;
1846 }
1847
1848 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1849 (pSubmits[i].commandBufferCount + do_flush));
1850
1851 if(do_flush)
1852 cs_array[0] = queue->device->flush_cs[queue->queue_family_index];
1853
1854 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1856 pSubmits[i].pCommandBuffers[j]);
1857 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1858
1859 cs_array[j + do_flush] = cmd_buffer->cs;
1860 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1861 can_patch = false;
1862 }
1863
1864 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1865 advance = MIN2(max_cs_submission,
1866 pSubmits[i].commandBufferCount + do_flush - j);
1867 bool b = j == 0;
1868 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1869
1870 if (queue->device->trace_bo)
1871 *queue->device->trace_id_ptr = 0;
1872
1873 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1874 advance, initial_preamble_cs, continue_preamble_cs,
1875 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1876 b ? pSubmits[i].waitSemaphoreCount : 0,
1877 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1878 e ? pSubmits[i].signalSemaphoreCount : 0,
1879 can_patch, base_fence);
1880
1881 if (ret) {
1882 radv_loge("failed to submit CS %d\n", i);
1883 abort();
1884 }
1885 fence_emitted = true;
1886 if (queue->device->trace_bo) {
1887 bool success = queue->device->ws->ctx_wait_idle(
1888 queue->hw_ctx,
1889 radv_queue_family_to_ring(
1890 queue->queue_family_index),
1891 queue->queue_idx);
1892
1893 if (!success) { /* Hang */
1894 radv_dump_trace(queue->device, cs_array[j]);
1895 abort();
1896 }
1897 }
1898 }
1899 free(cs_array);
1900 }
1901
1902 if (fence) {
1903 if (!fence_emitted)
1904 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1905 &queue->device->empty_cs[queue->queue_family_index],
1906 1, NULL, NULL, NULL, 0, NULL, 0,
1907 false, base_fence);
1908
1909 fence->submitted = true;
1910 }
1911
1912 return VK_SUCCESS;
1913 }
1914
1915 VkResult radv_QueueWaitIdle(
1916 VkQueue _queue)
1917 {
1918 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1919
1920 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1921 radv_queue_family_to_ring(queue->queue_family_index),
1922 queue->queue_idx);
1923 return VK_SUCCESS;
1924 }
1925
1926 VkResult radv_DeviceWaitIdle(
1927 VkDevice _device)
1928 {
1929 RADV_FROM_HANDLE(radv_device, device, _device);
1930
1931 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1932 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1933 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1934 }
1935 }
1936 return VK_SUCCESS;
1937 }
1938
1939 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1940 VkInstance instance,
1941 const char* pName)
1942 {
1943 return radv_lookup_entrypoint(pName);
1944 }
1945
1946 /* The loader wants us to expose a second GetInstanceProcAddr function
1947 * to work around certain LD_PRELOAD issues seen in apps.
1948 */
1949 PUBLIC
1950 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1951 VkInstance instance,
1952 const char* pName);
1953
1954 PUBLIC
1955 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1956 VkInstance instance,
1957 const char* pName)
1958 {
1959 return radv_GetInstanceProcAddr(instance, pName);
1960 }
1961
1962 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1963 VkDevice device,
1964 const char* pName)
1965 {
1966 return radv_lookup_entrypoint(pName);
1967 }
1968
1969 bool radv_get_memory_fd(struct radv_device *device,
1970 struct radv_device_memory *memory,
1971 int *pFD)
1972 {
1973 struct radeon_bo_metadata metadata;
1974
1975 if (memory->image) {
1976 radv_init_metadata(device, memory->image, &metadata);
1977 device->ws->buffer_set_metadata(memory->bo, &metadata);
1978 }
1979
1980 return device->ws->buffer_get_fd(device->ws, memory->bo,
1981 pFD);
1982 }
1983
1984 VkResult radv_AllocateMemory(
1985 VkDevice _device,
1986 const VkMemoryAllocateInfo* pAllocateInfo,
1987 const VkAllocationCallbacks* pAllocator,
1988 VkDeviceMemory* pMem)
1989 {
1990 RADV_FROM_HANDLE(radv_device, device, _device);
1991 struct radv_device_memory *mem;
1992 VkResult result;
1993 enum radeon_bo_domain domain;
1994 uint32_t flags = 0;
1995 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
1996 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1997
1998 if (pAllocateInfo->allocationSize == 0) {
1999 /* Apparently, this is allowed */
2000 *pMem = VK_NULL_HANDLE;
2001 return VK_SUCCESS;
2002 }
2003
2004 vk_foreach_struct(ext, pAllocateInfo->pNext) {
2005 switch (ext->sType) {
2006 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
2007 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
2008 break;
2009 default:
2010 break;
2011 }
2012 }
2013
2014 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2015 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2016 if (mem == NULL)
2017 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2018
2019 if (dedicate_info) {
2020 mem->image = radv_image_from_handle(dedicate_info->image);
2021 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2022 } else {
2023 mem->image = NULL;
2024 mem->buffer = NULL;
2025 }
2026
2027 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2028 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2029 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2030 domain = RADEON_DOMAIN_GTT;
2031 else
2032 domain = RADEON_DOMAIN_VRAM;
2033
2034 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2035 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2036 else
2037 flags |= RADEON_FLAG_CPU_ACCESS;
2038
2039 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2040 flags |= RADEON_FLAG_GTT_WC;
2041
2042 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2043 domain, flags);
2044
2045 if (!mem->bo) {
2046 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2047 goto fail;
2048 }
2049 mem->type_index = pAllocateInfo->memoryTypeIndex;
2050
2051 *pMem = radv_device_memory_to_handle(mem);
2052
2053 return VK_SUCCESS;
2054
2055 fail:
2056 vk_free2(&device->alloc, pAllocator, mem);
2057
2058 return result;
2059 }
2060
2061 void radv_FreeMemory(
2062 VkDevice _device,
2063 VkDeviceMemory _mem,
2064 const VkAllocationCallbacks* pAllocator)
2065 {
2066 RADV_FROM_HANDLE(radv_device, device, _device);
2067 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2068
2069 if (mem == NULL)
2070 return;
2071
2072 device->ws->buffer_destroy(mem->bo);
2073 mem->bo = NULL;
2074
2075 vk_free2(&device->alloc, pAllocator, mem);
2076 }
2077
2078 VkResult radv_MapMemory(
2079 VkDevice _device,
2080 VkDeviceMemory _memory,
2081 VkDeviceSize offset,
2082 VkDeviceSize size,
2083 VkMemoryMapFlags flags,
2084 void** ppData)
2085 {
2086 RADV_FROM_HANDLE(radv_device, device, _device);
2087 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2088
2089 if (mem == NULL) {
2090 *ppData = NULL;
2091 return VK_SUCCESS;
2092 }
2093
2094 *ppData = device->ws->buffer_map(mem->bo);
2095 if (*ppData) {
2096 *ppData += offset;
2097 return VK_SUCCESS;
2098 }
2099
2100 return VK_ERROR_MEMORY_MAP_FAILED;
2101 }
2102
2103 void radv_UnmapMemory(
2104 VkDevice _device,
2105 VkDeviceMemory _memory)
2106 {
2107 RADV_FROM_HANDLE(radv_device, device, _device);
2108 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2109
2110 if (mem == NULL)
2111 return;
2112
2113 device->ws->buffer_unmap(mem->bo);
2114 }
2115
2116 VkResult radv_FlushMappedMemoryRanges(
2117 VkDevice _device,
2118 uint32_t memoryRangeCount,
2119 const VkMappedMemoryRange* pMemoryRanges)
2120 {
2121 return VK_SUCCESS;
2122 }
2123
2124 VkResult radv_InvalidateMappedMemoryRanges(
2125 VkDevice _device,
2126 uint32_t memoryRangeCount,
2127 const VkMappedMemoryRange* pMemoryRanges)
2128 {
2129 return VK_SUCCESS;
2130 }
2131
2132 void radv_GetBufferMemoryRequirements(
2133 VkDevice device,
2134 VkBuffer _buffer,
2135 VkMemoryRequirements* pMemoryRequirements)
2136 {
2137 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2138
2139 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2140
2141 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2142 pMemoryRequirements->alignment = 4096;
2143 else
2144 pMemoryRequirements->alignment = 16;
2145
2146 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2147 }
2148
2149 void radv_GetImageMemoryRequirements(
2150 VkDevice device,
2151 VkImage _image,
2152 VkMemoryRequirements* pMemoryRequirements)
2153 {
2154 RADV_FROM_HANDLE(radv_image, image, _image);
2155
2156 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2157
2158 pMemoryRequirements->size = image->size;
2159 pMemoryRequirements->alignment = image->alignment;
2160 }
2161
2162 void radv_GetImageSparseMemoryRequirements(
2163 VkDevice device,
2164 VkImage image,
2165 uint32_t* pSparseMemoryRequirementCount,
2166 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2167 {
2168 stub();
2169 }
2170
2171 void radv_GetDeviceMemoryCommitment(
2172 VkDevice device,
2173 VkDeviceMemory memory,
2174 VkDeviceSize* pCommittedMemoryInBytes)
2175 {
2176 *pCommittedMemoryInBytes = 0;
2177 }
2178
2179 VkResult radv_BindBufferMemory(
2180 VkDevice device,
2181 VkBuffer _buffer,
2182 VkDeviceMemory _memory,
2183 VkDeviceSize memoryOffset)
2184 {
2185 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2186 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2187
2188 if (mem) {
2189 buffer->bo = mem->bo;
2190 buffer->offset = memoryOffset;
2191 } else {
2192 buffer->bo = NULL;
2193 buffer->offset = 0;
2194 }
2195
2196 return VK_SUCCESS;
2197 }
2198
2199 VkResult radv_BindImageMemory(
2200 VkDevice device,
2201 VkImage _image,
2202 VkDeviceMemory _memory,
2203 VkDeviceSize memoryOffset)
2204 {
2205 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2206 RADV_FROM_HANDLE(radv_image, image, _image);
2207
2208 if (mem) {
2209 image->bo = mem->bo;
2210 image->offset = memoryOffset;
2211 } else {
2212 image->bo = NULL;
2213 image->offset = 0;
2214 }
2215
2216 return VK_SUCCESS;
2217 }
2218
2219
2220 static void
2221 radv_sparse_buffer_bind_memory(struct radv_device *device,
2222 const VkSparseBufferMemoryBindInfo *bind)
2223 {
2224 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2225
2226 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2227 struct radv_device_memory *mem = NULL;
2228
2229 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2230 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2231
2232 device->ws->buffer_virtual_bind(buffer->bo,
2233 bind->pBinds[i].resourceOffset,
2234 bind->pBinds[i].size,
2235 mem ? mem->bo : NULL,
2236 bind->pBinds[i].memoryOffset);
2237 }
2238 }
2239
2240 static void
2241 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2242 const VkSparseImageOpaqueMemoryBindInfo *bind)
2243 {
2244 RADV_FROM_HANDLE(radv_image, image, bind->image);
2245
2246 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2247 struct radv_device_memory *mem = NULL;
2248
2249 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2250 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2251
2252 device->ws->buffer_virtual_bind(image->bo,
2253 bind->pBinds[i].resourceOffset,
2254 bind->pBinds[i].size,
2255 mem ? mem->bo : NULL,
2256 bind->pBinds[i].memoryOffset);
2257 }
2258 }
2259
2260 VkResult radv_QueueBindSparse(
2261 VkQueue _queue,
2262 uint32_t bindInfoCount,
2263 const VkBindSparseInfo* pBindInfo,
2264 VkFence _fence)
2265 {
2266 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2267 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2268 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2269 bool fence_emitted = false;
2270
2271 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2272 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2273 radv_sparse_buffer_bind_memory(queue->device,
2274 pBindInfo[i].pBufferBinds + j);
2275 }
2276
2277 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2278 radv_sparse_image_opaque_bind_memory(queue->device,
2279 pBindInfo[i].pImageOpaqueBinds + j);
2280 }
2281
2282 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2283 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2284 &queue->device->empty_cs[queue->queue_family_index],
2285 1, NULL, NULL,
2286 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2287 pBindInfo[i].waitSemaphoreCount,
2288 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2289 pBindInfo[i].signalSemaphoreCount,
2290 false, base_fence);
2291 fence_emitted = true;
2292 if (fence)
2293 fence->submitted = true;
2294 }
2295 }
2296
2297 if (fence && !fence_emitted) {
2298 fence->signalled = true;
2299 }
2300
2301 return VK_SUCCESS;
2302 }
2303
2304 VkResult radv_CreateFence(
2305 VkDevice _device,
2306 const VkFenceCreateInfo* pCreateInfo,
2307 const VkAllocationCallbacks* pAllocator,
2308 VkFence* pFence)
2309 {
2310 RADV_FROM_HANDLE(radv_device, device, _device);
2311 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2312 sizeof(*fence), 8,
2313 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2314
2315 if (!fence)
2316 return VK_ERROR_OUT_OF_HOST_MEMORY;
2317
2318 memset(fence, 0, sizeof(*fence));
2319 fence->submitted = false;
2320 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2321 fence->fence = device->ws->create_fence();
2322 if (!fence->fence) {
2323 vk_free2(&device->alloc, pAllocator, fence);
2324 return VK_ERROR_OUT_OF_HOST_MEMORY;
2325 }
2326
2327 *pFence = radv_fence_to_handle(fence);
2328
2329 return VK_SUCCESS;
2330 }
2331
2332 void radv_DestroyFence(
2333 VkDevice _device,
2334 VkFence _fence,
2335 const VkAllocationCallbacks* pAllocator)
2336 {
2337 RADV_FROM_HANDLE(radv_device, device, _device);
2338 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2339
2340 if (!fence)
2341 return;
2342 device->ws->destroy_fence(fence->fence);
2343 vk_free2(&device->alloc, pAllocator, fence);
2344 }
2345
2346 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2347 {
2348 uint64_t current_time;
2349 struct timespec tv;
2350
2351 clock_gettime(CLOCK_MONOTONIC, &tv);
2352 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2353
2354 timeout = MIN2(UINT64_MAX - current_time, timeout);
2355
2356 return current_time + timeout;
2357 }
2358
2359 VkResult radv_WaitForFences(
2360 VkDevice _device,
2361 uint32_t fenceCount,
2362 const VkFence* pFences,
2363 VkBool32 waitAll,
2364 uint64_t timeout)
2365 {
2366 RADV_FROM_HANDLE(radv_device, device, _device);
2367 timeout = radv_get_absolute_timeout(timeout);
2368
2369 if (!waitAll && fenceCount > 1) {
2370 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2371 }
2372
2373 for (uint32_t i = 0; i < fenceCount; ++i) {
2374 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2375 bool expired = false;
2376
2377 if (fence->signalled)
2378 continue;
2379
2380 if (!fence->submitted)
2381 return VK_TIMEOUT;
2382
2383 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2384 if (!expired)
2385 return VK_TIMEOUT;
2386
2387 fence->signalled = true;
2388 }
2389
2390 return VK_SUCCESS;
2391 }
2392
2393 VkResult radv_ResetFences(VkDevice device,
2394 uint32_t fenceCount,
2395 const VkFence *pFences)
2396 {
2397 for (unsigned i = 0; i < fenceCount; ++i) {
2398 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2399 fence->submitted = fence->signalled = false;
2400 }
2401
2402 return VK_SUCCESS;
2403 }
2404
2405 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2406 {
2407 RADV_FROM_HANDLE(radv_device, device, _device);
2408 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2409
2410 if (fence->signalled)
2411 return VK_SUCCESS;
2412 if (!fence->submitted)
2413 return VK_NOT_READY;
2414
2415 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2416 return VK_NOT_READY;
2417
2418 return VK_SUCCESS;
2419 }
2420
2421
2422 // Queue semaphore functions
2423
2424 VkResult radv_CreateSemaphore(
2425 VkDevice _device,
2426 const VkSemaphoreCreateInfo* pCreateInfo,
2427 const VkAllocationCallbacks* pAllocator,
2428 VkSemaphore* pSemaphore)
2429 {
2430 RADV_FROM_HANDLE(radv_device, device, _device);
2431 struct radeon_winsys_sem *sem;
2432
2433 sem = device->ws->create_sem(device->ws);
2434 if (!sem)
2435 return VK_ERROR_OUT_OF_HOST_MEMORY;
2436
2437 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2438 return VK_SUCCESS;
2439 }
2440
2441 void radv_DestroySemaphore(
2442 VkDevice _device,
2443 VkSemaphore _semaphore,
2444 const VkAllocationCallbacks* pAllocator)
2445 {
2446 RADV_FROM_HANDLE(radv_device, device, _device);
2447 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2448 if (!_semaphore)
2449 return;
2450
2451 device->ws->destroy_sem(sem);
2452 }
2453
2454 VkResult radv_CreateEvent(
2455 VkDevice _device,
2456 const VkEventCreateInfo* pCreateInfo,
2457 const VkAllocationCallbacks* pAllocator,
2458 VkEvent* pEvent)
2459 {
2460 RADV_FROM_HANDLE(radv_device, device, _device);
2461 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2462 sizeof(*event), 8,
2463 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2464
2465 if (!event)
2466 return VK_ERROR_OUT_OF_HOST_MEMORY;
2467
2468 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2469 RADEON_DOMAIN_GTT,
2470 RADEON_FLAG_CPU_ACCESS);
2471 if (!event->bo) {
2472 vk_free2(&device->alloc, pAllocator, event);
2473 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2474 }
2475
2476 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2477
2478 *pEvent = radv_event_to_handle(event);
2479
2480 return VK_SUCCESS;
2481 }
2482
2483 void radv_DestroyEvent(
2484 VkDevice _device,
2485 VkEvent _event,
2486 const VkAllocationCallbacks* pAllocator)
2487 {
2488 RADV_FROM_HANDLE(radv_device, device, _device);
2489 RADV_FROM_HANDLE(radv_event, event, _event);
2490
2491 if (!event)
2492 return;
2493 device->ws->buffer_destroy(event->bo);
2494 vk_free2(&device->alloc, pAllocator, event);
2495 }
2496
2497 VkResult radv_GetEventStatus(
2498 VkDevice _device,
2499 VkEvent _event)
2500 {
2501 RADV_FROM_HANDLE(radv_event, event, _event);
2502
2503 if (*event->map == 1)
2504 return VK_EVENT_SET;
2505 return VK_EVENT_RESET;
2506 }
2507
2508 VkResult radv_SetEvent(
2509 VkDevice _device,
2510 VkEvent _event)
2511 {
2512 RADV_FROM_HANDLE(radv_event, event, _event);
2513 *event->map = 1;
2514
2515 return VK_SUCCESS;
2516 }
2517
2518 VkResult radv_ResetEvent(
2519 VkDevice _device,
2520 VkEvent _event)
2521 {
2522 RADV_FROM_HANDLE(radv_event, event, _event);
2523 *event->map = 0;
2524
2525 return VK_SUCCESS;
2526 }
2527
2528 VkResult radv_CreateBuffer(
2529 VkDevice _device,
2530 const VkBufferCreateInfo* pCreateInfo,
2531 const VkAllocationCallbacks* pAllocator,
2532 VkBuffer* pBuffer)
2533 {
2534 RADV_FROM_HANDLE(radv_device, device, _device);
2535 struct radv_buffer *buffer;
2536
2537 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2538
2539 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2540 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2541 if (buffer == NULL)
2542 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2543
2544 buffer->size = pCreateInfo->size;
2545 buffer->usage = pCreateInfo->usage;
2546 buffer->bo = NULL;
2547 buffer->offset = 0;
2548 buffer->flags = pCreateInfo->flags;
2549
2550 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2551 buffer->bo = device->ws->buffer_create(device->ws,
2552 align64(buffer->size, 4096),
2553 4096, 0, RADEON_FLAG_VIRTUAL);
2554 if (!buffer->bo) {
2555 vk_free2(&device->alloc, pAllocator, buffer);
2556 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2557 }
2558 }
2559
2560 *pBuffer = radv_buffer_to_handle(buffer);
2561
2562 return VK_SUCCESS;
2563 }
2564
2565 void radv_DestroyBuffer(
2566 VkDevice _device,
2567 VkBuffer _buffer,
2568 const VkAllocationCallbacks* pAllocator)
2569 {
2570 RADV_FROM_HANDLE(radv_device, device, _device);
2571 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2572
2573 if (!buffer)
2574 return;
2575
2576 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2577 device->ws->buffer_destroy(buffer->bo);
2578
2579 vk_free2(&device->alloc, pAllocator, buffer);
2580 }
2581
2582 static inline unsigned
2583 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2584 {
2585 if (stencil)
2586 return image->surface.stencil_tiling_index[level];
2587 else
2588 return image->surface.tiling_index[level];
2589 }
2590
2591 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2592 {
2593 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2594 }
2595
2596 static void
2597 radv_initialise_color_surface(struct radv_device *device,
2598 struct radv_color_buffer_info *cb,
2599 struct radv_image_view *iview)
2600 {
2601 const struct vk_format_description *desc;
2602 unsigned ntype, format, swap, endian;
2603 unsigned blend_clamp = 0, blend_bypass = 0;
2604 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2605 uint64_t va;
2606 const struct radeon_surf *surf = &iview->image->surface;
2607 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2608
2609 desc = vk_format_description(iview->vk_format);
2610
2611 memset(cb, 0, sizeof(*cb));
2612
2613 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2614 va += level_info->offset;
2615 cb->cb_color_base = va >> 8;
2616
2617 /* CMASK variables */
2618 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2619 va += iview->image->cmask.offset;
2620 cb->cb_color_cmask = va >> 8;
2621 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2622
2623 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2624 va += iview->image->dcc_offset;
2625 cb->cb_dcc_base = va >> 8;
2626
2627 uint32_t max_slice = radv_surface_layer_count(iview);
2628 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2629 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2630
2631 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2632 pitch_tile_max = level_info->nblk_x / 8 - 1;
2633 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2634 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2635
2636 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2637 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2638
2639 /* Intensity is implemented as Red, so treat it that way. */
2640 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2641 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2642
2643 if (iview->image->info.samples > 1) {
2644 unsigned log_samples = util_logbase2(iview->image->info.samples);
2645
2646 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2647 S_028C74_NUM_FRAGMENTS(log_samples);
2648 }
2649
2650 if (iview->image->fmask.size) {
2651 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2652 if (device->physical_device->rad_info.chip_class >= CIK)
2653 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2654 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2655 cb->cb_color_fmask = va >> 8;
2656 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2657 } else {
2658 /* This must be set for fast clear to work without FMASK. */
2659 if (device->physical_device->rad_info.chip_class >= CIK)
2660 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2661 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2662 cb->cb_color_fmask = cb->cb_color_base;
2663 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2664 }
2665
2666 ntype = radv_translate_color_numformat(iview->vk_format,
2667 desc,
2668 vk_format_get_first_non_void_channel(iview->vk_format));
2669 format = radv_translate_colorformat(iview->vk_format);
2670 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2671 radv_finishme("Illegal color\n");
2672 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2673 endian = radv_colorformat_endian_swap(format);
2674
2675 /* blend clamp should be set for all NORM/SRGB types */
2676 if (ntype == V_028C70_NUMBER_UNORM ||
2677 ntype == V_028C70_NUMBER_SNORM ||
2678 ntype == V_028C70_NUMBER_SRGB)
2679 blend_clamp = 1;
2680
2681 /* set blend bypass according to docs if SINT/UINT or
2682 8/24 COLOR variants */
2683 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2684 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2685 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2686 blend_clamp = 0;
2687 blend_bypass = 1;
2688 }
2689 #if 0
2690 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2691 (format == V_028C70_COLOR_8 ||
2692 format == V_028C70_COLOR_8_8 ||
2693 format == V_028C70_COLOR_8_8_8_8))
2694 ->color_is_int8 = true;
2695 #endif
2696 cb->cb_color_info = S_028C70_FORMAT(format) |
2697 S_028C70_COMP_SWAP(swap) |
2698 S_028C70_BLEND_CLAMP(blend_clamp) |
2699 S_028C70_BLEND_BYPASS(blend_bypass) |
2700 S_028C70_SIMPLE_FLOAT(1) |
2701 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2702 ntype != V_028C70_NUMBER_SNORM &&
2703 ntype != V_028C70_NUMBER_SRGB &&
2704 format != V_028C70_COLOR_8_24 &&
2705 format != V_028C70_COLOR_24_8) |
2706 S_028C70_NUMBER_TYPE(ntype) |
2707 S_028C70_ENDIAN(endian);
2708 if (iview->image->info.samples > 1)
2709 if (iview->image->fmask.size)
2710 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2711
2712 if (iview->image->cmask.size &&
2713 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2714 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2715
2716 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2717 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2718
2719 if (device->physical_device->rad_info.chip_class >= VI) {
2720 unsigned max_uncompressed_block_size = 2;
2721 if (iview->image->info.samples > 1) {
2722 if (iview->image->surface.bpe == 1)
2723 max_uncompressed_block_size = 0;
2724 else if (iview->image->surface.bpe == 2)
2725 max_uncompressed_block_size = 1;
2726 }
2727
2728 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2729 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2730 }
2731
2732 /* This must be set for fast clear to work without FMASK. */
2733 if (!iview->image->fmask.size &&
2734 device->physical_device->rad_info.chip_class == SI) {
2735 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2736 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2737 }
2738 }
2739
2740 static void
2741 radv_initialise_ds_surface(struct radv_device *device,
2742 struct radv_ds_buffer_info *ds,
2743 struct radv_image_view *iview)
2744 {
2745 unsigned level = iview->base_mip;
2746 unsigned format;
2747 uint64_t va, s_offs, z_offs;
2748 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2749 bool stencil_only = false;
2750 memset(ds, 0, sizeof(*ds));
2751 switch (iview->vk_format) {
2752 case VK_FORMAT_D24_UNORM_S8_UINT:
2753 case VK_FORMAT_X8_D24_UNORM_PACK32:
2754 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2755 ds->offset_scale = 2.0f;
2756 break;
2757 case VK_FORMAT_D16_UNORM:
2758 case VK_FORMAT_D16_UNORM_S8_UINT:
2759 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2760 ds->offset_scale = 4.0f;
2761 break;
2762 case VK_FORMAT_D32_SFLOAT:
2763 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2764 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2765 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2766 ds->offset_scale = 1.0f;
2767 break;
2768 case VK_FORMAT_S8_UINT:
2769 stencil_only = true;
2770 level_info = &iview->image->surface.stencil_level[level];
2771 break;
2772 default:
2773 break;
2774 }
2775
2776 format = radv_translate_dbformat(iview->vk_format);
2777
2778 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2779 s_offs = z_offs = va;
2780 z_offs += iview->image->surface.level[level].offset;
2781 s_offs += iview->image->surface.stencil_level[level].offset;
2782
2783 uint32_t max_slice = radv_surface_layer_count(iview);
2784 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2785 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2786 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2787 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2788
2789 if (iview->image->info.samples > 1)
2790 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
2791
2792 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2793 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2794 else
2795 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2796
2797 if (device->physical_device->rad_info.chip_class >= CIK) {
2798 struct radeon_info *info = &device->physical_device->rad_info;
2799 unsigned tiling_index = iview->image->surface.tiling_index[level];
2800 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2801 unsigned macro_index = iview->image->surface.macro_tile_index;
2802 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2803 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2804 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2805
2806 if (stencil_only)
2807 tile_mode = stencil_tile_mode;
2808
2809 ds->db_depth_info |=
2810 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2811 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2812 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2813 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2814 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2815 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2816 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2817 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2818 } else {
2819 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2820 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2821 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2822 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2823 }
2824
2825 if (iview->image->surface.htile_size && !level) {
2826 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2827 S_028040_ALLOW_EXPCLEAR(1);
2828
2829 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2830 /* Workaround: For a not yet understood reason, the
2831 * combination of MSAA, fast stencil clear and stencil
2832 * decompress messes with subsequent stencil buffer
2833 * uses. Problem was reproduced on Verde, Bonaire,
2834 * Tonga, and Carrizo.
2835 *
2836 * Disabling EXPCLEAR works around the problem.
2837 *
2838 * Check piglit's arb_texture_multisample-stencil-clear
2839 * test if you want to try changing this.
2840 */
2841 if (iview->image->info.samples <= 1)
2842 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2843 } else
2844 /* Use all of the htile_buffer for depth if there's no stencil. */
2845 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2846
2847 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2848 iview->image->htile_offset;
2849 ds->db_htile_data_base = va >> 8;
2850 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2851 } else {
2852 ds->db_htile_data_base = 0;
2853 ds->db_htile_surface = 0;
2854 }
2855
2856 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2857 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2858
2859 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2860 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2861 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2862 }
2863
2864 VkResult radv_CreateFramebuffer(
2865 VkDevice _device,
2866 const VkFramebufferCreateInfo* pCreateInfo,
2867 const VkAllocationCallbacks* pAllocator,
2868 VkFramebuffer* pFramebuffer)
2869 {
2870 RADV_FROM_HANDLE(radv_device, device, _device);
2871 struct radv_framebuffer *framebuffer;
2872
2873 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2874
2875 size_t size = sizeof(*framebuffer) +
2876 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2877 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2878 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2879 if (framebuffer == NULL)
2880 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2881
2882 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2883 framebuffer->width = pCreateInfo->width;
2884 framebuffer->height = pCreateInfo->height;
2885 framebuffer->layers = pCreateInfo->layers;
2886 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2887 VkImageView _iview = pCreateInfo->pAttachments[i];
2888 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2889 framebuffer->attachments[i].attachment = iview;
2890 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2891 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2892 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2893 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2894 }
2895 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2896 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2897 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2898 }
2899
2900 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2901 return VK_SUCCESS;
2902 }
2903
2904 void radv_DestroyFramebuffer(
2905 VkDevice _device,
2906 VkFramebuffer _fb,
2907 const VkAllocationCallbacks* pAllocator)
2908 {
2909 RADV_FROM_HANDLE(radv_device, device, _device);
2910 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2911
2912 if (!fb)
2913 return;
2914 vk_free2(&device->alloc, pAllocator, fb);
2915 }
2916
2917 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2918 {
2919 switch (address_mode) {
2920 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2921 return V_008F30_SQ_TEX_WRAP;
2922 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2923 return V_008F30_SQ_TEX_MIRROR;
2924 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2925 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2926 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2927 return V_008F30_SQ_TEX_CLAMP_BORDER;
2928 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2929 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2930 default:
2931 unreachable("illegal tex wrap mode");
2932 break;
2933 }
2934 }
2935
2936 static unsigned
2937 radv_tex_compare(VkCompareOp op)
2938 {
2939 switch (op) {
2940 case VK_COMPARE_OP_NEVER:
2941 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2942 case VK_COMPARE_OP_LESS:
2943 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2944 case VK_COMPARE_OP_EQUAL:
2945 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2946 case VK_COMPARE_OP_LESS_OR_EQUAL:
2947 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2948 case VK_COMPARE_OP_GREATER:
2949 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2950 case VK_COMPARE_OP_NOT_EQUAL:
2951 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2952 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2953 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2954 case VK_COMPARE_OP_ALWAYS:
2955 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2956 default:
2957 unreachable("illegal compare mode");
2958 break;
2959 }
2960 }
2961
2962 static unsigned
2963 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2964 {
2965 switch (filter) {
2966 case VK_FILTER_NEAREST:
2967 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2968 V_008F38_SQ_TEX_XY_FILTER_POINT);
2969 case VK_FILTER_LINEAR:
2970 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2971 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2972 case VK_FILTER_CUBIC_IMG:
2973 default:
2974 fprintf(stderr, "illegal texture filter");
2975 return 0;
2976 }
2977 }
2978
2979 static unsigned
2980 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2981 {
2982 switch (mode) {
2983 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2984 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2985 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2986 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2987 default:
2988 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2989 }
2990 }
2991
2992 static unsigned
2993 radv_tex_bordercolor(VkBorderColor bcolor)
2994 {
2995 switch (bcolor) {
2996 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2997 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2998 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2999 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3000 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3001 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3002 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3003 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3004 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3005 default:
3006 break;
3007 }
3008 return 0;
3009 }
3010
3011 static unsigned
3012 radv_tex_aniso_filter(unsigned filter)
3013 {
3014 if (filter < 2)
3015 return 0;
3016 if (filter < 4)
3017 return 1;
3018 if (filter < 8)
3019 return 2;
3020 if (filter < 16)
3021 return 3;
3022 return 4;
3023 }
3024
3025 static void
3026 radv_init_sampler(struct radv_device *device,
3027 struct radv_sampler *sampler,
3028 const VkSamplerCreateInfo *pCreateInfo)
3029 {
3030 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3031 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3032 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3033 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3034
3035 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3036 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3037 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3038 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3039 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3040 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3041 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3042 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3043 S_008F30_DISABLE_CUBE_WRAP(0) |
3044 S_008F30_COMPAT_MODE(is_vi));
3045 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3046 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3047 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3048 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3049 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3050 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3051 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3052 S_008F38_MIP_POINT_PRECLAMP(0) |
3053 S_008F38_DISABLE_LSB_CEIL(1) |
3054 S_008F38_FILTER_PREC_FIX(1) |
3055 S_008F38_ANISO_OVERRIDE(is_vi));
3056 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3057 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3058 }
3059
3060 VkResult radv_CreateSampler(
3061 VkDevice _device,
3062 const VkSamplerCreateInfo* pCreateInfo,
3063 const VkAllocationCallbacks* pAllocator,
3064 VkSampler* pSampler)
3065 {
3066 RADV_FROM_HANDLE(radv_device, device, _device);
3067 struct radv_sampler *sampler;
3068
3069 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3070
3071 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3072 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3073 if (!sampler)
3074 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3075
3076 radv_init_sampler(device, sampler, pCreateInfo);
3077 *pSampler = radv_sampler_to_handle(sampler);
3078
3079 return VK_SUCCESS;
3080 }
3081
3082 void radv_DestroySampler(
3083 VkDevice _device,
3084 VkSampler _sampler,
3085 const VkAllocationCallbacks* pAllocator)
3086 {
3087 RADV_FROM_HANDLE(radv_device, device, _device);
3088 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3089
3090 if (!sampler)
3091 return;
3092 vk_free2(&device->alloc, pAllocator, sampler);
3093 }
3094
3095
3096 /* vk_icd.h does not declare this function, so we declare it here to
3097 * suppress Wmissing-prototypes.
3098 */
3099 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3100 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3101
3102 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3103 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3104 {
3105 /* For the full details on loader interface versioning, see
3106 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3107 * What follows is a condensed summary, to help you navigate the large and
3108 * confusing official doc.
3109 *
3110 * - Loader interface v0 is incompatible with later versions. We don't
3111 * support it.
3112 *
3113 * - In loader interface v1:
3114 * - The first ICD entrypoint called by the loader is
3115 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3116 * entrypoint.
3117 * - The ICD must statically expose no other Vulkan symbol unless it is
3118 * linked with -Bsymbolic.
3119 * - Each dispatchable Vulkan handle created by the ICD must be
3120 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3121 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3122 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3123 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3124 * such loader-managed surfaces.
3125 *
3126 * - Loader interface v2 differs from v1 in:
3127 * - The first ICD entrypoint called by the loader is
3128 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3129 * statically expose this entrypoint.
3130 *
3131 * - Loader interface v3 differs from v2 in:
3132 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3133 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3134 * because the loader no longer does so.
3135 */
3136 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3137 return VK_SUCCESS;
3138 }