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radv: Don't underflow non-visible VRAM size.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 {
102 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 {
106 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
107 .specVersion = 1,
108 },
109 };
110
111 static const VkExtensionProperties common_device_extensions[] = {
112 {
113 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
134 .specVersion = 68,
135 },
136 {
137 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 {
161 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
162 .specVersion = 1,
163 },
164 {
165 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
166 .specVersion = 1,
167 },
168 };
169 static const VkExtensionProperties ext_sema_device_extensions[] = {
170 {
171 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
172 .specVersion = 1,
173 },
174 {
175 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
176 .specVersion = 1,
177 },
178 };
179
180 static VkResult
181 radv_extensions_register(struct radv_instance *instance,
182 struct radv_extensions *extensions,
183 const VkExtensionProperties *new_ext,
184 uint32_t num_ext)
185 {
186 size_t new_size;
187 VkExtensionProperties *new_ptr;
188
189 assert(new_ext && num_ext > 0);
190
191 if (!new_ext)
192 return VK_ERROR_INITIALIZATION_FAILED;
193
194 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
195 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
196 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
197
198 /* Old array continues to be valid, update nothing */
199 if (!new_ptr)
200 return VK_ERROR_OUT_OF_HOST_MEMORY;
201
202 memcpy(&new_ptr[extensions->num_ext], new_ext,
203 num_ext * sizeof(VkExtensionProperties));
204 extensions->ext_array = new_ptr;
205 extensions->num_ext += num_ext;
206
207 return VK_SUCCESS;
208 }
209
210 static void
211 radv_extensions_finish(struct radv_instance *instance,
212 struct radv_extensions *extensions)
213 {
214 assert(extensions);
215
216 if (!extensions)
217 radv_loge("Attemted to free invalid extension struct\n");
218
219 if (extensions->ext_array)
220 vk_free(&instance->alloc, extensions->ext_array);
221 }
222
223 static bool
224 is_extension_enabled(const VkExtensionProperties *extensions,
225 size_t num_ext,
226 const char *name)
227 {
228 assert(extensions && name);
229
230 for (uint32_t i = 0; i < num_ext; i++) {
231 if (strcmp(name, extensions[i].extensionName) == 0)
232 return true;
233 }
234
235 return false;
236 }
237
238 static const char *
239 get_chip_name(enum radeon_family family)
240 {
241 switch (family) {
242 case CHIP_TAHITI: return "AMD RADV TAHITI";
243 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
244 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
245 case CHIP_OLAND: return "AMD RADV OLAND";
246 case CHIP_HAINAN: return "AMD RADV HAINAN";
247 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
248 case CHIP_KAVERI: return "AMD RADV KAVERI";
249 case CHIP_KABINI: return "AMD RADV KABINI";
250 case CHIP_HAWAII: return "AMD RADV HAWAII";
251 case CHIP_MULLINS: return "AMD RADV MULLINS";
252 case CHIP_TONGA: return "AMD RADV TONGA";
253 case CHIP_ICELAND: return "AMD RADV ICELAND";
254 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
255 case CHIP_FIJI: return "AMD RADV FIJI";
256 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
257 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
258 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
259 case CHIP_STONEY: return "AMD RADV STONEY";
260 case CHIP_VEGA10: return "AMD RADV VEGA";
261 case CHIP_RAVEN: return "AMD RADV RAVEN";
262 default: return "AMD RADV unknown";
263 }
264 }
265
266 static VkResult
267 radv_physical_device_init(struct radv_physical_device *device,
268 struct radv_instance *instance,
269 drmDevicePtr drm_device)
270 {
271 const char *path = drm_device->nodes[DRM_NODE_RENDER];
272 VkResult result;
273 drmVersionPtr version;
274 int fd;
275
276 fd = open(path, O_RDWR | O_CLOEXEC);
277 if (fd < 0)
278 return VK_ERROR_INCOMPATIBLE_DRIVER;
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
284 "failed to get version %s: %m", path);
285 }
286
287 if (strcmp(version->name, "amdgpu")) {
288 drmFreeVersion(version);
289 close(fd);
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
295 device->instance = instance;
296 assert(strlen(path) < ARRAY_SIZE(device->path));
297 strncpy(device->path, path, ARRAY_SIZE(device->path));
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = VK_ERROR_INCOMPATIBLE_DRIVER;
303 goto fail;
304 }
305
306 device->local_fd = fd;
307 device->ws->query_info(device->ws, &device->rad_info);
308 result = radv_init_wsi(device);
309 if (result != VK_SUCCESS) {
310 device->ws->destroy(device->ws);
311 goto fail;
312 }
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 radv_finish_wsi(device);
316 device->ws->destroy(device->ws);
317 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 result = radv_extensions_register(instance,
323 &device->extensions,
324 common_device_extensions,
325 ARRAY_SIZE(common_device_extensions));
326 if (result != VK_SUCCESS)
327 goto fail;
328
329 if (device->rad_info.has_syncobj) {
330 result = radv_extensions_register(instance,
331 &device->extensions,
332 ext_sema_device_extensions,
333 ARRAY_SIZE(ext_sema_device_extensions));
334 if (result != VK_SUCCESS)
335 goto fail;
336 }
337
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 device->name = get_chip_name(device->rad_info.family);
340
341 radv_get_device_uuid(drm_device, device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
347 }
348
349 return VK_SUCCESS;
350
351 fail:
352 close(fd);
353 return result;
354 }
355
356 static void
357 radv_physical_device_finish(struct radv_physical_device *device)
358 {
359 radv_extensions_finish(device->instance, &device->extensions);
360 radv_finish_wsi(device);
361 device->ws->destroy(device->ws);
362 close(device->local_fd);
363 }
364
365 static void *
366 default_alloc_func(void *pUserData, size_t size, size_t align,
367 VkSystemAllocationScope allocationScope)
368 {
369 return malloc(size);
370 }
371
372 static void *
373 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
374 size_t align, VkSystemAllocationScope allocationScope)
375 {
376 return realloc(pOriginal, size);
377 }
378
379 static void
380 default_free_func(void *pUserData, void *pMemory)
381 {
382 free(pMemory);
383 }
384
385 static const VkAllocationCallbacks default_alloc = {
386 .pUserData = NULL,
387 .pfnAllocation = default_alloc_func,
388 .pfnReallocation = default_realloc_func,
389 .pfnFree = default_free_func,
390 };
391
392 static const struct debug_control radv_debug_options[] = {
393 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
394 {"nodcc", RADV_DEBUG_NO_DCC},
395 {"shaders", RADV_DEBUG_DUMP_SHADERS},
396 {"nocache", RADV_DEBUG_NO_CACHE},
397 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
398 {"nohiz", RADV_DEBUG_NO_HIZ},
399 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
400 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
401 {"allbos", RADV_DEBUG_ALL_BOS},
402 {"noibs", RADV_DEBUG_NO_IBS},
403 {NULL, 0}
404 };
405
406 static const struct debug_control radv_perftest_options[] = {
407 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
408 {"sisched", RADV_PERFTEST_SISCHED},
409 {NULL, 0}
410 };
411
412 VkResult radv_CreateInstance(
413 const VkInstanceCreateInfo* pCreateInfo,
414 const VkAllocationCallbacks* pAllocator,
415 VkInstance* pInstance)
416 {
417 struct radv_instance *instance;
418
419 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
420
421 uint32_t client_version;
422 if (pCreateInfo->pApplicationInfo &&
423 pCreateInfo->pApplicationInfo->apiVersion != 0) {
424 client_version = pCreateInfo->pApplicationInfo->apiVersion;
425 } else {
426 client_version = VK_MAKE_VERSION(1, 0, 0);
427 }
428
429 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
430 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
431 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
432 "Client requested version %d.%d.%d",
433 VK_VERSION_MAJOR(client_version),
434 VK_VERSION_MINOR(client_version),
435 VK_VERSION_PATCH(client_version));
436 }
437
438 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
439 if (!is_extension_enabled(instance_extensions,
440 ARRAY_SIZE(instance_extensions),
441 pCreateInfo->ppEnabledExtensionNames[i]))
442 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
443 }
444
445 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
446 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
447 if (!instance)
448 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
449
450 memset(instance, 0, sizeof(*instance));
451
452 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
453
454 if (pAllocator)
455 instance->alloc = *pAllocator;
456 else
457 instance->alloc = default_alloc;
458
459 instance->apiVersion = client_version;
460 instance->physicalDeviceCount = -1;
461
462 _mesa_locale_init();
463
464 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
465
466 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
467 radv_debug_options);
468
469 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
470 radv_perftest_options);
471
472 *pInstance = radv_instance_to_handle(instance);
473
474 return VK_SUCCESS;
475 }
476
477 void radv_DestroyInstance(
478 VkInstance _instance,
479 const VkAllocationCallbacks* pAllocator)
480 {
481 RADV_FROM_HANDLE(radv_instance, instance, _instance);
482
483 if (!instance)
484 return;
485
486 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
487 radv_physical_device_finish(instance->physicalDevices + i);
488 }
489
490 VG(VALGRIND_DESTROY_MEMPOOL(instance));
491
492 _mesa_locale_fini();
493
494 vk_free(&instance->alloc, instance);
495 }
496
497 static VkResult
498 radv_enumerate_devices(struct radv_instance *instance)
499 {
500 /* TODO: Check for more devices ? */
501 drmDevicePtr devices[8];
502 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
503 int max_devices;
504
505 instance->physicalDeviceCount = 0;
506
507 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
508 if (max_devices < 1)
509 return VK_ERROR_INCOMPATIBLE_DRIVER;
510
511 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
512 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
513 devices[i]->bustype == DRM_BUS_PCI &&
514 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
515
516 result = radv_physical_device_init(instance->physicalDevices +
517 instance->physicalDeviceCount,
518 instance,
519 devices[i]);
520 if (result == VK_SUCCESS)
521 ++instance->physicalDeviceCount;
522 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
523 break;
524 }
525 }
526 drmFreeDevices(devices, max_devices);
527
528 return result;
529 }
530
531 VkResult radv_EnumeratePhysicalDevices(
532 VkInstance _instance,
533 uint32_t* pPhysicalDeviceCount,
534 VkPhysicalDevice* pPhysicalDevices)
535 {
536 RADV_FROM_HANDLE(radv_instance, instance, _instance);
537 VkResult result;
538
539 if (instance->physicalDeviceCount < 0) {
540 result = radv_enumerate_devices(instance);
541 if (result != VK_SUCCESS &&
542 result != VK_ERROR_INCOMPATIBLE_DRIVER)
543 return result;
544 }
545
546 if (!pPhysicalDevices) {
547 *pPhysicalDeviceCount = instance->physicalDeviceCount;
548 } else {
549 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
550 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
551 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
552 }
553
554 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
555 : VK_SUCCESS;
556 }
557
558 void radv_GetPhysicalDeviceFeatures(
559 VkPhysicalDevice physicalDevice,
560 VkPhysicalDeviceFeatures* pFeatures)
561 {
562 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
563 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
564 memset(pFeatures, 0, sizeof(*pFeatures));
565
566 *pFeatures = (VkPhysicalDeviceFeatures) {
567 .robustBufferAccess = true,
568 .fullDrawIndexUint32 = true,
569 .imageCubeArray = true,
570 .independentBlend = true,
571 .geometryShader = !is_gfx9,
572 .tessellationShader = !is_gfx9,
573 .sampleRateShading = true,
574 .dualSrcBlend = true,
575 .logicOp = true,
576 .multiDrawIndirect = true,
577 .drawIndirectFirstInstance = true,
578 .depthClamp = true,
579 .depthBiasClamp = true,
580 .fillModeNonSolid = true,
581 .depthBounds = true,
582 .wideLines = true,
583 .largePoints = true,
584 .alphaToOne = true,
585 .multiViewport = true,
586 .samplerAnisotropy = true,
587 .textureCompressionETC2 = false,
588 .textureCompressionASTC_LDR = false,
589 .textureCompressionBC = true,
590 .occlusionQueryPrecise = true,
591 .pipelineStatisticsQuery = true,
592 .vertexPipelineStoresAndAtomics = true,
593 .fragmentStoresAndAtomics = true,
594 .shaderTessellationAndGeometryPointSize = true,
595 .shaderImageGatherExtended = true,
596 .shaderStorageImageExtendedFormats = true,
597 .shaderStorageImageMultisample = false,
598 .shaderUniformBufferArrayDynamicIndexing = true,
599 .shaderSampledImageArrayDynamicIndexing = true,
600 .shaderStorageBufferArrayDynamicIndexing = true,
601 .shaderStorageImageArrayDynamicIndexing = true,
602 .shaderStorageImageReadWithoutFormat = true,
603 .shaderStorageImageWriteWithoutFormat = true,
604 .shaderClipDistance = true,
605 .shaderCullDistance = true,
606 .shaderFloat64 = true,
607 .shaderInt64 = true,
608 .shaderInt16 = false,
609 .sparseBinding = true,
610 .variableMultisampleRate = true,
611 .inheritedQueries = true,
612 };
613 }
614
615 void radv_GetPhysicalDeviceFeatures2KHR(
616 VkPhysicalDevice physicalDevice,
617 VkPhysicalDeviceFeatures2KHR *pFeatures)
618 {
619 vk_foreach_struct(ext, pFeatures->pNext) {
620 switch (ext->sType) {
621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
622 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
623 features->variablePointersStorageBuffer = true;
624 features->variablePointers = false;
625 break;
626 }
627 default:
628 break;
629 }
630 }
631 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
632 }
633
634 void radv_GetPhysicalDeviceProperties(
635 VkPhysicalDevice physicalDevice,
636 VkPhysicalDeviceProperties* pProperties)
637 {
638 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
639 VkSampleCountFlags sample_counts = 0xf;
640
641 /* make sure that the entire descriptor set is addressable with a signed
642 * 32-bit int. So the sum of all limits scaled by descriptor size has to
643 * be at most 2 GiB. the combined image & samples object count as one of
644 * both. This limit is for the pipeline layout, not for the set layout, but
645 * there is no set limit, so we just set a pipeline limit. I don't think
646 * any app is going to hit this soon. */
647 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
648 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
649 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
650 32 /* sampler, largest when combined with image */ +
651 64 /* sampled image */ +
652 64 /* storage image */);
653
654 VkPhysicalDeviceLimits limits = {
655 .maxImageDimension1D = (1 << 14),
656 .maxImageDimension2D = (1 << 14),
657 .maxImageDimension3D = (1 << 11),
658 .maxImageDimensionCube = (1 << 14),
659 .maxImageArrayLayers = (1 << 11),
660 .maxTexelBufferElements = 128 * 1024 * 1024,
661 .maxUniformBufferRange = UINT32_MAX,
662 .maxStorageBufferRange = UINT32_MAX,
663 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
664 .maxMemoryAllocationCount = UINT32_MAX,
665 .maxSamplerAllocationCount = 64 * 1024,
666 .bufferImageGranularity = 64, /* A cache line */
667 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
668 .maxBoundDescriptorSets = MAX_SETS,
669 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
670 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
671 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
672 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
673 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
674 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
675 .maxPerStageResources = max_descriptor_set_size,
676 .maxDescriptorSetSamplers = max_descriptor_set_size,
677 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
678 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
679 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
680 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
681 .maxDescriptorSetSampledImages = max_descriptor_set_size,
682 .maxDescriptorSetStorageImages = max_descriptor_set_size,
683 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
684 .maxVertexInputAttributes = 32,
685 .maxVertexInputBindings = 32,
686 .maxVertexInputAttributeOffset = 2047,
687 .maxVertexInputBindingStride = 2048,
688 .maxVertexOutputComponents = 128,
689 .maxTessellationGenerationLevel = 64,
690 .maxTessellationPatchSize = 32,
691 .maxTessellationControlPerVertexInputComponents = 128,
692 .maxTessellationControlPerVertexOutputComponents = 128,
693 .maxTessellationControlPerPatchOutputComponents = 120,
694 .maxTessellationControlTotalOutputComponents = 4096,
695 .maxTessellationEvaluationInputComponents = 128,
696 .maxTessellationEvaluationOutputComponents = 128,
697 .maxGeometryShaderInvocations = 127,
698 .maxGeometryInputComponents = 64,
699 .maxGeometryOutputComponents = 128,
700 .maxGeometryOutputVertices = 256,
701 .maxGeometryTotalOutputComponents = 1024,
702 .maxFragmentInputComponents = 128,
703 .maxFragmentOutputAttachments = 8,
704 .maxFragmentDualSrcAttachments = 1,
705 .maxFragmentCombinedOutputResources = 8,
706 .maxComputeSharedMemorySize = 32768,
707 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
708 .maxComputeWorkGroupInvocations = 2048,
709 .maxComputeWorkGroupSize = {
710 2048,
711 2048,
712 2048
713 },
714 .subPixelPrecisionBits = 4 /* FIXME */,
715 .subTexelPrecisionBits = 4 /* FIXME */,
716 .mipmapPrecisionBits = 4 /* FIXME */,
717 .maxDrawIndexedIndexValue = UINT32_MAX,
718 .maxDrawIndirectCount = UINT32_MAX,
719 .maxSamplerLodBias = 16,
720 .maxSamplerAnisotropy = 16,
721 .maxViewports = MAX_VIEWPORTS,
722 .maxViewportDimensions = { (1 << 14), (1 << 14) },
723 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
724 .viewportSubPixelBits = 13, /* We take a float? */
725 .minMemoryMapAlignment = 4096, /* A page */
726 .minTexelBufferOffsetAlignment = 1,
727 .minUniformBufferOffsetAlignment = 4,
728 .minStorageBufferOffsetAlignment = 4,
729 .minTexelOffset = -32,
730 .maxTexelOffset = 31,
731 .minTexelGatherOffset = -32,
732 .maxTexelGatherOffset = 31,
733 .minInterpolationOffset = -2,
734 .maxInterpolationOffset = 2,
735 .subPixelInterpolationOffsetBits = 8,
736 .maxFramebufferWidth = (1 << 14),
737 .maxFramebufferHeight = (1 << 14),
738 .maxFramebufferLayers = (1 << 10),
739 .framebufferColorSampleCounts = sample_counts,
740 .framebufferDepthSampleCounts = sample_counts,
741 .framebufferStencilSampleCounts = sample_counts,
742 .framebufferNoAttachmentsSampleCounts = sample_counts,
743 .maxColorAttachments = MAX_RTS,
744 .sampledImageColorSampleCounts = sample_counts,
745 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
746 .sampledImageDepthSampleCounts = sample_counts,
747 .sampledImageStencilSampleCounts = sample_counts,
748 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
749 .maxSampleMaskWords = 1,
750 .timestampComputeAndGraphics = true,
751 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
752 .maxClipDistances = 8,
753 .maxCullDistances = 8,
754 .maxCombinedClipAndCullDistances = 8,
755 .discreteQueuePriorities = 1,
756 .pointSizeRange = { 0.125, 255.875 },
757 .lineWidthRange = { 0.0, 7.9921875 },
758 .pointSizeGranularity = (1.0 / 8.0),
759 .lineWidthGranularity = (1.0 / 128.0),
760 .strictLines = false, /* FINISHME */
761 .standardSampleLocations = true,
762 .optimalBufferCopyOffsetAlignment = 128,
763 .optimalBufferCopyRowPitchAlignment = 128,
764 .nonCoherentAtomSize = 64,
765 };
766
767 *pProperties = (VkPhysicalDeviceProperties) {
768 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
769 .driverVersion = vk_get_driver_version(),
770 .vendorID = 0x1002,
771 .deviceID = pdevice->rad_info.pci_id,
772 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
773 .limits = limits,
774 .sparseProperties = {0},
775 };
776
777 strcpy(pProperties->deviceName, pdevice->name);
778 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
779 }
780
781 void radv_GetPhysicalDeviceProperties2KHR(
782 VkPhysicalDevice physicalDevice,
783 VkPhysicalDeviceProperties2KHR *pProperties)
784 {
785 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
786 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
787
788 vk_foreach_struct(ext, pProperties->pNext) {
789 switch (ext->sType) {
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
791 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
792 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
793 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
797 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
798 radv_device_get_cache_uuid(0, properties->driverUUID);
799 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
800 properties->deviceLUIDValid = false;
801 break;
802 }
803 default:
804 break;
805 }
806 }
807 }
808
809 static void radv_get_physical_device_queue_family_properties(
810 struct radv_physical_device* pdevice,
811 uint32_t* pCount,
812 VkQueueFamilyProperties** pQueueFamilyProperties)
813 {
814 int num_queue_families = 1;
815 int idx;
816 if (pdevice->rad_info.num_compute_rings > 0 &&
817 pdevice->rad_info.chip_class >= CIK &&
818 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
819 num_queue_families++;
820
821 if (pQueueFamilyProperties == NULL) {
822 *pCount = num_queue_families;
823 return;
824 }
825
826 if (!*pCount)
827 return;
828
829 idx = 0;
830 if (*pCount >= 1) {
831 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
832 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
833 VK_QUEUE_COMPUTE_BIT |
834 VK_QUEUE_TRANSFER_BIT |
835 VK_QUEUE_SPARSE_BINDING_BIT,
836 .queueCount = 1,
837 .timestampValidBits = 64,
838 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
839 };
840 idx++;
841 }
842
843 if (pdevice->rad_info.num_compute_rings > 0 &&
844 pdevice->rad_info.chip_class >= CIK &&
845 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
846 if (*pCount > idx) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_COMPUTE_BIT |
849 VK_QUEUE_TRANSFER_BIT |
850 VK_QUEUE_SPARSE_BINDING_BIT,
851 .queueCount = pdevice->rad_info.num_compute_rings,
852 .timestampValidBits = 64,
853 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
854 };
855 idx++;
856 }
857 }
858 *pCount = idx;
859 }
860
861 void radv_GetPhysicalDeviceQueueFamilyProperties(
862 VkPhysicalDevice physicalDevice,
863 uint32_t* pCount,
864 VkQueueFamilyProperties* pQueueFamilyProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 if (!pQueueFamilyProperties) {
868 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
869 return;
870 }
871 VkQueueFamilyProperties *properties[] = {
872 pQueueFamilyProperties + 0,
873 pQueueFamilyProperties + 1,
874 pQueueFamilyProperties + 2,
875 };
876 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
877 assert(*pCount <= 3);
878 }
879
880 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
881 VkPhysicalDevice physicalDevice,
882 uint32_t* pCount,
883 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 if (!pQueueFamilyProperties) {
887 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
888 return;
889 }
890 VkQueueFamilyProperties *properties[] = {
891 &pQueueFamilyProperties[0].queueFamilyProperties,
892 &pQueueFamilyProperties[1].queueFamilyProperties,
893 &pQueueFamilyProperties[2].queueFamilyProperties,
894 };
895 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
896 assert(*pCount <= 3);
897 }
898
899 void radv_GetPhysicalDeviceMemoryProperties(
900 VkPhysicalDevice physicalDevice,
901 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
902 {
903 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
904
905 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
906
907 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
908 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
909 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
910 .heapIndex = RADV_MEM_HEAP_VRAM,
911 };
912 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
913 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
914 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
915 .heapIndex = RADV_MEM_HEAP_GTT,
916 };
917 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
918 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
919 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
920 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
921 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
922 };
923 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
924 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
925 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
926 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
927 .heapIndex = RADV_MEM_HEAP_GTT,
928 };
929
930 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
931 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
932 physical_device->rad_info.vram_vis_size);
933
934 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
935 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
936 .size = physical_device->rad_info.vram_size -
937 visible_vram_size,
938 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
939 };
940 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
941 .size = visible_vram_size,
942 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
943 };
944 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
945 .size = physical_device->rad_info.gart_size,
946 .flags = 0,
947 };
948 }
949
950 void radv_GetPhysicalDeviceMemoryProperties2KHR(
951 VkPhysicalDevice physicalDevice,
952 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
953 {
954 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
955 &pMemoryProperties->memoryProperties);
956 }
957
958 static int
959 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
960 int queue_family_index, int idx)
961 {
962 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
963 queue->device = device;
964 queue->queue_family_index = queue_family_index;
965 queue->queue_idx = idx;
966
967 queue->hw_ctx = device->ws->ctx_create(device->ws);
968 if (!queue->hw_ctx)
969 return VK_ERROR_OUT_OF_HOST_MEMORY;
970
971 return VK_SUCCESS;
972 }
973
974 static void
975 radv_queue_finish(struct radv_queue *queue)
976 {
977 if (queue->hw_ctx)
978 queue->device->ws->ctx_destroy(queue->hw_ctx);
979
980 if (queue->initial_preamble_cs)
981 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
982 if (queue->continue_preamble_cs)
983 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
984 if (queue->descriptor_bo)
985 queue->device->ws->buffer_destroy(queue->descriptor_bo);
986 if (queue->scratch_bo)
987 queue->device->ws->buffer_destroy(queue->scratch_bo);
988 if (queue->esgs_ring_bo)
989 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
990 if (queue->gsvs_ring_bo)
991 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
992 if (queue->tess_factor_ring_bo)
993 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
994 if (queue->tess_offchip_ring_bo)
995 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
996 if (queue->compute_scratch_bo)
997 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
998 }
999
1000 static void
1001 radv_device_init_gs_info(struct radv_device *device)
1002 {
1003 switch (device->physical_device->rad_info.family) {
1004 case CHIP_OLAND:
1005 case CHIP_HAINAN:
1006 case CHIP_KAVERI:
1007 case CHIP_KABINI:
1008 case CHIP_MULLINS:
1009 case CHIP_ICELAND:
1010 case CHIP_CARRIZO:
1011 case CHIP_STONEY:
1012 device->gs_table_depth = 16;
1013 return;
1014 case CHIP_TAHITI:
1015 case CHIP_PITCAIRN:
1016 case CHIP_VERDE:
1017 case CHIP_BONAIRE:
1018 case CHIP_HAWAII:
1019 case CHIP_TONGA:
1020 case CHIP_FIJI:
1021 case CHIP_POLARIS10:
1022 case CHIP_POLARIS11:
1023 case CHIP_POLARIS12:
1024 case CHIP_VEGA10:
1025 case CHIP_RAVEN:
1026 device->gs_table_depth = 32;
1027 return;
1028 default:
1029 unreachable("unknown GPU");
1030 }
1031 }
1032
1033 VkResult radv_CreateDevice(
1034 VkPhysicalDevice physicalDevice,
1035 const VkDeviceCreateInfo* pCreateInfo,
1036 const VkAllocationCallbacks* pAllocator,
1037 VkDevice* pDevice)
1038 {
1039 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1040 VkResult result;
1041 struct radv_device *device;
1042
1043 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1044 if (!is_extension_enabled(physical_device->extensions.ext_array,
1045 physical_device->extensions.num_ext,
1046 pCreateInfo->ppEnabledExtensionNames[i]))
1047 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1048 }
1049
1050 /* Check enabled features */
1051 if (pCreateInfo->pEnabledFeatures) {
1052 VkPhysicalDeviceFeatures supported_features;
1053 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1054 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1055 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1056 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1057 for (uint32_t i = 0; i < num_features; i++) {
1058 if (enabled_feature[i] && !supported_feature[i])
1059 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1060 }
1061 }
1062
1063 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1064 sizeof(*device), 8,
1065 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1066 if (!device)
1067 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1068
1069 memset(device, 0, sizeof(*device));
1070
1071 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1072 device->instance = physical_device->instance;
1073 device->physical_device = physical_device;
1074
1075 device->debug_flags = device->instance->debug_flags;
1076
1077 device->ws = physical_device->ws;
1078 if (pAllocator)
1079 device->alloc = *pAllocator;
1080 else
1081 device->alloc = physical_device->instance->alloc;
1082
1083 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1084 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1085 uint32_t qfi = queue_create->queueFamilyIndex;
1086
1087 device->queues[qfi] = vk_alloc(&device->alloc,
1088 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1089 if (!device->queues[qfi]) {
1090 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1091 goto fail;
1092 }
1093
1094 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1095
1096 device->queue_count[qfi] = queue_create->queueCount;
1097
1098 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1099 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1100 if (result != VK_SUCCESS)
1101 goto fail;
1102 }
1103 }
1104
1105 #if HAVE_LLVM < 0x0400
1106 device->llvm_supports_spill = false;
1107 #else
1108 device->llvm_supports_spill = true;
1109 #endif
1110
1111 /* The maximum number of scratch waves. Scratch space isn't divided
1112 * evenly between CUs. The number is only a function of the number of CUs.
1113 * We can decrease the constant to decrease the scratch buffer size.
1114 *
1115 * sctx->scratch_waves must be >= the maximum posible size of
1116 * 1 threadgroup, so that the hw doesn't hang from being unable
1117 * to start any.
1118 *
1119 * The recommended value is 4 per CU at most. Higher numbers don't
1120 * bring much benefit, but they still occupy chip resources (think
1121 * async compute). I've seen ~2% performance difference between 4 and 32.
1122 */
1123 uint32_t max_threads_per_block = 2048;
1124 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1125 max_threads_per_block / 64);
1126
1127 radv_device_init_gs_info(device);
1128
1129 device->tess_offchip_block_dw_size =
1130 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1131 device->has_distributed_tess =
1132 device->physical_device->rad_info.chip_class >= VI &&
1133 device->physical_device->rad_info.max_se >= 2;
1134
1135 result = radv_device_init_meta(device);
1136 if (result != VK_SUCCESS)
1137 goto fail;
1138
1139 radv_device_init_msaa(device);
1140
1141 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1142 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1143 switch (family) {
1144 case RADV_QUEUE_GENERAL:
1145 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1146 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1147 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1148 break;
1149 case RADV_QUEUE_COMPUTE:
1150 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1151 radeon_emit(device->empty_cs[family], 0);
1152 break;
1153 }
1154 device->ws->cs_finalize(device->empty_cs[family]);
1155
1156 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1157 switch (family) {
1158 case RADV_QUEUE_GENERAL:
1159 case RADV_QUEUE_COMPUTE:
1160 si_cs_emit_cache_flush(device->flush_cs[family],
1161 false,
1162 device->physical_device->rad_info.chip_class,
1163 NULL, 0,
1164 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1165 RADV_CMD_FLAG_INV_ICACHE |
1166 RADV_CMD_FLAG_INV_SMEM_L1 |
1167 RADV_CMD_FLAG_INV_VMEM_L1 |
1168 RADV_CMD_FLAG_INV_GLOBAL_L2);
1169 break;
1170 }
1171 device->ws->cs_finalize(device->flush_cs[family]);
1172
1173 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1174 switch (family) {
1175 case RADV_QUEUE_GENERAL:
1176 case RADV_QUEUE_COMPUTE:
1177 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1178 false,
1179 device->physical_device->rad_info.chip_class,
1180 NULL, 0,
1181 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1182 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1183 RADV_CMD_FLAG_INV_ICACHE |
1184 RADV_CMD_FLAG_INV_SMEM_L1 |
1185 RADV_CMD_FLAG_INV_VMEM_L1 |
1186 RADV_CMD_FLAG_INV_GLOBAL_L2);
1187 break;
1188 }
1189 device->ws->cs_finalize(device->flush_shader_cs[family]);
1190 }
1191
1192 if (getenv("RADV_TRACE_FILE")) {
1193 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1194 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1195 if (!device->trace_bo)
1196 goto fail;
1197
1198 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1199 if (!device->trace_id_ptr)
1200 goto fail;
1201 }
1202
1203 if (device->physical_device->rad_info.chip_class >= CIK)
1204 cik_create_gfx_config(device);
1205
1206 VkPipelineCacheCreateInfo ci;
1207 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1208 ci.pNext = NULL;
1209 ci.flags = 0;
1210 ci.pInitialData = NULL;
1211 ci.initialDataSize = 0;
1212 VkPipelineCache pc;
1213 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1214 &ci, NULL, &pc);
1215 if (result != VK_SUCCESS)
1216 goto fail;
1217
1218 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1219
1220 *pDevice = radv_device_to_handle(device);
1221 return VK_SUCCESS;
1222
1223 fail:
1224 if (device->trace_bo)
1225 device->ws->buffer_destroy(device->trace_bo);
1226
1227 if (device->gfx_init)
1228 device->ws->buffer_destroy(device->gfx_init);
1229
1230 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1231 for (unsigned q = 0; q < device->queue_count[i]; q++)
1232 radv_queue_finish(&device->queues[i][q]);
1233 if (device->queue_count[i])
1234 vk_free(&device->alloc, device->queues[i]);
1235 }
1236
1237 vk_free(&device->alloc, device);
1238 return result;
1239 }
1240
1241 void radv_DestroyDevice(
1242 VkDevice _device,
1243 const VkAllocationCallbacks* pAllocator)
1244 {
1245 RADV_FROM_HANDLE(radv_device, device, _device);
1246
1247 if (!device)
1248 return;
1249
1250 if (device->trace_bo)
1251 device->ws->buffer_destroy(device->trace_bo);
1252
1253 if (device->gfx_init)
1254 device->ws->buffer_destroy(device->gfx_init);
1255
1256 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1257 for (unsigned q = 0; q < device->queue_count[i]; q++)
1258 radv_queue_finish(&device->queues[i][q]);
1259 if (device->queue_count[i])
1260 vk_free(&device->alloc, device->queues[i]);
1261 if (device->empty_cs[i])
1262 device->ws->cs_destroy(device->empty_cs[i]);
1263 if (device->flush_cs[i])
1264 device->ws->cs_destroy(device->flush_cs[i]);
1265 if (device->flush_shader_cs[i])
1266 device->ws->cs_destroy(device->flush_shader_cs[i]);
1267 }
1268 radv_device_finish_meta(device);
1269
1270 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1271 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1272
1273 vk_free(&device->alloc, device);
1274 }
1275
1276 VkResult radv_EnumerateInstanceExtensionProperties(
1277 const char* pLayerName,
1278 uint32_t* pPropertyCount,
1279 VkExtensionProperties* pProperties)
1280 {
1281 if (pProperties == NULL) {
1282 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1283 return VK_SUCCESS;
1284 }
1285
1286 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1287 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1288
1289 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1290 return VK_INCOMPLETE;
1291
1292 return VK_SUCCESS;
1293 }
1294
1295 VkResult radv_EnumerateDeviceExtensionProperties(
1296 VkPhysicalDevice physicalDevice,
1297 const char* pLayerName,
1298 uint32_t* pPropertyCount,
1299 VkExtensionProperties* pProperties)
1300 {
1301 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1302
1303 if (pProperties == NULL) {
1304 *pPropertyCount = pdevice->extensions.num_ext;
1305 return VK_SUCCESS;
1306 }
1307
1308 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1309 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1310
1311 if (*pPropertyCount < pdevice->extensions.num_ext)
1312 return VK_INCOMPLETE;
1313
1314 return VK_SUCCESS;
1315 }
1316
1317 VkResult radv_EnumerateInstanceLayerProperties(
1318 uint32_t* pPropertyCount,
1319 VkLayerProperties* pProperties)
1320 {
1321 if (pProperties == NULL) {
1322 *pPropertyCount = 0;
1323 return VK_SUCCESS;
1324 }
1325
1326 /* None supported at this time */
1327 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1328 }
1329
1330 VkResult radv_EnumerateDeviceLayerProperties(
1331 VkPhysicalDevice physicalDevice,
1332 uint32_t* pPropertyCount,
1333 VkLayerProperties* pProperties)
1334 {
1335 if (pProperties == NULL) {
1336 *pPropertyCount = 0;
1337 return VK_SUCCESS;
1338 }
1339
1340 /* None supported at this time */
1341 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1342 }
1343
1344 void radv_GetDeviceQueue(
1345 VkDevice _device,
1346 uint32_t queueFamilyIndex,
1347 uint32_t queueIndex,
1348 VkQueue* pQueue)
1349 {
1350 RADV_FROM_HANDLE(radv_device, device, _device);
1351
1352 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1353 }
1354
1355 static void radv_dump_trace(struct radv_device *device,
1356 struct radeon_winsys_cs *cs)
1357 {
1358 const char *filename = getenv("RADV_TRACE_FILE");
1359 FILE *f = fopen(filename, "w");
1360 if (!f) {
1361 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1362 return;
1363 }
1364
1365 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1366 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1367 fclose(f);
1368 }
1369
1370 static void
1371 fill_geom_tess_rings(struct radv_queue *queue,
1372 uint32_t *map,
1373 bool add_sample_positions,
1374 uint32_t esgs_ring_size,
1375 struct radeon_winsys_bo *esgs_ring_bo,
1376 uint32_t gsvs_ring_size,
1377 struct radeon_winsys_bo *gsvs_ring_bo,
1378 uint32_t tess_factor_ring_size,
1379 struct radeon_winsys_bo *tess_factor_ring_bo,
1380 uint32_t tess_offchip_ring_size,
1381 struct radeon_winsys_bo *tess_offchip_ring_bo)
1382 {
1383 uint64_t esgs_va = 0, gsvs_va = 0;
1384 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1385 uint32_t *desc = &map[4];
1386
1387 if (esgs_ring_bo)
1388 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1389 if (gsvs_ring_bo)
1390 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1391 if (tess_factor_ring_bo)
1392 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1393 if (tess_offchip_ring_bo)
1394 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1395
1396 /* stride 0, num records - size, add tid, swizzle, elsize4,
1397 index stride 64 */
1398 desc[0] = esgs_va;
1399 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1400 S_008F04_STRIDE(0) |
1401 S_008F04_SWIZZLE_ENABLE(true);
1402 desc[2] = esgs_ring_size;
1403 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1404 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1405 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1406 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1407 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1408 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1409 S_008F0C_ELEMENT_SIZE(1) |
1410 S_008F0C_INDEX_STRIDE(3) |
1411 S_008F0C_ADD_TID_ENABLE(true);
1412
1413 desc += 4;
1414 /* GS entry for ES->GS ring */
1415 /* stride 0, num records - size, elsize0,
1416 index stride 0 */
1417 desc[0] = esgs_va;
1418 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1419 S_008F04_STRIDE(0) |
1420 S_008F04_SWIZZLE_ENABLE(false);
1421 desc[2] = esgs_ring_size;
1422 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1423 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1424 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1425 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1426 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1427 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1428 S_008F0C_ELEMENT_SIZE(0) |
1429 S_008F0C_INDEX_STRIDE(0) |
1430 S_008F0C_ADD_TID_ENABLE(false);
1431
1432 desc += 4;
1433 /* VS entry for GS->VS ring */
1434 /* stride 0, num records - size, elsize0,
1435 index stride 0 */
1436 desc[0] = gsvs_va;
1437 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1438 S_008F04_STRIDE(0) |
1439 S_008F04_SWIZZLE_ENABLE(false);
1440 desc[2] = gsvs_ring_size;
1441 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1442 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1443 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1444 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1445 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1446 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1447 S_008F0C_ELEMENT_SIZE(0) |
1448 S_008F0C_INDEX_STRIDE(0) |
1449 S_008F0C_ADD_TID_ENABLE(false);
1450 desc += 4;
1451
1452 /* stride gsvs_itemsize, num records 64
1453 elsize 4, index stride 16 */
1454 /* shader will patch stride and desc[2] */
1455 desc[0] = gsvs_va;
1456 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1457 S_008F04_STRIDE(0) |
1458 S_008F04_SWIZZLE_ENABLE(true);
1459 desc[2] = 0;
1460 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1461 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1462 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1463 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1464 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1465 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1466 S_008F0C_ELEMENT_SIZE(1) |
1467 S_008F0C_INDEX_STRIDE(1) |
1468 S_008F0C_ADD_TID_ENABLE(true);
1469 desc += 4;
1470
1471 desc[0] = tess_factor_va;
1472 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1473 S_008F04_STRIDE(0) |
1474 S_008F04_SWIZZLE_ENABLE(false);
1475 desc[2] = tess_factor_ring_size;
1476 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1477 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1478 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1479 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1480 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1481 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1482 S_008F0C_ELEMENT_SIZE(0) |
1483 S_008F0C_INDEX_STRIDE(0) |
1484 S_008F0C_ADD_TID_ENABLE(false);
1485 desc += 4;
1486
1487 desc[0] = tess_offchip_va;
1488 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1489 S_008F04_STRIDE(0) |
1490 S_008F04_SWIZZLE_ENABLE(false);
1491 desc[2] = tess_offchip_ring_size;
1492 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1493 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1494 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1495 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1496 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1497 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1498 S_008F0C_ELEMENT_SIZE(0) |
1499 S_008F0C_INDEX_STRIDE(0) |
1500 S_008F0C_ADD_TID_ENABLE(false);
1501 desc += 4;
1502
1503 /* add sample positions after all rings */
1504 memcpy(desc, queue->device->sample_locations_1x, 8);
1505 desc += 2;
1506 memcpy(desc, queue->device->sample_locations_2x, 16);
1507 desc += 4;
1508 memcpy(desc, queue->device->sample_locations_4x, 32);
1509 desc += 8;
1510 memcpy(desc, queue->device->sample_locations_8x, 64);
1511 desc += 16;
1512 memcpy(desc, queue->device->sample_locations_16x, 128);
1513 }
1514
1515 static unsigned
1516 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1517 {
1518 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1519 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1520 device->physical_device->rad_info.family != CHIP_STONEY;
1521 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1522 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1523 device->physical_device->rad_info.max_se;
1524 unsigned offchip_granularity;
1525 unsigned hs_offchip_param;
1526 switch (device->tess_offchip_block_dw_size) {
1527 default:
1528 assert(0);
1529 /* fall through */
1530 case 8192:
1531 offchip_granularity = V_03093C_X_8K_DWORDS;
1532 break;
1533 case 4096:
1534 offchip_granularity = V_03093C_X_4K_DWORDS;
1535 break;
1536 }
1537
1538 switch (device->physical_device->rad_info.chip_class) {
1539 case SI:
1540 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1541 break;
1542 case CIK:
1543 case VI:
1544 case GFX9:
1545 default:
1546 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1547 break;
1548 }
1549
1550 *max_offchip_buffers_p = max_offchip_buffers;
1551 if (device->physical_device->rad_info.chip_class >= CIK) {
1552 if (device->physical_device->rad_info.chip_class >= VI)
1553 --max_offchip_buffers;
1554 hs_offchip_param =
1555 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1556 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1557 } else {
1558 hs_offchip_param =
1559 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1560 }
1561 return hs_offchip_param;
1562 }
1563
1564 static VkResult
1565 radv_get_preamble_cs(struct radv_queue *queue,
1566 uint32_t scratch_size,
1567 uint32_t compute_scratch_size,
1568 uint32_t esgs_ring_size,
1569 uint32_t gsvs_ring_size,
1570 bool needs_tess_rings,
1571 bool needs_sample_positions,
1572 struct radeon_winsys_cs **initial_preamble_cs,
1573 struct radeon_winsys_cs **continue_preamble_cs)
1574 {
1575 struct radeon_winsys_bo *scratch_bo = NULL;
1576 struct radeon_winsys_bo *descriptor_bo = NULL;
1577 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1578 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1579 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1580 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1581 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1582 struct radeon_winsys_cs *dest_cs[2] = {0};
1583 bool add_tess_rings = false, add_sample_positions = false;
1584 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1585 unsigned max_offchip_buffers;
1586 unsigned hs_offchip_param = 0;
1587 if (!queue->has_tess_rings) {
1588 if (needs_tess_rings)
1589 add_tess_rings = true;
1590 }
1591 if (!queue->has_sample_positions) {
1592 if (needs_sample_positions)
1593 add_sample_positions = true;
1594 }
1595 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1596 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1597 &max_offchip_buffers);
1598 tess_offchip_ring_size = max_offchip_buffers *
1599 queue->device->tess_offchip_block_dw_size * 4;
1600
1601 if (scratch_size <= queue->scratch_size &&
1602 compute_scratch_size <= queue->compute_scratch_size &&
1603 esgs_ring_size <= queue->esgs_ring_size &&
1604 gsvs_ring_size <= queue->gsvs_ring_size &&
1605 !add_tess_rings && !add_sample_positions &&
1606 queue->initial_preamble_cs) {
1607 *initial_preamble_cs = queue->initial_preamble_cs;
1608 *continue_preamble_cs = queue->continue_preamble_cs;
1609 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1610 *continue_preamble_cs = NULL;
1611 return VK_SUCCESS;
1612 }
1613
1614 if (scratch_size > queue->scratch_size) {
1615 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1616 scratch_size,
1617 4096,
1618 RADEON_DOMAIN_VRAM,
1619 RADEON_FLAG_NO_CPU_ACCESS);
1620 if (!scratch_bo)
1621 goto fail;
1622 } else
1623 scratch_bo = queue->scratch_bo;
1624
1625 if (compute_scratch_size > queue->compute_scratch_size) {
1626 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1627 compute_scratch_size,
1628 4096,
1629 RADEON_DOMAIN_VRAM,
1630 RADEON_FLAG_NO_CPU_ACCESS);
1631 if (!compute_scratch_bo)
1632 goto fail;
1633
1634 } else
1635 compute_scratch_bo = queue->compute_scratch_bo;
1636
1637 if (esgs_ring_size > queue->esgs_ring_size) {
1638 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1639 esgs_ring_size,
1640 4096,
1641 RADEON_DOMAIN_VRAM,
1642 RADEON_FLAG_NO_CPU_ACCESS);
1643 if (!esgs_ring_bo)
1644 goto fail;
1645 } else {
1646 esgs_ring_bo = queue->esgs_ring_bo;
1647 esgs_ring_size = queue->esgs_ring_size;
1648 }
1649
1650 if (gsvs_ring_size > queue->gsvs_ring_size) {
1651 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1652 gsvs_ring_size,
1653 4096,
1654 RADEON_DOMAIN_VRAM,
1655 RADEON_FLAG_NO_CPU_ACCESS);
1656 if (!gsvs_ring_bo)
1657 goto fail;
1658 } else {
1659 gsvs_ring_bo = queue->gsvs_ring_bo;
1660 gsvs_ring_size = queue->gsvs_ring_size;
1661 }
1662
1663 if (add_tess_rings) {
1664 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1665 tess_factor_ring_size,
1666 256,
1667 RADEON_DOMAIN_VRAM,
1668 RADEON_FLAG_NO_CPU_ACCESS);
1669 if (!tess_factor_ring_bo)
1670 goto fail;
1671 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1672 tess_offchip_ring_size,
1673 256,
1674 RADEON_DOMAIN_VRAM,
1675 RADEON_FLAG_NO_CPU_ACCESS);
1676 if (!tess_offchip_ring_bo)
1677 goto fail;
1678 } else {
1679 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1680 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1681 }
1682
1683 if (scratch_bo != queue->scratch_bo ||
1684 esgs_ring_bo != queue->esgs_ring_bo ||
1685 gsvs_ring_bo != queue->gsvs_ring_bo ||
1686 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1687 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1688 uint32_t size = 0;
1689 if (gsvs_ring_bo || esgs_ring_bo ||
1690 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1691 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1692 if (add_sample_positions)
1693 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1694 }
1695 else if (scratch_bo)
1696 size = 8; /* 2 dword */
1697
1698 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1699 size,
1700 4096,
1701 RADEON_DOMAIN_VRAM,
1702 RADEON_FLAG_CPU_ACCESS);
1703 if (!descriptor_bo)
1704 goto fail;
1705 } else
1706 descriptor_bo = queue->descriptor_bo;
1707
1708 for(int i = 0; i < 2; ++i) {
1709 struct radeon_winsys_cs *cs = NULL;
1710 cs = queue->device->ws->cs_create(queue->device->ws,
1711 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1712 if (!cs)
1713 goto fail;
1714
1715 dest_cs[i] = cs;
1716
1717 if (scratch_bo)
1718 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1719
1720 if (esgs_ring_bo)
1721 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1722
1723 if (gsvs_ring_bo)
1724 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1725
1726 if (tess_factor_ring_bo)
1727 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1728
1729 if (tess_offchip_ring_bo)
1730 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1731
1732 if (descriptor_bo)
1733 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1734
1735 if (descriptor_bo != queue->descriptor_bo) {
1736 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1737
1738 if (scratch_bo) {
1739 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1740 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1741 S_008F04_SWIZZLE_ENABLE(1);
1742 map[0] = scratch_va;
1743 map[1] = rsrc1;
1744 }
1745
1746 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1747 add_sample_positions)
1748 fill_geom_tess_rings(queue, map, add_sample_positions,
1749 esgs_ring_size, esgs_ring_bo,
1750 gsvs_ring_size, gsvs_ring_bo,
1751 tess_factor_ring_size, tess_factor_ring_bo,
1752 tess_offchip_ring_size, tess_offchip_ring_bo);
1753
1754 queue->device->ws->buffer_unmap(descriptor_bo);
1755 }
1756
1757 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1759 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1760 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1761 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1762 }
1763
1764 if (esgs_ring_bo || gsvs_ring_bo) {
1765 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1766 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1767 radeon_emit(cs, esgs_ring_size >> 8);
1768 radeon_emit(cs, gsvs_ring_size >> 8);
1769 } else {
1770 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1771 radeon_emit(cs, esgs_ring_size >> 8);
1772 radeon_emit(cs, gsvs_ring_size >> 8);
1773 }
1774 }
1775
1776 if (tess_factor_ring_bo) {
1777 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1778 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1779 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1780 S_030938_SIZE(tess_factor_ring_size / 4));
1781 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1782 tf_va >> 8);
1783 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1784 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1785 tf_va >> 40);
1786 }
1787 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1788 } else {
1789 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1790 S_008988_SIZE(tess_factor_ring_size / 4));
1791 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1792 tf_va >> 8);
1793 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1794 hs_offchip_param);
1795 }
1796 }
1797
1798 if (descriptor_bo) {
1799 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1800 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1801 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1802 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1803 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1804 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1805
1806 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1807
1808 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1809 radeon_set_sh_reg_seq(cs, regs[i], 2);
1810 radeon_emit(cs, va);
1811 radeon_emit(cs, va >> 32);
1812 }
1813 }
1814
1815 if (compute_scratch_bo) {
1816 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1817 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1818 S_008F04_SWIZZLE_ENABLE(1);
1819
1820 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1821
1822 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1823 radeon_emit(cs, scratch_va);
1824 radeon_emit(cs, rsrc1);
1825 }
1826
1827 if (!i) {
1828 si_cs_emit_cache_flush(cs,
1829 false,
1830 queue->device->physical_device->rad_info.chip_class,
1831 NULL, 0,
1832 queue->queue_family_index == RING_COMPUTE &&
1833 queue->device->physical_device->rad_info.chip_class >= CIK,
1834 RADV_CMD_FLAG_INV_ICACHE |
1835 RADV_CMD_FLAG_INV_SMEM_L1 |
1836 RADV_CMD_FLAG_INV_VMEM_L1 |
1837 RADV_CMD_FLAG_INV_GLOBAL_L2);
1838 }
1839
1840 if (!queue->device->ws->cs_finalize(cs))
1841 goto fail;
1842 }
1843
1844 if (queue->initial_preamble_cs)
1845 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1846
1847 if (queue->continue_preamble_cs)
1848 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1849
1850 queue->initial_preamble_cs = dest_cs[0];
1851 queue->continue_preamble_cs = dest_cs[1];
1852
1853 if (scratch_bo != queue->scratch_bo) {
1854 if (queue->scratch_bo)
1855 queue->device->ws->buffer_destroy(queue->scratch_bo);
1856 queue->scratch_bo = scratch_bo;
1857 queue->scratch_size = scratch_size;
1858 }
1859
1860 if (compute_scratch_bo != queue->compute_scratch_bo) {
1861 if (queue->compute_scratch_bo)
1862 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1863 queue->compute_scratch_bo = compute_scratch_bo;
1864 queue->compute_scratch_size = compute_scratch_size;
1865 }
1866
1867 if (esgs_ring_bo != queue->esgs_ring_bo) {
1868 if (queue->esgs_ring_bo)
1869 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1870 queue->esgs_ring_bo = esgs_ring_bo;
1871 queue->esgs_ring_size = esgs_ring_size;
1872 }
1873
1874 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1875 if (queue->gsvs_ring_bo)
1876 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1877 queue->gsvs_ring_bo = gsvs_ring_bo;
1878 queue->gsvs_ring_size = gsvs_ring_size;
1879 }
1880
1881 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1882 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1883 }
1884
1885 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1886 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1887 queue->has_tess_rings = true;
1888 }
1889
1890 if (descriptor_bo != queue->descriptor_bo) {
1891 if (queue->descriptor_bo)
1892 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1893
1894 queue->descriptor_bo = descriptor_bo;
1895 }
1896
1897 if (add_sample_positions)
1898 queue->has_sample_positions = true;
1899
1900 *initial_preamble_cs = queue->initial_preamble_cs;
1901 *continue_preamble_cs = queue->continue_preamble_cs;
1902 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1903 *continue_preamble_cs = NULL;
1904 return VK_SUCCESS;
1905 fail:
1906 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1907 if (dest_cs[i])
1908 queue->device->ws->cs_destroy(dest_cs[i]);
1909 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1910 queue->device->ws->buffer_destroy(descriptor_bo);
1911 if (scratch_bo && scratch_bo != queue->scratch_bo)
1912 queue->device->ws->buffer_destroy(scratch_bo);
1913 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1914 queue->device->ws->buffer_destroy(compute_scratch_bo);
1915 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1916 queue->device->ws->buffer_destroy(esgs_ring_bo);
1917 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1918 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1919 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1920 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1921 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1922 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1923 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1924 }
1925
1926 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1927 int num_sems,
1928 const VkSemaphore *sems,
1929 bool reset_temp)
1930 {
1931 int syncobj_idx = 0, sem_idx = 0;
1932
1933 if (num_sems == 0)
1934 return VK_SUCCESS;
1935 for (uint32_t i = 0; i < num_sems; i++) {
1936 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1937
1938 if (sem->temp_syncobj || sem->syncobj)
1939 counts->syncobj_count++;
1940 else
1941 counts->sem_count++;
1942 }
1943
1944 if (counts->syncobj_count) {
1945 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1946 if (!counts->syncobj)
1947 return VK_ERROR_OUT_OF_HOST_MEMORY;
1948 }
1949
1950 if (counts->sem_count) {
1951 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1952 if (!counts->sem) {
1953 free(counts->syncobj);
1954 return VK_ERROR_OUT_OF_HOST_MEMORY;
1955 }
1956 }
1957
1958 for (uint32_t i = 0; i < num_sems; i++) {
1959 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1960
1961 if (sem->temp_syncobj) {
1962 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1963 if (reset_temp) {
1964 /* after we wait on a temp import - drop it */
1965 sem->temp_syncobj = 0;
1966 }
1967 }
1968 else if (sem->syncobj)
1969 counts->syncobj[syncobj_idx++] = sem->syncobj;
1970 else {
1971 assert(sem->sem);
1972 counts->sem[sem_idx++] = sem->sem;
1973 }
1974 }
1975
1976 return VK_SUCCESS;
1977 }
1978
1979 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1980 {
1981 free(sem_info->wait.syncobj);
1982 free(sem_info->wait.sem);
1983 free(sem_info->signal.syncobj);
1984 free(sem_info->signal.sem);
1985 }
1986
1987 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1988 int num_wait_sems,
1989 const VkSemaphore *wait_sems,
1990 int num_signal_sems,
1991 const VkSemaphore *signal_sems)
1992 {
1993 VkResult ret;
1994 memset(sem_info, 0, sizeof(*sem_info));
1995
1996 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1997 if (ret)
1998 return ret;
1999 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2000 if (ret)
2001 radv_free_sem_info(sem_info);
2002
2003 /* caller can override these */
2004 sem_info->cs_emit_wait = true;
2005 sem_info->cs_emit_signal = true;
2006 return ret;
2007 }
2008
2009 VkResult radv_QueueSubmit(
2010 VkQueue _queue,
2011 uint32_t submitCount,
2012 const VkSubmitInfo* pSubmits,
2013 VkFence _fence)
2014 {
2015 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2016 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2017 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2018 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2019 int ret;
2020 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2021 uint32_t scratch_size = 0;
2022 uint32_t compute_scratch_size = 0;
2023 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2024 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
2025 VkResult result;
2026 bool fence_emitted = false;
2027 bool tess_rings_needed = false;
2028 bool sample_positions_needed = false;
2029
2030 /* Do this first so failing to allocate scratch buffers can't result in
2031 * partially executed submissions. */
2032 for (uint32_t i = 0; i < submitCount; i++) {
2033 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2034 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2035 pSubmits[i].pCommandBuffers[j]);
2036
2037 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2038 compute_scratch_size = MAX2(compute_scratch_size,
2039 cmd_buffer->compute_scratch_size_needed);
2040 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2041 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2042 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2043 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2044 }
2045 }
2046
2047 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2048 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2049 sample_positions_needed,
2050 &initial_preamble_cs, &continue_preamble_cs);
2051 if (result != VK_SUCCESS)
2052 return result;
2053
2054 for (uint32_t i = 0; i < submitCount; i++) {
2055 struct radeon_winsys_cs **cs_array;
2056 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2057 bool can_patch = !do_flush;
2058 uint32_t advance;
2059 struct radv_winsys_sem_info sem_info;
2060
2061 result = radv_alloc_sem_info(&sem_info,
2062 pSubmits[i].waitSemaphoreCount,
2063 pSubmits[i].pWaitSemaphores,
2064 pSubmits[i].signalSemaphoreCount,
2065 pSubmits[i].pSignalSemaphores);
2066 if (result != VK_SUCCESS)
2067 return result;
2068
2069 if (!pSubmits[i].commandBufferCount) {
2070 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2071 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2072 &queue->device->empty_cs[queue->queue_family_index],
2073 1, NULL, NULL,
2074 &sem_info,
2075 false, base_fence);
2076 if (ret) {
2077 radv_loge("failed to submit CS %d\n", i);
2078 abort();
2079 }
2080 fence_emitted = true;
2081 }
2082 radv_free_sem_info(&sem_info);
2083 continue;
2084 }
2085
2086 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2087 (pSubmits[i].commandBufferCount + do_flush));
2088
2089 if(do_flush)
2090 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
2091 queue->device->flush_shader_cs[queue->queue_family_index] :
2092 queue->device->flush_cs[queue->queue_family_index];
2093
2094 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2096 pSubmits[i].pCommandBuffers[j]);
2097 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2098
2099 cs_array[j + do_flush] = cmd_buffer->cs;
2100 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2101 can_patch = false;
2102 }
2103
2104 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
2105 advance = MIN2(max_cs_submission,
2106 pSubmits[i].commandBufferCount + do_flush - j);
2107
2108 if (queue->device->trace_bo)
2109 *queue->device->trace_id_ptr = 0;
2110
2111 sem_info.cs_emit_wait = j == 0;
2112 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount + do_flush;
2113
2114 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2115 advance, initial_preamble_cs, continue_preamble_cs,
2116 &sem_info,
2117 can_patch, base_fence);
2118
2119 if (ret) {
2120 radv_loge("failed to submit CS %d\n", i);
2121 abort();
2122 }
2123 fence_emitted = true;
2124 if (queue->device->trace_bo) {
2125 bool success = queue->device->ws->ctx_wait_idle(
2126 queue->hw_ctx,
2127 radv_queue_family_to_ring(
2128 queue->queue_family_index),
2129 queue->queue_idx);
2130
2131 if (!success) { /* Hang */
2132 radv_dump_trace(queue->device, cs_array[j]);
2133 abort();
2134 }
2135 }
2136 }
2137
2138 radv_free_sem_info(&sem_info);
2139 free(cs_array);
2140 }
2141
2142 if (fence) {
2143 if (!fence_emitted) {
2144 struct radv_winsys_sem_info sem_info = {0};
2145 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2146 &queue->device->empty_cs[queue->queue_family_index],
2147 1, NULL, NULL, &sem_info,
2148 false, base_fence);
2149 }
2150 fence->submitted = true;
2151 }
2152
2153 return VK_SUCCESS;
2154 }
2155
2156 VkResult radv_QueueWaitIdle(
2157 VkQueue _queue)
2158 {
2159 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2160
2161 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2162 radv_queue_family_to_ring(queue->queue_family_index),
2163 queue->queue_idx);
2164 return VK_SUCCESS;
2165 }
2166
2167 VkResult radv_DeviceWaitIdle(
2168 VkDevice _device)
2169 {
2170 RADV_FROM_HANDLE(radv_device, device, _device);
2171
2172 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2173 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2174 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2175 }
2176 }
2177 return VK_SUCCESS;
2178 }
2179
2180 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2181 VkInstance instance,
2182 const char* pName)
2183 {
2184 return radv_lookup_entrypoint(pName);
2185 }
2186
2187 /* The loader wants us to expose a second GetInstanceProcAddr function
2188 * to work around certain LD_PRELOAD issues seen in apps.
2189 */
2190 PUBLIC
2191 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2192 VkInstance instance,
2193 const char* pName);
2194
2195 PUBLIC
2196 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2197 VkInstance instance,
2198 const char* pName)
2199 {
2200 return radv_GetInstanceProcAddr(instance, pName);
2201 }
2202
2203 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2204 VkDevice device,
2205 const char* pName)
2206 {
2207 return radv_lookup_entrypoint(pName);
2208 }
2209
2210 bool radv_get_memory_fd(struct radv_device *device,
2211 struct radv_device_memory *memory,
2212 int *pFD)
2213 {
2214 struct radeon_bo_metadata metadata;
2215
2216 if (memory->image) {
2217 radv_init_metadata(device, memory->image, &metadata);
2218 device->ws->buffer_set_metadata(memory->bo, &metadata);
2219 }
2220
2221 return device->ws->buffer_get_fd(device->ws, memory->bo,
2222 pFD);
2223 }
2224
2225 VkResult radv_AllocateMemory(
2226 VkDevice _device,
2227 const VkMemoryAllocateInfo* pAllocateInfo,
2228 const VkAllocationCallbacks* pAllocator,
2229 VkDeviceMemory* pMem)
2230 {
2231 RADV_FROM_HANDLE(radv_device, device, _device);
2232 struct radv_device_memory *mem;
2233 VkResult result;
2234 enum radeon_bo_domain domain;
2235 uint32_t flags = 0;
2236
2237 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2238
2239 if (pAllocateInfo->allocationSize == 0) {
2240 /* Apparently, this is allowed */
2241 *pMem = VK_NULL_HANDLE;
2242 return VK_SUCCESS;
2243 }
2244
2245 const VkImportMemoryFdInfoKHR *import_info =
2246 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2247 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2248 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2249
2250 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2251 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2252 if (mem == NULL)
2253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2254
2255 if (dedicate_info) {
2256 mem->image = radv_image_from_handle(dedicate_info->image);
2257 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2258 } else {
2259 mem->image = NULL;
2260 mem->buffer = NULL;
2261 }
2262
2263 if (import_info) {
2264 assert(import_info->handleType ==
2265 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2266 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2267 NULL, NULL);
2268 if (!mem->bo) {
2269 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2270 goto fail;
2271 } else {
2272 close(import_info->fd);
2273 goto out_success;
2274 }
2275 }
2276
2277 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2278 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2279 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2280 domain = RADEON_DOMAIN_GTT;
2281 else
2282 domain = RADEON_DOMAIN_VRAM;
2283
2284 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2285 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2286 else
2287 flags |= RADEON_FLAG_CPU_ACCESS;
2288
2289 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2290 flags |= RADEON_FLAG_GTT_WC;
2291
2292 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2293 domain, flags);
2294
2295 if (!mem->bo) {
2296 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2297 goto fail;
2298 }
2299 mem->type_index = pAllocateInfo->memoryTypeIndex;
2300 out_success:
2301 *pMem = radv_device_memory_to_handle(mem);
2302
2303 return VK_SUCCESS;
2304
2305 fail:
2306 vk_free2(&device->alloc, pAllocator, mem);
2307
2308 return result;
2309 }
2310
2311 void radv_FreeMemory(
2312 VkDevice _device,
2313 VkDeviceMemory _mem,
2314 const VkAllocationCallbacks* pAllocator)
2315 {
2316 RADV_FROM_HANDLE(radv_device, device, _device);
2317 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2318
2319 if (mem == NULL)
2320 return;
2321
2322 device->ws->buffer_destroy(mem->bo);
2323 mem->bo = NULL;
2324
2325 vk_free2(&device->alloc, pAllocator, mem);
2326 }
2327
2328 VkResult radv_MapMemory(
2329 VkDevice _device,
2330 VkDeviceMemory _memory,
2331 VkDeviceSize offset,
2332 VkDeviceSize size,
2333 VkMemoryMapFlags flags,
2334 void** ppData)
2335 {
2336 RADV_FROM_HANDLE(radv_device, device, _device);
2337 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2338
2339 if (mem == NULL) {
2340 *ppData = NULL;
2341 return VK_SUCCESS;
2342 }
2343
2344 *ppData = device->ws->buffer_map(mem->bo);
2345 if (*ppData) {
2346 *ppData += offset;
2347 return VK_SUCCESS;
2348 }
2349
2350 return VK_ERROR_MEMORY_MAP_FAILED;
2351 }
2352
2353 void radv_UnmapMemory(
2354 VkDevice _device,
2355 VkDeviceMemory _memory)
2356 {
2357 RADV_FROM_HANDLE(radv_device, device, _device);
2358 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2359
2360 if (mem == NULL)
2361 return;
2362
2363 device->ws->buffer_unmap(mem->bo);
2364 }
2365
2366 VkResult radv_FlushMappedMemoryRanges(
2367 VkDevice _device,
2368 uint32_t memoryRangeCount,
2369 const VkMappedMemoryRange* pMemoryRanges)
2370 {
2371 return VK_SUCCESS;
2372 }
2373
2374 VkResult radv_InvalidateMappedMemoryRanges(
2375 VkDevice _device,
2376 uint32_t memoryRangeCount,
2377 const VkMappedMemoryRange* pMemoryRanges)
2378 {
2379 return VK_SUCCESS;
2380 }
2381
2382 void radv_GetBufferMemoryRequirements(
2383 VkDevice device,
2384 VkBuffer _buffer,
2385 VkMemoryRequirements* pMemoryRequirements)
2386 {
2387 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2388
2389 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2390
2391 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2392 pMemoryRequirements->alignment = 4096;
2393 else
2394 pMemoryRequirements->alignment = 16;
2395
2396 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2397 }
2398
2399 void radv_GetBufferMemoryRequirements2KHR(
2400 VkDevice device,
2401 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2402 VkMemoryRequirements2KHR* pMemoryRequirements)
2403 {
2404 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2405 &pMemoryRequirements->memoryRequirements);
2406
2407 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2408 switch (ext->sType) {
2409 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2410 VkMemoryDedicatedRequirementsKHR *req =
2411 (VkMemoryDedicatedRequirementsKHR *) ext;
2412 req->requiresDedicatedAllocation = false;
2413 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2414 break;
2415 }
2416 default:
2417 break;
2418 }
2419 }
2420 }
2421
2422 void radv_GetImageMemoryRequirements(
2423 VkDevice device,
2424 VkImage _image,
2425 VkMemoryRequirements* pMemoryRequirements)
2426 {
2427 RADV_FROM_HANDLE(radv_image, image, _image);
2428
2429 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2430
2431 pMemoryRequirements->size = image->size;
2432 pMemoryRequirements->alignment = image->alignment;
2433 }
2434
2435 void radv_GetImageMemoryRequirements2KHR(
2436 VkDevice device,
2437 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2438 VkMemoryRequirements2KHR* pMemoryRequirements)
2439 {
2440 radv_GetImageMemoryRequirements(device, pInfo->image,
2441 &pMemoryRequirements->memoryRequirements);
2442
2443 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2444
2445 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2446 switch (ext->sType) {
2447 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2448 VkMemoryDedicatedRequirementsKHR *req =
2449 (VkMemoryDedicatedRequirementsKHR *) ext;
2450 req->requiresDedicatedAllocation = image->shareable;
2451 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2452 break;
2453 }
2454 default:
2455 break;
2456 }
2457 }
2458 }
2459
2460 void radv_GetImageSparseMemoryRequirements(
2461 VkDevice device,
2462 VkImage image,
2463 uint32_t* pSparseMemoryRequirementCount,
2464 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2465 {
2466 stub();
2467 }
2468
2469 void radv_GetImageSparseMemoryRequirements2KHR(
2470 VkDevice device,
2471 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2472 uint32_t* pSparseMemoryRequirementCount,
2473 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2474 {
2475 stub();
2476 }
2477
2478 void radv_GetDeviceMemoryCommitment(
2479 VkDevice device,
2480 VkDeviceMemory memory,
2481 VkDeviceSize* pCommittedMemoryInBytes)
2482 {
2483 *pCommittedMemoryInBytes = 0;
2484 }
2485
2486 VkResult radv_BindBufferMemory(
2487 VkDevice device,
2488 VkBuffer _buffer,
2489 VkDeviceMemory _memory,
2490 VkDeviceSize memoryOffset)
2491 {
2492 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2493 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2494
2495 if (mem) {
2496 buffer->bo = mem->bo;
2497 buffer->offset = memoryOffset;
2498 } else {
2499 buffer->bo = NULL;
2500 buffer->offset = 0;
2501 }
2502
2503 return VK_SUCCESS;
2504 }
2505
2506 VkResult radv_BindImageMemory(
2507 VkDevice device,
2508 VkImage _image,
2509 VkDeviceMemory _memory,
2510 VkDeviceSize memoryOffset)
2511 {
2512 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2513 RADV_FROM_HANDLE(radv_image, image, _image);
2514
2515 if (mem) {
2516 image->bo = mem->bo;
2517 image->offset = memoryOffset;
2518 } else {
2519 image->bo = NULL;
2520 image->offset = 0;
2521 }
2522
2523 return VK_SUCCESS;
2524 }
2525
2526
2527 static void
2528 radv_sparse_buffer_bind_memory(struct radv_device *device,
2529 const VkSparseBufferMemoryBindInfo *bind)
2530 {
2531 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2532
2533 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2534 struct radv_device_memory *mem = NULL;
2535
2536 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2537 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2538
2539 device->ws->buffer_virtual_bind(buffer->bo,
2540 bind->pBinds[i].resourceOffset,
2541 bind->pBinds[i].size,
2542 mem ? mem->bo : NULL,
2543 bind->pBinds[i].memoryOffset);
2544 }
2545 }
2546
2547 static void
2548 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2549 const VkSparseImageOpaqueMemoryBindInfo *bind)
2550 {
2551 RADV_FROM_HANDLE(radv_image, image, bind->image);
2552
2553 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2554 struct radv_device_memory *mem = NULL;
2555
2556 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2557 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2558
2559 device->ws->buffer_virtual_bind(image->bo,
2560 bind->pBinds[i].resourceOffset,
2561 bind->pBinds[i].size,
2562 mem ? mem->bo : NULL,
2563 bind->pBinds[i].memoryOffset);
2564 }
2565 }
2566
2567 VkResult radv_QueueBindSparse(
2568 VkQueue _queue,
2569 uint32_t bindInfoCount,
2570 const VkBindSparseInfo* pBindInfo,
2571 VkFence _fence)
2572 {
2573 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2574 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2575 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2576 bool fence_emitted = false;
2577
2578 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2579 struct radv_winsys_sem_info sem_info;
2580 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2581 radv_sparse_buffer_bind_memory(queue->device,
2582 pBindInfo[i].pBufferBinds + j);
2583 }
2584
2585 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2586 radv_sparse_image_opaque_bind_memory(queue->device,
2587 pBindInfo[i].pImageOpaqueBinds + j);
2588 }
2589
2590 VkResult result;
2591 result = radv_alloc_sem_info(&sem_info,
2592 pBindInfo[i].waitSemaphoreCount,
2593 pBindInfo[i].pWaitSemaphores,
2594 pBindInfo[i].signalSemaphoreCount,
2595 pBindInfo[i].pSignalSemaphores);
2596 if (result != VK_SUCCESS)
2597 return result;
2598
2599 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2600 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2601 &queue->device->empty_cs[queue->queue_family_index],
2602 1, NULL, NULL,
2603 &sem_info,
2604 false, base_fence);
2605 fence_emitted = true;
2606 if (fence)
2607 fence->submitted = true;
2608 }
2609
2610 radv_free_sem_info(&sem_info);
2611
2612 }
2613
2614 if (fence && !fence_emitted) {
2615 fence->signalled = true;
2616 }
2617
2618 return VK_SUCCESS;
2619 }
2620
2621 VkResult radv_CreateFence(
2622 VkDevice _device,
2623 const VkFenceCreateInfo* pCreateInfo,
2624 const VkAllocationCallbacks* pAllocator,
2625 VkFence* pFence)
2626 {
2627 RADV_FROM_HANDLE(radv_device, device, _device);
2628 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2629 sizeof(*fence), 8,
2630 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2631
2632 if (!fence)
2633 return VK_ERROR_OUT_OF_HOST_MEMORY;
2634
2635 memset(fence, 0, sizeof(*fence));
2636 fence->submitted = false;
2637 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2638 fence->fence = device->ws->create_fence();
2639 if (!fence->fence) {
2640 vk_free2(&device->alloc, pAllocator, fence);
2641 return VK_ERROR_OUT_OF_HOST_MEMORY;
2642 }
2643
2644 *pFence = radv_fence_to_handle(fence);
2645
2646 return VK_SUCCESS;
2647 }
2648
2649 void radv_DestroyFence(
2650 VkDevice _device,
2651 VkFence _fence,
2652 const VkAllocationCallbacks* pAllocator)
2653 {
2654 RADV_FROM_HANDLE(radv_device, device, _device);
2655 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2656
2657 if (!fence)
2658 return;
2659 device->ws->destroy_fence(fence->fence);
2660 vk_free2(&device->alloc, pAllocator, fence);
2661 }
2662
2663 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2664 {
2665 uint64_t current_time;
2666 struct timespec tv;
2667
2668 clock_gettime(CLOCK_MONOTONIC, &tv);
2669 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2670
2671 timeout = MIN2(UINT64_MAX - current_time, timeout);
2672
2673 return current_time + timeout;
2674 }
2675
2676 VkResult radv_WaitForFences(
2677 VkDevice _device,
2678 uint32_t fenceCount,
2679 const VkFence* pFences,
2680 VkBool32 waitAll,
2681 uint64_t timeout)
2682 {
2683 RADV_FROM_HANDLE(radv_device, device, _device);
2684 timeout = radv_get_absolute_timeout(timeout);
2685
2686 if (!waitAll && fenceCount > 1) {
2687 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2688 }
2689
2690 for (uint32_t i = 0; i < fenceCount; ++i) {
2691 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2692 bool expired = false;
2693
2694 if (fence->signalled)
2695 continue;
2696
2697 if (!fence->submitted)
2698 return VK_TIMEOUT;
2699
2700 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2701 if (!expired)
2702 return VK_TIMEOUT;
2703
2704 fence->signalled = true;
2705 }
2706
2707 return VK_SUCCESS;
2708 }
2709
2710 VkResult radv_ResetFences(VkDevice device,
2711 uint32_t fenceCount,
2712 const VkFence *pFences)
2713 {
2714 for (unsigned i = 0; i < fenceCount; ++i) {
2715 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2716 fence->submitted = fence->signalled = false;
2717 }
2718
2719 return VK_SUCCESS;
2720 }
2721
2722 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2723 {
2724 RADV_FROM_HANDLE(radv_device, device, _device);
2725 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2726
2727 if (fence->signalled)
2728 return VK_SUCCESS;
2729 if (!fence->submitted)
2730 return VK_NOT_READY;
2731
2732 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2733 return VK_NOT_READY;
2734
2735 return VK_SUCCESS;
2736 }
2737
2738
2739 // Queue semaphore functions
2740
2741 VkResult radv_CreateSemaphore(
2742 VkDevice _device,
2743 const VkSemaphoreCreateInfo* pCreateInfo,
2744 const VkAllocationCallbacks* pAllocator,
2745 VkSemaphore* pSemaphore)
2746 {
2747 RADV_FROM_HANDLE(radv_device, device, _device);
2748 const VkExportSemaphoreCreateInfoKHR *export =
2749 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2750 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2751 export ? export->handleTypes : 0;
2752
2753 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2754 sizeof(*sem), 8,
2755 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2756 if (!sem)
2757 return VK_ERROR_OUT_OF_HOST_MEMORY;
2758
2759 sem->temp_syncobj = 0;
2760 /* create a syncobject if we are going to export this semaphore */
2761 if (handleTypes) {
2762 assert (device->physical_device->rad_info.has_syncobj);
2763 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2764 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2765 if (ret) {
2766 vk_free2(&device->alloc, pAllocator, sem);
2767 return VK_ERROR_OUT_OF_HOST_MEMORY;
2768 }
2769 sem->sem = NULL;
2770 } else {
2771 sem->sem = device->ws->create_sem(device->ws);
2772 if (!sem->sem) {
2773 vk_free2(&device->alloc, pAllocator, sem);
2774 return VK_ERROR_OUT_OF_HOST_MEMORY;
2775 }
2776 sem->syncobj = 0;
2777 }
2778
2779 *pSemaphore = radv_semaphore_to_handle(sem);
2780 return VK_SUCCESS;
2781 }
2782
2783 void radv_DestroySemaphore(
2784 VkDevice _device,
2785 VkSemaphore _semaphore,
2786 const VkAllocationCallbacks* pAllocator)
2787 {
2788 RADV_FROM_HANDLE(radv_device, device, _device);
2789 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2790 if (!_semaphore)
2791 return;
2792
2793 if (sem->syncobj)
2794 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2795 else
2796 device->ws->destroy_sem(sem->sem);
2797 vk_free2(&device->alloc, pAllocator, sem);
2798 }
2799
2800 VkResult radv_CreateEvent(
2801 VkDevice _device,
2802 const VkEventCreateInfo* pCreateInfo,
2803 const VkAllocationCallbacks* pAllocator,
2804 VkEvent* pEvent)
2805 {
2806 RADV_FROM_HANDLE(radv_device, device, _device);
2807 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2808 sizeof(*event), 8,
2809 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2810
2811 if (!event)
2812 return VK_ERROR_OUT_OF_HOST_MEMORY;
2813
2814 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2815 RADEON_DOMAIN_GTT,
2816 RADEON_FLAG_CPU_ACCESS);
2817 if (!event->bo) {
2818 vk_free2(&device->alloc, pAllocator, event);
2819 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2820 }
2821
2822 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2823
2824 *pEvent = radv_event_to_handle(event);
2825
2826 return VK_SUCCESS;
2827 }
2828
2829 void radv_DestroyEvent(
2830 VkDevice _device,
2831 VkEvent _event,
2832 const VkAllocationCallbacks* pAllocator)
2833 {
2834 RADV_FROM_HANDLE(radv_device, device, _device);
2835 RADV_FROM_HANDLE(radv_event, event, _event);
2836
2837 if (!event)
2838 return;
2839 device->ws->buffer_destroy(event->bo);
2840 vk_free2(&device->alloc, pAllocator, event);
2841 }
2842
2843 VkResult radv_GetEventStatus(
2844 VkDevice _device,
2845 VkEvent _event)
2846 {
2847 RADV_FROM_HANDLE(radv_event, event, _event);
2848
2849 if (*event->map == 1)
2850 return VK_EVENT_SET;
2851 return VK_EVENT_RESET;
2852 }
2853
2854 VkResult radv_SetEvent(
2855 VkDevice _device,
2856 VkEvent _event)
2857 {
2858 RADV_FROM_HANDLE(radv_event, event, _event);
2859 *event->map = 1;
2860
2861 return VK_SUCCESS;
2862 }
2863
2864 VkResult radv_ResetEvent(
2865 VkDevice _device,
2866 VkEvent _event)
2867 {
2868 RADV_FROM_HANDLE(radv_event, event, _event);
2869 *event->map = 0;
2870
2871 return VK_SUCCESS;
2872 }
2873
2874 VkResult radv_CreateBuffer(
2875 VkDevice _device,
2876 const VkBufferCreateInfo* pCreateInfo,
2877 const VkAllocationCallbacks* pAllocator,
2878 VkBuffer* pBuffer)
2879 {
2880 RADV_FROM_HANDLE(radv_device, device, _device);
2881 struct radv_buffer *buffer;
2882
2883 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2884
2885 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2886 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2887 if (buffer == NULL)
2888 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2889
2890 buffer->size = pCreateInfo->size;
2891 buffer->usage = pCreateInfo->usage;
2892 buffer->bo = NULL;
2893 buffer->offset = 0;
2894 buffer->flags = pCreateInfo->flags;
2895
2896 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2897 buffer->bo = device->ws->buffer_create(device->ws,
2898 align64(buffer->size, 4096),
2899 4096, 0, RADEON_FLAG_VIRTUAL);
2900 if (!buffer->bo) {
2901 vk_free2(&device->alloc, pAllocator, buffer);
2902 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2903 }
2904 }
2905
2906 *pBuffer = radv_buffer_to_handle(buffer);
2907
2908 return VK_SUCCESS;
2909 }
2910
2911 void radv_DestroyBuffer(
2912 VkDevice _device,
2913 VkBuffer _buffer,
2914 const VkAllocationCallbacks* pAllocator)
2915 {
2916 RADV_FROM_HANDLE(radv_device, device, _device);
2917 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2918
2919 if (!buffer)
2920 return;
2921
2922 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2923 device->ws->buffer_destroy(buffer->bo);
2924
2925 vk_free2(&device->alloc, pAllocator, buffer);
2926 }
2927
2928 static inline unsigned
2929 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2930 {
2931 if (stencil)
2932 return image->surface.u.legacy.stencil_tiling_index[level];
2933 else
2934 return image->surface.u.legacy.tiling_index[level];
2935 }
2936
2937 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2938 {
2939 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2940 }
2941
2942 static void
2943 radv_initialise_color_surface(struct radv_device *device,
2944 struct radv_color_buffer_info *cb,
2945 struct radv_image_view *iview)
2946 {
2947 const struct vk_format_description *desc;
2948 unsigned ntype, format, swap, endian;
2949 unsigned blend_clamp = 0, blend_bypass = 0;
2950 uint64_t va;
2951 const struct radeon_surf *surf = &iview->image->surface;
2952
2953 desc = vk_format_description(iview->vk_format);
2954
2955 memset(cb, 0, sizeof(*cb));
2956
2957 /* Intensity is implemented as Red, so treat it that way. */
2958 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2959
2960 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2961
2962 if (device->physical_device->rad_info.chip_class >= GFX9) {
2963 struct gfx9_surf_meta_flags meta;
2964 if (iview->image->dcc_offset)
2965 meta = iview->image->surface.u.gfx9.dcc;
2966 else
2967 meta = iview->image->surface.u.gfx9.cmask;
2968
2969 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2970 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2971 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2972 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2973
2974 va += iview->image->surface.u.gfx9.surf_offset >> 8;
2975 } else {
2976 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2977 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2978
2979 va += level_info->offset;
2980
2981 pitch_tile_max = level_info->nblk_x / 8 - 1;
2982 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2983 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2984
2985 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2986 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2987 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2988
2989 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2990 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2991
2992 if (iview->image->fmask.size) {
2993 if (device->physical_device->rad_info.chip_class >= CIK)
2994 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2995 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2996 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2997 } else {
2998 /* This must be set for fast clear to work without FMASK. */
2999 if (device->physical_device->rad_info.chip_class >= CIK)
3000 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3001 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3002 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3003 }
3004 }
3005
3006 cb->cb_color_base = va >> 8;
3007 if (device->physical_device->rad_info.chip_class < GFX9)
3008 cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
3009 /* CMASK variables */
3010 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3011 va += iview->image->cmask.offset;
3012 cb->cb_color_cmask = va >> 8;
3013
3014 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3015 va += iview->image->dcc_offset;
3016 cb->cb_dcc_base = va >> 8;
3017 if (device->physical_device->rad_info.chip_class < GFX9)
3018 cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
3019
3020 uint32_t max_slice = radv_surface_layer_count(iview);
3021 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3022 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3023
3024 if (iview->image->info.samples > 1) {
3025 unsigned log_samples = util_logbase2(iview->image->info.samples);
3026
3027 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3028 S_028C74_NUM_FRAGMENTS(log_samples);
3029 }
3030
3031 if (iview->image->fmask.size) {
3032 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3033 cb->cb_color_fmask = va >> 8;
3034 if (device->physical_device->rad_info.chip_class < GFX9)
3035 cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
3036 } else {
3037 cb->cb_color_fmask = cb->cb_color_base;
3038 }
3039
3040 ntype = radv_translate_color_numformat(iview->vk_format,
3041 desc,
3042 vk_format_get_first_non_void_channel(iview->vk_format));
3043 format = radv_translate_colorformat(iview->vk_format);
3044 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3045 radv_finishme("Illegal color\n");
3046 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3047 endian = radv_colorformat_endian_swap(format);
3048
3049 /* blend clamp should be set for all NORM/SRGB types */
3050 if (ntype == V_028C70_NUMBER_UNORM ||
3051 ntype == V_028C70_NUMBER_SNORM ||
3052 ntype == V_028C70_NUMBER_SRGB)
3053 blend_clamp = 1;
3054
3055 /* set blend bypass according to docs if SINT/UINT or
3056 8/24 COLOR variants */
3057 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3058 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3059 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3060 blend_clamp = 0;
3061 blend_bypass = 1;
3062 }
3063 #if 0
3064 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3065 (format == V_028C70_COLOR_8 ||
3066 format == V_028C70_COLOR_8_8 ||
3067 format == V_028C70_COLOR_8_8_8_8))
3068 ->color_is_int8 = true;
3069 #endif
3070 cb->cb_color_info = S_028C70_FORMAT(format) |
3071 S_028C70_COMP_SWAP(swap) |
3072 S_028C70_BLEND_CLAMP(blend_clamp) |
3073 S_028C70_BLEND_BYPASS(blend_bypass) |
3074 S_028C70_SIMPLE_FLOAT(1) |
3075 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3076 ntype != V_028C70_NUMBER_SNORM &&
3077 ntype != V_028C70_NUMBER_SRGB &&
3078 format != V_028C70_COLOR_8_24 &&
3079 format != V_028C70_COLOR_24_8) |
3080 S_028C70_NUMBER_TYPE(ntype) |
3081 S_028C70_ENDIAN(endian);
3082 if (iview->image->info.samples > 1)
3083 if (iview->image->fmask.size)
3084 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3085
3086 if (iview->image->cmask.size &&
3087 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3088 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3089
3090 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3091 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3092
3093 if (device->physical_device->rad_info.chip_class >= VI) {
3094 unsigned max_uncompressed_block_size = 2;
3095 if (iview->image->info.samples > 1) {
3096 if (iview->image->surface.bpe == 1)
3097 max_uncompressed_block_size = 0;
3098 else if (iview->image->surface.bpe == 2)
3099 max_uncompressed_block_size = 1;
3100 }
3101
3102 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3103 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3104 }
3105
3106 /* This must be set for fast clear to work without FMASK. */
3107 if (!iview->image->fmask.size &&
3108 device->physical_device->rad_info.chip_class == SI) {
3109 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3110 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3111 }
3112
3113 if (device->physical_device->rad_info.chip_class >= GFX9) {
3114 uint32_t max_slice = radv_surface_layer_count(iview);
3115 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3116
3117 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3118 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3119 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3120 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
3121 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
3122 S_028C68_MAX_MIP(iview->image->info.levels);
3123
3124 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3125
3126 }
3127 }
3128
3129 static void
3130 radv_initialise_ds_surface(struct radv_device *device,
3131 struct radv_ds_buffer_info *ds,
3132 struct radv_image_view *iview)
3133 {
3134 unsigned level = iview->base_mip;
3135 unsigned format, stencil_format;
3136 uint64_t va, s_offs, z_offs;
3137 bool stencil_only = false;
3138 memset(ds, 0, sizeof(*ds));
3139 switch (iview->image->vk_format) {
3140 case VK_FORMAT_D24_UNORM_S8_UINT:
3141 case VK_FORMAT_X8_D24_UNORM_PACK32:
3142 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3143 ds->offset_scale = 2.0f;
3144 break;
3145 case VK_FORMAT_D16_UNORM:
3146 case VK_FORMAT_D16_UNORM_S8_UINT:
3147 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3148 ds->offset_scale = 4.0f;
3149 break;
3150 case VK_FORMAT_D32_SFLOAT:
3151 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3152 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3153 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3154 ds->offset_scale = 1.0f;
3155 break;
3156 case VK_FORMAT_S8_UINT:
3157 stencil_only = true;
3158 break;
3159 default:
3160 break;
3161 }
3162
3163 format = radv_translate_dbformat(iview->image->vk_format);
3164 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
3165 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3166
3167 uint32_t max_slice = radv_surface_layer_count(iview);
3168 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3169 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3170
3171 ds->db_htile_data_base = 0;
3172 ds->db_htile_surface = 0;
3173
3174 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3175 s_offs = z_offs = va;
3176
3177 if (device->physical_device->rad_info.chip_class >= GFX9) {
3178 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3179 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3180
3181 ds->db_z_info = S_028038_FORMAT(format) |
3182 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3183 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3184 S_028038_MAXMIP(iview->image->info.levels - 1);
3185 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3186 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3187
3188 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3189 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3190 ds->db_depth_view |= S_028008_MIPID(level);
3191
3192 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3193 S_02801C_Y_MAX(iview->image->info.height - 1);
3194
3195 /* Only use HTILE for the first level. */
3196 if (iview->image->surface.htile_size && !level) {
3197 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3198
3199 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3200 /* Use all of the htile_buffer for depth if there's no stencil. */
3201 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3202 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3203 iview->image->htile_offset;
3204 ds->db_htile_data_base = va >> 8;
3205 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3206 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3207 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3208 }
3209 } else {
3210 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3211
3212 if (stencil_only)
3213 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3214
3215 z_offs += iview->image->surface.u.legacy.level[level].offset;
3216 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3217
3218 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3219 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3220 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3221
3222 if (iview->image->info.samples > 1)
3223 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3224
3225 if (device->physical_device->rad_info.chip_class >= CIK) {
3226 struct radeon_info *info = &device->physical_device->rad_info;
3227 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3228 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3229 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3230 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3231 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3232 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3233
3234 if (stencil_only)
3235 tile_mode = stencil_tile_mode;
3236
3237 ds->db_depth_info |=
3238 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3239 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3240 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3241 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3242 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3243 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3244 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3245 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3246 } else {
3247 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3248 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3249 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3250 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3251 if (stencil_only)
3252 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3253 }
3254
3255 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3256 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3257 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3258
3259 if (iview->image->surface.htile_size && !level) {
3260 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3261
3262 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3263 /* Use all of the htile_buffer for depth if there's no stencil. */
3264 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3265
3266 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3267 iview->image->htile_offset;
3268 ds->db_htile_data_base = va >> 8;
3269 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3270 }
3271 }
3272
3273 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3274 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3275 }
3276
3277 VkResult radv_CreateFramebuffer(
3278 VkDevice _device,
3279 const VkFramebufferCreateInfo* pCreateInfo,
3280 const VkAllocationCallbacks* pAllocator,
3281 VkFramebuffer* pFramebuffer)
3282 {
3283 RADV_FROM_HANDLE(radv_device, device, _device);
3284 struct radv_framebuffer *framebuffer;
3285
3286 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3287
3288 size_t size = sizeof(*framebuffer) +
3289 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3290 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3291 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3292 if (framebuffer == NULL)
3293 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3294
3295 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3296 framebuffer->width = pCreateInfo->width;
3297 framebuffer->height = pCreateInfo->height;
3298 framebuffer->layers = pCreateInfo->layers;
3299 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3300 VkImageView _iview = pCreateInfo->pAttachments[i];
3301 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3302 framebuffer->attachments[i].attachment = iview;
3303 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3304 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3305 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3306 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3307 }
3308 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3309 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3310 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3311 }
3312
3313 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3314 return VK_SUCCESS;
3315 }
3316
3317 void radv_DestroyFramebuffer(
3318 VkDevice _device,
3319 VkFramebuffer _fb,
3320 const VkAllocationCallbacks* pAllocator)
3321 {
3322 RADV_FROM_HANDLE(radv_device, device, _device);
3323 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3324
3325 if (!fb)
3326 return;
3327 vk_free2(&device->alloc, pAllocator, fb);
3328 }
3329
3330 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3331 {
3332 switch (address_mode) {
3333 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3334 return V_008F30_SQ_TEX_WRAP;
3335 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3336 return V_008F30_SQ_TEX_MIRROR;
3337 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3338 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3339 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3340 return V_008F30_SQ_TEX_CLAMP_BORDER;
3341 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3342 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3343 default:
3344 unreachable("illegal tex wrap mode");
3345 break;
3346 }
3347 }
3348
3349 static unsigned
3350 radv_tex_compare(VkCompareOp op)
3351 {
3352 switch (op) {
3353 case VK_COMPARE_OP_NEVER:
3354 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3355 case VK_COMPARE_OP_LESS:
3356 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3357 case VK_COMPARE_OP_EQUAL:
3358 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3359 case VK_COMPARE_OP_LESS_OR_EQUAL:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3361 case VK_COMPARE_OP_GREATER:
3362 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3363 case VK_COMPARE_OP_NOT_EQUAL:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3365 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3366 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3367 case VK_COMPARE_OP_ALWAYS:
3368 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3369 default:
3370 unreachable("illegal compare mode");
3371 break;
3372 }
3373 }
3374
3375 static unsigned
3376 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3377 {
3378 switch (filter) {
3379 case VK_FILTER_NEAREST:
3380 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3381 V_008F38_SQ_TEX_XY_FILTER_POINT);
3382 case VK_FILTER_LINEAR:
3383 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3384 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3385 case VK_FILTER_CUBIC_IMG:
3386 default:
3387 fprintf(stderr, "illegal texture filter");
3388 return 0;
3389 }
3390 }
3391
3392 static unsigned
3393 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3394 {
3395 switch (mode) {
3396 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3397 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3398 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3399 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3400 default:
3401 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3402 }
3403 }
3404
3405 static unsigned
3406 radv_tex_bordercolor(VkBorderColor bcolor)
3407 {
3408 switch (bcolor) {
3409 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3410 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3411 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3412 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3413 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3414 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3415 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3416 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3417 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3418 default:
3419 break;
3420 }
3421 return 0;
3422 }
3423
3424 static unsigned
3425 radv_tex_aniso_filter(unsigned filter)
3426 {
3427 if (filter < 2)
3428 return 0;
3429 if (filter < 4)
3430 return 1;
3431 if (filter < 8)
3432 return 2;
3433 if (filter < 16)
3434 return 3;
3435 return 4;
3436 }
3437
3438 static void
3439 radv_init_sampler(struct radv_device *device,
3440 struct radv_sampler *sampler,
3441 const VkSamplerCreateInfo *pCreateInfo)
3442 {
3443 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3444 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3445 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3446 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3447
3448 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3449 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3450 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3451 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3452 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3453 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3454 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3455 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3456 S_008F30_DISABLE_CUBE_WRAP(0) |
3457 S_008F30_COMPAT_MODE(is_vi));
3458 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3459 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3460 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3461 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3462 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3463 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3464 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3465 S_008F38_MIP_POINT_PRECLAMP(0) |
3466 S_008F38_DISABLE_LSB_CEIL(1) |
3467 S_008F38_FILTER_PREC_FIX(1) |
3468 S_008F38_ANISO_OVERRIDE(is_vi));
3469 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3470 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3471 }
3472
3473 VkResult radv_CreateSampler(
3474 VkDevice _device,
3475 const VkSamplerCreateInfo* pCreateInfo,
3476 const VkAllocationCallbacks* pAllocator,
3477 VkSampler* pSampler)
3478 {
3479 RADV_FROM_HANDLE(radv_device, device, _device);
3480 struct radv_sampler *sampler;
3481
3482 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3483
3484 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3485 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3486 if (!sampler)
3487 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3488
3489 radv_init_sampler(device, sampler, pCreateInfo);
3490 *pSampler = radv_sampler_to_handle(sampler);
3491
3492 return VK_SUCCESS;
3493 }
3494
3495 void radv_DestroySampler(
3496 VkDevice _device,
3497 VkSampler _sampler,
3498 const VkAllocationCallbacks* pAllocator)
3499 {
3500 RADV_FROM_HANDLE(radv_device, device, _device);
3501 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3502
3503 if (!sampler)
3504 return;
3505 vk_free2(&device->alloc, pAllocator, sampler);
3506 }
3507
3508 /* vk_icd.h does not declare this function, so we declare it here to
3509 * suppress Wmissing-prototypes.
3510 */
3511 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3512 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3513
3514 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3515 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3516 {
3517 /* For the full details on loader interface versioning, see
3518 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3519 * What follows is a condensed summary, to help you navigate the large and
3520 * confusing official doc.
3521 *
3522 * - Loader interface v0 is incompatible with later versions. We don't
3523 * support it.
3524 *
3525 * - In loader interface v1:
3526 * - The first ICD entrypoint called by the loader is
3527 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3528 * entrypoint.
3529 * - The ICD must statically expose no other Vulkan symbol unless it is
3530 * linked with -Bsymbolic.
3531 * - Each dispatchable Vulkan handle created by the ICD must be
3532 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3533 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3534 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3535 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3536 * such loader-managed surfaces.
3537 *
3538 * - Loader interface v2 differs from v1 in:
3539 * - The first ICD entrypoint called by the loader is
3540 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3541 * statically expose this entrypoint.
3542 *
3543 * - Loader interface v3 differs from v2 in:
3544 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3545 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3546 * because the loader no longer does so.
3547 */
3548 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3549 return VK_SUCCESS;
3550 }
3551
3552 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3553 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3554 int *pFD)
3555 {
3556 RADV_FROM_HANDLE(radv_device, device, _device);
3557 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3558
3559 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3560
3561 /* We support only one handle type. */
3562 assert(pGetFdInfo->handleType ==
3563 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3564
3565 bool ret = radv_get_memory_fd(device, memory, pFD);
3566 if (ret == false)
3567 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3568 return VK_SUCCESS;
3569 }
3570
3571 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3572 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3573 int fd,
3574 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3575 {
3576 /* The valid usage section for this function says:
3577 *
3578 * "handleType must not be one of the handle types defined as opaque."
3579 *
3580 * Since we only handle opaque handles for now, there are no FD properties.
3581 */
3582 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3583 }
3584
3585 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3586 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3587 {
3588 RADV_FROM_HANDLE(radv_device, device, _device);
3589 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3590 uint32_t syncobj_handle = 0;
3591 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3592
3593 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3594 if (ret != 0)
3595 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3596
3597 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3598 sem->temp_syncobj = syncobj_handle;
3599 } else {
3600 sem->syncobj = syncobj_handle;
3601 }
3602 close(pImportSemaphoreFdInfo->fd);
3603 return VK_SUCCESS;
3604 }
3605
3606 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3607 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3608 int *pFd)
3609 {
3610 RADV_FROM_HANDLE(radv_device, device, _device);
3611 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3612 int ret;
3613 uint32_t syncobj_handle;
3614
3615 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3616 if (sem->temp_syncobj)
3617 syncobj_handle = sem->temp_syncobj;
3618 else
3619 syncobj_handle = sem->syncobj;
3620 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3621 if (ret)
3622 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3623 return VK_SUCCESS;
3624 }
3625
3626 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3627 VkPhysicalDevice physicalDevice,
3628 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3629 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3630 {
3631 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3632 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3633 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3634 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3635 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3636 } else {
3637 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3638 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3639 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3640 }
3641 }