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radv: Update CTS version.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
619 DRI_CONF_SECTION_END
620
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
623 DRI_CONF_SECTION_END
624 DRI_CONF_END;
625
626 static void radv_init_dri_options(struct radv_instance *instance)
627 {
628 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
629 driParseConfigFiles(&instance->dri_options,
630 &instance->available_dri_options,
631 0, "radv", NULL,
632 instance->applicationName,
633 instance->applicationVersion,
634 instance->engineName,
635 instance->engineVersion);
636 }
637
638 VkResult radv_CreateInstance(
639 const VkInstanceCreateInfo* pCreateInfo,
640 const VkAllocationCallbacks* pAllocator,
641 VkInstance* pInstance)
642 {
643 struct radv_instance *instance;
644 VkResult result;
645
646 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
648 if (!instance)
649 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
650
651 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
652
653 if (pAllocator)
654 instance->alloc = *pAllocator;
655 else
656 instance->alloc = default_alloc;
657
658 if (pCreateInfo->pApplicationInfo) {
659 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
660
661 instance->applicationName =
662 vk_strdup(&instance->alloc, app->pApplicationName,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 instance->applicationVersion = app->applicationVersion;
665
666 instance->engineName =
667 vk_strdup(&instance->alloc, app->pEngineName,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = app->engineVersion;
670 instance->apiVersion = app->apiVersion;
671 }
672
673 if (instance->apiVersion == 0)
674 instance->apiVersion = VK_API_VERSION_1_0;
675
676 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
677 radv_debug_options);
678
679 const char *radv_perftest_str = getenv("RADV_PERFTEST");
680 instance->perftest_flags = parse_debug_string(radv_perftest_str,
681 radv_perftest_options);
682
683 if (radv_perftest_str) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
686 */
687 if (strstr(radv_perftest_str, "aco")) {
688 fprintf(stderr, "*******************************************************************************\n");
689 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr, "*******************************************************************************\n");
691 }
692 if (strstr(radv_perftest_str, "llvm")) {
693 fprintf(stderr, "*********************************************************************************\n");
694 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr, "*********************************************************************************\n");
696 abort();
697 }
698 }
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Created an instance");
702
703 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
704 int idx;
705 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
706 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
707 radv_instance_extensions[idx].extensionName))
708 break;
709 }
710
711 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
712 !radv_instance_extensions_supported.extensions[idx]) {
713 vk_object_base_finish(&instance->base);
714 vk_free2(&default_alloc, pAllocator, instance);
715 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
716 }
717
718 instance->enabled_extensions.extensions[idx] = true;
719 }
720
721 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
722
723 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
726 */
727 if (!unchecked &&
728 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
729 &instance->enabled_extensions)) {
730 instance->dispatch.entrypoints[i] = NULL;
731 } else {
732 instance->dispatch.entrypoints[i] =
733 radv_instance_dispatch_table.entrypoints[i];
734 }
735 }
736
737 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
740 */
741 if (!unchecked &&
742 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
743 &instance->enabled_extensions)) {
744 instance->physical_device_dispatch.entrypoints[i] = NULL;
745 } else {
746 instance->physical_device_dispatch.entrypoints[i] =
747 radv_physical_device_dispatch_table.entrypoints[i];
748 }
749 }
750
751 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
754 */
755 if (!unchecked &&
756 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
757 &instance->enabled_extensions, NULL)) {
758 instance->device_dispatch.entrypoints[i] = NULL;
759 } else {
760 instance->device_dispatch.entrypoints[i] =
761 radv_device_dispatch_table.entrypoints[i];
762 }
763 }
764
765 instance->physical_devices_enumerated = false;
766 list_inithead(&instance->physical_devices);
767
768 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
769 if (result != VK_SUCCESS) {
770 vk_object_base_finish(&instance->base);
771 vk_free2(&default_alloc, pAllocator, instance);
772 return vk_error(instance, result);
773 }
774
775 glsl_type_singleton_init_or_ref();
776
777 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
778
779 radv_init_dri_options(instance);
780 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
781
782 *pInstance = radv_instance_to_handle(instance);
783
784 return VK_SUCCESS;
785 }
786
787 void radv_DestroyInstance(
788 VkInstance _instance,
789 const VkAllocationCallbacks* pAllocator)
790 {
791 RADV_FROM_HANDLE(radv_instance, instance, _instance);
792
793 if (!instance)
794 return;
795
796 list_for_each_entry_safe(struct radv_physical_device, pdevice,
797 &instance->physical_devices, link) {
798 radv_physical_device_destroy(pdevice);
799 }
800
801 vk_free(&instance->alloc, instance->engineName);
802 vk_free(&instance->alloc, instance->applicationName);
803
804 VG(VALGRIND_DESTROY_MEMPOOL(instance));
805
806 glsl_type_singleton_decref();
807
808 driDestroyOptionCache(&instance->dri_options);
809 driDestroyOptionInfo(&instance->available_dri_options);
810
811 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
812
813 vk_object_base_finish(&instance->base);
814 vk_free(&instance->alloc, instance);
815 }
816
817 static VkResult
818 radv_enumerate_physical_devices(struct radv_instance *instance)
819 {
820 if (instance->physical_devices_enumerated)
821 return VK_SUCCESS;
822
823 instance->physical_devices_enumerated = true;
824
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices[8];
827 VkResult result = VK_SUCCESS;
828 int max_devices;
829
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
833 * AMDGPU instance.
834 */
835 struct radv_physical_device *pdevice;
836
837 result = radv_physical_device_try_create(instance, NULL, &pdevice);
838 if (result != VK_SUCCESS)
839 return result;
840
841 list_addtail(&pdevice->link, &instance->physical_devices);
842 return VK_SUCCESS;
843 }
844
845 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
846
847 if (instance->debug_flags & RADV_DEBUG_STARTUP)
848 radv_logi("Found %d drm nodes", max_devices);
849
850 if (max_devices < 1)
851 return vk_error(instance, VK_SUCCESS);
852
853 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
854 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
855 devices[i]->bustype == DRM_BUS_PCI &&
856 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
857
858 struct radv_physical_device *pdevice;
859 result = radv_physical_device_try_create(instance, devices[i],
860 &pdevice);
861 /* Incompatible DRM device, skip. */
862 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
863 result = VK_SUCCESS;
864 continue;
865 }
866
867 /* Error creating the physical device, report the error. */
868 if (result != VK_SUCCESS)
869 break;
870
871 list_addtail(&pdevice->link, &instance->physical_devices);
872 }
873 }
874 drmFreeDevices(devices, max_devices);
875
876 /* If we successfully enumerated any devices, call it success */
877 return result;
878 }
879
880 VkResult radv_EnumeratePhysicalDevices(
881 VkInstance _instance,
882 uint32_t* pPhysicalDeviceCount,
883 VkPhysicalDevice* pPhysicalDevices)
884 {
885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
886 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
887
888 VkResult result = radv_enumerate_physical_devices(instance);
889 if (result != VK_SUCCESS)
890 return result;
891
892 list_for_each_entry(struct radv_physical_device, pdevice,
893 &instance->physical_devices, link) {
894 vk_outarray_append(&out, i) {
895 *i = radv_physical_device_to_handle(pdevice);
896 }
897 }
898
899 return vk_outarray_status(&out);
900 }
901
902 VkResult radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance,
904 uint32_t* pPhysicalDeviceGroupCount,
905 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
906 {
907 RADV_FROM_HANDLE(radv_instance, instance, _instance);
908 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
909 pPhysicalDeviceGroupCount);
910
911 VkResult result = radv_enumerate_physical_devices(instance);
912 if (result != VK_SUCCESS)
913 return result;
914
915 list_for_each_entry(struct radv_physical_device, pdevice,
916 &instance->physical_devices, link) {
917 vk_outarray_append(&out, p) {
918 p->physicalDeviceCount = 1;
919 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
920 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
921 p->subsetAllocation = false;
922 }
923 }
924
925 return vk_outarray_status(&out);
926 }
927
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice,
930 VkPhysicalDeviceFeatures* pFeatures)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 memset(pFeatures, 0, sizeof(*pFeatures));
934
935 *pFeatures = (VkPhysicalDeviceFeatures) {
936 .robustBufferAccess = true,
937 .fullDrawIndexUint32 = true,
938 .imageCubeArray = true,
939 .independentBlend = true,
940 .geometryShader = true,
941 .tessellationShader = true,
942 .sampleRateShading = true,
943 .dualSrcBlend = true,
944 .logicOp = true,
945 .multiDrawIndirect = true,
946 .drawIndirectFirstInstance = true,
947 .depthClamp = true,
948 .depthBiasClamp = true,
949 .fillModeNonSolid = true,
950 .depthBounds = true,
951 .wideLines = true,
952 .largePoints = true,
953 .alphaToOne = true,
954 .multiViewport = true,
955 .samplerAnisotropy = true,
956 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
957 .textureCompressionASTC_LDR = false,
958 .textureCompressionBC = true,
959 .occlusionQueryPrecise = true,
960 .pipelineStatisticsQuery = true,
961 .vertexPipelineStoresAndAtomics = true,
962 .fragmentStoresAndAtomics = true,
963 .shaderTessellationAndGeometryPointSize = true,
964 .shaderImageGatherExtended = true,
965 .shaderStorageImageExtendedFormats = true,
966 .shaderStorageImageMultisample = true,
967 .shaderUniformBufferArrayDynamicIndexing = true,
968 .shaderSampledImageArrayDynamicIndexing = true,
969 .shaderStorageBufferArrayDynamicIndexing = true,
970 .shaderStorageImageArrayDynamicIndexing = true,
971 .shaderStorageImageReadWithoutFormat = true,
972 .shaderStorageImageWriteWithoutFormat = true,
973 .shaderClipDistance = true,
974 .shaderCullDistance = true,
975 .shaderFloat64 = true,
976 .shaderInt64 = true,
977 .shaderInt16 = true,
978 .sparseBinding = true,
979 .variableMultisampleRate = true,
980 .shaderResourceMinLod = true,
981 .inheritedQueries = true,
982 };
983 }
984
985 static void
986 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
987 VkPhysicalDeviceVulkan11Features *f)
988 {
989 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
990
991 f->storageBuffer16BitAccess = true;
992 f->uniformAndStorageBuffer16BitAccess = true;
993 f->storagePushConstant16 = true;
994 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
995 f->multiview = true;
996 f->multiviewGeometryShader = true;
997 f->multiviewTessellationShader = true;
998 f->variablePointersStorageBuffer = true;
999 f->variablePointers = true;
1000 f->protectedMemory = false;
1001 f->samplerYcbcrConversion = true;
1002 f->shaderDrawParameters = true;
1003 }
1004
1005 static void
1006 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1007 VkPhysicalDeviceVulkan12Features *f)
1008 {
1009 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1010
1011 f->samplerMirrorClampToEdge = true;
1012 f->drawIndirectCount = true;
1013 f->storageBuffer8BitAccess = true;
1014 f->uniformAndStorageBuffer8BitAccess = true;
1015 f->storagePushConstant8 = true;
1016 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1018 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1019 f->shaderInt8 = true;
1020
1021 f->descriptorIndexing = true;
1022 f->shaderInputAttachmentArrayDynamicIndexing = true;
1023 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1024 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1025 f->shaderUniformBufferArrayNonUniformIndexing = true;
1026 f->shaderSampledImageArrayNonUniformIndexing = true;
1027 f->shaderStorageBufferArrayNonUniformIndexing = true;
1028 f->shaderStorageImageArrayNonUniformIndexing = true;
1029 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1030 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1031 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1032 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1033 f->descriptorBindingSampledImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageImageUpdateAfterBind = true;
1035 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1036 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1038 f->descriptorBindingUpdateUnusedWhilePending = true;
1039 f->descriptorBindingPartiallyBound = true;
1040 f->descriptorBindingVariableDescriptorCount = true;
1041 f->runtimeDescriptorArray = true;
1042
1043 f->samplerFilterMinmax = true;
1044 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 f->imagelessFramebuffer = true;
1046 f->uniformBufferStandardLayout = true;
1047 f->shaderSubgroupExtendedTypes = true;
1048 f->separateDepthStencilLayouts = true;
1049 f->hostQueryReset = true;
1050 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1051 f->bufferDeviceAddress = true;
1052 f->bufferDeviceAddressCaptureReplay = false;
1053 f->bufferDeviceAddressMultiDevice = false;
1054 f->vulkanMemoryModel = true;
1055 f->vulkanMemoryModelDeviceScope = true;
1056 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1057 f->shaderOutputViewportIndex = true;
1058 f->shaderOutputLayer = true;
1059 f->subgroupBroadcastDynamicId = true;
1060 }
1061
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice,
1064 VkPhysicalDeviceFeatures2 *pFeatures)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1068
1069 VkPhysicalDeviceVulkan11Features core_1_1 = {
1070 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1071 };
1072 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1073
1074 VkPhysicalDeviceVulkan12Features core_1_2 = {
1075 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1076 };
1077 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1078
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1081
1082 vk_foreach_struct(ext, pFeatures->pNext) {
1083 switch (ext->sType) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1085 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1087 CORE_FEATURE(1, 1, variablePointers);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1091 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1092 CORE_FEATURE(1, 1, multiview);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader);
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1099 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1100 CORE_FEATURE(1, 1, shaderDrawParameters);
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1104 VkPhysicalDeviceProtectedMemoryFeatures *features =
1105 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1106 CORE_FEATURE(1, 1, protectedMemory);
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1110 VkPhysicalDevice16BitStorageFeatures *features =
1111 (VkPhysicalDevice16BitStorageFeatures*)ext;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1114 CORE_FEATURE(1, 1, storagePushConstant16);
1115 CORE_FEATURE(1, 1, storageInputOutput16);
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1126 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1152 features->conditionalRendering = true;
1153 features->inheritedConditionalRendering = false;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1159 features->vertexAttributeInstanceRateDivisor = true;
1160 features->vertexAttributeInstanceRateZeroDivisor = true;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1166 features->transformFeedback = true;
1167 features->geometryStreams = !pdevice->use_ngg_streamout;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1173 CORE_FEATURE(1, 2, scalarBlockLayout);
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1179 features->memoryPriority = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1185 features->bufferDeviceAddress = true;
1186 features->bufferDeviceAddressCaptureReplay = false;
1187 features->bufferDeviceAddressMultiDevice = false;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1201 features->depthClipEnable = true;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1205 VkPhysicalDeviceHostQueryResetFeatures *features =
1206 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1207 CORE_FEATURE(1, 2, hostQueryReset);
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1211 VkPhysicalDevice8BitStorageFeatures *features =
1212 (VkPhysicalDevice8BitStorageFeatures *)ext;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1215 CORE_FEATURE(1, 2, storagePushConstant8);
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1219 VkPhysicalDeviceShaderFloat16Int8Features *features =
1220 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1221 CORE_FEATURE(1, 2, shaderFloat16);
1222 CORE_FEATURE(1, 2, shaderInt8);
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1226 VkPhysicalDeviceShaderAtomicInt64Features *features =
1227 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1235 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1241
1242 features->inlineUniformBlock = true;
1243 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1249 features->computeDerivativeGroupQuads = false;
1250 features->computeDerivativeGroupLinear = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1256 features->ycbcrImageArrays = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1268 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1273 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer);
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1280 features->pipelineExecutableInfo = true;
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1285 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1286 features->shaderSubgroupClock = true;
1287 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1293 features->texelBufferAlignment = true;
1294 break;
1295 }
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1299 CORE_FEATURE(1, 2, timelineSemaphore);
1300 break;
1301 }
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1305 features->subgroupSizeControl = true;
1306 features->computeFullSubgroups = true;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1312 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1328 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1332 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1338 features->rectangularLines = false;
1339 features->bresenhamLines = true;
1340 features->smoothLines = false;
1341 features->stippledRectangularLines = false;
1342 features->stippledBresenhamLines = true;
1343 features->stippledSmoothLines = false;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1348 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1349 features->overallocationBehavior = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1354 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1355 features->robustBufferAccess2 = true;
1356 features->robustImageAccess2 = true;
1357 features->nullDescriptor = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1363 features->customBorderColors = true;
1364 features->customBorderColorWithoutFormat = true;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1369 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1370 features->privateData = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1376 features-> pipelineCreationCacheControl = true;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1390 features->extendedDynamicState = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1396 features->robustImageAccess = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1402 features->shaderBufferFloat32Atomics = true;
1403 features->shaderBufferFloat32AtomicAdd = false;
1404 features->shaderBufferFloat64Atomics = true;
1405 features->shaderBufferFloat64AtomicAdd = false;
1406 features->shaderSharedFloat32Atomics = true;
1407 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1408 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1409 features->shaderSharedFloat64Atomics = true;
1410 features->shaderSharedFloat64AtomicAdd = false;
1411 features->shaderImageFloat32Atomics = true;
1412 features->shaderImageFloat32AtomicAdd = false;
1413 features->sparseImageFloat32Atomics = false;
1414 features->sparseImageFloat32AtomicAdd = false;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1419 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1420 features->formatA4R4G4B4 = true;
1421 features->formatA4B4G4R4 = true;
1422 break;
1423 }
1424 default:
1425 break;
1426 }
1427 }
1428 #undef CORE_FEATURE
1429 }
1430
1431 static size_t
1432 radv_max_descriptor_set_size()
1433 {
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1447 }
1448
1449 static uint32_t
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1451 {
1452 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1455 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment);
1457 uniform_offset_alignment = 0;
1458 }
1459
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment, 4);
1462 }
1463
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceProperties* pProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1469 VkSampleCountFlags sample_counts = 0xf;
1470
1471 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1472
1473 VkPhysicalDeviceLimits limits = {
1474 .maxImageDimension1D = (1 << 14),
1475 .maxImageDimension2D = (1 << 14),
1476 .maxImageDimension3D = (1 << 11),
1477 .maxImageDimensionCube = (1 << 14),
1478 .maxImageArrayLayers = (1 << 11),
1479 .maxTexelBufferElements = UINT32_MAX,
1480 .maxUniformBufferRange = UINT32_MAX,
1481 .maxStorageBufferRange = UINT32_MAX,
1482 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1483 .maxMemoryAllocationCount = UINT32_MAX,
1484 .maxSamplerAllocationCount = 64 * 1024,
1485 .bufferImageGranularity = 64, /* A cache line */
1486 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1487 .maxBoundDescriptorSets = MAX_SETS,
1488 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1489 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1490 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1491 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1492 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1493 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1494 .maxPerStageResources = max_descriptor_set_size,
1495 .maxDescriptorSetSamplers = max_descriptor_set_size,
1496 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1497 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1498 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1499 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1500 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1501 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1502 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1503 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1504 .maxVertexInputBindings = MAX_VBS,
1505 .maxVertexInputAttributeOffset = 2047,
1506 .maxVertexInputBindingStride = 2048,
1507 .maxVertexOutputComponents = 128,
1508 .maxTessellationGenerationLevel = 64,
1509 .maxTessellationPatchSize = 32,
1510 .maxTessellationControlPerVertexInputComponents = 128,
1511 .maxTessellationControlPerVertexOutputComponents = 128,
1512 .maxTessellationControlPerPatchOutputComponents = 120,
1513 .maxTessellationControlTotalOutputComponents = 4096,
1514 .maxTessellationEvaluationInputComponents = 128,
1515 .maxTessellationEvaluationOutputComponents = 128,
1516 .maxGeometryShaderInvocations = 127,
1517 .maxGeometryInputComponents = 64,
1518 .maxGeometryOutputComponents = 128,
1519 .maxGeometryOutputVertices = 256,
1520 .maxGeometryTotalOutputComponents = 1024,
1521 .maxFragmentInputComponents = 128,
1522 .maxFragmentOutputAttachments = 8,
1523 .maxFragmentDualSrcAttachments = 1,
1524 .maxFragmentCombinedOutputResources = 8,
1525 .maxComputeSharedMemorySize = 32768,
1526 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations = 1024,
1528 .maxComputeWorkGroupSize = {
1529 1024,
1530 1024,
1531 1024
1532 },
1533 .subPixelPrecisionBits = 8,
1534 .subTexelPrecisionBits = 8,
1535 .mipmapPrecisionBits = 8,
1536 .maxDrawIndexedIndexValue = UINT32_MAX,
1537 .maxDrawIndirectCount = UINT32_MAX,
1538 .maxSamplerLodBias = 16,
1539 .maxSamplerAnisotropy = 16,
1540 .maxViewports = MAX_VIEWPORTS,
1541 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1543 .viewportSubPixelBits = 8,
1544 .minMemoryMapAlignment = 4096, /* A page */
1545 .minTexelBufferOffsetAlignment = 4,
1546 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1547 .minStorageBufferOffsetAlignment = 4,
1548 .minTexelOffset = -32,
1549 .maxTexelOffset = 31,
1550 .minTexelGatherOffset = -32,
1551 .maxTexelGatherOffset = 31,
1552 .minInterpolationOffset = -2,
1553 .maxInterpolationOffset = 2,
1554 .subPixelInterpolationOffsetBits = 8,
1555 .maxFramebufferWidth = (1 << 14),
1556 .maxFramebufferHeight = (1 << 14),
1557 .maxFramebufferLayers = (1 << 10),
1558 .framebufferColorSampleCounts = sample_counts,
1559 .framebufferDepthSampleCounts = sample_counts,
1560 .framebufferStencilSampleCounts = sample_counts,
1561 .framebufferNoAttachmentsSampleCounts = sample_counts,
1562 .maxColorAttachments = MAX_RTS,
1563 .sampledImageColorSampleCounts = sample_counts,
1564 .sampledImageIntegerSampleCounts = sample_counts,
1565 .sampledImageDepthSampleCounts = sample_counts,
1566 .sampledImageStencilSampleCounts = sample_counts,
1567 .storageImageSampleCounts = sample_counts,
1568 .maxSampleMaskWords = 1,
1569 .timestampComputeAndGraphics = true,
1570 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1571 .maxClipDistances = 8,
1572 .maxCullDistances = 8,
1573 .maxCombinedClipAndCullDistances = 8,
1574 .discreteQueuePriorities = 2,
1575 .pointSizeRange = { 0.0, 8191.875 },
1576 .lineWidthRange = { 0.0, 8191.875 },
1577 .pointSizeGranularity = (1.0 / 8.0),
1578 .lineWidthGranularity = (1.0 / 8.0),
1579 .strictLines = false, /* FINISHME */
1580 .standardSampleLocations = true,
1581 .optimalBufferCopyOffsetAlignment = 128,
1582 .optimalBufferCopyRowPitchAlignment = 128,
1583 .nonCoherentAtomSize = 64,
1584 };
1585
1586 *pProperties = (VkPhysicalDeviceProperties) {
1587 .apiVersion = radv_physical_device_api_version(pdevice),
1588 .driverVersion = vk_get_driver_version(),
1589 .vendorID = ATI_VENDOR_ID,
1590 .deviceID = pdevice->rad_info.pci_id,
1591 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1592 .limits = limits,
1593 .sparseProperties = {0},
1594 };
1595
1596 strcpy(pProperties->deviceName, pdevice->name);
1597 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1598 }
1599
1600 static void
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1602 VkPhysicalDeviceVulkan11Properties *p)
1603 {
1604 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1605
1606 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1607 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1608 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1609 /* The LUID is for Windows. */
1610 p->deviceLUIDValid = false;
1611 p->deviceNodeMask = 0;
1612
1613 p->subgroupSize = RADV_SUBGROUP_SIZE;
1614 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1615 VK_SHADER_STAGE_COMPUTE_BIT;
1616 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1617 VK_SUBGROUP_FEATURE_VOTE_BIT |
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1621 VK_SUBGROUP_FEATURE_QUAD_BIT |
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1624 p->subgroupQuadOperationsInAllStages = true;
1625
1626 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1627 p->maxMultiviewViewCount = MAX_VIEWS;
1628 p->maxMultiviewInstanceIndex = INT_MAX;
1629 p->protectedNoFault = false;
1630 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1631 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1632 }
1633
1634 static void
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1636 VkPhysicalDeviceVulkan12Properties *p)
1637 {
1638 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1639
1640 p->driverID = VK_DRIVER_ID_MESA_RADV;
1641 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1642 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1644 radv_get_compiler_string(pdevice));
1645 p->conformanceVersion = (VkConformanceVersion) {
1646 .major = 1,
1647 .minor = 2,
1648 .subminor = 3,
1649 .patch = 0,
1650 };
1651
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1654 */
1655 if (pdevice->rad_info.has_packed_math_16bit) {
1656 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1657 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1658 } else {
1659 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1660 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1661 }
1662
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1668 * register.
1669 */
1670 p->shaderDenormFlushToZeroFloat32 = true;
1671 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1672 p->shaderRoundingModeRTEFloat32 = true;
1673 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1674 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1675
1676 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1677 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1678 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1679 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1680 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1681
1682 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1683 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1684 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1685 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1686 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1687
1688 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1689 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1690 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1691 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1692 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1693 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1694 p->robustBufferAccessUpdateAfterBind = false;
1695 p->quadDivergentImplicitLod = false;
1696
1697 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1705 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1706 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1707 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1708 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1709 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1710 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1711 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1712 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1713 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1714 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1715 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1716 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1717 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1718 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1719
1720 /* We support all of the depth resolve modes */
1721 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1723 VK_RESOLVE_MODE_MIN_BIT_KHR |
1724 VK_RESOLVE_MODE_MAX_BIT_KHR;
1725
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1728 VK_RESOLVE_MODE_MIN_BIT_KHR |
1729 VK_RESOLVE_MODE_MAX_BIT_KHR;
1730
1731 p->independentResolveNone = true;
1732 p->independentResolve = true;
1733
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1736 p->filterMinmaxSingleComponentFormats = true;
1737
1738 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1739
1740 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1741 }
1742
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice,
1745 VkPhysicalDeviceProperties2 *pProperties)
1746 {
1747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1749
1750 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1751 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1752 };
1753 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1754
1755 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1756 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1757 };
1758 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1759
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1763
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1766
1767 vk_foreach_struct(ext, pProperties->pNext) {
1768 switch (ext->sType) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1772 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1776 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1777 CORE_PROPERTY(1, 1, deviceUUID);
1778 CORE_PROPERTY(1, 1, driverUUID);
1779 CORE_PROPERTY(1, 1, deviceLUID);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid);
1781 break;
1782 }
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1784 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1787 break;
1788 }
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1790 VkPhysicalDevicePointClippingProperties *properties =
1791 (VkPhysicalDevicePointClippingProperties*)ext;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior);
1793 break;
1794 }
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1798 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1799 break;
1800 }
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1804 properties->minImportedHostPointerAlignment = 4096;
1805 break;
1806 }
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1808 VkPhysicalDeviceSubgroupProperties *properties =
1809 (VkPhysicalDeviceSubgroupProperties*)ext;
1810 CORE_PROPERTY(1, 1, subgroupSize);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1812 subgroupSupportedStages);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1814 subgroupSupportedOperations);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1816 subgroupQuadOperationsInAllStages);
1817 break;
1818 }
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1820 VkPhysicalDeviceMaintenance3Properties *properties =
1821 (VkPhysicalDeviceMaintenance3Properties*)ext;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1824 break;
1825 }
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1831 break;
1832 }
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1835 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1836
1837 /* Shader engines. */
1838 properties->shaderEngineCount =
1839 pdevice->rad_info.max_se;
1840 properties->shaderArraysPerEngineCount =
1841 pdevice->rad_info.max_sh_per_se;
1842 properties->computeUnitsPerShaderArray =
1843 pdevice->rad_info.min_good_cu_per_sa;
1844 properties->simdPerComputeUnit =
1845 pdevice->rad_info.num_simd_per_compute_unit;
1846 properties->wavefrontsPerSimd =
1847 pdevice->rad_info.max_wave64_per_simd;
1848 properties->wavefrontSize = 64;
1849
1850 /* SGPR. */
1851 properties->sgprsPerSimd =
1852 pdevice->rad_info.num_physical_sgprs_per_simd;
1853 properties->minSgprAllocation =
1854 pdevice->rad_info.min_sgpr_alloc;
1855 properties->maxSgprAllocation =
1856 pdevice->rad_info.max_sgpr_alloc;
1857 properties->sgprAllocationGranularity =
1858 pdevice->rad_info.sgpr_alloc_granularity;
1859
1860 /* VGPR. */
1861 properties->vgprsPerSimd =
1862 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1863 properties->minVgprAllocation =
1864 pdevice->rad_info.min_wave64_vgpr_alloc;
1865 properties->maxVgprAllocation =
1866 pdevice->rad_info.max_vgpr_alloc;
1867 properties->vgprAllocationGranularity =
1868 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1873 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1874
1875 properties->shaderCoreFeatures = 0;
1876 properties->activeComputeUnitCount =
1877 pdevice->rad_info.num_good_compute_units;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1883 properties->maxVertexAttribDivisor = UINT32_MAX;
1884 break;
1885 }
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1887 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1888 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1912 break;
1913 }
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1915 VkPhysicalDeviceProtectedMemoryProperties *properties =
1916 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1917 CORE_PROPERTY(1, 1, protectedNoFault);
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1923 properties->primitiveOverestimationSize = 0;
1924 properties->maxExtraPrimitiveOverestimationSize = 0;
1925 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1926 properties->primitiveUnderestimation = false;
1927 properties->conservativePointAndLineRasterization = false;
1928 properties->degenerateTrianglesRasterized = false;
1929 properties->degenerateLinesRasterized = false;
1930 properties->fullyCoveredFragmentShaderInputVariable = false;
1931 properties->conservativeRasterizationPostDepthCoverage = false;
1932 break;
1933 }
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1937 properties->pciDomain = pdevice->bus_info.domain;
1938 properties->pciBus = pdevice->bus_info.bus;
1939 properties->pciDevice = pdevice->bus_info.dev;
1940 properties->pciFunction = pdevice->bus_info.func;
1941 break;
1942 }
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1944 VkPhysicalDeviceDriverProperties *properties =
1945 (VkPhysicalDeviceDriverProperties *) ext;
1946 CORE_PROPERTY(1, 2, driverID);
1947 CORE_PROPERTY(1, 2, driverName);
1948 CORE_PROPERTY(1, 2, driverInfo);
1949 CORE_PROPERTY(1, 2, conformanceVersion);
1950 break;
1951 }
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1955 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1956 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1957 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1958 properties->maxTransformFeedbackStreamDataSize = 512;
1959 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1960 properties->maxTransformFeedbackBufferDataStride = 512;
1961 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1962 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1963 properties->transformFeedbackRasterizationStreamSelect = false;
1964 properties->transformFeedbackDraw = true;
1965 break;
1966 }
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1970
1971 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1972 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1973 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1974 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1975 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1976 break;
1977 }
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1981 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1982 VK_SAMPLE_COUNT_4_BIT |
1983 VK_SAMPLE_COUNT_8_BIT;
1984 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1985 properties->sampleLocationCoordinateRange[0] = 0.0f;
1986 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1987 properties->sampleLocationSubPixelBits = 4;
1988 properties->variableSampleLocations = false;
1989 break;
1990 }
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1992 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1993 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1996 CORE_PROPERTY(1, 2, independentResolveNone);
1997 CORE_PROPERTY(1, 2, independentResolve);
1998 break;
1999 }
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
2003 properties->storageTexelBufferOffsetAlignmentBytes = 4;
2004 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
2005 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
2006 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
2007 break;
2008 }
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2010 VkPhysicalDeviceFloatControlsProperties *properties =
2011 (VkPhysicalDeviceFloatControlsProperties *)ext;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2029 break;
2030 }
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2033 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2035 break;
2036 }
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2040 props->minSubgroupSize = 64;
2041 props->maxSubgroupSize = 64;
2042 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2043 props->requiredSubgroupSizeStages = 0;
2044
2045 if (pdevice->rad_info.chip_class >= GFX10) {
2046 /* Only GFX10+ supports wave32. */
2047 props->minSubgroupSize = 32;
2048 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2049 }
2050 break;
2051 }
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2053 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2054 break;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2056 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2057 break;
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2061 props->lineSubPixelPrecisionBits = 4;
2062 break;
2063 }
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2066 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2067 properties->robustStorageBufferAccessSizeAlignment = 4;
2068 properties->robustUniformBufferAccessSizeAlignment = 4;
2069 break;
2070 }
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2074 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2075 break;
2076 }
2077 default:
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device* pdevice,
2085 uint32_t* pCount,
2086 VkQueueFamilyProperties** pQueueFamilyProperties)
2087 {
2088 int num_queue_families = 1;
2089 int idx;
2090 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2091 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2092 num_queue_families++;
2093
2094 if (pQueueFamilyProperties == NULL) {
2095 *pCount = num_queue_families;
2096 return;
2097 }
2098
2099 if (!*pCount)
2100 return;
2101
2102 idx = 0;
2103 if (*pCount >= 1) {
2104 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2105 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2106 VK_QUEUE_COMPUTE_BIT |
2107 VK_QUEUE_TRANSFER_BIT |
2108 VK_QUEUE_SPARSE_BINDING_BIT,
2109 .queueCount = 1,
2110 .timestampValidBits = 64,
2111 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2112 };
2113 idx++;
2114 }
2115
2116 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2117 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2118 if (*pCount > idx) {
2119 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2120 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2121 VK_QUEUE_TRANSFER_BIT |
2122 VK_QUEUE_SPARSE_BINDING_BIT,
2123 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2124 .timestampValidBits = 64,
2125 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2126 };
2127 idx++;
2128 }
2129 }
2130 *pCount = idx;
2131 }
2132
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice,
2135 uint32_t* pCount,
2136 VkQueueFamilyProperties* pQueueFamilyProperties)
2137 {
2138 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2139 if (!pQueueFamilyProperties) {
2140 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2141 return;
2142 }
2143 VkQueueFamilyProperties *properties[] = {
2144 pQueueFamilyProperties + 0,
2145 pQueueFamilyProperties + 1,
2146 pQueueFamilyProperties + 2,
2147 };
2148 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2149 assert(*pCount <= 3);
2150 }
2151
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice,
2154 uint32_t* pCount,
2155 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2156 {
2157 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2158 if (!pQueueFamilyProperties) {
2159 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2160 return;
2161 }
2162 VkQueueFamilyProperties *properties[] = {
2163 &pQueueFamilyProperties[0].queueFamilyProperties,
2164 &pQueueFamilyProperties[1].queueFamilyProperties,
2165 &pQueueFamilyProperties[2].queueFamilyProperties,
2166 };
2167 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2168 assert(*pCount <= 3);
2169 }
2170
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice,
2173 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2174 {
2175 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2176
2177 *pMemoryProperties = physical_device->memory_properties;
2178 }
2179
2180 static void
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2183 {
2184 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2185 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2186 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2187 uint64_t vram_size = radv_get_vram_size(device);
2188 uint64_t gtt_size = device->rad_info.gart_size;
2189 uint64_t heap_budget, heap_usage;
2190
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2193 *
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2196 *
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2199 */
2200 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2201 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2202
2203 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM);
2206
2207 heap_budget = vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2214 heap_usage = device->ws->query_value(device->ws,
2215 RADEON_ALLOCATED_VRAM_VIS);
2216
2217 heap_budget = visible_vram_size -
2218 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2219 heap_usage;
2220
2221 memoryBudget->heapBudget[heap_index] = heap_budget;
2222 memoryBudget->heapUsage[heap_index] = heap_usage;
2223 } else {
2224 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2225
2226 heap_usage = device->ws->query_value(device->ws,
2227 RADEON_ALLOCATED_GTT);
2228
2229 heap_budget = gtt_size -
2230 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2231 heap_usage;
2232
2233 memoryBudget->heapBudget[heap_index] = heap_budget;
2234 memoryBudget->heapUsage[heap_index] = heap_usage;
2235 }
2236 }
2237
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2241 */
2242 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2243 memoryBudget->heapBudget[i] = 0;
2244 memoryBudget->heapUsage[i] = 0;
2245 }
2246 }
2247
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice,
2250 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2251 {
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2253 &pMemoryProperties->memoryProperties);
2254
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2256 vk_find_struct(pMemoryProperties->pNext,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2258 if (memory_budget)
2259 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2260 }
2261
2262 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2263 VkDevice _device,
2264 VkExternalMemoryHandleTypeFlagBits handleType,
2265 const void *pHostPointer,
2266 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2267 {
2268 RADV_FROM_HANDLE(radv_device, device, _device);
2269
2270 switch (handleType)
2271 {
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2273 const struct radv_physical_device *physical_device = device->physical_device;
2274 uint32_t memoryTypeBits = 0;
2275 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2276 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2277 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2278 memoryTypeBits = (1 << i);
2279 break;
2280 }
2281 }
2282 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2283 return VK_SUCCESS;
2284 }
2285 default:
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2287 }
2288 }
2289
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2292 {
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2294 if (!pObj)
2295 return RADEON_CTX_PRIORITY_MEDIUM;
2296
2297 switch(pObj->globalPriority) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2299 return RADEON_CTX_PRIORITY_REALTIME;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2301 return RADEON_CTX_PRIORITY_HIGH;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2303 return RADEON_CTX_PRIORITY_MEDIUM;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2305 return RADEON_CTX_PRIORITY_LOW;
2306 default:
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID;
2309 }
2310 }
2311
2312 static int
2313 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2314 uint32_t queue_family_index, int idx,
2315 VkDeviceQueueCreateFlags flags,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2317 {
2318 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2319 queue->device = device;
2320 queue->queue_family_index = queue_family_index;
2321 queue->queue_idx = idx;
2322 queue->priority = radv_get_queue_global_priority(global_priority);
2323 queue->flags = flags;
2324 queue->hw_ctx = NULL;
2325
2326 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 list_inithead(&queue->pending_submissions);
2331 pthread_mutex_init(&queue->pending_mutex, NULL);
2332
2333 pthread_mutex_init(&queue->thread_mutex, NULL);
2334 queue->thread_submission = NULL;
2335 queue->thread_running = queue->thread_exit = false;
2336 result = radv_create_pthread_cond(&queue->thread_cond);
2337 if (result != VK_SUCCESS)
2338 return vk_error(device->instance, result);
2339
2340 return VK_SUCCESS;
2341 }
2342
2343 static void
2344 radv_queue_finish(struct radv_queue *queue)
2345 {
2346 if (queue->thread_running) {
2347 p_atomic_set(&queue->thread_exit, true);
2348 pthread_cond_broadcast(&queue->thread_cond);
2349 pthread_join(queue->submission_thread, NULL);
2350 }
2351 pthread_cond_destroy(&queue->thread_cond);
2352 pthread_mutex_destroy(&queue->pending_mutex);
2353 pthread_mutex_destroy(&queue->thread_mutex);
2354
2355 if (queue->hw_ctx)
2356 queue->device->ws->ctx_destroy(queue->hw_ctx);
2357
2358 if (queue->initial_full_flush_preamble_cs)
2359 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2360 if (queue->initial_preamble_cs)
2361 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2362 if (queue->continue_preamble_cs)
2363 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2364 if (queue->descriptor_bo)
2365 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2366 if (queue->scratch_bo)
2367 queue->device->ws->buffer_destroy(queue->scratch_bo);
2368 if (queue->esgs_ring_bo)
2369 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2370 if (queue->gsvs_ring_bo)
2371 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2372 if (queue->tess_rings_bo)
2373 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2374 if (queue->gds_bo)
2375 queue->device->ws->buffer_destroy(queue->gds_bo);
2376 if (queue->gds_oa_bo)
2377 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2378 if (queue->compute_scratch_bo)
2379 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2380 }
2381
2382 static void
2383 radv_bo_list_init(struct radv_bo_list *bo_list)
2384 {
2385 pthread_mutex_init(&bo_list->mutex, NULL);
2386 bo_list->list.count = bo_list->capacity = 0;
2387 bo_list->list.bos = NULL;
2388 }
2389
2390 static void
2391 radv_bo_list_finish(struct radv_bo_list *bo_list)
2392 {
2393 free(bo_list->list.bos);
2394 pthread_mutex_destroy(&bo_list->mutex);
2395 }
2396
2397 VkResult radv_bo_list_add(struct radv_device *device,
2398 struct radeon_winsys_bo *bo)
2399 {
2400 struct radv_bo_list *bo_list = &device->bo_list;
2401
2402 if (bo->is_local)
2403 return VK_SUCCESS;
2404
2405 if (unlikely(!device->use_global_bo_list))
2406 return VK_SUCCESS;
2407
2408 pthread_mutex_lock(&bo_list->mutex);
2409 if (bo_list->list.count == bo_list->capacity) {
2410 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2411 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2412
2413 if (!data) {
2414 pthread_mutex_unlock(&bo_list->mutex);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2419 bo_list->capacity = capacity;
2420 }
2421
2422 bo_list->list.bos[bo_list->list.count++] = bo;
2423 pthread_mutex_unlock(&bo_list->mutex);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_bo_list_remove(struct radv_device *device,
2428 struct radeon_winsys_bo *bo)
2429 {
2430 struct radv_bo_list *bo_list = &device->bo_list;
2431
2432 if (bo->is_local)
2433 return;
2434
2435 if (unlikely(!device->use_global_bo_list))
2436 return;
2437
2438 pthread_mutex_lock(&bo_list->mutex);
2439 /* Loop the list backwards so we find the most recently added
2440 * memory first. */
2441 for(unsigned i = bo_list->list.count; i-- > 0;) {
2442 if (bo_list->list.bos[i] == bo) {
2443 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2444 --bo_list->list.count;
2445 break;
2446 }
2447 }
2448 pthread_mutex_unlock(&bo_list->mutex);
2449 }
2450
2451 static void
2452 radv_device_init_gs_info(struct radv_device *device)
2453 {
2454 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2455 device->physical_device->rad_info.family);
2456 }
2457
2458 static int radv_get_device_extension_index(const char *name)
2459 {
2460 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2461 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2462 return i;
2463 }
2464 return -1;
2465 }
2466
2467 static int
2468 radv_get_int_debug_option(const char *name, int default_value)
2469 {
2470 const char *str;
2471 int result;
2472
2473 str = getenv(name);
2474 if (!str) {
2475 result = default_value;
2476 } else {
2477 char *endptr;
2478
2479 result = strtol(str, &endptr, 0);
2480 if (str == endptr) {
2481 /* No digits founs. */
2482 result = default_value;
2483 }
2484 }
2485
2486 return result;
2487 }
2488
2489 static void
2490 radv_device_init_dispatch(struct radv_device *device)
2491 {
2492 const struct radv_instance *instance = device->physical_device->instance;
2493 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2494 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2495 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2496
2497 if (radv_thread_trace >= 0) {
2498 /* Use device entrypoints from the SQTT layer if enabled. */
2499 dispatch_table_layer = &sqtt_device_dispatch_table;
2500 }
2501
2502 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2503 /* Vulkan requires that entrypoints for extensions which have not been
2504 * enabled must not be advertised.
2505 */
2506 if (!unchecked &&
2507 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2508 &instance->enabled_extensions,
2509 &device->enabled_extensions)) {
2510 device->dispatch.entrypoints[i] = NULL;
2511 } else if (dispatch_table_layer &&
2512 dispatch_table_layer->entrypoints[i]) {
2513 device->dispatch.entrypoints[i] =
2514 dispatch_table_layer->entrypoints[i];
2515 } else {
2516 device->dispatch.entrypoints[i] =
2517 radv_device_dispatch_table.entrypoints[i];
2518 }
2519 }
2520 }
2521
2522 static VkResult
2523 radv_create_pthread_cond(pthread_cond_t *cond)
2524 {
2525 pthread_condattr_t condattr;
2526 if (pthread_condattr_init(&condattr)) {
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529
2530 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2531 pthread_condattr_destroy(&condattr);
2532 return VK_ERROR_INITIALIZATION_FAILED;
2533 }
2534 if (pthread_cond_init(cond, &condattr)) {
2535 pthread_condattr_destroy(&condattr);
2536 return VK_ERROR_INITIALIZATION_FAILED;
2537 }
2538 pthread_condattr_destroy(&condattr);
2539 return VK_SUCCESS;
2540 }
2541
2542 static VkResult
2543 check_physical_device_features(VkPhysicalDevice physicalDevice,
2544 const VkPhysicalDeviceFeatures *features)
2545 {
2546 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2547 VkPhysicalDeviceFeatures supported_features;
2548 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2549 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2550 VkBool32 *enabled_feature = (VkBool32 *)features;
2551 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2552 for (uint32_t i = 0; i < num_features; i++) {
2553 if (enabled_feature[i] && !supported_feature[i])
2554 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2555 }
2556
2557 return VK_SUCCESS;
2558 }
2559
2560 static VkResult radv_device_init_border_color(struct radv_device *device)
2561 {
2562 device->border_color_data.bo =
2563 device->ws->buffer_create(device->ws,
2564 RADV_BORDER_COLOR_BUFFER_SIZE,
2565 4096,
2566 RADEON_DOMAIN_VRAM,
2567 RADEON_FLAG_CPU_ACCESS |
2568 RADEON_FLAG_READ_ONLY |
2569 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2570 RADV_BO_PRIORITY_SHADER);
2571
2572 if (device->border_color_data.bo == NULL)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574
2575 device->border_color_data.colors_gpu_ptr =
2576 device->ws->buffer_map(device->border_color_data.bo);
2577 if (!device->border_color_data.colors_gpu_ptr)
2578 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2579 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2580
2581 return VK_SUCCESS;
2582 }
2583
2584 static void radv_device_finish_border_color(struct radv_device *device)
2585 {
2586 if (device->border_color_data.bo) {
2587 device->ws->buffer_destroy(device->border_color_data.bo);
2588
2589 pthread_mutex_destroy(&device->border_color_data.mutex);
2590 }
2591 }
2592
2593 VkResult
2594 _radv_device_set_lost(struct radv_device *device,
2595 const char *file, int line,
2596 const char *msg, ...)
2597 {
2598 VkResult err;
2599 va_list ap;
2600
2601 p_atomic_inc(&device->lost);
2602
2603 va_start(ap, msg);
2604 err = __vk_errorv(device->physical_device->instance, device,
2605 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2606 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2607 va_end(ap);
2608
2609 return err;
2610 }
2611
2612 VkResult radv_CreateDevice(
2613 VkPhysicalDevice physicalDevice,
2614 const VkDeviceCreateInfo* pCreateInfo,
2615 const VkAllocationCallbacks* pAllocator,
2616 VkDevice* pDevice)
2617 {
2618 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2619 VkResult result;
2620 struct radv_device *device;
2621
2622 bool keep_shader_info = false;
2623 bool robust_buffer_access = false;
2624 bool overallocation_disallowed = false;
2625 bool custom_border_colors = false;
2626
2627 /* Check enabled features */
2628 if (pCreateInfo->pEnabledFeatures) {
2629 result = check_physical_device_features(physicalDevice,
2630 pCreateInfo->pEnabledFeatures);
2631 if (result != VK_SUCCESS)
2632 return result;
2633
2634 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2635 robust_buffer_access = true;
2636 }
2637
2638 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2639 switch (ext->sType) {
2640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2641 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2642 result = check_physical_device_features(physicalDevice,
2643 &features->features);
2644 if (result != VK_SUCCESS)
2645 return result;
2646
2647 if (features->features.robustBufferAccess)
2648 robust_buffer_access = true;
2649 break;
2650 }
2651 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2652 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2653 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2654 overallocation_disallowed = true;
2655 break;
2656 }
2657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2658 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2659 custom_border_colors = border_color_features->customBorderColors;
2660 break;
2661 }
2662 default:
2663 break;
2664 }
2665 }
2666
2667 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2668 sizeof(*device), 8,
2669 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2670 if (!device)
2671 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2672
2673 vk_device_init(&device->vk, pCreateInfo,
2674 &physical_device->instance->alloc, pAllocator);
2675
2676 device->instance = physical_device->instance;
2677 device->physical_device = physical_device;
2678
2679 device->ws = physical_device->ws;
2680
2681 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2682 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2683 int index = radv_get_device_extension_index(ext_name);
2684 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2685 vk_free(&device->vk.alloc, device);
2686 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2687 }
2688
2689 device->enabled_extensions.extensions[index] = true;
2690 }
2691
2692 radv_device_init_dispatch(device);
2693
2694 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2695
2696 /* With update after bind we can't attach bo's to the command buffer
2697 * from the descriptor set anymore, so we have to use a global BO list.
2698 */
2699 device->use_global_bo_list =
2700 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2701 device->enabled_extensions.EXT_descriptor_indexing ||
2702 device->enabled_extensions.EXT_buffer_device_address ||
2703 device->enabled_extensions.KHR_buffer_device_address;
2704
2705 device->robust_buffer_access = robust_buffer_access;
2706
2707 mtx_init(&device->shader_slab_mutex, mtx_plain);
2708 list_inithead(&device->shader_slabs);
2709
2710 device->overallocation_disallowed = overallocation_disallowed;
2711 mtx_init(&device->overallocation_mutex, mtx_plain);
2712
2713 radv_bo_list_init(&device->bo_list);
2714
2715 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2716 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2717 uint32_t qfi = queue_create->queueFamilyIndex;
2718 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2719 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2720
2721 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2722
2723 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2724 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2725 if (!device->queues[qfi]) {
2726 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2727 goto fail;
2728 }
2729
2730 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2731
2732 device->queue_count[qfi] = queue_create->queueCount;
2733
2734 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2735 result = radv_queue_init(device, &device->queues[qfi][q],
2736 qfi, q, queue_create->flags,
2737 global_priority);
2738 if (result != VK_SUCCESS)
2739 goto fail;
2740 }
2741 }
2742
2743 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2744 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2745
2746 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2747 device->dfsm_allowed = device->pbb_allowed &&
2748 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2749
2750 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2751
2752 /* The maximum number of scratch waves. Scratch space isn't divided
2753 * evenly between CUs. The number is only a function of the number of CUs.
2754 * We can decrease the constant to decrease the scratch buffer size.
2755 *
2756 * sctx->scratch_waves must be >= the maximum possible size of
2757 * 1 threadgroup, so that the hw doesn't hang from being unable
2758 * to start any.
2759 *
2760 * The recommended value is 4 per CU at most. Higher numbers don't
2761 * bring much benefit, but they still occupy chip resources (think
2762 * async compute). I've seen ~2% performance difference between 4 and 32.
2763 */
2764 uint32_t max_threads_per_block = 2048;
2765 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2766 max_threads_per_block / 64);
2767
2768 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2769
2770 if (device->physical_device->rad_info.chip_class >= GFX7) {
2771 /* If the KMD allows it (there is a KMD hw register for it),
2772 * allow launching waves out-of-order.
2773 */
2774 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2775 }
2776
2777 radv_device_init_gs_info(device);
2778
2779 device->tess_offchip_block_dw_size =
2780 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2781
2782 if (getenv("RADV_TRACE_FILE")) {
2783 const char *filename = getenv("RADV_TRACE_FILE");
2784
2785 keep_shader_info = true;
2786
2787 if (!radv_init_trace(device))
2788 goto fail;
2789
2790 fprintf(stderr, "*****************************************************************************\n");
2791 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2792 fprintf(stderr, "*****************************************************************************\n");
2793
2794 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2795 radv_dump_enabled_options(device, stderr);
2796 }
2797
2798 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2799 if (radv_thread_trace >= 0) {
2800 fprintf(stderr, "*************************************************\n");
2801 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2802 fprintf(stderr, "*************************************************\n");
2803
2804 if (device->physical_device->rad_info.chip_class < GFX8) {
2805 fprintf(stderr, "GPU hardware not supported: refer to "
2806 "the RGP documentation for the list of "
2807 "supported GPUs!\n");
2808 abort();
2809 }
2810
2811 /* Default buffer size set to 1MB per SE. */
2812 device->thread_trace_buffer_size =
2813 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2814 device->thread_trace_start_frame = radv_thread_trace;
2815
2816 if (!radv_thread_trace_init(device))
2817 goto fail;
2818 }
2819
2820 if (getenv("RADV_TRAP_HANDLER")) {
2821 /* TODO: Add support for more hardware. */
2822 assert(device->physical_device->rad_info.chip_class == GFX8);
2823
2824 /* To get the disassembly of the faulty shaders, we have to
2825 * keep some shader info around.
2826 */
2827 keep_shader_info = true;
2828
2829 if (!radv_trap_handler_init(device))
2830 goto fail;
2831 }
2832
2833 device->keep_shader_info = keep_shader_info;
2834 result = radv_device_init_meta(device);
2835 if (result != VK_SUCCESS)
2836 goto fail;
2837
2838 radv_device_init_msaa(device);
2839
2840 /* If the border color extension is enabled, let's create the buffer we need. */
2841 if (custom_border_colors) {
2842 result = radv_device_init_border_color(device);
2843 if (result != VK_SUCCESS)
2844 goto fail;
2845 }
2846
2847 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2848 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2849 if (!device->empty_cs[family])
2850 goto fail;
2851
2852 switch (family) {
2853 case RADV_QUEUE_GENERAL:
2854 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2855 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2856 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2857 break;
2858 case RADV_QUEUE_COMPUTE:
2859 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2860 radeon_emit(device->empty_cs[family], 0);
2861 break;
2862 }
2863
2864 result = device->ws->cs_finalize(device->empty_cs[family]);
2865 if (result != VK_SUCCESS)
2866 goto fail;
2867 }
2868
2869 if (device->physical_device->rad_info.chip_class >= GFX7)
2870 cik_create_gfx_config(device);
2871
2872 VkPipelineCacheCreateInfo ci;
2873 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2874 ci.pNext = NULL;
2875 ci.flags = 0;
2876 ci.pInitialData = NULL;
2877 ci.initialDataSize = 0;
2878 VkPipelineCache pc;
2879 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2880 &ci, NULL, &pc);
2881 if (result != VK_SUCCESS)
2882 goto fail_meta;
2883
2884 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2885
2886 result = radv_create_pthread_cond(&device->timeline_cond);
2887 if (result != VK_SUCCESS)
2888 goto fail_mem_cache;
2889
2890 device->force_aniso =
2891 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2892 if (device->force_aniso >= 0) {
2893 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2894 1 << util_logbase2(device->force_aniso));
2895 }
2896
2897 *pDevice = radv_device_to_handle(device);
2898 return VK_SUCCESS;
2899
2900 fail_mem_cache:
2901 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2902 fail_meta:
2903 radv_device_finish_meta(device);
2904 fail:
2905 radv_bo_list_finish(&device->bo_list);
2906
2907 radv_thread_trace_finish(device);
2908
2909 radv_trap_handler_finish(device);
2910
2911 if (device->trace_bo)
2912 device->ws->buffer_destroy(device->trace_bo);
2913
2914 if (device->gfx_init)
2915 device->ws->buffer_destroy(device->gfx_init);
2916
2917 radv_device_finish_border_color(device);
2918
2919 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2920 for (unsigned q = 0; q < device->queue_count[i]; q++)
2921 radv_queue_finish(&device->queues[i][q]);
2922 if (device->queue_count[i])
2923 vk_free(&device->vk.alloc, device->queues[i]);
2924 }
2925
2926 vk_free(&device->vk.alloc, device);
2927 return result;
2928 }
2929
2930 void radv_DestroyDevice(
2931 VkDevice _device,
2932 const VkAllocationCallbacks* pAllocator)
2933 {
2934 RADV_FROM_HANDLE(radv_device, device, _device);
2935
2936 if (!device)
2937 return;
2938
2939 if (device->trace_bo)
2940 device->ws->buffer_destroy(device->trace_bo);
2941
2942 if (device->gfx_init)
2943 device->ws->buffer_destroy(device->gfx_init);
2944
2945 radv_device_finish_border_color(device);
2946
2947 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2948 for (unsigned q = 0; q < device->queue_count[i]; q++)
2949 radv_queue_finish(&device->queues[i][q]);
2950 if (device->queue_count[i])
2951 vk_free(&device->vk.alloc, device->queues[i]);
2952 if (device->empty_cs[i])
2953 device->ws->cs_destroy(device->empty_cs[i]);
2954 }
2955 radv_device_finish_meta(device);
2956
2957 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2958 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2959
2960 radv_trap_handler_finish(device);
2961
2962 radv_destroy_shader_slabs(device);
2963
2964 pthread_cond_destroy(&device->timeline_cond);
2965 radv_bo_list_finish(&device->bo_list);
2966
2967 radv_thread_trace_finish(device);
2968
2969 vk_free(&device->vk.alloc, device);
2970 }
2971
2972 VkResult radv_EnumerateInstanceLayerProperties(
2973 uint32_t* pPropertyCount,
2974 VkLayerProperties* pProperties)
2975 {
2976 if (pProperties == NULL) {
2977 *pPropertyCount = 0;
2978 return VK_SUCCESS;
2979 }
2980
2981 /* None supported at this time */
2982 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2983 }
2984
2985 VkResult radv_EnumerateDeviceLayerProperties(
2986 VkPhysicalDevice physicalDevice,
2987 uint32_t* pPropertyCount,
2988 VkLayerProperties* pProperties)
2989 {
2990 if (pProperties == NULL) {
2991 *pPropertyCount = 0;
2992 return VK_SUCCESS;
2993 }
2994
2995 /* None supported at this time */
2996 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2997 }
2998
2999 void radv_GetDeviceQueue2(
3000 VkDevice _device,
3001 const VkDeviceQueueInfo2* pQueueInfo,
3002 VkQueue* pQueue)
3003 {
3004 RADV_FROM_HANDLE(radv_device, device, _device);
3005 struct radv_queue *queue;
3006
3007 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3008 if (pQueueInfo->flags != queue->flags) {
3009 /* From the Vulkan 1.1.70 spec:
3010 *
3011 * "The queue returned by vkGetDeviceQueue2 must have the same
3012 * flags value from this structure as that used at device
3013 * creation time in a VkDeviceQueueCreateInfo instance. If no
3014 * matching flags were specified at device creation time then
3015 * pQueue will return VK_NULL_HANDLE."
3016 */
3017 *pQueue = VK_NULL_HANDLE;
3018 return;
3019 }
3020
3021 *pQueue = radv_queue_to_handle(queue);
3022 }
3023
3024 void radv_GetDeviceQueue(
3025 VkDevice _device,
3026 uint32_t queueFamilyIndex,
3027 uint32_t queueIndex,
3028 VkQueue* pQueue)
3029 {
3030 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3031 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3032 .queueFamilyIndex = queueFamilyIndex,
3033 .queueIndex = queueIndex
3034 };
3035
3036 radv_GetDeviceQueue2(_device, &info, pQueue);
3037 }
3038
3039 static void
3040 fill_geom_tess_rings(struct radv_queue *queue,
3041 uint32_t *map,
3042 bool add_sample_positions,
3043 uint32_t esgs_ring_size,
3044 struct radeon_winsys_bo *esgs_ring_bo,
3045 uint32_t gsvs_ring_size,
3046 struct radeon_winsys_bo *gsvs_ring_bo,
3047 uint32_t tess_factor_ring_size,
3048 uint32_t tess_offchip_ring_offset,
3049 uint32_t tess_offchip_ring_size,
3050 struct radeon_winsys_bo *tess_rings_bo)
3051 {
3052 uint32_t *desc = &map[4];
3053
3054 if (esgs_ring_bo) {
3055 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3056
3057 /* stride 0, num records - size, add tid, swizzle, elsize4,
3058 index stride 64 */
3059 desc[0] = esgs_va;
3060 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3061 S_008F04_SWIZZLE_ENABLE(true);
3062 desc[2] = esgs_ring_size;
3063 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3064 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3065 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3066 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3067 S_008F0C_INDEX_STRIDE(3) |
3068 S_008F0C_ADD_TID_ENABLE(1);
3069
3070 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3071 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3072 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3073 S_008F0C_RESOURCE_LEVEL(1);
3074 } else {
3075 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3076 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3077 S_008F0C_ELEMENT_SIZE(1);
3078 }
3079
3080 /* GS entry for ES->GS ring */
3081 /* stride 0, num records - size, elsize0,
3082 index stride 0 */
3083 desc[4] = esgs_va;
3084 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3085 desc[6] = esgs_ring_size;
3086 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3087 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3088 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3089 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3090
3091 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3092 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3093 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3094 S_008F0C_RESOURCE_LEVEL(1);
3095 } else {
3096 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3097 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3098 }
3099 }
3100
3101 desc += 8;
3102
3103 if (gsvs_ring_bo) {
3104 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3105
3106 /* VS entry for GS->VS ring */
3107 /* stride 0, num records - size, elsize0,
3108 index stride 0 */
3109 desc[0] = gsvs_va;
3110 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3111 desc[2] = gsvs_ring_size;
3112 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3113 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3114 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3115 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3116
3117 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3118 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3119 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3120 S_008F0C_RESOURCE_LEVEL(1);
3121 } else {
3122 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3123 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3124 }
3125
3126 /* stride gsvs_itemsize, num records 64
3127 elsize 4, index stride 16 */
3128 /* shader will patch stride and desc[2] */
3129 desc[4] = gsvs_va;
3130 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3131 S_008F04_SWIZZLE_ENABLE(1);
3132 desc[6] = 0;
3133 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3134 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3135 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3136 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3137 S_008F0C_INDEX_STRIDE(1) |
3138 S_008F0C_ADD_TID_ENABLE(true);
3139
3140 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3141 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3142 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3143 S_008F0C_RESOURCE_LEVEL(1);
3144 } else {
3145 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3146 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3147 S_008F0C_ELEMENT_SIZE(1);
3148 }
3149
3150 }
3151
3152 desc += 8;
3153
3154 if (tess_rings_bo) {
3155 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3156 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3157
3158 desc[0] = tess_va;
3159 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3160 desc[2] = tess_factor_ring_size;
3161 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3165
3166 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3167 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3168 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3169 S_008F0C_RESOURCE_LEVEL(1);
3170 } else {
3171 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3173 }
3174
3175 desc[4] = tess_offchip_va;
3176 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3177 desc[6] = tess_offchip_ring_size;
3178 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3179 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3180 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3181 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3182
3183 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3184 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3185 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3186 S_008F0C_RESOURCE_LEVEL(1);
3187 } else {
3188 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3189 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3190 }
3191 }
3192
3193 desc += 8;
3194
3195 if (add_sample_positions) {
3196 /* add sample positions after all rings */
3197 memcpy(desc, queue->device->sample_locations_1x, 8);
3198 desc += 2;
3199 memcpy(desc, queue->device->sample_locations_2x, 16);
3200 desc += 4;
3201 memcpy(desc, queue->device->sample_locations_4x, 32);
3202 desc += 8;
3203 memcpy(desc, queue->device->sample_locations_8x, 64);
3204 }
3205 }
3206
3207 static unsigned
3208 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3209 {
3210 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3211 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3212 device->physical_device->rad_info.family != CHIP_STONEY;
3213 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3214 unsigned max_offchip_buffers;
3215 unsigned offchip_granularity;
3216 unsigned hs_offchip_param;
3217
3218 /*
3219 * Per RadeonSI:
3220 * This must be one less than the maximum number due to a hw limitation.
3221 * Various hardware bugs need thGFX7
3222 *
3223 * Per AMDVLK:
3224 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3225 * Gfx7 should limit max_offchip_buffers to 508
3226 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3227 *
3228 * Follow AMDVLK here.
3229 */
3230 if (device->physical_device->rad_info.chip_class >= GFX10) {
3231 max_offchip_buffers_per_se = 256;
3232 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3233 device->physical_device->rad_info.chip_class == GFX7 ||
3234 device->physical_device->rad_info.chip_class == GFX6)
3235 --max_offchip_buffers_per_se;
3236
3237 max_offchip_buffers = max_offchip_buffers_per_se *
3238 device->physical_device->rad_info.max_se;
3239
3240 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3241 * around by setting 4K granularity.
3242 */
3243 if (device->tess_offchip_block_dw_size == 4096) {
3244 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3245 offchip_granularity = V_03093C_X_4K_DWORDS;
3246 } else {
3247 assert(device->tess_offchip_block_dw_size == 8192);
3248 offchip_granularity = V_03093C_X_8K_DWORDS;
3249 }
3250
3251 switch (device->physical_device->rad_info.chip_class) {
3252 case GFX6:
3253 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3254 break;
3255 case GFX7:
3256 case GFX8:
3257 case GFX9:
3258 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3259 break;
3260 case GFX10:
3261 break;
3262 default:
3263 break;
3264 }
3265
3266 *max_offchip_buffers_p = max_offchip_buffers;
3267 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3268 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3269 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3270 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3271 if (device->physical_device->rad_info.chip_class >= GFX8)
3272 --max_offchip_buffers;
3273 hs_offchip_param =
3274 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3275 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3276 } else {
3277 hs_offchip_param =
3278 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3279 }
3280 return hs_offchip_param;
3281 }
3282
3283 static void
3284 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3285 struct radeon_winsys_bo *esgs_ring_bo,
3286 uint32_t esgs_ring_size,
3287 struct radeon_winsys_bo *gsvs_ring_bo,
3288 uint32_t gsvs_ring_size)
3289 {
3290 if (!esgs_ring_bo && !gsvs_ring_bo)
3291 return;
3292
3293 if (esgs_ring_bo)
3294 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3295
3296 if (gsvs_ring_bo)
3297 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3298
3299 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3300 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3301 radeon_emit(cs, esgs_ring_size >> 8);
3302 radeon_emit(cs, gsvs_ring_size >> 8);
3303 } else {
3304 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3305 radeon_emit(cs, esgs_ring_size >> 8);
3306 radeon_emit(cs, gsvs_ring_size >> 8);
3307 }
3308 }
3309
3310 static void
3311 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3312 unsigned hs_offchip_param, unsigned tf_ring_size,
3313 struct radeon_winsys_bo *tess_rings_bo)
3314 {
3315 uint64_t tf_va;
3316
3317 if (!tess_rings_bo)
3318 return;
3319
3320 tf_va = radv_buffer_get_va(tess_rings_bo);
3321
3322 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3323
3324 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3325 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3326 S_030938_SIZE(tf_ring_size / 4));
3327 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3328 tf_va >> 8);
3329
3330 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3331 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3332 S_030984_BASE_HI(tf_va >> 40));
3333 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3334 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3335 S_030944_BASE_HI(tf_va >> 40));
3336 }
3337 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3338 hs_offchip_param);
3339 } else {
3340 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3341 S_008988_SIZE(tf_ring_size / 4));
3342 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3343 tf_va >> 8);
3344 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3345 hs_offchip_param);
3346 }
3347 }
3348
3349 static void
3350 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3351 uint32_t size_per_wave, uint32_t waves,
3352 struct radeon_winsys_bo *scratch_bo)
3353 {
3354 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3355 return;
3356
3357 if (!scratch_bo)
3358 return;
3359
3360 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3361
3362 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3363 S_0286E8_WAVES(waves) |
3364 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3365 }
3366
3367 static void
3368 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3369 uint32_t size_per_wave, uint32_t waves,
3370 struct radeon_winsys_bo *compute_scratch_bo)
3371 {
3372 uint64_t scratch_va;
3373
3374 if (!compute_scratch_bo)
3375 return;
3376
3377 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3378
3379 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3380
3381 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3382 radeon_emit(cs, scratch_va);
3383 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3384 S_008F04_SWIZZLE_ENABLE(1));
3385
3386 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3387 S_00B860_WAVES(waves) |
3388 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3389 }
3390
3391 static void
3392 radv_emit_global_shader_pointers(struct radv_queue *queue,
3393 struct radeon_cmdbuf *cs,
3394 struct radeon_winsys_bo *descriptor_bo)
3395 {
3396 uint64_t va;
3397
3398 if (!descriptor_bo)
3399 return;
3400
3401 va = radv_buffer_get_va(descriptor_bo);
3402
3403 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3404
3405 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3406 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3407 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3408 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3409 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3410
3411 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3412 radv_emit_shader_pointer(queue->device, cs, regs[i],
3413 va, true);
3414 }
3415 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3416 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3417 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3418 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3419 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3420
3421 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3422 radv_emit_shader_pointer(queue->device, cs, regs[i],
3423 va, true);
3424 }
3425 } else {
3426 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3427 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3428 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3429 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3430 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3431 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3432
3433 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3434 radv_emit_shader_pointer(queue->device, cs, regs[i],
3435 va, true);
3436 }
3437 }
3438 }
3439
3440 static void
3441 radv_emit_trap_handler(struct radv_queue *queue,
3442 struct radeon_cmdbuf *cs,
3443 struct radeon_winsys_bo *tma_bo)
3444 {
3445 struct radv_device *device = queue->device;
3446 struct radeon_winsys_bo *tba_bo;
3447 uint64_t tba_va, tma_va;
3448
3449 if (!device->trap_handler_shader || !tma_bo)
3450 return;
3451
3452 tba_bo = device->trap_handler_shader->bo;
3453
3454 tba_va = radv_buffer_get_va(tba_bo) + device->trap_handler_shader->bo_offset;
3455 tma_va = radv_buffer_get_va(tma_bo);
3456
3457 radv_cs_add_buffer(queue->device->ws, cs, tba_bo);
3458 radv_cs_add_buffer(queue->device->ws, cs, tma_bo);
3459
3460 if (queue->queue_family_index == RADV_QUEUE_GENERAL) {
3461 uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS,
3462 R_00B100_SPI_SHADER_TBA_LO_VS,
3463 R_00B200_SPI_SHADER_TBA_LO_GS,
3464 R_00B300_SPI_SHADER_TBA_LO_ES,
3465 R_00B400_SPI_SHADER_TBA_LO_HS,
3466 R_00B500_SPI_SHADER_TBA_LO_LS};
3467
3468 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3469 radeon_set_sh_reg_seq(cs, regs[i], 4);
3470 radeon_emit(cs, tba_va >> 8);
3471 radeon_emit(cs, tba_va >> 40);
3472 radeon_emit(cs, tma_va >> 8);
3473 radeon_emit(cs, tma_va >> 40);
3474 }
3475 } else {
3476 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
3477 radeon_emit(cs, tba_va >> 8);
3478 radeon_emit(cs, tba_va >> 40);
3479 radeon_emit(cs, tma_va >> 8);
3480 radeon_emit(cs, tma_va >> 40);
3481 }
3482 }
3483
3484 static void
3485 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3486 {
3487 struct radv_device *device = queue->device;
3488
3489 if (device->gfx_init) {
3490 uint64_t va = radv_buffer_get_va(device->gfx_init);
3491
3492 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3493 radeon_emit(cs, va);
3494 radeon_emit(cs, va >> 32);
3495 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3496
3497 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3498 } else {
3499 si_emit_graphics(device, cs);
3500 }
3501 }
3502
3503 static void
3504 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3505 {
3506 si_emit_compute(queue->device, cs);
3507 }
3508
3509 static VkResult
3510 radv_get_preamble_cs(struct radv_queue *queue,
3511 uint32_t scratch_size_per_wave,
3512 uint32_t scratch_waves,
3513 uint32_t compute_scratch_size_per_wave,
3514 uint32_t compute_scratch_waves,
3515 uint32_t esgs_ring_size,
3516 uint32_t gsvs_ring_size,
3517 bool needs_tess_rings,
3518 bool needs_gds,
3519 bool needs_gds_oa,
3520 bool needs_sample_positions,
3521 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3522 struct radeon_cmdbuf **initial_preamble_cs,
3523 struct radeon_cmdbuf **continue_preamble_cs)
3524 {
3525 struct radeon_winsys_bo *scratch_bo = NULL;
3526 struct radeon_winsys_bo *descriptor_bo = NULL;
3527 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3528 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3529 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3530 struct radeon_winsys_bo *tess_rings_bo = NULL;
3531 struct radeon_winsys_bo *gds_bo = NULL;
3532 struct radeon_winsys_bo *gds_oa_bo = NULL;
3533 struct radeon_cmdbuf *dest_cs[3] = {0};
3534 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3535 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3536 unsigned max_offchip_buffers;
3537 unsigned hs_offchip_param = 0;
3538 unsigned tess_offchip_ring_offset;
3539 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3540 if (!queue->has_tess_rings) {
3541 if (needs_tess_rings)
3542 add_tess_rings = true;
3543 }
3544 if (!queue->has_gds) {
3545 if (needs_gds)
3546 add_gds = true;
3547 }
3548 if (!queue->has_gds_oa) {
3549 if (needs_gds_oa)
3550 add_gds_oa = true;
3551 }
3552 if (!queue->has_sample_positions) {
3553 if (needs_sample_positions)
3554 add_sample_positions = true;
3555 }
3556 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3557 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3558 &max_offchip_buffers);
3559 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3560 tess_offchip_ring_size = max_offchip_buffers *
3561 queue->device->tess_offchip_block_dw_size * 4;
3562
3563 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3564 if (scratch_size_per_wave)
3565 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3566 else
3567 scratch_waves = 0;
3568
3569 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3570 if (compute_scratch_size_per_wave)
3571 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3572 else
3573 compute_scratch_waves = 0;
3574
3575 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3576 scratch_waves <= queue->scratch_waves &&
3577 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3578 compute_scratch_waves <= queue->compute_scratch_waves &&
3579 esgs_ring_size <= queue->esgs_ring_size &&
3580 gsvs_ring_size <= queue->gsvs_ring_size &&
3581 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3582 queue->initial_preamble_cs) {
3583 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3584 *initial_preamble_cs = queue->initial_preamble_cs;
3585 *continue_preamble_cs = queue->continue_preamble_cs;
3586 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3587 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3588 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3589 *continue_preamble_cs = NULL;
3590 return VK_SUCCESS;
3591 }
3592
3593 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3594 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3595 if (scratch_size > queue_scratch_size) {
3596 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3597 scratch_size,
3598 4096,
3599 RADEON_DOMAIN_VRAM,
3600 ring_bo_flags,
3601 RADV_BO_PRIORITY_SCRATCH);
3602 if (!scratch_bo)
3603 goto fail;
3604 } else
3605 scratch_bo = queue->scratch_bo;
3606
3607 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3608 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3609 if (compute_scratch_size > compute_queue_scratch_size) {
3610 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3611 compute_scratch_size,
3612 4096,
3613 RADEON_DOMAIN_VRAM,
3614 ring_bo_flags,
3615 RADV_BO_PRIORITY_SCRATCH);
3616 if (!compute_scratch_bo)
3617 goto fail;
3618
3619 } else
3620 compute_scratch_bo = queue->compute_scratch_bo;
3621
3622 if (esgs_ring_size > queue->esgs_ring_size) {
3623 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3624 esgs_ring_size,
3625 4096,
3626 RADEON_DOMAIN_VRAM,
3627 ring_bo_flags,
3628 RADV_BO_PRIORITY_SCRATCH);
3629 if (!esgs_ring_bo)
3630 goto fail;
3631 } else {
3632 esgs_ring_bo = queue->esgs_ring_bo;
3633 esgs_ring_size = queue->esgs_ring_size;
3634 }
3635
3636 if (gsvs_ring_size > queue->gsvs_ring_size) {
3637 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3638 gsvs_ring_size,
3639 4096,
3640 RADEON_DOMAIN_VRAM,
3641 ring_bo_flags,
3642 RADV_BO_PRIORITY_SCRATCH);
3643 if (!gsvs_ring_bo)
3644 goto fail;
3645 } else {
3646 gsvs_ring_bo = queue->gsvs_ring_bo;
3647 gsvs_ring_size = queue->gsvs_ring_size;
3648 }
3649
3650 if (add_tess_rings) {
3651 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3652 tess_offchip_ring_offset + tess_offchip_ring_size,
3653 256,
3654 RADEON_DOMAIN_VRAM,
3655 ring_bo_flags,
3656 RADV_BO_PRIORITY_SCRATCH);
3657 if (!tess_rings_bo)
3658 goto fail;
3659 } else {
3660 tess_rings_bo = queue->tess_rings_bo;
3661 }
3662
3663 if (add_gds) {
3664 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3665
3666 /* 4 streamout GDS counters.
3667 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3668 */
3669 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3670 256, 4,
3671 RADEON_DOMAIN_GDS,
3672 ring_bo_flags,
3673 RADV_BO_PRIORITY_SCRATCH);
3674 if (!gds_bo)
3675 goto fail;
3676 } else {
3677 gds_bo = queue->gds_bo;
3678 }
3679
3680 if (add_gds_oa) {
3681 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3682
3683 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3684 4, 1,
3685 RADEON_DOMAIN_OA,
3686 ring_bo_flags,
3687 RADV_BO_PRIORITY_SCRATCH);
3688 if (!gds_oa_bo)
3689 goto fail;
3690 } else {
3691 gds_oa_bo = queue->gds_oa_bo;
3692 }
3693
3694 if (scratch_bo != queue->scratch_bo ||
3695 esgs_ring_bo != queue->esgs_ring_bo ||
3696 gsvs_ring_bo != queue->gsvs_ring_bo ||
3697 tess_rings_bo != queue->tess_rings_bo ||
3698 add_sample_positions) {
3699 uint32_t size = 0;
3700 if (gsvs_ring_bo || esgs_ring_bo ||
3701 tess_rings_bo || add_sample_positions) {
3702 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3703 if (add_sample_positions)
3704 size += 128; /* 64+32+16+8 = 120 bytes */
3705 }
3706 else if (scratch_bo)
3707 size = 8; /* 2 dword */
3708
3709 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3710 size,
3711 4096,
3712 RADEON_DOMAIN_VRAM,
3713 RADEON_FLAG_CPU_ACCESS |
3714 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3715 RADEON_FLAG_READ_ONLY,
3716 RADV_BO_PRIORITY_DESCRIPTOR);
3717 if (!descriptor_bo)
3718 goto fail;
3719 } else
3720 descriptor_bo = queue->descriptor_bo;
3721
3722 if (descriptor_bo != queue->descriptor_bo) {
3723 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3724 if (!map)
3725 goto fail;
3726
3727 if (scratch_bo) {
3728 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3729 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3730 S_008F04_SWIZZLE_ENABLE(1);
3731 map[0] = scratch_va;
3732 map[1] = rsrc1;
3733 }
3734
3735 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3736 fill_geom_tess_rings(queue, map, add_sample_positions,
3737 esgs_ring_size, esgs_ring_bo,
3738 gsvs_ring_size, gsvs_ring_bo,
3739 tess_factor_ring_size,
3740 tess_offchip_ring_offset,
3741 tess_offchip_ring_size,
3742 tess_rings_bo);
3743
3744 queue->device->ws->buffer_unmap(descriptor_bo);
3745 }
3746
3747 for(int i = 0; i < 3; ++i) {
3748 struct radeon_cmdbuf *cs = NULL;
3749 cs = queue->device->ws->cs_create(queue->device->ws,
3750 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3751 if (!cs)
3752 goto fail;
3753
3754 dest_cs[i] = cs;
3755
3756 if (scratch_bo)
3757 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3758
3759 /* Emit initial configuration. */
3760 switch (queue->queue_family_index) {
3761 case RADV_QUEUE_GENERAL:
3762 radv_init_graphics_state(cs, queue);
3763 break;
3764 case RADV_QUEUE_COMPUTE:
3765 radv_init_compute_state(cs, queue);
3766 break;
3767 case RADV_QUEUE_TRANSFER:
3768 break;
3769 }
3770
3771 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3772 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3773 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3774
3775 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3776 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3777 }
3778
3779 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3780 gsvs_ring_bo, gsvs_ring_size);
3781 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3782 tess_factor_ring_size, tess_rings_bo);
3783 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3784 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3785 compute_scratch_waves, compute_scratch_bo);
3786 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3787 scratch_waves, scratch_bo);
3788 radv_emit_trap_handler(queue, cs, queue->device->tma_bo);
3789
3790 if (gds_bo)
3791 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3792 if (gds_oa_bo)
3793 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3794
3795 if (queue->device->trace_bo)
3796 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3797
3798 if (queue->device->border_color_data.bo)
3799 radv_cs_add_buffer(queue->device->ws, cs,
3800 queue->device->border_color_data.bo);
3801
3802 if (i == 0) {
3803 si_cs_emit_cache_flush(cs,
3804 queue->device->physical_device->rad_info.chip_class,
3805 NULL, 0,
3806 queue->queue_family_index == RING_COMPUTE &&
3807 queue->device->physical_device->rad_info.chip_class >= GFX7,
3808 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3809 RADV_CMD_FLAG_INV_ICACHE |
3810 RADV_CMD_FLAG_INV_SCACHE |
3811 RADV_CMD_FLAG_INV_VCACHE |
3812 RADV_CMD_FLAG_INV_L2 |
3813 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3814 } else if (i == 1) {
3815 si_cs_emit_cache_flush(cs,
3816 queue->device->physical_device->rad_info.chip_class,
3817 NULL, 0,
3818 queue->queue_family_index == RING_COMPUTE &&
3819 queue->device->physical_device->rad_info.chip_class >= GFX7,
3820 RADV_CMD_FLAG_INV_ICACHE |
3821 RADV_CMD_FLAG_INV_SCACHE |
3822 RADV_CMD_FLAG_INV_VCACHE |
3823 RADV_CMD_FLAG_INV_L2 |
3824 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3825 }
3826
3827 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3828 goto fail;
3829 }
3830
3831 if (queue->initial_full_flush_preamble_cs)
3832 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3833
3834 if (queue->initial_preamble_cs)
3835 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3836
3837 if (queue->continue_preamble_cs)
3838 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3839
3840 queue->initial_full_flush_preamble_cs = dest_cs[0];
3841 queue->initial_preamble_cs = dest_cs[1];
3842 queue->continue_preamble_cs = dest_cs[2];
3843
3844 if (scratch_bo != queue->scratch_bo) {
3845 if (queue->scratch_bo)
3846 queue->device->ws->buffer_destroy(queue->scratch_bo);
3847 queue->scratch_bo = scratch_bo;
3848 }
3849 queue->scratch_size_per_wave = scratch_size_per_wave;
3850 queue->scratch_waves = scratch_waves;
3851
3852 if (compute_scratch_bo != queue->compute_scratch_bo) {
3853 if (queue->compute_scratch_bo)
3854 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3855 queue->compute_scratch_bo = compute_scratch_bo;
3856 }
3857 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3858 queue->compute_scratch_waves = compute_scratch_waves;
3859
3860 if (esgs_ring_bo != queue->esgs_ring_bo) {
3861 if (queue->esgs_ring_bo)
3862 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3863 queue->esgs_ring_bo = esgs_ring_bo;
3864 queue->esgs_ring_size = esgs_ring_size;
3865 }
3866
3867 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3868 if (queue->gsvs_ring_bo)
3869 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3870 queue->gsvs_ring_bo = gsvs_ring_bo;
3871 queue->gsvs_ring_size = gsvs_ring_size;
3872 }
3873
3874 if (tess_rings_bo != queue->tess_rings_bo) {
3875 queue->tess_rings_bo = tess_rings_bo;
3876 queue->has_tess_rings = true;
3877 }
3878
3879 if (gds_bo != queue->gds_bo) {
3880 queue->gds_bo = gds_bo;
3881 queue->has_gds = true;
3882 }
3883
3884 if (gds_oa_bo != queue->gds_oa_bo) {
3885 queue->gds_oa_bo = gds_oa_bo;
3886 queue->has_gds_oa = true;
3887 }
3888
3889 if (descriptor_bo != queue->descriptor_bo) {
3890 if (queue->descriptor_bo)
3891 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3892
3893 queue->descriptor_bo = descriptor_bo;
3894 }
3895
3896 if (add_sample_positions)
3897 queue->has_sample_positions = true;
3898
3899 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3900 *initial_preamble_cs = queue->initial_preamble_cs;
3901 *continue_preamble_cs = queue->continue_preamble_cs;
3902 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3903 *continue_preamble_cs = NULL;
3904 return VK_SUCCESS;
3905 fail:
3906 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3907 if (dest_cs[i])
3908 queue->device->ws->cs_destroy(dest_cs[i]);
3909 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3910 queue->device->ws->buffer_destroy(descriptor_bo);
3911 if (scratch_bo && scratch_bo != queue->scratch_bo)
3912 queue->device->ws->buffer_destroy(scratch_bo);
3913 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3914 queue->device->ws->buffer_destroy(compute_scratch_bo);
3915 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3916 queue->device->ws->buffer_destroy(esgs_ring_bo);
3917 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3918 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3919 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3920 queue->device->ws->buffer_destroy(tess_rings_bo);
3921 if (gds_bo && gds_bo != queue->gds_bo)
3922 queue->device->ws->buffer_destroy(gds_bo);
3923 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3924 queue->device->ws->buffer_destroy(gds_oa_bo);
3925
3926 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3927 }
3928
3929 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3930 struct radv_winsys_sem_counts *counts,
3931 int num_sems,
3932 struct radv_semaphore_part **sems,
3933 const uint64_t *timeline_values,
3934 VkFence _fence,
3935 bool is_signal)
3936 {
3937 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0, timeline_idx = 0;
3938
3939 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3940 return VK_SUCCESS;
3941
3942 for (uint32_t i = 0; i < num_sems; i++) {
3943 switch(sems[i]->kind) {
3944 case RADV_SEMAPHORE_SYNCOBJ:
3945 counts->syncobj_count++;
3946 counts->syncobj_reset_count++;
3947 break;
3948 case RADV_SEMAPHORE_WINSYS:
3949 counts->sem_count++;
3950 break;
3951 case RADV_SEMAPHORE_NONE:
3952 break;
3953 case RADV_SEMAPHORE_TIMELINE:
3954 counts->syncobj_count++;
3955 break;
3956 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3957 counts->timeline_syncobj_count++;
3958 break;
3959 }
3960 }
3961
3962 if (_fence != VK_NULL_HANDLE) {
3963 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3964
3965 struct radv_fence_part *part =
3966 fence->temporary.kind != RADV_FENCE_NONE ?
3967 &fence->temporary : &fence->permanent;
3968 if (part->kind == RADV_FENCE_SYNCOBJ)
3969 counts->syncobj_count++;
3970 }
3971
3972 if (counts->syncobj_count || counts->timeline_syncobj_count) {
3973 counts->points = (uint64_t *)malloc(
3974 sizeof(*counts->syncobj) * counts->syncobj_count +
3975 (sizeof(*counts->syncobj) + sizeof(*counts->points)) * counts->timeline_syncobj_count);
3976 if (!counts->points)
3977 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3978 counts->syncobj = (uint32_t*)(counts->points + counts->timeline_syncobj_count);
3979 }
3980
3981 if (counts->sem_count) {
3982 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3983 if (!counts->sem) {
3984 free(counts->syncobj);
3985 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3986 }
3987 }
3988
3989 non_reset_idx = counts->syncobj_reset_count;
3990
3991 for (uint32_t i = 0; i < num_sems; i++) {
3992 switch(sems[i]->kind) {
3993 case RADV_SEMAPHORE_NONE:
3994 unreachable("Empty semaphore");
3995 break;
3996 case RADV_SEMAPHORE_SYNCOBJ:
3997 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3998 break;
3999 case RADV_SEMAPHORE_WINSYS:
4000 counts->sem[sem_idx++] = sems[i]->ws_sem;
4001 break;
4002 case RADV_SEMAPHORE_TIMELINE: {
4003 pthread_mutex_lock(&sems[i]->timeline.mutex);
4004 struct radv_timeline_point *point = NULL;
4005 if (is_signal) {
4006 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4007 } else {
4008 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4009 }
4010
4011 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4012
4013 if (point) {
4014 counts->syncobj[non_reset_idx++] = point->syncobj;
4015 } else {
4016 /* Explicitly remove the semaphore so we might not find
4017 * a point later post-submit. */
4018 sems[i] = NULL;
4019 }
4020 break;
4021 }
4022 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
4023 counts->syncobj[counts->syncobj_count + timeline_idx] = sems[i]->syncobj;
4024 counts->points[timeline_idx] = timeline_values[i];
4025 ++timeline_idx;
4026 break;
4027 }
4028 }
4029
4030 if (_fence != VK_NULL_HANDLE) {
4031 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4032
4033 struct radv_fence_part *part =
4034 fence->temporary.kind != RADV_FENCE_NONE ?
4035 &fence->temporary : &fence->permanent;
4036 if (part->kind == RADV_FENCE_SYNCOBJ)
4037 counts->syncobj[non_reset_idx++] = part->syncobj;
4038 }
4039
4040 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
4041 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
4042
4043 return VK_SUCCESS;
4044 }
4045
4046 static void
4047 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4048 {
4049 free(sem_info->wait.points);
4050 free(sem_info->wait.sem);
4051 free(sem_info->signal.points);
4052 free(sem_info->signal.sem);
4053 }
4054
4055
4056 static void radv_free_temp_syncobjs(struct radv_device *device,
4057 int num_sems,
4058 struct radv_semaphore_part *sems)
4059 {
4060 for (uint32_t i = 0; i < num_sems; i++) {
4061 radv_destroy_semaphore_part(device, sems + i);
4062 }
4063 }
4064
4065 static VkResult
4066 radv_alloc_sem_info(struct radv_device *device,
4067 struct radv_winsys_sem_info *sem_info,
4068 int num_wait_sems,
4069 struct radv_semaphore_part **wait_sems,
4070 const uint64_t *wait_values,
4071 int num_signal_sems,
4072 struct radv_semaphore_part **signal_sems,
4073 const uint64_t *signal_values,
4074 VkFence fence)
4075 {
4076 VkResult ret;
4077 memset(sem_info, 0, sizeof(*sem_info));
4078
4079 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4080 if (ret)
4081 return ret;
4082 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4083 if (ret)
4084 radv_free_sem_info(sem_info);
4085
4086 /* caller can override these */
4087 sem_info->cs_emit_wait = true;
4088 sem_info->cs_emit_signal = true;
4089 return ret;
4090 }
4091
4092 static void
4093 radv_finalize_timelines(struct radv_device *device,
4094 uint32_t num_wait_sems,
4095 struct radv_semaphore_part **wait_sems,
4096 const uint64_t *wait_values,
4097 uint32_t num_signal_sems,
4098 struct radv_semaphore_part **signal_sems,
4099 const uint64_t *signal_values,
4100 struct list_head *processing_list)
4101 {
4102 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4103 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4104 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4105 struct radv_timeline_point *point =
4106 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4107 point->wait_count -= 2;
4108 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4109 }
4110 }
4111 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4112 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4113 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4114 struct radv_timeline_point *point =
4115 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4116 signal_sems[i]->timeline.highest_submitted =
4117 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4118 point->wait_count -= 2;
4119 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4120 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4121 } else if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) {
4122 signal_sems[i]->timeline_syncobj.max_point =
4123 MAX2(signal_sems[i]->timeline_syncobj.max_point, signal_values[i]);
4124 }
4125 }
4126 }
4127
4128 static VkResult
4129 radv_sparse_buffer_bind_memory(struct radv_device *device,
4130 const VkSparseBufferMemoryBindInfo *bind)
4131 {
4132 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4133 VkResult result;
4134
4135 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4136 struct radv_device_memory *mem = NULL;
4137
4138 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4139 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4140
4141 result = device->ws->buffer_virtual_bind(buffer->bo,
4142 bind->pBinds[i].resourceOffset,
4143 bind->pBinds[i].size,
4144 mem ? mem->bo : NULL,
4145 bind->pBinds[i].memoryOffset);
4146 if (result != VK_SUCCESS)
4147 return result;
4148 }
4149
4150 return VK_SUCCESS;
4151 }
4152
4153 static VkResult
4154 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4155 const VkSparseImageOpaqueMemoryBindInfo *bind)
4156 {
4157 RADV_FROM_HANDLE(radv_image, image, bind->image);
4158 VkResult result;
4159
4160 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4161 struct radv_device_memory *mem = NULL;
4162
4163 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4164 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4165
4166 result = device->ws->buffer_virtual_bind(image->bo,
4167 bind->pBinds[i].resourceOffset,
4168 bind->pBinds[i].size,
4169 mem ? mem->bo : NULL,
4170 bind->pBinds[i].memoryOffset);
4171 if (result != VK_SUCCESS)
4172 return result;
4173 }
4174
4175 return VK_SUCCESS;
4176 }
4177
4178 static VkResult
4179 radv_get_preambles(struct radv_queue *queue,
4180 const VkCommandBuffer *cmd_buffers,
4181 uint32_t cmd_buffer_count,
4182 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4183 struct radeon_cmdbuf **initial_preamble_cs,
4184 struct radeon_cmdbuf **continue_preamble_cs)
4185 {
4186 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4187 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4188 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4189 bool tess_rings_needed = false;
4190 bool gds_needed = false;
4191 bool gds_oa_needed = false;
4192 bool sample_positions_needed = false;
4193
4194 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4196 cmd_buffers[j]);
4197
4198 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4199 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4200 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4201 cmd_buffer->compute_scratch_size_per_wave_needed);
4202 compute_waves_wanted = MAX2(compute_waves_wanted,
4203 cmd_buffer->compute_scratch_waves_wanted);
4204 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4205 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4206 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4207 gds_needed |= cmd_buffer->gds_needed;
4208 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4209 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4210 }
4211
4212 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4213 compute_scratch_size_per_wave, compute_waves_wanted,
4214 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4215 gds_needed, gds_oa_needed, sample_positions_needed,
4216 initial_full_flush_preamble_cs,
4217 initial_preamble_cs, continue_preamble_cs);
4218 }
4219
4220 struct radv_deferred_queue_submission {
4221 struct radv_queue *queue;
4222 VkCommandBuffer *cmd_buffers;
4223 uint32_t cmd_buffer_count;
4224
4225 /* Sparse bindings that happen on a queue. */
4226 VkSparseBufferMemoryBindInfo *buffer_binds;
4227 uint32_t buffer_bind_count;
4228 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4229 uint32_t image_opaque_bind_count;
4230
4231 bool flush_caches;
4232 VkShaderStageFlags wait_dst_stage_mask;
4233 struct radv_semaphore_part **wait_semaphores;
4234 uint32_t wait_semaphore_count;
4235 struct radv_semaphore_part **signal_semaphores;
4236 uint32_t signal_semaphore_count;
4237 VkFence fence;
4238
4239 uint64_t *wait_values;
4240 uint64_t *signal_values;
4241
4242 struct radv_semaphore_part *temporary_semaphore_parts;
4243 uint32_t temporary_semaphore_part_count;
4244
4245 struct list_head queue_pending_list;
4246 uint32_t submission_wait_count;
4247 struct radv_timeline_waiter *wait_nodes;
4248
4249 struct list_head processing_list;
4250 };
4251
4252 struct radv_queue_submission {
4253 const VkCommandBuffer *cmd_buffers;
4254 uint32_t cmd_buffer_count;
4255
4256 /* Sparse bindings that happen on a queue. */
4257 const VkSparseBufferMemoryBindInfo *buffer_binds;
4258 uint32_t buffer_bind_count;
4259 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4260 uint32_t image_opaque_bind_count;
4261
4262 bool flush_caches;
4263 VkPipelineStageFlags wait_dst_stage_mask;
4264 const VkSemaphore *wait_semaphores;
4265 uint32_t wait_semaphore_count;
4266 const VkSemaphore *signal_semaphores;
4267 uint32_t signal_semaphore_count;
4268 VkFence fence;
4269
4270 const uint64_t *wait_values;
4271 uint32_t wait_value_count;
4272 const uint64_t *signal_values;
4273 uint32_t signal_value_count;
4274 };
4275
4276 static VkResult
4277 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4278 uint32_t decrement,
4279 struct list_head *processing_list);
4280
4281 static VkResult
4282 radv_create_deferred_submission(struct radv_queue *queue,
4283 const struct radv_queue_submission *submission,
4284 struct radv_deferred_queue_submission **out)
4285 {
4286 struct radv_deferred_queue_submission *deferred = NULL;
4287 size_t size = sizeof(struct radv_deferred_queue_submission);
4288
4289 uint32_t temporary_count = 0;
4290 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4291 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4292 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4293 ++temporary_count;
4294 }
4295
4296 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4297 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4298 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4299 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4300 size += temporary_count * sizeof(struct radv_semaphore_part);
4301 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4302 size += submission->wait_value_count * sizeof(uint64_t);
4303 size += submission->signal_value_count * sizeof(uint64_t);
4304 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4305
4306 deferred = calloc(1, size);
4307 if (!deferred)
4308 return VK_ERROR_OUT_OF_HOST_MEMORY;
4309
4310 deferred->queue = queue;
4311
4312 deferred->cmd_buffers = (void*)(deferred + 1);
4313 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4314 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4315 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4316
4317 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4318 deferred->buffer_bind_count = submission->buffer_bind_count;
4319 memcpy(deferred->buffer_binds, submission->buffer_binds,
4320 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4321
4322 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4323 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4324 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4325 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4326
4327 deferred->flush_caches = submission->flush_caches;
4328 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4329
4330 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4331 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4332
4333 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4334 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4335
4336 deferred->fence = submission->fence;
4337
4338 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4339 deferred->temporary_semaphore_part_count = temporary_count;
4340
4341 uint32_t temporary_idx = 0;
4342 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4343 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4344 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4345 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4346 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4347 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4348 ++temporary_idx;
4349 } else
4350 deferred->wait_semaphores[i] = &semaphore->permanent;
4351 }
4352
4353 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4354 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4355 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4356 deferred->signal_semaphores[i] = &semaphore->temporary;
4357 } else {
4358 deferred->signal_semaphores[i] = &semaphore->permanent;
4359 }
4360 }
4361
4362 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4363 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4364 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4365 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4366
4367 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4368 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4369 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4370 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4371
4372 *out = deferred;
4373 return VK_SUCCESS;
4374 }
4375
4376 static VkResult
4377 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4378 struct list_head *processing_list)
4379 {
4380 uint32_t wait_cnt = 0;
4381 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4382 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4383 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4384 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4385 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4386 ++wait_cnt;
4387 waiter->value = submission->wait_values[i];
4388 waiter->submission = submission;
4389 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4390 ++waiter;
4391 }
4392 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4393 }
4394 }
4395
4396 pthread_mutex_lock(&submission->queue->pending_mutex);
4397
4398 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4399 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4400
4401 pthread_mutex_unlock(&submission->queue->pending_mutex);
4402
4403 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4404 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4405 * submission. */
4406 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4407 return radv_queue_trigger_submission(submission, decrement, processing_list);
4408 }
4409
4410 static void
4411 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4412 struct list_head *processing_list)
4413 {
4414 pthread_mutex_lock(&submission->queue->pending_mutex);
4415 list_del(&submission->queue_pending_list);
4416
4417 /* trigger the next submission in the queue. */
4418 if (!list_is_empty(&submission->queue->pending_submissions)) {
4419 struct radv_deferred_queue_submission *next_submission =
4420 list_first_entry(&submission->queue->pending_submissions,
4421 struct radv_deferred_queue_submission,
4422 queue_pending_list);
4423 radv_queue_trigger_submission(next_submission, 1, processing_list);
4424 }
4425 pthread_mutex_unlock(&submission->queue->pending_mutex);
4426
4427 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4428 }
4429
4430 static VkResult
4431 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4432 struct list_head *processing_list)
4433 {
4434 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4435 struct radv_queue *queue = submission->queue;
4436 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4437 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4438 struct radeon_winsys_fence *base_fence = NULL;
4439 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4440 bool can_patch = true;
4441 uint32_t advance;
4442 struct radv_winsys_sem_info sem_info;
4443 VkResult result;
4444 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4445 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4446 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4447
4448 if (fence) {
4449 /* Under most circumstances, out fences won't be temporary.
4450 * However, the spec does allow it for opaque_fd.
4451 *
4452 * From the Vulkan 1.0.53 spec:
4453 *
4454 * "If the import is temporary, the implementation must
4455 * restore the semaphore to its prior permanent state after
4456 * submitting the next semaphore wait operation."
4457 */
4458 struct radv_fence_part *part =
4459 fence->temporary.kind != RADV_FENCE_NONE ?
4460 &fence->temporary : &fence->permanent;
4461 if (part->kind == RADV_FENCE_WINSYS)
4462 base_fence = part->fence;
4463 }
4464
4465 result = radv_get_preambles(queue, submission->cmd_buffers,
4466 submission->cmd_buffer_count,
4467 &initial_preamble_cs,
4468 &initial_flush_preamble_cs,
4469 &continue_preamble_cs);
4470 if (result != VK_SUCCESS)
4471 goto fail;
4472
4473 result = radv_alloc_sem_info(queue->device,
4474 &sem_info,
4475 submission->wait_semaphore_count,
4476 submission->wait_semaphores,
4477 submission->wait_values,
4478 submission->signal_semaphore_count,
4479 submission->signal_semaphores,
4480 submission->signal_values,
4481 submission->fence);
4482 if (result != VK_SUCCESS)
4483 goto fail;
4484
4485 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4486 result = radv_sparse_buffer_bind_memory(queue->device,
4487 submission->buffer_binds + i);
4488 if (result != VK_SUCCESS)
4489 goto fail;
4490 }
4491
4492 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4493 result = radv_sparse_image_opaque_bind_memory(queue->device,
4494 submission->image_opaque_binds + i);
4495 if (result != VK_SUCCESS)
4496 goto fail;
4497 }
4498
4499 if (!submission->cmd_buffer_count) {
4500 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4501 &queue->device->empty_cs[queue->queue_family_index],
4502 1, NULL, NULL,
4503 &sem_info, NULL,
4504 false, base_fence);
4505 if (result != VK_SUCCESS)
4506 goto fail;
4507 } else {
4508 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4509 (submission->cmd_buffer_count));
4510
4511 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4513 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4514
4515 cs_array[j] = cmd_buffer->cs;
4516 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4517 can_patch = false;
4518
4519 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4520 }
4521
4522 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4523 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4524 const struct radv_winsys_bo_list *bo_list = NULL;
4525
4526 advance = MIN2(max_cs_submission,
4527 submission->cmd_buffer_count - j);
4528
4529 if (queue->device->trace_bo)
4530 *queue->device->trace_id_ptr = 0;
4531
4532 sem_info.cs_emit_wait = j == 0;
4533 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4534
4535 if (unlikely(queue->device->use_global_bo_list)) {
4536 pthread_mutex_lock(&queue->device->bo_list.mutex);
4537 bo_list = &queue->device->bo_list.list;
4538 }
4539
4540 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4541 advance, initial_preamble, continue_preamble_cs,
4542 &sem_info, bo_list,
4543 can_patch, base_fence);
4544
4545 if (unlikely(queue->device->use_global_bo_list))
4546 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4547
4548 if (result != VK_SUCCESS)
4549 goto fail;
4550
4551 if (queue->device->trace_bo) {
4552 radv_check_gpu_hangs(queue, cs_array[j]);
4553 }
4554
4555 if (queue->device->tma_bo) {
4556 radv_check_trap_handler(queue);
4557 }
4558 }
4559
4560 free(cs_array);
4561 }
4562
4563 radv_free_temp_syncobjs(queue->device,
4564 submission->temporary_semaphore_part_count,
4565 submission->temporary_semaphore_parts);
4566 radv_finalize_timelines(queue->device,
4567 submission->wait_semaphore_count,
4568 submission->wait_semaphores,
4569 submission->wait_values,
4570 submission->signal_semaphore_count,
4571 submission->signal_semaphores,
4572 submission->signal_values,
4573 processing_list);
4574 /* Has to happen after timeline finalization to make sure the
4575 * condition variable is only triggered when timelines and queue have
4576 * been updated. */
4577 radv_queue_submission_update_queue(submission, processing_list);
4578 radv_free_sem_info(&sem_info);
4579 free(submission);
4580 return VK_SUCCESS;
4581
4582 fail:
4583 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4584 /* When something bad happened during the submission, such as
4585 * an out of memory issue, it might be hard to recover from
4586 * this inconsistent state. To avoid this sort of problem, we
4587 * assume that we are in a really bad situation and return
4588 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4589 * to submit the same job again to this device.
4590 */
4591 result = radv_device_set_lost(queue->device, "vkQueueSubmit() failed");
4592 }
4593
4594 radv_free_temp_syncobjs(queue->device,
4595 submission->temporary_semaphore_part_count,
4596 submission->temporary_semaphore_parts);
4597 free(submission);
4598 return result;
4599 }
4600
4601 static VkResult
4602 radv_process_submissions(struct list_head *processing_list)
4603 {
4604 while(!list_is_empty(processing_list)) {
4605 struct radv_deferred_queue_submission *submission =
4606 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4607 list_del(&submission->processing_list);
4608
4609 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4610 if (result != VK_SUCCESS)
4611 return result;
4612 }
4613 return VK_SUCCESS;
4614 }
4615
4616 static VkResult
4617 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4618 uint64_t timeout)
4619 {
4620 struct radv_device *device = submission->queue->device;
4621 uint32_t syncobj_count = 0;
4622 uint32_t syncobj_idx = 0;
4623
4624 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4625 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4626 continue;
4627
4628 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4629 continue;
4630 ++syncobj_count;
4631 }
4632
4633 if (!syncobj_count)
4634 return VK_SUCCESS;
4635
4636 uint64_t *points = malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count);
4637 if (!points)
4638 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4639
4640 uint32_t *syncobj = (uint32_t*)(points + syncobj_count);
4641
4642 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4643 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4644 continue;
4645
4646 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4647 continue;
4648
4649 syncobj[syncobj_idx] = submission->wait_semaphores[i]->syncobj;
4650 points[syncobj_idx] = submission->wait_values[i];
4651 ++syncobj_idx;
4652 }
4653 bool success = device->ws->wait_timeline_syncobj(device->ws, syncobj, points, syncobj_idx, true, true, timeout);
4654
4655 free(points);
4656 return success ? VK_SUCCESS : VK_TIMEOUT;
4657 }
4658
4659 static void* radv_queue_submission_thread_run(void *q)
4660 {
4661 struct radv_queue *queue = q;
4662
4663 pthread_mutex_lock(&queue->thread_mutex);
4664 while (!p_atomic_read(&queue->thread_exit)) {
4665 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4666 struct list_head processing_list;
4667 VkResult result = VK_SUCCESS;
4668 if (!submission) {
4669 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4670 continue;
4671 }
4672 pthread_mutex_unlock(&queue->thread_mutex);
4673
4674 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4675 * a semaphore never gets signaled. If it takes longer we just retry
4676 * the wait next iteration. */
4677 result = wait_for_submission_timelines_available(submission,
4678 radv_get_absolute_timeout(5000000000));
4679 if (result != VK_SUCCESS) {
4680 pthread_mutex_lock(&queue->thread_mutex);
4681 continue;
4682 }
4683
4684 /* The lock isn't held but nobody will add one until we finish
4685 * the current submission. */
4686 p_atomic_set(&queue->thread_submission, NULL);
4687
4688 list_inithead(&processing_list);
4689 list_addtail(&submission->processing_list, &processing_list);
4690 result = radv_process_submissions(&processing_list);
4691
4692 pthread_mutex_lock(&queue->thread_mutex);
4693 }
4694 pthread_mutex_unlock(&queue->thread_mutex);
4695 return NULL;
4696 }
4697
4698 static VkResult
4699 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4700 uint32_t decrement,
4701 struct list_head *processing_list)
4702 {
4703 struct radv_queue *queue = submission->queue;
4704 int ret;
4705 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4706 return VK_SUCCESS;
4707
4708 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4709 list_addtail(&submission->processing_list, processing_list);
4710 return VK_SUCCESS;
4711 }
4712
4713 pthread_mutex_lock(&queue->thread_mutex);
4714
4715 /* A submission can only be ready for the thread if it doesn't have
4716 * any predecessors in the same queue, so there can only be one such
4717 * submission at a time. */
4718 assert(queue->thread_submission == NULL);
4719
4720 /* Only start the thread on demand to save resources for the many games
4721 * which only use binary semaphores. */
4722 if (!queue->thread_running) {
4723 ret = pthread_create(&queue->submission_thread, NULL,
4724 radv_queue_submission_thread_run, queue);
4725 if (ret) {
4726 pthread_mutex_unlock(&queue->thread_mutex);
4727 return vk_errorf(queue->device->instance,
4728 VK_ERROR_DEVICE_LOST,
4729 "Failed to start submission thread");
4730 }
4731 queue->thread_running = true;
4732 }
4733
4734 queue->thread_submission = submission;
4735 pthread_mutex_unlock(&queue->thread_mutex);
4736
4737 pthread_cond_signal(&queue->thread_cond);
4738 return VK_SUCCESS;
4739 }
4740
4741 static VkResult radv_queue_submit(struct radv_queue *queue,
4742 const struct radv_queue_submission *submission)
4743 {
4744 struct radv_deferred_queue_submission *deferred = NULL;
4745
4746 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4747 if (result != VK_SUCCESS)
4748 return result;
4749
4750 struct list_head processing_list;
4751 list_inithead(&processing_list);
4752
4753 result = radv_queue_enqueue_submission(deferred, &processing_list);
4754 if (result != VK_SUCCESS) {
4755 /* If anything is in the list we leak. */
4756 assert(list_is_empty(&processing_list));
4757 return result;
4758 }
4759 return radv_process_submissions(&processing_list);
4760 }
4761
4762 bool
4763 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4764 {
4765 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4766 struct radv_winsys_sem_info sem_info;
4767 VkResult result;
4768
4769 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4770 0, NULL, VK_NULL_HANDLE);
4771 if (result != VK_SUCCESS)
4772 return false;
4773
4774 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4775 NULL, NULL, &sem_info, NULL,
4776 false, NULL);
4777 radv_free_sem_info(&sem_info);
4778 if (result != VK_SUCCESS)
4779 return false;
4780
4781 return true;
4782
4783 }
4784
4785 /* Signals fence as soon as all the work currently put on queue is done. */
4786 static VkResult radv_signal_fence(struct radv_queue *queue,
4787 VkFence fence)
4788 {
4789 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4790 .fence = fence
4791 });
4792 }
4793
4794 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4795 {
4796 return info->commandBufferCount ||
4797 info->waitSemaphoreCount ||
4798 info->signalSemaphoreCount;
4799 }
4800
4801 VkResult radv_QueueSubmit(
4802 VkQueue _queue,
4803 uint32_t submitCount,
4804 const VkSubmitInfo* pSubmits,
4805 VkFence fence)
4806 {
4807 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4808 VkResult result;
4809 uint32_t fence_idx = 0;
4810 bool flushed_caches = false;
4811
4812 if (radv_device_is_lost(queue->device))
4813 return VK_ERROR_DEVICE_LOST;
4814
4815 if (fence != VK_NULL_HANDLE) {
4816 for (uint32_t i = 0; i < submitCount; ++i)
4817 if (radv_submit_has_effects(pSubmits + i))
4818 fence_idx = i;
4819 } else
4820 fence_idx = UINT32_MAX;
4821
4822 for (uint32_t i = 0; i < submitCount; i++) {
4823 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4824 continue;
4825
4826 VkPipelineStageFlags wait_dst_stage_mask = 0;
4827 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4828 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4829 }
4830
4831 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4832 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4833
4834 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4835 .cmd_buffers = pSubmits[i].pCommandBuffers,
4836 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4837 .wait_dst_stage_mask = wait_dst_stage_mask,
4838 .flush_caches = !flushed_caches,
4839 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4840 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4841 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4842 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4843 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4844 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4845 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4846 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4847 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4848 });
4849 if (result != VK_SUCCESS)
4850 return result;
4851
4852 flushed_caches = true;
4853 }
4854
4855 if (fence != VK_NULL_HANDLE && !submitCount) {
4856 result = radv_signal_fence(queue, fence);
4857 if (result != VK_SUCCESS)
4858 return result;
4859 }
4860
4861 return VK_SUCCESS;
4862 }
4863
4864 static const char *
4865 radv_get_queue_family_name(struct radv_queue *queue)
4866 {
4867 switch (queue->queue_family_index) {
4868 case RADV_QUEUE_GENERAL:
4869 return "graphics";
4870 case RADV_QUEUE_COMPUTE:
4871 return "compute";
4872 case RADV_QUEUE_TRANSFER:
4873 return "transfer";
4874 default:
4875 unreachable("Unknown queue family");
4876 }
4877 }
4878
4879 VkResult radv_QueueWaitIdle(
4880 VkQueue _queue)
4881 {
4882 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4883
4884 if (radv_device_is_lost(queue->device))
4885 return VK_ERROR_DEVICE_LOST;
4886
4887 pthread_mutex_lock(&queue->pending_mutex);
4888 while (!list_is_empty(&queue->pending_submissions)) {
4889 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4890 }
4891 pthread_mutex_unlock(&queue->pending_mutex);
4892
4893 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4894 radv_queue_family_to_ring(queue->queue_family_index),
4895 queue->queue_idx)) {
4896 return radv_device_set_lost(queue->device,
4897 "Failed to wait for a '%s' queue "
4898 "to be idle. GPU hang ?",
4899 radv_get_queue_family_name(queue));
4900 }
4901
4902 return VK_SUCCESS;
4903 }
4904
4905 VkResult radv_DeviceWaitIdle(
4906 VkDevice _device)
4907 {
4908 RADV_FROM_HANDLE(radv_device, device, _device);
4909
4910 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4911 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4912 VkResult result =
4913 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4914
4915 if (result != VK_SUCCESS)
4916 return result;
4917 }
4918 }
4919 return VK_SUCCESS;
4920 }
4921
4922 VkResult radv_EnumerateInstanceExtensionProperties(
4923 const char* pLayerName,
4924 uint32_t* pPropertyCount,
4925 VkExtensionProperties* pProperties)
4926 {
4927 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4928
4929 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4930 if (radv_instance_extensions_supported.extensions[i]) {
4931 vk_outarray_append(&out, prop) {
4932 *prop = radv_instance_extensions[i];
4933 }
4934 }
4935 }
4936
4937 return vk_outarray_status(&out);
4938 }
4939
4940 VkResult radv_EnumerateDeviceExtensionProperties(
4941 VkPhysicalDevice physicalDevice,
4942 const char* pLayerName,
4943 uint32_t* pPropertyCount,
4944 VkExtensionProperties* pProperties)
4945 {
4946 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4947 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4948
4949 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4950 if (device->supported_extensions.extensions[i]) {
4951 vk_outarray_append(&out, prop) {
4952 *prop = radv_device_extensions[i];
4953 }
4954 }
4955 }
4956
4957 return vk_outarray_status(&out);
4958 }
4959
4960 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4961 VkInstance _instance,
4962 const char* pName)
4963 {
4964 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4965
4966 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4967 * when we have to return valid function pointers, NULL, or it's left
4968 * undefined. See the table for exact details.
4969 */
4970 if (pName == NULL)
4971 return NULL;
4972
4973 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4974 if (strcmp(pName, "vk" #entrypoint) == 0) \
4975 return (PFN_vkVoidFunction)radv_##entrypoint
4976
4977 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4978 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4979 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4980 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4981
4982 /* GetInstanceProcAddr() can also be called with a NULL instance.
4983 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4984 */
4985 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4986
4987 #undef LOOKUP_RADV_ENTRYPOINT
4988
4989 if (instance == NULL)
4990 return NULL;
4991
4992 int idx = radv_get_instance_entrypoint_index(pName);
4993 if (idx >= 0)
4994 return instance->dispatch.entrypoints[idx];
4995
4996 idx = radv_get_physical_device_entrypoint_index(pName);
4997 if (idx >= 0)
4998 return instance->physical_device_dispatch.entrypoints[idx];
4999
5000 idx = radv_get_device_entrypoint_index(pName);
5001 if (idx >= 0)
5002 return instance->device_dispatch.entrypoints[idx];
5003
5004 return NULL;
5005 }
5006
5007 /* The loader wants us to expose a second GetInstanceProcAddr function
5008 * to work around certain LD_PRELOAD issues seen in apps.
5009 */
5010 PUBLIC
5011 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5012 VkInstance instance,
5013 const char* pName);
5014
5015 PUBLIC
5016 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
5017 VkInstance instance,
5018 const char* pName)
5019 {
5020 return radv_GetInstanceProcAddr(instance, pName);
5021 }
5022
5023 PUBLIC
5024 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5025 VkInstance _instance,
5026 const char* pName);
5027
5028 PUBLIC
5029 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5030 VkInstance _instance,
5031 const char* pName)
5032 {
5033 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5034
5035 if (!pName || !instance)
5036 return NULL;
5037
5038 int idx = radv_get_physical_device_entrypoint_index(pName);
5039 if (idx < 0)
5040 return NULL;
5041
5042 return instance->physical_device_dispatch.entrypoints[idx];
5043 }
5044
5045 PFN_vkVoidFunction radv_GetDeviceProcAddr(
5046 VkDevice _device,
5047 const char* pName)
5048 {
5049 RADV_FROM_HANDLE(radv_device, device, _device);
5050
5051 if (!device || !pName)
5052 return NULL;
5053
5054 int idx = radv_get_device_entrypoint_index(pName);
5055 if (idx < 0)
5056 return NULL;
5057
5058 return device->dispatch.entrypoints[idx];
5059 }
5060
5061 bool radv_get_memory_fd(struct radv_device *device,
5062 struct radv_device_memory *memory,
5063 int *pFD)
5064 {
5065 struct radeon_bo_metadata metadata;
5066
5067 if (memory->image) {
5068 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5069 radv_init_metadata(device, memory->image, &metadata);
5070 device->ws->buffer_set_metadata(memory->bo, &metadata);
5071 }
5072
5073 return device->ws->buffer_get_fd(device->ws, memory->bo,
5074 pFD);
5075 }
5076
5077
5078 void
5079 radv_free_memory(struct radv_device *device,
5080 const VkAllocationCallbacks* pAllocator,
5081 struct radv_device_memory *mem)
5082 {
5083 if (mem == NULL)
5084 return;
5085
5086 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5087 if (mem->android_hardware_buffer)
5088 AHardwareBuffer_release(mem->android_hardware_buffer);
5089 #endif
5090
5091 if (mem->bo) {
5092 if (device->overallocation_disallowed) {
5093 mtx_lock(&device->overallocation_mutex);
5094 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5095 mtx_unlock(&device->overallocation_mutex);
5096 }
5097
5098 radv_bo_list_remove(device, mem->bo);
5099 device->ws->buffer_destroy(mem->bo);
5100 mem->bo = NULL;
5101 }
5102
5103 vk_object_base_finish(&mem->base);
5104 vk_free2(&device->vk.alloc, pAllocator, mem);
5105 }
5106
5107 static VkResult radv_alloc_memory(struct radv_device *device,
5108 const VkMemoryAllocateInfo* pAllocateInfo,
5109 const VkAllocationCallbacks* pAllocator,
5110 VkDeviceMemory* pMem)
5111 {
5112 struct radv_device_memory *mem;
5113 VkResult result;
5114 enum radeon_bo_domain domain;
5115 uint32_t flags = 0;
5116
5117 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5118
5119 const VkImportMemoryFdInfoKHR *import_info =
5120 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5121 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5122 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5123 const VkExportMemoryAllocateInfo *export_info =
5124 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5125 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5126 vk_find_struct_const(pAllocateInfo->pNext,
5127 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5128 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5129 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5130
5131 const struct wsi_memory_allocate_info *wsi_info =
5132 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5133
5134 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5135 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5136 /* Apparently, this is allowed */
5137 *pMem = VK_NULL_HANDLE;
5138 return VK_SUCCESS;
5139 }
5140
5141 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
5142 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5143 if (mem == NULL)
5144 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5145
5146 vk_object_base_init(&device->vk, &mem->base,
5147 VK_OBJECT_TYPE_DEVICE_MEMORY);
5148
5149 if (wsi_info && wsi_info->implicit_sync)
5150 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5151
5152 if (dedicate_info) {
5153 mem->image = radv_image_from_handle(dedicate_info->image);
5154 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5155 } else {
5156 mem->image = NULL;
5157 mem->buffer = NULL;
5158 }
5159
5160 float priority_float = 0.5;
5161 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5162 vk_find_struct_const(pAllocateInfo->pNext,
5163 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5164 if (priority_ext)
5165 priority_float = priority_ext->priority;
5166
5167 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5168 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5169
5170 mem->user_ptr = NULL;
5171 mem->bo = NULL;
5172
5173 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5174 mem->android_hardware_buffer = NULL;
5175 #endif
5176
5177 if (ahb_import_info) {
5178 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5179 if (result != VK_SUCCESS)
5180 goto fail;
5181 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5182 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5183 if (result != VK_SUCCESS)
5184 goto fail;
5185 } else if (import_info) {
5186 assert(import_info->handleType ==
5187 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5188 import_info->handleType ==
5189 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5190 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5191 priority, NULL);
5192 if (!mem->bo) {
5193 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5194 goto fail;
5195 } else {
5196 close(import_info->fd);
5197 }
5198
5199 if (mem->image && mem->image->plane_count == 1 &&
5200 !vk_format_is_depth_or_stencil(mem->image->vk_format)) {
5201 struct radeon_bo_metadata metadata;
5202 device->ws->buffer_get_metadata(mem->bo, &metadata);
5203
5204 struct radv_image_create_info create_info = {
5205 .no_metadata_planes = true,
5206 .bo_metadata = &metadata
5207 };
5208
5209 /* This gives a basic ability to import radeonsi images
5210 * that don't have DCC. This is not guaranteed by any
5211 * spec and can be removed after we support modifiers. */
5212 result = radv_image_create_layout(device, create_info, mem->image);
5213 if (result != VK_SUCCESS) {
5214 device->ws->buffer_destroy(mem->bo);
5215 goto fail;
5216 }
5217 }
5218 } else if (host_ptr_info) {
5219 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5220 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5221 pAllocateInfo->allocationSize,
5222 priority);
5223 if (!mem->bo) {
5224 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5225 goto fail;
5226 } else {
5227 mem->user_ptr = host_ptr_info->pHostPointer;
5228 }
5229 } else {
5230 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5231 uint32_t heap_index;
5232
5233 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5234 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5235 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5236
5237 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5238 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5239 if (device->use_global_bo_list) {
5240 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5241 }
5242 }
5243
5244 if (device->overallocation_disallowed) {
5245 uint64_t total_size =
5246 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5247
5248 mtx_lock(&device->overallocation_mutex);
5249 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5250 mtx_unlock(&device->overallocation_mutex);
5251 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5252 goto fail;
5253 }
5254 device->allocated_memory_size[heap_index] += alloc_size;
5255 mtx_unlock(&device->overallocation_mutex);
5256 }
5257
5258 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5259 domain, flags, priority);
5260
5261 if (!mem->bo) {
5262 if (device->overallocation_disallowed) {
5263 mtx_lock(&device->overallocation_mutex);
5264 device->allocated_memory_size[heap_index] -= alloc_size;
5265 mtx_unlock(&device->overallocation_mutex);
5266 }
5267 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5268 goto fail;
5269 }
5270
5271 mem->heap_index = heap_index;
5272 mem->alloc_size = alloc_size;
5273 }
5274
5275 if (!wsi_info) {
5276 result = radv_bo_list_add(device, mem->bo);
5277 if (result != VK_SUCCESS)
5278 goto fail;
5279 }
5280
5281 *pMem = radv_device_memory_to_handle(mem);
5282
5283 return VK_SUCCESS;
5284
5285 fail:
5286 radv_free_memory(device, pAllocator,mem);
5287
5288 return result;
5289 }
5290
5291 VkResult radv_AllocateMemory(
5292 VkDevice _device,
5293 const VkMemoryAllocateInfo* pAllocateInfo,
5294 const VkAllocationCallbacks* pAllocator,
5295 VkDeviceMemory* pMem)
5296 {
5297 RADV_FROM_HANDLE(radv_device, device, _device);
5298 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5299 }
5300
5301 void radv_FreeMemory(
5302 VkDevice _device,
5303 VkDeviceMemory _mem,
5304 const VkAllocationCallbacks* pAllocator)
5305 {
5306 RADV_FROM_HANDLE(radv_device, device, _device);
5307 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5308
5309 radv_free_memory(device, pAllocator, mem);
5310 }
5311
5312 VkResult radv_MapMemory(
5313 VkDevice _device,
5314 VkDeviceMemory _memory,
5315 VkDeviceSize offset,
5316 VkDeviceSize size,
5317 VkMemoryMapFlags flags,
5318 void** ppData)
5319 {
5320 RADV_FROM_HANDLE(radv_device, device, _device);
5321 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5322
5323 if (mem == NULL) {
5324 *ppData = NULL;
5325 return VK_SUCCESS;
5326 }
5327
5328 if (mem->user_ptr)
5329 *ppData = mem->user_ptr;
5330 else
5331 *ppData = device->ws->buffer_map(mem->bo);
5332
5333 if (*ppData) {
5334 *ppData += offset;
5335 return VK_SUCCESS;
5336 }
5337
5338 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5339 }
5340
5341 void radv_UnmapMemory(
5342 VkDevice _device,
5343 VkDeviceMemory _memory)
5344 {
5345 RADV_FROM_HANDLE(radv_device, device, _device);
5346 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5347
5348 if (mem == NULL)
5349 return;
5350
5351 if (mem->user_ptr == NULL)
5352 device->ws->buffer_unmap(mem->bo);
5353 }
5354
5355 VkResult radv_FlushMappedMemoryRanges(
5356 VkDevice _device,
5357 uint32_t memoryRangeCount,
5358 const VkMappedMemoryRange* pMemoryRanges)
5359 {
5360 return VK_SUCCESS;
5361 }
5362
5363 VkResult radv_InvalidateMappedMemoryRanges(
5364 VkDevice _device,
5365 uint32_t memoryRangeCount,
5366 const VkMappedMemoryRange* pMemoryRanges)
5367 {
5368 return VK_SUCCESS;
5369 }
5370
5371 void radv_GetBufferMemoryRequirements(
5372 VkDevice _device,
5373 VkBuffer _buffer,
5374 VkMemoryRequirements* pMemoryRequirements)
5375 {
5376 RADV_FROM_HANDLE(radv_device, device, _device);
5377 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5378
5379 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5380
5381 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5382 pMemoryRequirements->alignment = 4096;
5383 else
5384 pMemoryRequirements->alignment = 16;
5385
5386 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5387 }
5388
5389 void radv_GetBufferMemoryRequirements2(
5390 VkDevice device,
5391 const VkBufferMemoryRequirementsInfo2 *pInfo,
5392 VkMemoryRequirements2 *pMemoryRequirements)
5393 {
5394 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5395 &pMemoryRequirements->memoryRequirements);
5396 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5397 switch (ext->sType) {
5398 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5399 VkMemoryDedicatedRequirements *req =
5400 (VkMemoryDedicatedRequirements *) ext;
5401 req->requiresDedicatedAllocation = false;
5402 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5403 break;
5404 }
5405 default:
5406 break;
5407 }
5408 }
5409 }
5410
5411 void radv_GetImageMemoryRequirements(
5412 VkDevice _device,
5413 VkImage _image,
5414 VkMemoryRequirements* pMemoryRequirements)
5415 {
5416 RADV_FROM_HANDLE(radv_device, device, _device);
5417 RADV_FROM_HANDLE(radv_image, image, _image);
5418
5419 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5420
5421 pMemoryRequirements->size = image->size;
5422 pMemoryRequirements->alignment = image->alignment;
5423 }
5424
5425 void radv_GetImageMemoryRequirements2(
5426 VkDevice device,
5427 const VkImageMemoryRequirementsInfo2 *pInfo,
5428 VkMemoryRequirements2 *pMemoryRequirements)
5429 {
5430 radv_GetImageMemoryRequirements(device, pInfo->image,
5431 &pMemoryRequirements->memoryRequirements);
5432
5433 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5434
5435 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5436 switch (ext->sType) {
5437 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5438 VkMemoryDedicatedRequirements *req =
5439 (VkMemoryDedicatedRequirements *) ext;
5440 req->requiresDedicatedAllocation = image->shareable &&
5441 image->tiling != VK_IMAGE_TILING_LINEAR;
5442 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5443 break;
5444 }
5445 default:
5446 break;
5447 }
5448 }
5449 }
5450
5451 void radv_GetImageSparseMemoryRequirements(
5452 VkDevice device,
5453 VkImage image,
5454 uint32_t* pSparseMemoryRequirementCount,
5455 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5456 {
5457 stub();
5458 }
5459
5460 void radv_GetImageSparseMemoryRequirements2(
5461 VkDevice device,
5462 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5463 uint32_t* pSparseMemoryRequirementCount,
5464 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5465 {
5466 stub();
5467 }
5468
5469 void radv_GetDeviceMemoryCommitment(
5470 VkDevice device,
5471 VkDeviceMemory memory,
5472 VkDeviceSize* pCommittedMemoryInBytes)
5473 {
5474 *pCommittedMemoryInBytes = 0;
5475 }
5476
5477 VkResult radv_BindBufferMemory2(VkDevice device,
5478 uint32_t bindInfoCount,
5479 const VkBindBufferMemoryInfo *pBindInfos)
5480 {
5481 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5482 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5483 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5484
5485 if (mem) {
5486 buffer->bo = mem->bo;
5487 buffer->offset = pBindInfos[i].memoryOffset;
5488 } else {
5489 buffer->bo = NULL;
5490 }
5491 }
5492 return VK_SUCCESS;
5493 }
5494
5495 VkResult radv_BindBufferMemory(
5496 VkDevice device,
5497 VkBuffer buffer,
5498 VkDeviceMemory memory,
5499 VkDeviceSize memoryOffset)
5500 {
5501 const VkBindBufferMemoryInfo info = {
5502 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5503 .buffer = buffer,
5504 .memory = memory,
5505 .memoryOffset = memoryOffset
5506 };
5507
5508 return radv_BindBufferMemory2(device, 1, &info);
5509 }
5510
5511 VkResult radv_BindImageMemory2(VkDevice device,
5512 uint32_t bindInfoCount,
5513 const VkBindImageMemoryInfo *pBindInfos)
5514 {
5515 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5516 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5517 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5518
5519 if (mem) {
5520 image->bo = mem->bo;
5521 image->offset = pBindInfos[i].memoryOffset;
5522 } else {
5523 image->bo = NULL;
5524 image->offset = 0;
5525 }
5526 }
5527 return VK_SUCCESS;
5528 }
5529
5530
5531 VkResult radv_BindImageMemory(
5532 VkDevice device,
5533 VkImage image,
5534 VkDeviceMemory memory,
5535 VkDeviceSize memoryOffset)
5536 {
5537 const VkBindImageMemoryInfo info = {
5538 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5539 .image = image,
5540 .memory = memory,
5541 .memoryOffset = memoryOffset
5542 };
5543
5544 return radv_BindImageMemory2(device, 1, &info);
5545 }
5546
5547 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5548 {
5549 return info->bufferBindCount ||
5550 info->imageOpaqueBindCount ||
5551 info->imageBindCount ||
5552 info->waitSemaphoreCount ||
5553 info->signalSemaphoreCount;
5554 }
5555
5556 VkResult radv_QueueBindSparse(
5557 VkQueue _queue,
5558 uint32_t bindInfoCount,
5559 const VkBindSparseInfo* pBindInfo,
5560 VkFence fence)
5561 {
5562 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5563 VkResult result;
5564 uint32_t fence_idx = 0;
5565
5566 if (radv_device_is_lost(queue->device))
5567 return VK_ERROR_DEVICE_LOST;
5568
5569 if (fence != VK_NULL_HANDLE) {
5570 for (uint32_t i = 0; i < bindInfoCount; ++i)
5571 if (radv_sparse_bind_has_effects(pBindInfo + i))
5572 fence_idx = i;
5573 } else
5574 fence_idx = UINT32_MAX;
5575
5576 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5577 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5578 continue;
5579
5580 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5581 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5582
5583 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5584 .buffer_binds = pBindInfo[i].pBufferBinds,
5585 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5586 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5587 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5588 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5589 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5590 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5591 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5592 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5593 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5594 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5595 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5596 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5597 });
5598
5599 if (result != VK_SUCCESS)
5600 return result;
5601 }
5602
5603 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5604 result = radv_signal_fence(queue, fence);
5605 if (result != VK_SUCCESS)
5606 return result;
5607 }
5608
5609 return VK_SUCCESS;
5610 }
5611
5612 static void
5613 radv_destroy_fence_part(struct radv_device *device,
5614 struct radv_fence_part *part)
5615 {
5616 switch (part->kind) {
5617 case RADV_FENCE_NONE:
5618 break;
5619 case RADV_FENCE_WINSYS:
5620 device->ws->destroy_fence(part->fence);
5621 break;
5622 case RADV_FENCE_SYNCOBJ:
5623 device->ws->destroy_syncobj(device->ws, part->syncobj);
5624 break;
5625 case RADV_FENCE_WSI:
5626 part->fence_wsi->destroy(part->fence_wsi);
5627 break;
5628 default:
5629 unreachable("Invalid fence type");
5630 }
5631
5632 part->kind = RADV_FENCE_NONE;
5633 }
5634
5635 static void
5636 radv_destroy_fence(struct radv_device *device,
5637 const VkAllocationCallbacks *pAllocator,
5638 struct radv_fence *fence)
5639 {
5640 radv_destroy_fence_part(device, &fence->temporary);
5641 radv_destroy_fence_part(device, &fence->permanent);
5642
5643 vk_object_base_finish(&fence->base);
5644 vk_free2(&device->vk.alloc, pAllocator, fence);
5645 }
5646
5647 VkResult radv_CreateFence(
5648 VkDevice _device,
5649 const VkFenceCreateInfo* pCreateInfo,
5650 const VkAllocationCallbacks* pAllocator,
5651 VkFence* pFence)
5652 {
5653 RADV_FROM_HANDLE(radv_device, device, _device);
5654 const VkExportFenceCreateInfo *export =
5655 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5656 VkExternalFenceHandleTypeFlags handleTypes =
5657 export ? export->handleTypes : 0;
5658 struct radv_fence *fence;
5659
5660 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5661 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5662 if (!fence)
5663 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5664
5665 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5666
5667 if (device->always_use_syncobj || handleTypes) {
5668 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5669
5670 bool create_signaled = false;
5671 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5672 create_signaled = true;
5673
5674 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5675 &fence->permanent.syncobj);
5676 if (ret) {
5677 radv_destroy_fence(device, pAllocator, fence);
5678 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5679 }
5680 } else {
5681 fence->permanent.kind = RADV_FENCE_WINSYS;
5682
5683 fence->permanent.fence = device->ws->create_fence();
5684 if (!fence->permanent.fence) {
5685 vk_free2(&device->vk.alloc, pAllocator, fence);
5686 radv_destroy_fence(device, pAllocator, fence);
5687 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5688 }
5689 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5690 device->ws->signal_fence(fence->permanent.fence);
5691 }
5692
5693 *pFence = radv_fence_to_handle(fence);
5694
5695 return VK_SUCCESS;
5696 }
5697
5698
5699 void radv_DestroyFence(
5700 VkDevice _device,
5701 VkFence _fence,
5702 const VkAllocationCallbacks* pAllocator)
5703 {
5704 RADV_FROM_HANDLE(radv_device, device, _device);
5705 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5706
5707 if (!fence)
5708 return;
5709
5710 radv_destroy_fence(device, pAllocator, fence);
5711 }
5712
5713 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5714 uint32_t fenceCount, const VkFence *pFences)
5715 {
5716 for (uint32_t i = 0; i < fenceCount; ++i) {
5717 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5718
5719 struct radv_fence_part *part =
5720 fence->temporary.kind != RADV_FENCE_NONE ?
5721 &fence->temporary : &fence->permanent;
5722 if (part->kind != RADV_FENCE_WINSYS ||
5723 !device->ws->is_fence_waitable(part->fence))
5724 return false;
5725 }
5726 return true;
5727 }
5728
5729 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5730 {
5731 for (uint32_t i = 0; i < fenceCount; ++i) {
5732 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5733
5734 struct radv_fence_part *part =
5735 fence->temporary.kind != RADV_FENCE_NONE ?
5736 &fence->temporary : &fence->permanent;
5737 if (part->kind != RADV_FENCE_SYNCOBJ)
5738 return false;
5739 }
5740 return true;
5741 }
5742
5743 VkResult radv_WaitForFences(
5744 VkDevice _device,
5745 uint32_t fenceCount,
5746 const VkFence* pFences,
5747 VkBool32 waitAll,
5748 uint64_t timeout)
5749 {
5750 RADV_FROM_HANDLE(radv_device, device, _device);
5751
5752 if (radv_device_is_lost(device))
5753 return VK_ERROR_DEVICE_LOST;
5754
5755 timeout = radv_get_absolute_timeout(timeout);
5756
5757 if (device->always_use_syncobj &&
5758 radv_all_fences_syncobj(fenceCount, pFences))
5759 {
5760 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5761 if (!handles)
5762 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5763
5764 for (uint32_t i = 0; i < fenceCount; ++i) {
5765 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5766
5767 struct radv_fence_part *part =
5768 fence->temporary.kind != RADV_FENCE_NONE ?
5769 &fence->temporary : &fence->permanent;
5770
5771 assert(part->kind == RADV_FENCE_SYNCOBJ);
5772 handles[i] = part->syncobj;
5773 }
5774
5775 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5776
5777 free(handles);
5778 return success ? VK_SUCCESS : VK_TIMEOUT;
5779 }
5780
5781 if (!waitAll && fenceCount > 1) {
5782 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5783 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5784 uint32_t wait_count = 0;
5785 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5786 if (!fences)
5787 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5788
5789 for (uint32_t i = 0; i < fenceCount; ++i) {
5790 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5791
5792 struct radv_fence_part *part =
5793 fence->temporary.kind != RADV_FENCE_NONE ?
5794 &fence->temporary : &fence->permanent;
5795 assert(part->kind == RADV_FENCE_WINSYS);
5796
5797 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5798 free(fences);
5799 return VK_SUCCESS;
5800 }
5801
5802 fences[wait_count++] = part->fence;
5803 }
5804
5805 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5806 waitAll, timeout - radv_get_current_time());
5807
5808 free(fences);
5809 return success ? VK_SUCCESS : VK_TIMEOUT;
5810 }
5811
5812 while(radv_get_current_time() <= timeout) {
5813 for (uint32_t i = 0; i < fenceCount; ++i) {
5814 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5815 return VK_SUCCESS;
5816 }
5817 }
5818 return VK_TIMEOUT;
5819 }
5820
5821 for (uint32_t i = 0; i < fenceCount; ++i) {
5822 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5823 bool expired = false;
5824
5825 struct radv_fence_part *part =
5826 fence->temporary.kind != RADV_FENCE_NONE ?
5827 &fence->temporary : &fence->permanent;
5828
5829 switch (part->kind) {
5830 case RADV_FENCE_NONE:
5831 break;
5832 case RADV_FENCE_WINSYS:
5833 if (!device->ws->is_fence_waitable(part->fence)) {
5834 while (!device->ws->is_fence_waitable(part->fence) &&
5835 radv_get_current_time() <= timeout)
5836 /* Do nothing */;
5837 }
5838
5839 expired = device->ws->fence_wait(device->ws,
5840 part->fence,
5841 true, timeout);
5842 if (!expired)
5843 return VK_TIMEOUT;
5844 break;
5845 case RADV_FENCE_SYNCOBJ:
5846 if (!device->ws->wait_syncobj(device->ws,
5847 &part->syncobj, 1, true,
5848 timeout))
5849 return VK_TIMEOUT;
5850 break;
5851 case RADV_FENCE_WSI: {
5852 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5853 if (result != VK_SUCCESS)
5854 return result;
5855 break;
5856 }
5857 default:
5858 unreachable("Invalid fence type");
5859 }
5860 }
5861
5862 return VK_SUCCESS;
5863 }
5864
5865 VkResult radv_ResetFences(VkDevice _device,
5866 uint32_t fenceCount,
5867 const VkFence *pFences)
5868 {
5869 RADV_FROM_HANDLE(radv_device, device, _device);
5870
5871 for (unsigned i = 0; i < fenceCount; ++i) {
5872 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5873
5874 /* From the Vulkan 1.0.53 spec:
5875 *
5876 * "If any member of pFences currently has its payload
5877 * imported with temporary permanence, that fence’s prior
5878 * permanent payload is irst restored. The remaining
5879 * operations described therefore operate on the restored
5880 * payload."
5881 */
5882 if (fence->temporary.kind != RADV_FENCE_NONE)
5883 radv_destroy_fence_part(device, &fence->temporary);
5884
5885 struct radv_fence_part *part = &fence->permanent;
5886
5887 switch (part->kind) {
5888 case RADV_FENCE_WSI:
5889 device->ws->reset_fence(part->fence);
5890 break;
5891 case RADV_FENCE_SYNCOBJ:
5892 device->ws->reset_syncobj(device->ws, part->syncobj);
5893 break;
5894 default:
5895 unreachable("Invalid fence type");
5896 }
5897 }
5898
5899 return VK_SUCCESS;
5900 }
5901
5902 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5903 {
5904 RADV_FROM_HANDLE(radv_device, device, _device);
5905 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5906
5907 struct radv_fence_part *part =
5908 fence->temporary.kind != RADV_FENCE_NONE ?
5909 &fence->temporary : &fence->permanent;
5910
5911 if (radv_device_is_lost(device))
5912 return VK_ERROR_DEVICE_LOST;
5913
5914 switch (part->kind) {
5915 case RADV_FENCE_NONE:
5916 break;
5917 case RADV_FENCE_WINSYS:
5918 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5919 return VK_NOT_READY;
5920 break;
5921 case RADV_FENCE_SYNCOBJ: {
5922 bool success = device->ws->wait_syncobj(device->ws,
5923 &part->syncobj, 1, true, 0);
5924 if (!success)
5925 return VK_NOT_READY;
5926 break;
5927 }
5928 case RADV_FENCE_WSI: {
5929 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5930 if (result != VK_SUCCESS) {
5931 if (result == VK_TIMEOUT)
5932 return VK_NOT_READY;
5933 return result;
5934 }
5935 break;
5936 }
5937 default:
5938 unreachable("Invalid fence type");
5939 }
5940
5941 return VK_SUCCESS;
5942 }
5943
5944
5945 // Queue semaphore functions
5946
5947 static void
5948 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5949 {
5950 timeline->highest_signaled = value;
5951 timeline->highest_submitted = value;
5952 list_inithead(&timeline->points);
5953 list_inithead(&timeline->free_points);
5954 list_inithead(&timeline->waiters);
5955 pthread_mutex_init(&timeline->mutex, NULL);
5956 }
5957
5958 static void
5959 radv_destroy_timeline(struct radv_device *device,
5960 struct radv_timeline *timeline)
5961 {
5962 list_for_each_entry_safe(struct radv_timeline_point, point,
5963 &timeline->free_points, list) {
5964 list_del(&point->list);
5965 device->ws->destroy_syncobj(device->ws, point->syncobj);
5966 free(point);
5967 }
5968 list_for_each_entry_safe(struct radv_timeline_point, point,
5969 &timeline->points, list) {
5970 list_del(&point->list);
5971 device->ws->destroy_syncobj(device->ws, point->syncobj);
5972 free(point);
5973 }
5974 pthread_mutex_destroy(&timeline->mutex);
5975 }
5976
5977 static void
5978 radv_timeline_gc_locked(struct radv_device *device,
5979 struct radv_timeline *timeline)
5980 {
5981 list_for_each_entry_safe(struct radv_timeline_point, point,
5982 &timeline->points, list) {
5983 if (point->wait_count || point->value > timeline->highest_submitted)
5984 return;
5985
5986 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5987 timeline->highest_signaled = point->value;
5988 list_del(&point->list);
5989 list_add(&point->list, &timeline->free_points);
5990 }
5991 }
5992 }
5993
5994 static struct radv_timeline_point *
5995 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5996 struct radv_timeline *timeline,
5997 uint64_t p)
5998 {
5999 radv_timeline_gc_locked(device, timeline);
6000
6001 if (p <= timeline->highest_signaled)
6002 return NULL;
6003
6004 list_for_each_entry(struct radv_timeline_point, point,
6005 &timeline->points, list) {
6006 if (point->value >= p) {
6007 ++point->wait_count;
6008 return point;
6009 }
6010 }
6011 return NULL;
6012 }
6013
6014 static struct radv_timeline_point *
6015 radv_timeline_add_point_locked(struct radv_device *device,
6016 struct radv_timeline *timeline,
6017 uint64_t p)
6018 {
6019 radv_timeline_gc_locked(device, timeline);
6020
6021 struct radv_timeline_point *ret = NULL;
6022 struct radv_timeline_point *prev = NULL;
6023 int r;
6024
6025 if (p <= timeline->highest_signaled)
6026 return NULL;
6027
6028 list_for_each_entry(struct radv_timeline_point, point,
6029 &timeline->points, list) {
6030 if (point->value == p) {
6031 return NULL;
6032 }
6033
6034 if (point->value < p)
6035 prev = point;
6036 }
6037
6038 if (list_is_empty(&timeline->free_points)) {
6039 ret = malloc(sizeof(struct radv_timeline_point));
6040 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
6041 if (r) {
6042 free(ret);
6043 return NULL;
6044 }
6045 } else {
6046 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
6047 list_del(&ret->list);
6048
6049 device->ws->reset_syncobj(device->ws, ret->syncobj);
6050 }
6051
6052 ret->value = p;
6053 ret->wait_count = 1;
6054
6055 if (prev) {
6056 list_add(&ret->list, &prev->list);
6057 } else {
6058 list_addtail(&ret->list, &timeline->points);
6059 }
6060 return ret;
6061 }
6062
6063
6064 static VkResult
6065 radv_timeline_wait(struct radv_device *device,
6066 struct radv_timeline *timeline,
6067 uint64_t value,
6068 uint64_t abs_timeout)
6069 {
6070 pthread_mutex_lock(&timeline->mutex);
6071
6072 while(timeline->highest_submitted < value) {
6073 struct timespec abstime;
6074 timespec_from_nsec(&abstime, abs_timeout);
6075
6076 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
6077
6078 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value) {
6079 pthread_mutex_unlock(&timeline->mutex);
6080 return VK_TIMEOUT;
6081 }
6082 }
6083
6084 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
6085 pthread_mutex_unlock(&timeline->mutex);
6086 if (!point)
6087 return VK_SUCCESS;
6088
6089 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
6090
6091 pthread_mutex_lock(&timeline->mutex);
6092 point->wait_count--;
6093 pthread_mutex_unlock(&timeline->mutex);
6094 return success ? VK_SUCCESS : VK_TIMEOUT;
6095 }
6096
6097 static void
6098 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
6099 struct list_head *processing_list)
6100 {
6101 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
6102 &timeline->waiters, list) {
6103 if (waiter->value > timeline->highest_submitted)
6104 continue;
6105
6106 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
6107 list_del(&waiter->list);
6108 }
6109 }
6110
6111 static
6112 void radv_destroy_semaphore_part(struct radv_device *device,
6113 struct radv_semaphore_part *part)
6114 {
6115 switch(part->kind) {
6116 case RADV_SEMAPHORE_NONE:
6117 break;
6118 case RADV_SEMAPHORE_WINSYS:
6119 device->ws->destroy_sem(part->ws_sem);
6120 break;
6121 case RADV_SEMAPHORE_TIMELINE:
6122 radv_destroy_timeline(device, &part->timeline);
6123 break;
6124 case RADV_SEMAPHORE_SYNCOBJ:
6125 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
6126 device->ws->destroy_syncobj(device->ws, part->syncobj);
6127 break;
6128 }
6129 part->kind = RADV_SEMAPHORE_NONE;
6130 }
6131
6132 static VkSemaphoreTypeKHR
6133 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6134 {
6135 const VkSemaphoreTypeCreateInfo *type_info =
6136 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6137
6138 if (!type_info)
6139 return VK_SEMAPHORE_TYPE_BINARY;
6140
6141 if (initial_value)
6142 *initial_value = type_info->initialValue;
6143 return type_info->semaphoreType;
6144 }
6145
6146 static void
6147 radv_destroy_semaphore(struct radv_device *device,
6148 const VkAllocationCallbacks *pAllocator,
6149 struct radv_semaphore *sem)
6150 {
6151 radv_destroy_semaphore_part(device, &sem->temporary);
6152 radv_destroy_semaphore_part(device, &sem->permanent);
6153 vk_object_base_finish(&sem->base);
6154 vk_free2(&device->vk.alloc, pAllocator, sem);
6155 }
6156
6157 VkResult radv_CreateSemaphore(
6158 VkDevice _device,
6159 const VkSemaphoreCreateInfo* pCreateInfo,
6160 const VkAllocationCallbacks* pAllocator,
6161 VkSemaphore* pSemaphore)
6162 {
6163 RADV_FROM_HANDLE(radv_device, device, _device);
6164 const VkExportSemaphoreCreateInfo *export =
6165 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6166 VkExternalSemaphoreHandleTypeFlags handleTypes =
6167 export ? export->handleTypes : 0;
6168 uint64_t initial_value = 0;
6169 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6170
6171 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
6172 sizeof(*sem), 8,
6173 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6174 if (!sem)
6175 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6176
6177 vk_object_base_init(&device->vk, &sem->base,
6178 VK_OBJECT_TYPE_SEMAPHORE);
6179
6180 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6181 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6182
6183 if (type == VK_SEMAPHORE_TYPE_TIMELINE &&
6184 device->physical_device->rad_info.has_timeline_syncobj) {
6185 int ret = device->ws->create_syncobj(device->ws, false, &sem->permanent.syncobj);
6186 if (ret) {
6187 radv_destroy_semaphore(device, pAllocator, sem);
6188 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6189 }
6190 device->ws->signal_syncobj(device->ws, sem->permanent.syncobj, initial_value);
6191 sem->permanent.timeline_syncobj.max_point = initial_value;
6192 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
6193 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6194 radv_create_timeline(&sem->permanent.timeline, initial_value);
6195 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6196 } else if (device->always_use_syncobj || handleTypes) {
6197 assert (device->physical_device->rad_info.has_syncobj);
6198 int ret = device->ws->create_syncobj(device->ws, false,
6199 &sem->permanent.syncobj);
6200 if (ret) {
6201 radv_destroy_semaphore(device, pAllocator, sem);
6202 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6203 }
6204 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6205 } else {
6206 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6207 if (!sem->permanent.ws_sem) {
6208 radv_destroy_semaphore(device, pAllocator, sem);
6209 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6210 }
6211 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6212 }
6213
6214 *pSemaphore = radv_semaphore_to_handle(sem);
6215 return VK_SUCCESS;
6216 }
6217
6218 void radv_DestroySemaphore(
6219 VkDevice _device,
6220 VkSemaphore _semaphore,
6221 const VkAllocationCallbacks* pAllocator)
6222 {
6223 RADV_FROM_HANDLE(radv_device, device, _device);
6224 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6225 if (!_semaphore)
6226 return;
6227
6228 radv_destroy_semaphore(device, pAllocator, sem);
6229 }
6230
6231 VkResult
6232 radv_GetSemaphoreCounterValue(VkDevice _device,
6233 VkSemaphore _semaphore,
6234 uint64_t* pValue)
6235 {
6236 RADV_FROM_HANDLE(radv_device, device, _device);
6237 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6238
6239 if (radv_device_is_lost(device))
6240 return VK_ERROR_DEVICE_LOST;
6241
6242 struct radv_semaphore_part *part =
6243 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6244
6245 switch (part->kind) {
6246 case RADV_SEMAPHORE_TIMELINE: {
6247 pthread_mutex_lock(&part->timeline.mutex);
6248 radv_timeline_gc_locked(device, &part->timeline);
6249 *pValue = part->timeline.highest_signaled;
6250 pthread_mutex_unlock(&part->timeline.mutex);
6251 return VK_SUCCESS;
6252 }
6253 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6254 return device->ws->query_syncobj(device->ws, part->syncobj, pValue);
6255 }
6256 case RADV_SEMAPHORE_NONE:
6257 case RADV_SEMAPHORE_SYNCOBJ:
6258 case RADV_SEMAPHORE_WINSYS:
6259 unreachable("Invalid semaphore type");
6260 }
6261 unreachable("Unhandled semaphore type");
6262 }
6263
6264
6265 static VkResult
6266 radv_wait_timelines(struct radv_device *device,
6267 const VkSemaphoreWaitInfo* pWaitInfo,
6268 uint64_t abs_timeout)
6269 {
6270 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6271 for (;;) {
6272 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6273 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6274 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6275
6276 if (result == VK_SUCCESS)
6277 return VK_SUCCESS;
6278 }
6279 if (radv_get_current_time() > abs_timeout)
6280 return VK_TIMEOUT;
6281 }
6282 }
6283
6284 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6285 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6286 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6287
6288 if (result != VK_SUCCESS)
6289 return result;
6290 }
6291 return VK_SUCCESS;
6292 }
6293 VkResult
6294 radv_WaitSemaphores(VkDevice _device,
6295 const VkSemaphoreWaitInfo* pWaitInfo,
6296 uint64_t timeout)
6297 {
6298 RADV_FROM_HANDLE(radv_device, device, _device);
6299
6300 if (radv_device_is_lost(device))
6301 return VK_ERROR_DEVICE_LOST;
6302
6303 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6304
6305 if (radv_semaphore_from_handle(pWaitInfo->pSemaphores[0])->permanent.kind == RADV_SEMAPHORE_TIMELINE)
6306 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6307
6308 if (pWaitInfo->semaphoreCount > UINT32_MAX / sizeof(uint32_t))
6309 return vk_errorf(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY, "semaphoreCount integer overflow");
6310
6311 bool wait_all = !(pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR);
6312 uint32_t *handles = malloc(sizeof(*handles) * pWaitInfo->semaphoreCount);
6313 if (!handles)
6314 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6315
6316 for (uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6317 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6318 handles[i] = semaphore->permanent.syncobj;
6319 }
6320
6321 bool success = device->ws->wait_timeline_syncobj(device->ws, handles, pWaitInfo->pValues,
6322 pWaitInfo->semaphoreCount, wait_all, false,
6323 abs_timeout);
6324 free(handles);
6325 return success ? VK_SUCCESS : VK_TIMEOUT;
6326 }
6327
6328 VkResult
6329 radv_SignalSemaphore(VkDevice _device,
6330 const VkSemaphoreSignalInfo* pSignalInfo)
6331 {
6332 RADV_FROM_HANDLE(radv_device, device, _device);
6333 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6334
6335 struct radv_semaphore_part *part =
6336 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6337
6338 switch(part->kind) {
6339 case RADV_SEMAPHORE_TIMELINE: {
6340 pthread_mutex_lock(&part->timeline.mutex);
6341 radv_timeline_gc_locked(device, &part->timeline);
6342 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6343 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6344
6345 struct list_head processing_list;
6346 list_inithead(&processing_list);
6347 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6348 pthread_mutex_unlock(&part->timeline.mutex);
6349
6350 VkResult result = radv_process_submissions(&processing_list);
6351
6352 /* This needs to happen after radv_process_submissions, so
6353 * that any submitted submissions that are now unblocked get
6354 * processed before we wake the application. This way we
6355 * ensure that any binary semaphores that are now unblocked
6356 * are usable by the application. */
6357 pthread_cond_broadcast(&device->timeline_cond);
6358
6359 return result;
6360 }
6361 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6362 part->timeline_syncobj.max_point = MAX2(part->timeline_syncobj.max_point, pSignalInfo->value);
6363 device->ws->signal_syncobj(device->ws, part->syncobj, pSignalInfo->value);
6364 break;
6365 }
6366 case RADV_SEMAPHORE_NONE:
6367 case RADV_SEMAPHORE_SYNCOBJ:
6368 case RADV_SEMAPHORE_WINSYS:
6369 unreachable("Invalid semaphore type");
6370 }
6371 return VK_SUCCESS;
6372 }
6373
6374 static void radv_destroy_event(struct radv_device *device,
6375 const VkAllocationCallbacks* pAllocator,
6376 struct radv_event *event)
6377 {
6378 if (event->bo)
6379 device->ws->buffer_destroy(event->bo);
6380
6381 vk_object_base_finish(&event->base);
6382 vk_free2(&device->vk.alloc, pAllocator, event);
6383 }
6384
6385 VkResult radv_CreateEvent(
6386 VkDevice _device,
6387 const VkEventCreateInfo* pCreateInfo,
6388 const VkAllocationCallbacks* pAllocator,
6389 VkEvent* pEvent)
6390 {
6391 RADV_FROM_HANDLE(radv_device, device, _device);
6392 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6393 sizeof(*event), 8,
6394 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6395
6396 if (!event)
6397 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6398
6399 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6400
6401 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6402 RADEON_DOMAIN_GTT,
6403 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6404 RADV_BO_PRIORITY_FENCE);
6405 if (!event->bo) {
6406 radv_destroy_event(device, pAllocator, event);
6407 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6408 }
6409
6410 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6411 if (!event->map) {
6412 radv_destroy_event(device, pAllocator, event);
6413 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6414 }
6415
6416 *pEvent = radv_event_to_handle(event);
6417
6418 return VK_SUCCESS;
6419 }
6420
6421 void radv_DestroyEvent(
6422 VkDevice _device,
6423 VkEvent _event,
6424 const VkAllocationCallbacks* pAllocator)
6425 {
6426 RADV_FROM_HANDLE(radv_device, device, _device);
6427 RADV_FROM_HANDLE(radv_event, event, _event);
6428
6429 if (!event)
6430 return;
6431
6432 radv_destroy_event(device, pAllocator, event);
6433 }
6434
6435 VkResult radv_GetEventStatus(
6436 VkDevice _device,
6437 VkEvent _event)
6438 {
6439 RADV_FROM_HANDLE(radv_device, device, _device);
6440 RADV_FROM_HANDLE(radv_event, event, _event);
6441
6442 if (radv_device_is_lost(device))
6443 return VK_ERROR_DEVICE_LOST;
6444
6445 if (*event->map == 1)
6446 return VK_EVENT_SET;
6447 return VK_EVENT_RESET;
6448 }
6449
6450 VkResult radv_SetEvent(
6451 VkDevice _device,
6452 VkEvent _event)
6453 {
6454 RADV_FROM_HANDLE(radv_event, event, _event);
6455 *event->map = 1;
6456
6457 return VK_SUCCESS;
6458 }
6459
6460 VkResult radv_ResetEvent(
6461 VkDevice _device,
6462 VkEvent _event)
6463 {
6464 RADV_FROM_HANDLE(radv_event, event, _event);
6465 *event->map = 0;
6466
6467 return VK_SUCCESS;
6468 }
6469
6470 static void
6471 radv_destroy_buffer(struct radv_device *device,
6472 const VkAllocationCallbacks *pAllocator,
6473 struct radv_buffer *buffer)
6474 {
6475 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6476 device->ws->buffer_destroy(buffer->bo);
6477
6478 vk_object_base_finish(&buffer->base);
6479 vk_free2(&device->vk.alloc, pAllocator, buffer);
6480 }
6481
6482 VkResult radv_CreateBuffer(
6483 VkDevice _device,
6484 const VkBufferCreateInfo* pCreateInfo,
6485 const VkAllocationCallbacks* pAllocator,
6486 VkBuffer* pBuffer)
6487 {
6488 RADV_FROM_HANDLE(radv_device, device, _device);
6489 struct radv_buffer *buffer;
6490
6491 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6492 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6493
6494 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6495
6496 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6497 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6498 if (buffer == NULL)
6499 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6500
6501 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6502
6503 buffer->size = pCreateInfo->size;
6504 buffer->usage = pCreateInfo->usage;
6505 buffer->bo = NULL;
6506 buffer->offset = 0;
6507 buffer->flags = pCreateInfo->flags;
6508
6509 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6510 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6511
6512 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6513 buffer->bo = device->ws->buffer_create(device->ws,
6514 align64(buffer->size, 4096),
6515 4096, 0, RADEON_FLAG_VIRTUAL,
6516 RADV_BO_PRIORITY_VIRTUAL);
6517 if (!buffer->bo) {
6518 radv_destroy_buffer(device, pAllocator, buffer);
6519 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6520 }
6521 }
6522
6523 *pBuffer = radv_buffer_to_handle(buffer);
6524
6525 return VK_SUCCESS;
6526 }
6527
6528 void radv_DestroyBuffer(
6529 VkDevice _device,
6530 VkBuffer _buffer,
6531 const VkAllocationCallbacks* pAllocator)
6532 {
6533 RADV_FROM_HANDLE(radv_device, device, _device);
6534 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6535
6536 if (!buffer)
6537 return;
6538
6539 radv_destroy_buffer(device, pAllocator, buffer);
6540 }
6541
6542 VkDeviceAddress radv_GetBufferDeviceAddress(
6543 VkDevice device,
6544 const VkBufferDeviceAddressInfo* pInfo)
6545 {
6546 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6547 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6548 }
6549
6550
6551 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6552 const VkBufferDeviceAddressInfo* pInfo)
6553 {
6554 return 0;
6555 }
6556
6557 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6558 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6559 {
6560 return 0;
6561 }
6562
6563 static inline unsigned
6564 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6565 {
6566 if (stencil)
6567 return plane->surface.u.legacy.stencil_tiling_index[level];
6568 else
6569 return plane->surface.u.legacy.tiling_index[level];
6570 }
6571
6572 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6573 {
6574 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6575 }
6576
6577 static uint32_t
6578 radv_init_dcc_control_reg(struct radv_device *device,
6579 struct radv_image_view *iview)
6580 {
6581 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6582 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6583 unsigned max_compressed_block_size;
6584 unsigned independent_128b_blocks;
6585 unsigned independent_64b_blocks;
6586
6587 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6588 return 0;
6589
6590 if (!device->physical_device->rad_info.has_dedicated_vram) {
6591 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6592 * dGPU and 64 for APU because all of our APUs to date use
6593 * DIMMs which have a request granularity size of 64B while all
6594 * other chips have a 32B request size.
6595 */
6596 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6597 }
6598
6599 if (device->physical_device->rad_info.chip_class >= GFX10) {
6600 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6601 independent_64b_blocks = 0;
6602 independent_128b_blocks = 1;
6603 } else {
6604 independent_128b_blocks = 0;
6605
6606 if (iview->image->info.samples > 1) {
6607 if (iview->image->planes[0].surface.bpe == 1)
6608 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6609 else if (iview->image->planes[0].surface.bpe == 2)
6610 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6611 }
6612
6613 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6614 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6615 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6616 /* If this DCC image is potentially going to be used in texture
6617 * fetches, we need some special settings.
6618 */
6619 independent_64b_blocks = 1;
6620 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6621 } else {
6622 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6623 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6624 * big as possible for better compression state.
6625 */
6626 independent_64b_blocks = 0;
6627 max_compressed_block_size = max_uncompressed_block_size;
6628 }
6629 }
6630
6631 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6632 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6633 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6634 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6635 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6636 }
6637
6638 void
6639 radv_initialise_color_surface(struct radv_device *device,
6640 struct radv_color_buffer_info *cb,
6641 struct radv_image_view *iview)
6642 {
6643 const struct vk_format_description *desc;
6644 unsigned ntype, format, swap, endian;
6645 unsigned blend_clamp = 0, blend_bypass = 0;
6646 uint64_t va;
6647 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6648 const struct radeon_surf *surf = &plane->surface;
6649
6650 desc = vk_format_description(iview->vk_format);
6651
6652 memset(cb, 0, sizeof(*cb));
6653
6654 /* Intensity is implemented as Red, so treat it that way. */
6655 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6656
6657 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6658
6659 cb->cb_color_base = va >> 8;
6660
6661 if (device->physical_device->rad_info.chip_class >= GFX9) {
6662 if (device->physical_device->rad_info.chip_class >= GFX10) {
6663 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6664 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6665 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6666 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6667 } else {
6668 struct gfx9_surf_meta_flags meta = {
6669 .rb_aligned = 1,
6670 .pipe_aligned = 1,
6671 };
6672
6673 if (surf->dcc_offset)
6674 meta = surf->u.gfx9.dcc;
6675
6676 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6677 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6678 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6679 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6680 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6681 }
6682
6683 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6684 cb->cb_color_base |= surf->tile_swizzle;
6685 } else {
6686 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6687 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6688
6689 cb->cb_color_base += level_info->offset >> 8;
6690 if (level_info->mode == RADEON_SURF_MODE_2D)
6691 cb->cb_color_base |= surf->tile_swizzle;
6692
6693 pitch_tile_max = level_info->nblk_x / 8 - 1;
6694 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6695 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6696
6697 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6698 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6699 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6700
6701 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6702
6703 if (radv_image_has_fmask(iview->image)) {
6704 if (device->physical_device->rad_info.chip_class >= GFX7)
6705 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6706 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6707 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6708 } else {
6709 /* This must be set for fast clear to work without FMASK. */
6710 if (device->physical_device->rad_info.chip_class >= GFX7)
6711 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6712 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6713 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6714 }
6715 }
6716
6717 /* CMASK variables */
6718 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6719 va += surf->cmask_offset;
6720 cb->cb_color_cmask = va >> 8;
6721
6722 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6723 va += surf->dcc_offset;
6724
6725 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6726 device->physical_device->rad_info.chip_class <= GFX8)
6727 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6728
6729 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6730 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6731
6732 cb->cb_dcc_base = va >> 8;
6733 cb->cb_dcc_base |= dcc_tile_swizzle;
6734
6735 /* GFX10 field has the same base shift as the GFX6 field. */
6736 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6737 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6738 S_028C6C_SLICE_MAX_GFX10(max_slice);
6739
6740 if (iview->image->info.samples > 1) {
6741 unsigned log_samples = util_logbase2(iview->image->info.samples);
6742
6743 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6744 S_028C74_NUM_FRAGMENTS(log_samples);
6745 }
6746
6747 if (radv_image_has_fmask(iview->image)) {
6748 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6749 cb->cb_color_fmask = va >> 8;
6750 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6751 } else {
6752 cb->cb_color_fmask = cb->cb_color_base;
6753 }
6754
6755 ntype = radv_translate_color_numformat(iview->vk_format,
6756 desc,
6757 vk_format_get_first_non_void_channel(iview->vk_format));
6758 format = radv_translate_colorformat(iview->vk_format);
6759 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6760 radv_finishme("Illegal color\n");
6761 swap = radv_translate_colorswap(iview->vk_format, false);
6762 endian = radv_colorformat_endian_swap(format);
6763
6764 /* blend clamp should be set for all NORM/SRGB types */
6765 if (ntype == V_028C70_NUMBER_UNORM ||
6766 ntype == V_028C70_NUMBER_SNORM ||
6767 ntype == V_028C70_NUMBER_SRGB)
6768 blend_clamp = 1;
6769
6770 /* set blend bypass according to docs if SINT/UINT or
6771 8/24 COLOR variants */
6772 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6773 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6774 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6775 blend_clamp = 0;
6776 blend_bypass = 1;
6777 }
6778 #if 0
6779 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6780 (format == V_028C70_COLOR_8 ||
6781 format == V_028C70_COLOR_8_8 ||
6782 format == V_028C70_COLOR_8_8_8_8))
6783 ->color_is_int8 = true;
6784 #endif
6785 cb->cb_color_info = S_028C70_FORMAT(format) |
6786 S_028C70_COMP_SWAP(swap) |
6787 S_028C70_BLEND_CLAMP(blend_clamp) |
6788 S_028C70_BLEND_BYPASS(blend_bypass) |
6789 S_028C70_SIMPLE_FLOAT(1) |
6790 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6791 ntype != V_028C70_NUMBER_SNORM &&
6792 ntype != V_028C70_NUMBER_SRGB &&
6793 format != V_028C70_COLOR_8_24 &&
6794 format != V_028C70_COLOR_24_8) |
6795 S_028C70_NUMBER_TYPE(ntype) |
6796 S_028C70_ENDIAN(endian);
6797 if (radv_image_has_fmask(iview->image)) {
6798 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6799 if (device->physical_device->rad_info.chip_class == GFX6) {
6800 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6801 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6802 }
6803
6804 if (radv_image_is_tc_compat_cmask(iview->image)) {
6805 /* Allow the texture block to read FMASK directly
6806 * without decompressing it. This bit must be cleared
6807 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6808 * otherwise the operation doesn't happen.
6809 */
6810 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6811
6812 /* Set CMASK into a tiling format that allows the
6813 * texture block to read it.
6814 */
6815 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6816 }
6817 }
6818
6819 if (radv_image_has_cmask(iview->image) &&
6820 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6821 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6822
6823 if (radv_dcc_enabled(iview->image, iview->base_mip))
6824 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6825
6826 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6827
6828 /* This must be set for fast clear to work without FMASK. */
6829 if (!radv_image_has_fmask(iview->image) &&
6830 device->physical_device->rad_info.chip_class == GFX6) {
6831 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6832 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6833 }
6834
6835 if (device->physical_device->rad_info.chip_class >= GFX9) {
6836 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6837
6838 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6839 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6840 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6841 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6842
6843 if (device->physical_device->rad_info.chip_class >= GFX10) {
6844 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6845
6846 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6847 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6848 S_028EE0_RESOURCE_LEVEL(1);
6849 } else {
6850 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6851 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6852 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6853 }
6854
6855 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6856 S_028C68_MIP0_HEIGHT(height - 1) |
6857 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6858 }
6859 }
6860
6861 static unsigned
6862 radv_calc_decompress_on_z_planes(struct radv_device *device,
6863 struct radv_image_view *iview)
6864 {
6865 unsigned max_zplanes = 0;
6866
6867 assert(radv_image_is_tc_compat_htile(iview->image));
6868
6869 if (device->physical_device->rad_info.chip_class >= GFX9) {
6870 /* Default value for 32-bit depth surfaces. */
6871 max_zplanes = 4;
6872
6873 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6874 iview->image->info.samples > 1)
6875 max_zplanes = 2;
6876
6877 max_zplanes = max_zplanes + 1;
6878 } else {
6879 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6880 /* Do not enable Z plane compression for 16-bit depth
6881 * surfaces because isn't supported on GFX8. Only
6882 * 32-bit depth surfaces are supported by the hardware.
6883 * This allows to maintain shader compatibility and to
6884 * reduce the number of depth decompressions.
6885 */
6886 max_zplanes = 1;
6887 } else {
6888 if (iview->image->info.samples <= 1)
6889 max_zplanes = 5;
6890 else if (iview->image->info.samples <= 4)
6891 max_zplanes = 3;
6892 else
6893 max_zplanes = 2;
6894 }
6895 }
6896
6897 return max_zplanes;
6898 }
6899
6900 void
6901 radv_initialise_ds_surface(struct radv_device *device,
6902 struct radv_ds_buffer_info *ds,
6903 struct radv_image_view *iview)
6904 {
6905 unsigned level = iview->base_mip;
6906 unsigned format, stencil_format;
6907 uint64_t va, s_offs, z_offs;
6908 bool stencil_only = false;
6909 const struct radv_image_plane *plane = &iview->image->planes[0];
6910 const struct radeon_surf *surf = &plane->surface;
6911
6912 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6913
6914 memset(ds, 0, sizeof(*ds));
6915 switch (iview->image->vk_format) {
6916 case VK_FORMAT_D24_UNORM_S8_UINT:
6917 case VK_FORMAT_X8_D24_UNORM_PACK32:
6918 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6919 ds->offset_scale = 2.0f;
6920 break;
6921 case VK_FORMAT_D16_UNORM:
6922 case VK_FORMAT_D16_UNORM_S8_UINT:
6923 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6924 ds->offset_scale = 4.0f;
6925 break;
6926 case VK_FORMAT_D32_SFLOAT:
6927 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6928 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6929 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6930 ds->offset_scale = 1.0f;
6931 break;
6932 case VK_FORMAT_S8_UINT:
6933 stencil_only = true;
6934 break;
6935 default:
6936 break;
6937 }
6938
6939 format = radv_translate_dbformat(iview->image->vk_format);
6940 stencil_format = surf->has_stencil ?
6941 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6942
6943 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6944 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6945 S_028008_SLICE_MAX(max_slice);
6946 if (device->physical_device->rad_info.chip_class >= GFX10) {
6947 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6948 S_028008_SLICE_MAX_HI(max_slice >> 11);
6949 }
6950
6951 ds->db_htile_data_base = 0;
6952 ds->db_htile_surface = 0;
6953
6954 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6955 s_offs = z_offs = va;
6956
6957 if (device->physical_device->rad_info.chip_class >= GFX9) {
6958 assert(surf->u.gfx9.surf_offset == 0);
6959 s_offs += surf->u.gfx9.stencil_offset;
6960
6961 ds->db_z_info = S_028038_FORMAT(format) |
6962 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6963 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6964 S_028038_MAXMIP(iview->image->info.levels - 1) |
6965 S_028038_ZRANGE_PRECISION(1);
6966 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6967 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6968
6969 if (device->physical_device->rad_info.chip_class == GFX9) {
6970 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6971 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6972 }
6973
6974 ds->db_depth_view |= S_028008_MIPID(level);
6975 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6976 S_02801C_Y_MAX(iview->image->info.height - 1);
6977
6978 if (radv_htile_enabled(iview->image, level)) {
6979 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6980
6981 if (radv_image_is_tc_compat_htile(iview->image)) {
6982 unsigned max_zplanes =
6983 radv_calc_decompress_on_z_planes(device, iview);
6984
6985 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6986
6987 if (device->physical_device->rad_info.chip_class >= GFX10) {
6988 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6989 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6990 } else {
6991 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6992 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6993 }
6994 }
6995
6996 if (!surf->has_stencil)
6997 /* Use all of the htile_buffer for depth if there's no stencil. */
6998 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6999 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7000 surf->htile_offset;
7001 ds->db_htile_data_base = va >> 8;
7002 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
7003 S_028ABC_PIPE_ALIGNED(1);
7004
7005 if (device->physical_device->rad_info.chip_class == GFX9) {
7006 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
7007 }
7008 }
7009 } else {
7010 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
7011
7012 if (stencil_only)
7013 level_info = &surf->u.legacy.stencil_level[level];
7014
7015 z_offs += surf->u.legacy.level[level].offset;
7016 s_offs += surf->u.legacy.stencil_level[level].offset;
7017
7018 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
7019 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
7020 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
7021
7022 if (iview->image->info.samples > 1)
7023 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
7024
7025 if (device->physical_device->rad_info.chip_class >= GFX7) {
7026 struct radeon_info *info = &device->physical_device->rad_info;
7027 unsigned tiling_index = surf->u.legacy.tiling_index[level];
7028 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
7029 unsigned macro_index = surf->u.legacy.macro_tile_index;
7030 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
7031 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
7032 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
7033
7034 if (stencil_only)
7035 tile_mode = stencil_tile_mode;
7036
7037 ds->db_depth_info |=
7038 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
7039 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
7040 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
7041 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
7042 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
7043 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
7044 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
7045 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
7046 } else {
7047 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
7048 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7049 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
7050 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
7051 if (stencil_only)
7052 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
7053 }
7054
7055 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
7056 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
7057 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
7058
7059 if (radv_htile_enabled(iview->image, level)) {
7060 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
7061
7062 if (!surf->has_stencil &&
7063 !radv_image_is_tc_compat_htile(iview->image))
7064 /* Use all of the htile_buffer for depth if there's no stencil. */
7065 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
7066
7067 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
7068 surf->htile_offset;
7069 ds->db_htile_data_base = va >> 8;
7070 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
7071
7072 if (radv_image_is_tc_compat_htile(iview->image)) {
7073 unsigned max_zplanes =
7074 radv_calc_decompress_on_z_planes(device, iview);
7075
7076 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
7077 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
7078 }
7079 }
7080 }
7081
7082 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
7083 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
7084 }
7085
7086 VkResult radv_CreateFramebuffer(
7087 VkDevice _device,
7088 const VkFramebufferCreateInfo* pCreateInfo,
7089 const VkAllocationCallbacks* pAllocator,
7090 VkFramebuffer* pFramebuffer)
7091 {
7092 RADV_FROM_HANDLE(radv_device, device, _device);
7093 struct radv_framebuffer *framebuffer;
7094 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
7095 vk_find_struct_const(pCreateInfo->pNext,
7096 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
7097
7098 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
7099
7100 size_t size = sizeof(*framebuffer);
7101 if (!imageless_create_info)
7102 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
7103 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
7104 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7105 if (framebuffer == NULL)
7106 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7107
7108 vk_object_base_init(&device->vk, &framebuffer->base,
7109 VK_OBJECT_TYPE_FRAMEBUFFER);
7110
7111 framebuffer->attachment_count = pCreateInfo->attachmentCount;
7112 framebuffer->width = pCreateInfo->width;
7113 framebuffer->height = pCreateInfo->height;
7114 framebuffer->layers = pCreateInfo->layers;
7115 if (imageless_create_info) {
7116 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
7117 const VkFramebufferAttachmentImageInfo *attachment =
7118 imageless_create_info->pAttachmentImageInfos + i;
7119 framebuffer->width = MIN2(framebuffer->width, attachment->width);
7120 framebuffer->height = MIN2(framebuffer->height, attachment->height);
7121 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
7122 }
7123 } else {
7124 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
7125 VkImageView _iview = pCreateInfo->pAttachments[i];
7126 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
7127 framebuffer->attachments[i] = iview;
7128 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
7129 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
7130 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
7131 }
7132 }
7133
7134 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
7135 return VK_SUCCESS;
7136 }
7137
7138 void radv_DestroyFramebuffer(
7139 VkDevice _device,
7140 VkFramebuffer _fb,
7141 const VkAllocationCallbacks* pAllocator)
7142 {
7143 RADV_FROM_HANDLE(radv_device, device, _device);
7144 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
7145
7146 if (!fb)
7147 return;
7148 vk_object_base_finish(&fb->base);
7149 vk_free2(&device->vk.alloc, pAllocator, fb);
7150 }
7151
7152 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
7153 {
7154 switch (address_mode) {
7155 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
7156 return V_008F30_SQ_TEX_WRAP;
7157 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
7158 return V_008F30_SQ_TEX_MIRROR;
7159 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
7160 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
7161 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
7162 return V_008F30_SQ_TEX_CLAMP_BORDER;
7163 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
7164 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
7165 default:
7166 unreachable("illegal tex wrap mode");
7167 break;
7168 }
7169 }
7170
7171 static unsigned
7172 radv_tex_compare(VkCompareOp op)
7173 {
7174 switch (op) {
7175 case VK_COMPARE_OP_NEVER:
7176 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7177 case VK_COMPARE_OP_LESS:
7178 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
7179 case VK_COMPARE_OP_EQUAL:
7180 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
7181 case VK_COMPARE_OP_LESS_OR_EQUAL:
7182 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
7183 case VK_COMPARE_OP_GREATER:
7184 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
7185 case VK_COMPARE_OP_NOT_EQUAL:
7186 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
7187 case VK_COMPARE_OP_GREATER_OR_EQUAL:
7188 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
7189 case VK_COMPARE_OP_ALWAYS:
7190 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
7191 default:
7192 unreachable("illegal compare mode");
7193 break;
7194 }
7195 }
7196
7197 static unsigned
7198 radv_tex_filter(VkFilter filter, unsigned max_ansio)
7199 {
7200 switch (filter) {
7201 case VK_FILTER_NEAREST:
7202 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
7203 V_008F38_SQ_TEX_XY_FILTER_POINT);
7204 case VK_FILTER_LINEAR:
7205 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
7206 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
7207 case VK_FILTER_CUBIC_IMG:
7208 default:
7209 fprintf(stderr, "illegal texture filter");
7210 return 0;
7211 }
7212 }
7213
7214 static unsigned
7215 radv_tex_mipfilter(VkSamplerMipmapMode mode)
7216 {
7217 switch (mode) {
7218 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7219 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7220 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7221 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7222 default:
7223 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7224 }
7225 }
7226
7227 static unsigned
7228 radv_tex_bordercolor(VkBorderColor bcolor)
7229 {
7230 switch (bcolor) {
7231 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7232 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7233 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7234 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7235 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7236 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7237 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7238 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7239 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7240 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
7241 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
7242 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
7243 default:
7244 break;
7245 }
7246 return 0;
7247 }
7248
7249 static unsigned
7250 radv_tex_aniso_filter(unsigned filter)
7251 {
7252 if (filter < 2)
7253 return 0;
7254 if (filter < 4)
7255 return 1;
7256 if (filter < 8)
7257 return 2;
7258 if (filter < 16)
7259 return 3;
7260 return 4;
7261 }
7262
7263 static unsigned
7264 radv_tex_filter_mode(VkSamplerReductionMode mode)
7265 {
7266 switch (mode) {
7267 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7268 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7269 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7270 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7271 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7272 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7273 default:
7274 break;
7275 }
7276 return 0;
7277 }
7278
7279 static uint32_t
7280 radv_get_max_anisotropy(struct radv_device *device,
7281 const VkSamplerCreateInfo *pCreateInfo)
7282 {
7283 if (device->force_aniso >= 0)
7284 return device->force_aniso;
7285
7286 if (pCreateInfo->anisotropyEnable &&
7287 pCreateInfo->maxAnisotropy > 1.0f)
7288 return (uint32_t)pCreateInfo->maxAnisotropy;
7289
7290 return 0;
7291 }
7292
7293 static inline int S_FIXED(float value, unsigned frac_bits)
7294 {
7295 return value * (1 << frac_bits);
7296 }
7297
7298 static uint32_t radv_register_border_color(struct radv_device *device,
7299 VkClearColorValue value)
7300 {
7301 uint32_t slot;
7302
7303 pthread_mutex_lock(&device->border_color_data.mutex);
7304
7305 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
7306 if (!device->border_color_data.used[slot]) {
7307 /* Copy to the GPU wrt endian-ness. */
7308 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7309 &value,
7310 sizeof(VkClearColorValue));
7311
7312 device->border_color_data.used[slot] = true;
7313 break;
7314 }
7315 }
7316
7317 pthread_mutex_unlock(&device->border_color_data.mutex);
7318
7319 return slot;
7320 }
7321
7322 static void radv_unregister_border_color(struct radv_device *device,
7323 uint32_t slot)
7324 {
7325 pthread_mutex_lock(&device->border_color_data.mutex);
7326
7327 device->border_color_data.used[slot] = false;
7328
7329 pthread_mutex_unlock(&device->border_color_data.mutex);
7330 }
7331
7332 static void
7333 radv_init_sampler(struct radv_device *device,
7334 struct radv_sampler *sampler,
7335 const VkSamplerCreateInfo *pCreateInfo)
7336 {
7337 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7338 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7339 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7340 device->physical_device->rad_info.chip_class == GFX9;
7341 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7342 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7343 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7344 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7345 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7346 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7347 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7348 uint32_t border_color_ptr;
7349
7350 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7351 vk_find_struct_const(pCreateInfo->pNext,
7352 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7353 if (sampler_reduction)
7354 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7355
7356 if (pCreateInfo->compareEnable)
7357 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7358
7359 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7360
7361 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7362 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7363 vk_find_struct_const(pCreateInfo->pNext,
7364 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7365
7366 assert(custom_border_color);
7367
7368 sampler->border_color_slot =
7369 radv_register_border_color(device, custom_border_color->customBorderColor);
7370
7371 /* Did we fail to find a slot? */
7372 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7373 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7374 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7375 }
7376 }
7377
7378 /* If we don't have a custom color, set the ptr to 0 */
7379 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7380 ? sampler->border_color_slot
7381 : 0;
7382
7383 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7384 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7385 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7386 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7387 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7388 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7389 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7390 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7391 S_008F30_DISABLE_CUBE_WRAP(0) |
7392 S_008F30_COMPAT_MODE(compat_mode) |
7393 S_008F30_FILTER_MODE(filter_mode) |
7394 S_008F30_TRUNC_COORD(trunc_coord));
7395 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7396 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7397 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7398 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7399 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7400 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7401 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7402 S_008F38_MIP_POINT_PRECLAMP(0));
7403 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7404 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7405
7406 if (device->physical_device->rad_info.chip_class >= GFX10) {
7407 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7408 } else {
7409 sampler->state[2] |=
7410 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7411 S_008F38_FILTER_PREC_FIX(1) |
7412 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7413 }
7414 }
7415
7416 VkResult radv_CreateSampler(
7417 VkDevice _device,
7418 const VkSamplerCreateInfo* pCreateInfo,
7419 const VkAllocationCallbacks* pAllocator,
7420 VkSampler* pSampler)
7421 {
7422 RADV_FROM_HANDLE(radv_device, device, _device);
7423 struct radv_sampler *sampler;
7424
7425 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7426 vk_find_struct_const(pCreateInfo->pNext,
7427 SAMPLER_YCBCR_CONVERSION_INFO);
7428
7429 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7430
7431 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7432 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7433 if (!sampler)
7434 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7435
7436 vk_object_base_init(&device->vk, &sampler->base,
7437 VK_OBJECT_TYPE_SAMPLER);
7438
7439 radv_init_sampler(device, sampler, pCreateInfo);
7440
7441 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7442 *pSampler = radv_sampler_to_handle(sampler);
7443
7444 return VK_SUCCESS;
7445 }
7446
7447 void radv_DestroySampler(
7448 VkDevice _device,
7449 VkSampler _sampler,
7450 const VkAllocationCallbacks* pAllocator)
7451 {
7452 RADV_FROM_HANDLE(radv_device, device, _device);
7453 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7454
7455 if (!sampler)
7456 return;
7457
7458 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7459 radv_unregister_border_color(device, sampler->border_color_slot);
7460
7461 vk_object_base_finish(&sampler->base);
7462 vk_free2(&device->vk.alloc, pAllocator, sampler);
7463 }
7464
7465 /* vk_icd.h does not declare this function, so we declare it here to
7466 * suppress Wmissing-prototypes.
7467 */
7468 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7469 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7470
7471 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7472 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7473 {
7474 /* For the full details on loader interface versioning, see
7475 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7476 * What follows is a condensed summary, to help you navigate the large and
7477 * confusing official doc.
7478 *
7479 * - Loader interface v0 is incompatible with later versions. We don't
7480 * support it.
7481 *
7482 * - In loader interface v1:
7483 * - The first ICD entrypoint called by the loader is
7484 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7485 * entrypoint.
7486 * - The ICD must statically expose no other Vulkan symbol unless it is
7487 * linked with -Bsymbolic.
7488 * - Each dispatchable Vulkan handle created by the ICD must be
7489 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7490 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7491 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7492 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7493 * such loader-managed surfaces.
7494 *
7495 * - Loader interface v2 differs from v1 in:
7496 * - The first ICD entrypoint called by the loader is
7497 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7498 * statically expose this entrypoint.
7499 *
7500 * - Loader interface v3 differs from v2 in:
7501 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7502 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7503 * because the loader no longer does so.
7504 */
7505 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7506 return VK_SUCCESS;
7507 }
7508
7509 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7510 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7511 int *pFD)
7512 {
7513 RADV_FROM_HANDLE(radv_device, device, _device);
7514 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7515
7516 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7517
7518 /* At the moment, we support only the below handle types. */
7519 assert(pGetFdInfo->handleType ==
7520 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7521 pGetFdInfo->handleType ==
7522 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7523
7524 bool ret = radv_get_memory_fd(device, memory, pFD);
7525 if (ret == false)
7526 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7527 return VK_SUCCESS;
7528 }
7529
7530 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7531 enum radeon_bo_domain domains,
7532 enum radeon_bo_flag flags,
7533 enum radeon_bo_flag ignore_flags)
7534 {
7535 /* Don't count GTT/CPU as relevant:
7536 *
7537 * - We're not fully consistent between the two.
7538 * - Sometimes VRAM gets VRAM|GTT.
7539 */
7540 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7541 RADEON_DOMAIN_GDS |
7542 RADEON_DOMAIN_OA;
7543 uint32_t bits = 0;
7544 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7545 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7546 continue;
7547
7548 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7549 continue;
7550
7551 bits |= 1u << i;
7552 }
7553
7554 return bits;
7555 }
7556
7557 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7558 enum radeon_bo_domain domains,
7559 enum radeon_bo_flag flags)
7560 {
7561 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7562 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7563
7564 if (!bits) {
7565 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7566 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7567 }
7568
7569 return bits;
7570 }
7571 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7572 VkExternalMemoryHandleTypeFlagBits handleType,
7573 int fd,
7574 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7575 {
7576 RADV_FROM_HANDLE(radv_device, device, _device);
7577
7578 switch (handleType) {
7579 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7580 enum radeon_bo_domain domains;
7581 enum radeon_bo_flag flags;
7582 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7583 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7584
7585 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7586 return VK_SUCCESS;
7587 }
7588 default:
7589 /* The valid usage section for this function says:
7590 *
7591 * "handleType must not be one of the handle types defined as
7592 * opaque."
7593 *
7594 * So opaque handle types fall into the default "unsupported" case.
7595 */
7596 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7597 }
7598 }
7599
7600 static VkResult radv_import_opaque_fd(struct radv_device *device,
7601 int fd,
7602 uint32_t *syncobj)
7603 {
7604 uint32_t syncobj_handle = 0;
7605 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7606 if (ret != 0)
7607 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7608
7609 if (*syncobj)
7610 device->ws->destroy_syncobj(device->ws, *syncobj);
7611
7612 *syncobj = syncobj_handle;
7613 close(fd);
7614
7615 return VK_SUCCESS;
7616 }
7617
7618 static VkResult radv_import_sync_fd(struct radv_device *device,
7619 int fd,
7620 uint32_t *syncobj)
7621 {
7622 /* If we create a syncobj we do it locally so that if we have an error, we don't
7623 * leave a syncobj in an undetermined state in the fence. */
7624 uint32_t syncobj_handle = *syncobj;
7625 if (!syncobj_handle) {
7626 bool create_signaled = fd == -1 ? true : false;
7627
7628 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7629 &syncobj_handle);
7630 if (ret) {
7631 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7632 }
7633 } else {
7634 if (fd == -1)
7635 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7636 }
7637
7638 if (fd != -1) {
7639 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7640 if (ret)
7641 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7642 close(fd);
7643 }
7644
7645 *syncobj = syncobj_handle;
7646
7647 return VK_SUCCESS;
7648 }
7649
7650 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7651 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7652 {
7653 RADV_FROM_HANDLE(radv_device, device, _device);
7654 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7655 VkResult result;
7656 struct radv_semaphore_part *dst = NULL;
7657 bool timeline = sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7658
7659 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7660 assert(!timeline);
7661 dst = &sem->temporary;
7662 } else {
7663 dst = &sem->permanent;
7664 }
7665
7666 uint32_t syncobj = (dst->kind == RADV_SEMAPHORE_SYNCOBJ ||
7667 dst->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) ? dst->syncobj : 0;
7668
7669 switch(pImportSemaphoreFdInfo->handleType) {
7670 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7671 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7672 break;
7673 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7674 assert(!timeline);
7675 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7676 break;
7677 default:
7678 unreachable("Unhandled semaphore handle type");
7679 }
7680
7681 if (result == VK_SUCCESS) {
7682 dst->syncobj = syncobj;
7683 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7684 if (timeline) {
7685 dst->kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7686 dst->timeline_syncobj.max_point = 0;
7687 }
7688 }
7689
7690 return result;
7691 }
7692
7693 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7694 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7695 int *pFd)
7696 {
7697 RADV_FROM_HANDLE(radv_device, device, _device);
7698 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7699 int ret;
7700 uint32_t syncobj_handle;
7701
7702 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7703 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ ||
7704 sem->temporary.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7705 syncobj_handle = sem->temporary.syncobj;
7706 } else {
7707 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ ||
7708 sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7709 syncobj_handle = sem->permanent.syncobj;
7710 }
7711
7712 switch(pGetFdInfo->handleType) {
7713 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7714 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7715 if (ret)
7716 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7717 break;
7718 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7719 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7720 if (ret)
7721 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7722
7723 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7724 radv_destroy_semaphore_part(device, &sem->temporary);
7725 } else {
7726 device->ws->reset_syncobj(device->ws, syncobj_handle);
7727 }
7728 break;
7729 default:
7730 unreachable("Unhandled semaphore handle type");
7731 }
7732
7733 return VK_SUCCESS;
7734 }
7735
7736 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7737 VkPhysicalDevice physicalDevice,
7738 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7739 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7740 {
7741 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7742 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7743
7744 if (type == VK_SEMAPHORE_TYPE_TIMELINE && pdevice->rad_info.has_timeline_syncobj &&
7745 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7746 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7747 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7748 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7749 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7750 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7751 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7752 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7753 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7754
7755 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7756 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7757 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7758 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7759 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7760 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7761 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7762 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7763 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7764 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7765 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7766 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7767 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7768 } else {
7769 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7770 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7771 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7772 }
7773 }
7774
7775 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7776 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7777 {
7778 RADV_FROM_HANDLE(radv_device, device, _device);
7779 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7780 struct radv_fence_part *dst = NULL;
7781 VkResult result;
7782
7783 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7784 dst = &fence->temporary;
7785 } else {
7786 dst = &fence->permanent;
7787 }
7788
7789 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7790
7791 switch(pImportFenceFdInfo->handleType) {
7792 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7793 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7794 break;
7795 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7796 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7797 break;
7798 default:
7799 unreachable("Unhandled fence handle type");
7800 }
7801
7802 if (result == VK_SUCCESS) {
7803 dst->syncobj = syncobj;
7804 dst->kind = RADV_FENCE_SYNCOBJ;
7805 }
7806
7807 return result;
7808 }
7809
7810 VkResult radv_GetFenceFdKHR(VkDevice _device,
7811 const VkFenceGetFdInfoKHR *pGetFdInfo,
7812 int *pFd)
7813 {
7814 RADV_FROM_HANDLE(radv_device, device, _device);
7815 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7816 int ret;
7817
7818 struct radv_fence_part *part =
7819 fence->temporary.kind != RADV_FENCE_NONE ?
7820 &fence->temporary : &fence->permanent;
7821
7822 switch(pGetFdInfo->handleType) {
7823 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7824 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7825 if (ret)
7826 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7827 break;
7828 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7829 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7830 part->syncobj, pFd);
7831 if (ret)
7832 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7833
7834 if (part == &fence->temporary) {
7835 radv_destroy_fence_part(device, part);
7836 } else {
7837 device->ws->reset_syncobj(device->ws, part->syncobj);
7838 }
7839 break;
7840 default:
7841 unreachable("Unhandled fence handle type");
7842 }
7843
7844 return VK_SUCCESS;
7845 }
7846
7847 void radv_GetPhysicalDeviceExternalFenceProperties(
7848 VkPhysicalDevice physicalDevice,
7849 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7850 VkExternalFenceProperties *pExternalFenceProperties)
7851 {
7852 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7853
7854 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7855 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7856 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7857 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7858 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7859 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7860 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7861 } else {
7862 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7863 pExternalFenceProperties->compatibleHandleTypes = 0;
7864 pExternalFenceProperties->externalFenceFeatures = 0;
7865 }
7866 }
7867
7868 VkResult
7869 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7870 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7871 const VkAllocationCallbacks* pAllocator,
7872 VkDebugReportCallbackEXT* pCallback)
7873 {
7874 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7875 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7876 pCreateInfo, pAllocator, &instance->alloc,
7877 pCallback);
7878 }
7879
7880 void
7881 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7882 VkDebugReportCallbackEXT _callback,
7883 const VkAllocationCallbacks* pAllocator)
7884 {
7885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7886 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7887 _callback, pAllocator, &instance->alloc);
7888 }
7889
7890 void
7891 radv_DebugReportMessageEXT(VkInstance _instance,
7892 VkDebugReportFlagsEXT flags,
7893 VkDebugReportObjectTypeEXT objectType,
7894 uint64_t object,
7895 size_t location,
7896 int32_t messageCode,
7897 const char* pLayerPrefix,
7898 const char* pMessage)
7899 {
7900 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7901 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7902 object, location, messageCode, pLayerPrefix, pMessage);
7903 }
7904
7905 void
7906 radv_GetDeviceGroupPeerMemoryFeatures(
7907 VkDevice device,
7908 uint32_t heapIndex,
7909 uint32_t localDeviceIndex,
7910 uint32_t remoteDeviceIndex,
7911 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7912 {
7913 assert(localDeviceIndex == remoteDeviceIndex);
7914
7915 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7916 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7917 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7918 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7919 }
7920
7921 static const VkTimeDomainEXT radv_time_domains[] = {
7922 VK_TIME_DOMAIN_DEVICE_EXT,
7923 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7924 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7925 };
7926
7927 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7928 VkPhysicalDevice physicalDevice,
7929 uint32_t *pTimeDomainCount,
7930 VkTimeDomainEXT *pTimeDomains)
7931 {
7932 int d;
7933 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7934
7935 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7936 vk_outarray_append(&out, i) {
7937 *i = radv_time_domains[d];
7938 }
7939 }
7940
7941 return vk_outarray_status(&out);
7942 }
7943
7944 static uint64_t
7945 radv_clock_gettime(clockid_t clock_id)
7946 {
7947 struct timespec current;
7948 int ret;
7949
7950 ret = clock_gettime(clock_id, &current);
7951 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7952 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7953 if (ret < 0)
7954 return 0;
7955
7956 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7957 }
7958
7959 VkResult radv_GetCalibratedTimestampsEXT(
7960 VkDevice _device,
7961 uint32_t timestampCount,
7962 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7963 uint64_t *pTimestamps,
7964 uint64_t *pMaxDeviation)
7965 {
7966 RADV_FROM_HANDLE(radv_device, device, _device);
7967 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7968 int d;
7969 uint64_t begin, end;
7970 uint64_t max_clock_period = 0;
7971
7972 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7973
7974 for (d = 0; d < timestampCount; d++) {
7975 switch (pTimestampInfos[d].timeDomain) {
7976 case VK_TIME_DOMAIN_DEVICE_EXT:
7977 pTimestamps[d] = device->ws->query_value(device->ws,
7978 RADEON_TIMESTAMP);
7979 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7980 max_clock_period = MAX2(max_clock_period, device_period);
7981 break;
7982 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7983 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7984 max_clock_period = MAX2(max_clock_period, 1);
7985 break;
7986
7987 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7988 pTimestamps[d] = begin;
7989 break;
7990 default:
7991 pTimestamps[d] = 0;
7992 break;
7993 }
7994 }
7995
7996 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7997
7998 /*
7999 * The maximum deviation is the sum of the interval over which we
8000 * perform the sampling and the maximum period of any sampled
8001 * clock. That's because the maximum skew between any two sampled
8002 * clock edges is when the sampled clock with the largest period is
8003 * sampled at the end of that period but right at the beginning of the
8004 * sampling interval and some other clock is sampled right at the
8005 * begining of its sampling period and right at the end of the
8006 * sampling interval. Let's assume the GPU has the longest clock
8007 * period and that the application is sampling GPU and monotonic:
8008 *
8009 * s e
8010 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
8011 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8012 *
8013 * g
8014 * 0 1 2 3
8015 * GPU -----_____-----_____-----_____-----_____
8016 *
8017 * m
8018 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
8019 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
8020 *
8021 * Interval <----------------->
8022 * Deviation <-------------------------->
8023 *
8024 * s = read(raw) 2
8025 * g = read(GPU) 1
8026 * m = read(monotonic) 2
8027 * e = read(raw) b
8028 *
8029 * We round the sample interval up by one tick to cover sampling error
8030 * in the interval clock
8031 */
8032
8033 uint64_t sample_interval = end - begin + 1;
8034
8035 *pMaxDeviation = sample_interval + max_clock_period;
8036
8037 return VK_SUCCESS;
8038 }
8039
8040 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
8041 VkPhysicalDevice physicalDevice,
8042 VkSampleCountFlagBits samples,
8043 VkMultisamplePropertiesEXT* pMultisampleProperties)
8044 {
8045 if (samples & (VK_SAMPLE_COUNT_2_BIT |
8046 VK_SAMPLE_COUNT_4_BIT |
8047 VK_SAMPLE_COUNT_8_BIT)) {
8048 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
8049 } else {
8050 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
8051 }
8052 }
8053
8054 VkResult radv_CreatePrivateDataSlotEXT(
8055 VkDevice _device,
8056 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
8057 const VkAllocationCallbacks* pAllocator,
8058 VkPrivateDataSlotEXT* pPrivateDataSlot)
8059 {
8060 RADV_FROM_HANDLE(radv_device, device, _device);
8061 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
8062 pPrivateDataSlot);
8063 }
8064
8065 void radv_DestroyPrivateDataSlotEXT(
8066 VkDevice _device,
8067 VkPrivateDataSlotEXT privateDataSlot,
8068 const VkAllocationCallbacks* pAllocator)
8069 {
8070 RADV_FROM_HANDLE(radv_device, device, _device);
8071 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
8072 }
8073
8074 VkResult radv_SetPrivateDataEXT(
8075 VkDevice _device,
8076 VkObjectType objectType,
8077 uint64_t objectHandle,
8078 VkPrivateDataSlotEXT privateDataSlot,
8079 uint64_t data)
8080 {
8081 RADV_FROM_HANDLE(radv_device, device, _device);
8082 return vk_object_base_set_private_data(&device->vk, objectType,
8083 objectHandle, privateDataSlot,
8084 data);
8085 }
8086
8087 void radv_GetPrivateDataEXT(
8088 VkDevice _device,
8089 VkObjectType objectType,
8090 uint64_t objectHandle,
8091 VkPrivateDataSlotEXT privateDataSlot,
8092 uint64_t* pData)
8093 {
8094 RADV_FROM_HANDLE(radv_device, device, _device);
8095 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
8096 privateDataSlot, pData);
8097 }