2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 default: chip_string
= "AMD RADV unknown"; break;
119 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
123 radv_get_visible_vram_size(struct radv_physical_device
*device
)
125 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
129 radv_get_vram_size(struct radv_physical_device
*device
)
131 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
135 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
138 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
139 uint64_t vram_size
= radv_get_vram_size(device
);
140 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
141 device
->memory_properties
.memoryHeapCount
= 0;
143 vram_index
= device
->memory_properties
.memoryHeapCount
++;
144 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
146 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
149 if (visible_vram_size
) {
150 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
151 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
152 .size
= visible_vram_size
,
153 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
156 if (device
->rad_info
.gart_size
> 0) {
157 gart_index
= device
->memory_properties
.memoryHeapCount
++;
158 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
159 .size
= device
->rad_info
.gart_size
,
160 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
165 unsigned type_count
= 0;
166 if (vram_index
>= 0) {
167 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
168 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
169 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
170 .heapIndex
= vram_index
,
173 if (gart_index
>= 0) {
174 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
175 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
176 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
178 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
179 .heapIndex
= gart_index
,
182 if (visible_vram_index
>= 0) {
183 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
184 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
185 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
188 .heapIndex
= visible_vram_index
,
191 if (gart_index
>= 0) {
192 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
193 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
194 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
197 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
198 .heapIndex
= gart_index
,
201 device
->memory_properties
.memoryTypeCount
= type_count
;
205 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
207 const char *family
= getenv("RADV_FORCE_FAMILY");
213 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
214 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
215 /* Override family and chip_class. */
216 device
->rad_info
.family
= i
;
218 if (i
>= CHIP_VEGA10
)
219 device
->rad_info
.chip_class
= GFX9
;
220 else if (i
>= CHIP_TONGA
)
221 device
->rad_info
.chip_class
= GFX8
;
222 else if (i
>= CHIP_BONAIRE
)
223 device
->rad_info
.chip_class
= GFX7
;
225 device
->rad_info
.chip_class
= GFX6
;
231 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
236 radv_physical_device_init(struct radv_physical_device
*device
,
237 struct radv_instance
*instance
,
238 drmDevicePtr drm_device
)
240 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
242 drmVersionPtr version
;
246 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
248 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
249 radv_logi("Could not open device '%s'", path
);
251 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
254 version
= drmGetVersion(fd
);
258 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
259 radv_logi("Could not get the kernel driver version for device '%s'", path
);
261 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
262 "failed to get version %s: %m", path
);
265 if (strcmp(version
->name
, "amdgpu")) {
266 drmFreeVersion(version
);
269 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
272 return VK_ERROR_INCOMPATIBLE_DRIVER
;
274 drmFreeVersion(version
);
276 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
277 radv_logi("Found compatible device '%s'.", path
);
279 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
280 device
->instance
= instance
;
282 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
283 instance
->perftest_flags
);
285 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
289 if (instance
->enabled_extensions
.KHR_display
) {
290 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
291 if (master_fd
>= 0) {
292 uint32_t accel_working
= 0;
293 struct drm_amdgpu_info request
= {
294 .return_pointer
= (uintptr_t)&accel_working
,
295 .return_size
= sizeof(accel_working
),
296 .query
= AMDGPU_INFO_ACCEL_WORKING
299 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
306 device
->master_fd
= master_fd
;
307 device
->local_fd
= fd
;
308 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
310 radv_handle_env_var_force_family(device
);
312 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
314 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
315 device
->ws
->destroy(device
->ws
);
316 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
317 "cannot generate UUID");
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags
=
323 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
324 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
329 char buf
[VK_UUID_SIZE
* 2 + 1];
330 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
331 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
333 if (device
->rad_info
.chip_class
< GFX8
||
334 device
->rad_info
.chip_class
> GFX9
)
335 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337 radv_get_driver_uuid(&device
->driver_uuid
);
338 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
340 if (device
->rad_info
.family
== CHIP_STONEY
||
341 device
->rad_info
.chip_class
>= GFX9
) {
342 device
->has_rbplus
= true;
343 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
344 device
->rad_info
.family
== CHIP_VEGA12
||
345 device
->rad_info
.family
== CHIP_RAVEN
||
346 device
->rad_info
.family
== CHIP_RAVEN2
;
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
354 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
358 device
->rad_info
.family
== CHIP_RAVEN
;
360 /* Out-of-order primitive rasterization. */
361 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
362 device
->rad_info
.max_se
>= 2;
363 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
364 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
366 device
->dcc_msaa_allowed
=
367 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
371 (device
->rad_info
.chip_class
>= GFX8
&&
372 device
->rad_info
.me_fw_feature
>= 41);
374 device
->use_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
376 radv_physical_device_init_mem_types(device
);
377 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
379 device
->bus_info
= *drm_device
->businfo
.pci
;
381 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
382 ac_print_gpu_info(&device
->rad_info
);
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
388 result
= radv_init_wsi(device
);
389 if (result
!= VK_SUCCESS
) {
390 device
->ws
->destroy(device
->ws
);
391 vk_error(instance
, result
);
405 radv_physical_device_finish(struct radv_physical_device
*device
)
407 radv_finish_wsi(device
);
408 device
->ws
->destroy(device
->ws
);
409 disk_cache_destroy(device
->disk_cache
);
410 close(device
->local_fd
);
411 if (device
->master_fd
!= -1)
412 close(device
->master_fd
);
416 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
417 VkSystemAllocationScope allocationScope
)
423 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
424 size_t align
, VkSystemAllocationScope allocationScope
)
426 return realloc(pOriginal
, size
);
430 default_free_func(void *pUserData
, void *pMemory
)
435 static const VkAllocationCallbacks default_alloc
= {
437 .pfnAllocation
= default_alloc_func
,
438 .pfnReallocation
= default_realloc_func
,
439 .pfnFree
= default_free_func
,
442 static const struct debug_control radv_debug_options
[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
444 {"nodcc", RADV_DEBUG_NO_DCC
},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
446 {"nocache", RADV_DEBUG_NO_CACHE
},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
448 {"nohiz", RADV_DEBUG_NO_HIZ
},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
451 {"allbos", RADV_DEBUG_ALL_BOS
},
452 {"noibs", RADV_DEBUG_NO_IBS
},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
457 {"nosisched", RADV_DEBUG_NO_SISCHED
},
458 {"preoptir", RADV_DEBUG_PREOPTIR
},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
461 {"info", RADV_DEBUG_INFO
},
462 {"errors", RADV_DEBUG_ERRORS
},
463 {"startup", RADV_DEBUG_STARTUP
},
464 {"checkir", RADV_DEBUG_CHECKIR
},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
466 {"nobinning", RADV_DEBUG_NOBINNING
},
467 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
472 radv_get_debug_option_name(int id
)
474 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
475 return radv_debug_options
[id
].string
;
478 static const struct debug_control radv_perftest_options
[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
480 {"sisched", RADV_PERFTEST_SISCHED
},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
483 {"bolist", RADV_PERFTEST_BO_LIST
},
484 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
489 radv_get_perftest_option_name(int id
)
491 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
492 return radv_perftest_options
[id
].string
;
496 radv_handle_per_app_options(struct radv_instance
*instance
,
497 const VkApplicationInfo
*info
)
499 const char *name
= info
? info
->pApplicationName
: NULL
;
504 if (!strcmp(name
, "Talos - Linux - 32bit") ||
505 !strcmp(name
, "Talos - Linux - 64bit")) {
506 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
507 /* Force enable LLVM sisched for Talos because it looks
508 * safe and it gives few more FPS.
510 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
512 } else if (!strcmp(name
, "DOOM_VFR")) {
513 /* Work around a Doom VFR game bug */
514 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
515 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
516 /* Workaround for a WaW hazard when LLVM moves/merges
517 * load/store memory operations.
518 * See https://reviews.llvm.org/D61313
520 if (HAVE_LLVM
< 0x900)
521 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
525 static int radv_get_instance_extension_index(const char *name
)
527 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
528 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
534 static const char radv_dri_options_xml
[] =
536 DRI_CONF_SECTION_QUALITY
537 DRI_CONF_ADAPTIVE_SYNC("true")
541 static void radv_init_dri_options(struct radv_instance
*instance
)
543 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
544 driParseConfigFiles(&instance
->dri_options
,
545 &instance
->available_dri_options
,
549 VkResult
radv_CreateInstance(
550 const VkInstanceCreateInfo
* pCreateInfo
,
551 const VkAllocationCallbacks
* pAllocator
,
552 VkInstance
* pInstance
)
554 struct radv_instance
*instance
;
557 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
559 uint32_t client_version
;
560 if (pCreateInfo
->pApplicationInfo
&&
561 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
562 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
564 client_version
= VK_API_VERSION_1_0
;
567 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
568 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
570 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
572 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
575 instance
->alloc
= *pAllocator
;
577 instance
->alloc
= default_alloc
;
579 instance
->apiVersion
= client_version
;
580 instance
->physicalDeviceCount
= -1;
582 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
585 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
586 radv_perftest_options
);
589 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
590 radv_logi("Created an instance");
592 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
593 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
594 int index
= radv_get_instance_extension_index(ext_name
);
596 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
597 vk_free2(&default_alloc
, pAllocator
, instance
);
598 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
601 instance
->enabled_extensions
.extensions
[index
] = true;
604 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
605 if (result
!= VK_SUCCESS
) {
606 vk_free2(&default_alloc
, pAllocator
, instance
);
607 return vk_error(instance
, result
);
611 glsl_type_singleton_init_or_ref();
613 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
615 radv_init_dri_options(instance
);
616 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
618 *pInstance
= radv_instance_to_handle(instance
);
623 void radv_DestroyInstance(
624 VkInstance _instance
,
625 const VkAllocationCallbacks
* pAllocator
)
627 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
632 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
633 radv_physical_device_finish(instance
->physicalDevices
+ i
);
636 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
638 glsl_type_singleton_decref();
641 driDestroyOptionCache(&instance
->dri_options
);
642 driDestroyOptionInfo(&instance
->available_dri_options
);
644 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
646 vk_free(&instance
->alloc
, instance
);
650 radv_enumerate_devices(struct radv_instance
*instance
)
652 /* TODO: Check for more devices ? */
653 drmDevicePtr devices
[8];
654 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
657 instance
->physicalDeviceCount
= 0;
659 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
661 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
662 radv_logi("Found %d drm nodes", max_devices
);
665 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
667 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
668 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
669 devices
[i
]->bustype
== DRM_BUS_PCI
&&
670 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
672 result
= radv_physical_device_init(instance
->physicalDevices
+
673 instance
->physicalDeviceCount
,
676 if (result
== VK_SUCCESS
)
677 ++instance
->physicalDeviceCount
;
678 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
682 drmFreeDevices(devices
, max_devices
);
687 VkResult
radv_EnumeratePhysicalDevices(
688 VkInstance _instance
,
689 uint32_t* pPhysicalDeviceCount
,
690 VkPhysicalDevice
* pPhysicalDevices
)
692 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
695 if (instance
->physicalDeviceCount
< 0) {
696 result
= radv_enumerate_devices(instance
);
697 if (result
!= VK_SUCCESS
&&
698 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
702 if (!pPhysicalDevices
) {
703 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
705 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
706 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
707 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
710 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
714 VkResult
radv_EnumeratePhysicalDeviceGroups(
715 VkInstance _instance
,
716 uint32_t* pPhysicalDeviceGroupCount
,
717 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
719 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
722 if (instance
->physicalDeviceCount
< 0) {
723 result
= radv_enumerate_devices(instance
);
724 if (result
!= VK_SUCCESS
&&
725 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
729 if (!pPhysicalDeviceGroupProperties
) {
730 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
732 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
733 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
734 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
735 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
736 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
739 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
743 void radv_GetPhysicalDeviceFeatures(
744 VkPhysicalDevice physicalDevice
,
745 VkPhysicalDeviceFeatures
* pFeatures
)
747 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
748 memset(pFeatures
, 0, sizeof(*pFeatures
));
750 *pFeatures
= (VkPhysicalDeviceFeatures
) {
751 .robustBufferAccess
= true,
752 .fullDrawIndexUint32
= true,
753 .imageCubeArray
= true,
754 .independentBlend
= true,
755 .geometryShader
= true,
756 .tessellationShader
= true,
757 .sampleRateShading
= true,
758 .dualSrcBlend
= true,
760 .multiDrawIndirect
= true,
761 .drawIndirectFirstInstance
= true,
763 .depthBiasClamp
= true,
764 .fillModeNonSolid
= true,
769 .multiViewport
= true,
770 .samplerAnisotropy
= true,
771 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
772 .textureCompressionASTC_LDR
= false,
773 .textureCompressionBC
= true,
774 .occlusionQueryPrecise
= true,
775 .pipelineStatisticsQuery
= true,
776 .vertexPipelineStoresAndAtomics
= true,
777 .fragmentStoresAndAtomics
= true,
778 .shaderTessellationAndGeometryPointSize
= true,
779 .shaderImageGatherExtended
= true,
780 .shaderStorageImageExtendedFormats
= true,
781 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
782 .shaderUniformBufferArrayDynamicIndexing
= true,
783 .shaderSampledImageArrayDynamicIndexing
= true,
784 .shaderStorageBufferArrayDynamicIndexing
= true,
785 .shaderStorageImageArrayDynamicIndexing
= true,
786 .shaderStorageImageReadWithoutFormat
= true,
787 .shaderStorageImageWriteWithoutFormat
= true,
788 .shaderClipDistance
= true,
789 .shaderCullDistance
= true,
790 .shaderFloat64
= true,
792 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
793 .sparseBinding
= true,
794 .variableMultisampleRate
= true,
795 .inheritedQueries
= true,
799 void radv_GetPhysicalDeviceFeatures2(
800 VkPhysicalDevice physicalDevice
,
801 VkPhysicalDeviceFeatures2
*pFeatures
)
803 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
804 vk_foreach_struct(ext
, pFeatures
->pNext
) {
805 switch (ext
->sType
) {
806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
807 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
808 features
->variablePointersStorageBuffer
= true;
809 features
->variablePointers
= true;
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
813 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
814 features
->multiview
= true;
815 features
->multiviewGeometryShader
= true;
816 features
->multiviewTessellationShader
= true;
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
820 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
821 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
822 features
->shaderDrawParameters
= true;
825 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
826 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
827 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
828 features
->protectedMemory
= false;
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
832 VkPhysicalDevice16BitStorageFeatures
*features
=
833 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
834 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
835 features
->storageBuffer16BitAccess
= enabled
;
836 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
837 features
->storagePushConstant16
= enabled
;
838 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
842 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
843 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
844 features
->samplerYcbcrConversion
= true;
847 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
848 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
849 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
850 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
851 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
852 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
853 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
854 features
->shaderSampledImageArrayNonUniformIndexing
= true;
855 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
856 features
->shaderStorageImageArrayNonUniformIndexing
= true;
857 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
858 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
859 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
860 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
861 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
862 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
863 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
864 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
865 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
866 features
->descriptorBindingUpdateUnusedWhilePending
= true;
867 features
->descriptorBindingPartiallyBound
= true;
868 features
->descriptorBindingVariableDescriptorCount
= true;
869 features
->runtimeDescriptorArray
= true;
872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
873 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
874 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
875 features
->conditionalRendering
= true;
876 features
->inheritedConditionalRendering
= false;
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
880 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
881 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
882 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
883 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
887 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
888 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
889 features
->transformFeedback
= true;
890 features
->geometryStreams
= true;
893 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
894 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
895 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
896 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
900 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
901 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
902 features
->memoryPriority
= VK_TRUE
;
905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
906 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
907 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
908 features
->bufferDeviceAddress
= true;
909 features
->bufferDeviceAddressCaptureReplay
= false;
910 features
->bufferDeviceAddressMultiDevice
= false;
913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
914 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
915 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
916 features
->depthClipEnable
= true;
919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
920 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
921 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
922 features
->hostQueryReset
= true;
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
926 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
927 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
928 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
929 features
->storageBuffer8BitAccess
= enabled
;
930 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
931 features
->storagePushConstant8
= enabled
;
934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
935 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
936 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
937 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
938 features
->shaderInt8
= true;
941 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
942 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
943 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
944 /* TODO: Enable this once the driver supports 64-bit
945 * compare&swap atomic operations.
947 features
->shaderBufferInt64Atomics
= false;
948 features
->shaderSharedInt64Atomics
= false;
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
952 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
953 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
955 features
->inlineUniformBlock
= true;
956 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
960 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
961 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
962 features
->computeDerivativeGroupQuads
= false;
963 features
->computeDerivativeGroupLinear
= true;
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
967 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
968 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
969 features
->ycbcrImageArrays
= true;
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
973 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
974 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
975 features
->uniformBufferStandardLayout
= true;
982 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
985 void radv_GetPhysicalDeviceProperties(
986 VkPhysicalDevice physicalDevice
,
987 VkPhysicalDeviceProperties
* pProperties
)
989 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
990 VkSampleCountFlags sample_counts
= 0xf;
992 /* make sure that the entire descriptor set is addressable with a signed
993 * 32-bit int. So the sum of all limits scaled by descriptor size has to
994 * be at most 2 GiB. the combined image & samples object count as one of
995 * both. This limit is for the pipeline layout, not for the set layout, but
996 * there is no set limit, so we just set a pipeline limit. I don't think
997 * any app is going to hit this soon. */
998 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
999 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1000 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1001 32 /* sampler, largest when combined with image */ +
1002 64 /* sampled image */ +
1003 64 /* storage image */);
1005 VkPhysicalDeviceLimits limits
= {
1006 .maxImageDimension1D
= (1 << 14),
1007 .maxImageDimension2D
= (1 << 14),
1008 .maxImageDimension3D
= (1 << 11),
1009 .maxImageDimensionCube
= (1 << 14),
1010 .maxImageArrayLayers
= (1 << 11),
1011 .maxTexelBufferElements
= 128 * 1024 * 1024,
1012 .maxUniformBufferRange
= UINT32_MAX
,
1013 .maxStorageBufferRange
= UINT32_MAX
,
1014 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1015 .maxMemoryAllocationCount
= UINT32_MAX
,
1016 .maxSamplerAllocationCount
= 64 * 1024,
1017 .bufferImageGranularity
= 64, /* A cache line */
1018 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1019 .maxBoundDescriptorSets
= MAX_SETS
,
1020 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1021 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1022 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1023 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1024 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1025 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1026 .maxPerStageResources
= max_descriptor_set_size
,
1027 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1028 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1029 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1030 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1031 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1032 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1033 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1034 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1035 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1036 .maxVertexInputBindings
= MAX_VBS
,
1037 .maxVertexInputAttributeOffset
= 2047,
1038 .maxVertexInputBindingStride
= 2048,
1039 .maxVertexOutputComponents
= 128,
1040 .maxTessellationGenerationLevel
= 64,
1041 .maxTessellationPatchSize
= 32,
1042 .maxTessellationControlPerVertexInputComponents
= 128,
1043 .maxTessellationControlPerVertexOutputComponents
= 128,
1044 .maxTessellationControlPerPatchOutputComponents
= 120,
1045 .maxTessellationControlTotalOutputComponents
= 4096,
1046 .maxTessellationEvaluationInputComponents
= 128,
1047 .maxTessellationEvaluationOutputComponents
= 128,
1048 .maxGeometryShaderInvocations
= 127,
1049 .maxGeometryInputComponents
= 64,
1050 .maxGeometryOutputComponents
= 128,
1051 .maxGeometryOutputVertices
= 256,
1052 .maxGeometryTotalOutputComponents
= 1024,
1053 .maxFragmentInputComponents
= 128,
1054 .maxFragmentOutputAttachments
= 8,
1055 .maxFragmentDualSrcAttachments
= 1,
1056 .maxFragmentCombinedOutputResources
= 8,
1057 .maxComputeSharedMemorySize
= 32768,
1058 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1059 .maxComputeWorkGroupInvocations
= 2048,
1060 .maxComputeWorkGroupSize
= {
1065 .subPixelPrecisionBits
= 8,
1066 .subTexelPrecisionBits
= 8,
1067 .mipmapPrecisionBits
= 8,
1068 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1069 .maxDrawIndirectCount
= UINT32_MAX
,
1070 .maxSamplerLodBias
= 16,
1071 .maxSamplerAnisotropy
= 16,
1072 .maxViewports
= MAX_VIEWPORTS
,
1073 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1074 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1075 .viewportSubPixelBits
= 8,
1076 .minMemoryMapAlignment
= 4096, /* A page */
1077 .minTexelBufferOffsetAlignment
= 1,
1078 .minUniformBufferOffsetAlignment
= 4,
1079 .minStorageBufferOffsetAlignment
= 4,
1080 .minTexelOffset
= -32,
1081 .maxTexelOffset
= 31,
1082 .minTexelGatherOffset
= -32,
1083 .maxTexelGatherOffset
= 31,
1084 .minInterpolationOffset
= -2,
1085 .maxInterpolationOffset
= 2,
1086 .subPixelInterpolationOffsetBits
= 8,
1087 .maxFramebufferWidth
= (1 << 14),
1088 .maxFramebufferHeight
= (1 << 14),
1089 .maxFramebufferLayers
= (1 << 10),
1090 .framebufferColorSampleCounts
= sample_counts
,
1091 .framebufferDepthSampleCounts
= sample_counts
,
1092 .framebufferStencilSampleCounts
= sample_counts
,
1093 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1094 .maxColorAttachments
= MAX_RTS
,
1095 .sampledImageColorSampleCounts
= sample_counts
,
1096 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1097 .sampledImageDepthSampleCounts
= sample_counts
,
1098 .sampledImageStencilSampleCounts
= sample_counts
,
1099 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1100 .maxSampleMaskWords
= 1,
1101 .timestampComputeAndGraphics
= true,
1102 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1103 .maxClipDistances
= 8,
1104 .maxCullDistances
= 8,
1105 .maxCombinedClipAndCullDistances
= 8,
1106 .discreteQueuePriorities
= 2,
1107 .pointSizeRange
= { 0.0, 8192.0 },
1108 .lineWidthRange
= { 0.0, 7.9921875 },
1109 .pointSizeGranularity
= (1.0 / 8.0),
1110 .lineWidthGranularity
= (1.0 / 128.0),
1111 .strictLines
= false, /* FINISHME */
1112 .standardSampleLocations
= true,
1113 .optimalBufferCopyOffsetAlignment
= 128,
1114 .optimalBufferCopyRowPitchAlignment
= 128,
1115 .nonCoherentAtomSize
= 64,
1118 *pProperties
= (VkPhysicalDeviceProperties
) {
1119 .apiVersion
= radv_physical_device_api_version(pdevice
),
1120 .driverVersion
= vk_get_driver_version(),
1121 .vendorID
= ATI_VENDOR_ID
,
1122 .deviceID
= pdevice
->rad_info
.pci_id
,
1123 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1125 .sparseProperties
= {0},
1128 strcpy(pProperties
->deviceName
, pdevice
->name
);
1129 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1132 void radv_GetPhysicalDeviceProperties2(
1133 VkPhysicalDevice physicalDevice
,
1134 VkPhysicalDeviceProperties2
*pProperties
)
1136 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1137 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1139 vk_foreach_struct(ext
, pProperties
->pNext
) {
1140 switch (ext
->sType
) {
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1142 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1143 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1144 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1147 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1148 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1149 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1150 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1151 properties
->deviceLUIDValid
= false;
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1155 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1156 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1157 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1161 VkPhysicalDevicePointClippingProperties
*properties
=
1162 (VkPhysicalDevicePointClippingProperties
*)ext
;
1163 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1167 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1168 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1169 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1173 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1174 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1175 properties
->minImportedHostPointerAlignment
= 4096;
1178 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1179 VkPhysicalDeviceSubgroupProperties
*properties
=
1180 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1181 properties
->subgroupSize
= 64;
1182 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1183 properties
->supportedOperations
=
1184 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1185 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1186 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1187 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1188 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1189 properties
->supportedOperations
|=
1190 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1191 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1192 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1194 properties
->quadOperationsInAllStages
= true;
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1198 VkPhysicalDeviceMaintenance3Properties
*properties
=
1199 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1200 /* Make sure everything is addressable by a signed 32-bit int, and
1201 * our largest descriptors are 96 bytes. */
1202 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1203 /* Our buffer size fields allow only this much */
1204 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1208 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1209 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1210 /* GFX6-8 only support single channel min/max filter. */
1211 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1212 properties
->filterMinmaxSingleComponentFormats
= true;
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1216 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1217 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1219 /* Shader engines. */
1220 properties
->shaderEngineCount
=
1221 pdevice
->rad_info
.max_se
;
1222 properties
->shaderArraysPerEngineCount
=
1223 pdevice
->rad_info
.max_sh_per_se
;
1224 properties
->computeUnitsPerShaderArray
=
1225 pdevice
->rad_info
.num_good_cu_per_sh
;
1226 properties
->simdPerComputeUnit
= 4;
1227 properties
->wavefrontsPerSimd
=
1228 pdevice
->rad_info
.family
== CHIP_TONGA
||
1229 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1230 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1231 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1232 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1233 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1234 properties
->wavefrontSize
= 64;
1237 properties
->sgprsPerSimd
=
1238 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1239 properties
->minSgprAllocation
=
1240 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1241 properties
->maxSgprAllocation
=
1242 pdevice
->rad_info
.family
== CHIP_TONGA
||
1243 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1244 properties
->sgprAllocationGranularity
=
1245 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1248 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1249 properties
->minVgprAllocation
= 4;
1250 properties
->maxVgprAllocation
= 256;
1251 properties
->vgprAllocationGranularity
= 4;
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1255 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1256 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1257 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1260 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1261 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1262 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1263 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1264 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1265 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1266 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1267 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1268 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1269 properties
->robustBufferAccessUpdateAfterBind
= false;
1270 properties
->quadDivergentImplicitLod
= false;
1272 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1273 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1274 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1275 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1276 32 /* sampler, largest when combined with image */ +
1277 64 /* sampled image */ +
1278 64 /* storage image */);
1279 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1280 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1281 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1282 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1283 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1284 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1285 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1286 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1287 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1288 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1289 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1290 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1291 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1292 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1293 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1297 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1298 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1299 properties
->protectedNoFault
= false;
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1303 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1304 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1305 properties
->primitiveOverestimationSize
= 0;
1306 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1307 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1308 properties
->primitiveUnderestimation
= VK_FALSE
;
1309 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1310 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1311 properties
->degenerateLinesRasterized
= VK_FALSE
;
1312 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1313 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1316 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1317 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1318 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1319 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1320 properties
->pciBus
= pdevice
->bus_info
.bus
;
1321 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1322 properties
->pciFunction
= pdevice
->bus_info
.func
;
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1326 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1327 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1329 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1330 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1331 strcpy(driver_props
->driverName
, "radv");
1333 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1334 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1335 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1336 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1338 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1346 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1347 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1348 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1349 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1350 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1351 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1352 properties
->maxTransformFeedbackStreamDataSize
= 512;
1353 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1354 properties
->maxTransformFeedbackBufferDataStride
= 512;
1355 properties
->transformFeedbackQueries
= true;
1356 properties
->transformFeedbackStreamsLinesTriangles
= true;
1357 properties
->transformFeedbackRasterizationStreamSelect
= false;
1358 properties
->transformFeedbackDraw
= true;
1361 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1362 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1363 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1365 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1366 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1367 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1368 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1369 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1372 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1373 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1374 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1375 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1376 VK_SAMPLE_COUNT_4_BIT
|
1377 VK_SAMPLE_COUNT_8_BIT
;
1378 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1379 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1380 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1381 properties
->sampleLocationSubPixelBits
= 4;
1382 properties
->variableSampleLocations
= VK_FALSE
;
1391 static void radv_get_physical_device_queue_family_properties(
1392 struct radv_physical_device
* pdevice
,
1394 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1396 int num_queue_families
= 1;
1398 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1399 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1400 num_queue_families
++;
1402 if (pQueueFamilyProperties
== NULL
) {
1403 *pCount
= num_queue_families
;
1412 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1413 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1414 VK_QUEUE_COMPUTE_BIT
|
1415 VK_QUEUE_TRANSFER_BIT
|
1416 VK_QUEUE_SPARSE_BINDING_BIT
,
1418 .timestampValidBits
= 64,
1419 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1424 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1425 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1426 if (*pCount
> idx
) {
1427 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1428 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1429 VK_QUEUE_TRANSFER_BIT
|
1430 VK_QUEUE_SPARSE_BINDING_BIT
,
1431 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1432 .timestampValidBits
= 64,
1433 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1441 void radv_GetPhysicalDeviceQueueFamilyProperties(
1442 VkPhysicalDevice physicalDevice
,
1444 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1446 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1447 if (!pQueueFamilyProperties
) {
1448 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1451 VkQueueFamilyProperties
*properties
[] = {
1452 pQueueFamilyProperties
+ 0,
1453 pQueueFamilyProperties
+ 1,
1454 pQueueFamilyProperties
+ 2,
1456 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1457 assert(*pCount
<= 3);
1460 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1461 VkPhysicalDevice physicalDevice
,
1463 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1465 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1466 if (!pQueueFamilyProperties
) {
1467 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1470 VkQueueFamilyProperties
*properties
[] = {
1471 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1472 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1473 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1475 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1476 assert(*pCount
<= 3);
1479 void radv_GetPhysicalDeviceMemoryProperties(
1480 VkPhysicalDevice physicalDevice
,
1481 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1483 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1485 *pMemoryProperties
= physical_device
->memory_properties
;
1489 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1490 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1492 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1493 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1494 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1495 uint64_t vram_size
= radv_get_vram_size(device
);
1496 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1497 uint64_t heap_budget
, heap_usage
;
1499 /* For all memory heaps, the computation of budget is as follow:
1500 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1502 * The Vulkan spec 1.1.97 says that the budget should include any
1503 * currently allocated device memory.
1505 * Note that the application heap usages are not really accurate (eg.
1506 * in presence of shared buffers).
1508 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1509 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1511 switch (device
->mem_type_indices
[i
]) {
1512 case RADV_MEM_TYPE_VRAM
:
1513 heap_usage
= device
->ws
->query_value(device
->ws
,
1514 RADEON_ALLOCATED_VRAM
);
1516 heap_budget
= vram_size
-
1517 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1520 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1521 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1523 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1524 heap_usage
= device
->ws
->query_value(device
->ws
,
1525 RADEON_ALLOCATED_VRAM_VIS
);
1527 heap_budget
= visible_vram_size
-
1528 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1531 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1532 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1534 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1535 heap_usage
= device
->ws
->query_value(device
->ws
,
1536 RADEON_ALLOCATED_GTT
);
1538 heap_budget
= gtt_size
-
1539 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1542 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1543 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1550 /* The heapBudget and heapUsage values must be zero for array elements
1551 * greater than or equal to
1552 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1554 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1555 memoryBudget
->heapBudget
[i
] = 0;
1556 memoryBudget
->heapUsage
[i
] = 0;
1560 void radv_GetPhysicalDeviceMemoryProperties2(
1561 VkPhysicalDevice physicalDevice
,
1562 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1564 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1565 &pMemoryProperties
->memoryProperties
);
1567 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1568 vk_find_struct(pMemoryProperties
->pNext
,
1569 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1571 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1574 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1576 VkExternalMemoryHandleTypeFlagBits handleType
,
1577 const void *pHostPointer
,
1578 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1580 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1584 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1585 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1586 uint32_t memoryTypeBits
= 0;
1587 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1588 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1589 memoryTypeBits
= (1 << i
);
1593 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1597 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1601 static enum radeon_ctx_priority
1602 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1604 /* Default to MEDIUM when a specific global priority isn't requested */
1606 return RADEON_CTX_PRIORITY_MEDIUM
;
1608 switch(pObj
->globalPriority
) {
1609 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1610 return RADEON_CTX_PRIORITY_REALTIME
;
1611 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1612 return RADEON_CTX_PRIORITY_HIGH
;
1613 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1614 return RADEON_CTX_PRIORITY_MEDIUM
;
1615 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1616 return RADEON_CTX_PRIORITY_LOW
;
1618 unreachable("Illegal global priority value");
1619 return RADEON_CTX_PRIORITY_INVALID
;
1624 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1625 uint32_t queue_family_index
, int idx
,
1626 VkDeviceQueueCreateFlags flags
,
1627 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1629 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1630 queue
->device
= device
;
1631 queue
->queue_family_index
= queue_family_index
;
1632 queue
->queue_idx
= idx
;
1633 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1634 queue
->flags
= flags
;
1636 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1638 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1644 radv_queue_finish(struct radv_queue
*queue
)
1647 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1649 if (queue
->initial_full_flush_preamble_cs
)
1650 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1651 if (queue
->initial_preamble_cs
)
1652 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1653 if (queue
->continue_preamble_cs
)
1654 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1655 if (queue
->descriptor_bo
)
1656 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1657 if (queue
->scratch_bo
)
1658 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1659 if (queue
->esgs_ring_bo
)
1660 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1661 if (queue
->gsvs_ring_bo
)
1662 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1663 if (queue
->tess_rings_bo
)
1664 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1665 if (queue
->compute_scratch_bo
)
1666 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1670 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1672 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1673 bo_list
->list
.count
= bo_list
->capacity
= 0;
1674 bo_list
->list
.bos
= NULL
;
1678 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1680 free(bo_list
->list
.bos
);
1681 pthread_mutex_destroy(&bo_list
->mutex
);
1684 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1685 struct radeon_winsys_bo
*bo
)
1687 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1692 if (unlikely(!device
->use_global_bo_list
))
1695 pthread_mutex_lock(&bo_list
->mutex
);
1696 if (bo_list
->list
.count
== bo_list
->capacity
) {
1697 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1698 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1701 pthread_mutex_unlock(&bo_list
->mutex
);
1702 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1705 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1706 bo_list
->capacity
= capacity
;
1709 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1710 pthread_mutex_unlock(&bo_list
->mutex
);
1714 static void radv_bo_list_remove(struct radv_device
*device
,
1715 struct radeon_winsys_bo
*bo
)
1717 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1722 if (unlikely(!device
->use_global_bo_list
))
1725 pthread_mutex_lock(&bo_list
->mutex
);
1726 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1727 if (bo_list
->list
.bos
[i
] == bo
) {
1728 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1729 --bo_list
->list
.count
;
1733 pthread_mutex_unlock(&bo_list
->mutex
);
1737 radv_device_init_gs_info(struct radv_device
*device
)
1739 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1740 device
->physical_device
->rad_info
.family
);
1743 static int radv_get_device_extension_index(const char *name
)
1745 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1746 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1753 radv_get_int_debug_option(const char *name
, int default_value
)
1760 result
= default_value
;
1764 result
= strtol(str
, &endptr
, 0);
1765 if (str
== endptr
) {
1766 /* No digits founs. */
1767 result
= default_value
;
1774 VkResult
radv_CreateDevice(
1775 VkPhysicalDevice physicalDevice
,
1776 const VkDeviceCreateInfo
* pCreateInfo
,
1777 const VkAllocationCallbacks
* pAllocator
,
1780 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1782 struct radv_device
*device
;
1784 bool keep_shader_info
= false;
1786 /* Check enabled features */
1787 if (pCreateInfo
->pEnabledFeatures
) {
1788 VkPhysicalDeviceFeatures supported_features
;
1789 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1790 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1791 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1792 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1793 for (uint32_t i
= 0; i
< num_features
; i
++) {
1794 if (enabled_feature
[i
] && !supported_feature
[i
])
1795 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1799 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1801 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1803 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1805 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1806 device
->instance
= physical_device
->instance
;
1807 device
->physical_device
= physical_device
;
1809 device
->ws
= physical_device
->ws
;
1811 device
->alloc
= *pAllocator
;
1813 device
->alloc
= physical_device
->instance
->alloc
;
1815 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1816 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1817 int index
= radv_get_device_extension_index(ext_name
);
1818 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1819 vk_free(&device
->alloc
, device
);
1820 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1823 device
->enabled_extensions
.extensions
[index
] = true;
1826 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1828 /* With update after bind we can't attach bo's to the command buffer
1829 * from the descriptor set anymore, so we have to use a global BO list.
1831 device
->use_global_bo_list
=
1832 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1833 device
->enabled_extensions
.EXT_descriptor_indexing
||
1834 device
->enabled_extensions
.EXT_buffer_device_address
;
1836 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1837 list_inithead(&device
->shader_slabs
);
1839 radv_bo_list_init(&device
->bo_list
);
1841 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1842 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1843 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1844 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1845 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1847 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1849 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1850 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1851 if (!device
->queues
[qfi
]) {
1852 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1856 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1858 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1860 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1861 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1862 qfi
, q
, queue_create
->flags
,
1864 if (result
!= VK_SUCCESS
)
1869 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1870 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1872 /* Disabled and not implemented for now. */
1873 device
->dfsm_allowed
= device
->pbb_allowed
&&
1874 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1875 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1878 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1881 /* The maximum number of scratch waves. Scratch space isn't divided
1882 * evenly between CUs. The number is only a function of the number of CUs.
1883 * We can decrease the constant to decrease the scratch buffer size.
1885 * sctx->scratch_waves must be >= the maximum possible size of
1886 * 1 threadgroup, so that the hw doesn't hang from being unable
1889 * The recommended value is 4 per CU at most. Higher numbers don't
1890 * bring much benefit, but they still occupy chip resources (think
1891 * async compute). I've seen ~2% performance difference between 4 and 32.
1893 uint32_t max_threads_per_block
= 2048;
1894 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1895 max_threads_per_block
/ 64);
1897 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1899 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1900 /* If the KMD allows it (there is a KMD hw register for it),
1901 * allow launching waves out-of-order.
1903 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1906 radv_device_init_gs_info(device
);
1908 device
->tess_offchip_block_dw_size
=
1909 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1910 device
->has_distributed_tess
=
1911 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1912 device
->physical_device
->rad_info
.max_se
>= 2;
1914 if (getenv("RADV_TRACE_FILE")) {
1915 const char *filename
= getenv("RADV_TRACE_FILE");
1917 keep_shader_info
= true;
1919 if (!radv_init_trace(device
))
1922 fprintf(stderr
, "*****************************************************************************\n");
1923 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1924 fprintf(stderr
, "*****************************************************************************\n");
1926 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1927 radv_dump_enabled_options(device
, stderr
);
1930 device
->keep_shader_info
= keep_shader_info
;
1932 result
= radv_device_init_meta(device
);
1933 if (result
!= VK_SUCCESS
)
1936 radv_device_init_msaa(device
);
1938 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1939 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1941 case RADV_QUEUE_GENERAL
:
1942 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1943 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1944 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1946 case RADV_QUEUE_COMPUTE
:
1947 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1948 radeon_emit(device
->empty_cs
[family
], 0);
1951 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1954 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
1955 cik_create_gfx_config(device
);
1957 VkPipelineCacheCreateInfo ci
;
1958 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1961 ci
.pInitialData
= NULL
;
1962 ci
.initialDataSize
= 0;
1964 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1966 if (result
!= VK_SUCCESS
)
1969 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1971 device
->force_aniso
=
1972 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1973 if (device
->force_aniso
>= 0) {
1974 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1975 1 << util_logbase2(device
->force_aniso
));
1978 *pDevice
= radv_device_to_handle(device
);
1982 radv_device_finish_meta(device
);
1984 radv_bo_list_finish(&device
->bo_list
);
1986 if (device
->trace_bo
)
1987 device
->ws
->buffer_destroy(device
->trace_bo
);
1989 if (device
->gfx_init
)
1990 device
->ws
->buffer_destroy(device
->gfx_init
);
1992 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1993 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1994 radv_queue_finish(&device
->queues
[i
][q
]);
1995 if (device
->queue_count
[i
])
1996 vk_free(&device
->alloc
, device
->queues
[i
]);
1999 vk_free(&device
->alloc
, device
);
2003 void radv_DestroyDevice(
2005 const VkAllocationCallbacks
* pAllocator
)
2007 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2012 if (device
->trace_bo
)
2013 device
->ws
->buffer_destroy(device
->trace_bo
);
2015 if (device
->gfx_init
)
2016 device
->ws
->buffer_destroy(device
->gfx_init
);
2018 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2019 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2020 radv_queue_finish(&device
->queues
[i
][q
]);
2021 if (device
->queue_count
[i
])
2022 vk_free(&device
->alloc
, device
->queues
[i
]);
2023 if (device
->empty_cs
[i
])
2024 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2026 radv_device_finish_meta(device
);
2028 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2029 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2031 radv_destroy_shader_slabs(device
);
2033 radv_bo_list_finish(&device
->bo_list
);
2034 vk_free(&device
->alloc
, device
);
2037 VkResult
radv_EnumerateInstanceLayerProperties(
2038 uint32_t* pPropertyCount
,
2039 VkLayerProperties
* pProperties
)
2041 if (pProperties
== NULL
) {
2042 *pPropertyCount
= 0;
2046 /* None supported at this time */
2047 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2050 VkResult
radv_EnumerateDeviceLayerProperties(
2051 VkPhysicalDevice physicalDevice
,
2052 uint32_t* pPropertyCount
,
2053 VkLayerProperties
* pProperties
)
2055 if (pProperties
== NULL
) {
2056 *pPropertyCount
= 0;
2060 /* None supported at this time */
2061 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2064 void radv_GetDeviceQueue2(
2066 const VkDeviceQueueInfo2
* pQueueInfo
,
2069 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2070 struct radv_queue
*queue
;
2072 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2073 if (pQueueInfo
->flags
!= queue
->flags
) {
2074 /* From the Vulkan 1.1.70 spec:
2076 * "The queue returned by vkGetDeviceQueue2 must have the same
2077 * flags value from this structure as that used at device
2078 * creation time in a VkDeviceQueueCreateInfo instance. If no
2079 * matching flags were specified at device creation time then
2080 * pQueue will return VK_NULL_HANDLE."
2082 *pQueue
= VK_NULL_HANDLE
;
2086 *pQueue
= radv_queue_to_handle(queue
);
2089 void radv_GetDeviceQueue(
2091 uint32_t queueFamilyIndex
,
2092 uint32_t queueIndex
,
2095 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2096 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2097 .queueFamilyIndex
= queueFamilyIndex
,
2098 .queueIndex
= queueIndex
2101 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2105 fill_geom_tess_rings(struct radv_queue
*queue
,
2107 bool add_sample_positions
,
2108 uint32_t esgs_ring_size
,
2109 struct radeon_winsys_bo
*esgs_ring_bo
,
2110 uint32_t gsvs_ring_size
,
2111 struct radeon_winsys_bo
*gsvs_ring_bo
,
2112 uint32_t tess_factor_ring_size
,
2113 uint32_t tess_offchip_ring_offset
,
2114 uint32_t tess_offchip_ring_size
,
2115 struct radeon_winsys_bo
*tess_rings_bo
)
2117 uint32_t *desc
= &map
[4];
2120 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2122 /* stride 0, num records - size, add tid, swizzle, elsize4,
2125 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2126 S_008F04_STRIDE(0) |
2127 S_008F04_SWIZZLE_ENABLE(true);
2128 desc
[2] = esgs_ring_size
;
2129 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2130 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2131 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2132 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2133 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2134 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2135 S_008F0C_ELEMENT_SIZE(1) |
2136 S_008F0C_INDEX_STRIDE(3) |
2137 S_008F0C_ADD_TID_ENABLE(true);
2139 /* GS entry for ES->GS ring */
2140 /* stride 0, num records - size, elsize0,
2143 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2144 S_008F04_STRIDE(0) |
2145 S_008F04_SWIZZLE_ENABLE(false);
2146 desc
[6] = esgs_ring_size
;
2147 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2148 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2149 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2150 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2151 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2152 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2153 S_008F0C_ELEMENT_SIZE(0) |
2154 S_008F0C_INDEX_STRIDE(0) |
2155 S_008F0C_ADD_TID_ENABLE(false);
2161 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2163 /* VS entry for GS->VS ring */
2164 /* stride 0, num records - size, elsize0,
2167 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2168 S_008F04_STRIDE(0) |
2169 S_008F04_SWIZZLE_ENABLE(false);
2170 desc
[2] = gsvs_ring_size
;
2171 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2175 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2176 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2177 S_008F0C_ELEMENT_SIZE(0) |
2178 S_008F0C_INDEX_STRIDE(0) |
2179 S_008F0C_ADD_TID_ENABLE(false);
2181 /* stride gsvs_itemsize, num records 64
2182 elsize 4, index stride 16 */
2183 /* shader will patch stride and desc[2] */
2185 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2186 S_008F04_STRIDE(0) |
2187 S_008F04_SWIZZLE_ENABLE(true);
2189 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2190 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2191 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2192 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2193 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2194 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2195 S_008F0C_ELEMENT_SIZE(1) |
2196 S_008F0C_INDEX_STRIDE(1) |
2197 S_008F0C_ADD_TID_ENABLE(true);
2202 if (tess_rings_bo
) {
2203 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2204 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2207 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2208 S_008F04_STRIDE(0) |
2209 S_008F04_SWIZZLE_ENABLE(false);
2210 desc
[2] = tess_factor_ring_size
;
2211 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2212 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2213 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2214 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2215 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2216 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2217 S_008F0C_ELEMENT_SIZE(0) |
2218 S_008F0C_INDEX_STRIDE(0) |
2219 S_008F0C_ADD_TID_ENABLE(false);
2221 desc
[4] = tess_offchip_va
;
2222 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2223 S_008F04_STRIDE(0) |
2224 S_008F04_SWIZZLE_ENABLE(false);
2225 desc
[6] = tess_offchip_ring_size
;
2226 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2227 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2228 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2229 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2230 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2232 S_008F0C_ELEMENT_SIZE(0) |
2233 S_008F0C_INDEX_STRIDE(0) |
2234 S_008F0C_ADD_TID_ENABLE(false);
2239 if (add_sample_positions
) {
2240 /* add sample positions after all rings */
2241 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2243 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2245 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2247 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2252 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2254 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2255 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2256 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2257 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2258 unsigned max_offchip_buffers
;
2259 unsigned offchip_granularity
;
2260 unsigned hs_offchip_param
;
2264 * This must be one less than the maximum number due to a hw limitation.
2265 * Various hardware bugs need thGFX7
2268 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2269 * Gfx7 should limit max_offchip_buffers to 508
2270 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2272 * Follow AMDVLK here.
2274 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2275 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2276 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2277 --max_offchip_buffers_per_se
;
2279 max_offchip_buffers
= max_offchip_buffers_per_se
*
2280 device
->physical_device
->rad_info
.max_se
;
2282 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2283 * around by setting 4K granularity.
2285 if (device
->tess_offchip_block_dw_size
== 4096) {
2286 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2287 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2289 assert(device
->tess_offchip_block_dw_size
== 8192);
2290 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2293 switch (device
->physical_device
->rad_info
.chip_class
) {
2295 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2301 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2305 *max_offchip_buffers_p
= max_offchip_buffers
;
2306 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2307 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2308 --max_offchip_buffers
;
2310 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2311 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2314 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2316 return hs_offchip_param
;
2320 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2321 struct radeon_winsys_bo
*esgs_ring_bo
,
2322 uint32_t esgs_ring_size
,
2323 struct radeon_winsys_bo
*gsvs_ring_bo
,
2324 uint32_t gsvs_ring_size
)
2326 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2330 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2333 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2335 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2336 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2337 radeon_emit(cs
, esgs_ring_size
>> 8);
2338 radeon_emit(cs
, gsvs_ring_size
>> 8);
2340 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2341 radeon_emit(cs
, esgs_ring_size
>> 8);
2342 radeon_emit(cs
, gsvs_ring_size
>> 8);
2347 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2348 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2349 struct radeon_winsys_bo
*tess_rings_bo
)
2356 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2358 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2360 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2361 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2362 S_030938_SIZE(tf_ring_size
/ 4));
2363 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2365 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2366 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2367 S_030944_BASE_HI(tf_va
>> 40));
2369 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2372 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2373 S_008988_SIZE(tf_ring_size
/ 4));
2374 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2376 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2382 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2383 struct radeon_winsys_bo
*compute_scratch_bo
)
2385 uint64_t scratch_va
;
2387 if (!compute_scratch_bo
)
2390 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2392 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2394 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2395 radeon_emit(cs
, scratch_va
);
2396 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2397 S_008F04_SWIZZLE_ENABLE(1));
2401 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2402 struct radeon_cmdbuf
*cs
,
2403 struct radeon_winsys_bo
*descriptor_bo
)
2410 va
= radv_buffer_get_va(descriptor_bo
);
2412 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2414 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2415 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2416 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2417 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2418 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2420 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2421 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2425 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2426 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2427 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2428 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2429 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2430 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2432 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2433 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2440 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2442 struct radv_device
*device
= queue
->device
;
2444 if (device
->gfx_init
) {
2445 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2447 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2448 radeon_emit(cs
, va
);
2449 radeon_emit(cs
, va
>> 32);
2450 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2452 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2454 struct radv_physical_device
*physical_device
= device
->physical_device
;
2455 si_emit_graphics(physical_device
, cs
);
2460 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2462 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2463 si_emit_compute(physical_device
, cs
);
2467 radv_get_preamble_cs(struct radv_queue
*queue
,
2468 uint32_t scratch_size
,
2469 uint32_t compute_scratch_size
,
2470 uint32_t esgs_ring_size
,
2471 uint32_t gsvs_ring_size
,
2472 bool needs_tess_rings
,
2473 bool needs_sample_positions
,
2474 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2475 struct radeon_cmdbuf
**initial_preamble_cs
,
2476 struct radeon_cmdbuf
**continue_preamble_cs
)
2478 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2479 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2480 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2481 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2482 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2483 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2484 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2485 bool add_tess_rings
= false, add_sample_positions
= false;
2486 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2487 unsigned max_offchip_buffers
;
2488 unsigned hs_offchip_param
= 0;
2489 unsigned tess_offchip_ring_offset
;
2490 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2491 if (!queue
->has_tess_rings
) {
2492 if (needs_tess_rings
)
2493 add_tess_rings
= true;
2495 if (!queue
->has_sample_positions
) {
2496 if (needs_sample_positions
)
2497 add_sample_positions
= true;
2499 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2500 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2501 &max_offchip_buffers
);
2502 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2503 tess_offchip_ring_size
= max_offchip_buffers
*
2504 queue
->device
->tess_offchip_block_dw_size
* 4;
2506 if (scratch_size
<= queue
->scratch_size
&&
2507 compute_scratch_size
<= queue
->compute_scratch_size
&&
2508 esgs_ring_size
<= queue
->esgs_ring_size
&&
2509 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2510 !add_tess_rings
&& !add_sample_positions
&&
2511 queue
->initial_preamble_cs
) {
2512 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2513 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2514 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2515 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2516 *continue_preamble_cs
= NULL
;
2520 if (scratch_size
> queue
->scratch_size
) {
2521 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2526 RADV_BO_PRIORITY_SCRATCH
);
2530 scratch_bo
= queue
->scratch_bo
;
2532 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2533 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2534 compute_scratch_size
,
2538 RADV_BO_PRIORITY_SCRATCH
);
2539 if (!compute_scratch_bo
)
2543 compute_scratch_bo
= queue
->compute_scratch_bo
;
2545 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2546 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2551 RADV_BO_PRIORITY_SCRATCH
);
2555 esgs_ring_bo
= queue
->esgs_ring_bo
;
2556 esgs_ring_size
= queue
->esgs_ring_size
;
2559 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2560 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2565 RADV_BO_PRIORITY_SCRATCH
);
2569 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2570 gsvs_ring_size
= queue
->gsvs_ring_size
;
2573 if (add_tess_rings
) {
2574 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2575 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2579 RADV_BO_PRIORITY_SCRATCH
);
2583 tess_rings_bo
= queue
->tess_rings_bo
;
2586 if (scratch_bo
!= queue
->scratch_bo
||
2587 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2588 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2589 tess_rings_bo
!= queue
->tess_rings_bo
||
2590 add_sample_positions
) {
2592 if (gsvs_ring_bo
|| esgs_ring_bo
||
2593 tess_rings_bo
|| add_sample_positions
) {
2594 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2595 if (add_sample_positions
)
2596 size
+= 128; /* 64+32+16+8 = 120 bytes */
2598 else if (scratch_bo
)
2599 size
= 8; /* 2 dword */
2601 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2605 RADEON_FLAG_CPU_ACCESS
|
2606 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2607 RADEON_FLAG_READ_ONLY
,
2608 RADV_BO_PRIORITY_DESCRIPTOR
);
2612 descriptor_bo
= queue
->descriptor_bo
;
2614 if (descriptor_bo
!= queue
->descriptor_bo
) {
2615 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2618 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2619 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2620 S_008F04_SWIZZLE_ENABLE(1);
2621 map
[0] = scratch_va
;
2625 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2626 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2627 esgs_ring_size
, esgs_ring_bo
,
2628 gsvs_ring_size
, gsvs_ring_bo
,
2629 tess_factor_ring_size
,
2630 tess_offchip_ring_offset
,
2631 tess_offchip_ring_size
,
2634 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2637 for(int i
= 0; i
< 3; ++i
) {
2638 struct radeon_cmdbuf
*cs
= NULL
;
2639 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2640 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2647 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2649 /* Emit initial configuration. */
2650 switch (queue
->queue_family_index
) {
2651 case RADV_QUEUE_GENERAL
:
2652 radv_init_graphics_state(cs
, queue
);
2654 case RADV_QUEUE_COMPUTE
:
2655 radv_init_compute_state(cs
, queue
);
2657 case RADV_QUEUE_TRANSFER
:
2661 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2662 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2663 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2664 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2665 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2668 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2669 gsvs_ring_bo
, gsvs_ring_size
);
2670 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2671 tess_factor_ring_size
, tess_rings_bo
);
2672 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2673 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2676 si_cs_emit_cache_flush(cs
,
2677 queue
->device
->physical_device
->rad_info
.chip_class
,
2679 queue
->queue_family_index
== RING_COMPUTE
&&
2680 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2681 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2682 RADV_CMD_FLAG_INV_ICACHE
|
2683 RADV_CMD_FLAG_INV_SMEM_L1
|
2684 RADV_CMD_FLAG_INV_VMEM_L1
|
2685 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2686 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2687 } else if (i
== 1) {
2688 si_cs_emit_cache_flush(cs
,
2689 queue
->device
->physical_device
->rad_info
.chip_class
,
2691 queue
->queue_family_index
== RING_COMPUTE
&&
2692 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2693 RADV_CMD_FLAG_INV_ICACHE
|
2694 RADV_CMD_FLAG_INV_SMEM_L1
|
2695 RADV_CMD_FLAG_INV_VMEM_L1
|
2696 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2697 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2700 if (!queue
->device
->ws
->cs_finalize(cs
))
2704 if (queue
->initial_full_flush_preamble_cs
)
2705 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2707 if (queue
->initial_preamble_cs
)
2708 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2710 if (queue
->continue_preamble_cs
)
2711 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2713 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2714 queue
->initial_preamble_cs
= dest_cs
[1];
2715 queue
->continue_preamble_cs
= dest_cs
[2];
2717 if (scratch_bo
!= queue
->scratch_bo
) {
2718 if (queue
->scratch_bo
)
2719 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2720 queue
->scratch_bo
= scratch_bo
;
2721 queue
->scratch_size
= scratch_size
;
2724 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2725 if (queue
->compute_scratch_bo
)
2726 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2727 queue
->compute_scratch_bo
= compute_scratch_bo
;
2728 queue
->compute_scratch_size
= compute_scratch_size
;
2731 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2732 if (queue
->esgs_ring_bo
)
2733 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2734 queue
->esgs_ring_bo
= esgs_ring_bo
;
2735 queue
->esgs_ring_size
= esgs_ring_size
;
2738 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2739 if (queue
->gsvs_ring_bo
)
2740 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2741 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2742 queue
->gsvs_ring_size
= gsvs_ring_size
;
2745 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2746 queue
->tess_rings_bo
= tess_rings_bo
;
2747 queue
->has_tess_rings
= true;
2750 if (descriptor_bo
!= queue
->descriptor_bo
) {
2751 if (queue
->descriptor_bo
)
2752 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2754 queue
->descriptor_bo
= descriptor_bo
;
2757 if (add_sample_positions
)
2758 queue
->has_sample_positions
= true;
2760 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2761 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2762 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2763 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2764 *continue_preamble_cs
= NULL
;
2767 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2769 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2770 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2771 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2772 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2773 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2774 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2775 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2776 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2777 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2778 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2779 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2780 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2781 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2782 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2785 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2786 struct radv_winsys_sem_counts
*counts
,
2788 const VkSemaphore
*sems
,
2792 int syncobj_idx
= 0, sem_idx
= 0;
2794 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2797 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2798 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2800 if (sem
->temp_syncobj
|| sem
->syncobj
)
2801 counts
->syncobj_count
++;
2803 counts
->sem_count
++;
2806 if (_fence
!= VK_NULL_HANDLE
) {
2807 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2808 if (fence
->temp_syncobj
|| fence
->syncobj
)
2809 counts
->syncobj_count
++;
2812 if (counts
->syncobj_count
) {
2813 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2814 if (!counts
->syncobj
)
2815 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2818 if (counts
->sem_count
) {
2819 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2821 free(counts
->syncobj
);
2822 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2826 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2827 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2829 if (sem
->temp_syncobj
) {
2830 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2832 else if (sem
->syncobj
)
2833 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2836 counts
->sem
[sem_idx
++] = sem
->sem
;
2840 if (_fence
!= VK_NULL_HANDLE
) {
2841 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2842 if (fence
->temp_syncobj
)
2843 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2844 else if (fence
->syncobj
)
2845 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2852 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2854 free(sem_info
->wait
.syncobj
);
2855 free(sem_info
->wait
.sem
);
2856 free(sem_info
->signal
.syncobj
);
2857 free(sem_info
->signal
.sem
);
2861 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2863 const VkSemaphore
*sems
)
2865 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2866 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2868 if (sem
->temp_syncobj
) {
2869 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2870 sem
->temp_syncobj
= 0;
2876 radv_alloc_sem_info(struct radv_instance
*instance
,
2877 struct radv_winsys_sem_info
*sem_info
,
2879 const VkSemaphore
*wait_sems
,
2880 int num_signal_sems
,
2881 const VkSemaphore
*signal_sems
,
2885 memset(sem_info
, 0, sizeof(*sem_info
));
2887 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2890 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2892 radv_free_sem_info(sem_info
);
2894 /* caller can override these */
2895 sem_info
->cs_emit_wait
= true;
2896 sem_info
->cs_emit_signal
= true;
2900 /* Signals fence as soon as all the work currently put on queue is done. */
2901 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2902 struct radv_fence
*fence
)
2906 struct radv_winsys_sem_info sem_info
;
2908 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2909 radv_fence_to_handle(fence
));
2910 if (result
!= VK_SUCCESS
)
2913 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2914 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2915 1, NULL
, NULL
, &sem_info
, NULL
,
2916 false, fence
->fence
);
2917 radv_free_sem_info(&sem_info
);
2920 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2925 VkResult
radv_QueueSubmit(
2927 uint32_t submitCount
,
2928 const VkSubmitInfo
* pSubmits
,
2931 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2932 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2933 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2934 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2936 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
2937 uint32_t scratch_size
= 0;
2938 uint32_t compute_scratch_size
= 0;
2939 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2940 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2942 bool fence_emitted
= false;
2943 bool tess_rings_needed
= false;
2944 bool sample_positions_needed
= false;
2946 /* Do this first so failing to allocate scratch buffers can't result in
2947 * partially executed submissions. */
2948 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2949 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2950 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2951 pSubmits
[i
].pCommandBuffers
[j
]);
2953 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2954 compute_scratch_size
= MAX2(compute_scratch_size
,
2955 cmd_buffer
->compute_scratch_size_needed
);
2956 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2957 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2958 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2959 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2963 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2964 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2965 sample_positions_needed
, &initial_flush_preamble_cs
,
2966 &initial_preamble_cs
, &continue_preamble_cs
);
2967 if (result
!= VK_SUCCESS
)
2970 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2971 struct radeon_cmdbuf
**cs_array
;
2972 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2973 bool can_patch
= true;
2975 struct radv_winsys_sem_info sem_info
;
2977 result
= radv_alloc_sem_info(queue
->device
->instance
,
2979 pSubmits
[i
].waitSemaphoreCount
,
2980 pSubmits
[i
].pWaitSemaphores
,
2981 pSubmits
[i
].signalSemaphoreCount
,
2982 pSubmits
[i
].pSignalSemaphores
,
2984 if (result
!= VK_SUCCESS
)
2987 if (!pSubmits
[i
].commandBufferCount
) {
2988 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2989 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2990 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2995 radv_loge("failed to submit CS %d\n", i
);
2998 fence_emitted
= true;
3000 radv_free_sem_info(&sem_info
);
3004 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3005 (pSubmits
[i
].commandBufferCount
));
3007 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3008 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3009 pSubmits
[i
].pCommandBuffers
[j
]);
3010 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3012 cs_array
[j
] = cmd_buffer
->cs
;
3013 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3016 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3019 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3020 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3021 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3023 advance
= MIN2(max_cs_submission
,
3024 pSubmits
[i
].commandBufferCount
- j
);
3026 if (queue
->device
->trace_bo
)
3027 *queue
->device
->trace_id_ptr
= 0;
3029 sem_info
.cs_emit_wait
= j
== 0;
3030 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3032 if (unlikely(queue
->device
->use_global_bo_list
)) {
3033 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3034 bo_list
= &queue
->device
->bo_list
.list
;
3037 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3038 advance
, initial_preamble
, continue_preamble_cs
,
3040 can_patch
, base_fence
);
3042 if (unlikely(queue
->device
->use_global_bo_list
))
3043 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3046 radv_loge("failed to submit CS %d\n", i
);
3049 fence_emitted
= true;
3050 if (queue
->device
->trace_bo
) {
3051 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3055 radv_free_temp_syncobjs(queue
->device
,
3056 pSubmits
[i
].waitSemaphoreCount
,
3057 pSubmits
[i
].pWaitSemaphores
);
3058 radv_free_sem_info(&sem_info
);
3063 if (!fence_emitted
) {
3064 result
= radv_signal_fence(queue
, fence
);
3065 if (result
!= VK_SUCCESS
)
3073 VkResult
radv_QueueWaitIdle(
3076 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3078 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3079 radv_queue_family_to_ring(queue
->queue_family_index
),
3084 VkResult
radv_DeviceWaitIdle(
3087 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3089 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3090 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3091 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3097 VkResult
radv_EnumerateInstanceExtensionProperties(
3098 const char* pLayerName
,
3099 uint32_t* pPropertyCount
,
3100 VkExtensionProperties
* pProperties
)
3102 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3104 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3105 if (radv_supported_instance_extensions
.extensions
[i
]) {
3106 vk_outarray_append(&out
, prop
) {
3107 *prop
= radv_instance_extensions
[i
];
3112 return vk_outarray_status(&out
);
3115 VkResult
radv_EnumerateDeviceExtensionProperties(
3116 VkPhysicalDevice physicalDevice
,
3117 const char* pLayerName
,
3118 uint32_t* pPropertyCount
,
3119 VkExtensionProperties
* pProperties
)
3121 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3122 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3124 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3125 if (device
->supported_extensions
.extensions
[i
]) {
3126 vk_outarray_append(&out
, prop
) {
3127 *prop
= radv_device_extensions
[i
];
3132 return vk_outarray_status(&out
);
3135 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3136 VkInstance _instance
,
3139 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3141 return radv_lookup_entrypoint_checked(pName
,
3142 instance
? instance
->apiVersion
: 0,
3143 instance
? &instance
->enabled_extensions
: NULL
,
3147 /* The loader wants us to expose a second GetInstanceProcAddr function
3148 * to work around certain LD_PRELOAD issues seen in apps.
3151 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3152 VkInstance instance
,
3156 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3157 VkInstance instance
,
3160 return radv_GetInstanceProcAddr(instance
, pName
);
3164 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3165 VkInstance _instance
,
3169 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3170 VkInstance _instance
,
3173 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3175 return radv_lookup_physical_device_entrypoint_checked(pName
,
3176 instance
? instance
->apiVersion
: 0,
3177 instance
? &instance
->enabled_extensions
: NULL
);
3180 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3184 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3186 return radv_lookup_entrypoint_checked(pName
,
3187 device
->instance
->apiVersion
,
3188 &device
->instance
->enabled_extensions
,
3189 &device
->enabled_extensions
);
3192 bool radv_get_memory_fd(struct radv_device
*device
,
3193 struct radv_device_memory
*memory
,
3196 struct radeon_bo_metadata metadata
;
3198 if (memory
->image
) {
3199 radv_init_metadata(device
, memory
->image
, &metadata
);
3200 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3203 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3207 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3208 const VkMemoryAllocateInfo
* pAllocateInfo
,
3209 const VkAllocationCallbacks
* pAllocator
,
3210 VkDeviceMemory
* pMem
)
3212 struct radv_device_memory
*mem
;
3214 enum radeon_bo_domain domain
;
3216 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3218 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3220 if (pAllocateInfo
->allocationSize
== 0) {
3221 /* Apparently, this is allowed */
3222 *pMem
= VK_NULL_HANDLE
;
3226 const VkImportMemoryFdInfoKHR
*import_info
=
3227 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3228 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3229 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3230 const VkExportMemoryAllocateInfo
*export_info
=
3231 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3232 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3233 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3235 const struct wsi_memory_allocate_info
*wsi_info
=
3236 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3238 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3239 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3241 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3243 if (wsi_info
&& wsi_info
->implicit_sync
)
3244 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3246 if (dedicate_info
) {
3247 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3248 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3254 float priority_float
= 0.5;
3255 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3256 vk_find_struct_const(pAllocateInfo
->pNext
,
3257 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3259 priority_float
= priority_ext
->priority
;
3261 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3262 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3264 mem
->user_ptr
= NULL
;
3267 assert(import_info
->handleType
==
3268 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3269 import_info
->handleType
==
3270 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3271 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3272 priority
, NULL
, NULL
);
3274 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3277 close(import_info
->fd
);
3279 } else if (host_ptr_info
) {
3280 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3281 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3282 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3283 pAllocateInfo
->allocationSize
,
3286 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3289 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3292 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3293 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3294 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3295 domain
= RADEON_DOMAIN_GTT
;
3297 domain
= RADEON_DOMAIN_VRAM
;
3299 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3300 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3302 flags
|= RADEON_FLAG_CPU_ACCESS
;
3304 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3305 flags
|= RADEON_FLAG_GTT_WC
;
3307 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3308 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3309 if (device
->use_global_bo_list
) {
3310 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3314 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3315 domain
, flags
, priority
);
3318 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3321 mem
->type_index
= mem_type_index
;
3324 result
= radv_bo_list_add(device
, mem
->bo
);
3325 if (result
!= VK_SUCCESS
)
3328 *pMem
= radv_device_memory_to_handle(mem
);
3333 device
->ws
->buffer_destroy(mem
->bo
);
3335 vk_free2(&device
->alloc
, pAllocator
, mem
);
3340 VkResult
radv_AllocateMemory(
3342 const VkMemoryAllocateInfo
* pAllocateInfo
,
3343 const VkAllocationCallbacks
* pAllocator
,
3344 VkDeviceMemory
* pMem
)
3346 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3347 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3350 void radv_FreeMemory(
3352 VkDeviceMemory _mem
,
3353 const VkAllocationCallbacks
* pAllocator
)
3355 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3356 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3361 radv_bo_list_remove(device
, mem
->bo
);
3362 device
->ws
->buffer_destroy(mem
->bo
);
3365 vk_free2(&device
->alloc
, pAllocator
, mem
);
3368 VkResult
radv_MapMemory(
3370 VkDeviceMemory _memory
,
3371 VkDeviceSize offset
,
3373 VkMemoryMapFlags flags
,
3376 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3377 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3385 *ppData
= mem
->user_ptr
;
3387 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3394 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3397 void radv_UnmapMemory(
3399 VkDeviceMemory _memory
)
3401 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3402 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3407 if (mem
->user_ptr
== NULL
)
3408 device
->ws
->buffer_unmap(mem
->bo
);
3411 VkResult
radv_FlushMappedMemoryRanges(
3413 uint32_t memoryRangeCount
,
3414 const VkMappedMemoryRange
* pMemoryRanges
)
3419 VkResult
radv_InvalidateMappedMemoryRanges(
3421 uint32_t memoryRangeCount
,
3422 const VkMappedMemoryRange
* pMemoryRanges
)
3427 void radv_GetBufferMemoryRequirements(
3430 VkMemoryRequirements
* pMemoryRequirements
)
3432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3433 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3435 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3437 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3438 pMemoryRequirements
->alignment
= 4096;
3440 pMemoryRequirements
->alignment
= 16;
3442 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3445 void radv_GetBufferMemoryRequirements2(
3447 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3448 VkMemoryRequirements2
*pMemoryRequirements
)
3450 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3451 &pMemoryRequirements
->memoryRequirements
);
3452 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3453 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3454 switch (ext
->sType
) {
3455 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3456 VkMemoryDedicatedRequirements
*req
=
3457 (VkMemoryDedicatedRequirements
*) ext
;
3458 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3459 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3468 void radv_GetImageMemoryRequirements(
3471 VkMemoryRequirements
* pMemoryRequirements
)
3473 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3474 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3476 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3478 pMemoryRequirements
->size
= image
->size
;
3479 pMemoryRequirements
->alignment
= image
->alignment
;
3482 void radv_GetImageMemoryRequirements2(
3484 const VkImageMemoryRequirementsInfo2
*pInfo
,
3485 VkMemoryRequirements2
*pMemoryRequirements
)
3487 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3488 &pMemoryRequirements
->memoryRequirements
);
3490 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3492 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3493 switch (ext
->sType
) {
3494 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3495 VkMemoryDedicatedRequirements
*req
=
3496 (VkMemoryDedicatedRequirements
*) ext
;
3497 req
->requiresDedicatedAllocation
= image
->shareable
;
3498 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3507 void radv_GetImageSparseMemoryRequirements(
3510 uint32_t* pSparseMemoryRequirementCount
,
3511 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3516 void radv_GetImageSparseMemoryRequirements2(
3518 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3519 uint32_t* pSparseMemoryRequirementCount
,
3520 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3525 void radv_GetDeviceMemoryCommitment(
3527 VkDeviceMemory memory
,
3528 VkDeviceSize
* pCommittedMemoryInBytes
)
3530 *pCommittedMemoryInBytes
= 0;
3533 VkResult
radv_BindBufferMemory2(VkDevice device
,
3534 uint32_t bindInfoCount
,
3535 const VkBindBufferMemoryInfo
*pBindInfos
)
3537 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3538 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3539 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3542 buffer
->bo
= mem
->bo
;
3543 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3551 VkResult
radv_BindBufferMemory(
3554 VkDeviceMemory memory
,
3555 VkDeviceSize memoryOffset
)
3557 const VkBindBufferMemoryInfo info
= {
3558 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3561 .memoryOffset
= memoryOffset
3564 return radv_BindBufferMemory2(device
, 1, &info
);
3567 VkResult
radv_BindImageMemory2(VkDevice device
,
3568 uint32_t bindInfoCount
,
3569 const VkBindImageMemoryInfo
*pBindInfos
)
3571 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3572 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3573 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3576 image
->bo
= mem
->bo
;
3577 image
->offset
= pBindInfos
[i
].memoryOffset
;
3587 VkResult
radv_BindImageMemory(
3590 VkDeviceMemory memory
,
3591 VkDeviceSize memoryOffset
)
3593 const VkBindImageMemoryInfo info
= {
3594 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3597 .memoryOffset
= memoryOffset
3600 return radv_BindImageMemory2(device
, 1, &info
);
3605 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3606 const VkSparseBufferMemoryBindInfo
*bind
)
3608 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3610 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3611 struct radv_device_memory
*mem
= NULL
;
3613 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3614 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3616 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3617 bind
->pBinds
[i
].resourceOffset
,
3618 bind
->pBinds
[i
].size
,
3619 mem
? mem
->bo
: NULL
,
3620 bind
->pBinds
[i
].memoryOffset
);
3625 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3626 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3628 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3630 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3631 struct radv_device_memory
*mem
= NULL
;
3633 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3634 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3636 device
->ws
->buffer_virtual_bind(image
->bo
,
3637 bind
->pBinds
[i
].resourceOffset
,
3638 bind
->pBinds
[i
].size
,
3639 mem
? mem
->bo
: NULL
,
3640 bind
->pBinds
[i
].memoryOffset
);
3644 VkResult
radv_QueueBindSparse(
3646 uint32_t bindInfoCount
,
3647 const VkBindSparseInfo
* pBindInfo
,
3650 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3651 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3652 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3653 bool fence_emitted
= false;
3657 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3658 struct radv_winsys_sem_info sem_info
;
3659 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3660 radv_sparse_buffer_bind_memory(queue
->device
,
3661 pBindInfo
[i
].pBufferBinds
+ j
);
3664 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3665 radv_sparse_image_opaque_bind_memory(queue
->device
,
3666 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3670 result
= radv_alloc_sem_info(queue
->device
->instance
,
3672 pBindInfo
[i
].waitSemaphoreCount
,
3673 pBindInfo
[i
].pWaitSemaphores
,
3674 pBindInfo
[i
].signalSemaphoreCount
,
3675 pBindInfo
[i
].pSignalSemaphores
,
3677 if (result
!= VK_SUCCESS
)
3680 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3681 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3682 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3687 radv_loge("failed to submit CS %d\n", i
);
3691 fence_emitted
= true;
3694 radv_free_sem_info(&sem_info
);
3699 if (!fence_emitted
) {
3700 result
= radv_signal_fence(queue
, fence
);
3701 if (result
!= VK_SUCCESS
)
3709 VkResult
radv_CreateFence(
3711 const VkFenceCreateInfo
* pCreateInfo
,
3712 const VkAllocationCallbacks
* pAllocator
,
3715 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3716 const VkExportFenceCreateInfo
*export
=
3717 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3718 VkExternalFenceHandleTypeFlags handleTypes
=
3719 export
? export
->handleTypes
: 0;
3721 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3723 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3726 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3728 fence
->fence_wsi
= NULL
;
3729 fence
->temp_syncobj
= 0;
3730 if (device
->always_use_syncobj
|| handleTypes
) {
3731 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3733 vk_free2(&device
->alloc
, pAllocator
, fence
);
3734 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3736 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3737 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3739 fence
->fence
= NULL
;
3741 fence
->fence
= device
->ws
->create_fence();
3742 if (!fence
->fence
) {
3743 vk_free2(&device
->alloc
, pAllocator
, fence
);
3744 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3747 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3748 device
->ws
->signal_fence(fence
->fence
);
3751 *pFence
= radv_fence_to_handle(fence
);
3756 void radv_DestroyFence(
3759 const VkAllocationCallbacks
* pAllocator
)
3761 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3762 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3767 if (fence
->temp_syncobj
)
3768 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3770 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3772 device
->ws
->destroy_fence(fence
->fence
);
3773 if (fence
->fence_wsi
)
3774 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3775 vk_free2(&device
->alloc
, pAllocator
, fence
);
3779 uint64_t radv_get_current_time(void)
3782 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3783 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3786 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3788 uint64_t current_time
= radv_get_current_time();
3790 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3792 return current_time
+ timeout
;
3796 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3797 uint32_t fenceCount
, const VkFence
*pFences
)
3799 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3800 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3801 if (fence
->fence
== NULL
|| fence
->syncobj
||
3802 fence
->temp_syncobj
|| fence
->fence_wsi
||
3803 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3809 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3811 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3812 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3813 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3819 VkResult
radv_WaitForFences(
3821 uint32_t fenceCount
,
3822 const VkFence
* pFences
,
3826 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3827 timeout
= radv_get_absolute_timeout(timeout
);
3829 if (device
->always_use_syncobj
&&
3830 radv_all_fences_syncobj(fenceCount
, pFences
))
3832 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3834 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3836 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3837 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3838 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3841 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3844 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3847 if (!waitAll
&& fenceCount
> 1) {
3848 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3849 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3850 uint32_t wait_count
= 0;
3851 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3853 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3855 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3856 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3858 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3863 fences
[wait_count
++] = fence
->fence
;
3866 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3867 waitAll
, timeout
- radv_get_current_time());
3870 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3873 while(radv_get_current_time() <= timeout
) {
3874 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3875 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3882 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3883 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3884 bool expired
= false;
3886 if (fence
->temp_syncobj
) {
3887 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3892 if (fence
->syncobj
) {
3893 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3899 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
3900 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
3901 radv_get_current_time() <= timeout
)
3905 expired
= device
->ws
->fence_wait(device
->ws
,
3912 if (fence
->fence_wsi
) {
3913 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3914 if (result
!= VK_SUCCESS
)
3922 VkResult
radv_ResetFences(VkDevice _device
,
3923 uint32_t fenceCount
,
3924 const VkFence
*pFences
)
3926 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3928 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3929 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3931 device
->ws
->reset_fence(fence
->fence
);
3933 /* Per spec, we first restore the permanent payload, and then reset, so
3934 * having a temp syncobj should not skip resetting the permanent syncobj. */
3935 if (fence
->temp_syncobj
) {
3936 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3937 fence
->temp_syncobj
= 0;
3940 if (fence
->syncobj
) {
3941 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3948 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3950 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3951 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3953 if (fence
->temp_syncobj
) {
3954 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3955 return success
? VK_SUCCESS
: VK_NOT_READY
;
3958 if (fence
->syncobj
) {
3959 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3960 return success
? VK_SUCCESS
: VK_NOT_READY
;
3964 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3965 return VK_NOT_READY
;
3967 if (fence
->fence_wsi
) {
3968 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3970 if (result
!= VK_SUCCESS
) {
3971 if (result
== VK_TIMEOUT
)
3972 return VK_NOT_READY
;
3980 // Queue semaphore functions
3982 VkResult
radv_CreateSemaphore(
3984 const VkSemaphoreCreateInfo
* pCreateInfo
,
3985 const VkAllocationCallbacks
* pAllocator
,
3986 VkSemaphore
* pSemaphore
)
3988 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3989 const VkExportSemaphoreCreateInfo
*export
=
3990 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
3991 VkExternalSemaphoreHandleTypeFlags handleTypes
=
3992 export
? export
->handleTypes
: 0;
3994 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
3996 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3998 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4000 sem
->temp_syncobj
= 0;
4001 /* create a syncobject if we are going to export this semaphore */
4002 if (device
->always_use_syncobj
|| handleTypes
) {
4003 assert (device
->physical_device
->rad_info
.has_syncobj
);
4004 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4006 vk_free2(&device
->alloc
, pAllocator
, sem
);
4007 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4011 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4013 vk_free2(&device
->alloc
, pAllocator
, sem
);
4014 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4019 *pSemaphore
= radv_semaphore_to_handle(sem
);
4023 void radv_DestroySemaphore(
4025 VkSemaphore _semaphore
,
4026 const VkAllocationCallbacks
* pAllocator
)
4028 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4029 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4034 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4036 device
->ws
->destroy_sem(sem
->sem
);
4037 vk_free2(&device
->alloc
, pAllocator
, sem
);
4040 VkResult
radv_CreateEvent(
4042 const VkEventCreateInfo
* pCreateInfo
,
4043 const VkAllocationCallbacks
* pAllocator
,
4046 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4047 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4049 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4052 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4054 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4056 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4057 RADV_BO_PRIORITY_FENCE
);
4059 vk_free2(&device
->alloc
, pAllocator
, event
);
4060 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4063 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4065 *pEvent
= radv_event_to_handle(event
);
4070 void radv_DestroyEvent(
4073 const VkAllocationCallbacks
* pAllocator
)
4075 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4076 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4080 device
->ws
->buffer_destroy(event
->bo
);
4081 vk_free2(&device
->alloc
, pAllocator
, event
);
4084 VkResult
radv_GetEventStatus(
4088 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4090 if (*event
->map
== 1)
4091 return VK_EVENT_SET
;
4092 return VK_EVENT_RESET
;
4095 VkResult
radv_SetEvent(
4099 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4105 VkResult
radv_ResetEvent(
4109 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4115 VkResult
radv_CreateBuffer(
4117 const VkBufferCreateInfo
* pCreateInfo
,
4118 const VkAllocationCallbacks
* pAllocator
,
4121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4122 struct radv_buffer
*buffer
;
4124 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4126 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4127 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4129 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4131 buffer
->size
= pCreateInfo
->size
;
4132 buffer
->usage
= pCreateInfo
->usage
;
4135 buffer
->flags
= pCreateInfo
->flags
;
4137 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4138 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4140 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4141 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4142 align64(buffer
->size
, 4096),
4143 4096, 0, RADEON_FLAG_VIRTUAL
,
4144 RADV_BO_PRIORITY_VIRTUAL
);
4146 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4147 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4151 *pBuffer
= radv_buffer_to_handle(buffer
);
4156 void radv_DestroyBuffer(
4159 const VkAllocationCallbacks
* pAllocator
)
4161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4162 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4167 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4168 device
->ws
->buffer_destroy(buffer
->bo
);
4170 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4173 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4175 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4177 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4178 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4182 static inline unsigned
4183 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4186 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4188 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4191 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4193 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4197 radv_init_dcc_control_reg(struct radv_device
*device
,
4198 struct radv_image_view
*iview
)
4200 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4201 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4202 unsigned max_compressed_block_size
;
4203 unsigned independent_64b_blocks
;
4205 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4208 if (iview
->image
->info
.samples
> 1) {
4209 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4210 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4211 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4212 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4215 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4216 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4217 * dGPU and 64 for APU because all of our APUs to date use
4218 * DIMMs which have a request granularity size of 64B while all
4219 * other chips have a 32B request size.
4221 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4224 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4225 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4226 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4227 /* If this DCC image is potentially going to be used in texture
4228 * fetches, we need some special settings.
4230 independent_64b_blocks
= 1;
4231 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4233 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4234 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4235 * big as possible for better compression state.
4237 independent_64b_blocks
= 0;
4238 max_compressed_block_size
= max_uncompressed_block_size
;
4241 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4242 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4243 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4244 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
4248 radv_initialise_color_surface(struct radv_device
*device
,
4249 struct radv_color_buffer_info
*cb
,
4250 struct radv_image_view
*iview
)
4252 const struct vk_format_description
*desc
;
4253 unsigned ntype
, format
, swap
, endian
;
4254 unsigned blend_clamp
= 0, blend_bypass
= 0;
4256 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4257 const struct radeon_surf
*surf
= &plane
->surface
;
4259 desc
= vk_format_description(iview
->vk_format
);
4261 memset(cb
, 0, sizeof(*cb
));
4263 /* Intensity is implemented as Red, so treat it that way. */
4264 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4266 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4268 cb
->cb_color_base
= va
>> 8;
4270 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4271 struct gfx9_surf_meta_flags meta
;
4272 if (iview
->image
->dcc_offset
)
4273 meta
= surf
->u
.gfx9
.dcc
;
4275 meta
= surf
->u
.gfx9
.cmask
;
4277 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4278 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4279 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4280 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4282 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4283 cb
->cb_color_base
|= surf
->tile_swizzle
;
4285 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4287 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4288 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4290 cb
->cb_color_base
+= level_info
->offset
>> 8;
4291 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4292 cb
->cb_color_base
|= surf
->tile_swizzle
;
4294 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4295 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4296 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4298 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4299 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4300 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4302 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4304 if (radv_image_has_fmask(iview
->image
)) {
4305 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4306 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4307 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4308 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4310 /* This must be set for fast clear to work without FMASK. */
4311 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4312 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4313 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4314 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4318 /* CMASK variables */
4319 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4320 va
+= iview
->image
->cmask
.offset
;
4321 cb
->cb_color_cmask
= va
>> 8;
4323 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4324 va
+= iview
->image
->dcc_offset
;
4325 cb
->cb_dcc_base
= va
>> 8;
4326 cb
->cb_dcc_base
|= surf
->tile_swizzle
;
4328 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4329 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4330 S_028C6C_SLICE_MAX(max_slice
);
4332 if (iview
->image
->info
.samples
> 1) {
4333 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4335 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4336 S_028C74_NUM_FRAGMENTS(log_samples
);
4339 if (radv_image_has_fmask(iview
->image
)) {
4340 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4341 cb
->cb_color_fmask
= va
>> 8;
4342 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4344 cb
->cb_color_fmask
= cb
->cb_color_base
;
4347 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4349 vk_format_get_first_non_void_channel(iview
->vk_format
));
4350 format
= radv_translate_colorformat(iview
->vk_format
);
4351 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4352 radv_finishme("Illegal color\n");
4353 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4354 endian
= radv_colorformat_endian_swap(format
);
4356 /* blend clamp should be set for all NORM/SRGB types */
4357 if (ntype
== V_028C70_NUMBER_UNORM
||
4358 ntype
== V_028C70_NUMBER_SNORM
||
4359 ntype
== V_028C70_NUMBER_SRGB
)
4362 /* set blend bypass according to docs if SINT/UINT or
4363 8/24 COLOR variants */
4364 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4365 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4366 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4371 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4372 (format
== V_028C70_COLOR_8
||
4373 format
== V_028C70_COLOR_8_8
||
4374 format
== V_028C70_COLOR_8_8_8_8
))
4375 ->color_is_int8
= true;
4377 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4378 S_028C70_COMP_SWAP(swap
) |
4379 S_028C70_BLEND_CLAMP(blend_clamp
) |
4380 S_028C70_BLEND_BYPASS(blend_bypass
) |
4381 S_028C70_SIMPLE_FLOAT(1) |
4382 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4383 ntype
!= V_028C70_NUMBER_SNORM
&&
4384 ntype
!= V_028C70_NUMBER_SRGB
&&
4385 format
!= V_028C70_COLOR_8_24
&&
4386 format
!= V_028C70_COLOR_24_8
) |
4387 S_028C70_NUMBER_TYPE(ntype
) |
4388 S_028C70_ENDIAN(endian
);
4389 if (radv_image_has_fmask(iview
->image
)) {
4390 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4391 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4392 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4393 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4397 if (radv_image_has_cmask(iview
->image
) &&
4398 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4399 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4401 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4402 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4404 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4406 /* This must be set for fast clear to work without FMASK. */
4407 if (!radv_image_has_fmask(iview
->image
) &&
4408 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4409 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4410 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4413 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4414 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4416 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4417 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4418 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4419 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4421 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
4422 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4423 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4424 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4425 S_028C68_MIP0_HEIGHT(height
- 1) |
4426 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4431 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4432 struct radv_image_view
*iview
)
4434 unsigned max_zplanes
= 0;
4436 assert(radv_image_is_tc_compat_htile(iview
->image
));
4438 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4439 /* Default value for 32-bit depth surfaces. */
4442 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4443 iview
->image
->info
.samples
> 1)
4446 max_zplanes
= max_zplanes
+ 1;
4448 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4449 /* Do not enable Z plane compression for 16-bit depth
4450 * surfaces because isn't supported on GFX8. Only
4451 * 32-bit depth surfaces are supported by the hardware.
4452 * This allows to maintain shader compatibility and to
4453 * reduce the number of depth decompressions.
4457 if (iview
->image
->info
.samples
<= 1)
4459 else if (iview
->image
->info
.samples
<= 4)
4470 radv_initialise_ds_surface(struct radv_device
*device
,
4471 struct radv_ds_buffer_info
*ds
,
4472 struct radv_image_view
*iview
)
4474 unsigned level
= iview
->base_mip
;
4475 unsigned format
, stencil_format
;
4476 uint64_t va
, s_offs
, z_offs
;
4477 bool stencil_only
= false;
4478 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4479 const struct radeon_surf
*surf
= &plane
->surface
;
4481 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4483 memset(ds
, 0, sizeof(*ds
));
4484 switch (iview
->image
->vk_format
) {
4485 case VK_FORMAT_D24_UNORM_S8_UINT
:
4486 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4487 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4488 ds
->offset_scale
= 2.0f
;
4490 case VK_FORMAT_D16_UNORM
:
4491 case VK_FORMAT_D16_UNORM_S8_UINT
:
4492 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4493 ds
->offset_scale
= 4.0f
;
4495 case VK_FORMAT_D32_SFLOAT
:
4496 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4497 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4498 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4499 ds
->offset_scale
= 1.0f
;
4501 case VK_FORMAT_S8_UINT
:
4502 stencil_only
= true;
4508 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4509 stencil_format
= surf
->has_stencil
?
4510 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4512 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4513 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4514 S_028008_SLICE_MAX(max_slice
);
4516 ds
->db_htile_data_base
= 0;
4517 ds
->db_htile_surface
= 0;
4519 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4520 s_offs
= z_offs
= va
;
4522 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4523 assert(surf
->u
.gfx9
.surf_offset
== 0);
4524 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4526 ds
->db_z_info
= S_028038_FORMAT(format
) |
4527 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4528 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4529 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4530 S_028038_ZRANGE_PRECISION(1);
4531 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4532 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4534 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4535 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4536 ds
->db_depth_view
|= S_028008_MIPID(level
);
4538 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4539 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4541 if (radv_htile_enabled(iview
->image
, level
)) {
4542 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4544 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4545 unsigned max_zplanes
=
4546 radv_calc_decompress_on_z_planes(device
, iview
);
4548 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4549 S_028038_ITERATE_FLUSH(1);
4550 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4553 if (!surf
->has_stencil
)
4554 /* Use all of the htile_buffer for depth if there's no stencil. */
4555 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4556 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4557 iview
->image
->htile_offset
;
4558 ds
->db_htile_data_base
= va
>> 8;
4559 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4560 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
) |
4561 S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4564 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4567 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4569 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4570 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4572 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4573 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4574 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4576 if (iview
->image
->info
.samples
> 1)
4577 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4579 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4580 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4581 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4582 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4583 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4584 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4585 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4586 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4589 tile_mode
= stencil_tile_mode
;
4591 ds
->db_depth_info
|=
4592 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4593 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4594 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4595 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4596 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4597 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4598 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4599 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4601 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4602 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4603 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4604 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4606 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4609 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4610 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4611 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4613 if (radv_htile_enabled(iview
->image
, level
)) {
4614 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4616 if (!surf
->has_stencil
&&
4617 !radv_image_is_tc_compat_htile(iview
->image
))
4618 /* Use all of the htile_buffer for depth if there's no stencil. */
4619 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4621 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4622 iview
->image
->htile_offset
;
4623 ds
->db_htile_data_base
= va
>> 8;
4624 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4626 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4627 unsigned max_zplanes
=
4628 radv_calc_decompress_on_z_planes(device
, iview
);
4630 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4631 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4636 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4637 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4640 VkResult
radv_CreateFramebuffer(
4642 const VkFramebufferCreateInfo
* pCreateInfo
,
4643 const VkAllocationCallbacks
* pAllocator
,
4644 VkFramebuffer
* pFramebuffer
)
4646 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4647 struct radv_framebuffer
*framebuffer
;
4649 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4651 size_t size
= sizeof(*framebuffer
) +
4652 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4653 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4654 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4655 if (framebuffer
== NULL
)
4656 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4658 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4659 framebuffer
->width
= pCreateInfo
->width
;
4660 framebuffer
->height
= pCreateInfo
->height
;
4661 framebuffer
->layers
= pCreateInfo
->layers
;
4662 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4663 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4664 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4665 framebuffer
->attachments
[i
].attachment
= iview
;
4666 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4667 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4669 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4671 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4672 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4673 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4676 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4680 void radv_DestroyFramebuffer(
4683 const VkAllocationCallbacks
* pAllocator
)
4685 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4686 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4690 vk_free2(&device
->alloc
, pAllocator
, fb
);
4693 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4695 switch (address_mode
) {
4696 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4697 return V_008F30_SQ_TEX_WRAP
;
4698 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4699 return V_008F30_SQ_TEX_MIRROR
;
4700 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4701 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4702 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4703 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4704 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4705 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4707 unreachable("illegal tex wrap mode");
4713 radv_tex_compare(VkCompareOp op
)
4716 case VK_COMPARE_OP_NEVER
:
4717 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4718 case VK_COMPARE_OP_LESS
:
4719 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4720 case VK_COMPARE_OP_EQUAL
:
4721 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4722 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4723 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4724 case VK_COMPARE_OP_GREATER
:
4725 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4726 case VK_COMPARE_OP_NOT_EQUAL
:
4727 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4728 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4729 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4730 case VK_COMPARE_OP_ALWAYS
:
4731 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4733 unreachable("illegal compare mode");
4739 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4742 case VK_FILTER_NEAREST
:
4743 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4744 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4745 case VK_FILTER_LINEAR
:
4746 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4747 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4748 case VK_FILTER_CUBIC_IMG
:
4750 fprintf(stderr
, "illegal texture filter");
4756 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4759 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4760 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4761 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4762 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4764 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4769 radv_tex_bordercolor(VkBorderColor bcolor
)
4772 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4773 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4774 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4775 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4776 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4777 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4778 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4779 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4780 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4788 radv_tex_aniso_filter(unsigned filter
)
4802 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4805 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4806 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4807 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4808 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4809 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4810 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4818 radv_get_max_anisotropy(struct radv_device
*device
,
4819 const VkSamplerCreateInfo
*pCreateInfo
)
4821 if (device
->force_aniso
>= 0)
4822 return device
->force_aniso
;
4824 if (pCreateInfo
->anisotropyEnable
&&
4825 pCreateInfo
->maxAnisotropy
> 1.0f
)
4826 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4832 radv_init_sampler(struct radv_device
*device
,
4833 struct radv_sampler
*sampler
,
4834 const VkSamplerCreateInfo
*pCreateInfo
)
4836 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4837 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4838 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= GFX8
);
4839 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4841 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4842 vk_find_struct_const(pCreateInfo
->pNext
,
4843 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4844 if (sampler_reduction
)
4845 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4847 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4848 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4849 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4850 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4851 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4852 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4853 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4854 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4855 S_008F30_DISABLE_CUBE_WRAP(0) |
4856 S_008F30_COMPAT_MODE(is_vi
) |
4857 S_008F30_FILTER_MODE(filter_mode
));
4858 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4859 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4860 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4861 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4862 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4863 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4864 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4865 S_008F38_MIP_POINT_PRECLAMP(0) |
4866 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
4867 S_008F38_FILTER_PREC_FIX(1) |
4868 S_008F38_ANISO_OVERRIDE(is_vi
));
4869 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4870 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4873 VkResult
radv_CreateSampler(
4875 const VkSamplerCreateInfo
* pCreateInfo
,
4876 const VkAllocationCallbacks
* pAllocator
,
4877 VkSampler
* pSampler
)
4879 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4880 struct radv_sampler
*sampler
;
4882 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
4883 vk_find_struct_const(pCreateInfo
->pNext
,
4884 SAMPLER_YCBCR_CONVERSION_INFO
);
4886 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4888 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4889 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4891 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4893 radv_init_sampler(device
, sampler
, pCreateInfo
);
4895 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
4896 *pSampler
= radv_sampler_to_handle(sampler
);
4901 void radv_DestroySampler(
4904 const VkAllocationCallbacks
* pAllocator
)
4906 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4907 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4911 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4914 /* vk_icd.h does not declare this function, so we declare it here to
4915 * suppress Wmissing-prototypes.
4917 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4918 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4920 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4921 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4923 /* For the full details on loader interface versioning, see
4924 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4925 * What follows is a condensed summary, to help you navigate the large and
4926 * confusing official doc.
4928 * - Loader interface v0 is incompatible with later versions. We don't
4931 * - In loader interface v1:
4932 * - The first ICD entrypoint called by the loader is
4933 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4935 * - The ICD must statically expose no other Vulkan symbol unless it is
4936 * linked with -Bsymbolic.
4937 * - Each dispatchable Vulkan handle created by the ICD must be
4938 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4939 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4940 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4941 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4942 * such loader-managed surfaces.
4944 * - Loader interface v2 differs from v1 in:
4945 * - The first ICD entrypoint called by the loader is
4946 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4947 * statically expose this entrypoint.
4949 * - Loader interface v3 differs from v2 in:
4950 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4951 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4952 * because the loader no longer does so.
4954 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
4958 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
4959 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
4962 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4963 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
4965 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
4967 /* At the moment, we support only the below handle types. */
4968 assert(pGetFdInfo
->handleType
==
4969 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4970 pGetFdInfo
->handleType
==
4971 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4973 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
4975 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4979 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
4980 VkExternalMemoryHandleTypeFlagBits handleType
,
4982 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
4984 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4986 switch (handleType
) {
4987 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
4988 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
4992 /* The valid usage section for this function says:
4994 * "handleType must not be one of the handle types defined as
4997 * So opaque handle types fall into the default "unsupported" case.
4999 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5003 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5007 uint32_t syncobj_handle
= 0;
5008 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5010 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5013 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5015 *syncobj
= syncobj_handle
;
5021 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5025 /* If we create a syncobj we do it locally so that if we have an error, we don't
5026 * leave a syncobj in an undetermined state in the fence. */
5027 uint32_t syncobj_handle
= *syncobj
;
5028 if (!syncobj_handle
) {
5029 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5031 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5036 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5038 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5040 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5043 *syncobj
= syncobj_handle
;
5050 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5051 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5053 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5054 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5055 uint32_t *syncobj_dst
= NULL
;
5057 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5058 syncobj_dst
= &sem
->temp_syncobj
;
5060 syncobj_dst
= &sem
->syncobj
;
5063 switch(pImportSemaphoreFdInfo
->handleType
) {
5064 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5065 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5066 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5067 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5069 unreachable("Unhandled semaphore handle type");
5073 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5074 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5077 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5078 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5080 uint32_t syncobj_handle
;
5082 if (sem
->temp_syncobj
)
5083 syncobj_handle
= sem
->temp_syncobj
;
5085 syncobj_handle
= sem
->syncobj
;
5087 switch(pGetFdInfo
->handleType
) {
5088 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5089 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5091 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5092 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5094 if (sem
->temp_syncobj
) {
5095 close (sem
->temp_syncobj
);
5096 sem
->temp_syncobj
= 0;
5098 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5103 unreachable("Unhandled semaphore handle type");
5107 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5111 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5112 VkPhysicalDevice physicalDevice
,
5113 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5114 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5116 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5118 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5119 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5120 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5121 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5122 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5123 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5124 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5125 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5126 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5127 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5128 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5129 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5130 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5132 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5133 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5134 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5138 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5139 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5141 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5142 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5143 uint32_t *syncobj_dst
= NULL
;
5146 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5147 syncobj_dst
= &fence
->temp_syncobj
;
5149 syncobj_dst
= &fence
->syncobj
;
5152 switch(pImportFenceFdInfo
->handleType
) {
5153 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5154 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5155 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5156 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5158 unreachable("Unhandled fence handle type");
5162 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5163 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5166 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5167 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5169 uint32_t syncobj_handle
;
5171 if (fence
->temp_syncobj
)
5172 syncobj_handle
= fence
->temp_syncobj
;
5174 syncobj_handle
= fence
->syncobj
;
5176 switch(pGetFdInfo
->handleType
) {
5177 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5178 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5180 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5181 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5183 if (fence
->temp_syncobj
) {
5184 close (fence
->temp_syncobj
);
5185 fence
->temp_syncobj
= 0;
5187 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5192 unreachable("Unhandled fence handle type");
5196 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5200 void radv_GetPhysicalDeviceExternalFenceProperties(
5201 VkPhysicalDevice physicalDevice
,
5202 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5203 VkExternalFenceProperties
*pExternalFenceProperties
)
5205 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5207 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5208 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5209 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5210 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5211 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5212 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5213 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5215 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5216 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5217 pExternalFenceProperties
->externalFenceFeatures
= 0;
5222 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5223 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5224 const VkAllocationCallbacks
* pAllocator
,
5225 VkDebugReportCallbackEXT
* pCallback
)
5227 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5228 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5229 pCreateInfo
, pAllocator
, &instance
->alloc
,
5234 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5235 VkDebugReportCallbackEXT _callback
,
5236 const VkAllocationCallbacks
* pAllocator
)
5238 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5239 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5240 _callback
, pAllocator
, &instance
->alloc
);
5244 radv_DebugReportMessageEXT(VkInstance _instance
,
5245 VkDebugReportFlagsEXT flags
,
5246 VkDebugReportObjectTypeEXT objectType
,
5249 int32_t messageCode
,
5250 const char* pLayerPrefix
,
5251 const char* pMessage
)
5253 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5254 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5255 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5259 radv_GetDeviceGroupPeerMemoryFeatures(
5262 uint32_t localDeviceIndex
,
5263 uint32_t remoteDeviceIndex
,
5264 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5266 assert(localDeviceIndex
== remoteDeviceIndex
);
5268 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5269 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5270 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5271 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5274 static const VkTimeDomainEXT radv_time_domains
[] = {
5275 VK_TIME_DOMAIN_DEVICE_EXT
,
5276 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5277 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5280 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5281 VkPhysicalDevice physicalDevice
,
5282 uint32_t *pTimeDomainCount
,
5283 VkTimeDomainEXT
*pTimeDomains
)
5286 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5288 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5289 vk_outarray_append(&out
, i
) {
5290 *i
= radv_time_domains
[d
];
5294 return vk_outarray_status(&out
);
5298 radv_clock_gettime(clockid_t clock_id
)
5300 struct timespec current
;
5303 ret
= clock_gettime(clock_id
, ¤t
);
5304 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5305 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5309 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5312 VkResult
radv_GetCalibratedTimestampsEXT(
5314 uint32_t timestampCount
,
5315 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5316 uint64_t *pTimestamps
,
5317 uint64_t *pMaxDeviation
)
5319 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5320 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5322 uint64_t begin
, end
;
5323 uint64_t max_clock_period
= 0;
5325 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5327 for (d
= 0; d
< timestampCount
; d
++) {
5328 switch (pTimestampInfos
[d
].timeDomain
) {
5329 case VK_TIME_DOMAIN_DEVICE_EXT
:
5330 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5332 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5333 max_clock_period
= MAX2(max_clock_period
, device_period
);
5335 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5336 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5337 max_clock_period
= MAX2(max_clock_period
, 1);
5340 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5341 pTimestamps
[d
] = begin
;
5349 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5352 * The maximum deviation is the sum of the interval over which we
5353 * perform the sampling and the maximum period of any sampled
5354 * clock. That's because the maximum skew between any two sampled
5355 * clock edges is when the sampled clock with the largest period is
5356 * sampled at the end of that period but right at the beginning of the
5357 * sampling interval and some other clock is sampled right at the
5358 * begining of its sampling period and right at the end of the
5359 * sampling interval. Let's assume the GPU has the longest clock
5360 * period and that the application is sampling GPU and monotonic:
5363 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5364 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5368 * GPU -----_____-----_____-----_____-----_____
5371 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5372 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5374 * Interval <----------------->
5375 * Deviation <-------------------------->
5379 * m = read(monotonic) 2
5382 * We round the sample interval up by one tick to cover sampling error
5383 * in the interval clock
5386 uint64_t sample_interval
= end
- begin
+ 1;
5388 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5393 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5394 VkPhysicalDevice physicalDevice
,
5395 VkSampleCountFlagBits samples
,
5396 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5398 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5399 VK_SAMPLE_COUNT_4_BIT
|
5400 VK_SAMPLE_COUNT_8_BIT
)) {
5401 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5403 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };