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radv: fix possible stack corruption
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 {
88 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
89 .specVersion = 1,
90 },
91 };
92
93 static const VkExtensionProperties common_device_extensions[] = {
94 {
95 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
100 .specVersion = 1,
101 },
102 {
103 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
116 .specVersion = 68,
117 },
118 {
119 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 {
123 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
124 .specVersion = 1,
125 },
126 {
127 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
128 .specVersion = 1,
129 },
130 };
131
132 static VkResult
133 radv_extensions_register(struct radv_instance *instance,
134 struct radv_extensions *extensions,
135 const VkExtensionProperties *new_ext,
136 uint32_t num_ext)
137 {
138 size_t new_size;
139 VkExtensionProperties *new_ptr;
140
141 assert(new_ext && num_ext > 0);
142
143 if (!new_ext)
144 return VK_ERROR_INITIALIZATION_FAILED;
145
146 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
147 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
148 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
149
150 /* Old array continues to be valid, update nothing */
151 if (!new_ptr)
152 return VK_ERROR_OUT_OF_HOST_MEMORY;
153
154 memcpy(&new_ptr[extensions->num_ext], new_ext,
155 num_ext * sizeof(VkExtensionProperties));
156 extensions->ext_array = new_ptr;
157 extensions->num_ext += num_ext;
158
159 return VK_SUCCESS;
160 }
161
162 static void
163 radv_extensions_finish(struct radv_instance *instance,
164 struct radv_extensions *extensions)
165 {
166 assert(extensions);
167
168 if (!extensions)
169 radv_loge("Attemted to free invalid extension struct\n");
170
171 if (extensions->ext_array)
172 vk_free(&instance->alloc, extensions->ext_array);
173 }
174
175 static bool
176 is_extension_enabled(const VkExtensionProperties *extensions,
177 size_t num_ext,
178 const char *name)
179 {
180 assert(extensions && name);
181
182 for (uint32_t i = 0; i < num_ext; i++) {
183 if (strcmp(name, extensions[i].extensionName) == 0)
184 return true;
185 }
186
187 return false;
188 }
189
190 static VkResult
191 radv_physical_device_init(struct radv_physical_device *device,
192 struct radv_instance *instance,
193 const char *path)
194 {
195 VkResult result;
196 drmVersionPtr version;
197 int fd;
198
199 fd = open(path, O_RDWR | O_CLOEXEC);
200 if (fd < 0)
201 return VK_ERROR_INCOMPATIBLE_DRIVER;
202
203 version = drmGetVersion(fd);
204 if (!version) {
205 close(fd);
206 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
207 "failed to get version %s: %m", path);
208 }
209
210 if (strcmp(version->name, "amdgpu")) {
211 drmFreeVersion(version);
212 close(fd);
213 return VK_ERROR_INCOMPATIBLE_DRIVER;
214 }
215 drmFreeVersion(version);
216
217 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 device->instance = instance;
219 assert(strlen(path) < ARRAY_SIZE(device->path));
220 strncpy(device->path, path, ARRAY_SIZE(device->path));
221
222 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
223 if (!device->ws) {
224 result = VK_ERROR_INCOMPATIBLE_DRIVER;
225 goto fail;
226 }
227
228 device->local_fd = fd;
229 device->ws->query_info(device->ws, &device->rad_info);
230 result = radv_init_wsi(device);
231 if (result != VK_SUCCESS) {
232 device->ws->destroy(device->ws);
233 goto fail;
234 }
235
236 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
237 radv_finish_wsi(device);
238 device->ws->destroy(device->ws);
239 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
240 "cannot generate UUID");
241 goto fail;
242 }
243
244 result = radv_extensions_register(instance,
245 &device->extensions,
246 common_device_extensions,
247 ARRAY_SIZE(common_device_extensions));
248 if (result != VK_SUCCESS)
249 goto fail;
250
251 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 device->name = device->rad_info.name;
253
254 return VK_SUCCESS;
255
256 fail:
257 close(fd);
258 return result;
259 }
260
261 static void
262 radv_physical_device_finish(struct radv_physical_device *device)
263 {
264 radv_extensions_finish(device->instance, &device->extensions);
265 radv_finish_wsi(device);
266 device->ws->destroy(device->ws);
267 close(device->local_fd);
268 }
269
270
271 static void *
272 default_alloc_func(void *pUserData, size_t size, size_t align,
273 VkSystemAllocationScope allocationScope)
274 {
275 return malloc(size);
276 }
277
278 static void *
279 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
280 size_t align, VkSystemAllocationScope allocationScope)
281 {
282 return realloc(pOriginal, size);
283 }
284
285 static void
286 default_free_func(void *pUserData, void *pMemory)
287 {
288 free(pMemory);
289 }
290
291 static const VkAllocationCallbacks default_alloc = {
292 .pUserData = NULL,
293 .pfnAllocation = default_alloc_func,
294 .pfnReallocation = default_realloc_func,
295 .pfnFree = default_free_func,
296 };
297
298 static const struct debug_control radv_debug_options[] = {
299 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
300 {"nodcc", RADV_DEBUG_NO_DCC},
301 {"shaders", RADV_DEBUG_DUMP_SHADERS},
302 {"nocache", RADV_DEBUG_NO_CACHE},
303 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
304 {"nohiz", RADV_DEBUG_NO_HIZ},
305 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
306 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
307 {"allbos", RADV_DEBUG_ALL_BOS},
308 {"noibs", RADV_DEBUG_NO_IBS},
309 {NULL, 0}
310 };
311
312 VkResult radv_CreateInstance(
313 const VkInstanceCreateInfo* pCreateInfo,
314 const VkAllocationCallbacks* pAllocator,
315 VkInstance* pInstance)
316 {
317 struct radv_instance *instance;
318
319 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
320
321 uint32_t client_version;
322 if (pCreateInfo->pApplicationInfo &&
323 pCreateInfo->pApplicationInfo->apiVersion != 0) {
324 client_version = pCreateInfo->pApplicationInfo->apiVersion;
325 } else {
326 client_version = VK_MAKE_VERSION(1, 0, 0);
327 }
328
329 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
330 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
331 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
332 "Client requested version %d.%d.%d",
333 VK_VERSION_MAJOR(client_version),
334 VK_VERSION_MINOR(client_version),
335 VK_VERSION_PATCH(client_version));
336 }
337
338 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
339 if (!is_extension_enabled(instance_extensions,
340 ARRAY_SIZE(instance_extensions),
341 pCreateInfo->ppEnabledExtensionNames[i]))
342 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
343 }
344
345 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
346 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
347 if (!instance)
348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
349
350 memset(instance, 0, sizeof(*instance));
351
352 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
353
354 if (pAllocator)
355 instance->alloc = *pAllocator;
356 else
357 instance->alloc = default_alloc;
358
359 instance->apiVersion = client_version;
360 instance->physicalDeviceCount = -1;
361
362 _mesa_locale_init();
363
364 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
365
366 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
367 radv_debug_options);
368
369 *pInstance = radv_instance_to_handle(instance);
370
371 return VK_SUCCESS;
372 }
373
374 void radv_DestroyInstance(
375 VkInstance _instance,
376 const VkAllocationCallbacks* pAllocator)
377 {
378 RADV_FROM_HANDLE(radv_instance, instance, _instance);
379
380 if (!instance)
381 return;
382
383 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
384 radv_physical_device_finish(instance->physicalDevices + i);
385 }
386
387 VG(VALGRIND_DESTROY_MEMPOOL(instance));
388
389 _mesa_locale_fini();
390
391 vk_free(&instance->alloc, instance);
392 }
393
394 static VkResult
395 radv_enumerate_devices(struct radv_instance *instance)
396 {
397 /* TODO: Check for more devices ? */
398 drmDevicePtr devices[8];
399 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
400 int max_devices;
401
402 instance->physicalDeviceCount = 0;
403
404 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
405 if (max_devices < 1)
406 return VK_ERROR_INCOMPATIBLE_DRIVER;
407
408 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
409 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
410 devices[i]->bustype == DRM_BUS_PCI &&
411 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
412
413 result = radv_physical_device_init(instance->physicalDevices +
414 instance->physicalDeviceCount,
415 instance,
416 devices[i]->nodes[DRM_NODE_RENDER]);
417 if (result == VK_SUCCESS)
418 ++instance->physicalDeviceCount;
419 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
420 return result;
421 }
422 }
423 return result;
424 }
425
426 VkResult radv_EnumeratePhysicalDevices(
427 VkInstance _instance,
428 uint32_t* pPhysicalDeviceCount,
429 VkPhysicalDevice* pPhysicalDevices)
430 {
431 RADV_FROM_HANDLE(radv_instance, instance, _instance);
432 VkResult result;
433
434 if (instance->physicalDeviceCount < 0) {
435 result = radv_enumerate_devices(instance);
436 if (result != VK_SUCCESS &&
437 result != VK_ERROR_INCOMPATIBLE_DRIVER)
438 return result;
439 }
440
441 if (!pPhysicalDevices) {
442 *pPhysicalDeviceCount = instance->physicalDeviceCount;
443 } else {
444 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
445 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
446 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
447 }
448
449 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
450 : VK_SUCCESS;
451 }
452
453 void radv_GetPhysicalDeviceFeatures(
454 VkPhysicalDevice physicalDevice,
455 VkPhysicalDeviceFeatures* pFeatures)
456 {
457 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
458
459 memset(pFeatures, 0, sizeof(*pFeatures));
460
461 *pFeatures = (VkPhysicalDeviceFeatures) {
462 .robustBufferAccess = true,
463 .fullDrawIndexUint32 = true,
464 .imageCubeArray = true,
465 .independentBlend = true,
466 .geometryShader = true,
467 .tessellationShader = true,
468 .sampleRateShading = false,
469 .dualSrcBlend = true,
470 .logicOp = true,
471 .multiDrawIndirect = true,
472 .drawIndirectFirstInstance = true,
473 .depthClamp = true,
474 .depthBiasClamp = true,
475 .fillModeNonSolid = true,
476 .depthBounds = true,
477 .wideLines = true,
478 .largePoints = true,
479 .alphaToOne = true,
480 .multiViewport = true,
481 .samplerAnisotropy = true,
482 .textureCompressionETC2 = false,
483 .textureCompressionASTC_LDR = false,
484 .textureCompressionBC = true,
485 .occlusionQueryPrecise = true,
486 .pipelineStatisticsQuery = true,
487 .vertexPipelineStoresAndAtomics = true,
488 .fragmentStoresAndAtomics = true,
489 .shaderTessellationAndGeometryPointSize = true,
490 .shaderImageGatherExtended = true,
491 .shaderStorageImageExtendedFormats = true,
492 .shaderStorageImageMultisample = false,
493 .shaderUniformBufferArrayDynamicIndexing = true,
494 .shaderSampledImageArrayDynamicIndexing = true,
495 .shaderStorageBufferArrayDynamicIndexing = true,
496 .shaderStorageImageArrayDynamicIndexing = true,
497 .shaderStorageImageReadWithoutFormat = true,
498 .shaderStorageImageWriteWithoutFormat = true,
499 .shaderClipDistance = true,
500 .shaderCullDistance = true,
501 .shaderFloat64 = true,
502 .shaderInt64 = false,
503 .shaderInt16 = false,
504 .sparseBinding = true,
505 .variableMultisampleRate = true,
506 .inheritedQueries = true,
507 };
508 }
509
510 void radv_GetPhysicalDeviceFeatures2KHR(
511 VkPhysicalDevice physicalDevice,
512 VkPhysicalDeviceFeatures2KHR *pFeatures)
513 {
514 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
515 }
516
517 static uint32_t radv_get_driver_version()
518 {
519 const char *minor_string = strchr(VERSION, '.');
520 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
521 int major = atoi(VERSION);
522 int minor = minor_string ? atoi(minor_string + 1) : 0;
523 int patch = patch_string ? atoi(patch_string + 1) : 0;
524 if (strstr(VERSION, "devel")) {
525 if (patch == 0) {
526 patch = 99;
527 if (minor == 0) {
528 minor = 99;
529 --major;
530 } else
531 --minor;
532 } else
533 --patch;
534 }
535 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
536 return version;
537 }
538
539 void radv_GetPhysicalDeviceProperties(
540 VkPhysicalDevice physicalDevice,
541 VkPhysicalDeviceProperties* pProperties)
542 {
543 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
544 VkSampleCountFlags sample_counts = 0xf;
545
546 /* make sure that the entire descriptor set is addressable with a signed
547 * 32-bit int. So the sum of all limits scaled by descriptor size has to
548 * be at most 2 GiB. the combined image & samples object count as one of
549 * both. This limit is for the pipeline layout, not for the set layout, but
550 * there is no set limit, so we just set a pipeline limit. I don't think
551 * any app is going to hit this soon. */
552 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
553 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
554 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
555 32 /* sampler, largest when combined with image */ +
556 64 /* sampled image */ +
557 64 /* storage image */);
558
559 VkPhysicalDeviceLimits limits = {
560 .maxImageDimension1D = (1 << 14),
561 .maxImageDimension2D = (1 << 14),
562 .maxImageDimension3D = (1 << 11),
563 .maxImageDimensionCube = (1 << 14),
564 .maxImageArrayLayers = (1 << 11),
565 .maxTexelBufferElements = 128 * 1024 * 1024,
566 .maxUniformBufferRange = UINT32_MAX,
567 .maxStorageBufferRange = UINT32_MAX,
568 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
569 .maxMemoryAllocationCount = UINT32_MAX,
570 .maxSamplerAllocationCount = 64 * 1024,
571 .bufferImageGranularity = 64, /* A cache line */
572 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
573 .maxBoundDescriptorSets = MAX_SETS,
574 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
575 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
576 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
577 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
578 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
579 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
580 .maxPerStageResources = max_descriptor_set_size,
581 .maxDescriptorSetSamplers = max_descriptor_set_size,
582 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
583 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
584 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
585 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
586 .maxDescriptorSetSampledImages = max_descriptor_set_size,
587 .maxDescriptorSetStorageImages = max_descriptor_set_size,
588 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
589 .maxVertexInputAttributes = 32,
590 .maxVertexInputBindings = 32,
591 .maxVertexInputAttributeOffset = 2047,
592 .maxVertexInputBindingStride = 2048,
593 .maxVertexOutputComponents = 128,
594 .maxTessellationGenerationLevel = 64,
595 .maxTessellationPatchSize = 32,
596 .maxTessellationControlPerVertexInputComponents = 128,
597 .maxTessellationControlPerVertexOutputComponents = 128,
598 .maxTessellationControlPerPatchOutputComponents = 120,
599 .maxTessellationControlTotalOutputComponents = 4096,
600 .maxTessellationEvaluationInputComponents = 128,
601 .maxTessellationEvaluationOutputComponents = 128,
602 .maxGeometryShaderInvocations = 127,
603 .maxGeometryInputComponents = 64,
604 .maxGeometryOutputComponents = 128,
605 .maxGeometryOutputVertices = 256,
606 .maxGeometryTotalOutputComponents = 1024,
607 .maxFragmentInputComponents = 128,
608 .maxFragmentOutputAttachments = 8,
609 .maxFragmentDualSrcAttachments = 1,
610 .maxFragmentCombinedOutputResources = 8,
611 .maxComputeSharedMemorySize = 32768,
612 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
613 .maxComputeWorkGroupInvocations = 2048,
614 .maxComputeWorkGroupSize = {
615 2048,
616 2048,
617 2048
618 },
619 .subPixelPrecisionBits = 4 /* FIXME */,
620 .subTexelPrecisionBits = 4 /* FIXME */,
621 .mipmapPrecisionBits = 4 /* FIXME */,
622 .maxDrawIndexedIndexValue = UINT32_MAX,
623 .maxDrawIndirectCount = UINT32_MAX,
624 .maxSamplerLodBias = 16,
625 .maxSamplerAnisotropy = 16,
626 .maxViewports = MAX_VIEWPORTS,
627 .maxViewportDimensions = { (1 << 14), (1 << 14) },
628 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
629 .viewportSubPixelBits = 13, /* We take a float? */
630 .minMemoryMapAlignment = 4096, /* A page */
631 .minTexelBufferOffsetAlignment = 1,
632 .minUniformBufferOffsetAlignment = 4,
633 .minStorageBufferOffsetAlignment = 4,
634 .minTexelOffset = -32,
635 .maxTexelOffset = 31,
636 .minTexelGatherOffset = -32,
637 .maxTexelGatherOffset = 31,
638 .minInterpolationOffset = -2,
639 .maxInterpolationOffset = 2,
640 .subPixelInterpolationOffsetBits = 8,
641 .maxFramebufferWidth = (1 << 14),
642 .maxFramebufferHeight = (1 << 14),
643 .maxFramebufferLayers = (1 << 10),
644 .framebufferColorSampleCounts = sample_counts,
645 .framebufferDepthSampleCounts = sample_counts,
646 .framebufferStencilSampleCounts = sample_counts,
647 .framebufferNoAttachmentsSampleCounts = sample_counts,
648 .maxColorAttachments = MAX_RTS,
649 .sampledImageColorSampleCounts = sample_counts,
650 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
651 .sampledImageDepthSampleCounts = sample_counts,
652 .sampledImageStencilSampleCounts = sample_counts,
653 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
654 .maxSampleMaskWords = 1,
655 .timestampComputeAndGraphics = true,
656 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
657 .maxClipDistances = 8,
658 .maxCullDistances = 8,
659 .maxCombinedClipAndCullDistances = 8,
660 .discreteQueuePriorities = 1,
661 .pointSizeRange = { 0.125, 255.875 },
662 .lineWidthRange = { 0.0, 7.9921875 },
663 .pointSizeGranularity = (1.0 / 8.0),
664 .lineWidthGranularity = (1.0 / 128.0),
665 .strictLines = false, /* FINISHME */
666 .standardSampleLocations = true,
667 .optimalBufferCopyOffsetAlignment = 128,
668 .optimalBufferCopyRowPitchAlignment = 128,
669 .nonCoherentAtomSize = 64,
670 };
671
672 *pProperties = (VkPhysicalDeviceProperties) {
673 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
674 .driverVersion = radv_get_driver_version(),
675 .vendorID = 0x1002,
676 .deviceID = pdevice->rad_info.pci_id,
677 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
678 .limits = limits,
679 .sparseProperties = {0},
680 };
681
682 strcpy(pProperties->deviceName, pdevice->name);
683 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
684 }
685
686 void radv_GetPhysicalDeviceProperties2KHR(
687 VkPhysicalDevice physicalDevice,
688 VkPhysicalDeviceProperties2KHR *pProperties)
689 {
690 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
691
692 vk_foreach_struct(ext, pProperties->pNext) {
693 switch (ext->sType) {
694 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
695 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
696 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
697 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
698 break;
699 }
700 default:
701 break;
702 }
703 }
704 }
705
706 static void radv_get_physical_device_queue_family_properties(
707 struct radv_physical_device* pdevice,
708 uint32_t* pCount,
709 VkQueueFamilyProperties** pQueueFamilyProperties)
710 {
711 int num_queue_families = 1;
712 int idx;
713 if (pdevice->rad_info.compute_rings > 0 &&
714 pdevice->rad_info.chip_class >= CIK &&
715 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
716 num_queue_families++;
717
718 if (pQueueFamilyProperties == NULL) {
719 *pCount = num_queue_families;
720 return;
721 }
722
723 if (!*pCount)
724 return;
725
726 idx = 0;
727 if (*pCount >= 1) {
728 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
729 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
730 VK_QUEUE_COMPUTE_BIT |
731 VK_QUEUE_TRANSFER_BIT |
732 VK_QUEUE_SPARSE_BINDING_BIT,
733 .queueCount = 1,
734 .timestampValidBits = 64,
735 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
736 };
737 idx++;
738 }
739
740 if (pdevice->rad_info.compute_rings > 0 &&
741 pdevice->rad_info.chip_class >= CIK &&
742 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
743 if (*pCount > idx) {
744 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
745 .queueFlags = VK_QUEUE_COMPUTE_BIT |
746 VK_QUEUE_TRANSFER_BIT |
747 VK_QUEUE_SPARSE_BINDING_BIT,
748 .queueCount = pdevice->rad_info.compute_rings,
749 .timestampValidBits = 64,
750 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
751 };
752 idx++;
753 }
754 }
755 *pCount = idx;
756 }
757
758 void radv_GetPhysicalDeviceQueueFamilyProperties(
759 VkPhysicalDevice physicalDevice,
760 uint32_t* pCount,
761 VkQueueFamilyProperties* pQueueFamilyProperties)
762 {
763 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
764 if (!pQueueFamilyProperties) {
765 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
766 return;
767 }
768 VkQueueFamilyProperties *properties[] = {
769 pQueueFamilyProperties + 0,
770 pQueueFamilyProperties + 1,
771 pQueueFamilyProperties + 2,
772 };
773 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
774 assert(*pCount <= 3);
775 }
776
777 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
778 VkPhysicalDevice physicalDevice,
779 uint32_t* pCount,
780 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
781 {
782 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
783 if (!pQueueFamilyProperties) {
784 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
785 return;
786 }
787 VkQueueFamilyProperties *properties[] = {
788 &pQueueFamilyProperties[0].queueFamilyProperties,
789 &pQueueFamilyProperties[1].queueFamilyProperties,
790 &pQueueFamilyProperties[2].queueFamilyProperties,
791 };
792 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
793 assert(*pCount <= 3);
794 }
795
796 void radv_GetPhysicalDeviceMemoryProperties(
797 VkPhysicalDevice physicalDevice,
798 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
799 {
800 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
801
802 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
803
804 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
805 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
806 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
807 .heapIndex = RADV_MEM_HEAP_VRAM,
808 };
809 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
810 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
811 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
812 .heapIndex = RADV_MEM_HEAP_GTT,
813 };
814 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
815 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
816 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
817 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
818 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
819 };
820 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
821 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
822 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
823 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
824 .heapIndex = RADV_MEM_HEAP_GTT,
825 };
826
827 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
828
829 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
830 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
831 .size = physical_device->rad_info.vram_size -
832 physical_device->rad_info.visible_vram_size,
833 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
834 };
835 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
836 .size = physical_device->rad_info.visible_vram_size,
837 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
838 };
839 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
840 .size = physical_device->rad_info.gart_size,
841 .flags = 0,
842 };
843 }
844
845 void radv_GetPhysicalDeviceMemoryProperties2KHR(
846 VkPhysicalDevice physicalDevice,
847 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
848 {
849 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
850 &pMemoryProperties->memoryProperties);
851 }
852
853 static int
854 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
855 int queue_family_index, int idx)
856 {
857 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
858 queue->device = device;
859 queue->queue_family_index = queue_family_index;
860 queue->queue_idx = idx;
861
862 queue->hw_ctx = device->ws->ctx_create(device->ws);
863 if (!queue->hw_ctx)
864 return VK_ERROR_OUT_OF_HOST_MEMORY;
865
866 return VK_SUCCESS;
867 }
868
869 static void
870 radv_queue_finish(struct radv_queue *queue)
871 {
872 if (queue->hw_ctx)
873 queue->device->ws->ctx_destroy(queue->hw_ctx);
874
875 if (queue->initial_preamble_cs)
876 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
877 if (queue->continue_preamble_cs)
878 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
879 if (queue->descriptor_bo)
880 queue->device->ws->buffer_destroy(queue->descriptor_bo);
881 if (queue->scratch_bo)
882 queue->device->ws->buffer_destroy(queue->scratch_bo);
883 if (queue->esgs_ring_bo)
884 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
885 if (queue->gsvs_ring_bo)
886 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
887 if (queue->tess_factor_ring_bo)
888 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
889 if (queue->tess_offchip_ring_bo)
890 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
891 if (queue->compute_scratch_bo)
892 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
893 }
894
895 static void
896 radv_device_init_gs_info(struct radv_device *device)
897 {
898 switch (device->physical_device->rad_info.family) {
899 case CHIP_OLAND:
900 case CHIP_HAINAN:
901 case CHIP_KAVERI:
902 case CHIP_KABINI:
903 case CHIP_MULLINS:
904 case CHIP_ICELAND:
905 case CHIP_CARRIZO:
906 case CHIP_STONEY:
907 device->gs_table_depth = 16;
908 return;
909 case CHIP_TAHITI:
910 case CHIP_PITCAIRN:
911 case CHIP_VERDE:
912 case CHIP_BONAIRE:
913 case CHIP_HAWAII:
914 case CHIP_TONGA:
915 case CHIP_FIJI:
916 case CHIP_POLARIS10:
917 case CHIP_POLARIS11:
918 device->gs_table_depth = 32;
919 return;
920 default:
921 unreachable("unknown GPU");
922 }
923 }
924
925 VkResult radv_CreateDevice(
926 VkPhysicalDevice physicalDevice,
927 const VkDeviceCreateInfo* pCreateInfo,
928 const VkAllocationCallbacks* pAllocator,
929 VkDevice* pDevice)
930 {
931 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
932 VkResult result;
933 struct radv_device *device;
934
935 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
936 if (!is_extension_enabled(physical_device->extensions.ext_array,
937 physical_device->extensions.num_ext,
938 pCreateInfo->ppEnabledExtensionNames[i]))
939 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
940 }
941
942 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
943 sizeof(*device), 8,
944 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
945 if (!device)
946 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
947
948 memset(device, 0, sizeof(*device));
949
950 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
951 device->instance = physical_device->instance;
952 device->physical_device = physical_device;
953
954 device->debug_flags = device->instance->debug_flags;
955
956 device->ws = physical_device->ws;
957 if (pAllocator)
958 device->alloc = *pAllocator;
959 else
960 device->alloc = physical_device->instance->alloc;
961
962 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
963 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
964 uint32_t qfi = queue_create->queueFamilyIndex;
965
966 device->queues[qfi] = vk_alloc(&device->alloc,
967 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
968 if (!device->queues[qfi]) {
969 result = VK_ERROR_OUT_OF_HOST_MEMORY;
970 goto fail;
971 }
972
973 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
974
975 device->queue_count[qfi] = queue_create->queueCount;
976
977 for (unsigned q = 0; q < queue_create->queueCount; q++) {
978 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
979 if (result != VK_SUCCESS)
980 goto fail;
981 }
982 }
983
984 #if HAVE_LLVM < 0x0400
985 device->llvm_supports_spill = false;
986 #else
987 device->llvm_supports_spill = true;
988 #endif
989
990 /* The maximum number of scratch waves. Scratch space isn't divided
991 * evenly between CUs. The number is only a function of the number of CUs.
992 * We can decrease the constant to decrease the scratch buffer size.
993 *
994 * sctx->scratch_waves must be >= the maximum posible size of
995 * 1 threadgroup, so that the hw doesn't hang from being unable
996 * to start any.
997 *
998 * The recommended value is 4 per CU at most. Higher numbers don't
999 * bring much benefit, but they still occupy chip resources (think
1000 * async compute). I've seen ~2% performance difference between 4 and 32.
1001 */
1002 uint32_t max_threads_per_block = 2048;
1003 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1004 max_threads_per_block / 64);
1005
1006 radv_device_init_gs_info(device);
1007
1008 device->tess_offchip_block_dw_size =
1009 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1010 device->has_distributed_tess =
1011 device->physical_device->rad_info.chip_class >= VI &&
1012 device->physical_device->rad_info.max_se >= 2;
1013
1014 result = radv_device_init_meta(device);
1015 if (result != VK_SUCCESS)
1016 goto fail;
1017
1018 radv_device_init_msaa(device);
1019
1020 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1021 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1022 switch (family) {
1023 case RADV_QUEUE_GENERAL:
1024 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1025 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1026 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1027 break;
1028 case RADV_QUEUE_COMPUTE:
1029 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1030 radeon_emit(device->empty_cs[family], 0);
1031 break;
1032 }
1033 device->ws->cs_finalize(device->empty_cs[family]);
1034
1035 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1036 switch (family) {
1037 case RADV_QUEUE_GENERAL:
1038 case RADV_QUEUE_COMPUTE:
1039 si_cs_emit_cache_flush(device->flush_cs[family],
1040 device->physical_device->rad_info.chip_class,
1041 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1042 RADV_CMD_FLAG_INV_ICACHE |
1043 RADV_CMD_FLAG_INV_SMEM_L1 |
1044 RADV_CMD_FLAG_INV_VMEM_L1 |
1045 RADV_CMD_FLAG_INV_GLOBAL_L2);
1046 break;
1047 }
1048 device->ws->cs_finalize(device->flush_cs[family]);
1049
1050 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1051 switch (family) {
1052 case RADV_QUEUE_GENERAL:
1053 case RADV_QUEUE_COMPUTE:
1054 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1055 device->physical_device->rad_info.chip_class,
1056 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1057 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1058 RADV_CMD_FLAG_INV_ICACHE |
1059 RADV_CMD_FLAG_INV_SMEM_L1 |
1060 RADV_CMD_FLAG_INV_VMEM_L1 |
1061 RADV_CMD_FLAG_INV_GLOBAL_L2);
1062 break;
1063 }
1064 device->ws->cs_finalize(device->flush_shader_cs[family]);
1065 }
1066
1067 if (getenv("RADV_TRACE_FILE")) {
1068 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1069 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1070 if (!device->trace_bo)
1071 goto fail;
1072
1073 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1074 if (!device->trace_id_ptr)
1075 goto fail;
1076 }
1077
1078 if (device->physical_device->rad_info.chip_class >= CIK)
1079 cik_create_gfx_config(device);
1080
1081 VkPipelineCacheCreateInfo ci;
1082 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1083 ci.pNext = NULL;
1084 ci.flags = 0;
1085 ci.pInitialData = NULL;
1086 ci.initialDataSize = 0;
1087 VkPipelineCache pc;
1088 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1089 &ci, NULL, &pc);
1090 if (result != VK_SUCCESS)
1091 goto fail;
1092
1093 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1094
1095 *pDevice = radv_device_to_handle(device);
1096 return VK_SUCCESS;
1097
1098 fail:
1099 if (device->trace_bo)
1100 device->ws->buffer_destroy(device->trace_bo);
1101
1102 if (device->gfx_init)
1103 device->ws->buffer_destroy(device->gfx_init);
1104
1105 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1106 for (unsigned q = 0; q < device->queue_count[i]; q++)
1107 radv_queue_finish(&device->queues[i][q]);
1108 if (device->queue_count[i])
1109 vk_free(&device->alloc, device->queues[i]);
1110 }
1111
1112 vk_free(&device->alloc, device);
1113 return result;
1114 }
1115
1116 void radv_DestroyDevice(
1117 VkDevice _device,
1118 const VkAllocationCallbacks* pAllocator)
1119 {
1120 RADV_FROM_HANDLE(radv_device, device, _device);
1121
1122 if (!device)
1123 return;
1124
1125 if (device->trace_bo)
1126 device->ws->buffer_destroy(device->trace_bo);
1127
1128 if (device->gfx_init)
1129 device->ws->buffer_destroy(device->gfx_init);
1130
1131 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1132 for (unsigned q = 0; q < device->queue_count[i]; q++)
1133 radv_queue_finish(&device->queues[i][q]);
1134 if (device->queue_count[i])
1135 vk_free(&device->alloc, device->queues[i]);
1136 if (device->empty_cs[i])
1137 device->ws->cs_destroy(device->empty_cs[i]);
1138 if (device->flush_cs[i])
1139 device->ws->cs_destroy(device->flush_cs[i]);
1140 if (device->flush_shader_cs[i])
1141 device->ws->cs_destroy(device->flush_shader_cs[i]);
1142 }
1143 radv_device_finish_meta(device);
1144
1145 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1146 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1147
1148 vk_free(&device->alloc, device);
1149 }
1150
1151 VkResult radv_EnumerateInstanceExtensionProperties(
1152 const char* pLayerName,
1153 uint32_t* pPropertyCount,
1154 VkExtensionProperties* pProperties)
1155 {
1156 if (pProperties == NULL) {
1157 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1158 return VK_SUCCESS;
1159 }
1160
1161 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1162 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1163
1164 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1165 return VK_INCOMPLETE;
1166
1167 return VK_SUCCESS;
1168 }
1169
1170 VkResult radv_EnumerateDeviceExtensionProperties(
1171 VkPhysicalDevice physicalDevice,
1172 const char* pLayerName,
1173 uint32_t* pPropertyCount,
1174 VkExtensionProperties* pProperties)
1175 {
1176 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1177
1178 if (pProperties == NULL) {
1179 *pPropertyCount = pdevice->extensions.num_ext;
1180 return VK_SUCCESS;
1181 }
1182
1183 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1184 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1185
1186 if (*pPropertyCount < pdevice->extensions.num_ext)
1187 return VK_INCOMPLETE;
1188
1189 return VK_SUCCESS;
1190 }
1191
1192 VkResult radv_EnumerateInstanceLayerProperties(
1193 uint32_t* pPropertyCount,
1194 VkLayerProperties* pProperties)
1195 {
1196 if (pProperties == NULL) {
1197 *pPropertyCount = 0;
1198 return VK_SUCCESS;
1199 }
1200
1201 /* None supported at this time */
1202 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1203 }
1204
1205 VkResult radv_EnumerateDeviceLayerProperties(
1206 VkPhysicalDevice physicalDevice,
1207 uint32_t* pPropertyCount,
1208 VkLayerProperties* pProperties)
1209 {
1210 if (pProperties == NULL) {
1211 *pPropertyCount = 0;
1212 return VK_SUCCESS;
1213 }
1214
1215 /* None supported at this time */
1216 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1217 }
1218
1219 void radv_GetDeviceQueue(
1220 VkDevice _device,
1221 uint32_t queueFamilyIndex,
1222 uint32_t queueIndex,
1223 VkQueue* pQueue)
1224 {
1225 RADV_FROM_HANDLE(radv_device, device, _device);
1226
1227 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1228 }
1229
1230 static void radv_dump_trace(struct radv_device *device,
1231 struct radeon_winsys_cs *cs)
1232 {
1233 const char *filename = getenv("RADV_TRACE_FILE");
1234 FILE *f = fopen(filename, "w");
1235 if (!f) {
1236 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1237 return;
1238 }
1239
1240 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1241 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1242 fclose(f);
1243 }
1244
1245 static void
1246 fill_geom_tess_rings(struct radv_queue *queue,
1247 uint32_t *map,
1248 bool add_sample_positions,
1249 uint32_t esgs_ring_size,
1250 struct radeon_winsys_bo *esgs_ring_bo,
1251 uint32_t gsvs_ring_size,
1252 struct radeon_winsys_bo *gsvs_ring_bo,
1253 uint32_t tess_factor_ring_size,
1254 struct radeon_winsys_bo *tess_factor_ring_bo,
1255 uint32_t tess_offchip_ring_size,
1256 struct radeon_winsys_bo *tess_offchip_ring_bo)
1257 {
1258 uint64_t esgs_va = 0, gsvs_va = 0;
1259 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1260 uint32_t *desc = &map[4];
1261
1262 if (esgs_ring_bo)
1263 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1264 if (gsvs_ring_bo)
1265 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1266 if (tess_factor_ring_bo)
1267 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1268 if (tess_offchip_ring_bo)
1269 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1270
1271 /* stride 0, num records - size, add tid, swizzle, elsize4,
1272 index stride 64 */
1273 desc[0] = esgs_va;
1274 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1275 S_008F04_STRIDE(0) |
1276 S_008F04_SWIZZLE_ENABLE(true);
1277 desc[2] = esgs_ring_size;
1278 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1279 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1280 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1281 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1282 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1284 S_008F0C_ELEMENT_SIZE(1) |
1285 S_008F0C_INDEX_STRIDE(3) |
1286 S_008F0C_ADD_TID_ENABLE(true);
1287
1288 desc += 4;
1289 /* GS entry for ES->GS ring */
1290 /* stride 0, num records - size, elsize0,
1291 index stride 0 */
1292 desc[0] = esgs_va;
1293 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1294 S_008F04_STRIDE(0) |
1295 S_008F04_SWIZZLE_ENABLE(false);
1296 desc[2] = esgs_ring_size;
1297 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1298 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1299 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1300 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1301 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1302 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1303 S_008F0C_ELEMENT_SIZE(0) |
1304 S_008F0C_INDEX_STRIDE(0) |
1305 S_008F0C_ADD_TID_ENABLE(false);
1306
1307 desc += 4;
1308 /* VS entry for GS->VS ring */
1309 /* stride 0, num records - size, elsize0,
1310 index stride 0 */
1311 desc[0] = gsvs_va;
1312 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1313 S_008F04_STRIDE(0) |
1314 S_008F04_SWIZZLE_ENABLE(false);
1315 desc[2] = gsvs_ring_size;
1316 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1317 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1318 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1319 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1320 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1321 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1322 S_008F0C_ELEMENT_SIZE(0) |
1323 S_008F0C_INDEX_STRIDE(0) |
1324 S_008F0C_ADD_TID_ENABLE(false);
1325 desc += 4;
1326
1327 /* stride gsvs_itemsize, num records 64
1328 elsize 4, index stride 16 */
1329 /* shader will patch stride and desc[2] */
1330 desc[0] = gsvs_va;
1331 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1332 S_008F04_STRIDE(0) |
1333 S_008F04_SWIZZLE_ENABLE(true);
1334 desc[2] = 0;
1335 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1336 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1337 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1338 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1339 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1340 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1341 S_008F0C_ELEMENT_SIZE(1) |
1342 S_008F0C_INDEX_STRIDE(1) |
1343 S_008F0C_ADD_TID_ENABLE(true);
1344 desc += 4;
1345
1346 desc[0] = tess_factor_va;
1347 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1348 S_008F04_STRIDE(0) |
1349 S_008F04_SWIZZLE_ENABLE(false);
1350 desc[2] = tess_factor_ring_size;
1351 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1352 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1353 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1354 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1355 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1356 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1357 S_008F0C_ELEMENT_SIZE(0) |
1358 S_008F0C_INDEX_STRIDE(0) |
1359 S_008F0C_ADD_TID_ENABLE(false);
1360 desc += 4;
1361
1362 desc[0] = tess_offchip_va;
1363 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1364 S_008F04_STRIDE(0) |
1365 S_008F04_SWIZZLE_ENABLE(false);
1366 desc[2] = tess_offchip_ring_size;
1367 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1368 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1369 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1370 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1371 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1372 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1373 S_008F0C_ELEMENT_SIZE(0) |
1374 S_008F0C_INDEX_STRIDE(0) |
1375 S_008F0C_ADD_TID_ENABLE(false);
1376 desc += 4;
1377
1378 /* add sample positions after all rings */
1379 memcpy(desc, queue->device->sample_locations_1x, 8);
1380 desc += 2;
1381 memcpy(desc, queue->device->sample_locations_2x, 16);
1382 desc += 4;
1383 memcpy(desc, queue->device->sample_locations_4x, 32);
1384 desc += 8;
1385 memcpy(desc, queue->device->sample_locations_8x, 64);
1386 desc += 16;
1387 memcpy(desc, queue->device->sample_locations_16x, 128);
1388 }
1389
1390 static unsigned
1391 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1392 {
1393 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1394 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1395 device->physical_device->rad_info.family != CHIP_STONEY;
1396 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1397 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1398 device->physical_device->rad_info.max_se;
1399 unsigned offchip_granularity;
1400 unsigned hs_offchip_param;
1401 switch (device->tess_offchip_block_dw_size) {
1402 default:
1403 assert(0);
1404 /* fall through */
1405 case 8192:
1406 offchip_granularity = V_03093C_X_8K_DWORDS;
1407 break;
1408 case 4096:
1409 offchip_granularity = V_03093C_X_4K_DWORDS;
1410 break;
1411 }
1412
1413 switch (device->physical_device->rad_info.chip_class) {
1414 case SI:
1415 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1416 break;
1417 case CIK:
1418 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1419 break;
1420 case VI:
1421 default:
1422 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
1423 break;
1424 }
1425
1426 *max_offchip_buffers_p = max_offchip_buffers;
1427 if (device->physical_device->rad_info.chip_class >= CIK) {
1428 if (device->physical_device->rad_info.chip_class >= VI)
1429 --max_offchip_buffers;
1430 hs_offchip_param =
1431 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1432 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1433 } else {
1434 hs_offchip_param =
1435 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1436 }
1437 return hs_offchip_param;
1438 }
1439
1440 static VkResult
1441 radv_get_preamble_cs(struct radv_queue *queue,
1442 uint32_t scratch_size,
1443 uint32_t compute_scratch_size,
1444 uint32_t esgs_ring_size,
1445 uint32_t gsvs_ring_size,
1446 bool needs_tess_rings,
1447 bool needs_sample_positions,
1448 struct radeon_winsys_cs **initial_preamble_cs,
1449 struct radeon_winsys_cs **continue_preamble_cs)
1450 {
1451 struct radeon_winsys_bo *scratch_bo = NULL;
1452 struct radeon_winsys_bo *descriptor_bo = NULL;
1453 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1454 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1455 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1456 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1457 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1458 struct radeon_winsys_cs *dest_cs[2] = {0};
1459 bool add_tess_rings = false, add_sample_positions = false;
1460 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1461 unsigned max_offchip_buffers;
1462 unsigned hs_offchip_param = 0;
1463 if (!queue->has_tess_rings) {
1464 if (needs_tess_rings)
1465 add_tess_rings = true;
1466 }
1467 if (!queue->has_sample_positions) {
1468 if (needs_sample_positions)
1469 add_sample_positions = true;
1470 }
1471 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1472 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1473 &max_offchip_buffers);
1474 tess_offchip_ring_size = max_offchip_buffers *
1475 queue->device->tess_offchip_block_dw_size * 4;
1476
1477 if (scratch_size <= queue->scratch_size &&
1478 compute_scratch_size <= queue->compute_scratch_size &&
1479 esgs_ring_size <= queue->esgs_ring_size &&
1480 gsvs_ring_size <= queue->gsvs_ring_size &&
1481 !add_tess_rings && !add_sample_positions &&
1482 queue->initial_preamble_cs) {
1483 *initial_preamble_cs = queue->initial_preamble_cs;
1484 *continue_preamble_cs = queue->continue_preamble_cs;
1485 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1486 *continue_preamble_cs = NULL;
1487 return VK_SUCCESS;
1488 }
1489
1490 if (scratch_size > queue->scratch_size) {
1491 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1492 scratch_size,
1493 4096,
1494 RADEON_DOMAIN_VRAM,
1495 RADEON_FLAG_NO_CPU_ACCESS);
1496 if (!scratch_bo)
1497 goto fail;
1498 } else
1499 scratch_bo = queue->scratch_bo;
1500
1501 if (compute_scratch_size > queue->compute_scratch_size) {
1502 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1503 compute_scratch_size,
1504 4096,
1505 RADEON_DOMAIN_VRAM,
1506 RADEON_FLAG_NO_CPU_ACCESS);
1507 if (!compute_scratch_bo)
1508 goto fail;
1509
1510 } else
1511 compute_scratch_bo = queue->compute_scratch_bo;
1512
1513 if (esgs_ring_size > queue->esgs_ring_size) {
1514 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1515 esgs_ring_size,
1516 4096,
1517 RADEON_DOMAIN_VRAM,
1518 RADEON_FLAG_NO_CPU_ACCESS);
1519 if (!esgs_ring_bo)
1520 goto fail;
1521 } else {
1522 esgs_ring_bo = queue->esgs_ring_bo;
1523 esgs_ring_size = queue->esgs_ring_size;
1524 }
1525
1526 if (gsvs_ring_size > queue->gsvs_ring_size) {
1527 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1528 gsvs_ring_size,
1529 4096,
1530 RADEON_DOMAIN_VRAM,
1531 RADEON_FLAG_NO_CPU_ACCESS);
1532 if (!gsvs_ring_bo)
1533 goto fail;
1534 } else {
1535 gsvs_ring_bo = queue->gsvs_ring_bo;
1536 gsvs_ring_size = queue->gsvs_ring_size;
1537 }
1538
1539 if (add_tess_rings) {
1540 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1541 tess_factor_ring_size,
1542 256,
1543 RADEON_DOMAIN_VRAM,
1544 RADEON_FLAG_NO_CPU_ACCESS);
1545 if (!tess_factor_ring_bo)
1546 goto fail;
1547 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1548 tess_offchip_ring_size,
1549 256,
1550 RADEON_DOMAIN_VRAM,
1551 RADEON_FLAG_NO_CPU_ACCESS);
1552 if (!tess_offchip_ring_bo)
1553 goto fail;
1554 } else {
1555 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1556 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1557 }
1558
1559 if (scratch_bo != queue->scratch_bo ||
1560 esgs_ring_bo != queue->esgs_ring_bo ||
1561 gsvs_ring_bo != queue->gsvs_ring_bo ||
1562 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1563 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1564 uint32_t size = 0;
1565 if (gsvs_ring_bo || esgs_ring_bo ||
1566 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1567 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1568 if (add_sample_positions)
1569 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1570 }
1571 else if (scratch_bo)
1572 size = 8; /* 2 dword */
1573
1574 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1575 size,
1576 4096,
1577 RADEON_DOMAIN_VRAM,
1578 RADEON_FLAG_CPU_ACCESS);
1579 if (!descriptor_bo)
1580 goto fail;
1581 } else
1582 descriptor_bo = queue->descriptor_bo;
1583
1584 for(int i = 0; i < 2; ++i) {
1585 struct radeon_winsys_cs *cs = NULL;
1586 cs = queue->device->ws->cs_create(queue->device->ws,
1587 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1588 if (!cs)
1589 goto fail;
1590
1591 dest_cs[i] = cs;
1592
1593 if (scratch_bo)
1594 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1595
1596 if (esgs_ring_bo)
1597 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1598
1599 if (gsvs_ring_bo)
1600 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1601
1602 if (tess_factor_ring_bo)
1603 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1604
1605 if (tess_offchip_ring_bo)
1606 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1607
1608 if (descriptor_bo)
1609 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1610
1611 if (descriptor_bo != queue->descriptor_bo) {
1612 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1613
1614 if (scratch_bo) {
1615 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1616 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1617 S_008F04_SWIZZLE_ENABLE(1);
1618 map[0] = scratch_va;
1619 map[1] = rsrc1;
1620 }
1621
1622 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1623 add_sample_positions)
1624 fill_geom_tess_rings(queue, map, add_sample_positions,
1625 esgs_ring_size, esgs_ring_bo,
1626 gsvs_ring_size, gsvs_ring_bo,
1627 tess_factor_ring_size, tess_factor_ring_bo,
1628 tess_offchip_ring_size, tess_offchip_ring_bo);
1629
1630 queue->device->ws->buffer_unmap(descriptor_bo);
1631 }
1632
1633 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1634 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1635 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1636 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1637 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1638 }
1639
1640 if (esgs_ring_bo || gsvs_ring_bo) {
1641 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1642 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1643 radeon_emit(cs, esgs_ring_size >> 8);
1644 radeon_emit(cs, gsvs_ring_size >> 8);
1645 } else {
1646 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1647 radeon_emit(cs, esgs_ring_size >> 8);
1648 radeon_emit(cs, gsvs_ring_size >> 8);
1649 }
1650 }
1651
1652 if (tess_factor_ring_bo) {
1653 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1654 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1655 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1656 S_030938_SIZE(tess_factor_ring_size / 4));
1657 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1658 tf_va >> 8);
1659 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1660 } else {
1661 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1662 S_008988_SIZE(tess_factor_ring_size / 4));
1663 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1664 tf_va >> 8);
1665 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1666 hs_offchip_param);
1667 }
1668 }
1669
1670 if (descriptor_bo) {
1671 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1672 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1673 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1674 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1675 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1676 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1677
1678 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1679
1680 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1681 radeon_set_sh_reg_seq(cs, regs[i], 2);
1682 radeon_emit(cs, va);
1683 radeon_emit(cs, va >> 32);
1684 }
1685 }
1686
1687 if (compute_scratch_bo) {
1688 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1689 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1690 S_008F04_SWIZZLE_ENABLE(1);
1691
1692 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1693
1694 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1695 radeon_emit(cs, scratch_va);
1696 radeon_emit(cs, rsrc1);
1697 }
1698
1699 if (!i) {
1700 si_cs_emit_cache_flush(cs,
1701 queue->device->physical_device->rad_info.chip_class,
1702 queue->queue_family_index == RING_COMPUTE &&
1703 queue->device->physical_device->rad_info.chip_class >= CIK,
1704 RADV_CMD_FLAG_INV_ICACHE |
1705 RADV_CMD_FLAG_INV_SMEM_L1 |
1706 RADV_CMD_FLAG_INV_VMEM_L1 |
1707 RADV_CMD_FLAG_INV_GLOBAL_L2);
1708 }
1709
1710 if (!queue->device->ws->cs_finalize(cs))
1711 goto fail;
1712 }
1713
1714 if (queue->initial_preamble_cs)
1715 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1716
1717 if (queue->continue_preamble_cs)
1718 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1719
1720 queue->initial_preamble_cs = dest_cs[0];
1721 queue->continue_preamble_cs = dest_cs[1];
1722
1723 if (scratch_bo != queue->scratch_bo) {
1724 if (queue->scratch_bo)
1725 queue->device->ws->buffer_destroy(queue->scratch_bo);
1726 queue->scratch_bo = scratch_bo;
1727 queue->scratch_size = scratch_size;
1728 }
1729
1730 if (compute_scratch_bo != queue->compute_scratch_bo) {
1731 if (queue->compute_scratch_bo)
1732 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1733 queue->compute_scratch_bo = compute_scratch_bo;
1734 queue->compute_scratch_size = compute_scratch_size;
1735 }
1736
1737 if (esgs_ring_bo != queue->esgs_ring_bo) {
1738 if (queue->esgs_ring_bo)
1739 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1740 queue->esgs_ring_bo = esgs_ring_bo;
1741 queue->esgs_ring_size = esgs_ring_size;
1742 }
1743
1744 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1745 if (queue->gsvs_ring_bo)
1746 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1747 queue->gsvs_ring_bo = gsvs_ring_bo;
1748 queue->gsvs_ring_size = gsvs_ring_size;
1749 }
1750
1751 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1752 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1753 }
1754
1755 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1756 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1757 queue->has_tess_rings = true;
1758 }
1759
1760 if (descriptor_bo != queue->descriptor_bo) {
1761 if (queue->descriptor_bo)
1762 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1763
1764 queue->descriptor_bo = descriptor_bo;
1765 }
1766
1767 if (add_sample_positions)
1768 queue->has_sample_positions = true;
1769
1770 *initial_preamble_cs = queue->initial_preamble_cs;
1771 *continue_preamble_cs = queue->continue_preamble_cs;
1772 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1773 *continue_preamble_cs = NULL;
1774 return VK_SUCCESS;
1775 fail:
1776 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1777 if (dest_cs[i])
1778 queue->device->ws->cs_destroy(dest_cs[i]);
1779 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1780 queue->device->ws->buffer_destroy(descriptor_bo);
1781 if (scratch_bo && scratch_bo != queue->scratch_bo)
1782 queue->device->ws->buffer_destroy(scratch_bo);
1783 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1784 queue->device->ws->buffer_destroy(compute_scratch_bo);
1785 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1786 queue->device->ws->buffer_destroy(esgs_ring_bo);
1787 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1788 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1789 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1790 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1791 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1792 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1793 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1794 }
1795
1796 VkResult radv_QueueSubmit(
1797 VkQueue _queue,
1798 uint32_t submitCount,
1799 const VkSubmitInfo* pSubmits,
1800 VkFence _fence)
1801 {
1802 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1803 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1804 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1805 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1806 int ret;
1807 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1808 uint32_t scratch_size = 0;
1809 uint32_t compute_scratch_size = 0;
1810 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1811 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1812 VkResult result;
1813 bool fence_emitted = false;
1814 bool tess_rings_needed = false;
1815 bool sample_positions_needed = false;
1816
1817 /* Do this first so failing to allocate scratch buffers can't result in
1818 * partially executed submissions. */
1819 for (uint32_t i = 0; i < submitCount; i++) {
1820 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1821 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1822 pSubmits[i].pCommandBuffers[j]);
1823
1824 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1825 compute_scratch_size = MAX2(compute_scratch_size,
1826 cmd_buffer->compute_scratch_size_needed);
1827 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1828 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1829 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1830 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1831 }
1832 }
1833
1834 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1835 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1836 sample_positions_needed,
1837 &initial_preamble_cs, &continue_preamble_cs);
1838 if (result != VK_SUCCESS)
1839 return result;
1840
1841 for (uint32_t i = 0; i < submitCount; i++) {
1842 struct radeon_winsys_cs **cs_array;
1843 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1844 bool can_patch = !do_flush;
1845 uint32_t advance;
1846
1847 if (!pSubmits[i].commandBufferCount) {
1848 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1849 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1850 &queue->device->empty_cs[queue->queue_family_index],
1851 1, NULL, NULL,
1852 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1853 pSubmits[i].waitSemaphoreCount,
1854 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1855 pSubmits[i].signalSemaphoreCount,
1856 false, base_fence);
1857 if (ret) {
1858 radv_loge("failed to submit CS %d\n", i);
1859 abort();
1860 }
1861 fence_emitted = true;
1862 }
1863 continue;
1864 }
1865
1866 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1867 (pSubmits[i].commandBufferCount + do_flush));
1868
1869 if(do_flush)
1870 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
1871 queue->device->flush_shader_cs[queue->queue_family_index] :
1872 queue->device->flush_cs[queue->queue_family_index];
1873
1874 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1876 pSubmits[i].pCommandBuffers[j]);
1877 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1878
1879 cs_array[j + do_flush] = cmd_buffer->cs;
1880 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1881 can_patch = false;
1882 }
1883
1884 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1885 advance = MIN2(max_cs_submission,
1886 pSubmits[i].commandBufferCount + do_flush - j);
1887 bool b = j == 0;
1888 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1889
1890 if (queue->device->trace_bo)
1891 *queue->device->trace_id_ptr = 0;
1892
1893 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1894 advance, initial_preamble_cs, continue_preamble_cs,
1895 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1896 b ? pSubmits[i].waitSemaphoreCount : 0,
1897 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1898 e ? pSubmits[i].signalSemaphoreCount : 0,
1899 can_patch, base_fence);
1900
1901 if (ret) {
1902 radv_loge("failed to submit CS %d\n", i);
1903 abort();
1904 }
1905 fence_emitted = true;
1906 if (queue->device->trace_bo) {
1907 bool success = queue->device->ws->ctx_wait_idle(
1908 queue->hw_ctx,
1909 radv_queue_family_to_ring(
1910 queue->queue_family_index),
1911 queue->queue_idx);
1912
1913 if (!success) { /* Hang */
1914 radv_dump_trace(queue->device, cs_array[j]);
1915 abort();
1916 }
1917 }
1918 }
1919 free(cs_array);
1920 }
1921
1922 if (fence) {
1923 if (!fence_emitted)
1924 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1925 &queue->device->empty_cs[queue->queue_family_index],
1926 1, NULL, NULL, NULL, 0, NULL, 0,
1927 false, base_fence);
1928
1929 fence->submitted = true;
1930 }
1931
1932 return VK_SUCCESS;
1933 }
1934
1935 VkResult radv_QueueWaitIdle(
1936 VkQueue _queue)
1937 {
1938 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1939
1940 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1941 radv_queue_family_to_ring(queue->queue_family_index),
1942 queue->queue_idx);
1943 return VK_SUCCESS;
1944 }
1945
1946 VkResult radv_DeviceWaitIdle(
1947 VkDevice _device)
1948 {
1949 RADV_FROM_HANDLE(radv_device, device, _device);
1950
1951 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1952 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1953 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1954 }
1955 }
1956 return VK_SUCCESS;
1957 }
1958
1959 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1960 VkInstance instance,
1961 const char* pName)
1962 {
1963 return radv_lookup_entrypoint(pName);
1964 }
1965
1966 /* The loader wants us to expose a second GetInstanceProcAddr function
1967 * to work around certain LD_PRELOAD issues seen in apps.
1968 */
1969 PUBLIC
1970 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1971 VkInstance instance,
1972 const char* pName);
1973
1974 PUBLIC
1975 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1976 VkInstance instance,
1977 const char* pName)
1978 {
1979 return radv_GetInstanceProcAddr(instance, pName);
1980 }
1981
1982 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1983 VkDevice device,
1984 const char* pName)
1985 {
1986 return radv_lookup_entrypoint(pName);
1987 }
1988
1989 bool radv_get_memory_fd(struct radv_device *device,
1990 struct radv_device_memory *memory,
1991 int *pFD)
1992 {
1993 struct radeon_bo_metadata metadata;
1994
1995 if (memory->image) {
1996 radv_init_metadata(device, memory->image, &metadata);
1997 device->ws->buffer_set_metadata(memory->bo, &metadata);
1998 }
1999
2000 return device->ws->buffer_get_fd(device->ws, memory->bo,
2001 pFD);
2002 }
2003
2004 VkResult radv_AllocateMemory(
2005 VkDevice _device,
2006 const VkMemoryAllocateInfo* pAllocateInfo,
2007 const VkAllocationCallbacks* pAllocator,
2008 VkDeviceMemory* pMem)
2009 {
2010 RADV_FROM_HANDLE(radv_device, device, _device);
2011 struct radv_device_memory *mem;
2012 VkResult result;
2013 enum radeon_bo_domain domain;
2014 uint32_t flags = 0;
2015 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
2016 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2017
2018 if (pAllocateInfo->allocationSize == 0) {
2019 /* Apparently, this is allowed */
2020 *pMem = VK_NULL_HANDLE;
2021 return VK_SUCCESS;
2022 }
2023
2024 vk_foreach_struct(ext, pAllocateInfo->pNext) {
2025 switch (ext->sType) {
2026 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
2027 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
2028 break;
2029 default:
2030 break;
2031 }
2032 }
2033
2034 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2035 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2036 if (mem == NULL)
2037 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2038
2039 if (dedicate_info) {
2040 mem->image = radv_image_from_handle(dedicate_info->image);
2041 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2042 } else {
2043 mem->image = NULL;
2044 mem->buffer = NULL;
2045 }
2046
2047 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2048 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2049 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2050 domain = RADEON_DOMAIN_GTT;
2051 else
2052 domain = RADEON_DOMAIN_VRAM;
2053
2054 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2055 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2056 else
2057 flags |= RADEON_FLAG_CPU_ACCESS;
2058
2059 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2060 flags |= RADEON_FLAG_GTT_WC;
2061
2062 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2063 domain, flags);
2064
2065 if (!mem->bo) {
2066 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2067 goto fail;
2068 }
2069 mem->type_index = pAllocateInfo->memoryTypeIndex;
2070
2071 *pMem = radv_device_memory_to_handle(mem);
2072
2073 return VK_SUCCESS;
2074
2075 fail:
2076 vk_free2(&device->alloc, pAllocator, mem);
2077
2078 return result;
2079 }
2080
2081 void radv_FreeMemory(
2082 VkDevice _device,
2083 VkDeviceMemory _mem,
2084 const VkAllocationCallbacks* pAllocator)
2085 {
2086 RADV_FROM_HANDLE(radv_device, device, _device);
2087 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2088
2089 if (mem == NULL)
2090 return;
2091
2092 device->ws->buffer_destroy(mem->bo);
2093 mem->bo = NULL;
2094
2095 vk_free2(&device->alloc, pAllocator, mem);
2096 }
2097
2098 VkResult radv_MapMemory(
2099 VkDevice _device,
2100 VkDeviceMemory _memory,
2101 VkDeviceSize offset,
2102 VkDeviceSize size,
2103 VkMemoryMapFlags flags,
2104 void** ppData)
2105 {
2106 RADV_FROM_HANDLE(radv_device, device, _device);
2107 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2108
2109 if (mem == NULL) {
2110 *ppData = NULL;
2111 return VK_SUCCESS;
2112 }
2113
2114 *ppData = device->ws->buffer_map(mem->bo);
2115 if (*ppData) {
2116 *ppData += offset;
2117 return VK_SUCCESS;
2118 }
2119
2120 return VK_ERROR_MEMORY_MAP_FAILED;
2121 }
2122
2123 void radv_UnmapMemory(
2124 VkDevice _device,
2125 VkDeviceMemory _memory)
2126 {
2127 RADV_FROM_HANDLE(radv_device, device, _device);
2128 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2129
2130 if (mem == NULL)
2131 return;
2132
2133 device->ws->buffer_unmap(mem->bo);
2134 }
2135
2136 VkResult radv_FlushMappedMemoryRanges(
2137 VkDevice _device,
2138 uint32_t memoryRangeCount,
2139 const VkMappedMemoryRange* pMemoryRanges)
2140 {
2141 return VK_SUCCESS;
2142 }
2143
2144 VkResult radv_InvalidateMappedMemoryRanges(
2145 VkDevice _device,
2146 uint32_t memoryRangeCount,
2147 const VkMappedMemoryRange* pMemoryRanges)
2148 {
2149 return VK_SUCCESS;
2150 }
2151
2152 void radv_GetBufferMemoryRequirements(
2153 VkDevice device,
2154 VkBuffer _buffer,
2155 VkMemoryRequirements* pMemoryRequirements)
2156 {
2157 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2158
2159 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2160
2161 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2162 pMemoryRequirements->alignment = 4096;
2163 else
2164 pMemoryRequirements->alignment = 16;
2165
2166 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2167 }
2168
2169 void radv_GetImageMemoryRequirements(
2170 VkDevice device,
2171 VkImage _image,
2172 VkMemoryRequirements* pMemoryRequirements)
2173 {
2174 RADV_FROM_HANDLE(radv_image, image, _image);
2175
2176 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2177
2178 pMemoryRequirements->size = image->size;
2179 pMemoryRequirements->alignment = image->alignment;
2180 }
2181
2182 void radv_GetImageSparseMemoryRequirements(
2183 VkDevice device,
2184 VkImage image,
2185 uint32_t* pSparseMemoryRequirementCount,
2186 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2187 {
2188 stub();
2189 }
2190
2191 void radv_GetDeviceMemoryCommitment(
2192 VkDevice device,
2193 VkDeviceMemory memory,
2194 VkDeviceSize* pCommittedMemoryInBytes)
2195 {
2196 *pCommittedMemoryInBytes = 0;
2197 }
2198
2199 VkResult radv_BindBufferMemory(
2200 VkDevice device,
2201 VkBuffer _buffer,
2202 VkDeviceMemory _memory,
2203 VkDeviceSize memoryOffset)
2204 {
2205 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2206 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2207
2208 if (mem) {
2209 buffer->bo = mem->bo;
2210 buffer->offset = memoryOffset;
2211 } else {
2212 buffer->bo = NULL;
2213 buffer->offset = 0;
2214 }
2215
2216 return VK_SUCCESS;
2217 }
2218
2219 VkResult radv_BindImageMemory(
2220 VkDevice device,
2221 VkImage _image,
2222 VkDeviceMemory _memory,
2223 VkDeviceSize memoryOffset)
2224 {
2225 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2226 RADV_FROM_HANDLE(radv_image, image, _image);
2227
2228 if (mem) {
2229 image->bo = mem->bo;
2230 image->offset = memoryOffset;
2231 } else {
2232 image->bo = NULL;
2233 image->offset = 0;
2234 }
2235
2236 return VK_SUCCESS;
2237 }
2238
2239
2240 static void
2241 radv_sparse_buffer_bind_memory(struct radv_device *device,
2242 const VkSparseBufferMemoryBindInfo *bind)
2243 {
2244 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2245
2246 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2247 struct radv_device_memory *mem = NULL;
2248
2249 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2250 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2251
2252 device->ws->buffer_virtual_bind(buffer->bo,
2253 bind->pBinds[i].resourceOffset,
2254 bind->pBinds[i].size,
2255 mem ? mem->bo : NULL,
2256 bind->pBinds[i].memoryOffset);
2257 }
2258 }
2259
2260 static void
2261 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2262 const VkSparseImageOpaqueMemoryBindInfo *bind)
2263 {
2264 RADV_FROM_HANDLE(radv_image, image, bind->image);
2265
2266 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2267 struct radv_device_memory *mem = NULL;
2268
2269 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2270 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2271
2272 device->ws->buffer_virtual_bind(image->bo,
2273 bind->pBinds[i].resourceOffset,
2274 bind->pBinds[i].size,
2275 mem ? mem->bo : NULL,
2276 bind->pBinds[i].memoryOffset);
2277 }
2278 }
2279
2280 VkResult radv_QueueBindSparse(
2281 VkQueue _queue,
2282 uint32_t bindInfoCount,
2283 const VkBindSparseInfo* pBindInfo,
2284 VkFence _fence)
2285 {
2286 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2287 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2288 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2289 bool fence_emitted = false;
2290
2291 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2292 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2293 radv_sparse_buffer_bind_memory(queue->device,
2294 pBindInfo[i].pBufferBinds + j);
2295 }
2296
2297 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2298 radv_sparse_image_opaque_bind_memory(queue->device,
2299 pBindInfo[i].pImageOpaqueBinds + j);
2300 }
2301
2302 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2303 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2304 &queue->device->empty_cs[queue->queue_family_index],
2305 1, NULL, NULL,
2306 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2307 pBindInfo[i].waitSemaphoreCount,
2308 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2309 pBindInfo[i].signalSemaphoreCount,
2310 false, base_fence);
2311 fence_emitted = true;
2312 if (fence)
2313 fence->submitted = true;
2314 }
2315 }
2316
2317 if (fence && !fence_emitted) {
2318 fence->signalled = true;
2319 }
2320
2321 return VK_SUCCESS;
2322 }
2323
2324 VkResult radv_CreateFence(
2325 VkDevice _device,
2326 const VkFenceCreateInfo* pCreateInfo,
2327 const VkAllocationCallbacks* pAllocator,
2328 VkFence* pFence)
2329 {
2330 RADV_FROM_HANDLE(radv_device, device, _device);
2331 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2332 sizeof(*fence), 8,
2333 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2334
2335 if (!fence)
2336 return VK_ERROR_OUT_OF_HOST_MEMORY;
2337
2338 memset(fence, 0, sizeof(*fence));
2339 fence->submitted = false;
2340 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2341 fence->fence = device->ws->create_fence();
2342 if (!fence->fence) {
2343 vk_free2(&device->alloc, pAllocator, fence);
2344 return VK_ERROR_OUT_OF_HOST_MEMORY;
2345 }
2346
2347 *pFence = radv_fence_to_handle(fence);
2348
2349 return VK_SUCCESS;
2350 }
2351
2352 void radv_DestroyFence(
2353 VkDevice _device,
2354 VkFence _fence,
2355 const VkAllocationCallbacks* pAllocator)
2356 {
2357 RADV_FROM_HANDLE(radv_device, device, _device);
2358 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2359
2360 if (!fence)
2361 return;
2362 device->ws->destroy_fence(fence->fence);
2363 vk_free2(&device->alloc, pAllocator, fence);
2364 }
2365
2366 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2367 {
2368 uint64_t current_time;
2369 struct timespec tv;
2370
2371 clock_gettime(CLOCK_MONOTONIC, &tv);
2372 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2373
2374 timeout = MIN2(UINT64_MAX - current_time, timeout);
2375
2376 return current_time + timeout;
2377 }
2378
2379 VkResult radv_WaitForFences(
2380 VkDevice _device,
2381 uint32_t fenceCount,
2382 const VkFence* pFences,
2383 VkBool32 waitAll,
2384 uint64_t timeout)
2385 {
2386 RADV_FROM_HANDLE(radv_device, device, _device);
2387 timeout = radv_get_absolute_timeout(timeout);
2388
2389 if (!waitAll && fenceCount > 1) {
2390 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2391 }
2392
2393 for (uint32_t i = 0; i < fenceCount; ++i) {
2394 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2395 bool expired = false;
2396
2397 if (fence->signalled)
2398 continue;
2399
2400 if (!fence->submitted)
2401 return VK_TIMEOUT;
2402
2403 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2404 if (!expired)
2405 return VK_TIMEOUT;
2406
2407 fence->signalled = true;
2408 }
2409
2410 return VK_SUCCESS;
2411 }
2412
2413 VkResult radv_ResetFences(VkDevice device,
2414 uint32_t fenceCount,
2415 const VkFence *pFences)
2416 {
2417 for (unsigned i = 0; i < fenceCount; ++i) {
2418 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2419 fence->submitted = fence->signalled = false;
2420 }
2421
2422 return VK_SUCCESS;
2423 }
2424
2425 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2426 {
2427 RADV_FROM_HANDLE(radv_device, device, _device);
2428 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2429
2430 if (fence->signalled)
2431 return VK_SUCCESS;
2432 if (!fence->submitted)
2433 return VK_NOT_READY;
2434
2435 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2436 return VK_NOT_READY;
2437
2438 return VK_SUCCESS;
2439 }
2440
2441
2442 // Queue semaphore functions
2443
2444 VkResult radv_CreateSemaphore(
2445 VkDevice _device,
2446 const VkSemaphoreCreateInfo* pCreateInfo,
2447 const VkAllocationCallbacks* pAllocator,
2448 VkSemaphore* pSemaphore)
2449 {
2450 RADV_FROM_HANDLE(radv_device, device, _device);
2451 struct radeon_winsys_sem *sem;
2452
2453 sem = device->ws->create_sem(device->ws);
2454 if (!sem)
2455 return VK_ERROR_OUT_OF_HOST_MEMORY;
2456
2457 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2458 return VK_SUCCESS;
2459 }
2460
2461 void radv_DestroySemaphore(
2462 VkDevice _device,
2463 VkSemaphore _semaphore,
2464 const VkAllocationCallbacks* pAllocator)
2465 {
2466 RADV_FROM_HANDLE(radv_device, device, _device);
2467 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2468 if (!_semaphore)
2469 return;
2470
2471 device->ws->destroy_sem(sem);
2472 }
2473
2474 VkResult radv_CreateEvent(
2475 VkDevice _device,
2476 const VkEventCreateInfo* pCreateInfo,
2477 const VkAllocationCallbacks* pAllocator,
2478 VkEvent* pEvent)
2479 {
2480 RADV_FROM_HANDLE(radv_device, device, _device);
2481 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2482 sizeof(*event), 8,
2483 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2484
2485 if (!event)
2486 return VK_ERROR_OUT_OF_HOST_MEMORY;
2487
2488 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2489 RADEON_DOMAIN_GTT,
2490 RADEON_FLAG_CPU_ACCESS);
2491 if (!event->bo) {
2492 vk_free2(&device->alloc, pAllocator, event);
2493 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2494 }
2495
2496 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2497
2498 *pEvent = radv_event_to_handle(event);
2499
2500 return VK_SUCCESS;
2501 }
2502
2503 void radv_DestroyEvent(
2504 VkDevice _device,
2505 VkEvent _event,
2506 const VkAllocationCallbacks* pAllocator)
2507 {
2508 RADV_FROM_HANDLE(radv_device, device, _device);
2509 RADV_FROM_HANDLE(radv_event, event, _event);
2510
2511 if (!event)
2512 return;
2513 device->ws->buffer_destroy(event->bo);
2514 vk_free2(&device->alloc, pAllocator, event);
2515 }
2516
2517 VkResult radv_GetEventStatus(
2518 VkDevice _device,
2519 VkEvent _event)
2520 {
2521 RADV_FROM_HANDLE(radv_event, event, _event);
2522
2523 if (*event->map == 1)
2524 return VK_EVENT_SET;
2525 return VK_EVENT_RESET;
2526 }
2527
2528 VkResult radv_SetEvent(
2529 VkDevice _device,
2530 VkEvent _event)
2531 {
2532 RADV_FROM_HANDLE(radv_event, event, _event);
2533 *event->map = 1;
2534
2535 return VK_SUCCESS;
2536 }
2537
2538 VkResult radv_ResetEvent(
2539 VkDevice _device,
2540 VkEvent _event)
2541 {
2542 RADV_FROM_HANDLE(radv_event, event, _event);
2543 *event->map = 0;
2544
2545 return VK_SUCCESS;
2546 }
2547
2548 VkResult radv_CreateBuffer(
2549 VkDevice _device,
2550 const VkBufferCreateInfo* pCreateInfo,
2551 const VkAllocationCallbacks* pAllocator,
2552 VkBuffer* pBuffer)
2553 {
2554 RADV_FROM_HANDLE(radv_device, device, _device);
2555 struct radv_buffer *buffer;
2556
2557 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2558
2559 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2560 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2561 if (buffer == NULL)
2562 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2563
2564 buffer->size = pCreateInfo->size;
2565 buffer->usage = pCreateInfo->usage;
2566 buffer->bo = NULL;
2567 buffer->offset = 0;
2568 buffer->flags = pCreateInfo->flags;
2569
2570 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2571 buffer->bo = device->ws->buffer_create(device->ws,
2572 align64(buffer->size, 4096),
2573 4096, 0, RADEON_FLAG_VIRTUAL);
2574 if (!buffer->bo) {
2575 vk_free2(&device->alloc, pAllocator, buffer);
2576 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2577 }
2578 }
2579
2580 *pBuffer = radv_buffer_to_handle(buffer);
2581
2582 return VK_SUCCESS;
2583 }
2584
2585 void radv_DestroyBuffer(
2586 VkDevice _device,
2587 VkBuffer _buffer,
2588 const VkAllocationCallbacks* pAllocator)
2589 {
2590 RADV_FROM_HANDLE(radv_device, device, _device);
2591 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2592
2593 if (!buffer)
2594 return;
2595
2596 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2597 device->ws->buffer_destroy(buffer->bo);
2598
2599 vk_free2(&device->alloc, pAllocator, buffer);
2600 }
2601
2602 static inline unsigned
2603 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2604 {
2605 if (stencil)
2606 return image->surface.stencil_tiling_index[level];
2607 else
2608 return image->surface.tiling_index[level];
2609 }
2610
2611 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2612 {
2613 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2614 }
2615
2616 static void
2617 radv_initialise_color_surface(struct radv_device *device,
2618 struct radv_color_buffer_info *cb,
2619 struct radv_image_view *iview)
2620 {
2621 const struct vk_format_description *desc;
2622 unsigned ntype, format, swap, endian;
2623 unsigned blend_clamp = 0, blend_bypass = 0;
2624 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2625 uint64_t va;
2626 const struct radeon_surf *surf = &iview->image->surface;
2627 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2628
2629 desc = vk_format_description(iview->vk_format);
2630
2631 memset(cb, 0, sizeof(*cb));
2632
2633 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2634 va += level_info->offset;
2635 cb->cb_color_base = va >> 8;
2636
2637 /* CMASK variables */
2638 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2639 va += iview->image->cmask.offset;
2640 cb->cb_color_cmask = va >> 8;
2641 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2642
2643 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2644 va += iview->image->dcc_offset;
2645 cb->cb_dcc_base = va >> 8;
2646
2647 uint32_t max_slice = radv_surface_layer_count(iview);
2648 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2649 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2650
2651 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2652 pitch_tile_max = level_info->nblk_x / 8 - 1;
2653 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2654 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2655
2656 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2657 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2658
2659 /* Intensity is implemented as Red, so treat it that way. */
2660 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2661 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2662
2663 if (iview->image->info.samples > 1) {
2664 unsigned log_samples = util_logbase2(iview->image->info.samples);
2665
2666 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2667 S_028C74_NUM_FRAGMENTS(log_samples);
2668 }
2669
2670 if (iview->image->fmask.size) {
2671 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2672 if (device->physical_device->rad_info.chip_class >= CIK)
2673 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2674 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2675 cb->cb_color_fmask = va >> 8;
2676 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2677 } else {
2678 /* This must be set for fast clear to work without FMASK. */
2679 if (device->physical_device->rad_info.chip_class >= CIK)
2680 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2681 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2682 cb->cb_color_fmask = cb->cb_color_base;
2683 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2684 }
2685
2686 ntype = radv_translate_color_numformat(iview->vk_format,
2687 desc,
2688 vk_format_get_first_non_void_channel(iview->vk_format));
2689 format = radv_translate_colorformat(iview->vk_format);
2690 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2691 radv_finishme("Illegal color\n");
2692 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2693 endian = radv_colorformat_endian_swap(format);
2694
2695 /* blend clamp should be set for all NORM/SRGB types */
2696 if (ntype == V_028C70_NUMBER_UNORM ||
2697 ntype == V_028C70_NUMBER_SNORM ||
2698 ntype == V_028C70_NUMBER_SRGB)
2699 blend_clamp = 1;
2700
2701 /* set blend bypass according to docs if SINT/UINT or
2702 8/24 COLOR variants */
2703 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2704 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2705 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2706 blend_clamp = 0;
2707 blend_bypass = 1;
2708 }
2709 #if 0
2710 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2711 (format == V_028C70_COLOR_8 ||
2712 format == V_028C70_COLOR_8_8 ||
2713 format == V_028C70_COLOR_8_8_8_8))
2714 ->color_is_int8 = true;
2715 #endif
2716 cb->cb_color_info = S_028C70_FORMAT(format) |
2717 S_028C70_COMP_SWAP(swap) |
2718 S_028C70_BLEND_CLAMP(blend_clamp) |
2719 S_028C70_BLEND_BYPASS(blend_bypass) |
2720 S_028C70_SIMPLE_FLOAT(1) |
2721 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2722 ntype != V_028C70_NUMBER_SNORM &&
2723 ntype != V_028C70_NUMBER_SRGB &&
2724 format != V_028C70_COLOR_8_24 &&
2725 format != V_028C70_COLOR_24_8) |
2726 S_028C70_NUMBER_TYPE(ntype) |
2727 S_028C70_ENDIAN(endian);
2728 if (iview->image->info.samples > 1)
2729 if (iview->image->fmask.size)
2730 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2731
2732 if (iview->image->cmask.size &&
2733 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2734 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2735
2736 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2737 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2738
2739 if (device->physical_device->rad_info.chip_class >= VI) {
2740 unsigned max_uncompressed_block_size = 2;
2741 if (iview->image->info.samples > 1) {
2742 if (iview->image->surface.bpe == 1)
2743 max_uncompressed_block_size = 0;
2744 else if (iview->image->surface.bpe == 2)
2745 max_uncompressed_block_size = 1;
2746 }
2747
2748 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2749 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2750 }
2751
2752 /* This must be set for fast clear to work without FMASK. */
2753 if (!iview->image->fmask.size &&
2754 device->physical_device->rad_info.chip_class == SI) {
2755 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2756 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2757 }
2758 }
2759
2760 static void
2761 radv_initialise_ds_surface(struct radv_device *device,
2762 struct radv_ds_buffer_info *ds,
2763 struct radv_image_view *iview)
2764 {
2765 unsigned level = iview->base_mip;
2766 unsigned format;
2767 uint64_t va, s_offs, z_offs;
2768 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2769 bool stencil_only = false;
2770 memset(ds, 0, sizeof(*ds));
2771 switch (iview->vk_format) {
2772 case VK_FORMAT_D24_UNORM_S8_UINT:
2773 case VK_FORMAT_X8_D24_UNORM_PACK32:
2774 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2775 ds->offset_scale = 2.0f;
2776 break;
2777 case VK_FORMAT_D16_UNORM:
2778 case VK_FORMAT_D16_UNORM_S8_UINT:
2779 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2780 ds->offset_scale = 4.0f;
2781 break;
2782 case VK_FORMAT_D32_SFLOAT:
2783 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2784 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2785 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2786 ds->offset_scale = 1.0f;
2787 break;
2788 case VK_FORMAT_S8_UINT:
2789 stencil_only = true;
2790 level_info = &iview->image->surface.stencil_level[level];
2791 break;
2792 default:
2793 break;
2794 }
2795
2796 format = radv_translate_dbformat(iview->vk_format);
2797
2798 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2799 s_offs = z_offs = va;
2800 z_offs += iview->image->surface.level[level].offset;
2801 s_offs += iview->image->surface.stencil_level[level].offset;
2802
2803 uint32_t max_slice = radv_surface_layer_count(iview);
2804 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2805 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2806 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2807 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2808
2809 if (iview->image->info.samples > 1)
2810 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
2811
2812 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2813 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2814 else
2815 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2816
2817 if (device->physical_device->rad_info.chip_class >= CIK) {
2818 struct radeon_info *info = &device->physical_device->rad_info;
2819 unsigned tiling_index = iview->image->surface.tiling_index[level];
2820 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2821 unsigned macro_index = iview->image->surface.macro_tile_index;
2822 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2823 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2824 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2825
2826 if (stencil_only)
2827 tile_mode = stencil_tile_mode;
2828
2829 ds->db_depth_info |=
2830 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2831 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2832 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2833 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2834 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2835 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2836 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2837 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2838 } else {
2839 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2840 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2841 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2842 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2843 }
2844
2845 if (iview->image->surface.htile_size && !level) {
2846 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2847 S_028040_ALLOW_EXPCLEAR(1);
2848
2849 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2850 /* Workaround: For a not yet understood reason, the
2851 * combination of MSAA, fast stencil clear and stencil
2852 * decompress messes with subsequent stencil buffer
2853 * uses. Problem was reproduced on Verde, Bonaire,
2854 * Tonga, and Carrizo.
2855 *
2856 * Disabling EXPCLEAR works around the problem.
2857 *
2858 * Check piglit's arb_texture_multisample-stencil-clear
2859 * test if you want to try changing this.
2860 */
2861 if (iview->image->info.samples <= 1)
2862 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2863 } else
2864 /* Use all of the htile_buffer for depth if there's no stencil. */
2865 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2866
2867 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2868 iview->image->htile_offset;
2869 ds->db_htile_data_base = va >> 8;
2870 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2871 } else {
2872 ds->db_htile_data_base = 0;
2873 ds->db_htile_surface = 0;
2874 }
2875
2876 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2877 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2878
2879 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2880 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2881 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2882 }
2883
2884 VkResult radv_CreateFramebuffer(
2885 VkDevice _device,
2886 const VkFramebufferCreateInfo* pCreateInfo,
2887 const VkAllocationCallbacks* pAllocator,
2888 VkFramebuffer* pFramebuffer)
2889 {
2890 RADV_FROM_HANDLE(radv_device, device, _device);
2891 struct radv_framebuffer *framebuffer;
2892
2893 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2894
2895 size_t size = sizeof(*framebuffer) +
2896 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2897 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2898 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2899 if (framebuffer == NULL)
2900 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2901
2902 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2903 framebuffer->width = pCreateInfo->width;
2904 framebuffer->height = pCreateInfo->height;
2905 framebuffer->layers = pCreateInfo->layers;
2906 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2907 VkImageView _iview = pCreateInfo->pAttachments[i];
2908 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2909 framebuffer->attachments[i].attachment = iview;
2910 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2911 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2912 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2913 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2914 }
2915 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2916 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2917 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2918 }
2919
2920 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2921 return VK_SUCCESS;
2922 }
2923
2924 void radv_DestroyFramebuffer(
2925 VkDevice _device,
2926 VkFramebuffer _fb,
2927 const VkAllocationCallbacks* pAllocator)
2928 {
2929 RADV_FROM_HANDLE(radv_device, device, _device);
2930 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2931
2932 if (!fb)
2933 return;
2934 vk_free2(&device->alloc, pAllocator, fb);
2935 }
2936
2937 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2938 {
2939 switch (address_mode) {
2940 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2941 return V_008F30_SQ_TEX_WRAP;
2942 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2943 return V_008F30_SQ_TEX_MIRROR;
2944 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2945 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2946 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2947 return V_008F30_SQ_TEX_CLAMP_BORDER;
2948 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2949 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2950 default:
2951 unreachable("illegal tex wrap mode");
2952 break;
2953 }
2954 }
2955
2956 static unsigned
2957 radv_tex_compare(VkCompareOp op)
2958 {
2959 switch (op) {
2960 case VK_COMPARE_OP_NEVER:
2961 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2962 case VK_COMPARE_OP_LESS:
2963 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2964 case VK_COMPARE_OP_EQUAL:
2965 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2966 case VK_COMPARE_OP_LESS_OR_EQUAL:
2967 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2968 case VK_COMPARE_OP_GREATER:
2969 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2970 case VK_COMPARE_OP_NOT_EQUAL:
2971 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2972 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2973 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2974 case VK_COMPARE_OP_ALWAYS:
2975 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2976 default:
2977 unreachable("illegal compare mode");
2978 break;
2979 }
2980 }
2981
2982 static unsigned
2983 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2984 {
2985 switch (filter) {
2986 case VK_FILTER_NEAREST:
2987 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2988 V_008F38_SQ_TEX_XY_FILTER_POINT);
2989 case VK_FILTER_LINEAR:
2990 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2991 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2992 case VK_FILTER_CUBIC_IMG:
2993 default:
2994 fprintf(stderr, "illegal texture filter");
2995 return 0;
2996 }
2997 }
2998
2999 static unsigned
3000 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3001 {
3002 switch (mode) {
3003 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3004 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3005 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3006 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3007 default:
3008 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3009 }
3010 }
3011
3012 static unsigned
3013 radv_tex_bordercolor(VkBorderColor bcolor)
3014 {
3015 switch (bcolor) {
3016 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3017 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3018 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3019 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3020 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3021 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3022 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3023 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3024 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3025 default:
3026 break;
3027 }
3028 return 0;
3029 }
3030
3031 static unsigned
3032 radv_tex_aniso_filter(unsigned filter)
3033 {
3034 if (filter < 2)
3035 return 0;
3036 if (filter < 4)
3037 return 1;
3038 if (filter < 8)
3039 return 2;
3040 if (filter < 16)
3041 return 3;
3042 return 4;
3043 }
3044
3045 static void
3046 radv_init_sampler(struct radv_device *device,
3047 struct radv_sampler *sampler,
3048 const VkSamplerCreateInfo *pCreateInfo)
3049 {
3050 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3051 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3052 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3053 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3054
3055 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3056 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3057 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3058 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3059 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3060 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3061 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3062 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3063 S_008F30_DISABLE_CUBE_WRAP(0) |
3064 S_008F30_COMPAT_MODE(is_vi));
3065 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3066 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3067 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3068 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3069 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3070 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3071 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3072 S_008F38_MIP_POINT_PRECLAMP(0) |
3073 S_008F38_DISABLE_LSB_CEIL(1) |
3074 S_008F38_FILTER_PREC_FIX(1) |
3075 S_008F38_ANISO_OVERRIDE(is_vi));
3076 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3077 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3078 }
3079
3080 VkResult radv_CreateSampler(
3081 VkDevice _device,
3082 const VkSamplerCreateInfo* pCreateInfo,
3083 const VkAllocationCallbacks* pAllocator,
3084 VkSampler* pSampler)
3085 {
3086 RADV_FROM_HANDLE(radv_device, device, _device);
3087 struct radv_sampler *sampler;
3088
3089 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3090
3091 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3092 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3093 if (!sampler)
3094 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3095
3096 radv_init_sampler(device, sampler, pCreateInfo);
3097 *pSampler = radv_sampler_to_handle(sampler);
3098
3099 return VK_SUCCESS;
3100 }
3101
3102 void radv_DestroySampler(
3103 VkDevice _device,
3104 VkSampler _sampler,
3105 const VkAllocationCallbacks* pAllocator)
3106 {
3107 RADV_FROM_HANDLE(radv_device, device, _device);
3108 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3109
3110 if (!sampler)
3111 return;
3112 vk_free2(&device->alloc, pAllocator, sampler);
3113 }
3114
3115
3116 /* vk_icd.h does not declare this function, so we declare it here to
3117 * suppress Wmissing-prototypes.
3118 */
3119 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3120 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3121
3122 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3123 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3124 {
3125 /* For the full details on loader interface versioning, see
3126 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3127 * What follows is a condensed summary, to help you navigate the large and
3128 * confusing official doc.
3129 *
3130 * - Loader interface v0 is incompatible with later versions. We don't
3131 * support it.
3132 *
3133 * - In loader interface v1:
3134 * - The first ICD entrypoint called by the loader is
3135 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3136 * entrypoint.
3137 * - The ICD must statically expose no other Vulkan symbol unless it is
3138 * linked with -Bsymbolic.
3139 * - Each dispatchable Vulkan handle created by the ICD must be
3140 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3141 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3142 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3143 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3144 * such loader-managed surfaces.
3145 *
3146 * - Loader interface v2 differs from v1 in:
3147 * - The first ICD entrypoint called by the loader is
3148 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3149 * statically expose this entrypoint.
3150 *
3151 * - Loader interface v3 differs from v2 in:
3152 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3153 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3154 * because the loader no longer does so.
3155 */
3156 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3157 return VK_SUCCESS;
3158 }