2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10
: chip_string
= "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12
: chip_string
= "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14
: chip_string
= "AMD RADV NAVI14"; break;
119 default: chip_string
= "AMD RADV unknown"; break;
122 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
126 radv_get_visible_vram_size(struct radv_physical_device
*device
)
128 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
132 radv_get_vram_size(struct radv_physical_device
*device
)
134 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
138 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
141 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
142 uint64_t vram_size
= radv_get_vram_size(device
);
143 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
144 device
->memory_properties
.memoryHeapCount
= 0;
146 vram_index
= device
->memory_properties
.memoryHeapCount
++;
147 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
149 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
152 if (visible_vram_size
) {
153 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
154 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
155 .size
= visible_vram_size
,
156 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
159 if (device
->rad_info
.gart_size
> 0) {
160 gart_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
162 .size
= device
->rad_info
.gart_size
,
163 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
168 unsigned type_count
= 0;
169 if (vram_index
>= 0) {
170 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
171 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
172 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
173 .heapIndex
= vram_index
,
176 if (gart_index
>= 0) {
177 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
178 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
179 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
181 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
182 .heapIndex
= gart_index
,
185 if (visible_vram_index
>= 0) {
186 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
187 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
188 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
191 .heapIndex
= visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
196 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
197 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
200 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
201 .heapIndex
= gart_index
,
204 device
->memory_properties
.memoryTypeCount
= type_count
;
208 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
210 const char *family
= getenv("RADV_FORCE_FAMILY");
216 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
217 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
218 /* Override family and chip_class. */
219 device
->rad_info
.family
= i
;
221 if (i
>= CHIP_NAVI10
)
222 device
->rad_info
.chip_class
= GFX10
;
223 else if (i
>= CHIP_VEGA10
)
224 device
->rad_info
.chip_class
= GFX9
;
225 else if (i
>= CHIP_TONGA
)
226 device
->rad_info
.chip_class
= GFX8
;
227 else if (i
>= CHIP_BONAIRE
)
228 device
->rad_info
.chip_class
= GFX7
;
230 device
->rad_info
.chip_class
= GFX6
;
236 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
251 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
253 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
254 radv_logi("Could not open device '%s'", path
);
256 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
259 version
= drmGetVersion(fd
);
263 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
264 radv_logi("Could not get the kernel driver version for device '%s'", path
);
266 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
267 "failed to get version %s: %m", path
);
270 if (strcmp(version
->name
, "amdgpu")) {
271 drmFreeVersion(version
);
274 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
277 return VK_ERROR_INCOMPATIBLE_DRIVER
;
279 drmFreeVersion(version
);
281 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
282 radv_logi("Found compatible device '%s'.", path
);
284 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
285 device
->instance
= instance
;
287 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
288 instance
->perftest_flags
);
290 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
294 if (instance
->enabled_extensions
.KHR_display
) {
295 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
296 if (master_fd
>= 0) {
297 uint32_t accel_working
= 0;
298 struct drm_amdgpu_info request
= {
299 .return_pointer
= (uintptr_t)&accel_working
,
300 .return_size
= sizeof(accel_working
),
301 .query
= AMDGPU_INFO_ACCEL_WORKING
304 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
311 device
->master_fd
= master_fd
;
312 device
->local_fd
= fd
;
313 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
315 radv_handle_env_var_force_family(device
);
317 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
319 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
320 device
->ws
->destroy(device
->ws
);
321 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
322 "cannot generate UUID");
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags
=
328 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
329 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
334 char buf
[VK_UUID_SIZE
* 2 + 1];
335 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
336 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
338 if (device
->rad_info
.chip_class
< GFX8
||
339 device
->rad_info
.chip_class
> GFX9
)
340 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
342 radv_get_driver_uuid(&device
->driver_uuid
);
343 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
345 if (device
->rad_info
.family
== CHIP_STONEY
||
346 device
->rad_info
.chip_class
>= GFX9
) {
347 device
->has_rbplus
= true;
348 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
349 device
->rad_info
.family
== CHIP_VEGA12
||
350 device
->rad_info
.family
== CHIP_RAVEN
||
351 device
->rad_info
.family
== CHIP_RAVEN2
;
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
357 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
359 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
363 device
->rad_info
.family
== CHIP_RAVEN
;
365 device
->has_tc_compat_zrange_bug
= device
->rad_info
.chip_class
< GFX10
;
367 /* Out-of-order primitive rasterization. */
368 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
369 device
->rad_info
.max_se
>= 2;
370 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
371 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
373 device
->dcc_msaa_allowed
=
374 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
378 (device
->rad_info
.chip_class
>= GFX8
&&
379 device
->rad_info
.me_fw_feature
>= 41);
381 device
->has_dcc_constant_encode
= device
->rad_info
.family
== CHIP_RAVEN2
||
382 device
->rad_info
.chip_class
>= GFX10
;
384 device
->use_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
386 /* Determine the number of threads per wave for all stages. */
387 device
->cs_wave_size
= 64;
388 device
->ps_wave_size
= 64;
389 device
->ge_wave_size
= 64;
391 if (device
->rad_info
.chip_class
>= GFX10
) {
392 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
393 device
->cs_wave_size
= 32;
395 /* For pixel shaders, wave64 is recommanded. */
396 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
397 device
->ps_wave_size
= 32;
399 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
400 device
->ge_wave_size
= 32;
403 radv_physical_device_init_mem_types(device
);
404 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
406 device
->bus_info
= *drm_device
->businfo
.pci
;
408 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
409 ac_print_gpu_info(&device
->rad_info
);
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
415 result
= radv_init_wsi(device
);
416 if (result
!= VK_SUCCESS
) {
417 device
->ws
->destroy(device
->ws
);
418 vk_error(instance
, result
);
432 radv_physical_device_finish(struct radv_physical_device
*device
)
434 radv_finish_wsi(device
);
435 device
->ws
->destroy(device
->ws
);
436 disk_cache_destroy(device
->disk_cache
);
437 close(device
->local_fd
);
438 if (device
->master_fd
!= -1)
439 close(device
->master_fd
);
443 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
444 VkSystemAllocationScope allocationScope
)
450 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
451 size_t align
, VkSystemAllocationScope allocationScope
)
453 return realloc(pOriginal
, size
);
457 default_free_func(void *pUserData
, void *pMemory
)
462 static const VkAllocationCallbacks default_alloc
= {
464 .pfnAllocation
= default_alloc_func
,
465 .pfnReallocation
= default_realloc_func
,
466 .pfnFree
= default_free_func
,
469 static const struct debug_control radv_debug_options
[] = {
470 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
471 {"nodcc", RADV_DEBUG_NO_DCC
},
472 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
473 {"nocache", RADV_DEBUG_NO_CACHE
},
474 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
475 {"nohiz", RADV_DEBUG_NO_HIZ
},
476 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
477 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
478 {"allbos", RADV_DEBUG_ALL_BOS
},
479 {"noibs", RADV_DEBUG_NO_IBS
},
480 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
481 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
482 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
483 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
484 {"nosisched", RADV_DEBUG_NO_SISCHED
},
485 {"preoptir", RADV_DEBUG_PREOPTIR
},
486 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
487 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
488 {"info", RADV_DEBUG_INFO
},
489 {"errors", RADV_DEBUG_ERRORS
},
490 {"startup", RADV_DEBUG_STARTUP
},
491 {"checkir", RADV_DEBUG_CHECKIR
},
492 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
493 {"nobinning", RADV_DEBUG_NOBINNING
},
494 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
495 {"nongg", RADV_DEBUG_NO_NGG
},
500 radv_get_debug_option_name(int id
)
502 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
503 return radv_debug_options
[id
].string
;
506 static const struct debug_control radv_perftest_options
[] = {
507 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
508 {"sisched", RADV_PERFTEST_SISCHED
},
509 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
510 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
511 {"bolist", RADV_PERFTEST_BO_LIST
},
512 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
513 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
514 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
515 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
516 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
517 {"storagedcc", RADV_PERFTEST_STORAGE_DCC
},
522 radv_get_perftest_option_name(int id
)
524 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
525 return radv_perftest_options
[id
].string
;
529 radv_handle_per_app_options(struct radv_instance
*instance
,
530 const VkApplicationInfo
*info
)
532 const char *name
= info
? info
->pApplicationName
: NULL
;
537 if (!strcmp(name
, "Talos - Linux - 32bit") ||
538 !strcmp(name
, "Talos - Linux - 64bit")) {
539 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
540 /* Force enable LLVM sisched for Talos because it looks
541 * safe and it gives few more FPS.
543 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
545 } else if (!strcmp(name
, "DOOM_VFR")) {
546 /* Work around a Doom VFR game bug */
547 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
548 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
549 /* Workaround for a WaW hazard when LLVM moves/merges
550 * load/store memory operations.
551 * See https://reviews.llvm.org/D61313
553 if (HAVE_LLVM
< 0x900)
554 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
558 static int radv_get_instance_extension_index(const char *name
)
560 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
561 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
567 static const char radv_dri_options_xml
[] =
569 DRI_CONF_SECTION_QUALITY
570 DRI_CONF_ADAPTIVE_SYNC("true")
574 static void radv_init_dri_options(struct radv_instance
*instance
)
576 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
577 driParseConfigFiles(&instance
->dri_options
,
578 &instance
->available_dri_options
,
582 VkResult
radv_CreateInstance(
583 const VkInstanceCreateInfo
* pCreateInfo
,
584 const VkAllocationCallbacks
* pAllocator
,
585 VkInstance
* pInstance
)
587 struct radv_instance
*instance
;
590 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
592 uint32_t client_version
;
593 if (pCreateInfo
->pApplicationInfo
&&
594 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
595 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
597 client_version
= VK_API_VERSION_1_0
;
600 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
601 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
603 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
605 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
608 instance
->alloc
= *pAllocator
;
610 instance
->alloc
= default_alloc
;
612 instance
->apiVersion
= client_version
;
613 instance
->physicalDeviceCount
= -1;
615 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
618 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
619 radv_perftest_options
);
622 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
623 radv_logi("Created an instance");
625 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
626 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
627 int index
= radv_get_instance_extension_index(ext_name
);
629 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
630 vk_free2(&default_alloc
, pAllocator
, instance
);
631 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
634 instance
->enabled_extensions
.extensions
[index
] = true;
637 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
638 if (result
!= VK_SUCCESS
) {
639 vk_free2(&default_alloc
, pAllocator
, instance
);
640 return vk_error(instance
, result
);
644 glsl_type_singleton_init_or_ref();
646 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
648 radv_init_dri_options(instance
);
649 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
651 *pInstance
= radv_instance_to_handle(instance
);
656 void radv_DestroyInstance(
657 VkInstance _instance
,
658 const VkAllocationCallbacks
* pAllocator
)
660 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
665 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
666 radv_physical_device_finish(instance
->physicalDevices
+ i
);
669 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
671 glsl_type_singleton_decref();
674 driDestroyOptionCache(&instance
->dri_options
);
675 driDestroyOptionInfo(&instance
->available_dri_options
);
677 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
679 vk_free(&instance
->alloc
, instance
);
683 radv_enumerate_devices(struct radv_instance
*instance
)
685 /* TODO: Check for more devices ? */
686 drmDevicePtr devices
[8];
687 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
690 instance
->physicalDeviceCount
= 0;
692 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
694 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
695 radv_logi("Found %d drm nodes", max_devices
);
698 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
700 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
701 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
702 devices
[i
]->bustype
== DRM_BUS_PCI
&&
703 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
705 result
= radv_physical_device_init(instance
->physicalDevices
+
706 instance
->physicalDeviceCount
,
709 if (result
== VK_SUCCESS
)
710 ++instance
->physicalDeviceCount
;
711 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
715 drmFreeDevices(devices
, max_devices
);
720 VkResult
radv_EnumeratePhysicalDevices(
721 VkInstance _instance
,
722 uint32_t* pPhysicalDeviceCount
,
723 VkPhysicalDevice
* pPhysicalDevices
)
725 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
728 if (instance
->physicalDeviceCount
< 0) {
729 result
= radv_enumerate_devices(instance
);
730 if (result
!= VK_SUCCESS
&&
731 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
735 if (!pPhysicalDevices
) {
736 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
738 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
739 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
740 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
743 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
747 VkResult
radv_EnumeratePhysicalDeviceGroups(
748 VkInstance _instance
,
749 uint32_t* pPhysicalDeviceGroupCount
,
750 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
752 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
755 if (instance
->physicalDeviceCount
< 0) {
756 result
= radv_enumerate_devices(instance
);
757 if (result
!= VK_SUCCESS
&&
758 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
762 if (!pPhysicalDeviceGroupProperties
) {
763 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
765 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
766 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
767 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
768 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
769 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
772 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
776 void radv_GetPhysicalDeviceFeatures(
777 VkPhysicalDevice physicalDevice
,
778 VkPhysicalDeviceFeatures
* pFeatures
)
780 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
781 memset(pFeatures
, 0, sizeof(*pFeatures
));
783 *pFeatures
= (VkPhysicalDeviceFeatures
) {
784 .robustBufferAccess
= true,
785 .fullDrawIndexUint32
= true,
786 .imageCubeArray
= true,
787 .independentBlend
= true,
788 .geometryShader
= true,
789 .tessellationShader
= true,
790 .sampleRateShading
= true,
791 .dualSrcBlend
= true,
793 .multiDrawIndirect
= true,
794 .drawIndirectFirstInstance
= true,
796 .depthBiasClamp
= true,
797 .fillModeNonSolid
= true,
802 .multiViewport
= true,
803 .samplerAnisotropy
= true,
804 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
805 .textureCompressionASTC_LDR
= false,
806 .textureCompressionBC
= true,
807 .occlusionQueryPrecise
= true,
808 .pipelineStatisticsQuery
= true,
809 .vertexPipelineStoresAndAtomics
= true,
810 .fragmentStoresAndAtomics
= true,
811 .shaderTessellationAndGeometryPointSize
= true,
812 .shaderImageGatherExtended
= true,
813 .shaderStorageImageExtendedFormats
= true,
814 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
815 .shaderUniformBufferArrayDynamicIndexing
= true,
816 .shaderSampledImageArrayDynamicIndexing
= true,
817 .shaderStorageBufferArrayDynamicIndexing
= true,
818 .shaderStorageImageArrayDynamicIndexing
= true,
819 .shaderStorageImageReadWithoutFormat
= true,
820 .shaderStorageImageWriteWithoutFormat
= true,
821 .shaderClipDistance
= true,
822 .shaderCullDistance
= true,
823 .shaderFloat64
= true,
825 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
826 .sparseBinding
= true,
827 .variableMultisampleRate
= true,
828 .inheritedQueries
= true,
832 void radv_GetPhysicalDeviceFeatures2(
833 VkPhysicalDevice physicalDevice
,
834 VkPhysicalDeviceFeatures2
*pFeatures
)
836 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
837 vk_foreach_struct(ext
, pFeatures
->pNext
) {
838 switch (ext
->sType
) {
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
840 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
841 features
->variablePointersStorageBuffer
= true;
842 features
->variablePointers
= true;
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
846 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
847 features
->multiview
= true;
848 features
->multiviewGeometryShader
= true;
849 features
->multiviewTessellationShader
= true;
852 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
853 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
854 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
855 features
->shaderDrawParameters
= true;
858 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
859 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
860 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
861 features
->protectedMemory
= false;
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
865 VkPhysicalDevice16BitStorageFeatures
*features
=
866 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
867 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
868 features
->storageBuffer16BitAccess
= enabled
;
869 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
870 features
->storagePushConstant16
= enabled
;
871 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
875 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
876 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
877 features
->samplerYcbcrConversion
= true;
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
881 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
882 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
883 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
884 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
885 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
886 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
887 features
->shaderSampledImageArrayNonUniformIndexing
= true;
888 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
889 features
->shaderStorageImageArrayNonUniformIndexing
= true;
890 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
891 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
892 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
893 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
894 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
895 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
896 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
897 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
898 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
899 features
->descriptorBindingUpdateUnusedWhilePending
= true;
900 features
->descriptorBindingPartiallyBound
= true;
901 features
->descriptorBindingVariableDescriptorCount
= true;
902 features
->runtimeDescriptorArray
= true;
905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
906 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
907 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
908 features
->conditionalRendering
= true;
909 features
->inheritedConditionalRendering
= false;
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
913 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
914 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
915 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
916 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
920 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
921 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
922 features
->transformFeedback
= true;
923 features
->geometryStreams
= true;
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
927 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
928 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
929 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
933 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
934 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
935 features
->memoryPriority
= VK_TRUE
;
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
939 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
940 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
941 features
->bufferDeviceAddress
= true;
942 features
->bufferDeviceAddressCaptureReplay
= false;
943 features
->bufferDeviceAddressMultiDevice
= false;
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
947 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
948 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
949 features
->depthClipEnable
= true;
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
953 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
954 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
955 features
->hostQueryReset
= true;
958 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
959 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
960 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
961 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
962 features
->storageBuffer8BitAccess
= enabled
;
963 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
964 features
->storagePushConstant8
= enabled
;
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
968 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
969 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
970 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
971 features
->shaderInt8
= true;
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
975 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
976 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
977 features
->shaderBufferInt64Atomics
= HAVE_LLVM
>= 0x0900;
978 features
->shaderSharedInt64Atomics
= HAVE_LLVM
>= 0x0900;
981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
982 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
983 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
985 features
->inlineUniformBlock
= true;
986 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
990 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
991 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
992 features
->computeDerivativeGroupQuads
= false;
993 features
->computeDerivativeGroupLinear
= true;
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
997 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
998 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
999 features
->ycbcrImageArrays
= true;
1002 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
1003 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
1004 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
1005 features
->uniformBufferStandardLayout
= true;
1008 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1009 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1010 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1011 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1014 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR
: {
1015 VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*features
=
1016 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*)ext
;
1017 features
->imagelessFramebuffer
= true;
1024 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1027 void radv_GetPhysicalDeviceProperties(
1028 VkPhysicalDevice physicalDevice
,
1029 VkPhysicalDeviceProperties
* pProperties
)
1031 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1032 VkSampleCountFlags sample_counts
= 0xf;
1034 /* make sure that the entire descriptor set is addressable with a signed
1035 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1036 * be at most 2 GiB. the combined image & samples object count as one of
1037 * both. This limit is for the pipeline layout, not for the set layout, but
1038 * there is no set limit, so we just set a pipeline limit. I don't think
1039 * any app is going to hit this soon. */
1040 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1041 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1042 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1043 32 /* sampler, largest when combined with image */ +
1044 64 /* sampled image */ +
1045 64 /* storage image */);
1047 VkPhysicalDeviceLimits limits
= {
1048 .maxImageDimension1D
= (1 << 14),
1049 .maxImageDimension2D
= (1 << 14),
1050 .maxImageDimension3D
= (1 << 11),
1051 .maxImageDimensionCube
= (1 << 14),
1052 .maxImageArrayLayers
= (1 << 11),
1053 .maxTexelBufferElements
= 128 * 1024 * 1024,
1054 .maxUniformBufferRange
= UINT32_MAX
,
1055 .maxStorageBufferRange
= UINT32_MAX
,
1056 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1057 .maxMemoryAllocationCount
= UINT32_MAX
,
1058 .maxSamplerAllocationCount
= 64 * 1024,
1059 .bufferImageGranularity
= 64, /* A cache line */
1060 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1061 .maxBoundDescriptorSets
= MAX_SETS
,
1062 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1063 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1064 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1065 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1066 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1067 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1068 .maxPerStageResources
= max_descriptor_set_size
,
1069 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1070 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1071 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1072 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1073 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1074 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1075 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1076 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1077 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1078 .maxVertexInputBindings
= MAX_VBS
,
1079 .maxVertexInputAttributeOffset
= 2047,
1080 .maxVertexInputBindingStride
= 2048,
1081 .maxVertexOutputComponents
= 128,
1082 .maxTessellationGenerationLevel
= 64,
1083 .maxTessellationPatchSize
= 32,
1084 .maxTessellationControlPerVertexInputComponents
= 128,
1085 .maxTessellationControlPerVertexOutputComponents
= 128,
1086 .maxTessellationControlPerPatchOutputComponents
= 120,
1087 .maxTessellationControlTotalOutputComponents
= 4096,
1088 .maxTessellationEvaluationInputComponents
= 128,
1089 .maxTessellationEvaluationOutputComponents
= 128,
1090 .maxGeometryShaderInvocations
= 127,
1091 .maxGeometryInputComponents
= 64,
1092 .maxGeometryOutputComponents
= 128,
1093 .maxGeometryOutputVertices
= 256,
1094 .maxGeometryTotalOutputComponents
= 1024,
1095 .maxFragmentInputComponents
= 128,
1096 .maxFragmentOutputAttachments
= 8,
1097 .maxFragmentDualSrcAttachments
= 1,
1098 .maxFragmentCombinedOutputResources
= 8,
1099 .maxComputeSharedMemorySize
= 32768,
1100 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1101 .maxComputeWorkGroupInvocations
= 2048,
1102 .maxComputeWorkGroupSize
= {
1107 .subPixelPrecisionBits
= 8,
1108 .subTexelPrecisionBits
= 8,
1109 .mipmapPrecisionBits
= 8,
1110 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1111 .maxDrawIndirectCount
= UINT32_MAX
,
1112 .maxSamplerLodBias
= 16,
1113 .maxSamplerAnisotropy
= 16,
1114 .maxViewports
= MAX_VIEWPORTS
,
1115 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1116 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1117 .viewportSubPixelBits
= 8,
1118 .minMemoryMapAlignment
= 4096, /* A page */
1119 .minTexelBufferOffsetAlignment
= 1,
1120 .minUniformBufferOffsetAlignment
= 4,
1121 .minStorageBufferOffsetAlignment
= 4,
1122 .minTexelOffset
= -32,
1123 .maxTexelOffset
= 31,
1124 .minTexelGatherOffset
= -32,
1125 .maxTexelGatherOffset
= 31,
1126 .minInterpolationOffset
= -2,
1127 .maxInterpolationOffset
= 2,
1128 .subPixelInterpolationOffsetBits
= 8,
1129 .maxFramebufferWidth
= (1 << 14),
1130 .maxFramebufferHeight
= (1 << 14),
1131 .maxFramebufferLayers
= (1 << 10),
1132 .framebufferColorSampleCounts
= sample_counts
,
1133 .framebufferDepthSampleCounts
= sample_counts
,
1134 .framebufferStencilSampleCounts
= sample_counts
,
1135 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1136 .maxColorAttachments
= MAX_RTS
,
1137 .sampledImageColorSampleCounts
= sample_counts
,
1138 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1139 .sampledImageDepthSampleCounts
= sample_counts
,
1140 .sampledImageStencilSampleCounts
= sample_counts
,
1141 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1142 .maxSampleMaskWords
= 1,
1143 .timestampComputeAndGraphics
= true,
1144 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1145 .maxClipDistances
= 8,
1146 .maxCullDistances
= 8,
1147 .maxCombinedClipAndCullDistances
= 8,
1148 .discreteQueuePriorities
= 2,
1149 .pointSizeRange
= { 0.0, 8192.0 },
1150 .lineWidthRange
= { 0.0, 7.9921875 },
1151 .pointSizeGranularity
= (1.0 / 8.0),
1152 .lineWidthGranularity
= (1.0 / 128.0),
1153 .strictLines
= false, /* FINISHME */
1154 .standardSampleLocations
= true,
1155 .optimalBufferCopyOffsetAlignment
= 128,
1156 .optimalBufferCopyRowPitchAlignment
= 128,
1157 .nonCoherentAtomSize
= 64,
1160 *pProperties
= (VkPhysicalDeviceProperties
) {
1161 .apiVersion
= radv_physical_device_api_version(pdevice
),
1162 .driverVersion
= vk_get_driver_version(),
1163 .vendorID
= ATI_VENDOR_ID
,
1164 .deviceID
= pdevice
->rad_info
.pci_id
,
1165 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1167 .sparseProperties
= {0},
1170 strcpy(pProperties
->deviceName
, pdevice
->name
);
1171 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1174 void radv_GetPhysicalDeviceProperties2(
1175 VkPhysicalDevice physicalDevice
,
1176 VkPhysicalDeviceProperties2
*pProperties
)
1178 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1179 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1181 vk_foreach_struct(ext
, pProperties
->pNext
) {
1182 switch (ext
->sType
) {
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1184 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1185 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1186 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1190 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1191 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1192 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1193 properties
->deviceLUIDValid
= false;
1196 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1197 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1198 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1199 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1202 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1203 VkPhysicalDevicePointClippingProperties
*properties
=
1204 (VkPhysicalDevicePointClippingProperties
*)ext
;
1205 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1209 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1210 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1211 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1214 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1215 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1216 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1217 properties
->minImportedHostPointerAlignment
= 4096;
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1221 VkPhysicalDeviceSubgroupProperties
*properties
=
1222 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1223 properties
->subgroupSize
= 64;
1224 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1225 properties
->supportedOperations
=
1226 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1227 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1228 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1229 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1230 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1231 properties
->supportedOperations
|=
1232 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1233 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1234 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1236 properties
->quadOperationsInAllStages
= true;
1239 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1240 VkPhysicalDeviceMaintenance3Properties
*properties
=
1241 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1242 /* Make sure everything is addressable by a signed 32-bit int, and
1243 * our largest descriptors are 96 bytes. */
1244 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1245 /* Our buffer size fields allow only this much */
1246 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1250 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1251 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1252 /* GFX6-8 only support single channel min/max filter. */
1253 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1254 properties
->filterMinmaxSingleComponentFormats
= true;
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1258 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1259 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1261 /* Shader engines. */
1262 properties
->shaderEngineCount
=
1263 pdevice
->rad_info
.max_se
;
1264 properties
->shaderArraysPerEngineCount
=
1265 pdevice
->rad_info
.max_sh_per_se
;
1266 properties
->computeUnitsPerShaderArray
=
1267 pdevice
->rad_info
.num_good_cu_per_sh
;
1268 properties
->simdPerComputeUnit
= 4;
1269 properties
->wavefrontsPerSimd
=
1270 pdevice
->rad_info
.family
== CHIP_TONGA
||
1271 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1272 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1273 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1274 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1275 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1276 properties
->wavefrontSize
= 64;
1279 properties
->sgprsPerSimd
=
1280 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1281 properties
->minSgprAllocation
=
1282 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1283 properties
->maxSgprAllocation
=
1284 pdevice
->rad_info
.family
== CHIP_TONGA
||
1285 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1286 properties
->sgprAllocationGranularity
=
1287 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1290 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1291 properties
->minVgprAllocation
= 4;
1292 properties
->maxVgprAllocation
= 256;
1293 properties
->vgprAllocationGranularity
= 4;
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1297 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1298 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1299 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1303 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1304 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1305 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1306 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1307 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1308 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1309 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1310 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1311 properties
->robustBufferAccessUpdateAfterBind
= false;
1312 properties
->quadDivergentImplicitLod
= false;
1314 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1315 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1316 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1317 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1318 32 /* sampler, largest when combined with image */ +
1319 64 /* sampled image */ +
1320 64 /* storage image */);
1321 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1322 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1323 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1324 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1325 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1326 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1327 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1328 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1329 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1330 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1331 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1332 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1333 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1334 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1335 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1338 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1339 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1340 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1341 properties
->protectedNoFault
= false;
1344 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1345 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1346 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1347 properties
->primitiveOverestimationSize
= 0;
1348 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1349 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1350 properties
->primitiveUnderestimation
= VK_FALSE
;
1351 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1352 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1353 properties
->degenerateLinesRasterized
= VK_FALSE
;
1354 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1355 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1358 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1359 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1360 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1361 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1362 properties
->pciBus
= pdevice
->bus_info
.bus
;
1363 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1364 properties
->pciFunction
= pdevice
->bus_info
.func
;
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1368 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1369 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1371 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1372 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE_KHR
, "radv");
1373 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1374 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1375 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1377 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1385 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1386 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1387 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1388 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1389 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1390 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1391 properties
->maxTransformFeedbackStreamDataSize
= 512;
1392 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1393 properties
->maxTransformFeedbackBufferDataStride
= 512;
1394 properties
->transformFeedbackQueries
= true;
1395 properties
->transformFeedbackStreamsLinesTriangles
= true;
1396 properties
->transformFeedbackRasterizationStreamSelect
= false;
1397 properties
->transformFeedbackDraw
= true;
1400 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1401 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1402 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1404 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1405 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1406 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1407 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1408 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1411 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1412 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1413 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1414 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1415 VK_SAMPLE_COUNT_4_BIT
|
1416 VK_SAMPLE_COUNT_8_BIT
;
1417 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1418 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1419 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1420 properties
->sampleLocationSubPixelBits
= 4;
1421 properties
->variableSampleLocations
= VK_FALSE
;
1424 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1425 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1426 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1428 /* We support all of the depth resolve modes */
1429 properties
->supportedDepthResolveModes
=
1430 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1431 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1432 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1433 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1435 /* Average doesn't make sense for stencil so we don't support that */
1436 properties
->supportedStencilResolveModes
=
1437 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1438 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1439 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1441 properties
->independentResolveNone
= VK_TRUE
;
1442 properties
->independentResolve
= VK_TRUE
;
1451 static void radv_get_physical_device_queue_family_properties(
1452 struct radv_physical_device
* pdevice
,
1454 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1456 int num_queue_families
= 1;
1458 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1459 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1460 num_queue_families
++;
1462 if (pQueueFamilyProperties
== NULL
) {
1463 *pCount
= num_queue_families
;
1472 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1473 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1474 VK_QUEUE_COMPUTE_BIT
|
1475 VK_QUEUE_TRANSFER_BIT
|
1476 VK_QUEUE_SPARSE_BINDING_BIT
,
1478 .timestampValidBits
= 64,
1479 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1484 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1485 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1486 if (*pCount
> idx
) {
1487 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1488 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1489 VK_QUEUE_TRANSFER_BIT
|
1490 VK_QUEUE_SPARSE_BINDING_BIT
,
1491 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1492 .timestampValidBits
= 64,
1493 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1501 void radv_GetPhysicalDeviceQueueFamilyProperties(
1502 VkPhysicalDevice physicalDevice
,
1504 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1506 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1507 if (!pQueueFamilyProperties
) {
1508 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1511 VkQueueFamilyProperties
*properties
[] = {
1512 pQueueFamilyProperties
+ 0,
1513 pQueueFamilyProperties
+ 1,
1514 pQueueFamilyProperties
+ 2,
1516 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1517 assert(*pCount
<= 3);
1520 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1521 VkPhysicalDevice physicalDevice
,
1523 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1525 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1526 if (!pQueueFamilyProperties
) {
1527 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1530 VkQueueFamilyProperties
*properties
[] = {
1531 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1532 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1533 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1535 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1536 assert(*pCount
<= 3);
1539 void radv_GetPhysicalDeviceMemoryProperties(
1540 VkPhysicalDevice physicalDevice
,
1541 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1543 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1545 *pMemoryProperties
= physical_device
->memory_properties
;
1549 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1550 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1552 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1553 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1554 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1555 uint64_t vram_size
= radv_get_vram_size(device
);
1556 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1557 uint64_t heap_budget
, heap_usage
;
1559 /* For all memory heaps, the computation of budget is as follow:
1560 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1562 * The Vulkan spec 1.1.97 says that the budget should include any
1563 * currently allocated device memory.
1565 * Note that the application heap usages are not really accurate (eg.
1566 * in presence of shared buffers).
1568 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1569 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1571 switch (device
->mem_type_indices
[i
]) {
1572 case RADV_MEM_TYPE_VRAM
:
1573 heap_usage
= device
->ws
->query_value(device
->ws
,
1574 RADEON_ALLOCATED_VRAM
);
1576 heap_budget
= vram_size
-
1577 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1580 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1581 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1583 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1584 heap_usage
= device
->ws
->query_value(device
->ws
,
1585 RADEON_ALLOCATED_VRAM_VIS
);
1587 heap_budget
= visible_vram_size
-
1588 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1591 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1592 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1594 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1595 heap_usage
= device
->ws
->query_value(device
->ws
,
1596 RADEON_ALLOCATED_GTT
);
1598 heap_budget
= gtt_size
-
1599 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1602 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1603 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1610 /* The heapBudget and heapUsage values must be zero for array elements
1611 * greater than or equal to
1612 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1614 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1615 memoryBudget
->heapBudget
[i
] = 0;
1616 memoryBudget
->heapUsage
[i
] = 0;
1620 void radv_GetPhysicalDeviceMemoryProperties2(
1621 VkPhysicalDevice physicalDevice
,
1622 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1624 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1625 &pMemoryProperties
->memoryProperties
);
1627 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1628 vk_find_struct(pMemoryProperties
->pNext
,
1629 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1631 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1634 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1636 VkExternalMemoryHandleTypeFlagBits handleType
,
1637 const void *pHostPointer
,
1638 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1640 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1644 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1645 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1646 uint32_t memoryTypeBits
= 0;
1647 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1648 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1649 memoryTypeBits
= (1 << i
);
1653 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1657 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1661 static enum radeon_ctx_priority
1662 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1664 /* Default to MEDIUM when a specific global priority isn't requested */
1666 return RADEON_CTX_PRIORITY_MEDIUM
;
1668 switch(pObj
->globalPriority
) {
1669 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1670 return RADEON_CTX_PRIORITY_REALTIME
;
1671 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1672 return RADEON_CTX_PRIORITY_HIGH
;
1673 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1674 return RADEON_CTX_PRIORITY_MEDIUM
;
1675 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1676 return RADEON_CTX_PRIORITY_LOW
;
1678 unreachable("Illegal global priority value");
1679 return RADEON_CTX_PRIORITY_INVALID
;
1684 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1685 uint32_t queue_family_index
, int idx
,
1686 VkDeviceQueueCreateFlags flags
,
1687 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1689 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1690 queue
->device
= device
;
1691 queue
->queue_family_index
= queue_family_index
;
1692 queue
->queue_idx
= idx
;
1693 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1694 queue
->flags
= flags
;
1696 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1698 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1704 radv_queue_finish(struct radv_queue
*queue
)
1707 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1709 if (queue
->initial_full_flush_preamble_cs
)
1710 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1711 if (queue
->initial_preamble_cs
)
1712 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1713 if (queue
->continue_preamble_cs
)
1714 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1715 if (queue
->descriptor_bo
)
1716 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1717 if (queue
->scratch_bo
)
1718 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1719 if (queue
->esgs_ring_bo
)
1720 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1721 if (queue
->gsvs_ring_bo
)
1722 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1723 if (queue
->tess_rings_bo
)
1724 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1725 if (queue
->compute_scratch_bo
)
1726 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1730 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1732 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1733 bo_list
->list
.count
= bo_list
->capacity
= 0;
1734 bo_list
->list
.bos
= NULL
;
1738 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1740 free(bo_list
->list
.bos
);
1741 pthread_mutex_destroy(&bo_list
->mutex
);
1744 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1745 struct radeon_winsys_bo
*bo
)
1747 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1752 if (unlikely(!device
->use_global_bo_list
))
1755 pthread_mutex_lock(&bo_list
->mutex
);
1756 if (bo_list
->list
.count
== bo_list
->capacity
) {
1757 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1758 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1761 pthread_mutex_unlock(&bo_list
->mutex
);
1762 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1765 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1766 bo_list
->capacity
= capacity
;
1769 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1770 pthread_mutex_unlock(&bo_list
->mutex
);
1774 static void radv_bo_list_remove(struct radv_device
*device
,
1775 struct radeon_winsys_bo
*bo
)
1777 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1782 if (unlikely(!device
->use_global_bo_list
))
1785 pthread_mutex_lock(&bo_list
->mutex
);
1786 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1787 if (bo_list
->list
.bos
[i
] == bo
) {
1788 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1789 --bo_list
->list
.count
;
1793 pthread_mutex_unlock(&bo_list
->mutex
);
1797 radv_device_init_gs_info(struct radv_device
*device
)
1799 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1800 device
->physical_device
->rad_info
.family
);
1803 static int radv_get_device_extension_index(const char *name
)
1805 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1806 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1813 radv_get_int_debug_option(const char *name
, int default_value
)
1820 result
= default_value
;
1824 result
= strtol(str
, &endptr
, 0);
1825 if (str
== endptr
) {
1826 /* No digits founs. */
1827 result
= default_value
;
1834 VkResult
radv_CreateDevice(
1835 VkPhysicalDevice physicalDevice
,
1836 const VkDeviceCreateInfo
* pCreateInfo
,
1837 const VkAllocationCallbacks
* pAllocator
,
1840 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1842 struct radv_device
*device
;
1844 bool keep_shader_info
= false;
1846 /* Check enabled features */
1847 if (pCreateInfo
->pEnabledFeatures
) {
1848 VkPhysicalDeviceFeatures supported_features
;
1849 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1850 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1851 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1852 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1853 for (uint32_t i
= 0; i
< num_features
; i
++) {
1854 if (enabled_feature
[i
] && !supported_feature
[i
])
1855 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1859 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1861 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1863 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1865 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1866 device
->instance
= physical_device
->instance
;
1867 device
->physical_device
= physical_device
;
1869 device
->ws
= physical_device
->ws
;
1871 device
->alloc
= *pAllocator
;
1873 device
->alloc
= physical_device
->instance
->alloc
;
1875 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1876 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1877 int index
= radv_get_device_extension_index(ext_name
);
1878 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1879 vk_free(&device
->alloc
, device
);
1880 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1883 device
->enabled_extensions
.extensions
[index
] = true;
1886 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1888 /* With update after bind we can't attach bo's to the command buffer
1889 * from the descriptor set anymore, so we have to use a global BO list.
1891 device
->use_global_bo_list
=
1892 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1893 device
->enabled_extensions
.EXT_descriptor_indexing
||
1894 device
->enabled_extensions
.EXT_buffer_device_address
;
1896 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
1897 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
1899 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1900 list_inithead(&device
->shader_slabs
);
1902 radv_bo_list_init(&device
->bo_list
);
1904 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1905 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1906 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1907 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1908 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1910 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1912 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1913 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1914 if (!device
->queues
[qfi
]) {
1915 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1919 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1921 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1923 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1924 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1925 qfi
, q
, queue_create
->flags
,
1927 if (result
!= VK_SUCCESS
)
1932 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1933 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1935 /* Disabled and not implemented for now. */
1936 device
->dfsm_allowed
= device
->pbb_allowed
&&
1937 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1938 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1941 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1944 /* The maximum number of scratch waves. Scratch space isn't divided
1945 * evenly between CUs. The number is only a function of the number of CUs.
1946 * We can decrease the constant to decrease the scratch buffer size.
1948 * sctx->scratch_waves must be >= the maximum possible size of
1949 * 1 threadgroup, so that the hw doesn't hang from being unable
1952 * The recommended value is 4 per CU at most. Higher numbers don't
1953 * bring much benefit, but they still occupy chip resources (think
1954 * async compute). I've seen ~2% performance difference between 4 and 32.
1956 uint32_t max_threads_per_block
= 2048;
1957 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1958 max_threads_per_block
/ 64);
1960 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
1961 S_00B800_CS_W32_EN(device
->physical_device
->cs_wave_size
== 32);
1963 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1964 /* If the KMD allows it (there is a KMD hw register for it),
1965 * allow launching waves out-of-order.
1967 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1970 radv_device_init_gs_info(device
);
1972 device
->tess_offchip_block_dw_size
=
1973 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1974 device
->has_distributed_tess
=
1975 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1976 device
->physical_device
->rad_info
.max_se
>= 2;
1978 if (getenv("RADV_TRACE_FILE")) {
1979 const char *filename
= getenv("RADV_TRACE_FILE");
1981 keep_shader_info
= true;
1983 if (!radv_init_trace(device
))
1986 fprintf(stderr
, "*****************************************************************************\n");
1987 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1988 fprintf(stderr
, "*****************************************************************************\n");
1990 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1991 radv_dump_enabled_options(device
, stderr
);
1994 device
->keep_shader_info
= keep_shader_info
;
1996 result
= radv_device_init_meta(device
);
1997 if (result
!= VK_SUCCESS
)
2000 radv_device_init_msaa(device
);
2002 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2003 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2005 case RADV_QUEUE_GENERAL
:
2006 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2007 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2008 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2010 case RADV_QUEUE_COMPUTE
:
2011 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2012 radeon_emit(device
->empty_cs
[family
], 0);
2015 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2018 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2019 cik_create_gfx_config(device
);
2021 VkPipelineCacheCreateInfo ci
;
2022 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2025 ci
.pInitialData
= NULL
;
2026 ci
.initialDataSize
= 0;
2028 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2030 if (result
!= VK_SUCCESS
)
2033 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2035 device
->force_aniso
=
2036 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2037 if (device
->force_aniso
>= 0) {
2038 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2039 1 << util_logbase2(device
->force_aniso
));
2042 *pDevice
= radv_device_to_handle(device
);
2046 radv_device_finish_meta(device
);
2048 radv_bo_list_finish(&device
->bo_list
);
2050 if (device
->trace_bo
)
2051 device
->ws
->buffer_destroy(device
->trace_bo
);
2053 if (device
->gfx_init
)
2054 device
->ws
->buffer_destroy(device
->gfx_init
);
2056 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2057 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2058 radv_queue_finish(&device
->queues
[i
][q
]);
2059 if (device
->queue_count
[i
])
2060 vk_free(&device
->alloc
, device
->queues
[i
]);
2063 vk_free(&device
->alloc
, device
);
2067 void radv_DestroyDevice(
2069 const VkAllocationCallbacks
* pAllocator
)
2071 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2076 if (device
->trace_bo
)
2077 device
->ws
->buffer_destroy(device
->trace_bo
);
2079 if (device
->gfx_init
)
2080 device
->ws
->buffer_destroy(device
->gfx_init
);
2082 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2083 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2084 radv_queue_finish(&device
->queues
[i
][q
]);
2085 if (device
->queue_count
[i
])
2086 vk_free(&device
->alloc
, device
->queues
[i
]);
2087 if (device
->empty_cs
[i
])
2088 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2090 radv_device_finish_meta(device
);
2092 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2093 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2095 radv_destroy_shader_slabs(device
);
2097 radv_bo_list_finish(&device
->bo_list
);
2098 vk_free(&device
->alloc
, device
);
2101 VkResult
radv_EnumerateInstanceLayerProperties(
2102 uint32_t* pPropertyCount
,
2103 VkLayerProperties
* pProperties
)
2105 if (pProperties
== NULL
) {
2106 *pPropertyCount
= 0;
2110 /* None supported at this time */
2111 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2114 VkResult
radv_EnumerateDeviceLayerProperties(
2115 VkPhysicalDevice physicalDevice
,
2116 uint32_t* pPropertyCount
,
2117 VkLayerProperties
* pProperties
)
2119 if (pProperties
== NULL
) {
2120 *pPropertyCount
= 0;
2124 /* None supported at this time */
2125 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2128 void radv_GetDeviceQueue2(
2130 const VkDeviceQueueInfo2
* pQueueInfo
,
2133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2134 struct radv_queue
*queue
;
2136 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2137 if (pQueueInfo
->flags
!= queue
->flags
) {
2138 /* From the Vulkan 1.1.70 spec:
2140 * "The queue returned by vkGetDeviceQueue2 must have the same
2141 * flags value from this structure as that used at device
2142 * creation time in a VkDeviceQueueCreateInfo instance. If no
2143 * matching flags were specified at device creation time then
2144 * pQueue will return VK_NULL_HANDLE."
2146 *pQueue
= VK_NULL_HANDLE
;
2150 *pQueue
= radv_queue_to_handle(queue
);
2153 void radv_GetDeviceQueue(
2155 uint32_t queueFamilyIndex
,
2156 uint32_t queueIndex
,
2159 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2160 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2161 .queueFamilyIndex
= queueFamilyIndex
,
2162 .queueIndex
= queueIndex
2165 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2169 fill_geom_tess_rings(struct radv_queue
*queue
,
2171 bool add_sample_positions
,
2172 uint32_t esgs_ring_size
,
2173 struct radeon_winsys_bo
*esgs_ring_bo
,
2174 uint32_t gsvs_ring_size
,
2175 struct radeon_winsys_bo
*gsvs_ring_bo
,
2176 uint32_t tess_factor_ring_size
,
2177 uint32_t tess_offchip_ring_offset
,
2178 uint32_t tess_offchip_ring_size
,
2179 struct radeon_winsys_bo
*tess_rings_bo
)
2181 uint32_t *desc
= &map
[4];
2184 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2186 /* stride 0, num records - size, add tid, swizzle, elsize4,
2189 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2190 S_008F04_SWIZZLE_ENABLE(true);
2191 desc
[2] = esgs_ring_size
;
2192 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2193 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2194 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2195 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2196 S_008F0C_INDEX_STRIDE(3) |
2197 S_008F0C_ADD_TID_ENABLE(1);
2199 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2200 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2201 S_008F0C_OOB_SELECT(2) |
2202 S_008F0C_RESOURCE_LEVEL(1);
2204 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2205 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2206 S_008F0C_ELEMENT_SIZE(1);
2209 /* GS entry for ES->GS ring */
2210 /* stride 0, num records - size, elsize0,
2213 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2214 desc
[6] = esgs_ring_size
;
2215 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2216 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2217 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2218 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2220 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2221 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2222 S_008F0C_OOB_SELECT(2) |
2223 S_008F0C_RESOURCE_LEVEL(1);
2225 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2233 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2235 /* VS entry for GS->VS ring */
2236 /* stride 0, num records - size, elsize0,
2239 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2240 desc
[2] = gsvs_ring_size
;
2241 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2242 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2243 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2244 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2246 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2247 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2248 S_008F0C_OOB_SELECT(2) |
2249 S_008F0C_RESOURCE_LEVEL(1);
2251 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2252 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2255 /* stride gsvs_itemsize, num records 64
2256 elsize 4, index stride 16 */
2257 /* shader will patch stride and desc[2] */
2259 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
2260 S_008F04_SWIZZLE_ENABLE(1);
2262 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2263 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2264 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2265 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2266 S_008F0C_INDEX_STRIDE(1) |
2267 S_008F0C_ADD_TID_ENABLE(true);
2269 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2270 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2271 S_008F0C_OOB_SELECT(2) |
2272 S_008F0C_RESOURCE_LEVEL(1);
2274 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2275 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2276 S_008F0C_ELEMENT_SIZE(1);
2283 if (tess_rings_bo
) {
2284 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2285 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2288 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
2289 desc
[2] = tess_factor_ring_size
;
2290 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2291 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2292 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2293 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2295 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2296 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2297 S_008F0C_OOB_SELECT(3) |
2298 S_008F0C_RESOURCE_LEVEL(1);
2300 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2301 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2304 desc
[4] = tess_offchip_va
;
2305 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
2306 desc
[6] = tess_offchip_ring_size
;
2307 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2308 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2309 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2310 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2312 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2313 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2314 S_008F0C_OOB_SELECT(3) |
2315 S_008F0C_RESOURCE_LEVEL(1);
2317 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2318 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2324 if (add_sample_positions
) {
2325 /* add sample positions after all rings */
2326 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2328 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2330 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2332 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2337 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2339 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2340 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2341 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2342 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2343 unsigned max_offchip_buffers
;
2344 unsigned offchip_granularity
;
2345 unsigned hs_offchip_param
;
2349 * This must be one less than the maximum number due to a hw limitation.
2350 * Various hardware bugs need thGFX7
2353 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2354 * Gfx7 should limit max_offchip_buffers to 508
2355 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2357 * Follow AMDVLK here.
2359 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2360 max_offchip_buffers_per_se
= 256;
2361 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2362 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2363 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2364 --max_offchip_buffers_per_se
;
2366 max_offchip_buffers
= max_offchip_buffers_per_se
*
2367 device
->physical_device
->rad_info
.max_se
;
2369 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2370 * around by setting 4K granularity.
2372 if (device
->tess_offchip_block_dw_size
== 4096) {
2373 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2374 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2376 assert(device
->tess_offchip_block_dw_size
== 8192);
2377 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2380 switch (device
->physical_device
->rad_info
.chip_class
) {
2382 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2387 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2395 *max_offchip_buffers_p
= max_offchip_buffers
;
2396 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2397 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2398 --max_offchip_buffers
;
2400 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2401 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2404 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2406 return hs_offchip_param
;
2410 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2411 struct radeon_winsys_bo
*esgs_ring_bo
,
2412 uint32_t esgs_ring_size
,
2413 struct radeon_winsys_bo
*gsvs_ring_bo
,
2414 uint32_t gsvs_ring_size
)
2416 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2420 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2423 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2425 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2426 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2427 radeon_emit(cs
, esgs_ring_size
>> 8);
2428 radeon_emit(cs
, gsvs_ring_size
>> 8);
2430 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2431 radeon_emit(cs
, esgs_ring_size
>> 8);
2432 radeon_emit(cs
, gsvs_ring_size
>> 8);
2437 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2438 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2439 struct radeon_winsys_bo
*tess_rings_bo
)
2446 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2448 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2450 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2451 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2452 S_030938_SIZE(tf_ring_size
/ 4));
2453 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2456 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2457 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2458 S_030984_BASE_HI(tf_va
>> 40));
2459 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2460 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2461 S_030944_BASE_HI(tf_va
>> 40));
2463 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2466 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2467 S_008988_SIZE(tf_ring_size
/ 4));
2468 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2470 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2476 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2477 struct radeon_winsys_bo
*compute_scratch_bo
)
2479 uint64_t scratch_va
;
2481 if (!compute_scratch_bo
)
2484 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2486 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2488 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2489 radeon_emit(cs
, scratch_va
);
2490 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2491 S_008F04_SWIZZLE_ENABLE(1));
2495 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2496 struct radeon_cmdbuf
*cs
,
2497 struct radeon_winsys_bo
*descriptor_bo
)
2504 va
= radv_buffer_get_va(descriptor_bo
);
2506 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2508 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2509 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2510 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2511 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2512 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2514 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2515 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2518 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2519 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2520 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2521 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2522 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2524 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2525 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2529 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2530 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2531 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2532 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2533 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2534 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2536 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2537 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2544 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2546 struct radv_device
*device
= queue
->device
;
2548 if (device
->gfx_init
) {
2549 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2551 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2552 radeon_emit(cs
, va
);
2553 radeon_emit(cs
, va
>> 32);
2554 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2556 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2558 struct radv_physical_device
*physical_device
= device
->physical_device
;
2559 si_emit_graphics(physical_device
, cs
);
2564 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2566 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2567 si_emit_compute(physical_device
, cs
);
2571 radv_get_preamble_cs(struct radv_queue
*queue
,
2572 uint32_t scratch_size
,
2573 uint32_t compute_scratch_size
,
2574 uint32_t esgs_ring_size
,
2575 uint32_t gsvs_ring_size
,
2576 bool needs_tess_rings
,
2577 bool needs_sample_positions
,
2578 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2579 struct radeon_cmdbuf
**initial_preamble_cs
,
2580 struct radeon_cmdbuf
**continue_preamble_cs
)
2582 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2583 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2584 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2585 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2586 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2587 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2588 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2589 bool add_tess_rings
= false, add_sample_positions
= false;
2590 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2591 unsigned max_offchip_buffers
;
2592 unsigned hs_offchip_param
= 0;
2593 unsigned tess_offchip_ring_offset
;
2594 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2595 if (!queue
->has_tess_rings
) {
2596 if (needs_tess_rings
)
2597 add_tess_rings
= true;
2599 if (!queue
->has_sample_positions
) {
2600 if (needs_sample_positions
)
2601 add_sample_positions
= true;
2603 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2604 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2605 &max_offchip_buffers
);
2606 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2607 tess_offchip_ring_size
= max_offchip_buffers
*
2608 queue
->device
->tess_offchip_block_dw_size
* 4;
2610 if (scratch_size
<= queue
->scratch_size
&&
2611 compute_scratch_size
<= queue
->compute_scratch_size
&&
2612 esgs_ring_size
<= queue
->esgs_ring_size
&&
2613 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2614 !add_tess_rings
&& !add_sample_positions
&&
2615 queue
->initial_preamble_cs
) {
2616 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2617 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2618 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2619 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2620 *continue_preamble_cs
= NULL
;
2624 if (scratch_size
> queue
->scratch_size
) {
2625 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2630 RADV_BO_PRIORITY_SCRATCH
);
2634 scratch_bo
= queue
->scratch_bo
;
2636 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2637 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2638 compute_scratch_size
,
2642 RADV_BO_PRIORITY_SCRATCH
);
2643 if (!compute_scratch_bo
)
2647 compute_scratch_bo
= queue
->compute_scratch_bo
;
2649 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2650 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2655 RADV_BO_PRIORITY_SCRATCH
);
2659 esgs_ring_bo
= queue
->esgs_ring_bo
;
2660 esgs_ring_size
= queue
->esgs_ring_size
;
2663 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2664 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2669 RADV_BO_PRIORITY_SCRATCH
);
2673 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2674 gsvs_ring_size
= queue
->gsvs_ring_size
;
2677 if (add_tess_rings
) {
2678 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2679 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2683 RADV_BO_PRIORITY_SCRATCH
);
2687 tess_rings_bo
= queue
->tess_rings_bo
;
2690 if (scratch_bo
!= queue
->scratch_bo
||
2691 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2692 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2693 tess_rings_bo
!= queue
->tess_rings_bo
||
2694 add_sample_positions
) {
2696 if (gsvs_ring_bo
|| esgs_ring_bo
||
2697 tess_rings_bo
|| add_sample_positions
) {
2698 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2699 if (add_sample_positions
)
2700 size
+= 128; /* 64+32+16+8 = 120 bytes */
2702 else if (scratch_bo
)
2703 size
= 8; /* 2 dword */
2705 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2709 RADEON_FLAG_CPU_ACCESS
|
2710 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2711 RADEON_FLAG_READ_ONLY
,
2712 RADV_BO_PRIORITY_DESCRIPTOR
);
2716 descriptor_bo
= queue
->descriptor_bo
;
2718 if (descriptor_bo
!= queue
->descriptor_bo
) {
2719 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2722 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2723 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2724 S_008F04_SWIZZLE_ENABLE(1);
2725 map
[0] = scratch_va
;
2729 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2730 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2731 esgs_ring_size
, esgs_ring_bo
,
2732 gsvs_ring_size
, gsvs_ring_bo
,
2733 tess_factor_ring_size
,
2734 tess_offchip_ring_offset
,
2735 tess_offchip_ring_size
,
2738 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2741 for(int i
= 0; i
< 3; ++i
) {
2742 struct radeon_cmdbuf
*cs
= NULL
;
2743 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2744 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2751 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2753 /* Emit initial configuration. */
2754 switch (queue
->queue_family_index
) {
2755 case RADV_QUEUE_GENERAL
:
2756 radv_init_graphics_state(cs
, queue
);
2758 case RADV_QUEUE_COMPUTE
:
2759 radv_init_compute_state(cs
, queue
);
2761 case RADV_QUEUE_TRANSFER
:
2765 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2766 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2767 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2769 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2770 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2773 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2774 gsvs_ring_bo
, gsvs_ring_size
);
2775 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2776 tess_factor_ring_size
, tess_rings_bo
);
2777 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2778 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2781 si_cs_emit_cache_flush(cs
,
2782 queue
->device
->physical_device
->rad_info
.chip_class
,
2784 queue
->queue_family_index
== RING_COMPUTE
&&
2785 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2786 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2787 RADV_CMD_FLAG_INV_ICACHE
|
2788 RADV_CMD_FLAG_INV_SCACHE
|
2789 RADV_CMD_FLAG_INV_VCACHE
|
2790 RADV_CMD_FLAG_INV_L2
|
2791 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2792 } else if (i
== 1) {
2793 si_cs_emit_cache_flush(cs
,
2794 queue
->device
->physical_device
->rad_info
.chip_class
,
2796 queue
->queue_family_index
== RING_COMPUTE
&&
2797 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2798 RADV_CMD_FLAG_INV_ICACHE
|
2799 RADV_CMD_FLAG_INV_SCACHE
|
2800 RADV_CMD_FLAG_INV_VCACHE
|
2801 RADV_CMD_FLAG_INV_L2
|
2802 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2805 if (!queue
->device
->ws
->cs_finalize(cs
))
2809 if (queue
->initial_full_flush_preamble_cs
)
2810 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2812 if (queue
->initial_preamble_cs
)
2813 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2815 if (queue
->continue_preamble_cs
)
2816 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2818 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2819 queue
->initial_preamble_cs
= dest_cs
[1];
2820 queue
->continue_preamble_cs
= dest_cs
[2];
2822 if (scratch_bo
!= queue
->scratch_bo
) {
2823 if (queue
->scratch_bo
)
2824 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2825 queue
->scratch_bo
= scratch_bo
;
2826 queue
->scratch_size
= scratch_size
;
2829 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2830 if (queue
->compute_scratch_bo
)
2831 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2832 queue
->compute_scratch_bo
= compute_scratch_bo
;
2833 queue
->compute_scratch_size
= compute_scratch_size
;
2836 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2837 if (queue
->esgs_ring_bo
)
2838 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2839 queue
->esgs_ring_bo
= esgs_ring_bo
;
2840 queue
->esgs_ring_size
= esgs_ring_size
;
2843 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2844 if (queue
->gsvs_ring_bo
)
2845 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2846 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2847 queue
->gsvs_ring_size
= gsvs_ring_size
;
2850 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2851 queue
->tess_rings_bo
= tess_rings_bo
;
2852 queue
->has_tess_rings
= true;
2855 if (descriptor_bo
!= queue
->descriptor_bo
) {
2856 if (queue
->descriptor_bo
)
2857 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2859 queue
->descriptor_bo
= descriptor_bo
;
2862 if (add_sample_positions
)
2863 queue
->has_sample_positions
= true;
2865 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2866 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2867 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2868 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2869 *continue_preamble_cs
= NULL
;
2872 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2874 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2875 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2876 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2877 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2878 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2879 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2880 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2881 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2882 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2883 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2884 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2885 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2886 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2887 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2890 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2891 struct radv_winsys_sem_counts
*counts
,
2893 const VkSemaphore
*sems
,
2897 int syncobj_idx
= 0, sem_idx
= 0;
2899 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2902 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2903 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2905 if (sem
->temp_syncobj
|| sem
->syncobj
)
2906 counts
->syncobj_count
++;
2908 counts
->sem_count
++;
2911 if (_fence
!= VK_NULL_HANDLE
) {
2912 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2913 if (fence
->temp_syncobj
|| fence
->syncobj
)
2914 counts
->syncobj_count
++;
2917 if (counts
->syncobj_count
) {
2918 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2919 if (!counts
->syncobj
)
2920 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2923 if (counts
->sem_count
) {
2924 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2926 free(counts
->syncobj
);
2927 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2931 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2932 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2934 if (sem
->temp_syncobj
) {
2935 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2937 else if (sem
->syncobj
)
2938 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2941 counts
->sem
[sem_idx
++] = sem
->sem
;
2945 if (_fence
!= VK_NULL_HANDLE
) {
2946 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2947 if (fence
->temp_syncobj
)
2948 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2949 else if (fence
->syncobj
)
2950 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2957 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2959 free(sem_info
->wait
.syncobj
);
2960 free(sem_info
->wait
.sem
);
2961 free(sem_info
->signal
.syncobj
);
2962 free(sem_info
->signal
.sem
);
2966 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2968 const VkSemaphore
*sems
)
2970 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2971 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2973 if (sem
->temp_syncobj
) {
2974 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2975 sem
->temp_syncobj
= 0;
2981 radv_alloc_sem_info(struct radv_instance
*instance
,
2982 struct radv_winsys_sem_info
*sem_info
,
2984 const VkSemaphore
*wait_sems
,
2985 int num_signal_sems
,
2986 const VkSemaphore
*signal_sems
,
2990 memset(sem_info
, 0, sizeof(*sem_info
));
2992 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2995 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2997 radv_free_sem_info(sem_info
);
2999 /* caller can override these */
3000 sem_info
->cs_emit_wait
= true;
3001 sem_info
->cs_emit_signal
= true;
3005 /* Signals fence as soon as all the work currently put on queue is done. */
3006 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
3007 struct radv_fence
*fence
)
3011 struct radv_winsys_sem_info sem_info
;
3013 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
3014 radv_fence_to_handle(fence
));
3015 if (result
!= VK_SUCCESS
)
3018 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3019 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3020 1, NULL
, NULL
, &sem_info
, NULL
,
3021 false, fence
->fence
);
3022 radv_free_sem_info(&sem_info
);
3025 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
3030 VkResult
radv_QueueSubmit(
3032 uint32_t submitCount
,
3033 const VkSubmitInfo
* pSubmits
,
3036 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3037 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3038 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3039 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3041 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3042 uint32_t scratch_size
= 0;
3043 uint32_t compute_scratch_size
= 0;
3044 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3045 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
3047 bool fence_emitted
= false;
3048 bool tess_rings_needed
= false;
3049 bool sample_positions_needed
= false;
3051 /* Do this first so failing to allocate scratch buffers can't result in
3052 * partially executed submissions. */
3053 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3054 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3055 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3056 pSubmits
[i
].pCommandBuffers
[j
]);
3058 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3059 compute_scratch_size
= MAX2(compute_scratch_size
,
3060 cmd_buffer
->compute_scratch_size_needed
);
3061 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3062 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3063 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3064 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3068 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3069 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3070 sample_positions_needed
, &initial_flush_preamble_cs
,
3071 &initial_preamble_cs
, &continue_preamble_cs
);
3072 if (result
!= VK_SUCCESS
)
3075 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3076 struct radeon_cmdbuf
**cs_array
;
3077 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
3078 bool can_patch
= true;
3080 struct radv_winsys_sem_info sem_info
;
3082 result
= radv_alloc_sem_info(queue
->device
->instance
,
3084 pSubmits
[i
].waitSemaphoreCount
,
3085 pSubmits
[i
].pWaitSemaphores
,
3086 pSubmits
[i
].signalSemaphoreCount
,
3087 pSubmits
[i
].pSignalSemaphores
,
3089 if (result
!= VK_SUCCESS
)
3092 if (!pSubmits
[i
].commandBufferCount
) {
3093 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3094 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3095 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3100 radv_loge("failed to submit CS %d\n", i
);
3103 fence_emitted
= true;
3105 radv_free_sem_info(&sem_info
);
3109 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3110 (pSubmits
[i
].commandBufferCount
));
3112 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3113 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3114 pSubmits
[i
].pCommandBuffers
[j
]);
3115 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3117 cs_array
[j
] = cmd_buffer
->cs
;
3118 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3121 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3124 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3125 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3126 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3128 advance
= MIN2(max_cs_submission
,
3129 pSubmits
[i
].commandBufferCount
- j
);
3131 if (queue
->device
->trace_bo
)
3132 *queue
->device
->trace_id_ptr
= 0;
3134 sem_info
.cs_emit_wait
= j
== 0;
3135 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3137 if (unlikely(queue
->device
->use_global_bo_list
)) {
3138 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3139 bo_list
= &queue
->device
->bo_list
.list
;
3142 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3143 advance
, initial_preamble
, continue_preamble_cs
,
3145 can_patch
, base_fence
);
3147 if (unlikely(queue
->device
->use_global_bo_list
))
3148 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3151 radv_loge("failed to submit CS %d\n", i
);
3154 fence_emitted
= true;
3155 if (queue
->device
->trace_bo
) {
3156 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3160 radv_free_temp_syncobjs(queue
->device
,
3161 pSubmits
[i
].waitSemaphoreCount
,
3162 pSubmits
[i
].pWaitSemaphores
);
3163 radv_free_sem_info(&sem_info
);
3168 if (!fence_emitted
) {
3169 result
= radv_signal_fence(queue
, fence
);
3170 if (result
!= VK_SUCCESS
)
3178 VkResult
radv_QueueWaitIdle(
3181 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3183 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3184 radv_queue_family_to_ring(queue
->queue_family_index
),
3189 VkResult
radv_DeviceWaitIdle(
3192 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3194 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3195 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3196 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3202 VkResult
radv_EnumerateInstanceExtensionProperties(
3203 const char* pLayerName
,
3204 uint32_t* pPropertyCount
,
3205 VkExtensionProperties
* pProperties
)
3207 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3209 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3210 if (radv_supported_instance_extensions
.extensions
[i
]) {
3211 vk_outarray_append(&out
, prop
) {
3212 *prop
= radv_instance_extensions
[i
];
3217 return vk_outarray_status(&out
);
3220 VkResult
radv_EnumerateDeviceExtensionProperties(
3221 VkPhysicalDevice physicalDevice
,
3222 const char* pLayerName
,
3223 uint32_t* pPropertyCount
,
3224 VkExtensionProperties
* pProperties
)
3226 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3227 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3229 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3230 if (device
->supported_extensions
.extensions
[i
]) {
3231 vk_outarray_append(&out
, prop
) {
3232 *prop
= radv_device_extensions
[i
];
3237 return vk_outarray_status(&out
);
3240 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3241 VkInstance _instance
,
3244 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3246 return radv_lookup_entrypoint_checked(pName
,
3247 instance
? instance
->apiVersion
: 0,
3248 instance
? &instance
->enabled_extensions
: NULL
,
3252 /* The loader wants us to expose a second GetInstanceProcAddr function
3253 * to work around certain LD_PRELOAD issues seen in apps.
3256 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3257 VkInstance instance
,
3261 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3262 VkInstance instance
,
3265 return radv_GetInstanceProcAddr(instance
, pName
);
3269 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3270 VkInstance _instance
,
3274 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3275 VkInstance _instance
,
3278 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3280 return radv_lookup_physical_device_entrypoint_checked(pName
,
3281 instance
? instance
->apiVersion
: 0,
3282 instance
? &instance
->enabled_extensions
: NULL
);
3285 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3289 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3291 return radv_lookup_entrypoint_checked(pName
,
3292 device
->instance
->apiVersion
,
3293 &device
->instance
->enabled_extensions
,
3294 &device
->enabled_extensions
);
3297 bool radv_get_memory_fd(struct radv_device
*device
,
3298 struct radv_device_memory
*memory
,
3301 struct radeon_bo_metadata metadata
;
3303 if (memory
->image
) {
3304 radv_init_metadata(device
, memory
->image
, &metadata
);
3305 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3308 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3312 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3313 const VkMemoryAllocateInfo
* pAllocateInfo
,
3314 const VkAllocationCallbacks
* pAllocator
,
3315 VkDeviceMemory
* pMem
)
3317 struct radv_device_memory
*mem
;
3319 enum radeon_bo_domain domain
;
3321 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3323 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3325 if (pAllocateInfo
->allocationSize
== 0) {
3326 /* Apparently, this is allowed */
3327 *pMem
= VK_NULL_HANDLE
;
3331 const VkImportMemoryFdInfoKHR
*import_info
=
3332 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3333 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3334 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3335 const VkExportMemoryAllocateInfo
*export_info
=
3336 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3337 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3338 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3340 const struct wsi_memory_allocate_info
*wsi_info
=
3341 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3343 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3344 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3346 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3348 if (wsi_info
&& wsi_info
->implicit_sync
)
3349 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3351 if (dedicate_info
) {
3352 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3353 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3359 float priority_float
= 0.5;
3360 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3361 vk_find_struct_const(pAllocateInfo
->pNext
,
3362 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3364 priority_float
= priority_ext
->priority
;
3366 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3367 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3369 mem
->user_ptr
= NULL
;
3372 assert(import_info
->handleType
==
3373 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3374 import_info
->handleType
==
3375 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3376 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3377 priority
, NULL
, NULL
);
3379 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3382 close(import_info
->fd
);
3384 } else if (host_ptr_info
) {
3385 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3386 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3387 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3388 pAllocateInfo
->allocationSize
,
3391 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3394 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3397 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3398 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3399 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3400 domain
= RADEON_DOMAIN_GTT
;
3402 domain
= RADEON_DOMAIN_VRAM
;
3404 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3405 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3407 flags
|= RADEON_FLAG_CPU_ACCESS
;
3409 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3410 flags
|= RADEON_FLAG_GTT_WC
;
3412 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3413 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3414 if (device
->use_global_bo_list
) {
3415 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3419 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3420 domain
, flags
, priority
);
3423 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3426 mem
->type_index
= mem_type_index
;
3429 result
= radv_bo_list_add(device
, mem
->bo
);
3430 if (result
!= VK_SUCCESS
)
3433 *pMem
= radv_device_memory_to_handle(mem
);
3438 device
->ws
->buffer_destroy(mem
->bo
);
3440 vk_free2(&device
->alloc
, pAllocator
, mem
);
3445 VkResult
radv_AllocateMemory(
3447 const VkMemoryAllocateInfo
* pAllocateInfo
,
3448 const VkAllocationCallbacks
* pAllocator
,
3449 VkDeviceMemory
* pMem
)
3451 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3452 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3455 void radv_FreeMemory(
3457 VkDeviceMemory _mem
,
3458 const VkAllocationCallbacks
* pAllocator
)
3460 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3461 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3466 radv_bo_list_remove(device
, mem
->bo
);
3467 device
->ws
->buffer_destroy(mem
->bo
);
3470 vk_free2(&device
->alloc
, pAllocator
, mem
);
3473 VkResult
radv_MapMemory(
3475 VkDeviceMemory _memory
,
3476 VkDeviceSize offset
,
3478 VkMemoryMapFlags flags
,
3481 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3482 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3490 *ppData
= mem
->user_ptr
;
3492 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3499 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3502 void radv_UnmapMemory(
3504 VkDeviceMemory _memory
)
3506 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3507 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3512 if (mem
->user_ptr
== NULL
)
3513 device
->ws
->buffer_unmap(mem
->bo
);
3516 VkResult
radv_FlushMappedMemoryRanges(
3518 uint32_t memoryRangeCount
,
3519 const VkMappedMemoryRange
* pMemoryRanges
)
3524 VkResult
radv_InvalidateMappedMemoryRanges(
3526 uint32_t memoryRangeCount
,
3527 const VkMappedMemoryRange
* pMemoryRanges
)
3532 void radv_GetBufferMemoryRequirements(
3535 VkMemoryRequirements
* pMemoryRequirements
)
3537 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3538 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3540 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3542 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3543 pMemoryRequirements
->alignment
= 4096;
3545 pMemoryRequirements
->alignment
= 16;
3547 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3550 void radv_GetBufferMemoryRequirements2(
3552 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3553 VkMemoryRequirements2
*pMemoryRequirements
)
3555 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3556 &pMemoryRequirements
->memoryRequirements
);
3557 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3558 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3559 switch (ext
->sType
) {
3560 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3561 VkMemoryDedicatedRequirements
*req
=
3562 (VkMemoryDedicatedRequirements
*) ext
;
3563 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3564 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3573 void radv_GetImageMemoryRequirements(
3576 VkMemoryRequirements
* pMemoryRequirements
)
3578 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3579 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3581 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3583 pMemoryRequirements
->size
= image
->size
;
3584 pMemoryRequirements
->alignment
= image
->alignment
;
3587 void radv_GetImageMemoryRequirements2(
3589 const VkImageMemoryRequirementsInfo2
*pInfo
,
3590 VkMemoryRequirements2
*pMemoryRequirements
)
3592 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3593 &pMemoryRequirements
->memoryRequirements
);
3595 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3597 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3598 switch (ext
->sType
) {
3599 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3600 VkMemoryDedicatedRequirements
*req
=
3601 (VkMemoryDedicatedRequirements
*) ext
;
3602 req
->requiresDedicatedAllocation
= image
->shareable
;
3603 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3612 void radv_GetImageSparseMemoryRequirements(
3615 uint32_t* pSparseMemoryRequirementCount
,
3616 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3621 void radv_GetImageSparseMemoryRequirements2(
3623 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3624 uint32_t* pSparseMemoryRequirementCount
,
3625 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3630 void radv_GetDeviceMemoryCommitment(
3632 VkDeviceMemory memory
,
3633 VkDeviceSize
* pCommittedMemoryInBytes
)
3635 *pCommittedMemoryInBytes
= 0;
3638 VkResult
radv_BindBufferMemory2(VkDevice device
,
3639 uint32_t bindInfoCount
,
3640 const VkBindBufferMemoryInfo
*pBindInfos
)
3642 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3643 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3644 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3647 buffer
->bo
= mem
->bo
;
3648 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3656 VkResult
radv_BindBufferMemory(
3659 VkDeviceMemory memory
,
3660 VkDeviceSize memoryOffset
)
3662 const VkBindBufferMemoryInfo info
= {
3663 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3666 .memoryOffset
= memoryOffset
3669 return radv_BindBufferMemory2(device
, 1, &info
);
3672 VkResult
radv_BindImageMemory2(VkDevice device
,
3673 uint32_t bindInfoCount
,
3674 const VkBindImageMemoryInfo
*pBindInfos
)
3676 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3677 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3678 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3681 image
->bo
= mem
->bo
;
3682 image
->offset
= pBindInfos
[i
].memoryOffset
;
3692 VkResult
radv_BindImageMemory(
3695 VkDeviceMemory memory
,
3696 VkDeviceSize memoryOffset
)
3698 const VkBindImageMemoryInfo info
= {
3699 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3702 .memoryOffset
= memoryOffset
3705 return radv_BindImageMemory2(device
, 1, &info
);
3710 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3711 const VkSparseBufferMemoryBindInfo
*bind
)
3713 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3715 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3716 struct radv_device_memory
*mem
= NULL
;
3718 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3719 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3721 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3722 bind
->pBinds
[i
].resourceOffset
,
3723 bind
->pBinds
[i
].size
,
3724 mem
? mem
->bo
: NULL
,
3725 bind
->pBinds
[i
].memoryOffset
);
3730 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3731 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3733 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3735 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3736 struct radv_device_memory
*mem
= NULL
;
3738 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3739 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3741 device
->ws
->buffer_virtual_bind(image
->bo
,
3742 bind
->pBinds
[i
].resourceOffset
,
3743 bind
->pBinds
[i
].size
,
3744 mem
? mem
->bo
: NULL
,
3745 bind
->pBinds
[i
].memoryOffset
);
3749 VkResult
radv_QueueBindSparse(
3751 uint32_t bindInfoCount
,
3752 const VkBindSparseInfo
* pBindInfo
,
3755 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3756 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3757 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3758 bool fence_emitted
= false;
3762 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3763 struct radv_winsys_sem_info sem_info
;
3764 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3765 radv_sparse_buffer_bind_memory(queue
->device
,
3766 pBindInfo
[i
].pBufferBinds
+ j
);
3769 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3770 radv_sparse_image_opaque_bind_memory(queue
->device
,
3771 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3775 result
= radv_alloc_sem_info(queue
->device
->instance
,
3777 pBindInfo
[i
].waitSemaphoreCount
,
3778 pBindInfo
[i
].pWaitSemaphores
,
3779 pBindInfo
[i
].signalSemaphoreCount
,
3780 pBindInfo
[i
].pSignalSemaphores
,
3782 if (result
!= VK_SUCCESS
)
3785 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3786 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3787 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3792 radv_loge("failed to submit CS %d\n", i
);
3796 fence_emitted
= true;
3799 radv_free_sem_info(&sem_info
);
3804 if (!fence_emitted
) {
3805 result
= radv_signal_fence(queue
, fence
);
3806 if (result
!= VK_SUCCESS
)
3814 VkResult
radv_CreateFence(
3816 const VkFenceCreateInfo
* pCreateInfo
,
3817 const VkAllocationCallbacks
* pAllocator
,
3820 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3821 const VkExportFenceCreateInfo
*export
=
3822 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3823 VkExternalFenceHandleTypeFlags handleTypes
=
3824 export
? export
->handleTypes
: 0;
3826 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3828 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3831 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3833 fence
->fence_wsi
= NULL
;
3834 fence
->temp_syncobj
= 0;
3835 if (device
->always_use_syncobj
|| handleTypes
) {
3836 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3838 vk_free2(&device
->alloc
, pAllocator
, fence
);
3839 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3841 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3842 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3844 fence
->fence
= NULL
;
3846 fence
->fence
= device
->ws
->create_fence();
3847 if (!fence
->fence
) {
3848 vk_free2(&device
->alloc
, pAllocator
, fence
);
3849 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3852 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3853 device
->ws
->signal_fence(fence
->fence
);
3856 *pFence
= radv_fence_to_handle(fence
);
3861 void radv_DestroyFence(
3864 const VkAllocationCallbacks
* pAllocator
)
3866 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3867 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3872 if (fence
->temp_syncobj
)
3873 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3875 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3877 device
->ws
->destroy_fence(fence
->fence
);
3878 if (fence
->fence_wsi
)
3879 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3880 vk_free2(&device
->alloc
, pAllocator
, fence
);
3884 uint64_t radv_get_current_time(void)
3887 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3888 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3891 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3893 uint64_t current_time
= radv_get_current_time();
3895 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3897 return current_time
+ timeout
;
3901 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3902 uint32_t fenceCount
, const VkFence
*pFences
)
3904 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3905 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3906 if (fence
->fence
== NULL
|| fence
->syncobj
||
3907 fence
->temp_syncobj
|| fence
->fence_wsi
||
3908 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3914 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3916 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3917 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3918 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3924 VkResult
radv_WaitForFences(
3926 uint32_t fenceCount
,
3927 const VkFence
* pFences
,
3931 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3932 timeout
= radv_get_absolute_timeout(timeout
);
3934 if (device
->always_use_syncobj
&&
3935 radv_all_fences_syncobj(fenceCount
, pFences
))
3937 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3939 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3941 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3942 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3943 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3946 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3949 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3952 if (!waitAll
&& fenceCount
> 1) {
3953 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3954 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3955 uint32_t wait_count
= 0;
3956 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3958 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3960 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3961 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3963 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3968 fences
[wait_count
++] = fence
->fence
;
3971 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3972 waitAll
, timeout
- radv_get_current_time());
3975 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3978 while(radv_get_current_time() <= timeout
) {
3979 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3980 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3987 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3988 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3989 bool expired
= false;
3991 if (fence
->temp_syncobj
) {
3992 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3997 if (fence
->syncobj
) {
3998 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
4004 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
4005 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
4006 radv_get_current_time() <= timeout
)
4010 expired
= device
->ws
->fence_wait(device
->ws
,
4017 if (fence
->fence_wsi
) {
4018 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
4019 if (result
!= VK_SUCCESS
)
4027 VkResult
radv_ResetFences(VkDevice _device
,
4028 uint32_t fenceCount
,
4029 const VkFence
*pFences
)
4031 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4033 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4034 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4036 device
->ws
->reset_fence(fence
->fence
);
4038 /* Per spec, we first restore the permanent payload, and then reset, so
4039 * having a temp syncobj should not skip resetting the permanent syncobj. */
4040 if (fence
->temp_syncobj
) {
4041 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4042 fence
->temp_syncobj
= 0;
4045 if (fence
->syncobj
) {
4046 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4053 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4055 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4056 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4058 if (fence
->temp_syncobj
) {
4059 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4060 return success
? VK_SUCCESS
: VK_NOT_READY
;
4063 if (fence
->syncobj
) {
4064 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4065 return success
? VK_SUCCESS
: VK_NOT_READY
;
4069 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4070 return VK_NOT_READY
;
4072 if (fence
->fence_wsi
) {
4073 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4075 if (result
!= VK_SUCCESS
) {
4076 if (result
== VK_TIMEOUT
)
4077 return VK_NOT_READY
;
4085 // Queue semaphore functions
4087 VkResult
radv_CreateSemaphore(
4089 const VkSemaphoreCreateInfo
* pCreateInfo
,
4090 const VkAllocationCallbacks
* pAllocator
,
4091 VkSemaphore
* pSemaphore
)
4093 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4094 const VkExportSemaphoreCreateInfo
*export
=
4095 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4096 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4097 export
? export
->handleTypes
: 0;
4099 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4101 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4103 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4105 sem
->temp_syncobj
= 0;
4106 /* create a syncobject if we are going to export this semaphore */
4107 if (device
->always_use_syncobj
|| handleTypes
) {
4108 assert (device
->physical_device
->rad_info
.has_syncobj
);
4109 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4111 vk_free2(&device
->alloc
, pAllocator
, sem
);
4112 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4116 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4118 vk_free2(&device
->alloc
, pAllocator
, sem
);
4119 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4124 *pSemaphore
= radv_semaphore_to_handle(sem
);
4128 void radv_DestroySemaphore(
4130 VkSemaphore _semaphore
,
4131 const VkAllocationCallbacks
* pAllocator
)
4133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4134 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4139 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4141 device
->ws
->destroy_sem(sem
->sem
);
4142 vk_free2(&device
->alloc
, pAllocator
, sem
);
4145 VkResult
radv_CreateEvent(
4147 const VkEventCreateInfo
* pCreateInfo
,
4148 const VkAllocationCallbacks
* pAllocator
,
4151 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4152 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4154 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4157 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4159 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4161 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4162 RADV_BO_PRIORITY_FENCE
);
4164 vk_free2(&device
->alloc
, pAllocator
, event
);
4165 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4168 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4170 *pEvent
= radv_event_to_handle(event
);
4175 void radv_DestroyEvent(
4178 const VkAllocationCallbacks
* pAllocator
)
4180 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4181 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4185 device
->ws
->buffer_destroy(event
->bo
);
4186 vk_free2(&device
->alloc
, pAllocator
, event
);
4189 VkResult
radv_GetEventStatus(
4193 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4195 if (*event
->map
== 1)
4196 return VK_EVENT_SET
;
4197 return VK_EVENT_RESET
;
4200 VkResult
radv_SetEvent(
4204 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4210 VkResult
radv_ResetEvent(
4214 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4220 VkResult
radv_CreateBuffer(
4222 const VkBufferCreateInfo
* pCreateInfo
,
4223 const VkAllocationCallbacks
* pAllocator
,
4226 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4227 struct radv_buffer
*buffer
;
4229 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4231 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4232 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4234 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4236 buffer
->size
= pCreateInfo
->size
;
4237 buffer
->usage
= pCreateInfo
->usage
;
4240 buffer
->flags
= pCreateInfo
->flags
;
4242 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4243 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4245 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4246 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4247 align64(buffer
->size
, 4096),
4248 4096, 0, RADEON_FLAG_VIRTUAL
,
4249 RADV_BO_PRIORITY_VIRTUAL
);
4251 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4252 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4256 *pBuffer
= radv_buffer_to_handle(buffer
);
4261 void radv_DestroyBuffer(
4264 const VkAllocationCallbacks
* pAllocator
)
4266 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4267 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4272 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4273 device
->ws
->buffer_destroy(buffer
->bo
);
4275 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4278 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4280 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4282 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4283 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4287 static inline unsigned
4288 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4291 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4293 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4296 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4298 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4302 radv_init_dcc_control_reg(struct radv_device
*device
,
4303 struct radv_image_view
*iview
)
4305 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4306 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4307 unsigned max_compressed_block_size
;
4308 unsigned independent_128b_blocks
;
4309 unsigned independent_64b_blocks
;
4311 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4314 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4315 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4316 * dGPU and 64 for APU because all of our APUs to date use
4317 * DIMMs which have a request granularity size of 64B while all
4318 * other chips have a 32B request size.
4320 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4323 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4324 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4325 independent_64b_blocks
= 0;
4326 independent_128b_blocks
= 1;
4328 independent_128b_blocks
= 0;
4330 if (iview
->image
->info
.samples
> 1) {
4331 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4332 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4333 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4334 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4337 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4338 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4339 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4340 /* If this DCC image is potentially going to be used in texture
4341 * fetches, we need some special settings.
4343 independent_64b_blocks
= 1;
4344 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4346 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4347 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4348 * big as possible for better compression state.
4350 independent_64b_blocks
= 0;
4351 max_compressed_block_size
= max_uncompressed_block_size
;
4355 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4356 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4357 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4358 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4359 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4363 radv_initialise_color_surface(struct radv_device
*device
,
4364 struct radv_color_buffer_info
*cb
,
4365 struct radv_image_view
*iview
)
4367 const struct vk_format_description
*desc
;
4368 unsigned ntype
, format
, swap
, endian
;
4369 unsigned blend_clamp
= 0, blend_bypass
= 0;
4371 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4372 const struct radeon_surf
*surf
= &plane
->surface
;
4374 desc
= vk_format_description(iview
->vk_format
);
4376 memset(cb
, 0, sizeof(*cb
));
4378 /* Intensity is implemented as Red, so treat it that way. */
4379 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4381 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4383 cb
->cb_color_base
= va
>> 8;
4385 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4386 struct gfx9_surf_meta_flags meta
;
4387 if (iview
->image
->dcc_offset
)
4388 meta
= surf
->u
.gfx9
.dcc
;
4390 meta
= surf
->u
.gfx9
.cmask
;
4392 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4393 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4394 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4395 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
4396 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
4398 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4399 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4400 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4401 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4402 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4405 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4406 cb
->cb_color_base
|= surf
->tile_swizzle
;
4408 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4409 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4411 cb
->cb_color_base
+= level_info
->offset
>> 8;
4412 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4413 cb
->cb_color_base
|= surf
->tile_swizzle
;
4415 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4416 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4417 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4419 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4420 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4421 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
4423 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4425 if (radv_image_has_fmask(iview
->image
)) {
4426 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4427 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
4428 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
4429 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
4431 /* This must be set for fast clear to work without FMASK. */
4432 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4433 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4434 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4435 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4439 /* CMASK variables */
4440 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4441 va
+= iview
->image
->cmask_offset
;
4442 cb
->cb_color_cmask
= va
>> 8;
4444 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4445 va
+= iview
->image
->dcc_offset
;
4447 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4448 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4449 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4451 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
4452 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
4454 cb
->cb_dcc_base
= va
>> 8;
4455 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
4457 /* GFX10 field has the same base shift as the GFX6 field. */
4458 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4459 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4460 S_028C6C_SLICE_MAX_GFX10(max_slice
);
4462 if (iview
->image
->info
.samples
> 1) {
4463 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4465 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4466 S_028C74_NUM_FRAGMENTS(log_samples
);
4469 if (radv_image_has_fmask(iview
->image
)) {
4470 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
4471 cb
->cb_color_fmask
= va
>> 8;
4472 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
4474 cb
->cb_color_fmask
= cb
->cb_color_base
;
4477 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4479 vk_format_get_first_non_void_channel(iview
->vk_format
));
4480 format
= radv_translate_colorformat(iview
->vk_format
);
4481 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4482 radv_finishme("Illegal color\n");
4483 swap
= radv_translate_colorswap(iview
->vk_format
, false);
4484 endian
= radv_colorformat_endian_swap(format
);
4486 /* blend clamp should be set for all NORM/SRGB types */
4487 if (ntype
== V_028C70_NUMBER_UNORM
||
4488 ntype
== V_028C70_NUMBER_SNORM
||
4489 ntype
== V_028C70_NUMBER_SRGB
)
4492 /* set blend bypass according to docs if SINT/UINT or
4493 8/24 COLOR variants */
4494 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4495 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4496 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4501 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4502 (format
== V_028C70_COLOR_8
||
4503 format
== V_028C70_COLOR_8_8
||
4504 format
== V_028C70_COLOR_8_8_8_8
))
4505 ->color_is_int8
= true;
4507 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4508 S_028C70_COMP_SWAP(swap
) |
4509 S_028C70_BLEND_CLAMP(blend_clamp
) |
4510 S_028C70_BLEND_BYPASS(blend_bypass
) |
4511 S_028C70_SIMPLE_FLOAT(1) |
4512 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4513 ntype
!= V_028C70_NUMBER_SNORM
&&
4514 ntype
!= V_028C70_NUMBER_SRGB
&&
4515 format
!= V_028C70_COLOR_8_24
&&
4516 format
!= V_028C70_COLOR_24_8
) |
4517 S_028C70_NUMBER_TYPE(ntype
) |
4518 S_028C70_ENDIAN(endian
);
4519 if (radv_image_has_fmask(iview
->image
)) {
4520 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4521 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4522 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
4523 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4526 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4527 /* Allow the texture block to read FMASK directly
4528 * without decompressing it. This bit must be cleared
4529 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4530 * otherwise the operation doesn't happen.
4532 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4534 /* Set CMASK into a tiling format that allows the
4535 * texture block to read it.
4537 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4541 if (radv_image_has_cmask(iview
->image
) &&
4542 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4543 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4545 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4546 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4548 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4550 /* This must be set for fast clear to work without FMASK. */
4551 if (!radv_image_has_fmask(iview
->image
) &&
4552 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4553 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4554 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4557 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4558 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4560 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4561 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4562 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4563 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4565 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4566 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
4568 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
4569 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
4570 S_028EE0_RESOURCE_LEVEL(1);
4572 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4573 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4574 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4577 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4578 S_028C68_MIP0_HEIGHT(height
- 1) |
4579 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4584 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4585 struct radv_image_view
*iview
)
4587 unsigned max_zplanes
= 0;
4589 assert(radv_image_is_tc_compat_htile(iview
->image
));
4591 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4592 /* Default value for 32-bit depth surfaces. */
4595 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4596 iview
->image
->info
.samples
> 1)
4599 max_zplanes
= max_zplanes
+ 1;
4601 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4602 /* Do not enable Z plane compression for 16-bit depth
4603 * surfaces because isn't supported on GFX8. Only
4604 * 32-bit depth surfaces are supported by the hardware.
4605 * This allows to maintain shader compatibility and to
4606 * reduce the number of depth decompressions.
4610 if (iview
->image
->info
.samples
<= 1)
4612 else if (iview
->image
->info
.samples
<= 4)
4623 radv_initialise_ds_surface(struct radv_device
*device
,
4624 struct radv_ds_buffer_info
*ds
,
4625 struct radv_image_view
*iview
)
4627 unsigned level
= iview
->base_mip
;
4628 unsigned format
, stencil_format
;
4629 uint64_t va
, s_offs
, z_offs
;
4630 bool stencil_only
= false;
4631 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4632 const struct radeon_surf
*surf
= &plane
->surface
;
4634 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4636 memset(ds
, 0, sizeof(*ds
));
4637 switch (iview
->image
->vk_format
) {
4638 case VK_FORMAT_D24_UNORM_S8_UINT
:
4639 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4640 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4641 ds
->offset_scale
= 2.0f
;
4643 case VK_FORMAT_D16_UNORM
:
4644 case VK_FORMAT_D16_UNORM_S8_UINT
:
4645 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4646 ds
->offset_scale
= 4.0f
;
4648 case VK_FORMAT_D32_SFLOAT
:
4649 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4650 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4651 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4652 ds
->offset_scale
= 1.0f
;
4654 case VK_FORMAT_S8_UINT
:
4655 stencil_only
= true;
4661 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4662 stencil_format
= surf
->has_stencil
?
4663 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4665 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4666 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4667 S_028008_SLICE_MAX(max_slice
);
4668 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4669 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
4670 S_028008_SLICE_MAX_HI(max_slice
>> 11);
4673 ds
->db_htile_data_base
= 0;
4674 ds
->db_htile_surface
= 0;
4676 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4677 s_offs
= z_offs
= va
;
4679 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4680 assert(surf
->u
.gfx9
.surf_offset
== 0);
4681 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4683 ds
->db_z_info
= S_028038_FORMAT(format
) |
4684 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4685 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4686 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4687 S_028038_ZRANGE_PRECISION(1);
4688 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4689 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4691 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4692 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4693 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4696 ds
->db_depth_view
|= S_028008_MIPID(level
);
4697 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4698 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4700 if (radv_htile_enabled(iview
->image
, level
)) {
4701 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4703 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4704 unsigned max_zplanes
=
4705 radv_calc_decompress_on_z_planes(device
, iview
);
4707 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4709 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4710 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
4711 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
4713 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
4714 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4718 if (!surf
->has_stencil
)
4719 /* Use all of the htile_buffer for depth if there's no stencil. */
4720 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4721 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4722 iview
->image
->htile_offset
;
4723 ds
->db_htile_data_base
= va
>> 8;
4724 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4725 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
4727 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4728 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4732 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4735 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4737 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4738 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4740 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4741 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4742 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4744 if (iview
->image
->info
.samples
> 1)
4745 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4747 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4748 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4749 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4750 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4751 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4752 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4753 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4754 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4757 tile_mode
= stencil_tile_mode
;
4759 ds
->db_depth_info
|=
4760 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4761 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4762 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4763 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4764 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4765 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4766 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4767 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4769 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4770 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4771 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4772 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4774 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4777 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4778 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4779 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4781 if (radv_htile_enabled(iview
->image
, level
)) {
4782 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4784 if (!surf
->has_stencil
&&
4785 !radv_image_is_tc_compat_htile(iview
->image
))
4786 /* Use all of the htile_buffer for depth if there's no stencil. */
4787 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4789 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4790 iview
->image
->htile_offset
;
4791 ds
->db_htile_data_base
= va
>> 8;
4792 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4794 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4795 unsigned max_zplanes
=
4796 radv_calc_decompress_on_z_planes(device
, iview
);
4798 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4799 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4804 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4805 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4808 VkResult
radv_CreateFramebuffer(
4810 const VkFramebufferCreateInfo
* pCreateInfo
,
4811 const VkAllocationCallbacks
* pAllocator
,
4812 VkFramebuffer
* pFramebuffer
)
4814 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4815 struct radv_framebuffer
*framebuffer
;
4816 const VkFramebufferAttachmentsCreateInfoKHR
*imageless_create_info
=
4817 vk_find_struct_const(pCreateInfo
->pNext
,
4818 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR
);
4820 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4822 size_t size
= sizeof(*framebuffer
);
4823 if (!imageless_create_info
)
4824 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
4825 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4826 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4827 if (framebuffer
== NULL
)
4828 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4830 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4831 framebuffer
->width
= pCreateInfo
->width
;
4832 framebuffer
->height
= pCreateInfo
->height
;
4833 framebuffer
->layers
= pCreateInfo
->layers
;
4834 if (imageless_create_info
) {
4835 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
4836 const VkFramebufferAttachmentImageInfoKHR
*attachment
=
4837 imageless_create_info
->pAttachmentImageInfos
+ i
;
4838 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
4839 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
4840 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
4843 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4844 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4845 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4846 framebuffer
->attachments
[i
] = iview
;
4847 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4848 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4849 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4853 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4857 void radv_DestroyFramebuffer(
4860 const VkAllocationCallbacks
* pAllocator
)
4862 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4863 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4867 vk_free2(&device
->alloc
, pAllocator
, fb
);
4870 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4872 switch (address_mode
) {
4873 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4874 return V_008F30_SQ_TEX_WRAP
;
4875 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4876 return V_008F30_SQ_TEX_MIRROR
;
4877 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4878 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4879 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4880 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4881 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4882 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4884 unreachable("illegal tex wrap mode");
4890 radv_tex_compare(VkCompareOp op
)
4893 case VK_COMPARE_OP_NEVER
:
4894 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4895 case VK_COMPARE_OP_LESS
:
4896 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4897 case VK_COMPARE_OP_EQUAL
:
4898 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4899 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4900 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4901 case VK_COMPARE_OP_GREATER
:
4902 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4903 case VK_COMPARE_OP_NOT_EQUAL
:
4904 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4905 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4906 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4907 case VK_COMPARE_OP_ALWAYS
:
4908 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4910 unreachable("illegal compare mode");
4916 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4919 case VK_FILTER_NEAREST
:
4920 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4921 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4922 case VK_FILTER_LINEAR
:
4923 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4924 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4925 case VK_FILTER_CUBIC_IMG
:
4927 fprintf(stderr
, "illegal texture filter");
4933 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4936 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4937 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4938 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4939 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4941 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4946 radv_tex_bordercolor(VkBorderColor bcolor
)
4949 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4950 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4951 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4952 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4953 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4954 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4955 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4956 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4957 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4965 radv_tex_aniso_filter(unsigned filter
)
4979 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4982 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4983 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4984 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4985 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4986 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4987 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4995 radv_get_max_anisotropy(struct radv_device
*device
,
4996 const VkSamplerCreateInfo
*pCreateInfo
)
4998 if (device
->force_aniso
>= 0)
4999 return device
->force_aniso
;
5001 if (pCreateInfo
->anisotropyEnable
&&
5002 pCreateInfo
->maxAnisotropy
> 1.0f
)
5003 return (uint32_t)pCreateInfo
->maxAnisotropy
;
5009 radv_init_sampler(struct radv_device
*device
,
5010 struct radv_sampler
*sampler
,
5011 const VkSamplerCreateInfo
*pCreateInfo
)
5013 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
5014 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
5015 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
5016 device
->physical_device
->rad_info
.chip_class
== GFX9
;
5017 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5019 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
5020 vk_find_struct_const(pCreateInfo
->pNext
,
5021 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
5022 if (sampler_reduction
)
5023 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
5025 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
5026 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
5027 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
5028 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
5029 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
5030 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
5031 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
5032 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
5033 S_008F30_DISABLE_CUBE_WRAP(0) |
5034 S_008F30_COMPAT_MODE(compat_mode
) |
5035 S_008F30_FILTER_MODE(filter_mode
));
5036 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5037 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5038 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5039 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5040 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5041 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5042 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5043 S_008F38_MIP_POINT_PRECLAMP(0));
5044 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5045 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5047 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5048 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5050 sampler
->state
[2] |=
5051 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5052 S_008F38_FILTER_PREC_FIX(1) |
5053 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5057 VkResult
radv_CreateSampler(
5059 const VkSamplerCreateInfo
* pCreateInfo
,
5060 const VkAllocationCallbacks
* pAllocator
,
5061 VkSampler
* pSampler
)
5063 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5064 struct radv_sampler
*sampler
;
5066 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5067 vk_find_struct_const(pCreateInfo
->pNext
,
5068 SAMPLER_YCBCR_CONVERSION_INFO
);
5070 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5072 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5073 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5075 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5077 radv_init_sampler(device
, sampler
, pCreateInfo
);
5079 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5080 *pSampler
= radv_sampler_to_handle(sampler
);
5085 void radv_DestroySampler(
5088 const VkAllocationCallbacks
* pAllocator
)
5090 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5091 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5095 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5098 /* vk_icd.h does not declare this function, so we declare it here to
5099 * suppress Wmissing-prototypes.
5101 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5102 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5104 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5105 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5107 /* For the full details on loader interface versioning, see
5108 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5109 * What follows is a condensed summary, to help you navigate the large and
5110 * confusing official doc.
5112 * - Loader interface v0 is incompatible with later versions. We don't
5115 * - In loader interface v1:
5116 * - The first ICD entrypoint called by the loader is
5117 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5119 * - The ICD must statically expose no other Vulkan symbol unless it is
5120 * linked with -Bsymbolic.
5121 * - Each dispatchable Vulkan handle created by the ICD must be
5122 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5123 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5124 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5125 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5126 * such loader-managed surfaces.
5128 * - Loader interface v2 differs from v1 in:
5129 * - The first ICD entrypoint called by the loader is
5130 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5131 * statically expose this entrypoint.
5133 * - Loader interface v3 differs from v2 in:
5134 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5135 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5136 * because the loader no longer does so.
5138 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5142 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5143 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5146 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5147 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5149 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5151 /* At the moment, we support only the below handle types. */
5152 assert(pGetFdInfo
->handleType
==
5153 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5154 pGetFdInfo
->handleType
==
5155 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5157 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5159 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5163 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5164 VkExternalMemoryHandleTypeFlagBits handleType
,
5166 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5168 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5170 switch (handleType
) {
5171 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5172 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5176 /* The valid usage section for this function says:
5178 * "handleType must not be one of the handle types defined as
5181 * So opaque handle types fall into the default "unsupported" case.
5183 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5187 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5191 uint32_t syncobj_handle
= 0;
5192 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5194 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5197 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5199 *syncobj
= syncobj_handle
;
5205 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5209 /* If we create a syncobj we do it locally so that if we have an error, we don't
5210 * leave a syncobj in an undetermined state in the fence. */
5211 uint32_t syncobj_handle
= *syncobj
;
5212 if (!syncobj_handle
) {
5213 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5215 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5220 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5222 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5224 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5227 *syncobj
= syncobj_handle
;
5234 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5235 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5237 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5238 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5239 uint32_t *syncobj_dst
= NULL
;
5241 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5242 syncobj_dst
= &sem
->temp_syncobj
;
5244 syncobj_dst
= &sem
->syncobj
;
5247 switch(pImportSemaphoreFdInfo
->handleType
) {
5248 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5249 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5250 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5251 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5253 unreachable("Unhandled semaphore handle type");
5257 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5258 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5261 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5262 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5264 uint32_t syncobj_handle
;
5266 if (sem
->temp_syncobj
)
5267 syncobj_handle
= sem
->temp_syncobj
;
5269 syncobj_handle
= sem
->syncobj
;
5271 switch(pGetFdInfo
->handleType
) {
5272 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5273 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5275 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5276 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5278 if (sem
->temp_syncobj
) {
5279 close (sem
->temp_syncobj
);
5280 sem
->temp_syncobj
= 0;
5282 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5287 unreachable("Unhandled semaphore handle type");
5291 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5295 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5296 VkPhysicalDevice physicalDevice
,
5297 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5298 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5300 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5302 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5303 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5304 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5305 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5306 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5307 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5308 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5309 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5310 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5311 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5312 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5313 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5314 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5316 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5317 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5318 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5322 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5323 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5325 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5326 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5327 uint32_t *syncobj_dst
= NULL
;
5330 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5331 syncobj_dst
= &fence
->temp_syncobj
;
5333 syncobj_dst
= &fence
->syncobj
;
5336 switch(pImportFenceFdInfo
->handleType
) {
5337 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5338 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5339 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5340 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5342 unreachable("Unhandled fence handle type");
5346 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5347 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5350 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5351 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5353 uint32_t syncobj_handle
;
5355 if (fence
->temp_syncobj
)
5356 syncobj_handle
= fence
->temp_syncobj
;
5358 syncobj_handle
= fence
->syncobj
;
5360 switch(pGetFdInfo
->handleType
) {
5361 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5362 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5364 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5365 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5367 if (fence
->temp_syncobj
) {
5368 close (fence
->temp_syncobj
);
5369 fence
->temp_syncobj
= 0;
5371 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5376 unreachable("Unhandled fence handle type");
5380 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5384 void radv_GetPhysicalDeviceExternalFenceProperties(
5385 VkPhysicalDevice physicalDevice
,
5386 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5387 VkExternalFenceProperties
*pExternalFenceProperties
)
5389 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5391 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5392 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5393 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5394 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5395 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5396 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5397 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5399 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5400 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5401 pExternalFenceProperties
->externalFenceFeatures
= 0;
5406 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5407 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5408 const VkAllocationCallbacks
* pAllocator
,
5409 VkDebugReportCallbackEXT
* pCallback
)
5411 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5412 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5413 pCreateInfo
, pAllocator
, &instance
->alloc
,
5418 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5419 VkDebugReportCallbackEXT _callback
,
5420 const VkAllocationCallbacks
* pAllocator
)
5422 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5423 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5424 _callback
, pAllocator
, &instance
->alloc
);
5428 radv_DebugReportMessageEXT(VkInstance _instance
,
5429 VkDebugReportFlagsEXT flags
,
5430 VkDebugReportObjectTypeEXT objectType
,
5433 int32_t messageCode
,
5434 const char* pLayerPrefix
,
5435 const char* pMessage
)
5437 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5438 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5439 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5443 radv_GetDeviceGroupPeerMemoryFeatures(
5446 uint32_t localDeviceIndex
,
5447 uint32_t remoteDeviceIndex
,
5448 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5450 assert(localDeviceIndex
== remoteDeviceIndex
);
5452 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5453 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5454 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5455 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5458 static const VkTimeDomainEXT radv_time_domains
[] = {
5459 VK_TIME_DOMAIN_DEVICE_EXT
,
5460 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5461 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5464 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5465 VkPhysicalDevice physicalDevice
,
5466 uint32_t *pTimeDomainCount
,
5467 VkTimeDomainEXT
*pTimeDomains
)
5470 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5472 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5473 vk_outarray_append(&out
, i
) {
5474 *i
= radv_time_domains
[d
];
5478 return vk_outarray_status(&out
);
5482 radv_clock_gettime(clockid_t clock_id
)
5484 struct timespec current
;
5487 ret
= clock_gettime(clock_id
, ¤t
);
5488 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5489 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5493 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5496 VkResult
radv_GetCalibratedTimestampsEXT(
5498 uint32_t timestampCount
,
5499 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5500 uint64_t *pTimestamps
,
5501 uint64_t *pMaxDeviation
)
5503 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5504 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5506 uint64_t begin
, end
;
5507 uint64_t max_clock_period
= 0;
5509 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5511 for (d
= 0; d
< timestampCount
; d
++) {
5512 switch (pTimestampInfos
[d
].timeDomain
) {
5513 case VK_TIME_DOMAIN_DEVICE_EXT
:
5514 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5516 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5517 max_clock_period
= MAX2(max_clock_period
, device_period
);
5519 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5520 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5521 max_clock_period
= MAX2(max_clock_period
, 1);
5524 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5525 pTimestamps
[d
] = begin
;
5533 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5536 * The maximum deviation is the sum of the interval over which we
5537 * perform the sampling and the maximum period of any sampled
5538 * clock. That's because the maximum skew between any two sampled
5539 * clock edges is when the sampled clock with the largest period is
5540 * sampled at the end of that period but right at the beginning of the
5541 * sampling interval and some other clock is sampled right at the
5542 * begining of its sampling period and right at the end of the
5543 * sampling interval. Let's assume the GPU has the longest clock
5544 * period and that the application is sampling GPU and monotonic:
5547 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5548 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5552 * GPU -----_____-----_____-----_____-----_____
5555 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5556 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5558 * Interval <----------------->
5559 * Deviation <-------------------------->
5563 * m = read(monotonic) 2
5566 * We round the sample interval up by one tick to cover sampling error
5567 * in the interval clock
5570 uint64_t sample_interval
= end
- begin
+ 1;
5572 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5577 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5578 VkPhysicalDevice physicalDevice
,
5579 VkSampleCountFlagBits samples
,
5580 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5582 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5583 VK_SAMPLE_COUNT_4_BIT
|
5584 VK_SAMPLE_COUNT_8_BIT
)) {
5585 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5587 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };