2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_private.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
45 #include "util/debug.h"
48 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
50 uint32_t mesa_timestamp
, llvm_timestamp
;
52 memset(uuid
, 0, VK_UUID_SIZE
);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
57 memcpy(uuid
, &mesa_timestamp
, 4);
58 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
59 memcpy((char*)uuid
+ 8, &f
, 2);
60 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
64 static const VkExtensionProperties instance_extensions
[] = {
66 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
69 #ifdef VK_USE_PLATFORM_XCB_KHR
71 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
77 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
83 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
88 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
93 static const VkExtensionProperties common_device_extensions
[] = {
95 .extensionName
= VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME
,
99 .extensionName
= VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME
,
103 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
107 .extensionName
= VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME
,
111 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
115 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
119 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
123 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
127 .extensionName
= VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME
,
133 radv_extensions_register(struct radv_instance
*instance
,
134 struct radv_extensions
*extensions
,
135 const VkExtensionProperties
*new_ext
,
139 VkExtensionProperties
*new_ptr
;
141 assert(new_ext
&& num_ext
> 0);
144 return VK_ERROR_INITIALIZATION_FAILED
;
146 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
147 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
148 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
150 /* Old array continues to be valid, update nothing */
152 return VK_ERROR_OUT_OF_HOST_MEMORY
;
154 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
155 num_ext
* sizeof(VkExtensionProperties
));
156 extensions
->ext_array
= new_ptr
;
157 extensions
->num_ext
+= num_ext
;
163 radv_extensions_finish(struct radv_instance
*instance
,
164 struct radv_extensions
*extensions
)
169 radv_loge("Attemted to free invalid extension struct\n");
171 if (extensions
->ext_array
)
172 vk_free(&instance
->alloc
, extensions
->ext_array
);
176 is_extension_enabled(const VkExtensionProperties
*extensions
,
180 assert(extensions
&& name
);
182 for (uint32_t i
= 0; i
< num_ext
; i
++) {
183 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
191 radv_physical_device_init(struct radv_physical_device
*device
,
192 struct radv_instance
*instance
,
196 drmVersionPtr version
;
199 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
201 return VK_ERROR_INCOMPATIBLE_DRIVER
;
203 version
= drmGetVersion(fd
);
206 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
207 "failed to get version %s: %m", path
);
210 if (strcmp(version
->name
, "amdgpu")) {
211 drmFreeVersion(version
);
213 return VK_ERROR_INCOMPATIBLE_DRIVER
;
215 drmFreeVersion(version
);
217 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
218 device
->instance
= instance
;
219 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
220 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
222 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
);
224 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
228 device
->local_fd
= fd
;
229 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
230 result
= radv_init_wsi(device
);
231 if (result
!= VK_SUCCESS
) {
232 device
->ws
->destroy(device
->ws
);
236 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
237 radv_finish_wsi(device
);
238 device
->ws
->destroy(device
->ws
);
239 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
240 "cannot generate UUID");
244 result
= radv_extensions_register(instance
,
246 common_device_extensions
,
247 ARRAY_SIZE(common_device_extensions
));
248 if (result
!= VK_SUCCESS
)
251 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 device
->name
= device
->rad_info
.name
;
262 radv_physical_device_finish(struct radv_physical_device
*device
)
264 radv_extensions_finish(device
->instance
, &device
->extensions
);
265 radv_finish_wsi(device
);
266 device
->ws
->destroy(device
->ws
);
267 close(device
->local_fd
);
272 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
273 VkSystemAllocationScope allocationScope
)
279 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
280 size_t align
, VkSystemAllocationScope allocationScope
)
282 return realloc(pOriginal
, size
);
286 default_free_func(void *pUserData
, void *pMemory
)
291 static const VkAllocationCallbacks default_alloc
= {
293 .pfnAllocation
= default_alloc_func
,
294 .pfnReallocation
= default_realloc_func
,
295 .pfnFree
= default_free_func
,
298 static const struct debug_control radv_debug_options
[] = {
299 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
300 {"nodcc", RADV_DEBUG_NO_DCC
},
301 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
302 {"nocache", RADV_DEBUG_NO_CACHE
},
303 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
304 {"nohiz", RADV_DEBUG_NO_HIZ
},
305 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
306 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
307 {"allbos", RADV_DEBUG_ALL_BOS
},
308 {"noibs", RADV_DEBUG_NO_IBS
},
312 VkResult
radv_CreateInstance(
313 const VkInstanceCreateInfo
* pCreateInfo
,
314 const VkAllocationCallbacks
* pAllocator
,
315 VkInstance
* pInstance
)
317 struct radv_instance
*instance
;
319 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
321 uint32_t client_version
;
322 if (pCreateInfo
->pApplicationInfo
&&
323 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
324 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
326 client_version
= VK_MAKE_VERSION(1, 0, 0);
329 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
330 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
331 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
332 "Client requested version %d.%d.%d",
333 VK_VERSION_MAJOR(client_version
),
334 VK_VERSION_MINOR(client_version
),
335 VK_VERSION_PATCH(client_version
));
338 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
339 if (!is_extension_enabled(instance_extensions
,
340 ARRAY_SIZE(instance_extensions
),
341 pCreateInfo
->ppEnabledExtensionNames
[i
]))
342 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
345 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
346 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
350 memset(instance
, 0, sizeof(*instance
));
352 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
355 instance
->alloc
= *pAllocator
;
357 instance
->alloc
= default_alloc
;
359 instance
->apiVersion
= client_version
;
360 instance
->physicalDeviceCount
= -1;
364 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
366 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
369 *pInstance
= radv_instance_to_handle(instance
);
374 void radv_DestroyInstance(
375 VkInstance _instance
,
376 const VkAllocationCallbacks
* pAllocator
)
378 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
383 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
384 radv_physical_device_finish(instance
->physicalDevices
+ i
);
387 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
391 vk_free(&instance
->alloc
, instance
);
395 radv_enumerate_devices(struct radv_instance
*instance
)
397 /* TODO: Check for more devices ? */
398 drmDevicePtr devices
[8];
399 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
402 instance
->physicalDeviceCount
= 0;
404 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
406 return VK_ERROR_INCOMPATIBLE_DRIVER
;
408 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
409 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
410 devices
[i
]->bustype
== DRM_BUS_PCI
&&
411 devices
[i
]->deviceinfo
.pci
->vendor_id
== 0x1002) {
413 result
= radv_physical_device_init(instance
->physicalDevices
+
414 instance
->physicalDeviceCount
,
416 devices
[i
]->nodes
[DRM_NODE_RENDER
]);
417 if (result
== VK_SUCCESS
)
418 ++instance
->physicalDeviceCount
;
419 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
423 drmFreeDevices(devices
, max_devices
);
428 VkResult
radv_EnumeratePhysicalDevices(
429 VkInstance _instance
,
430 uint32_t* pPhysicalDeviceCount
,
431 VkPhysicalDevice
* pPhysicalDevices
)
433 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
436 if (instance
->physicalDeviceCount
< 0) {
437 result
= radv_enumerate_devices(instance
);
438 if (result
!= VK_SUCCESS
&&
439 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
443 if (!pPhysicalDevices
) {
444 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
446 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
447 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
448 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
451 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
455 void radv_GetPhysicalDeviceFeatures(
456 VkPhysicalDevice physicalDevice
,
457 VkPhysicalDeviceFeatures
* pFeatures
)
459 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
461 memset(pFeatures
, 0, sizeof(*pFeatures
));
463 *pFeatures
= (VkPhysicalDeviceFeatures
) {
464 .robustBufferAccess
= true,
465 .fullDrawIndexUint32
= true,
466 .imageCubeArray
= true,
467 .independentBlend
= true,
468 .geometryShader
= true,
469 .tessellationShader
= true,
470 .sampleRateShading
= false,
471 .dualSrcBlend
= true,
473 .multiDrawIndirect
= true,
474 .drawIndirectFirstInstance
= true,
476 .depthBiasClamp
= true,
477 .fillModeNonSolid
= true,
482 .multiViewport
= true,
483 .samplerAnisotropy
= true,
484 .textureCompressionETC2
= false,
485 .textureCompressionASTC_LDR
= false,
486 .textureCompressionBC
= true,
487 .occlusionQueryPrecise
= true,
488 .pipelineStatisticsQuery
= true,
489 .vertexPipelineStoresAndAtomics
= true,
490 .fragmentStoresAndAtomics
= true,
491 .shaderTessellationAndGeometryPointSize
= true,
492 .shaderImageGatherExtended
= true,
493 .shaderStorageImageExtendedFormats
= true,
494 .shaderStorageImageMultisample
= false,
495 .shaderUniformBufferArrayDynamicIndexing
= true,
496 .shaderSampledImageArrayDynamicIndexing
= true,
497 .shaderStorageBufferArrayDynamicIndexing
= true,
498 .shaderStorageImageArrayDynamicIndexing
= true,
499 .shaderStorageImageReadWithoutFormat
= true,
500 .shaderStorageImageWriteWithoutFormat
= true,
501 .shaderClipDistance
= true,
502 .shaderCullDistance
= true,
503 .shaderFloat64
= true,
504 .shaderInt64
= false,
505 .shaderInt16
= false,
506 .sparseBinding
= true,
507 .variableMultisampleRate
= true,
508 .inheritedQueries
= true,
512 void radv_GetPhysicalDeviceFeatures2KHR(
513 VkPhysicalDevice physicalDevice
,
514 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
516 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
519 static uint32_t radv_get_driver_version()
521 const char *minor_string
= strchr(VERSION
, '.');
522 const char *patch_string
= minor_string
? strchr(minor_string
+ 1, ','): NULL
;
523 int major
= atoi(VERSION
);
524 int minor
= minor_string
? atoi(minor_string
+ 1) : 0;
525 int patch
= patch_string
? atoi(patch_string
+ 1) : 0;
526 if (strstr(VERSION
, "devel")) {
537 uint32_t version
= VK_MAKE_VERSION(major
, minor
, patch
);
541 void radv_GetPhysicalDeviceProperties(
542 VkPhysicalDevice physicalDevice
,
543 VkPhysicalDeviceProperties
* pProperties
)
545 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
546 VkSampleCountFlags sample_counts
= 0xf;
548 /* make sure that the entire descriptor set is addressable with a signed
549 * 32-bit int. So the sum of all limits scaled by descriptor size has to
550 * be at most 2 GiB. the combined image & samples object count as one of
551 * both. This limit is for the pipeline layout, not for the set layout, but
552 * there is no set limit, so we just set a pipeline limit. I don't think
553 * any app is going to hit this soon. */
554 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
555 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
556 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
557 32 /* sampler, largest when combined with image */ +
558 64 /* sampled image */ +
559 64 /* storage image */);
561 VkPhysicalDeviceLimits limits
= {
562 .maxImageDimension1D
= (1 << 14),
563 .maxImageDimension2D
= (1 << 14),
564 .maxImageDimension3D
= (1 << 11),
565 .maxImageDimensionCube
= (1 << 14),
566 .maxImageArrayLayers
= (1 << 11),
567 .maxTexelBufferElements
= 128 * 1024 * 1024,
568 .maxUniformBufferRange
= UINT32_MAX
,
569 .maxStorageBufferRange
= UINT32_MAX
,
570 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
571 .maxMemoryAllocationCount
= UINT32_MAX
,
572 .maxSamplerAllocationCount
= 64 * 1024,
573 .bufferImageGranularity
= 64, /* A cache line */
574 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
575 .maxBoundDescriptorSets
= MAX_SETS
,
576 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
577 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
578 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
579 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
580 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
581 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
582 .maxPerStageResources
= max_descriptor_set_size
,
583 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
584 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
585 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
586 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
587 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
588 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
589 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
590 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
591 .maxVertexInputAttributes
= 32,
592 .maxVertexInputBindings
= 32,
593 .maxVertexInputAttributeOffset
= 2047,
594 .maxVertexInputBindingStride
= 2048,
595 .maxVertexOutputComponents
= 128,
596 .maxTessellationGenerationLevel
= 64,
597 .maxTessellationPatchSize
= 32,
598 .maxTessellationControlPerVertexInputComponents
= 128,
599 .maxTessellationControlPerVertexOutputComponents
= 128,
600 .maxTessellationControlPerPatchOutputComponents
= 120,
601 .maxTessellationControlTotalOutputComponents
= 4096,
602 .maxTessellationEvaluationInputComponents
= 128,
603 .maxTessellationEvaluationOutputComponents
= 128,
604 .maxGeometryShaderInvocations
= 127,
605 .maxGeometryInputComponents
= 64,
606 .maxGeometryOutputComponents
= 128,
607 .maxGeometryOutputVertices
= 256,
608 .maxGeometryTotalOutputComponents
= 1024,
609 .maxFragmentInputComponents
= 128,
610 .maxFragmentOutputAttachments
= 8,
611 .maxFragmentDualSrcAttachments
= 1,
612 .maxFragmentCombinedOutputResources
= 8,
613 .maxComputeSharedMemorySize
= 32768,
614 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
615 .maxComputeWorkGroupInvocations
= 2048,
616 .maxComputeWorkGroupSize
= {
621 .subPixelPrecisionBits
= 4 /* FIXME */,
622 .subTexelPrecisionBits
= 4 /* FIXME */,
623 .mipmapPrecisionBits
= 4 /* FIXME */,
624 .maxDrawIndexedIndexValue
= UINT32_MAX
,
625 .maxDrawIndirectCount
= UINT32_MAX
,
626 .maxSamplerLodBias
= 16,
627 .maxSamplerAnisotropy
= 16,
628 .maxViewports
= MAX_VIEWPORTS
,
629 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
630 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
631 .viewportSubPixelBits
= 13, /* We take a float? */
632 .minMemoryMapAlignment
= 4096, /* A page */
633 .minTexelBufferOffsetAlignment
= 1,
634 .minUniformBufferOffsetAlignment
= 4,
635 .minStorageBufferOffsetAlignment
= 4,
636 .minTexelOffset
= -32,
637 .maxTexelOffset
= 31,
638 .minTexelGatherOffset
= -32,
639 .maxTexelGatherOffset
= 31,
640 .minInterpolationOffset
= -2,
641 .maxInterpolationOffset
= 2,
642 .subPixelInterpolationOffsetBits
= 8,
643 .maxFramebufferWidth
= (1 << 14),
644 .maxFramebufferHeight
= (1 << 14),
645 .maxFramebufferLayers
= (1 << 10),
646 .framebufferColorSampleCounts
= sample_counts
,
647 .framebufferDepthSampleCounts
= sample_counts
,
648 .framebufferStencilSampleCounts
= sample_counts
,
649 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
650 .maxColorAttachments
= MAX_RTS
,
651 .sampledImageColorSampleCounts
= sample_counts
,
652 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
653 .sampledImageDepthSampleCounts
= sample_counts
,
654 .sampledImageStencilSampleCounts
= sample_counts
,
655 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
656 .maxSampleMaskWords
= 1,
657 .timestampComputeAndGraphics
= true,
658 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
659 .maxClipDistances
= 8,
660 .maxCullDistances
= 8,
661 .maxCombinedClipAndCullDistances
= 8,
662 .discreteQueuePriorities
= 1,
663 .pointSizeRange
= { 0.125, 255.875 },
664 .lineWidthRange
= { 0.0, 7.9921875 },
665 .pointSizeGranularity
= (1.0 / 8.0),
666 .lineWidthGranularity
= (1.0 / 128.0),
667 .strictLines
= false, /* FINISHME */
668 .standardSampleLocations
= true,
669 .optimalBufferCopyOffsetAlignment
= 128,
670 .optimalBufferCopyRowPitchAlignment
= 128,
671 .nonCoherentAtomSize
= 64,
674 *pProperties
= (VkPhysicalDeviceProperties
) {
675 .apiVersion
= VK_MAKE_VERSION(1, 0, 42),
676 .driverVersion
= radv_get_driver_version(),
678 .deviceID
= pdevice
->rad_info
.pci_id
,
679 .deviceType
= VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
,
681 .sparseProperties
= {0},
684 strcpy(pProperties
->deviceName
, pdevice
->name
);
685 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
688 void radv_GetPhysicalDeviceProperties2KHR(
689 VkPhysicalDevice physicalDevice
,
690 VkPhysicalDeviceProperties2KHR
*pProperties
)
692 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
694 vk_foreach_struct(ext
, pProperties
->pNext
) {
695 switch (ext
->sType
) {
696 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
697 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
698 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
699 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
708 static void radv_get_physical_device_queue_family_properties(
709 struct radv_physical_device
* pdevice
,
711 VkQueueFamilyProperties
** pQueueFamilyProperties
)
713 int num_queue_families
= 1;
715 if (pdevice
->rad_info
.compute_rings
> 0 &&
716 pdevice
->rad_info
.chip_class
>= CIK
&&
717 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
718 num_queue_families
++;
720 if (pQueueFamilyProperties
== NULL
) {
721 *pCount
= num_queue_families
;
730 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
731 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
732 VK_QUEUE_COMPUTE_BIT
|
733 VK_QUEUE_TRANSFER_BIT
|
734 VK_QUEUE_SPARSE_BINDING_BIT
,
736 .timestampValidBits
= 64,
737 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
742 if (pdevice
->rad_info
.compute_rings
> 0 &&
743 pdevice
->rad_info
.chip_class
>= CIK
&&
744 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
746 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
747 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
748 VK_QUEUE_TRANSFER_BIT
|
749 VK_QUEUE_SPARSE_BINDING_BIT
,
750 .queueCount
= pdevice
->rad_info
.compute_rings
,
751 .timestampValidBits
= 64,
752 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
760 void radv_GetPhysicalDeviceQueueFamilyProperties(
761 VkPhysicalDevice physicalDevice
,
763 VkQueueFamilyProperties
* pQueueFamilyProperties
)
765 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
766 if (!pQueueFamilyProperties
) {
767 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
770 VkQueueFamilyProperties
*properties
[] = {
771 pQueueFamilyProperties
+ 0,
772 pQueueFamilyProperties
+ 1,
773 pQueueFamilyProperties
+ 2,
775 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
776 assert(*pCount
<= 3);
779 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
780 VkPhysicalDevice physicalDevice
,
782 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
784 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
785 if (!pQueueFamilyProperties
) {
786 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
789 VkQueueFamilyProperties
*properties
[] = {
790 &pQueueFamilyProperties
[0].queueFamilyProperties
,
791 &pQueueFamilyProperties
[1].queueFamilyProperties
,
792 &pQueueFamilyProperties
[2].queueFamilyProperties
,
794 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
795 assert(*pCount
<= 3);
798 void radv_GetPhysicalDeviceMemoryProperties(
799 VkPhysicalDevice physicalDevice
,
800 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
802 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
804 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
806 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
807 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
808 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
809 .heapIndex
= RADV_MEM_HEAP_VRAM
,
811 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
812 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
813 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
814 .heapIndex
= RADV_MEM_HEAP_GTT
,
816 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
817 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
818 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
819 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
820 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
822 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
823 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
824 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
825 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
826 .heapIndex
= RADV_MEM_HEAP_GTT
,
829 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
831 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
832 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
833 .size
= physical_device
->rad_info
.vram_size
-
834 physical_device
->rad_info
.visible_vram_size
,
835 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
837 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
838 .size
= physical_device
->rad_info
.visible_vram_size
,
839 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
841 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
842 .size
= physical_device
->rad_info
.gart_size
,
847 void radv_GetPhysicalDeviceMemoryProperties2KHR(
848 VkPhysicalDevice physicalDevice
,
849 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
851 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
852 &pMemoryProperties
->memoryProperties
);
856 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
857 int queue_family_index
, int idx
)
859 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
860 queue
->device
= device
;
861 queue
->queue_family_index
= queue_family_index
;
862 queue
->queue_idx
= idx
;
864 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
866 return VK_ERROR_OUT_OF_HOST_MEMORY
;
872 radv_queue_finish(struct radv_queue
*queue
)
875 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
877 if (queue
->initial_preamble_cs
)
878 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
879 if (queue
->continue_preamble_cs
)
880 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
881 if (queue
->descriptor_bo
)
882 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
883 if (queue
->scratch_bo
)
884 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
885 if (queue
->esgs_ring_bo
)
886 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
887 if (queue
->gsvs_ring_bo
)
888 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
889 if (queue
->tess_factor_ring_bo
)
890 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
891 if (queue
->tess_offchip_ring_bo
)
892 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
893 if (queue
->compute_scratch_bo
)
894 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
898 radv_device_init_gs_info(struct radv_device
*device
)
900 switch (device
->physical_device
->rad_info
.family
) {
909 device
->gs_table_depth
= 16;
920 device
->gs_table_depth
= 32;
923 unreachable("unknown GPU");
927 VkResult
radv_CreateDevice(
928 VkPhysicalDevice physicalDevice
,
929 const VkDeviceCreateInfo
* pCreateInfo
,
930 const VkAllocationCallbacks
* pAllocator
,
933 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
935 struct radv_device
*device
;
937 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
938 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
939 physical_device
->extensions
.num_ext
,
940 pCreateInfo
->ppEnabledExtensionNames
[i
]))
941 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
944 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
946 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
948 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
950 memset(device
, 0, sizeof(*device
));
952 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
953 device
->instance
= physical_device
->instance
;
954 device
->physical_device
= physical_device
;
956 device
->debug_flags
= device
->instance
->debug_flags
;
958 device
->ws
= physical_device
->ws
;
960 device
->alloc
= *pAllocator
;
962 device
->alloc
= physical_device
->instance
->alloc
;
964 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
965 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
966 uint32_t qfi
= queue_create
->queueFamilyIndex
;
968 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
969 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
970 if (!device
->queues
[qfi
]) {
971 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
975 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
977 device
->queue_count
[qfi
] = queue_create
->queueCount
;
979 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
980 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
981 if (result
!= VK_SUCCESS
)
986 #if HAVE_LLVM < 0x0400
987 device
->llvm_supports_spill
= false;
989 device
->llvm_supports_spill
= true;
992 /* The maximum number of scratch waves. Scratch space isn't divided
993 * evenly between CUs. The number is only a function of the number of CUs.
994 * We can decrease the constant to decrease the scratch buffer size.
996 * sctx->scratch_waves must be >= the maximum posible size of
997 * 1 threadgroup, so that the hw doesn't hang from being unable
1000 * The recommended value is 4 per CU at most. Higher numbers don't
1001 * bring much benefit, but they still occupy chip resources (think
1002 * async compute). I've seen ~2% performance difference between 4 and 32.
1004 uint32_t max_threads_per_block
= 2048;
1005 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1006 max_threads_per_block
/ 64);
1008 radv_device_init_gs_info(device
);
1010 device
->tess_offchip_block_dw_size
=
1011 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1012 device
->has_distributed_tess
=
1013 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1014 device
->physical_device
->rad_info
.max_se
>= 2;
1016 result
= radv_device_init_meta(device
);
1017 if (result
!= VK_SUCCESS
)
1020 radv_device_init_msaa(device
);
1022 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1023 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1025 case RADV_QUEUE_GENERAL
:
1026 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1027 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1028 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1030 case RADV_QUEUE_COMPUTE
:
1031 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1032 radeon_emit(device
->empty_cs
[family
], 0);
1035 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1037 device
->flush_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1039 case RADV_QUEUE_GENERAL
:
1040 case RADV_QUEUE_COMPUTE
:
1041 si_cs_emit_cache_flush(device
->flush_cs
[family
],
1042 device
->physical_device
->rad_info
.chip_class
,
1043 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1044 RADV_CMD_FLAG_INV_ICACHE
|
1045 RADV_CMD_FLAG_INV_SMEM_L1
|
1046 RADV_CMD_FLAG_INV_VMEM_L1
|
1047 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1050 device
->ws
->cs_finalize(device
->flush_cs
[family
]);
1052 device
->flush_shader_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1054 case RADV_QUEUE_GENERAL
:
1055 case RADV_QUEUE_COMPUTE
:
1056 si_cs_emit_cache_flush(device
->flush_shader_cs
[family
],
1057 device
->physical_device
->rad_info
.chip_class
,
1058 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1059 family
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) |
1060 RADV_CMD_FLAG_INV_ICACHE
|
1061 RADV_CMD_FLAG_INV_SMEM_L1
|
1062 RADV_CMD_FLAG_INV_VMEM_L1
|
1063 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1066 device
->ws
->cs_finalize(device
->flush_shader_cs
[family
]);
1069 if (getenv("RADV_TRACE_FILE")) {
1070 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
1071 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
1072 if (!device
->trace_bo
)
1075 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
1076 if (!device
->trace_id_ptr
)
1080 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1081 cik_create_gfx_config(device
);
1083 VkPipelineCacheCreateInfo ci
;
1084 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1087 ci
.pInitialData
= NULL
;
1088 ci
.initialDataSize
= 0;
1090 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1092 if (result
!= VK_SUCCESS
)
1095 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1097 *pDevice
= radv_device_to_handle(device
);
1101 if (device
->trace_bo
)
1102 device
->ws
->buffer_destroy(device
->trace_bo
);
1104 if (device
->gfx_init
)
1105 device
->ws
->buffer_destroy(device
->gfx_init
);
1107 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1108 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1109 radv_queue_finish(&device
->queues
[i
][q
]);
1110 if (device
->queue_count
[i
])
1111 vk_free(&device
->alloc
, device
->queues
[i
]);
1114 vk_free(&device
->alloc
, device
);
1118 void radv_DestroyDevice(
1120 const VkAllocationCallbacks
* pAllocator
)
1122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1127 if (device
->trace_bo
)
1128 device
->ws
->buffer_destroy(device
->trace_bo
);
1130 if (device
->gfx_init
)
1131 device
->ws
->buffer_destroy(device
->gfx_init
);
1133 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1134 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1135 radv_queue_finish(&device
->queues
[i
][q
]);
1136 if (device
->queue_count
[i
])
1137 vk_free(&device
->alloc
, device
->queues
[i
]);
1138 if (device
->empty_cs
[i
])
1139 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1140 if (device
->flush_cs
[i
])
1141 device
->ws
->cs_destroy(device
->flush_cs
[i
]);
1142 if (device
->flush_shader_cs
[i
])
1143 device
->ws
->cs_destroy(device
->flush_shader_cs
[i
]);
1145 radv_device_finish_meta(device
);
1147 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1148 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1150 vk_free(&device
->alloc
, device
);
1153 VkResult
radv_EnumerateInstanceExtensionProperties(
1154 const char* pLayerName
,
1155 uint32_t* pPropertyCount
,
1156 VkExtensionProperties
* pProperties
)
1158 if (pProperties
== NULL
) {
1159 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1163 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1164 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1166 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1167 return VK_INCOMPLETE
;
1172 VkResult
radv_EnumerateDeviceExtensionProperties(
1173 VkPhysicalDevice physicalDevice
,
1174 const char* pLayerName
,
1175 uint32_t* pPropertyCount
,
1176 VkExtensionProperties
* pProperties
)
1178 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1180 if (pProperties
== NULL
) {
1181 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1185 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1186 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1188 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1189 return VK_INCOMPLETE
;
1194 VkResult
radv_EnumerateInstanceLayerProperties(
1195 uint32_t* pPropertyCount
,
1196 VkLayerProperties
* pProperties
)
1198 if (pProperties
== NULL
) {
1199 *pPropertyCount
= 0;
1203 /* None supported at this time */
1204 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1207 VkResult
radv_EnumerateDeviceLayerProperties(
1208 VkPhysicalDevice physicalDevice
,
1209 uint32_t* pPropertyCount
,
1210 VkLayerProperties
* pProperties
)
1212 if (pProperties
== NULL
) {
1213 *pPropertyCount
= 0;
1217 /* None supported at this time */
1218 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1221 void radv_GetDeviceQueue(
1223 uint32_t queueFamilyIndex
,
1224 uint32_t queueIndex
,
1227 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1229 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1232 static void radv_dump_trace(struct radv_device
*device
,
1233 struct radeon_winsys_cs
*cs
)
1235 const char *filename
= getenv("RADV_TRACE_FILE");
1236 FILE *f
= fopen(filename
, "w");
1238 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1242 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1243 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1248 fill_geom_tess_rings(struct radv_queue
*queue
,
1250 bool add_sample_positions
,
1251 uint32_t esgs_ring_size
,
1252 struct radeon_winsys_bo
*esgs_ring_bo
,
1253 uint32_t gsvs_ring_size
,
1254 struct radeon_winsys_bo
*gsvs_ring_bo
,
1255 uint32_t tess_factor_ring_size
,
1256 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1257 uint32_t tess_offchip_ring_size
,
1258 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1260 uint64_t esgs_va
= 0, gsvs_va
= 0;
1261 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1262 uint32_t *desc
= &map
[4];
1265 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1267 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1268 if (tess_factor_ring_bo
)
1269 tess_factor_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1270 if (tess_offchip_ring_bo
)
1271 tess_offchip_va
= queue
->device
->ws
->buffer_get_va(tess_offchip_ring_bo
);
1273 /* stride 0, num records - size, add tid, swizzle, elsize4,
1276 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1277 S_008F04_STRIDE(0) |
1278 S_008F04_SWIZZLE_ENABLE(true);
1279 desc
[2] = esgs_ring_size
;
1280 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1281 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1282 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1283 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1284 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1286 S_008F0C_ELEMENT_SIZE(1) |
1287 S_008F0C_INDEX_STRIDE(3) |
1288 S_008F0C_ADD_TID_ENABLE(true);
1291 /* GS entry for ES->GS ring */
1292 /* stride 0, num records - size, elsize0,
1295 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1296 S_008F04_STRIDE(0) |
1297 S_008F04_SWIZZLE_ENABLE(false);
1298 desc
[2] = esgs_ring_size
;
1299 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1300 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1301 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1302 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1303 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1304 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1305 S_008F0C_ELEMENT_SIZE(0) |
1306 S_008F0C_INDEX_STRIDE(0) |
1307 S_008F0C_ADD_TID_ENABLE(false);
1310 /* VS entry for GS->VS ring */
1311 /* stride 0, num records - size, elsize0,
1314 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1315 S_008F04_STRIDE(0) |
1316 S_008F04_SWIZZLE_ENABLE(false);
1317 desc
[2] = gsvs_ring_size
;
1318 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1319 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1320 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1321 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1322 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1324 S_008F0C_ELEMENT_SIZE(0) |
1325 S_008F0C_INDEX_STRIDE(0) |
1326 S_008F0C_ADD_TID_ENABLE(false);
1329 /* stride gsvs_itemsize, num records 64
1330 elsize 4, index stride 16 */
1331 /* shader will patch stride and desc[2] */
1333 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1334 S_008F04_STRIDE(0) |
1335 S_008F04_SWIZZLE_ENABLE(true);
1337 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1338 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1339 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1340 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1341 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1342 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1343 S_008F0C_ELEMENT_SIZE(1) |
1344 S_008F0C_INDEX_STRIDE(1) |
1345 S_008F0C_ADD_TID_ENABLE(true);
1348 desc
[0] = tess_factor_va
;
1349 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1350 S_008F04_STRIDE(0) |
1351 S_008F04_SWIZZLE_ENABLE(false);
1352 desc
[2] = tess_factor_ring_size
;
1353 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1354 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1355 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1356 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1357 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1358 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1359 S_008F0C_ELEMENT_SIZE(0) |
1360 S_008F0C_INDEX_STRIDE(0) |
1361 S_008F0C_ADD_TID_ENABLE(false);
1364 desc
[0] = tess_offchip_va
;
1365 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1366 S_008F04_STRIDE(0) |
1367 S_008F04_SWIZZLE_ENABLE(false);
1368 desc
[2] = tess_offchip_ring_size
;
1369 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1370 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1371 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1372 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1373 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1374 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1375 S_008F0C_ELEMENT_SIZE(0) |
1376 S_008F0C_INDEX_STRIDE(0) |
1377 S_008F0C_ADD_TID_ENABLE(false);
1380 /* add sample positions after all rings */
1381 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1383 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1385 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1387 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1389 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1393 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1395 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1396 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1397 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1398 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1399 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1400 device
->physical_device
->rad_info
.max_se
;
1401 unsigned offchip_granularity
;
1402 unsigned hs_offchip_param
;
1403 switch (device
->tess_offchip_block_dw_size
) {
1408 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1411 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1415 switch (device
->physical_device
->rad_info
.chip_class
) {
1417 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1420 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1424 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
1428 *max_offchip_buffers_p
= max_offchip_buffers
;
1429 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1430 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1431 --max_offchip_buffers
;
1433 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1434 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1437 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1439 return hs_offchip_param
;
1443 radv_get_preamble_cs(struct radv_queue
*queue
,
1444 uint32_t scratch_size
,
1445 uint32_t compute_scratch_size
,
1446 uint32_t esgs_ring_size
,
1447 uint32_t gsvs_ring_size
,
1448 bool needs_tess_rings
,
1449 bool needs_sample_positions
,
1450 struct radeon_winsys_cs
**initial_preamble_cs
,
1451 struct radeon_winsys_cs
**continue_preamble_cs
)
1453 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1454 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1455 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1456 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1457 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1458 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1459 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1460 struct radeon_winsys_cs
*dest_cs
[2] = {0};
1461 bool add_tess_rings
= false, add_sample_positions
= false;
1462 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1463 unsigned max_offchip_buffers
;
1464 unsigned hs_offchip_param
= 0;
1465 if (!queue
->has_tess_rings
) {
1466 if (needs_tess_rings
)
1467 add_tess_rings
= true;
1469 if (!queue
->has_sample_positions
) {
1470 if (needs_sample_positions
)
1471 add_sample_positions
= true;
1473 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1474 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1475 &max_offchip_buffers
);
1476 tess_offchip_ring_size
= max_offchip_buffers
*
1477 queue
->device
->tess_offchip_block_dw_size
* 4;
1479 if (scratch_size
<= queue
->scratch_size
&&
1480 compute_scratch_size
<= queue
->compute_scratch_size
&&
1481 esgs_ring_size
<= queue
->esgs_ring_size
&&
1482 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1483 !add_tess_rings
&& !add_sample_positions
&&
1484 queue
->initial_preamble_cs
) {
1485 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1486 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1487 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1488 *continue_preamble_cs
= NULL
;
1492 if (scratch_size
> queue
->scratch_size
) {
1493 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1497 RADEON_FLAG_NO_CPU_ACCESS
);
1501 scratch_bo
= queue
->scratch_bo
;
1503 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1504 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1505 compute_scratch_size
,
1508 RADEON_FLAG_NO_CPU_ACCESS
);
1509 if (!compute_scratch_bo
)
1513 compute_scratch_bo
= queue
->compute_scratch_bo
;
1515 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1516 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1520 RADEON_FLAG_NO_CPU_ACCESS
);
1524 esgs_ring_bo
= queue
->esgs_ring_bo
;
1525 esgs_ring_size
= queue
->esgs_ring_size
;
1528 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1529 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1533 RADEON_FLAG_NO_CPU_ACCESS
);
1537 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1538 gsvs_ring_size
= queue
->gsvs_ring_size
;
1541 if (add_tess_rings
) {
1542 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1543 tess_factor_ring_size
,
1546 RADEON_FLAG_NO_CPU_ACCESS
);
1547 if (!tess_factor_ring_bo
)
1549 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1550 tess_offchip_ring_size
,
1553 RADEON_FLAG_NO_CPU_ACCESS
);
1554 if (!tess_offchip_ring_bo
)
1557 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1558 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1561 if (scratch_bo
!= queue
->scratch_bo
||
1562 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1563 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1564 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1565 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1567 if (gsvs_ring_bo
|| esgs_ring_bo
||
1568 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1569 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1570 if (add_sample_positions
)
1571 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1573 else if (scratch_bo
)
1574 size
= 8; /* 2 dword */
1576 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1580 RADEON_FLAG_CPU_ACCESS
);
1584 descriptor_bo
= queue
->descriptor_bo
;
1586 for(int i
= 0; i
< 2; ++i
) {
1587 struct radeon_winsys_cs
*cs
= NULL
;
1588 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1589 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1596 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1599 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1602 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1604 if (tess_factor_ring_bo
)
1605 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1607 if (tess_offchip_ring_bo
)
1608 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1611 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1613 if (descriptor_bo
!= queue
->descriptor_bo
) {
1614 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1617 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1618 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1619 S_008F04_SWIZZLE_ENABLE(1);
1620 map
[0] = scratch_va
;
1624 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1625 add_sample_positions
)
1626 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1627 esgs_ring_size
, esgs_ring_bo
,
1628 gsvs_ring_size
, gsvs_ring_bo
,
1629 tess_factor_ring_size
, tess_factor_ring_bo
,
1630 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1632 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1635 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1636 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1637 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1638 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1639 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1642 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1643 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1644 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1645 radeon_emit(cs
, esgs_ring_size
>> 8);
1646 radeon_emit(cs
, gsvs_ring_size
>> 8);
1648 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1649 radeon_emit(cs
, esgs_ring_size
>> 8);
1650 radeon_emit(cs
, gsvs_ring_size
>> 8);
1654 if (tess_factor_ring_bo
) {
1655 uint64_t tf_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1656 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1657 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1658 S_030938_SIZE(tess_factor_ring_size
/ 4));
1659 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1661 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1663 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1664 S_008988_SIZE(tess_factor_ring_size
/ 4));
1665 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1667 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1672 if (descriptor_bo
) {
1673 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1674 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1675 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1676 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1677 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1678 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1680 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1682 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1683 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1684 radeon_emit(cs
, va
);
1685 radeon_emit(cs
, va
>> 32);
1689 if (compute_scratch_bo
) {
1690 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1691 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1692 S_008F04_SWIZZLE_ENABLE(1);
1694 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1696 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1697 radeon_emit(cs
, scratch_va
);
1698 radeon_emit(cs
, rsrc1
);
1702 si_cs_emit_cache_flush(cs
,
1703 queue
->device
->physical_device
->rad_info
.chip_class
,
1704 queue
->queue_family_index
== RING_COMPUTE
&&
1705 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1706 RADV_CMD_FLAG_INV_ICACHE
|
1707 RADV_CMD_FLAG_INV_SMEM_L1
|
1708 RADV_CMD_FLAG_INV_VMEM_L1
|
1709 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1712 if (!queue
->device
->ws
->cs_finalize(cs
))
1716 if (queue
->initial_preamble_cs
)
1717 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1719 if (queue
->continue_preamble_cs
)
1720 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1722 queue
->initial_preamble_cs
= dest_cs
[0];
1723 queue
->continue_preamble_cs
= dest_cs
[1];
1725 if (scratch_bo
!= queue
->scratch_bo
) {
1726 if (queue
->scratch_bo
)
1727 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1728 queue
->scratch_bo
= scratch_bo
;
1729 queue
->scratch_size
= scratch_size
;
1732 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1733 if (queue
->compute_scratch_bo
)
1734 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1735 queue
->compute_scratch_bo
= compute_scratch_bo
;
1736 queue
->compute_scratch_size
= compute_scratch_size
;
1739 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1740 if (queue
->esgs_ring_bo
)
1741 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1742 queue
->esgs_ring_bo
= esgs_ring_bo
;
1743 queue
->esgs_ring_size
= esgs_ring_size
;
1746 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1747 if (queue
->gsvs_ring_bo
)
1748 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1749 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1750 queue
->gsvs_ring_size
= gsvs_ring_size
;
1753 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1754 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1757 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1758 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1759 queue
->has_tess_rings
= true;
1762 if (descriptor_bo
!= queue
->descriptor_bo
) {
1763 if (queue
->descriptor_bo
)
1764 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1766 queue
->descriptor_bo
= descriptor_bo
;
1769 if (add_sample_positions
)
1770 queue
->has_sample_positions
= true;
1772 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1773 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1774 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1775 *continue_preamble_cs
= NULL
;
1778 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1780 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1781 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1782 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1783 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1784 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1785 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1786 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1787 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1788 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1789 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1790 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1791 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1792 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1793 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1794 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1795 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1798 VkResult
radv_QueueSubmit(
1800 uint32_t submitCount
,
1801 const VkSubmitInfo
* pSubmits
,
1804 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1805 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1806 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1807 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1809 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1810 uint32_t scratch_size
= 0;
1811 uint32_t compute_scratch_size
= 0;
1812 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1813 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1815 bool fence_emitted
= false;
1816 bool tess_rings_needed
= false;
1817 bool sample_positions_needed
= false;
1819 /* Do this first so failing to allocate scratch buffers can't result in
1820 * partially executed submissions. */
1821 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1822 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1823 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1824 pSubmits
[i
].pCommandBuffers
[j
]);
1826 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1827 compute_scratch_size
= MAX2(compute_scratch_size
,
1828 cmd_buffer
->compute_scratch_size_needed
);
1829 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1830 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1831 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1832 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1836 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1837 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1838 sample_positions_needed
,
1839 &initial_preamble_cs
, &continue_preamble_cs
);
1840 if (result
!= VK_SUCCESS
)
1843 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1844 struct radeon_winsys_cs
**cs_array
;
1845 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1846 bool can_patch
= !do_flush
;
1849 if (!pSubmits
[i
].commandBufferCount
) {
1850 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1851 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1852 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1854 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1855 pSubmits
[i
].waitSemaphoreCount
,
1856 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1857 pSubmits
[i
].signalSemaphoreCount
,
1860 radv_loge("failed to submit CS %d\n", i
);
1863 fence_emitted
= true;
1868 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1869 (pSubmits
[i
].commandBufferCount
+ do_flush
));
1872 cs_array
[0] = pSubmits
[i
].waitSemaphoreCount
?
1873 queue
->device
->flush_shader_cs
[queue
->queue_family_index
] :
1874 queue
->device
->flush_cs
[queue
->queue_family_index
];
1876 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1877 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1878 pSubmits
[i
].pCommandBuffers
[j
]);
1879 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1881 cs_array
[j
+ do_flush
] = cmd_buffer
->cs
;
1882 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1886 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
+ do_flush
; j
+= advance
) {
1887 advance
= MIN2(max_cs_submission
,
1888 pSubmits
[i
].commandBufferCount
+ do_flush
- j
);
1890 bool e
= j
+ advance
== pSubmits
[i
].commandBufferCount
+ do_flush
;
1892 if (queue
->device
->trace_bo
)
1893 *queue
->device
->trace_id_ptr
= 0;
1895 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1896 advance
, initial_preamble_cs
, continue_preamble_cs
,
1897 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1898 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1899 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1900 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1901 can_patch
, base_fence
);
1904 radv_loge("failed to submit CS %d\n", i
);
1907 fence_emitted
= true;
1908 if (queue
->device
->trace_bo
) {
1909 bool success
= queue
->device
->ws
->ctx_wait_idle(
1911 radv_queue_family_to_ring(
1912 queue
->queue_family_index
),
1915 if (!success
) { /* Hang */
1916 radv_dump_trace(queue
->device
, cs_array
[j
]);
1926 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1927 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1928 1, NULL
, NULL
, NULL
, 0, NULL
, 0,
1931 fence
->submitted
= true;
1937 VkResult
radv_QueueWaitIdle(
1940 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1942 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
1943 radv_queue_family_to_ring(queue
->queue_family_index
),
1948 VkResult
radv_DeviceWaitIdle(
1951 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1953 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1954 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
1955 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
1961 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
1962 VkInstance instance
,
1965 return radv_lookup_entrypoint(pName
);
1968 /* The loader wants us to expose a second GetInstanceProcAddr function
1969 * to work around certain LD_PRELOAD issues seen in apps.
1972 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1973 VkInstance instance
,
1977 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1978 VkInstance instance
,
1981 return radv_GetInstanceProcAddr(instance
, pName
);
1984 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
1988 return radv_lookup_entrypoint(pName
);
1991 bool radv_get_memory_fd(struct radv_device
*device
,
1992 struct radv_device_memory
*memory
,
1995 struct radeon_bo_metadata metadata
;
1997 if (memory
->image
) {
1998 radv_init_metadata(device
, memory
->image
, &metadata
);
1999 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2002 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2006 VkResult
radv_AllocateMemory(
2008 const VkMemoryAllocateInfo
* pAllocateInfo
,
2009 const VkAllocationCallbacks
* pAllocator
,
2010 VkDeviceMemory
* pMem
)
2012 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2013 struct radv_device_memory
*mem
;
2015 enum radeon_bo_domain domain
;
2017 const VkDedicatedAllocationMemoryAllocateInfoNV
*dedicate_info
= NULL
;
2018 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2020 if (pAllocateInfo
->allocationSize
== 0) {
2021 /* Apparently, this is allowed */
2022 *pMem
= VK_NULL_HANDLE
;
2026 vk_foreach_struct(ext
, pAllocateInfo
->pNext
) {
2027 switch (ext
->sType
) {
2028 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV
:
2029 dedicate_info
= (const VkDedicatedAllocationMemoryAllocateInfoNV
*)ext
;
2036 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2037 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2039 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2041 if (dedicate_info
) {
2042 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2043 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2049 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2050 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2051 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2052 domain
= RADEON_DOMAIN_GTT
;
2054 domain
= RADEON_DOMAIN_VRAM
;
2056 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2057 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2059 flags
|= RADEON_FLAG_CPU_ACCESS
;
2061 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2062 flags
|= RADEON_FLAG_GTT_WC
;
2064 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, 65536,
2068 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2071 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2073 *pMem
= radv_device_memory_to_handle(mem
);
2078 vk_free2(&device
->alloc
, pAllocator
, mem
);
2083 void radv_FreeMemory(
2085 VkDeviceMemory _mem
,
2086 const VkAllocationCallbacks
* pAllocator
)
2088 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2089 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2094 device
->ws
->buffer_destroy(mem
->bo
);
2097 vk_free2(&device
->alloc
, pAllocator
, mem
);
2100 VkResult
radv_MapMemory(
2102 VkDeviceMemory _memory
,
2103 VkDeviceSize offset
,
2105 VkMemoryMapFlags flags
,
2108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2109 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2116 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2122 return VK_ERROR_MEMORY_MAP_FAILED
;
2125 void radv_UnmapMemory(
2127 VkDeviceMemory _memory
)
2129 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2130 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2135 device
->ws
->buffer_unmap(mem
->bo
);
2138 VkResult
radv_FlushMappedMemoryRanges(
2140 uint32_t memoryRangeCount
,
2141 const VkMappedMemoryRange
* pMemoryRanges
)
2146 VkResult
radv_InvalidateMappedMemoryRanges(
2148 uint32_t memoryRangeCount
,
2149 const VkMappedMemoryRange
* pMemoryRanges
)
2154 void radv_GetBufferMemoryRequirements(
2157 VkMemoryRequirements
* pMemoryRequirements
)
2159 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2161 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2163 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2164 pMemoryRequirements
->alignment
= 4096;
2166 pMemoryRequirements
->alignment
= 16;
2168 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2171 void radv_GetImageMemoryRequirements(
2174 VkMemoryRequirements
* pMemoryRequirements
)
2176 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2178 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2180 pMemoryRequirements
->size
= image
->size
;
2181 pMemoryRequirements
->alignment
= image
->alignment
;
2184 void radv_GetImageSparseMemoryRequirements(
2187 uint32_t* pSparseMemoryRequirementCount
,
2188 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2193 void radv_GetDeviceMemoryCommitment(
2195 VkDeviceMemory memory
,
2196 VkDeviceSize
* pCommittedMemoryInBytes
)
2198 *pCommittedMemoryInBytes
= 0;
2201 VkResult
radv_BindBufferMemory(
2204 VkDeviceMemory _memory
,
2205 VkDeviceSize memoryOffset
)
2207 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2208 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2211 buffer
->bo
= mem
->bo
;
2212 buffer
->offset
= memoryOffset
;
2221 VkResult
radv_BindImageMemory(
2224 VkDeviceMemory _memory
,
2225 VkDeviceSize memoryOffset
)
2227 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2228 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2231 image
->bo
= mem
->bo
;
2232 image
->offset
= memoryOffset
;
2243 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2244 const VkSparseBufferMemoryBindInfo
*bind
)
2246 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2248 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2249 struct radv_device_memory
*mem
= NULL
;
2251 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2252 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2254 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2255 bind
->pBinds
[i
].resourceOffset
,
2256 bind
->pBinds
[i
].size
,
2257 mem
? mem
->bo
: NULL
,
2258 bind
->pBinds
[i
].memoryOffset
);
2263 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2264 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2266 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2268 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2269 struct radv_device_memory
*mem
= NULL
;
2271 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2272 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2274 device
->ws
->buffer_virtual_bind(image
->bo
,
2275 bind
->pBinds
[i
].resourceOffset
,
2276 bind
->pBinds
[i
].size
,
2277 mem
? mem
->bo
: NULL
,
2278 bind
->pBinds
[i
].memoryOffset
);
2282 VkResult
radv_QueueBindSparse(
2284 uint32_t bindInfoCount
,
2285 const VkBindSparseInfo
* pBindInfo
,
2288 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2289 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2290 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2291 bool fence_emitted
= false;
2293 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2294 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2295 radv_sparse_buffer_bind_memory(queue
->device
,
2296 pBindInfo
[i
].pBufferBinds
+ j
);
2299 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2300 radv_sparse_image_opaque_bind_memory(queue
->device
,
2301 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2304 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2305 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2306 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2308 (struct radeon_winsys_sem
**)pBindInfo
[i
].pWaitSemaphores
,
2309 pBindInfo
[i
].waitSemaphoreCount
,
2310 (struct radeon_winsys_sem
**)pBindInfo
[i
].pSignalSemaphores
,
2311 pBindInfo
[i
].signalSemaphoreCount
,
2313 fence_emitted
= true;
2315 fence
->submitted
= true;
2319 if (fence
&& !fence_emitted
) {
2320 fence
->signalled
= true;
2326 VkResult
radv_CreateFence(
2328 const VkFenceCreateInfo
* pCreateInfo
,
2329 const VkAllocationCallbacks
* pAllocator
,
2332 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2333 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2335 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2338 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2340 memset(fence
, 0, sizeof(*fence
));
2341 fence
->submitted
= false;
2342 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2343 fence
->fence
= device
->ws
->create_fence();
2344 if (!fence
->fence
) {
2345 vk_free2(&device
->alloc
, pAllocator
, fence
);
2346 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2349 *pFence
= radv_fence_to_handle(fence
);
2354 void radv_DestroyFence(
2357 const VkAllocationCallbacks
* pAllocator
)
2359 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2360 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2364 device
->ws
->destroy_fence(fence
->fence
);
2365 vk_free2(&device
->alloc
, pAllocator
, fence
);
2368 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2370 uint64_t current_time
;
2373 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2374 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2376 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2378 return current_time
+ timeout
;
2381 VkResult
radv_WaitForFences(
2383 uint32_t fenceCount
,
2384 const VkFence
* pFences
,
2388 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2389 timeout
= radv_get_absolute_timeout(timeout
);
2391 if (!waitAll
&& fenceCount
> 1) {
2392 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2395 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2396 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2397 bool expired
= false;
2399 if (fence
->signalled
)
2402 if (!fence
->submitted
)
2405 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2409 fence
->signalled
= true;
2415 VkResult
radv_ResetFences(VkDevice device
,
2416 uint32_t fenceCount
,
2417 const VkFence
*pFences
)
2419 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2420 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2421 fence
->submitted
= fence
->signalled
= false;
2427 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2429 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2430 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2432 if (fence
->signalled
)
2434 if (!fence
->submitted
)
2435 return VK_NOT_READY
;
2437 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2438 return VK_NOT_READY
;
2444 // Queue semaphore functions
2446 VkResult
radv_CreateSemaphore(
2448 const VkSemaphoreCreateInfo
* pCreateInfo
,
2449 const VkAllocationCallbacks
* pAllocator
,
2450 VkSemaphore
* pSemaphore
)
2452 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2453 struct radeon_winsys_sem
*sem
;
2455 sem
= device
->ws
->create_sem(device
->ws
);
2457 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2459 *pSemaphore
= radeon_winsys_sem_to_handle(sem
);
2463 void radv_DestroySemaphore(
2465 VkSemaphore _semaphore
,
2466 const VkAllocationCallbacks
* pAllocator
)
2468 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2469 RADV_FROM_HANDLE(radeon_winsys_sem
, sem
, _semaphore
);
2473 device
->ws
->destroy_sem(sem
);
2476 VkResult
radv_CreateEvent(
2478 const VkEventCreateInfo
* pCreateInfo
,
2479 const VkAllocationCallbacks
* pAllocator
,
2482 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2483 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2485 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2488 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2490 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2492 RADEON_FLAG_CPU_ACCESS
);
2494 vk_free2(&device
->alloc
, pAllocator
, event
);
2495 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2498 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2500 *pEvent
= radv_event_to_handle(event
);
2505 void radv_DestroyEvent(
2508 const VkAllocationCallbacks
* pAllocator
)
2510 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2511 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2515 device
->ws
->buffer_destroy(event
->bo
);
2516 vk_free2(&device
->alloc
, pAllocator
, event
);
2519 VkResult
radv_GetEventStatus(
2523 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2525 if (*event
->map
== 1)
2526 return VK_EVENT_SET
;
2527 return VK_EVENT_RESET
;
2530 VkResult
radv_SetEvent(
2534 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2540 VkResult
radv_ResetEvent(
2544 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2550 VkResult
radv_CreateBuffer(
2552 const VkBufferCreateInfo
* pCreateInfo
,
2553 const VkAllocationCallbacks
* pAllocator
,
2556 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2557 struct radv_buffer
*buffer
;
2559 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2561 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2562 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2564 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2566 buffer
->size
= pCreateInfo
->size
;
2567 buffer
->usage
= pCreateInfo
->usage
;
2570 buffer
->flags
= pCreateInfo
->flags
;
2572 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2573 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2574 align64(buffer
->size
, 4096),
2575 4096, 0, RADEON_FLAG_VIRTUAL
);
2577 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2578 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2582 *pBuffer
= radv_buffer_to_handle(buffer
);
2587 void radv_DestroyBuffer(
2590 const VkAllocationCallbacks
* pAllocator
)
2592 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2593 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2598 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2599 device
->ws
->buffer_destroy(buffer
->bo
);
2601 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2604 static inline unsigned
2605 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2608 return image
->surface
.stencil_tiling_index
[level
];
2610 return image
->surface
.tiling_index
[level
];
2613 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2615 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2619 radv_initialise_color_surface(struct radv_device
*device
,
2620 struct radv_color_buffer_info
*cb
,
2621 struct radv_image_view
*iview
)
2623 const struct vk_format_description
*desc
;
2624 unsigned ntype
, format
, swap
, endian
;
2625 unsigned blend_clamp
= 0, blend_bypass
= 0;
2626 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2628 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2629 const struct radeon_surf_level
*level_info
= &surf
->level
[iview
->base_mip
];
2631 desc
= vk_format_description(iview
->vk_format
);
2633 memset(cb
, 0, sizeof(*cb
));
2635 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2636 va
+= level_info
->offset
;
2637 cb
->cb_color_base
= va
>> 8;
2639 /* CMASK variables */
2640 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2641 va
+= iview
->image
->cmask
.offset
;
2642 cb
->cb_color_cmask
= va
>> 8;
2643 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2645 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2646 va
+= iview
->image
->dcc_offset
;
2647 cb
->cb_dcc_base
= va
>> 8;
2649 uint32_t max_slice
= radv_surface_layer_count(iview
);
2650 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2651 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2653 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2654 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2655 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2656 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2658 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2659 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2661 /* Intensity is implemented as Red, so treat it that way. */
2662 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
) |
2663 S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2665 if (iview
->image
->info
.samples
> 1) {
2666 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2668 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2669 S_028C74_NUM_FRAGMENTS(log_samples
);
2672 if (iview
->image
->fmask
.size
) {
2673 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2674 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2675 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2676 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2677 cb
->cb_color_fmask
= va
>> 8;
2678 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2680 /* This must be set for fast clear to work without FMASK. */
2681 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2682 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2683 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2684 cb
->cb_color_fmask
= cb
->cb_color_base
;
2685 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2688 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2690 vk_format_get_first_non_void_channel(iview
->vk_format
));
2691 format
= radv_translate_colorformat(iview
->vk_format
);
2692 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2693 radv_finishme("Illegal color\n");
2694 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2695 endian
= radv_colorformat_endian_swap(format
);
2697 /* blend clamp should be set for all NORM/SRGB types */
2698 if (ntype
== V_028C70_NUMBER_UNORM
||
2699 ntype
== V_028C70_NUMBER_SNORM
||
2700 ntype
== V_028C70_NUMBER_SRGB
)
2703 /* set blend bypass according to docs if SINT/UINT or
2704 8/24 COLOR variants */
2705 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2706 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2707 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2712 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2713 (format
== V_028C70_COLOR_8
||
2714 format
== V_028C70_COLOR_8_8
||
2715 format
== V_028C70_COLOR_8_8_8_8
))
2716 ->color_is_int8
= true;
2718 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2719 S_028C70_COMP_SWAP(swap
) |
2720 S_028C70_BLEND_CLAMP(blend_clamp
) |
2721 S_028C70_BLEND_BYPASS(blend_bypass
) |
2722 S_028C70_SIMPLE_FLOAT(1) |
2723 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2724 ntype
!= V_028C70_NUMBER_SNORM
&&
2725 ntype
!= V_028C70_NUMBER_SRGB
&&
2726 format
!= V_028C70_COLOR_8_24
&&
2727 format
!= V_028C70_COLOR_24_8
) |
2728 S_028C70_NUMBER_TYPE(ntype
) |
2729 S_028C70_ENDIAN(endian
);
2730 if (iview
->image
->info
.samples
> 1)
2731 if (iview
->image
->fmask
.size
)
2732 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2734 if (iview
->image
->cmask
.size
&&
2735 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2736 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2738 if (iview
->image
->surface
.dcc_size
&& level_info
->dcc_enabled
)
2739 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2741 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2742 unsigned max_uncompressed_block_size
= 2;
2743 if (iview
->image
->info
.samples
> 1) {
2744 if (iview
->image
->surface
.bpe
== 1)
2745 max_uncompressed_block_size
= 0;
2746 else if (iview
->image
->surface
.bpe
== 2)
2747 max_uncompressed_block_size
= 1;
2750 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2751 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2754 /* This must be set for fast clear to work without FMASK. */
2755 if (!iview
->image
->fmask
.size
&&
2756 device
->physical_device
->rad_info
.chip_class
== SI
) {
2757 unsigned bankh
= util_logbase2(iview
->image
->surface
.bankh
);
2758 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2763 radv_initialise_ds_surface(struct radv_device
*device
,
2764 struct radv_ds_buffer_info
*ds
,
2765 struct radv_image_view
*iview
)
2767 unsigned level
= iview
->base_mip
;
2769 uint64_t va
, s_offs
, z_offs
;
2770 const struct radeon_surf_level
*level_info
= &iview
->image
->surface
.level
[level
];
2771 bool stencil_only
= false;
2772 memset(ds
, 0, sizeof(*ds
));
2773 switch (iview
->vk_format
) {
2774 case VK_FORMAT_D24_UNORM_S8_UINT
:
2775 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2776 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2777 ds
->offset_scale
= 2.0f
;
2779 case VK_FORMAT_D16_UNORM
:
2780 case VK_FORMAT_D16_UNORM_S8_UINT
:
2781 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2782 ds
->offset_scale
= 4.0f
;
2784 case VK_FORMAT_D32_SFLOAT
:
2785 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2786 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2787 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2788 ds
->offset_scale
= 1.0f
;
2790 case VK_FORMAT_S8_UINT
:
2791 stencil_only
= true;
2792 level_info
= &iview
->image
->surface
.stencil_level
[level
];
2798 format
= radv_translate_dbformat(iview
->vk_format
);
2800 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2801 s_offs
= z_offs
= va
;
2802 z_offs
+= iview
->image
->surface
.level
[level
].offset
;
2803 s_offs
+= iview
->image
->surface
.stencil_level
[level
].offset
;
2805 uint32_t max_slice
= radv_surface_layer_count(iview
);
2806 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2807 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2808 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2809 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2811 if (iview
->image
->info
.samples
> 1)
2812 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
2814 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
)
2815 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2817 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2819 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2820 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2821 unsigned tiling_index
= iview
->image
->surface
.tiling_index
[level
];
2822 unsigned stencil_index
= iview
->image
->surface
.stencil_tiling_index
[level
];
2823 unsigned macro_index
= iview
->image
->surface
.macro_tile_index
;
2824 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2825 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2826 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2829 tile_mode
= stencil_tile_mode
;
2831 ds
->db_depth_info
|=
2832 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2833 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2834 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2835 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2836 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2837 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2838 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2839 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2841 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2842 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2843 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2844 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2847 if (iview
->image
->surface
.htile_size
&& !level
) {
2848 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2849 S_028040_ALLOW_EXPCLEAR(1);
2851 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2852 /* Workaround: For a not yet understood reason, the
2853 * combination of MSAA, fast stencil clear and stencil
2854 * decompress messes with subsequent stencil buffer
2855 * uses. Problem was reproduced on Verde, Bonaire,
2856 * Tonga, and Carrizo.
2858 * Disabling EXPCLEAR works around the problem.
2860 * Check piglit's arb_texture_multisample-stencil-clear
2861 * test if you want to try changing this.
2863 if (iview
->image
->info
.samples
<= 1)
2864 ds
->db_stencil_info
|= S_028044_ALLOW_EXPCLEAR(1);
2866 /* Use all of the htile_buffer for depth if there's no stencil. */
2867 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2869 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2870 iview
->image
->htile_offset
;
2871 ds
->db_htile_data_base
= va
>> 8;
2872 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2874 ds
->db_htile_data_base
= 0;
2875 ds
->db_htile_surface
= 0;
2878 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
2879 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
2881 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2882 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2883 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
2886 VkResult
radv_CreateFramebuffer(
2888 const VkFramebufferCreateInfo
* pCreateInfo
,
2889 const VkAllocationCallbacks
* pAllocator
,
2890 VkFramebuffer
* pFramebuffer
)
2892 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2893 struct radv_framebuffer
*framebuffer
;
2895 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
2897 size_t size
= sizeof(*framebuffer
) +
2898 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
2899 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
2900 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2901 if (framebuffer
== NULL
)
2902 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2904 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
2905 framebuffer
->width
= pCreateInfo
->width
;
2906 framebuffer
->height
= pCreateInfo
->height
;
2907 framebuffer
->layers
= pCreateInfo
->layers
;
2908 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
2909 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
2910 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
2911 framebuffer
->attachments
[i
].attachment
= iview
;
2912 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
2913 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
2914 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2915 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
2917 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
2918 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
2919 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
2922 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
2926 void radv_DestroyFramebuffer(
2929 const VkAllocationCallbacks
* pAllocator
)
2931 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2932 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
2936 vk_free2(&device
->alloc
, pAllocator
, fb
);
2939 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
2941 switch (address_mode
) {
2942 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
2943 return V_008F30_SQ_TEX_WRAP
;
2944 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
2945 return V_008F30_SQ_TEX_MIRROR
;
2946 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
2947 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
2948 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
2949 return V_008F30_SQ_TEX_CLAMP_BORDER
;
2950 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
2951 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2953 unreachable("illegal tex wrap mode");
2959 radv_tex_compare(VkCompareOp op
)
2962 case VK_COMPARE_OP_NEVER
:
2963 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
2964 case VK_COMPARE_OP_LESS
:
2965 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
2966 case VK_COMPARE_OP_EQUAL
:
2967 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2968 case VK_COMPARE_OP_LESS_OR_EQUAL
:
2969 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2970 case VK_COMPARE_OP_GREATER
:
2971 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
2972 case VK_COMPARE_OP_NOT_EQUAL
:
2973 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2974 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
2975 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2976 case VK_COMPARE_OP_ALWAYS
:
2977 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2979 unreachable("illegal compare mode");
2985 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
2988 case VK_FILTER_NEAREST
:
2989 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
2990 V_008F38_SQ_TEX_XY_FILTER_POINT
);
2991 case VK_FILTER_LINEAR
:
2992 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
2993 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
2994 case VK_FILTER_CUBIC_IMG
:
2996 fprintf(stderr
, "illegal texture filter");
3002 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3005 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3006 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3007 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3008 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3010 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3015 radv_tex_bordercolor(VkBorderColor bcolor
)
3018 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3019 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3020 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3021 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3022 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3023 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3024 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3025 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3026 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3034 radv_tex_aniso_filter(unsigned filter
)
3048 radv_init_sampler(struct radv_device
*device
,
3049 struct radv_sampler
*sampler
,
3050 const VkSamplerCreateInfo
*pCreateInfo
)
3052 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3053 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3054 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3055 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3057 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3058 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3059 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3060 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3061 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3062 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3063 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3064 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3065 S_008F30_DISABLE_CUBE_WRAP(0) |
3066 S_008F30_COMPAT_MODE(is_vi
));
3067 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3068 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3069 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3070 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3071 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3072 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3073 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3074 S_008F38_MIP_POINT_PRECLAMP(0) |
3075 S_008F38_DISABLE_LSB_CEIL(1) |
3076 S_008F38_FILTER_PREC_FIX(1) |
3077 S_008F38_ANISO_OVERRIDE(is_vi
));
3078 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3079 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3082 VkResult
radv_CreateSampler(
3084 const VkSamplerCreateInfo
* pCreateInfo
,
3085 const VkAllocationCallbacks
* pAllocator
,
3086 VkSampler
* pSampler
)
3088 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3089 struct radv_sampler
*sampler
;
3091 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3093 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3094 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3096 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3098 radv_init_sampler(device
, sampler
, pCreateInfo
);
3099 *pSampler
= radv_sampler_to_handle(sampler
);
3104 void radv_DestroySampler(
3107 const VkAllocationCallbacks
* pAllocator
)
3109 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3110 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3114 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3118 /* vk_icd.h does not declare this function, so we declare it here to
3119 * suppress Wmissing-prototypes.
3121 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3122 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3124 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3125 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3127 /* For the full details on loader interface versioning, see
3128 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3129 * What follows is a condensed summary, to help you navigate the large and
3130 * confusing official doc.
3132 * - Loader interface v0 is incompatible with later versions. We don't
3135 * - In loader interface v1:
3136 * - The first ICD entrypoint called by the loader is
3137 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3139 * - The ICD must statically expose no other Vulkan symbol unless it is
3140 * linked with -Bsymbolic.
3141 * - Each dispatchable Vulkan handle created by the ICD must be
3142 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3143 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3144 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3145 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3146 * such loader-managed surfaces.
3148 * - Loader interface v2 differs from v1 in:
3149 * - The first ICD entrypoint called by the loader is
3150 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3151 * statically expose this entrypoint.
3153 * - Loader interface v3 differs from v2 in:
3154 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3155 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3156 * because the loader no longer does so.
3158 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);