2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/xmlpool.h"
69 static struct radv_timeline_point
*
70 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
71 struct radv_timeline
*timeline
,
74 static struct radv_timeline_point
*
75 radv_timeline_add_point_locked(struct radv_device
*device
,
76 struct radv_timeline
*timeline
,
80 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
81 struct list_head
*processing_list
);
84 void radv_destroy_semaphore_part(struct radv_device
*device
,
85 struct radv_semaphore_part
*part
);
88 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
91 unsigned char sha1
[20];
92 unsigned ptr_size
= sizeof(void*);
94 memset(uuid
, 0, VK_UUID_SIZE
);
95 _mesa_sha1_init(&ctx
);
97 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
98 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
101 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
102 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
103 _mesa_sha1_final(&ctx
, sha1
);
105 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
110 radv_get_driver_uuid(void *uuid
)
112 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
116 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
118 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
122 radv_get_visible_vram_size(struct radv_physical_device
*device
)
124 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
128 radv_get_vram_size(struct radv_physical_device
*device
)
130 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
134 radv_is_mem_type_vram(enum radv_mem_type type
)
136 return type
== RADV_MEM_TYPE_VRAM
||
137 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
141 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
143 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
144 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
147 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
149 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
150 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
154 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
156 return type
== RADV_MEM_TYPE_GTT_CACHED
||
157 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
161 radv_is_mem_type_uncached(enum radv_mem_type type
)
163 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
164 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
166 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
170 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
172 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
173 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
174 uint64_t vram_size
= radv_get_vram_size(device
);
175 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
176 device
->memory_properties
.memoryHeapCount
= 0;
178 vram_index
= device
->memory_properties
.memoryHeapCount
++;
179 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
181 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
184 if (visible_vram_size
) {
185 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
186 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
187 .size
= visible_vram_size
,
188 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
191 if (device
->rad_info
.gart_size
> 0) {
192 gart_index
= device
->memory_properties
.memoryHeapCount
++;
193 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
194 .size
= device
->rad_info
.gart_size
,
195 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
199 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
200 unsigned type_count
= 0;
201 if (vram_index
>= 0) {
202 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
203 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
204 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
205 .heapIndex
= vram_index
,
208 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
209 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
210 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
211 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
212 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
213 .heapIndex
= gart_index
,
216 if (visible_vram_index
>= 0) {
217 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
218 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
219 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
220 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
221 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
222 .heapIndex
= visible_vram_index
,
225 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
226 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
227 * as they have identical property flags, and according to the
228 * spec, for types with identical flags, the one with greater
229 * performance must be given a lower index. */
230 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
231 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
232 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
233 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
234 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
235 .heapIndex
= gart_index
,
238 if (gart_index
>= 0) {
239 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
240 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
241 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
242 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
243 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
244 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
245 .heapIndex
= gart_index
,
248 device
->memory_properties
.memoryTypeCount
= type_count
;
250 if (device
->rad_info
.has_l2_uncached
) {
251 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
252 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
254 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
255 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
256 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
257 enum radv_mem_type mem_type_id
;
259 switch (device
->mem_type_indices
[i
]) {
260 case RADV_MEM_TYPE_VRAM
:
261 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
263 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
264 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
266 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
267 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
269 case RADV_MEM_TYPE_GTT_CACHED
:
270 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
273 unreachable("invalid memory type");
276 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
277 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
278 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
280 device
->mem_type_indices
[type_count
] = mem_type_id
;
281 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
282 .propertyFlags
= property_flags
,
283 .heapIndex
= mem_type
.heapIndex
,
287 device
->memory_properties
.memoryTypeCount
= type_count
;
292 radv_physical_device_init(struct radv_physical_device
*device
,
293 struct radv_instance
*instance
,
294 drmDevicePtr drm_device
)
301 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
302 drmVersionPtr version
;
304 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
306 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
307 radv_logi("Could not open device '%s'", path
);
309 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
312 version
= drmGetVersion(fd
);
316 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
317 radv_logi("Could not get the kernel driver version for device '%s'", path
);
319 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
320 "failed to get version %s: %m", path
);
323 if (strcmp(version
->name
, "amdgpu")) {
324 drmFreeVersion(version
);
327 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
328 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
330 return VK_ERROR_INCOMPATIBLE_DRIVER
;
332 drmFreeVersion(version
);
334 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
335 radv_logi("Found compatible device '%s'.", path
);
338 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
339 device
->instance
= instance
;
342 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
343 instance
->perftest_flags
);
345 device
->ws
= radv_null_winsys_create();
349 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
353 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
354 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
355 if (master_fd
>= 0) {
356 uint32_t accel_working
= 0;
357 struct drm_amdgpu_info request
= {
358 .return_pointer
= (uintptr_t)&accel_working
,
359 .return_size
= sizeof(accel_working
),
360 .query
= AMDGPU_INFO_ACCEL_WORKING
363 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
370 device
->master_fd
= master_fd
;
371 device
->local_fd
= fd
;
372 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
374 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
376 snprintf(device
->name
, sizeof(device
->name
),
377 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
378 device
->rad_info
.name
);
380 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
381 device
->ws
->destroy(device
->ws
);
382 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
383 "cannot generate UUID");
387 /* These flags affect shader compilation. */
388 uint64_t shader_env_flags
= (device
->use_aco
? 0x2 : 0);
390 /* The gpu id is already embedded in the uuid so we just pass "radv"
391 * when creating the cache.
393 char buf
[VK_UUID_SIZE
* 2 + 1];
394 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
395 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
397 if (device
->rad_info
.chip_class
< GFX8
)
398 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
400 radv_get_driver_uuid(&device
->driver_uuid
);
401 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
403 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
404 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
406 device
->dcc_msaa_allowed
=
407 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
409 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
410 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
412 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
413 device
->rad_info
.family
!= CHIP_NAVI14
&&
414 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
415 if (device
->use_aco
&& device
->use_ngg
) {
416 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
417 device
->use_ngg
= false;
420 device
->use_ngg_streamout
= false;
422 /* Determine the number of threads per wave for all stages. */
423 device
->cs_wave_size
= 64;
424 device
->ps_wave_size
= 64;
425 device
->ge_wave_size
= 64;
427 if (device
->rad_info
.chip_class
>= GFX10
) {
428 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
429 device
->cs_wave_size
= 32;
431 /* For pixel shaders, wave64 is recommanded. */
432 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
433 device
->ps_wave_size
= 32;
435 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
436 device
->ge_wave_size
= 32;
439 radv_physical_device_init_mem_types(device
);
440 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
443 device
->bus_info
= *drm_device
->businfo
.pci
;
445 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
446 ac_print_gpu_info(&device
->rad_info
);
448 /* The WSI is structured as a layer on top of the driver, so this has
449 * to be the last part of initialization (at least until we get other
452 result
= radv_init_wsi(device
);
453 if (result
!= VK_SUCCESS
) {
454 device
->ws
->destroy(device
->ws
);
455 vk_error(instance
, result
);
469 radv_physical_device_finish(struct radv_physical_device
*device
)
471 radv_finish_wsi(device
);
472 device
->ws
->destroy(device
->ws
);
473 disk_cache_destroy(device
->disk_cache
);
474 close(device
->local_fd
);
475 if (device
->master_fd
!= -1)
476 close(device
->master_fd
);
480 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
481 VkSystemAllocationScope allocationScope
)
487 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
488 size_t align
, VkSystemAllocationScope allocationScope
)
490 return realloc(pOriginal
, size
);
494 default_free_func(void *pUserData
, void *pMemory
)
499 static const VkAllocationCallbacks default_alloc
= {
501 .pfnAllocation
= default_alloc_func
,
502 .pfnReallocation
= default_realloc_func
,
503 .pfnFree
= default_free_func
,
506 static const struct debug_control radv_debug_options
[] = {
507 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
508 {"nodcc", RADV_DEBUG_NO_DCC
},
509 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
510 {"nocache", RADV_DEBUG_NO_CACHE
},
511 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
512 {"nohiz", RADV_DEBUG_NO_HIZ
},
513 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
514 {"allbos", RADV_DEBUG_ALL_BOS
},
515 {"noibs", RADV_DEBUG_NO_IBS
},
516 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
517 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
518 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
519 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
520 {"preoptir", RADV_DEBUG_PREOPTIR
},
521 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
522 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
523 {"info", RADV_DEBUG_INFO
},
524 {"errors", RADV_DEBUG_ERRORS
},
525 {"startup", RADV_DEBUG_STARTUP
},
526 {"checkir", RADV_DEBUG_CHECKIR
},
527 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
528 {"nobinning", RADV_DEBUG_NOBINNING
},
529 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
530 {"nongg", RADV_DEBUG_NO_NGG
},
531 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
532 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
533 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
534 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
539 radv_get_debug_option_name(int id
)
541 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
542 return radv_debug_options
[id
].string
;
545 static const struct debug_control radv_perftest_options
[] = {
546 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
547 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
548 {"bolist", RADV_PERFTEST_BO_LIST
},
549 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
550 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
551 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
552 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
553 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
554 {"dfsm", RADV_PERFTEST_DFSM
},
555 {"aco", RADV_PERFTEST_ACO
},
560 radv_get_perftest_option_name(int id
)
562 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
563 return radv_perftest_options
[id
].string
;
567 radv_handle_per_app_options(struct radv_instance
*instance
,
568 const VkApplicationInfo
*info
)
570 const char *name
= info
? info
->pApplicationName
: NULL
;
575 if (!strcmp(name
, "DOOM_VFR")) {
576 /* Work around a Doom VFR game bug */
577 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
578 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
579 /* Workaround for a WaW hazard when LLVM moves/merges
580 * load/store memory operations.
581 * See https://reviews.llvm.org/D61313
583 if (LLVM_VERSION_MAJOR
< 9)
584 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
585 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
586 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
587 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
588 /* Force enable VK_AMD_shader_ballot because it looks
589 * safe and it gives a nice boost (+20% on Vega 56 at
590 * this time). It also prevents corruption on LLVM.
592 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
594 } else if (!strcmp(name
, "Fledge")) {
596 * Zero VRAM for "The Surge 2"
598 * This avoid a hang when when rendering any level. Likely
599 * uninitialized data in an indirect draw.
601 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
605 static int radv_get_instance_extension_index(const char *name
)
607 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
608 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
614 static const char radv_dri_options_xml
[] =
616 DRI_CONF_SECTION_PERFORMANCE
617 DRI_CONF_ADAPTIVE_SYNC("true")
618 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
619 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
622 DRI_CONF_SECTION_DEBUG
623 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
627 static void radv_init_dri_options(struct radv_instance
*instance
)
629 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
630 driParseConfigFiles(&instance
->dri_options
,
631 &instance
->available_dri_options
,
633 instance
->engineName
,
634 instance
->engineVersion
);
637 VkResult
radv_CreateInstance(
638 const VkInstanceCreateInfo
* pCreateInfo
,
639 const VkAllocationCallbacks
* pAllocator
,
640 VkInstance
* pInstance
)
642 struct radv_instance
*instance
;
645 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
647 uint32_t client_version
;
648 if (pCreateInfo
->pApplicationInfo
&&
649 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
650 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
652 client_version
= VK_API_VERSION_1_0
;
655 const char *engine_name
= NULL
;
656 uint32_t engine_version
= 0;
657 if (pCreateInfo
->pApplicationInfo
) {
658 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
659 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
662 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
665 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
667 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
670 instance
->alloc
= *pAllocator
;
672 instance
->alloc
= default_alloc
;
674 instance
->apiVersion
= client_version
;
675 instance
->physicalDeviceCount
= -1;
677 /* Get secure compile thread count. NOTE: We cap this at 32 */
678 #define MAX_SC_PROCS 32
679 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
681 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
683 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
686 /* Disable memory cache when secure compile is set */
687 if (radv_device_use_secure_compile(instance
))
688 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
690 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
691 radv_perftest_options
);
693 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
694 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
696 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
697 radv_logi("Created an instance");
699 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
700 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
701 int index
= radv_get_instance_extension_index(ext_name
);
703 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
704 vk_free2(&default_alloc
, pAllocator
, instance
);
705 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
708 instance
->enabled_extensions
.extensions
[index
] = true;
711 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
712 if (result
!= VK_SUCCESS
) {
713 vk_free2(&default_alloc
, pAllocator
, instance
);
714 return vk_error(instance
, result
);
717 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
718 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
719 instance
->engineVersion
= engine_version
;
721 glsl_type_singleton_init_or_ref();
723 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
725 radv_init_dri_options(instance
);
726 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
728 *pInstance
= radv_instance_to_handle(instance
);
733 void radv_DestroyInstance(
734 VkInstance _instance
,
735 const VkAllocationCallbacks
* pAllocator
)
737 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
742 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
743 radv_physical_device_finish(instance
->physicalDevices
+ i
);
746 vk_free(&instance
->alloc
, instance
->engineName
);
748 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
750 glsl_type_singleton_decref();
752 driDestroyOptionCache(&instance
->dri_options
);
753 driDestroyOptionInfo(&instance
->available_dri_options
);
755 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
757 vk_free(&instance
->alloc
, instance
);
761 radv_enumerate_devices(struct radv_instance
*instance
)
763 /* TODO: Check for more devices ? */
764 drmDevicePtr devices
[8];
765 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
768 instance
->physicalDeviceCount
= 0;
770 if (getenv("RADV_FORCE_FAMILY")) {
771 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
772 * device that allows to test the compiler without having an
775 result
= radv_physical_device_init(instance
->physicalDevices
+
776 instance
->physicalDeviceCount
,
779 ++instance
->physicalDeviceCount
;
783 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
785 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
786 radv_logi("Found %d drm nodes", max_devices
);
789 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
791 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
792 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
793 devices
[i
]->bustype
== DRM_BUS_PCI
&&
794 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
796 result
= radv_physical_device_init(instance
->physicalDevices
+
797 instance
->physicalDeviceCount
,
800 if (result
== VK_SUCCESS
)
801 ++instance
->physicalDeviceCount
;
802 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
806 drmFreeDevices(devices
, max_devices
);
811 VkResult
radv_EnumeratePhysicalDevices(
812 VkInstance _instance
,
813 uint32_t* pPhysicalDeviceCount
,
814 VkPhysicalDevice
* pPhysicalDevices
)
816 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
819 if (instance
->physicalDeviceCount
< 0) {
820 result
= radv_enumerate_devices(instance
);
821 if (result
!= VK_SUCCESS
&&
822 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
826 if (!pPhysicalDevices
) {
827 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
829 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
830 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
831 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
834 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
838 VkResult
radv_EnumeratePhysicalDeviceGroups(
839 VkInstance _instance
,
840 uint32_t* pPhysicalDeviceGroupCount
,
841 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
843 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
846 if (instance
->physicalDeviceCount
< 0) {
847 result
= radv_enumerate_devices(instance
);
848 if (result
!= VK_SUCCESS
&&
849 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
853 if (!pPhysicalDeviceGroupProperties
) {
854 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
856 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
857 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
858 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
859 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
860 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
863 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
867 void radv_GetPhysicalDeviceFeatures(
868 VkPhysicalDevice physicalDevice
,
869 VkPhysicalDeviceFeatures
* pFeatures
)
871 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
872 memset(pFeatures
, 0, sizeof(*pFeatures
));
874 *pFeatures
= (VkPhysicalDeviceFeatures
) {
875 .robustBufferAccess
= true,
876 .fullDrawIndexUint32
= true,
877 .imageCubeArray
= true,
878 .independentBlend
= true,
879 .geometryShader
= true,
880 .tessellationShader
= true,
881 .sampleRateShading
= true,
882 .dualSrcBlend
= true,
884 .multiDrawIndirect
= true,
885 .drawIndirectFirstInstance
= true,
887 .depthBiasClamp
= true,
888 .fillModeNonSolid
= true,
893 .multiViewport
= true,
894 .samplerAnisotropy
= true,
895 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
896 .textureCompressionASTC_LDR
= false,
897 .textureCompressionBC
= true,
898 .occlusionQueryPrecise
= true,
899 .pipelineStatisticsQuery
= true,
900 .vertexPipelineStoresAndAtomics
= true,
901 .fragmentStoresAndAtomics
= true,
902 .shaderTessellationAndGeometryPointSize
= true,
903 .shaderImageGatherExtended
= true,
904 .shaderStorageImageExtendedFormats
= true,
905 .shaderStorageImageMultisample
= true,
906 .shaderUniformBufferArrayDynamicIndexing
= true,
907 .shaderSampledImageArrayDynamicIndexing
= true,
908 .shaderStorageBufferArrayDynamicIndexing
= true,
909 .shaderStorageImageArrayDynamicIndexing
= true,
910 .shaderStorageImageReadWithoutFormat
= true,
911 .shaderStorageImageWriteWithoutFormat
= true,
912 .shaderClipDistance
= true,
913 .shaderCullDistance
= true,
914 .shaderFloat64
= true,
916 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
917 .sparseBinding
= true,
918 .variableMultisampleRate
= true,
919 .inheritedQueries
= true,
923 void radv_GetPhysicalDeviceFeatures2(
924 VkPhysicalDevice physicalDevice
,
925 VkPhysicalDeviceFeatures2
*pFeatures
)
927 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
928 vk_foreach_struct(ext
, pFeatures
->pNext
) {
929 switch (ext
->sType
) {
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
931 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
932 features
->variablePointersStorageBuffer
= true;
933 features
->variablePointers
= true;
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
937 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
938 features
->multiview
= true;
939 features
->multiviewGeometryShader
= true;
940 features
->multiviewTessellationShader
= true;
943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
944 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
945 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
946 features
->shaderDrawParameters
= true;
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
950 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
951 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
952 features
->protectedMemory
= false;
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
956 VkPhysicalDevice16BitStorageFeatures
*features
=
957 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
958 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
959 features
->storageBuffer16BitAccess
= enabled
;
960 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
961 features
->storagePushConstant16
= enabled
;
962 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
966 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
967 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
968 features
->samplerYcbcrConversion
= true;
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
972 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
973 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
974 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
975 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
976 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
977 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
978 features
->shaderSampledImageArrayNonUniformIndexing
= true;
979 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
980 features
->shaderStorageImageArrayNonUniformIndexing
= true;
981 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
982 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
983 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
984 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
985 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
986 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
987 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
988 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
989 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
990 features
->descriptorBindingUpdateUnusedWhilePending
= true;
991 features
->descriptorBindingPartiallyBound
= true;
992 features
->descriptorBindingVariableDescriptorCount
= true;
993 features
->runtimeDescriptorArray
= true;
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
997 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
998 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
999 features
->conditionalRendering
= true;
1000 features
->inheritedConditionalRendering
= false;
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1004 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1005 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1006 features
->vertexAttributeInstanceRateDivisor
= true;
1007 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1011 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1012 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1013 features
->transformFeedback
= true;
1014 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1018 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1019 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1020 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1023 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1024 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1025 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1026 features
->memoryPriority
= true;
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1030 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1031 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1032 features
->bufferDeviceAddress
= true;
1033 features
->bufferDeviceAddressCaptureReplay
= false;
1034 features
->bufferDeviceAddressMultiDevice
= false;
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1038 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1039 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1040 features
->bufferDeviceAddress
= true;
1041 features
->bufferDeviceAddressCaptureReplay
= false;
1042 features
->bufferDeviceAddressMultiDevice
= false;
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1046 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1047 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1048 features
->depthClipEnable
= true;
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1052 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1053 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1054 features
->hostQueryReset
= true;
1057 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1058 VkPhysicalDevice8BitStorageFeatures
*features
=
1059 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1060 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1061 features
->storageBuffer8BitAccess
= enabled
;
1062 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1063 features
->storagePushConstant8
= enabled
;
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1067 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1068 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1069 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1070 features
->shaderInt8
= !pdevice
->use_aco
;
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1074 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1075 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1076 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1077 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1081 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1082 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1083 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1087 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1088 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1090 features
->inlineUniformBlock
= true;
1091 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1095 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1096 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1097 features
->computeDerivativeGroupQuads
= false;
1098 features
->computeDerivativeGroupLinear
= true;
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1102 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1103 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1104 features
->ycbcrImageArrays
= true;
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1108 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1109 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1110 features
->uniformBufferStandardLayout
= true;
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1114 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1115 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1116 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1119 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1120 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1121 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1122 features
->imagelessFramebuffer
= true;
1125 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1126 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1127 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1128 features
->pipelineExecutableInfo
= true;
1131 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1132 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1133 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1134 features
->shaderSubgroupClock
= true;
1135 features
->shaderDeviceClock
= false;
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1139 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1140 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1141 features
->texelBufferAlignment
= true;
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1145 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1146 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1147 features
->timelineSemaphore
= true;
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1151 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1152 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1153 features
->subgroupSizeControl
= true;
1154 features
->computeFullSubgroups
= true;
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1158 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1159 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1160 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1164 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1165 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1166 features
->shaderSubgroupExtendedTypes
= true;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1170 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1171 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1172 features
->separateDepthStencilLayouts
= true;
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1176 VkPhysicalDeviceVulkan11Features
*features
=
1177 (VkPhysicalDeviceVulkan11Features
*)ext
;
1178 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1179 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1180 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1181 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1182 features
->multiview
= true;
1183 features
->multiviewGeometryShader
= true;
1184 features
->multiviewTessellationShader
= true;
1185 features
->variablePointersStorageBuffer
= true;
1186 features
->variablePointers
= true;
1187 features
->protectedMemory
= false;
1188 features
->samplerYcbcrConversion
= true;
1189 features
->shaderDrawParameters
= true;
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1193 VkPhysicalDeviceVulkan12Features
*features
=
1194 (VkPhysicalDeviceVulkan12Features
*)ext
;
1195 features
->samplerMirrorClampToEdge
= true;
1196 features
->drawIndirectCount
= true;
1197 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1198 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1199 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1200 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1201 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1202 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1203 features
->shaderInt8
= !pdevice
->use_aco
;
1204 features
->descriptorIndexing
= true;
1205 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1206 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1207 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1208 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1209 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1210 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1211 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1212 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1213 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1214 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1215 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1216 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1217 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1218 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1219 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1220 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1221 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1222 features
->descriptorBindingPartiallyBound
= true;
1223 features
->descriptorBindingVariableDescriptorCount
= true;
1224 features
->runtimeDescriptorArray
= true;
1225 features
->samplerFilterMinmax
= true;
1226 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1227 features
->imagelessFramebuffer
= true;
1228 features
->uniformBufferStandardLayout
= true;
1229 features
->shaderSubgroupExtendedTypes
= true;
1230 features
->separateDepthStencilLayouts
= true;
1231 features
->hostQueryReset
= true;
1232 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1233 features
->bufferDeviceAddress
= true;
1234 features
->bufferDeviceAddressCaptureReplay
= false;
1235 features
->bufferDeviceAddressMultiDevice
= false;
1236 features
->vulkanMemoryModel
= false;
1237 features
->vulkanMemoryModelDeviceScope
= false;
1238 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1239 features
->shaderOutputViewportIndex
= true;
1240 features
->shaderOutputLayer
= true;
1241 features
->subgroupBroadcastDynamicId
= true;
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1245 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1246 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1247 features
->rectangularLines
= false;
1248 features
->bresenhamLines
= true;
1249 features
->smoothLines
= false;
1250 features
->stippledRectangularLines
= false;
1251 features
->stippledBresenhamLines
= true;
1252 features
->stippledSmoothLines
= false;
1259 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1263 radv_max_descriptor_set_size()
1265 /* make sure that the entire descriptor set is addressable with a signed
1266 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1267 * be at most 2 GiB. the combined image & samples object count as one of
1268 * both. This limit is for the pipeline layout, not for the set layout, but
1269 * there is no set limit, so we just set a pipeline limit. I don't think
1270 * any app is going to hit this soon. */
1271 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1272 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1273 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1274 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1275 32 /* sampler, largest when combined with image */ +
1276 64 /* sampled image */ +
1277 64 /* storage image */);
1280 void radv_GetPhysicalDeviceProperties(
1281 VkPhysicalDevice physicalDevice
,
1282 VkPhysicalDeviceProperties
* pProperties
)
1284 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1285 VkSampleCountFlags sample_counts
= 0xf;
1287 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1289 VkPhysicalDeviceLimits limits
= {
1290 .maxImageDimension1D
= (1 << 14),
1291 .maxImageDimension2D
= (1 << 14),
1292 .maxImageDimension3D
= (1 << 11),
1293 .maxImageDimensionCube
= (1 << 14),
1294 .maxImageArrayLayers
= (1 << 11),
1295 .maxTexelBufferElements
= 128 * 1024 * 1024,
1296 .maxUniformBufferRange
= UINT32_MAX
,
1297 .maxStorageBufferRange
= UINT32_MAX
,
1298 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1299 .maxMemoryAllocationCount
= UINT32_MAX
,
1300 .maxSamplerAllocationCount
= 64 * 1024,
1301 .bufferImageGranularity
= 64, /* A cache line */
1302 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1303 .maxBoundDescriptorSets
= MAX_SETS
,
1304 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1305 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1306 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1307 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1308 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1309 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1310 .maxPerStageResources
= max_descriptor_set_size
,
1311 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1312 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1313 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1314 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1315 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1316 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1317 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1318 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1319 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1320 .maxVertexInputBindings
= MAX_VBS
,
1321 .maxVertexInputAttributeOffset
= 2047,
1322 .maxVertexInputBindingStride
= 2048,
1323 .maxVertexOutputComponents
= 128,
1324 .maxTessellationGenerationLevel
= 64,
1325 .maxTessellationPatchSize
= 32,
1326 .maxTessellationControlPerVertexInputComponents
= 128,
1327 .maxTessellationControlPerVertexOutputComponents
= 128,
1328 .maxTessellationControlPerPatchOutputComponents
= 120,
1329 .maxTessellationControlTotalOutputComponents
= 4096,
1330 .maxTessellationEvaluationInputComponents
= 128,
1331 .maxTessellationEvaluationOutputComponents
= 128,
1332 .maxGeometryShaderInvocations
= 127,
1333 .maxGeometryInputComponents
= 64,
1334 .maxGeometryOutputComponents
= 128,
1335 .maxGeometryOutputVertices
= 256,
1336 .maxGeometryTotalOutputComponents
= 1024,
1337 .maxFragmentInputComponents
= 128,
1338 .maxFragmentOutputAttachments
= 8,
1339 .maxFragmentDualSrcAttachments
= 1,
1340 .maxFragmentCombinedOutputResources
= 8,
1341 .maxComputeSharedMemorySize
= 32768,
1342 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1343 .maxComputeWorkGroupInvocations
= 1024,
1344 .maxComputeWorkGroupSize
= {
1349 .subPixelPrecisionBits
= 8,
1350 .subTexelPrecisionBits
= 8,
1351 .mipmapPrecisionBits
= 8,
1352 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1353 .maxDrawIndirectCount
= UINT32_MAX
,
1354 .maxSamplerLodBias
= 16,
1355 .maxSamplerAnisotropy
= 16,
1356 .maxViewports
= MAX_VIEWPORTS
,
1357 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1358 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1359 .viewportSubPixelBits
= 8,
1360 .minMemoryMapAlignment
= 4096, /* A page */
1361 .minTexelBufferOffsetAlignment
= 4,
1362 .minUniformBufferOffsetAlignment
= 4,
1363 .minStorageBufferOffsetAlignment
= 4,
1364 .minTexelOffset
= -32,
1365 .maxTexelOffset
= 31,
1366 .minTexelGatherOffset
= -32,
1367 .maxTexelGatherOffset
= 31,
1368 .minInterpolationOffset
= -2,
1369 .maxInterpolationOffset
= 2,
1370 .subPixelInterpolationOffsetBits
= 8,
1371 .maxFramebufferWidth
= (1 << 14),
1372 .maxFramebufferHeight
= (1 << 14),
1373 .maxFramebufferLayers
= (1 << 10),
1374 .framebufferColorSampleCounts
= sample_counts
,
1375 .framebufferDepthSampleCounts
= sample_counts
,
1376 .framebufferStencilSampleCounts
= sample_counts
,
1377 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1378 .maxColorAttachments
= MAX_RTS
,
1379 .sampledImageColorSampleCounts
= sample_counts
,
1380 .sampledImageIntegerSampleCounts
= sample_counts
,
1381 .sampledImageDepthSampleCounts
= sample_counts
,
1382 .sampledImageStencilSampleCounts
= sample_counts
,
1383 .storageImageSampleCounts
= sample_counts
,
1384 .maxSampleMaskWords
= 1,
1385 .timestampComputeAndGraphics
= true,
1386 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1387 .maxClipDistances
= 8,
1388 .maxCullDistances
= 8,
1389 .maxCombinedClipAndCullDistances
= 8,
1390 .discreteQueuePriorities
= 2,
1391 .pointSizeRange
= { 0.0, 8192.0 },
1392 .lineWidthRange
= { 0.0, 8192.0 },
1393 .pointSizeGranularity
= (1.0 / 8.0),
1394 .lineWidthGranularity
= (1.0 / 8.0),
1395 .strictLines
= false, /* FINISHME */
1396 .standardSampleLocations
= true,
1397 .optimalBufferCopyOffsetAlignment
= 128,
1398 .optimalBufferCopyRowPitchAlignment
= 128,
1399 .nonCoherentAtomSize
= 64,
1402 *pProperties
= (VkPhysicalDeviceProperties
) {
1403 .apiVersion
= radv_physical_device_api_version(pdevice
),
1404 .driverVersion
= vk_get_driver_version(),
1405 .vendorID
= ATI_VENDOR_ID
,
1406 .deviceID
= pdevice
->rad_info
.pci_id
,
1407 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1409 .sparseProperties
= {0},
1412 strcpy(pProperties
->deviceName
, pdevice
->name
);
1413 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1417 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1418 VkPhysicalDeviceVulkan11Properties
*p
)
1420 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1422 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1423 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1424 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1425 /* The LUID is for Windows. */
1426 p
->deviceLUIDValid
= false;
1427 p
->deviceNodeMask
= 0;
1429 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1430 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1431 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1432 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1433 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1434 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1435 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1436 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1438 if (pdevice
->rad_info
.chip_class
== GFX8
||
1439 pdevice
->rad_info
.chip_class
== GFX9
) {
1440 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1441 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1443 p
->subgroupQuadOperationsInAllStages
= true;
1445 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1446 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1447 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1448 p
->protectedNoFault
= false;
1449 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1450 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1454 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1455 VkPhysicalDeviceVulkan12Properties
*p
)
1457 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1459 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1460 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1461 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1462 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1463 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1464 p
->conformanceVersion
= (VkConformanceVersion
) {
1471 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1472 * controlled by the same config register.
1474 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1475 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1477 /* Do not allow both preserving and flushing denorms because different
1478 * shaders in the same pipeline can have different settings and this
1479 * won't work for merged shaders. To make it work, this requires LLVM
1480 * support for changing the register. The same logic applies for the
1481 * rounding modes because they are configured with the same config
1482 * register. TODO: we can enable a lot of these for ACO when it
1483 * supports all stages.
1485 p
->shaderDenormFlushToZeroFloat32
= true;
1486 p
->shaderDenormPreserveFloat32
= false;
1487 p
->shaderRoundingModeRTEFloat32
= true;
1488 p
->shaderRoundingModeRTZFloat32
= false;
1489 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1491 p
->shaderDenormFlushToZeroFloat16
= false;
1492 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1493 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1494 p
->shaderRoundingModeRTZFloat16
= false;
1495 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1497 p
->shaderDenormFlushToZeroFloat64
= false;
1498 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1499 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1500 p
->shaderRoundingModeRTZFloat64
= false;
1501 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1503 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1504 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1505 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1506 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1507 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1508 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1509 p
->robustBufferAccessUpdateAfterBind
= false;
1510 p
->quadDivergentImplicitLod
= false;
1512 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1513 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1514 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1515 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1516 32 /* sampler, largest when combined with image */ +
1517 64 /* sampled image */ +
1518 64 /* storage image */);
1519 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1520 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1521 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1522 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1523 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1524 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1525 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1526 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1527 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1528 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1529 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1530 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1531 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1532 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1533 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1535 /* We support all of the depth resolve modes */
1536 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1537 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1538 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1539 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1541 /* Average doesn't make sense for stencil so we don't support that */
1542 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1543 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1544 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1546 p
->independentResolveNone
= true;
1547 p
->independentResolve
= true;
1549 /* GFX6-8 only support single channel min/max filter. */
1550 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1551 p
->filterMinmaxSingleComponentFormats
= true;
1553 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1555 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1558 void radv_GetPhysicalDeviceProperties2(
1559 VkPhysicalDevice physicalDevice
,
1560 VkPhysicalDeviceProperties2
*pProperties
)
1562 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1563 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1565 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1566 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1568 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1570 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1571 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1573 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1575 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1576 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1577 sizeof(core_##major##_##minor.core_property))
1579 #define CORE_PROPERTY(major, minor, property) \
1580 CORE_RENAMED_PROPERTY(major, minor, property, property)
1582 vk_foreach_struct(ext
, pProperties
->pNext
) {
1583 switch (ext
->sType
) {
1584 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1585 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1586 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1587 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1590 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1591 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1592 CORE_PROPERTY(1, 1, deviceUUID
);
1593 CORE_PROPERTY(1, 1, driverUUID
);
1594 CORE_PROPERTY(1, 1, deviceLUID
);
1595 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1598 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1599 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1600 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1601 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1604 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1605 VkPhysicalDevicePointClippingProperties
*properties
=
1606 (VkPhysicalDevicePointClippingProperties
*)ext
;
1607 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1610 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1611 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1612 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1613 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1616 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1617 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1618 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1619 properties
->minImportedHostPointerAlignment
= 4096;
1622 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1623 VkPhysicalDeviceSubgroupProperties
*properties
=
1624 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1625 CORE_PROPERTY(1, 1, subgroupSize
);
1626 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1627 subgroupSupportedStages
);
1628 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1629 subgroupSupportedOperations
);
1630 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1631 subgroupQuadOperationsInAllStages
);
1634 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1635 VkPhysicalDeviceMaintenance3Properties
*properties
=
1636 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1637 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1638 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1641 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1642 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1643 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1644 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1645 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1648 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1649 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1650 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1652 /* Shader engines. */
1653 properties
->shaderEngineCount
=
1654 pdevice
->rad_info
.max_se
;
1655 properties
->shaderArraysPerEngineCount
=
1656 pdevice
->rad_info
.max_sh_per_se
;
1657 properties
->computeUnitsPerShaderArray
=
1658 pdevice
->rad_info
.num_good_cu_per_sh
;
1659 properties
->simdPerComputeUnit
=
1660 pdevice
->rad_info
.num_simd_per_compute_unit
;
1661 properties
->wavefrontsPerSimd
=
1662 pdevice
->rad_info
.max_wave64_per_simd
;
1663 properties
->wavefrontSize
= 64;
1666 properties
->sgprsPerSimd
=
1667 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1668 properties
->minSgprAllocation
=
1669 pdevice
->rad_info
.min_sgpr_alloc
;
1670 properties
->maxSgprAllocation
=
1671 pdevice
->rad_info
.max_sgpr_alloc
;
1672 properties
->sgprAllocationGranularity
=
1673 pdevice
->rad_info
.sgpr_alloc_granularity
;
1676 properties
->vgprsPerSimd
=
1677 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1678 properties
->minVgprAllocation
=
1679 pdevice
->rad_info
.min_vgpr_alloc
;
1680 properties
->maxVgprAllocation
=
1681 pdevice
->rad_info
.max_vgpr_alloc
;
1682 properties
->vgprAllocationGranularity
=
1683 pdevice
->rad_info
.vgpr_alloc_granularity
;
1686 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1687 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1688 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1690 properties
->shaderCoreFeatures
= 0;
1691 properties
->activeComputeUnitCount
=
1692 pdevice
->rad_info
.num_good_compute_units
;
1695 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1696 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1697 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1698 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1701 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1702 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1703 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1704 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1705 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1706 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1707 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1708 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1709 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1710 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1711 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1712 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1713 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1714 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1715 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1716 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1717 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1718 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1719 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1720 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1721 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1722 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1723 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1724 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1725 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1726 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1730 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1731 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1732 CORE_PROPERTY(1, 1, protectedNoFault
);
1735 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1736 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1737 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1738 properties
->primitiveOverestimationSize
= 0;
1739 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1740 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1741 properties
->primitiveUnderestimation
= false;
1742 properties
->conservativePointAndLineRasterization
= false;
1743 properties
->degenerateTrianglesRasterized
= false;
1744 properties
->degenerateLinesRasterized
= false;
1745 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1746 properties
->conservativeRasterizationPostDepthCoverage
= false;
1749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1750 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1751 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1752 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1753 properties
->pciBus
= pdevice
->bus_info
.bus
;
1754 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1755 properties
->pciFunction
= pdevice
->bus_info
.func
;
1758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1759 VkPhysicalDeviceDriverProperties
*properties
=
1760 (VkPhysicalDeviceDriverProperties
*) ext
;
1761 CORE_PROPERTY(1, 2, driverID
);
1762 CORE_PROPERTY(1, 2, driverName
);
1763 CORE_PROPERTY(1, 2, driverInfo
);
1764 CORE_PROPERTY(1, 2, conformanceVersion
);
1767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1768 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1769 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1770 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1771 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1772 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1773 properties
->maxTransformFeedbackStreamDataSize
= 512;
1774 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1775 properties
->maxTransformFeedbackBufferDataStride
= 512;
1776 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1777 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1778 properties
->transformFeedbackRasterizationStreamSelect
= false;
1779 properties
->transformFeedbackDraw
= true;
1782 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1783 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1784 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1786 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1787 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1788 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1789 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1790 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1794 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1795 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1796 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1797 VK_SAMPLE_COUNT_4_BIT
|
1798 VK_SAMPLE_COUNT_8_BIT
;
1799 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1800 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1801 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1802 properties
->sampleLocationSubPixelBits
= 4;
1803 properties
->variableSampleLocations
= false;
1806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1807 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1808 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1809 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1810 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1811 CORE_PROPERTY(1, 2, independentResolveNone
);
1812 CORE_PROPERTY(1, 2, independentResolve
);
1815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1816 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1817 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1818 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1819 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1820 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1821 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1825 VkPhysicalDeviceFloatControlsProperties
*properties
=
1826 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1827 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1828 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1829 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1830 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1831 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1832 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1833 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1834 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1835 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1836 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1837 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1838 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1839 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1840 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1841 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1842 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1843 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1847 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1848 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1849 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1852 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1853 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1854 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1855 props
->minSubgroupSize
= 64;
1856 props
->maxSubgroupSize
= 64;
1857 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1858 props
->requiredSubgroupSizeStages
= 0;
1860 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1861 /* Only GFX10+ supports wave32. */
1862 props
->minSubgroupSize
= 32;
1863 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1867 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1868 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1871 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1874 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1875 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1876 props
->lineSubPixelPrecisionBits
= 4;
1885 static void radv_get_physical_device_queue_family_properties(
1886 struct radv_physical_device
* pdevice
,
1888 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1890 int num_queue_families
= 1;
1892 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1893 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1894 num_queue_families
++;
1896 if (pQueueFamilyProperties
== NULL
) {
1897 *pCount
= num_queue_families
;
1906 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1907 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1908 VK_QUEUE_COMPUTE_BIT
|
1909 VK_QUEUE_TRANSFER_BIT
|
1910 VK_QUEUE_SPARSE_BINDING_BIT
,
1912 .timestampValidBits
= 64,
1913 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1918 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1919 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1920 if (*pCount
> idx
) {
1921 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1922 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1923 VK_QUEUE_TRANSFER_BIT
|
1924 VK_QUEUE_SPARSE_BINDING_BIT
,
1925 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1926 .timestampValidBits
= 64,
1927 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1935 void radv_GetPhysicalDeviceQueueFamilyProperties(
1936 VkPhysicalDevice physicalDevice
,
1938 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1940 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1941 if (!pQueueFamilyProperties
) {
1942 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1945 VkQueueFamilyProperties
*properties
[] = {
1946 pQueueFamilyProperties
+ 0,
1947 pQueueFamilyProperties
+ 1,
1948 pQueueFamilyProperties
+ 2,
1950 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1951 assert(*pCount
<= 3);
1954 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1955 VkPhysicalDevice physicalDevice
,
1957 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1959 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1960 if (!pQueueFamilyProperties
) {
1961 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1964 VkQueueFamilyProperties
*properties
[] = {
1965 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1966 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1967 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1969 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1970 assert(*pCount
<= 3);
1973 void radv_GetPhysicalDeviceMemoryProperties(
1974 VkPhysicalDevice physicalDevice
,
1975 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1977 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1979 *pMemoryProperties
= physical_device
->memory_properties
;
1983 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1984 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1986 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1987 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1988 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1989 uint64_t vram_size
= radv_get_vram_size(device
);
1990 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1991 uint64_t heap_budget
, heap_usage
;
1993 /* For all memory heaps, the computation of budget is as follow:
1994 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1996 * The Vulkan spec 1.1.97 says that the budget should include any
1997 * currently allocated device memory.
1999 * Note that the application heap usages are not really accurate (eg.
2000 * in presence of shared buffers).
2002 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2003 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2005 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2006 heap_usage
= device
->ws
->query_value(device
->ws
,
2007 RADEON_ALLOCATED_VRAM
);
2009 heap_budget
= vram_size
-
2010 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2013 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2014 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2015 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2016 heap_usage
= device
->ws
->query_value(device
->ws
,
2017 RADEON_ALLOCATED_VRAM_VIS
);
2019 heap_budget
= visible_vram_size
-
2020 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2023 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2024 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2025 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2026 heap_usage
= device
->ws
->query_value(device
->ws
,
2027 RADEON_ALLOCATED_GTT
);
2029 heap_budget
= gtt_size
-
2030 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2033 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2034 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2038 /* The heapBudget and heapUsage values must be zero for array elements
2039 * greater than or equal to
2040 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2042 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2043 memoryBudget
->heapBudget
[i
] = 0;
2044 memoryBudget
->heapUsage
[i
] = 0;
2048 void radv_GetPhysicalDeviceMemoryProperties2(
2049 VkPhysicalDevice physicalDevice
,
2050 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2052 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2053 &pMemoryProperties
->memoryProperties
);
2055 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2056 vk_find_struct(pMemoryProperties
->pNext
,
2057 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2059 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2062 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2064 VkExternalMemoryHandleTypeFlagBits handleType
,
2065 const void *pHostPointer
,
2066 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2072 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2073 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2074 uint32_t memoryTypeBits
= 0;
2075 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2076 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2077 memoryTypeBits
= (1 << i
);
2081 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2085 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2089 static enum radeon_ctx_priority
2090 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2092 /* Default to MEDIUM when a specific global priority isn't requested */
2094 return RADEON_CTX_PRIORITY_MEDIUM
;
2096 switch(pObj
->globalPriority
) {
2097 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2098 return RADEON_CTX_PRIORITY_REALTIME
;
2099 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2100 return RADEON_CTX_PRIORITY_HIGH
;
2101 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2102 return RADEON_CTX_PRIORITY_MEDIUM
;
2103 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2104 return RADEON_CTX_PRIORITY_LOW
;
2106 unreachable("Illegal global priority value");
2107 return RADEON_CTX_PRIORITY_INVALID
;
2112 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2113 uint32_t queue_family_index
, int idx
,
2114 VkDeviceQueueCreateFlags flags
,
2115 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2117 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2118 queue
->device
= device
;
2119 queue
->queue_family_index
= queue_family_index
;
2120 queue
->queue_idx
= idx
;
2121 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2122 queue
->flags
= flags
;
2124 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2126 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2128 list_inithead(&queue
->pending_submissions
);
2129 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2135 radv_queue_finish(struct radv_queue
*queue
)
2137 pthread_mutex_destroy(&queue
->pending_mutex
);
2140 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2142 if (queue
->initial_full_flush_preamble_cs
)
2143 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2144 if (queue
->initial_preamble_cs
)
2145 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2146 if (queue
->continue_preamble_cs
)
2147 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2148 if (queue
->descriptor_bo
)
2149 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2150 if (queue
->scratch_bo
)
2151 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2152 if (queue
->esgs_ring_bo
)
2153 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2154 if (queue
->gsvs_ring_bo
)
2155 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2156 if (queue
->tess_rings_bo
)
2157 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2159 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2160 if (queue
->gds_oa_bo
)
2161 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2162 if (queue
->compute_scratch_bo
)
2163 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2167 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2169 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2170 bo_list
->list
.count
= bo_list
->capacity
= 0;
2171 bo_list
->list
.bos
= NULL
;
2175 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2177 free(bo_list
->list
.bos
);
2178 pthread_mutex_destroy(&bo_list
->mutex
);
2181 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2182 struct radeon_winsys_bo
*bo
)
2184 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2189 if (unlikely(!device
->use_global_bo_list
))
2192 pthread_mutex_lock(&bo_list
->mutex
);
2193 if (bo_list
->list
.count
== bo_list
->capacity
) {
2194 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2195 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2198 pthread_mutex_unlock(&bo_list
->mutex
);
2199 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2202 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2203 bo_list
->capacity
= capacity
;
2206 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2207 pthread_mutex_unlock(&bo_list
->mutex
);
2211 static void radv_bo_list_remove(struct radv_device
*device
,
2212 struct radeon_winsys_bo
*bo
)
2214 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2219 if (unlikely(!device
->use_global_bo_list
))
2222 pthread_mutex_lock(&bo_list
->mutex
);
2223 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2224 if (bo_list
->list
.bos
[i
] == bo
) {
2225 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2226 --bo_list
->list
.count
;
2230 pthread_mutex_unlock(&bo_list
->mutex
);
2234 radv_device_init_gs_info(struct radv_device
*device
)
2236 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2237 device
->physical_device
->rad_info
.family
);
2240 static int radv_get_device_extension_index(const char *name
)
2242 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2243 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2250 radv_get_int_debug_option(const char *name
, int default_value
)
2257 result
= default_value
;
2261 result
= strtol(str
, &endptr
, 0);
2262 if (str
== endptr
) {
2263 /* No digits founs. */
2264 result
= default_value
;
2271 static int install_seccomp_filter() {
2273 struct sock_filter filter
[] = {
2274 /* Check arch is 64bit x86 */
2275 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2276 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2278 /* Futex is required for mutex locks */
2279 #if defined __NR__newselect
2280 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2281 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2282 #elif defined __NR_select
2283 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2284 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2286 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2287 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2290 /* Allow system exit calls for the forked process */
2291 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2292 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2294 /* Allow system read calls */
2295 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2296 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2298 /* Allow system write calls */
2299 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2300 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2302 /* Allow system brk calls (we need this for malloc) */
2303 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2304 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2306 /* Futex is required for mutex locks */
2307 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2308 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2310 /* Return error if we hit a system call not on the whitelist */
2311 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2313 /* Allow whitelisted system calls */
2314 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2317 struct sock_fprog prog
= {
2318 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2322 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2325 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2331 /* Helper function with timeout support for reading from the pipe between
2332 * processes used for secure compile.
2334 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2343 /* We can't rely on the value of tv after calling select() so
2344 * we must reset it on each iteration of the loop.
2349 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2355 ssize_t bytes_read
= read(fd
, buf
, size
);
2364 /* select timeout */
2370 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2374 d
= opendir("/proc/self/fd");
2377 int dir_fd
= dirfd(d
);
2379 while ((dir
= readdir(d
)) != NULL
) {
2380 if (dir
->d_name
[0] == '.')
2383 int fd
= atoi(dir
->d_name
);
2388 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2389 if (keep_fds
[i
] == fd
)
2401 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2402 int *fd_server
, int *fd_client
,
2403 unsigned process
, bool make_fifo
)
2405 bool result
= false;
2406 char *fifo_server_path
= NULL
;
2407 char *fifo_client_path
= NULL
;
2409 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2410 goto open_fifo_exit
;
2412 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2413 goto open_fifo_exit
;
2416 int file1
= mkfifo(fifo_server_path
, 0666);
2418 goto open_fifo_exit
;
2420 int file2
= mkfifo(fifo_client_path
, 0666);
2422 goto open_fifo_exit
;
2425 *fd_server
= open(fifo_server_path
, O_RDWR
);
2427 goto open_fifo_exit
;
2429 *fd_client
= open(fifo_client_path
, O_RDWR
);
2430 if(*fd_client
< 1) {
2432 goto open_fifo_exit
;
2438 free(fifo_server_path
);
2439 free(fifo_client_path
);
2444 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2445 int fd_idle_device_output
)
2447 int fd_secure_input
;
2448 int fd_secure_output
;
2449 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2454 enum radv_secure_compile_type sc_type
;
2456 const int needed_fds
[] = {
2459 fd_idle_device_output
,
2462 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2463 install_seccomp_filter() == -1) {
2464 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2466 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2467 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2468 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2471 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2473 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2474 goto secure_compile_exit
;
2477 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2479 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2480 struct radv_pipeline
*pipeline
;
2481 bool sc_read
= true;
2483 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2484 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2486 pipeline
->device
= device
;
2488 /* Read pipeline layout */
2489 struct radv_pipeline_layout layout
;
2490 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2491 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2493 goto secure_compile_exit
;
2495 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2496 uint32_t layout_size
;
2497 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2499 goto secure_compile_exit
;
2501 layout
.set
[set
].layout
= malloc(layout_size
);
2502 layout
.set
[set
].layout
->layout_size
= layout_size
;
2503 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2504 layout
.set
[set
].layout
->layout_size
, true);
2507 pipeline
->layout
= &layout
;
2509 /* Read pipeline key */
2510 struct radv_pipeline_key key
;
2511 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2513 /* Read pipeline create flags */
2514 VkPipelineCreateFlags flags
;
2515 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2517 /* Read stage and shader information */
2518 uint32_t num_stages
;
2519 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2520 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2522 goto secure_compile_exit
;
2524 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2527 gl_shader_stage stage
;
2528 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2530 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2532 /* Read entry point name */
2534 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2536 goto secure_compile_exit
;
2538 char *ep_name
= malloc(name_size
);
2539 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2540 pStage
->pName
= ep_name
;
2542 /* Read shader module */
2544 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2546 goto secure_compile_exit
;
2548 struct radv_shader_module
*module
= malloc(module_size
);
2549 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2550 pStage
->module
= radv_shader_module_to_handle(module
);
2552 /* Read specialization info */
2554 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2556 goto secure_compile_exit
;
2558 if (has_spec_info
) {
2559 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2560 pStage
->pSpecializationInfo
= specInfo
;
2562 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2564 goto secure_compile_exit
;
2566 void *si_data
= malloc(specInfo
->dataSize
);
2567 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2568 specInfo
->pData
= si_data
;
2570 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2572 goto secure_compile_exit
;
2574 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2575 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2576 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2578 goto secure_compile_exit
;
2581 specInfo
->pMapEntries
= mapEntries
;
2584 pStages
[stage
] = pStage
;
2587 /* Compile the shaders */
2588 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2589 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2591 /* free memory allocated above */
2592 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2593 free(layout
.set
[set
].layout
);
2595 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2599 free((void *) pStages
[i
]->pName
);
2600 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2601 if (pStages
[i
]->pSpecializationInfo
) {
2602 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2603 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2604 free((void *) pStages
[i
]->pSpecializationInfo
);
2606 free((void *) pStages
[i
]);
2609 vk_free(&device
->alloc
, pipeline
);
2611 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2612 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2614 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2615 goto secure_compile_exit
;
2619 secure_compile_exit
:
2620 close(fd_secure_input
);
2621 close(fd_secure_output
);
2622 close(fd_idle_device_output
);
2626 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2628 int fd_secure_input
[2];
2629 int fd_secure_output
[2];
2631 /* create pipe descriptors (used to communicate between processes) */
2632 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2633 return RADV_SC_TYPE_INIT_FAILURE
;
2637 if ((sc_pid
= fork()) == 0) {
2638 device
->sc_state
->secure_compile_thread_counter
= process
;
2639 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2642 return RADV_SC_TYPE_INIT_FAILURE
;
2644 /* Read the init result returned from the secure process */
2645 enum radv_secure_compile_type sc_type
;
2646 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2648 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2649 close(fd_secure_input
[0]);
2650 close(fd_secure_input
[1]);
2651 close(fd_secure_output
[1]);
2652 close(fd_secure_output
[0]);
2654 waitpid(sc_pid
, &status
, 0);
2656 return RADV_SC_TYPE_INIT_FAILURE
;
2658 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2659 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2661 close(fd_secure_input
[0]);
2662 close(fd_secure_input
[1]);
2663 close(fd_secure_output
[1]);
2664 close(fd_secure_output
[0]);
2667 waitpid(sc_pid
, &status
, 0);
2671 return RADV_SC_TYPE_INIT_SUCCESS
;
2674 /* Run a bare bones fork of a device that was forked right after its creation.
2675 * This device will have low overhead when it is forked again before each
2676 * pipeline compilation. This device sits idle and its only job is to fork
2679 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2680 int fd_secure_input
, int fd_secure_output
)
2682 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2683 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2684 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2686 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2689 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2691 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2692 sc_type
= fork_secure_compile_device(device
, process
);
2694 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2695 goto secure_compile_exit
;
2697 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2698 goto secure_compile_exit
;
2702 secure_compile_exit
:
2703 close(fd_secure_input
);
2704 close(fd_secure_output
);
2708 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2710 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2712 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2713 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2715 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2716 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2719 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2722 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2724 device
->sc_state
= vk_zalloc(&device
->alloc
,
2725 sizeof(struct radv_secure_compile_state
),
2726 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2728 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2730 pid_t upid
= getpid();
2731 time_t seconds
= time(NULL
);
2734 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2735 return VK_ERROR_INITIALIZATION_FAILED
;
2737 device
->sc_state
->uid
= uid
;
2739 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2740 int fd_secure_input
[MAX_SC_PROCS
][2];
2741 int fd_secure_output
[MAX_SC_PROCS
][2];
2743 /* create pipe descriptors (used to communicate between processes) */
2744 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2745 if (pipe(fd_secure_input
[i
]) == -1 ||
2746 pipe(fd_secure_output
[i
]) == -1) {
2747 return VK_ERROR_INITIALIZATION_FAILED
;
2751 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2752 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2753 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2755 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2756 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2757 device
->sc_state
->secure_compile_thread_counter
= process
;
2758 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2760 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2761 return VK_ERROR_INITIALIZATION_FAILED
;
2763 /* Read the init result returned from the secure process */
2764 enum radv_secure_compile_type sc_type
;
2765 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2768 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2769 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2770 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2771 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2774 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2775 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2778 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2779 close(fd_secure_input
[process
][0]);
2780 close(fd_secure_input
[process
][1]);
2781 close(fd_secure_output
[process
][1]);
2782 close(fd_secure_output
[process
][0]);
2784 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2786 /* Destroy any forks that were created sucessfully */
2787 for (unsigned i
= 0; i
< process
; i
++) {
2788 destroy_secure_compile_device(device
, i
);
2791 return VK_ERROR_INITIALIZATION_FAILED
;
2799 radv_create_pthread_cond(pthread_cond_t
*cond
)
2801 pthread_condattr_t condattr
;
2802 if (pthread_condattr_init(&condattr
)) {
2803 return VK_ERROR_INITIALIZATION_FAILED
;
2806 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2807 pthread_condattr_destroy(&condattr
);
2808 return VK_ERROR_INITIALIZATION_FAILED
;
2810 if (pthread_cond_init(cond
, &condattr
)) {
2811 pthread_condattr_destroy(&condattr
);
2812 return VK_ERROR_INITIALIZATION_FAILED
;
2814 pthread_condattr_destroy(&condattr
);
2818 VkResult
radv_CreateDevice(
2819 VkPhysicalDevice physicalDevice
,
2820 const VkDeviceCreateInfo
* pCreateInfo
,
2821 const VkAllocationCallbacks
* pAllocator
,
2824 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2826 struct radv_device
*device
;
2828 bool keep_shader_info
= false;
2830 /* Check enabled features */
2831 if (pCreateInfo
->pEnabledFeatures
) {
2832 VkPhysicalDeviceFeatures supported_features
;
2833 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2834 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2835 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2836 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2837 for (uint32_t i
= 0; i
< num_features
; i
++) {
2838 if (enabled_feature
[i
] && !supported_feature
[i
])
2839 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2843 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2845 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2847 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2849 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2850 device
->instance
= physical_device
->instance
;
2851 device
->physical_device
= physical_device
;
2853 device
->ws
= physical_device
->ws
;
2855 device
->alloc
= *pAllocator
;
2857 device
->alloc
= physical_device
->instance
->alloc
;
2859 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2860 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2861 int index
= radv_get_device_extension_index(ext_name
);
2862 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2863 vk_free(&device
->alloc
, device
);
2864 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2867 device
->enabled_extensions
.extensions
[index
] = true;
2870 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2872 /* With update after bind we can't attach bo's to the command buffer
2873 * from the descriptor set anymore, so we have to use a global BO list.
2875 device
->use_global_bo_list
=
2876 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2877 device
->enabled_extensions
.EXT_descriptor_indexing
||
2878 device
->enabled_extensions
.EXT_buffer_device_address
||
2879 device
->enabled_extensions
.KHR_buffer_device_address
;
2881 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2882 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2884 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2885 list_inithead(&device
->shader_slabs
);
2887 radv_bo_list_init(&device
->bo_list
);
2889 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2890 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2891 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2892 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2893 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2895 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2897 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2898 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2899 if (!device
->queues
[qfi
]) {
2900 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2904 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2906 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2908 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2909 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2910 qfi
, q
, queue_create
->flags
,
2912 if (result
!= VK_SUCCESS
)
2917 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2918 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2920 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2921 device
->dfsm_allowed
= device
->pbb_allowed
&&
2922 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2924 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2926 /* The maximum number of scratch waves. Scratch space isn't divided
2927 * evenly between CUs. The number is only a function of the number of CUs.
2928 * We can decrease the constant to decrease the scratch buffer size.
2930 * sctx->scratch_waves must be >= the maximum possible size of
2931 * 1 threadgroup, so that the hw doesn't hang from being unable
2934 * The recommended value is 4 per CU at most. Higher numbers don't
2935 * bring much benefit, but they still occupy chip resources (think
2936 * async compute). I've seen ~2% performance difference between 4 and 32.
2938 uint32_t max_threads_per_block
= 2048;
2939 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2940 max_threads_per_block
/ 64);
2942 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2944 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2945 /* If the KMD allows it (there is a KMD hw register for it),
2946 * allow launching waves out-of-order.
2948 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2951 radv_device_init_gs_info(device
);
2953 device
->tess_offchip_block_dw_size
=
2954 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2956 if (getenv("RADV_TRACE_FILE")) {
2957 const char *filename
= getenv("RADV_TRACE_FILE");
2959 keep_shader_info
= true;
2961 if (!radv_init_trace(device
))
2964 fprintf(stderr
, "*****************************************************************************\n");
2965 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2966 fprintf(stderr
, "*****************************************************************************\n");
2968 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2969 radv_dump_enabled_options(device
, stderr
);
2972 /* Temporarily disable secure compile while we create meta shaders, etc */
2973 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2975 device
->instance
->num_sc_threads
= 0;
2977 device
->keep_shader_info
= keep_shader_info
;
2978 result
= radv_device_init_meta(device
);
2979 if (result
!= VK_SUCCESS
)
2982 radv_device_init_msaa(device
);
2984 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2985 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2987 case RADV_QUEUE_GENERAL
:
2988 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2989 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2990 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2992 case RADV_QUEUE_COMPUTE
:
2993 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2994 radeon_emit(device
->empty_cs
[family
], 0);
2997 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3000 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3001 cik_create_gfx_config(device
);
3003 VkPipelineCacheCreateInfo ci
;
3004 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3007 ci
.pInitialData
= NULL
;
3008 ci
.initialDataSize
= 0;
3010 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3012 if (result
!= VK_SUCCESS
)
3015 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3017 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3018 if (result
!= VK_SUCCESS
)
3019 goto fail_mem_cache
;
3021 device
->force_aniso
=
3022 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3023 if (device
->force_aniso
>= 0) {
3024 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3025 1 << util_logbase2(device
->force_aniso
));
3028 /* Fork device for secure compile as required */
3029 device
->instance
->num_sc_threads
= sc_threads
;
3030 if (radv_device_use_secure_compile(device
->instance
)) {
3032 result
= fork_secure_compile_idle_device(device
);
3033 if (result
!= VK_SUCCESS
)
3037 *pDevice
= radv_device_to_handle(device
);
3041 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3043 radv_device_finish_meta(device
);
3045 radv_bo_list_finish(&device
->bo_list
);
3047 if (device
->trace_bo
)
3048 device
->ws
->buffer_destroy(device
->trace_bo
);
3050 if (device
->gfx_init
)
3051 device
->ws
->buffer_destroy(device
->gfx_init
);
3053 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3054 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3055 radv_queue_finish(&device
->queues
[i
][q
]);
3056 if (device
->queue_count
[i
])
3057 vk_free(&device
->alloc
, device
->queues
[i
]);
3060 vk_free(&device
->alloc
, device
);
3064 void radv_DestroyDevice(
3066 const VkAllocationCallbacks
* pAllocator
)
3068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3073 if (device
->trace_bo
)
3074 device
->ws
->buffer_destroy(device
->trace_bo
);
3076 if (device
->gfx_init
)
3077 device
->ws
->buffer_destroy(device
->gfx_init
);
3079 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3080 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3081 radv_queue_finish(&device
->queues
[i
][q
]);
3082 if (device
->queue_count
[i
])
3083 vk_free(&device
->alloc
, device
->queues
[i
]);
3084 if (device
->empty_cs
[i
])
3085 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3087 radv_device_finish_meta(device
);
3089 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3090 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3092 radv_destroy_shader_slabs(device
);
3094 pthread_cond_destroy(&device
->timeline_cond
);
3095 radv_bo_list_finish(&device
->bo_list
);
3096 if (radv_device_use_secure_compile(device
->instance
)) {
3097 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3098 destroy_secure_compile_device(device
, i
);
3102 if (device
->sc_state
) {
3103 free(device
->sc_state
->uid
);
3104 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3106 vk_free(&device
->alloc
, device
->sc_state
);
3107 vk_free(&device
->alloc
, device
);
3110 VkResult
radv_EnumerateInstanceLayerProperties(
3111 uint32_t* pPropertyCount
,
3112 VkLayerProperties
* pProperties
)
3114 if (pProperties
== NULL
) {
3115 *pPropertyCount
= 0;
3119 /* None supported at this time */
3120 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3123 VkResult
radv_EnumerateDeviceLayerProperties(
3124 VkPhysicalDevice physicalDevice
,
3125 uint32_t* pPropertyCount
,
3126 VkLayerProperties
* pProperties
)
3128 if (pProperties
== NULL
) {
3129 *pPropertyCount
= 0;
3133 /* None supported at this time */
3134 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3137 void radv_GetDeviceQueue2(
3139 const VkDeviceQueueInfo2
* pQueueInfo
,
3142 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3143 struct radv_queue
*queue
;
3145 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3146 if (pQueueInfo
->flags
!= queue
->flags
) {
3147 /* From the Vulkan 1.1.70 spec:
3149 * "The queue returned by vkGetDeviceQueue2 must have the same
3150 * flags value from this structure as that used at device
3151 * creation time in a VkDeviceQueueCreateInfo instance. If no
3152 * matching flags were specified at device creation time then
3153 * pQueue will return VK_NULL_HANDLE."
3155 *pQueue
= VK_NULL_HANDLE
;
3159 *pQueue
= radv_queue_to_handle(queue
);
3162 void radv_GetDeviceQueue(
3164 uint32_t queueFamilyIndex
,
3165 uint32_t queueIndex
,
3168 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3169 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3170 .queueFamilyIndex
= queueFamilyIndex
,
3171 .queueIndex
= queueIndex
3174 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3178 fill_geom_tess_rings(struct radv_queue
*queue
,
3180 bool add_sample_positions
,
3181 uint32_t esgs_ring_size
,
3182 struct radeon_winsys_bo
*esgs_ring_bo
,
3183 uint32_t gsvs_ring_size
,
3184 struct radeon_winsys_bo
*gsvs_ring_bo
,
3185 uint32_t tess_factor_ring_size
,
3186 uint32_t tess_offchip_ring_offset
,
3187 uint32_t tess_offchip_ring_size
,
3188 struct radeon_winsys_bo
*tess_rings_bo
)
3190 uint32_t *desc
= &map
[4];
3193 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3195 /* stride 0, num records - size, add tid, swizzle, elsize4,
3198 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3199 S_008F04_SWIZZLE_ENABLE(true);
3200 desc
[2] = esgs_ring_size
;
3201 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3202 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3203 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3204 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3205 S_008F0C_INDEX_STRIDE(3) |
3206 S_008F0C_ADD_TID_ENABLE(1);
3208 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3209 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3210 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3211 S_008F0C_RESOURCE_LEVEL(1);
3213 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3214 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3215 S_008F0C_ELEMENT_SIZE(1);
3218 /* GS entry for ES->GS ring */
3219 /* stride 0, num records - size, elsize0,
3222 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3223 desc
[6] = esgs_ring_size
;
3224 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3225 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3226 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3227 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3229 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3230 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3231 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3232 S_008F0C_RESOURCE_LEVEL(1);
3234 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3235 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3242 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3244 /* VS entry for GS->VS ring */
3245 /* stride 0, num records - size, elsize0,
3248 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3249 desc
[2] = gsvs_ring_size
;
3250 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3255 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3256 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3257 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3258 S_008F0C_RESOURCE_LEVEL(1);
3260 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3261 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3264 /* stride gsvs_itemsize, num records 64
3265 elsize 4, index stride 16 */
3266 /* shader will patch stride and desc[2] */
3268 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3269 S_008F04_SWIZZLE_ENABLE(1);
3271 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3275 S_008F0C_INDEX_STRIDE(1) |
3276 S_008F0C_ADD_TID_ENABLE(true);
3278 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3279 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3280 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3281 S_008F0C_RESOURCE_LEVEL(1);
3283 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3284 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3285 S_008F0C_ELEMENT_SIZE(1);
3292 if (tess_rings_bo
) {
3293 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3294 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3297 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3298 desc
[2] = tess_factor_ring_size
;
3299 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3300 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3301 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3302 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3304 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3305 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3306 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3307 S_008F0C_RESOURCE_LEVEL(1);
3309 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3310 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3313 desc
[4] = tess_offchip_va
;
3314 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3315 desc
[6] = tess_offchip_ring_size
;
3316 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3317 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3318 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3319 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3321 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3322 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3323 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3324 S_008F0C_RESOURCE_LEVEL(1);
3326 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3327 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3333 if (add_sample_positions
) {
3334 /* add sample positions after all rings */
3335 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3337 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3339 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3341 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3346 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3348 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3349 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3350 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3351 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3352 unsigned max_offchip_buffers
;
3353 unsigned offchip_granularity
;
3354 unsigned hs_offchip_param
;
3358 * This must be one less than the maximum number due to a hw limitation.
3359 * Various hardware bugs need thGFX7
3362 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3363 * Gfx7 should limit max_offchip_buffers to 508
3364 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3366 * Follow AMDVLK here.
3368 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3369 max_offchip_buffers_per_se
= 256;
3370 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3371 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3372 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3373 --max_offchip_buffers_per_se
;
3375 max_offchip_buffers
= max_offchip_buffers_per_se
*
3376 device
->physical_device
->rad_info
.max_se
;
3378 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3379 * around by setting 4K granularity.
3381 if (device
->tess_offchip_block_dw_size
== 4096) {
3382 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3383 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3385 assert(device
->tess_offchip_block_dw_size
== 8192);
3386 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3389 switch (device
->physical_device
->rad_info
.chip_class
) {
3391 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3396 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3404 *max_offchip_buffers_p
= max_offchip_buffers
;
3405 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3406 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3407 --max_offchip_buffers
;
3409 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3410 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3413 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3415 return hs_offchip_param
;
3419 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3420 struct radeon_winsys_bo
*esgs_ring_bo
,
3421 uint32_t esgs_ring_size
,
3422 struct radeon_winsys_bo
*gsvs_ring_bo
,
3423 uint32_t gsvs_ring_size
)
3425 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3429 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3432 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3434 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3435 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3436 radeon_emit(cs
, esgs_ring_size
>> 8);
3437 radeon_emit(cs
, gsvs_ring_size
>> 8);
3439 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3440 radeon_emit(cs
, esgs_ring_size
>> 8);
3441 radeon_emit(cs
, gsvs_ring_size
>> 8);
3446 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3447 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3448 struct radeon_winsys_bo
*tess_rings_bo
)
3455 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3457 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3459 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3460 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3461 S_030938_SIZE(tf_ring_size
/ 4));
3462 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3465 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3466 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3467 S_030984_BASE_HI(tf_va
>> 40));
3468 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3469 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3470 S_030944_BASE_HI(tf_va
>> 40));
3472 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3475 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3476 S_008988_SIZE(tf_ring_size
/ 4));
3477 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3479 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3485 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3486 uint32_t size_per_wave
, uint32_t waves
,
3487 struct radeon_winsys_bo
*scratch_bo
)
3489 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3495 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3497 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3498 S_0286E8_WAVES(waves
) |
3499 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3503 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3504 uint32_t size_per_wave
, uint32_t waves
,
3505 struct radeon_winsys_bo
*compute_scratch_bo
)
3507 uint64_t scratch_va
;
3509 if (!compute_scratch_bo
)
3512 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3514 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3516 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3517 radeon_emit(cs
, scratch_va
);
3518 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3519 S_008F04_SWIZZLE_ENABLE(1));
3521 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3522 S_00B860_WAVES(waves
) |
3523 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3527 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3528 struct radeon_cmdbuf
*cs
,
3529 struct radeon_winsys_bo
*descriptor_bo
)
3536 va
= radv_buffer_get_va(descriptor_bo
);
3538 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3540 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3541 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3542 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3543 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3544 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3546 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3547 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3550 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3551 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3552 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3553 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3554 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3556 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3557 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3561 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3562 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3563 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3564 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3565 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3566 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3568 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3569 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3576 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3578 struct radv_device
*device
= queue
->device
;
3580 if (device
->gfx_init
) {
3581 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3583 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3584 radeon_emit(cs
, va
);
3585 radeon_emit(cs
, va
>> 32);
3586 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3588 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3590 struct radv_physical_device
*physical_device
= device
->physical_device
;
3591 si_emit_graphics(physical_device
, cs
);
3596 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3598 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3599 si_emit_compute(physical_device
, cs
);
3603 radv_get_preamble_cs(struct radv_queue
*queue
,
3604 uint32_t scratch_size_per_wave
,
3605 uint32_t scratch_waves
,
3606 uint32_t compute_scratch_size_per_wave
,
3607 uint32_t compute_scratch_waves
,
3608 uint32_t esgs_ring_size
,
3609 uint32_t gsvs_ring_size
,
3610 bool needs_tess_rings
,
3613 bool needs_sample_positions
,
3614 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3615 struct radeon_cmdbuf
**initial_preamble_cs
,
3616 struct radeon_cmdbuf
**continue_preamble_cs
)
3618 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3619 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3620 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3621 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3622 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3623 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3624 struct radeon_winsys_bo
*gds_bo
= NULL
;
3625 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3626 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3627 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3628 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3629 unsigned max_offchip_buffers
;
3630 unsigned hs_offchip_param
= 0;
3631 unsigned tess_offchip_ring_offset
;
3632 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3633 if (!queue
->has_tess_rings
) {
3634 if (needs_tess_rings
)
3635 add_tess_rings
= true;
3637 if (!queue
->has_gds
) {
3641 if (!queue
->has_gds_oa
) {
3645 if (!queue
->has_sample_positions
) {
3646 if (needs_sample_positions
)
3647 add_sample_positions
= true;
3649 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3650 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3651 &max_offchip_buffers
);
3652 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3653 tess_offchip_ring_size
= max_offchip_buffers
*
3654 queue
->device
->tess_offchip_block_dw_size
* 4;
3656 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3657 if (scratch_size_per_wave
)
3658 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3662 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3663 if (compute_scratch_size_per_wave
)
3664 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3666 compute_scratch_waves
= 0;
3668 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3669 scratch_waves
<= queue
->scratch_waves
&&
3670 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3671 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3672 esgs_ring_size
<= queue
->esgs_ring_size
&&
3673 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3674 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3675 queue
->initial_preamble_cs
) {
3676 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3677 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3678 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3679 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3680 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3681 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3682 *continue_preamble_cs
= NULL
;
3686 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3687 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3688 if (scratch_size
> queue_scratch_size
) {
3689 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3694 RADV_BO_PRIORITY_SCRATCH
);
3698 scratch_bo
= queue
->scratch_bo
;
3700 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3701 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3702 if (compute_scratch_size
> compute_queue_scratch_size
) {
3703 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3704 compute_scratch_size
,
3708 RADV_BO_PRIORITY_SCRATCH
);
3709 if (!compute_scratch_bo
)
3713 compute_scratch_bo
= queue
->compute_scratch_bo
;
3715 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3716 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3721 RADV_BO_PRIORITY_SCRATCH
);
3725 esgs_ring_bo
= queue
->esgs_ring_bo
;
3726 esgs_ring_size
= queue
->esgs_ring_size
;
3729 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3730 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3735 RADV_BO_PRIORITY_SCRATCH
);
3739 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3740 gsvs_ring_size
= queue
->gsvs_ring_size
;
3743 if (add_tess_rings
) {
3744 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3745 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3749 RADV_BO_PRIORITY_SCRATCH
);
3753 tess_rings_bo
= queue
->tess_rings_bo
;
3757 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3759 /* 4 streamout GDS counters.
3760 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3762 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3766 RADV_BO_PRIORITY_SCRATCH
);
3770 gds_bo
= queue
->gds_bo
;
3774 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3776 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3780 RADV_BO_PRIORITY_SCRATCH
);
3784 gds_oa_bo
= queue
->gds_oa_bo
;
3787 if (scratch_bo
!= queue
->scratch_bo
||
3788 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3789 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3790 tess_rings_bo
!= queue
->tess_rings_bo
||
3791 add_sample_positions
) {
3793 if (gsvs_ring_bo
|| esgs_ring_bo
||
3794 tess_rings_bo
|| add_sample_positions
) {
3795 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3796 if (add_sample_positions
)
3797 size
+= 128; /* 64+32+16+8 = 120 bytes */
3799 else if (scratch_bo
)
3800 size
= 8; /* 2 dword */
3802 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3806 RADEON_FLAG_CPU_ACCESS
|
3807 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3808 RADEON_FLAG_READ_ONLY
,
3809 RADV_BO_PRIORITY_DESCRIPTOR
);
3813 descriptor_bo
= queue
->descriptor_bo
;
3815 if (descriptor_bo
!= queue
->descriptor_bo
) {
3816 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3819 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3820 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3821 S_008F04_SWIZZLE_ENABLE(1);
3822 map
[0] = scratch_va
;
3826 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3827 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3828 esgs_ring_size
, esgs_ring_bo
,
3829 gsvs_ring_size
, gsvs_ring_bo
,
3830 tess_factor_ring_size
,
3831 tess_offchip_ring_offset
,
3832 tess_offchip_ring_size
,
3835 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3838 for(int i
= 0; i
< 3; ++i
) {
3839 struct radeon_cmdbuf
*cs
= NULL
;
3840 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3841 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3848 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3850 /* Emit initial configuration. */
3851 switch (queue
->queue_family_index
) {
3852 case RADV_QUEUE_GENERAL
:
3853 radv_init_graphics_state(cs
, queue
);
3855 case RADV_QUEUE_COMPUTE
:
3856 radv_init_compute_state(cs
, queue
);
3858 case RADV_QUEUE_TRANSFER
:
3862 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3863 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3864 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3866 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3867 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3870 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3871 gsvs_ring_bo
, gsvs_ring_size
);
3872 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3873 tess_factor_ring_size
, tess_rings_bo
);
3874 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3875 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3876 compute_scratch_waves
, compute_scratch_bo
);
3877 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3878 scratch_waves
, scratch_bo
);
3881 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3883 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3885 if (queue
->device
->trace_bo
)
3886 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3889 si_cs_emit_cache_flush(cs
,
3890 queue
->device
->physical_device
->rad_info
.chip_class
,
3892 queue
->queue_family_index
== RING_COMPUTE
&&
3893 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3894 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3895 RADV_CMD_FLAG_INV_ICACHE
|
3896 RADV_CMD_FLAG_INV_SCACHE
|
3897 RADV_CMD_FLAG_INV_VCACHE
|
3898 RADV_CMD_FLAG_INV_L2
|
3899 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3900 } else if (i
== 1) {
3901 si_cs_emit_cache_flush(cs
,
3902 queue
->device
->physical_device
->rad_info
.chip_class
,
3904 queue
->queue_family_index
== RING_COMPUTE
&&
3905 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3906 RADV_CMD_FLAG_INV_ICACHE
|
3907 RADV_CMD_FLAG_INV_SCACHE
|
3908 RADV_CMD_FLAG_INV_VCACHE
|
3909 RADV_CMD_FLAG_INV_L2
|
3910 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3913 if (!queue
->device
->ws
->cs_finalize(cs
))
3917 if (queue
->initial_full_flush_preamble_cs
)
3918 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3920 if (queue
->initial_preamble_cs
)
3921 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3923 if (queue
->continue_preamble_cs
)
3924 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3926 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3927 queue
->initial_preamble_cs
= dest_cs
[1];
3928 queue
->continue_preamble_cs
= dest_cs
[2];
3930 if (scratch_bo
!= queue
->scratch_bo
) {
3931 if (queue
->scratch_bo
)
3932 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3933 queue
->scratch_bo
= scratch_bo
;
3935 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3936 queue
->scratch_waves
= scratch_waves
;
3938 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3939 if (queue
->compute_scratch_bo
)
3940 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3941 queue
->compute_scratch_bo
= compute_scratch_bo
;
3943 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3944 queue
->compute_scratch_waves
= compute_scratch_waves
;
3946 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3947 if (queue
->esgs_ring_bo
)
3948 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3949 queue
->esgs_ring_bo
= esgs_ring_bo
;
3950 queue
->esgs_ring_size
= esgs_ring_size
;
3953 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3954 if (queue
->gsvs_ring_bo
)
3955 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3956 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3957 queue
->gsvs_ring_size
= gsvs_ring_size
;
3960 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3961 queue
->tess_rings_bo
= tess_rings_bo
;
3962 queue
->has_tess_rings
= true;
3965 if (gds_bo
!= queue
->gds_bo
) {
3966 queue
->gds_bo
= gds_bo
;
3967 queue
->has_gds
= true;
3970 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3971 queue
->gds_oa_bo
= gds_oa_bo
;
3972 queue
->has_gds_oa
= true;
3975 if (descriptor_bo
!= queue
->descriptor_bo
) {
3976 if (queue
->descriptor_bo
)
3977 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3979 queue
->descriptor_bo
= descriptor_bo
;
3982 if (add_sample_positions
)
3983 queue
->has_sample_positions
= true;
3985 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3986 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3987 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3988 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3989 *continue_preamble_cs
= NULL
;
3992 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3994 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3995 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3996 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3997 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3998 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3999 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4000 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4001 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4002 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4003 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4004 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4005 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4006 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4007 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4008 queue
->device
->ws
->buffer_destroy(gds_bo
);
4009 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4010 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4012 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4015 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4016 struct radv_winsys_sem_counts
*counts
,
4018 struct radv_semaphore_part
**sems
,
4019 const uint64_t *timeline_values
,
4023 int syncobj_idx
= 0, sem_idx
= 0;
4025 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4028 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4029 switch(sems
[i
]->kind
) {
4030 case RADV_SEMAPHORE_SYNCOBJ
:
4031 counts
->syncobj_count
++;
4033 case RADV_SEMAPHORE_WINSYS
:
4034 counts
->sem_count
++;
4036 case RADV_SEMAPHORE_NONE
:
4038 case RADV_SEMAPHORE_TIMELINE
:
4039 counts
->syncobj_count
++;
4044 if (_fence
!= VK_NULL_HANDLE
) {
4045 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4046 if (fence
->temp_syncobj
|| fence
->syncobj
)
4047 counts
->syncobj_count
++;
4050 if (counts
->syncobj_count
) {
4051 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4052 if (!counts
->syncobj
)
4053 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4056 if (counts
->sem_count
) {
4057 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4059 free(counts
->syncobj
);
4060 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4064 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4065 switch(sems
[i
]->kind
) {
4066 case RADV_SEMAPHORE_NONE
:
4067 unreachable("Empty semaphore");
4069 case RADV_SEMAPHORE_SYNCOBJ
:
4070 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4072 case RADV_SEMAPHORE_WINSYS
:
4073 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4075 case RADV_SEMAPHORE_TIMELINE
: {
4076 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4077 struct radv_timeline_point
*point
= NULL
;
4079 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4081 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4084 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4087 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4089 /* Explicitly remove the semaphore so we might not find
4090 * a point later post-submit. */
4098 if (_fence
!= VK_NULL_HANDLE
) {
4099 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4100 if (fence
->temp_syncobj
)
4101 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4102 else if (fence
->syncobj
)
4103 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4106 assert(syncobj_idx
<= counts
->syncobj_count
);
4107 counts
->syncobj_count
= syncobj_idx
;
4113 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4115 free(sem_info
->wait
.syncobj
);
4116 free(sem_info
->wait
.sem
);
4117 free(sem_info
->signal
.syncobj
);
4118 free(sem_info
->signal
.sem
);
4122 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4124 struct radv_semaphore_part
*sems
)
4126 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4127 radv_destroy_semaphore_part(device
, sems
+ i
);
4132 radv_alloc_sem_info(struct radv_device
*device
,
4133 struct radv_winsys_sem_info
*sem_info
,
4135 struct radv_semaphore_part
**wait_sems
,
4136 const uint64_t *wait_values
,
4137 int num_signal_sems
,
4138 struct radv_semaphore_part
**signal_sems
,
4139 const uint64_t *signal_values
,
4143 memset(sem_info
, 0, sizeof(*sem_info
));
4145 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4148 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4150 radv_free_sem_info(sem_info
);
4152 /* caller can override these */
4153 sem_info
->cs_emit_wait
= true;
4154 sem_info
->cs_emit_signal
= true;
4159 radv_finalize_timelines(struct radv_device
*device
,
4160 uint32_t num_wait_sems
,
4161 struct radv_semaphore_part
**wait_sems
,
4162 const uint64_t *wait_values
,
4163 uint32_t num_signal_sems
,
4164 struct radv_semaphore_part
**signal_sems
,
4165 const uint64_t *signal_values
,
4166 struct list_head
*processing_list
)
4168 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4169 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4170 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4171 struct radv_timeline_point
*point
=
4172 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4173 point
->wait_count
-= 2;
4174 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4177 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4178 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4179 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4180 struct radv_timeline_point
*point
=
4181 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4182 signal_sems
[i
]->timeline
.highest_submitted
=
4183 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4184 point
->wait_count
-= 2;
4185 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4186 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4192 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4193 const VkSparseBufferMemoryBindInfo
*bind
)
4195 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4197 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4198 struct radv_device_memory
*mem
= NULL
;
4200 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4201 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4203 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4204 bind
->pBinds
[i
].resourceOffset
,
4205 bind
->pBinds
[i
].size
,
4206 mem
? mem
->bo
: NULL
,
4207 bind
->pBinds
[i
].memoryOffset
);
4212 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4213 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4215 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4217 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4218 struct radv_device_memory
*mem
= NULL
;
4220 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4221 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4223 device
->ws
->buffer_virtual_bind(image
->bo
,
4224 bind
->pBinds
[i
].resourceOffset
,
4225 bind
->pBinds
[i
].size
,
4226 mem
? mem
->bo
: NULL
,
4227 bind
->pBinds
[i
].memoryOffset
);
4232 radv_get_preambles(struct radv_queue
*queue
,
4233 const VkCommandBuffer
*cmd_buffers
,
4234 uint32_t cmd_buffer_count
,
4235 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4236 struct radeon_cmdbuf
**initial_preamble_cs
,
4237 struct radeon_cmdbuf
**continue_preamble_cs
)
4239 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4240 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4241 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4242 bool tess_rings_needed
= false;
4243 bool gds_needed
= false;
4244 bool gds_oa_needed
= false;
4245 bool sample_positions_needed
= false;
4247 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4248 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4251 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4252 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4253 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4254 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4255 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4256 cmd_buffer
->compute_scratch_waves_wanted
);
4257 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4258 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4259 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4260 gds_needed
|= cmd_buffer
->gds_needed
;
4261 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4262 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4265 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4266 compute_scratch_size_per_wave
, compute_waves_wanted
,
4267 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4268 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4269 initial_full_flush_preamble_cs
,
4270 initial_preamble_cs
, continue_preamble_cs
);
4273 struct radv_deferred_queue_submission
{
4274 struct radv_queue
*queue
;
4275 VkCommandBuffer
*cmd_buffers
;
4276 uint32_t cmd_buffer_count
;
4278 /* Sparse bindings that happen on a queue. */
4279 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4280 uint32_t buffer_bind_count
;
4281 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4282 uint32_t image_opaque_bind_count
;
4285 VkShaderStageFlags wait_dst_stage_mask
;
4286 struct radv_semaphore_part
**wait_semaphores
;
4287 uint32_t wait_semaphore_count
;
4288 struct radv_semaphore_part
**signal_semaphores
;
4289 uint32_t signal_semaphore_count
;
4292 uint64_t *wait_values
;
4293 uint64_t *signal_values
;
4295 struct radv_semaphore_part
*temporary_semaphore_parts
;
4296 uint32_t temporary_semaphore_part_count
;
4298 struct list_head queue_pending_list
;
4299 uint32_t submission_wait_count
;
4300 struct radv_timeline_waiter
*wait_nodes
;
4302 struct list_head processing_list
;
4305 struct radv_queue_submission
{
4306 const VkCommandBuffer
*cmd_buffers
;
4307 uint32_t cmd_buffer_count
;
4309 /* Sparse bindings that happen on a queue. */
4310 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4311 uint32_t buffer_bind_count
;
4312 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4313 uint32_t image_opaque_bind_count
;
4316 VkPipelineStageFlags wait_dst_stage_mask
;
4317 const VkSemaphore
*wait_semaphores
;
4318 uint32_t wait_semaphore_count
;
4319 const VkSemaphore
*signal_semaphores
;
4320 uint32_t signal_semaphore_count
;
4323 const uint64_t *wait_values
;
4324 uint32_t wait_value_count
;
4325 const uint64_t *signal_values
;
4326 uint32_t signal_value_count
;
4330 radv_create_deferred_submission(struct radv_queue
*queue
,
4331 const struct radv_queue_submission
*submission
,
4332 struct radv_deferred_queue_submission
**out
)
4334 struct radv_deferred_queue_submission
*deferred
= NULL
;
4335 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4337 uint32_t temporary_count
= 0;
4338 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4339 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4340 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4344 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4345 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4346 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4347 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4348 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4349 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4350 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4351 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4352 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4354 deferred
= calloc(1, size
);
4356 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4358 deferred
->queue
= queue
;
4360 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4361 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4362 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4363 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4365 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4366 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4367 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4368 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4370 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4371 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4372 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4373 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4375 deferred
->flush_caches
= submission
->flush_caches
;
4376 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4378 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4379 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4381 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4382 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4384 deferred
->fence
= submission
->fence
;
4386 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4387 deferred
->temporary_semaphore_part_count
= temporary_count
;
4389 uint32_t temporary_idx
= 0;
4390 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4391 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4392 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4393 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4394 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4395 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4398 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4401 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4402 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4403 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4404 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4406 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4410 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4411 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4412 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4413 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4415 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4416 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4417 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4418 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4425 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4426 struct list_head
*processing_list
)
4428 uint32_t wait_cnt
= 0;
4429 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4430 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4431 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4432 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4433 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4435 waiter
->value
= submission
->wait_values
[i
];
4436 waiter
->submission
= submission
;
4437 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4440 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4444 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4446 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4447 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4449 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4451 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4452 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4454 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4455 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4456 list_addtail(&submission
->processing_list
, processing_list
);
4461 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4462 struct list_head
*processing_list
)
4464 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4465 list_del(&submission
->queue_pending_list
);
4467 /* trigger the next submission in the queue. */
4468 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4469 struct radv_deferred_queue_submission
*next_submission
=
4470 list_first_entry(&submission
->queue
->pending_submissions
,
4471 struct radv_deferred_queue_submission
,
4472 queue_pending_list
);
4473 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4474 list_addtail(&next_submission
->processing_list
, processing_list
);
4477 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4479 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4483 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4484 struct list_head
*processing_list
)
4486 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4487 struct radv_queue
*queue
= submission
->queue
;
4488 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4489 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4490 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4491 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4492 bool can_patch
= true;
4494 struct radv_winsys_sem_info sem_info
;
4497 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4498 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4499 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4501 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4502 submission
->cmd_buffer_count
,
4503 &initial_preamble_cs
,
4504 &initial_flush_preamble_cs
,
4505 &continue_preamble_cs
);
4506 if (result
!= VK_SUCCESS
)
4509 result
= radv_alloc_sem_info(queue
->device
,
4511 submission
->wait_semaphore_count
,
4512 submission
->wait_semaphores
,
4513 submission
->wait_values
,
4514 submission
->signal_semaphore_count
,
4515 submission
->signal_semaphores
,
4516 submission
->signal_values
,
4518 if (result
!= VK_SUCCESS
)
4521 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4522 radv_sparse_buffer_bind_memory(queue
->device
,
4523 submission
->buffer_binds
+ i
);
4526 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4527 radv_sparse_image_opaque_bind_memory(queue
->device
,
4528 submission
->image_opaque_binds
+ i
);
4531 if (!submission
->cmd_buffer_count
) {
4532 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4533 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4538 radv_loge("failed to submit CS\n");
4544 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4545 (submission
->cmd_buffer_count
));
4547 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4548 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4549 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4551 cs_array
[j
] = cmd_buffer
->cs
;
4552 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4555 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4558 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4559 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4560 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4562 advance
= MIN2(max_cs_submission
,
4563 submission
->cmd_buffer_count
- j
);
4565 if (queue
->device
->trace_bo
)
4566 *queue
->device
->trace_id_ptr
= 0;
4568 sem_info
.cs_emit_wait
= j
== 0;
4569 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4571 if (unlikely(queue
->device
->use_global_bo_list
)) {
4572 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4573 bo_list
= &queue
->device
->bo_list
.list
;
4576 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4577 advance
, initial_preamble
, continue_preamble_cs
,
4579 can_patch
, base_fence
);
4581 if (unlikely(queue
->device
->use_global_bo_list
))
4582 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4585 radv_loge("failed to submit CS\n");
4588 if (queue
->device
->trace_bo
) {
4589 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4597 radv_free_temp_syncobjs(queue
->device
,
4598 submission
->temporary_semaphore_part_count
,
4599 submission
->temporary_semaphore_parts
);
4600 radv_finalize_timelines(queue
->device
,
4601 submission
->wait_semaphore_count
,
4602 submission
->wait_semaphores
,
4603 submission
->wait_values
,
4604 submission
->signal_semaphore_count
,
4605 submission
->signal_semaphores
,
4606 submission
->signal_values
,
4608 /* Has to happen after timeline finalization to make sure the
4609 * condition variable is only triggered when timelines and queue have
4611 radv_queue_submission_update_queue(submission
, processing_list
);
4612 radv_free_sem_info(&sem_info
);
4617 radv_free_temp_syncobjs(queue
->device
,
4618 submission
->temporary_semaphore_part_count
,
4619 submission
->temporary_semaphore_parts
);
4621 return VK_ERROR_DEVICE_LOST
;
4625 radv_process_submissions(struct list_head
*processing_list
)
4627 while(!list_is_empty(processing_list
)) {
4628 struct radv_deferred_queue_submission
*submission
=
4629 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4630 list_del(&submission
->processing_list
);
4632 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4633 if (result
!= VK_SUCCESS
)
4639 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4640 const struct radv_queue_submission
*submission
)
4642 struct radv_deferred_queue_submission
*deferred
= NULL
;
4644 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4645 if (result
!= VK_SUCCESS
)
4648 struct list_head processing_list
;
4649 list_inithead(&processing_list
);
4651 radv_queue_enqueue_submission(deferred
, &processing_list
);
4652 return radv_process_submissions(&processing_list
);
4656 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4658 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4659 struct radv_winsys_sem_info sem_info
;
4663 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4665 if (result
!= VK_SUCCESS
)
4668 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1, NULL
,
4669 NULL
, &sem_info
, NULL
, false, NULL
);
4670 radv_free_sem_info(&sem_info
);
4674 /* Signals fence as soon as all the work currently put on queue is done. */
4675 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4678 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4683 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4685 return info
->commandBufferCount
||
4686 info
->waitSemaphoreCount
||
4687 info
->signalSemaphoreCount
;
4690 VkResult
radv_QueueSubmit(
4692 uint32_t submitCount
,
4693 const VkSubmitInfo
* pSubmits
,
4696 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4698 uint32_t fence_idx
= 0;
4699 bool flushed_caches
= false;
4701 if (fence
!= VK_NULL_HANDLE
) {
4702 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4703 if (radv_submit_has_effects(pSubmits
+ i
))
4706 fence_idx
= UINT32_MAX
;
4708 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4709 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4712 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4713 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4714 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4717 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4718 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4720 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4721 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4722 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4723 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4724 .flush_caches
= !flushed_caches
,
4725 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4726 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4727 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4728 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4729 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4730 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4731 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4732 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4733 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4735 if (result
!= VK_SUCCESS
)
4738 flushed_caches
= true;
4741 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4742 result
= radv_signal_fence(queue
, fence
);
4743 if (result
!= VK_SUCCESS
)
4750 VkResult
radv_QueueWaitIdle(
4753 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4755 pthread_mutex_lock(&queue
->pending_mutex
);
4756 while (!list_is_empty(&queue
->pending_submissions
)) {
4757 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4759 pthread_mutex_unlock(&queue
->pending_mutex
);
4761 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4762 radv_queue_family_to_ring(queue
->queue_family_index
),
4767 VkResult
radv_DeviceWaitIdle(
4770 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4772 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4773 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4774 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4780 VkResult
radv_EnumerateInstanceExtensionProperties(
4781 const char* pLayerName
,
4782 uint32_t* pPropertyCount
,
4783 VkExtensionProperties
* pProperties
)
4785 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4787 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4788 if (radv_supported_instance_extensions
.extensions
[i
]) {
4789 vk_outarray_append(&out
, prop
) {
4790 *prop
= radv_instance_extensions
[i
];
4795 return vk_outarray_status(&out
);
4798 VkResult
radv_EnumerateDeviceExtensionProperties(
4799 VkPhysicalDevice physicalDevice
,
4800 const char* pLayerName
,
4801 uint32_t* pPropertyCount
,
4802 VkExtensionProperties
* pProperties
)
4804 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4805 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4807 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4808 if (device
->supported_extensions
.extensions
[i
]) {
4809 vk_outarray_append(&out
, prop
) {
4810 *prop
= radv_device_extensions
[i
];
4815 return vk_outarray_status(&out
);
4818 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4819 VkInstance _instance
,
4822 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4823 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4826 return radv_lookup_entrypoint_unchecked(pName
);
4828 return radv_lookup_entrypoint_checked(pName
,
4829 instance
? instance
->apiVersion
: 0,
4830 instance
? &instance
->enabled_extensions
: NULL
,
4835 /* The loader wants us to expose a second GetInstanceProcAddr function
4836 * to work around certain LD_PRELOAD issues seen in apps.
4839 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4840 VkInstance instance
,
4844 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4845 VkInstance instance
,
4848 return radv_GetInstanceProcAddr(instance
, pName
);
4852 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4853 VkInstance _instance
,
4857 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4858 VkInstance _instance
,
4861 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4863 return radv_lookup_physical_device_entrypoint_checked(pName
,
4864 instance
? instance
->apiVersion
: 0,
4865 instance
? &instance
->enabled_extensions
: NULL
);
4868 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4872 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4873 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4876 return radv_lookup_entrypoint_unchecked(pName
);
4878 return radv_lookup_entrypoint_checked(pName
,
4879 device
->instance
->apiVersion
,
4880 &device
->instance
->enabled_extensions
,
4881 &device
->enabled_extensions
);
4885 bool radv_get_memory_fd(struct radv_device
*device
,
4886 struct radv_device_memory
*memory
,
4889 struct radeon_bo_metadata metadata
;
4891 if (memory
->image
) {
4892 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4893 radv_init_metadata(device
, memory
->image
, &metadata
);
4894 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4897 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4902 static void radv_free_memory(struct radv_device
*device
,
4903 const VkAllocationCallbacks
* pAllocator
,
4904 struct radv_device_memory
*mem
)
4909 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4910 if (mem
->android_hardware_buffer
)
4911 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4915 radv_bo_list_remove(device
, mem
->bo
);
4916 device
->ws
->buffer_destroy(mem
->bo
);
4920 vk_free2(&device
->alloc
, pAllocator
, mem
);
4923 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4924 const VkMemoryAllocateInfo
* pAllocateInfo
,
4925 const VkAllocationCallbacks
* pAllocator
,
4926 VkDeviceMemory
* pMem
)
4928 struct radv_device_memory
*mem
;
4930 enum radeon_bo_domain domain
;
4932 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
4934 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4936 const VkImportMemoryFdInfoKHR
*import_info
=
4937 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4938 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4939 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4940 const VkExportMemoryAllocateInfo
*export_info
=
4941 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4942 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4943 vk_find_struct_const(pAllocateInfo
->pNext
,
4944 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4945 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4946 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4948 const struct wsi_memory_allocate_info
*wsi_info
=
4949 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4951 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4952 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4953 /* Apparently, this is allowed */
4954 *pMem
= VK_NULL_HANDLE
;
4958 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4961 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4963 if (wsi_info
&& wsi_info
->implicit_sync
)
4964 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4966 if (dedicate_info
) {
4967 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4968 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4974 float priority_float
= 0.5;
4975 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4976 vk_find_struct_const(pAllocateInfo
->pNext
,
4977 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4979 priority_float
= priority_ext
->priority
;
4981 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4982 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4984 mem
->user_ptr
= NULL
;
4987 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4988 mem
->android_hardware_buffer
= NULL
;
4991 if (ahb_import_info
) {
4992 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4993 if (result
!= VK_SUCCESS
)
4995 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4996 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4997 if (result
!= VK_SUCCESS
)
4999 } else if (import_info
) {
5000 assert(import_info
->handleType
==
5001 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5002 import_info
->handleType
==
5003 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5004 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5007 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5010 close(import_info
->fd
);
5012 } else if (host_ptr_info
) {
5013 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5014 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5015 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5016 pAllocateInfo
->allocationSize
,
5019 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5022 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5025 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5026 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5027 radv_is_mem_type_gtt_cached(mem_type_index
))
5028 domain
= RADEON_DOMAIN_GTT
;
5030 domain
= RADEON_DOMAIN_VRAM
;
5032 if (radv_is_mem_type_vram(mem_type_index
))
5033 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5035 flags
|= RADEON_FLAG_CPU_ACCESS
;
5037 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5038 flags
|= RADEON_FLAG_GTT_WC
;
5040 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5041 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5042 if (device
->use_global_bo_list
) {
5043 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5047 if (radv_is_mem_type_uncached(mem_type_index
)) {
5048 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5049 flags
|= RADEON_FLAG_VA_UNCACHED
;
5052 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5053 domain
, flags
, priority
);
5056 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5059 mem
->type_index
= mem_type_index
;
5062 result
= radv_bo_list_add(device
, mem
->bo
);
5063 if (result
!= VK_SUCCESS
)
5066 *pMem
= radv_device_memory_to_handle(mem
);
5071 radv_free_memory(device
, pAllocator
,mem
);
5076 VkResult
radv_AllocateMemory(
5078 const VkMemoryAllocateInfo
* pAllocateInfo
,
5079 const VkAllocationCallbacks
* pAllocator
,
5080 VkDeviceMemory
* pMem
)
5082 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5083 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5086 void radv_FreeMemory(
5088 VkDeviceMemory _mem
,
5089 const VkAllocationCallbacks
* pAllocator
)
5091 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5092 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5094 radv_free_memory(device
, pAllocator
, mem
);
5097 VkResult
radv_MapMemory(
5099 VkDeviceMemory _memory
,
5100 VkDeviceSize offset
,
5102 VkMemoryMapFlags flags
,
5105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5106 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5114 *ppData
= mem
->user_ptr
;
5116 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5123 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5126 void radv_UnmapMemory(
5128 VkDeviceMemory _memory
)
5130 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5131 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5136 if (mem
->user_ptr
== NULL
)
5137 device
->ws
->buffer_unmap(mem
->bo
);
5140 VkResult
radv_FlushMappedMemoryRanges(
5142 uint32_t memoryRangeCount
,
5143 const VkMappedMemoryRange
* pMemoryRanges
)
5148 VkResult
radv_InvalidateMappedMemoryRanges(
5150 uint32_t memoryRangeCount
,
5151 const VkMappedMemoryRange
* pMemoryRanges
)
5156 void radv_GetBufferMemoryRequirements(
5159 VkMemoryRequirements
* pMemoryRequirements
)
5161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5162 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5164 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5166 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5167 pMemoryRequirements
->alignment
= 4096;
5169 pMemoryRequirements
->alignment
= 16;
5171 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5174 void radv_GetBufferMemoryRequirements2(
5176 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5177 VkMemoryRequirements2
*pMemoryRequirements
)
5179 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5180 &pMemoryRequirements
->memoryRequirements
);
5181 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5182 switch (ext
->sType
) {
5183 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5184 VkMemoryDedicatedRequirements
*req
=
5185 (VkMemoryDedicatedRequirements
*) ext
;
5186 req
->requiresDedicatedAllocation
= false;
5187 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5196 void radv_GetImageMemoryRequirements(
5199 VkMemoryRequirements
* pMemoryRequirements
)
5201 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5202 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5204 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5206 pMemoryRequirements
->size
= image
->size
;
5207 pMemoryRequirements
->alignment
= image
->alignment
;
5210 void radv_GetImageMemoryRequirements2(
5212 const VkImageMemoryRequirementsInfo2
*pInfo
,
5213 VkMemoryRequirements2
*pMemoryRequirements
)
5215 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5216 &pMemoryRequirements
->memoryRequirements
);
5218 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5220 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5221 switch (ext
->sType
) {
5222 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5223 VkMemoryDedicatedRequirements
*req
=
5224 (VkMemoryDedicatedRequirements
*) ext
;
5225 req
->requiresDedicatedAllocation
= image
->shareable
&&
5226 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5227 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5236 void radv_GetImageSparseMemoryRequirements(
5239 uint32_t* pSparseMemoryRequirementCount
,
5240 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5245 void radv_GetImageSparseMemoryRequirements2(
5247 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5248 uint32_t* pSparseMemoryRequirementCount
,
5249 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5254 void radv_GetDeviceMemoryCommitment(
5256 VkDeviceMemory memory
,
5257 VkDeviceSize
* pCommittedMemoryInBytes
)
5259 *pCommittedMemoryInBytes
= 0;
5262 VkResult
radv_BindBufferMemory2(VkDevice device
,
5263 uint32_t bindInfoCount
,
5264 const VkBindBufferMemoryInfo
*pBindInfos
)
5266 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5267 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5268 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5271 buffer
->bo
= mem
->bo
;
5272 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5280 VkResult
radv_BindBufferMemory(
5283 VkDeviceMemory memory
,
5284 VkDeviceSize memoryOffset
)
5286 const VkBindBufferMemoryInfo info
= {
5287 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5290 .memoryOffset
= memoryOffset
5293 return radv_BindBufferMemory2(device
, 1, &info
);
5296 VkResult
radv_BindImageMemory2(VkDevice device
,
5297 uint32_t bindInfoCount
,
5298 const VkBindImageMemoryInfo
*pBindInfos
)
5300 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5301 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5302 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5305 image
->bo
= mem
->bo
;
5306 image
->offset
= pBindInfos
[i
].memoryOffset
;
5316 VkResult
radv_BindImageMemory(
5319 VkDeviceMemory memory
,
5320 VkDeviceSize memoryOffset
)
5322 const VkBindImageMemoryInfo info
= {
5323 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5326 .memoryOffset
= memoryOffset
5329 return radv_BindImageMemory2(device
, 1, &info
);
5332 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5334 return info
->bufferBindCount
||
5335 info
->imageOpaqueBindCount
||
5336 info
->imageBindCount
||
5337 info
->waitSemaphoreCount
||
5338 info
->signalSemaphoreCount
;
5341 VkResult
radv_QueueBindSparse(
5343 uint32_t bindInfoCount
,
5344 const VkBindSparseInfo
* pBindInfo
,
5347 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5349 uint32_t fence_idx
= 0;
5351 if (fence
!= VK_NULL_HANDLE
) {
5352 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5353 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5356 fence_idx
= UINT32_MAX
;
5358 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5359 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5362 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5363 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5365 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5366 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5367 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5368 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5369 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5370 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5371 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5372 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5373 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5374 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5375 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5376 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5377 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5378 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5381 if (result
!= VK_SUCCESS
)
5385 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5386 result
= radv_signal_fence(queue
, fence
);
5387 if (result
!= VK_SUCCESS
)
5394 VkResult
radv_CreateFence(
5396 const VkFenceCreateInfo
* pCreateInfo
,
5397 const VkAllocationCallbacks
* pAllocator
,
5400 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5401 const VkExportFenceCreateInfo
*export
=
5402 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5403 VkExternalFenceHandleTypeFlags handleTypes
=
5404 export
? export
->handleTypes
: 0;
5406 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5408 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5411 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5413 fence
->fence_wsi
= NULL
;
5414 fence
->temp_syncobj
= 0;
5415 if (device
->always_use_syncobj
|| handleTypes
) {
5416 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5418 vk_free2(&device
->alloc
, pAllocator
, fence
);
5419 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5421 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5422 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5424 fence
->fence
= NULL
;
5426 fence
->fence
= device
->ws
->create_fence();
5427 if (!fence
->fence
) {
5428 vk_free2(&device
->alloc
, pAllocator
, fence
);
5429 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5432 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5433 device
->ws
->signal_fence(fence
->fence
);
5436 *pFence
= radv_fence_to_handle(fence
);
5441 void radv_DestroyFence(
5444 const VkAllocationCallbacks
* pAllocator
)
5446 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5447 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5452 if (fence
->temp_syncobj
)
5453 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5455 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5457 device
->ws
->destroy_fence(fence
->fence
);
5458 if (fence
->fence_wsi
)
5459 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5460 vk_free2(&device
->alloc
, pAllocator
, fence
);
5464 uint64_t radv_get_current_time(void)
5467 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5468 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5471 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5473 uint64_t current_time
= radv_get_current_time();
5475 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5477 return current_time
+ timeout
;
5481 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5482 uint32_t fenceCount
, const VkFence
*pFences
)
5484 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5485 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5486 if (fence
->fence
== NULL
|| fence
->syncobj
||
5487 fence
->temp_syncobj
|| fence
->fence_wsi
||
5488 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5494 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5496 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5497 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5498 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5504 VkResult
radv_WaitForFences(
5506 uint32_t fenceCount
,
5507 const VkFence
* pFences
,
5511 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5512 timeout
= radv_get_absolute_timeout(timeout
);
5514 if (device
->always_use_syncobj
&&
5515 radv_all_fences_syncobj(fenceCount
, pFences
))
5517 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5519 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5521 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5522 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5523 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5526 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5529 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5532 if (!waitAll
&& fenceCount
> 1) {
5533 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5534 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5535 uint32_t wait_count
= 0;
5536 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5538 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5540 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5541 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5543 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5548 fences
[wait_count
++] = fence
->fence
;
5551 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5552 waitAll
, timeout
- radv_get_current_time());
5555 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5558 while(radv_get_current_time() <= timeout
) {
5559 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5560 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5567 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5568 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5569 bool expired
= false;
5571 if (fence
->temp_syncobj
) {
5572 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5577 if (fence
->syncobj
) {
5578 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5584 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5585 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5586 radv_get_current_time() <= timeout
)
5590 expired
= device
->ws
->fence_wait(device
->ws
,
5597 if (fence
->fence_wsi
) {
5598 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5599 if (result
!= VK_SUCCESS
)
5607 VkResult
radv_ResetFences(VkDevice _device
,
5608 uint32_t fenceCount
,
5609 const VkFence
*pFences
)
5611 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5613 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5614 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5616 device
->ws
->reset_fence(fence
->fence
);
5618 /* Per spec, we first restore the permanent payload, and then reset, so
5619 * having a temp syncobj should not skip resetting the permanent syncobj. */
5620 if (fence
->temp_syncobj
) {
5621 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5622 fence
->temp_syncobj
= 0;
5625 if (fence
->syncobj
) {
5626 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5633 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5635 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5636 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5638 if (fence
->temp_syncobj
) {
5639 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5640 return success
? VK_SUCCESS
: VK_NOT_READY
;
5643 if (fence
->syncobj
) {
5644 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5645 return success
? VK_SUCCESS
: VK_NOT_READY
;
5649 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5650 return VK_NOT_READY
;
5652 if (fence
->fence_wsi
) {
5653 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5655 if (result
!= VK_SUCCESS
) {
5656 if (result
== VK_TIMEOUT
)
5657 return VK_NOT_READY
;
5665 // Queue semaphore functions
5668 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5670 timeline
->highest_signaled
= value
;
5671 timeline
->highest_submitted
= value
;
5672 list_inithead(&timeline
->points
);
5673 list_inithead(&timeline
->free_points
);
5674 list_inithead(&timeline
->waiters
);
5675 pthread_mutex_init(&timeline
->mutex
, NULL
);
5679 radv_destroy_timeline(struct radv_device
*device
,
5680 struct radv_timeline
*timeline
)
5682 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5683 &timeline
->free_points
, list
) {
5684 list_del(&point
->list
);
5685 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5688 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5689 &timeline
->points
, list
) {
5690 list_del(&point
->list
);
5691 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5694 pthread_mutex_destroy(&timeline
->mutex
);
5698 radv_timeline_gc_locked(struct radv_device
*device
,
5699 struct radv_timeline
*timeline
)
5701 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5702 &timeline
->points
, list
) {
5703 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5706 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5707 timeline
->highest_signaled
= point
->value
;
5708 list_del(&point
->list
);
5709 list_add(&point
->list
, &timeline
->free_points
);
5714 static struct radv_timeline_point
*
5715 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5716 struct radv_timeline
*timeline
,
5719 radv_timeline_gc_locked(device
, timeline
);
5721 if (p
<= timeline
->highest_signaled
)
5724 list_for_each_entry(struct radv_timeline_point
, point
,
5725 &timeline
->points
, list
) {
5726 if (point
->value
>= p
) {
5727 ++point
->wait_count
;
5734 static struct radv_timeline_point
*
5735 radv_timeline_add_point_locked(struct radv_device
*device
,
5736 struct radv_timeline
*timeline
,
5739 radv_timeline_gc_locked(device
, timeline
);
5741 struct radv_timeline_point
*ret
= NULL
;
5742 struct radv_timeline_point
*prev
= NULL
;
5744 if (p
<= timeline
->highest_signaled
)
5747 list_for_each_entry(struct radv_timeline_point
, point
,
5748 &timeline
->points
, list
) {
5749 if (point
->value
== p
) {
5753 if (point
->value
< p
)
5757 if (list_is_empty(&timeline
->free_points
)) {
5758 ret
= malloc(sizeof(struct radv_timeline_point
));
5759 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5761 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5762 list_del(&ret
->list
);
5764 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5768 ret
->wait_count
= 1;
5771 list_add(&ret
->list
, &prev
->list
);
5773 list_addtail(&ret
->list
, &timeline
->points
);
5780 radv_timeline_wait_locked(struct radv_device
*device
,
5781 struct radv_timeline
*timeline
,
5783 uint64_t abs_timeout
)
5785 while(timeline
->highest_submitted
< value
) {
5786 struct timespec abstime
;
5787 timespec_from_nsec(&abstime
, abs_timeout
);
5789 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5791 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5795 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5799 pthread_mutex_unlock(&timeline
->mutex
);
5801 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5803 pthread_mutex_lock(&timeline
->mutex
);
5804 point
->wait_count
--;
5805 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5809 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5810 struct list_head
*processing_list
)
5812 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5813 &timeline
->waiters
, list
) {
5814 if (waiter
->value
> timeline
->highest_submitted
)
5817 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5818 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5820 list_del(&waiter
->list
);
5825 void radv_destroy_semaphore_part(struct radv_device
*device
,
5826 struct radv_semaphore_part
*part
)
5828 switch(part
->kind
) {
5829 case RADV_SEMAPHORE_NONE
:
5831 case RADV_SEMAPHORE_WINSYS
:
5832 device
->ws
->destroy_sem(part
->ws_sem
);
5834 case RADV_SEMAPHORE_TIMELINE
:
5835 radv_destroy_timeline(device
, &part
->timeline
);
5837 case RADV_SEMAPHORE_SYNCOBJ
:
5838 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5841 part
->kind
= RADV_SEMAPHORE_NONE
;
5844 static VkSemaphoreTypeKHR
5845 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5847 const VkSemaphoreTypeCreateInfo
*type_info
=
5848 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5851 return VK_SEMAPHORE_TYPE_BINARY
;
5854 *initial_value
= type_info
->initialValue
;
5855 return type_info
->semaphoreType
;
5858 VkResult
radv_CreateSemaphore(
5860 const VkSemaphoreCreateInfo
* pCreateInfo
,
5861 const VkAllocationCallbacks
* pAllocator
,
5862 VkSemaphore
* pSemaphore
)
5864 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5865 const VkExportSemaphoreCreateInfo
*export
=
5866 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5867 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5868 export
? export
->handleTypes
: 0;
5869 uint64_t initial_value
= 0;
5870 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5872 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5874 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5876 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5878 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5879 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5881 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5882 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5883 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5884 } else if (device
->always_use_syncobj
|| handleTypes
) {
5885 assert (device
->physical_device
->rad_info
.has_syncobj
);
5886 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
5888 vk_free2(&device
->alloc
, pAllocator
, sem
);
5889 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5891 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5893 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5894 if (!sem
->permanent
.ws_sem
) {
5895 vk_free2(&device
->alloc
, pAllocator
, sem
);
5896 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5898 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5901 *pSemaphore
= radv_semaphore_to_handle(sem
);
5905 void radv_DestroySemaphore(
5907 VkSemaphore _semaphore
,
5908 const VkAllocationCallbacks
* pAllocator
)
5910 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5911 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5915 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5916 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5917 vk_free2(&device
->alloc
, pAllocator
, sem
);
5921 radv_GetSemaphoreCounterValue(VkDevice _device
,
5922 VkSemaphore _semaphore
,
5925 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5926 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5928 struct radv_semaphore_part
*part
=
5929 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5931 switch (part
->kind
) {
5932 case RADV_SEMAPHORE_TIMELINE
: {
5933 pthread_mutex_lock(&part
->timeline
.mutex
);
5934 radv_timeline_gc_locked(device
, &part
->timeline
);
5935 *pValue
= part
->timeline
.highest_signaled
;
5936 pthread_mutex_unlock(&part
->timeline
.mutex
);
5939 case RADV_SEMAPHORE_NONE
:
5940 case RADV_SEMAPHORE_SYNCOBJ
:
5941 case RADV_SEMAPHORE_WINSYS
:
5942 unreachable("Invalid semaphore type");
5944 unreachable("Unhandled semaphore type");
5949 radv_wait_timelines(struct radv_device
*device
,
5950 const VkSemaphoreWaitInfo
* pWaitInfo
,
5951 uint64_t abs_timeout
)
5953 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5955 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5956 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5957 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5958 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5959 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5961 if (result
== VK_SUCCESS
)
5964 if (radv_get_current_time() > abs_timeout
)
5969 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5970 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5971 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5972 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5973 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5975 if (result
!= VK_SUCCESS
)
5981 radv_WaitSemaphores(VkDevice _device
,
5982 const VkSemaphoreWaitInfo
* pWaitInfo
,
5985 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5986 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5987 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5991 radv_SignalSemaphore(VkDevice _device
,
5992 const VkSemaphoreSignalInfo
* pSignalInfo
)
5994 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5995 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
5997 struct radv_semaphore_part
*part
=
5998 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6000 switch(part
->kind
) {
6001 case RADV_SEMAPHORE_TIMELINE
: {
6002 pthread_mutex_lock(&part
->timeline
.mutex
);
6003 radv_timeline_gc_locked(device
, &part
->timeline
);
6004 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6005 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6007 struct list_head processing_list
;
6008 list_inithead(&processing_list
);
6009 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6010 pthread_mutex_unlock(&part
->timeline
.mutex
);
6012 return radv_process_submissions(&processing_list
);
6014 case RADV_SEMAPHORE_NONE
:
6015 case RADV_SEMAPHORE_SYNCOBJ
:
6016 case RADV_SEMAPHORE_WINSYS
:
6017 unreachable("Invalid semaphore type");
6024 VkResult
radv_CreateEvent(
6026 const VkEventCreateInfo
* pCreateInfo
,
6027 const VkAllocationCallbacks
* pAllocator
,
6030 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6031 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6033 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6036 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6038 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6040 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6041 RADV_BO_PRIORITY_FENCE
);
6043 vk_free2(&device
->alloc
, pAllocator
, event
);
6044 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6047 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6049 *pEvent
= radv_event_to_handle(event
);
6054 void radv_DestroyEvent(
6057 const VkAllocationCallbacks
* pAllocator
)
6059 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6060 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6064 device
->ws
->buffer_destroy(event
->bo
);
6065 vk_free2(&device
->alloc
, pAllocator
, event
);
6068 VkResult
radv_GetEventStatus(
6072 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6074 if (*event
->map
== 1)
6075 return VK_EVENT_SET
;
6076 return VK_EVENT_RESET
;
6079 VkResult
radv_SetEvent(
6083 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6089 VkResult
radv_ResetEvent(
6093 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6099 VkResult
radv_CreateBuffer(
6101 const VkBufferCreateInfo
* pCreateInfo
,
6102 const VkAllocationCallbacks
* pAllocator
,
6105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6106 struct radv_buffer
*buffer
;
6108 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6110 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6111 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6113 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6115 buffer
->size
= pCreateInfo
->size
;
6116 buffer
->usage
= pCreateInfo
->usage
;
6119 buffer
->flags
= pCreateInfo
->flags
;
6121 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6122 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6124 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6125 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6126 align64(buffer
->size
, 4096),
6127 4096, 0, RADEON_FLAG_VIRTUAL
,
6128 RADV_BO_PRIORITY_VIRTUAL
);
6130 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6131 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6135 *pBuffer
= radv_buffer_to_handle(buffer
);
6140 void radv_DestroyBuffer(
6143 const VkAllocationCallbacks
* pAllocator
)
6145 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6146 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6151 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6152 device
->ws
->buffer_destroy(buffer
->bo
);
6154 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6157 VkDeviceAddress
radv_GetBufferDeviceAddress(
6159 const VkBufferDeviceAddressInfo
* pInfo
)
6161 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6162 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6166 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6167 const VkBufferDeviceAddressInfo
* pInfo
)
6172 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6173 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6178 static inline unsigned
6179 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6182 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6184 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6187 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6189 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6193 radv_init_dcc_control_reg(struct radv_device
*device
,
6194 struct radv_image_view
*iview
)
6196 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6197 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6198 unsigned max_compressed_block_size
;
6199 unsigned independent_128b_blocks
;
6200 unsigned independent_64b_blocks
;
6202 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6205 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6206 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6207 * dGPU and 64 for APU because all of our APUs to date use
6208 * DIMMs which have a request granularity size of 64B while all
6209 * other chips have a 32B request size.
6211 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6214 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6215 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6216 independent_64b_blocks
= 0;
6217 independent_128b_blocks
= 1;
6219 independent_128b_blocks
= 0;
6221 if (iview
->image
->info
.samples
> 1) {
6222 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6223 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6224 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6225 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6228 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6229 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6230 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6231 /* If this DCC image is potentially going to be used in texture
6232 * fetches, we need some special settings.
6234 independent_64b_blocks
= 1;
6235 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6237 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6238 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6239 * big as possible for better compression state.
6241 independent_64b_blocks
= 0;
6242 max_compressed_block_size
= max_uncompressed_block_size
;
6246 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6247 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6248 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6249 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6250 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6254 radv_initialise_color_surface(struct radv_device
*device
,
6255 struct radv_color_buffer_info
*cb
,
6256 struct radv_image_view
*iview
)
6258 const struct vk_format_description
*desc
;
6259 unsigned ntype
, format
, swap
, endian
;
6260 unsigned blend_clamp
= 0, blend_bypass
= 0;
6262 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6263 const struct radeon_surf
*surf
= &plane
->surface
;
6265 desc
= vk_format_description(iview
->vk_format
);
6267 memset(cb
, 0, sizeof(*cb
));
6269 /* Intensity is implemented as Red, so treat it that way. */
6270 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6272 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6274 cb
->cb_color_base
= va
>> 8;
6276 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6277 struct gfx9_surf_meta_flags meta
;
6278 if (iview
->image
->dcc_offset
)
6279 meta
= surf
->u
.gfx9
.dcc
;
6281 meta
= surf
->u
.gfx9
.cmask
;
6283 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6284 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6285 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6286 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6287 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6289 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6290 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6291 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6292 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6293 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6296 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6297 cb
->cb_color_base
|= surf
->tile_swizzle
;
6299 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6300 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6302 cb
->cb_color_base
+= level_info
->offset
>> 8;
6303 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6304 cb
->cb_color_base
|= surf
->tile_swizzle
;
6306 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6307 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6308 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6310 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6311 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6312 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6314 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6316 if (radv_image_has_fmask(iview
->image
)) {
6317 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6318 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6319 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6320 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6322 /* This must be set for fast clear to work without FMASK. */
6323 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6324 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6325 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6326 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6330 /* CMASK variables */
6331 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6332 va
+= iview
->image
->cmask_offset
;
6333 cb
->cb_color_cmask
= va
>> 8;
6335 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6336 va
+= iview
->image
->dcc_offset
;
6338 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6339 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6340 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6342 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6343 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6345 cb
->cb_dcc_base
= va
>> 8;
6346 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6348 /* GFX10 field has the same base shift as the GFX6 field. */
6349 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6350 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6351 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6353 if (iview
->image
->info
.samples
> 1) {
6354 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6356 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6357 S_028C74_NUM_FRAGMENTS(log_samples
);
6360 if (radv_image_has_fmask(iview
->image
)) {
6361 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6362 cb
->cb_color_fmask
= va
>> 8;
6363 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6365 cb
->cb_color_fmask
= cb
->cb_color_base
;
6368 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6370 vk_format_get_first_non_void_channel(iview
->vk_format
));
6371 format
= radv_translate_colorformat(iview
->vk_format
);
6372 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6373 radv_finishme("Illegal color\n");
6374 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6375 endian
= radv_colorformat_endian_swap(format
);
6377 /* blend clamp should be set for all NORM/SRGB types */
6378 if (ntype
== V_028C70_NUMBER_UNORM
||
6379 ntype
== V_028C70_NUMBER_SNORM
||
6380 ntype
== V_028C70_NUMBER_SRGB
)
6383 /* set blend bypass according to docs if SINT/UINT or
6384 8/24 COLOR variants */
6385 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6386 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6387 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6392 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6393 (format
== V_028C70_COLOR_8
||
6394 format
== V_028C70_COLOR_8_8
||
6395 format
== V_028C70_COLOR_8_8_8_8
))
6396 ->color_is_int8
= true;
6398 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6399 S_028C70_COMP_SWAP(swap
) |
6400 S_028C70_BLEND_CLAMP(blend_clamp
) |
6401 S_028C70_BLEND_BYPASS(blend_bypass
) |
6402 S_028C70_SIMPLE_FLOAT(1) |
6403 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6404 ntype
!= V_028C70_NUMBER_SNORM
&&
6405 ntype
!= V_028C70_NUMBER_SRGB
&&
6406 format
!= V_028C70_COLOR_8_24
&&
6407 format
!= V_028C70_COLOR_24_8
) |
6408 S_028C70_NUMBER_TYPE(ntype
) |
6409 S_028C70_ENDIAN(endian
);
6410 if (radv_image_has_fmask(iview
->image
)) {
6411 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6412 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6413 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6414 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6417 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6418 /* Allow the texture block to read FMASK directly
6419 * without decompressing it. This bit must be cleared
6420 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6421 * otherwise the operation doesn't happen.
6423 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6425 /* Set CMASK into a tiling format that allows the
6426 * texture block to read it.
6428 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6432 if (radv_image_has_cmask(iview
->image
) &&
6433 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6434 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6436 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6437 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6439 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6441 /* This must be set for fast clear to work without FMASK. */
6442 if (!radv_image_has_fmask(iview
->image
) &&
6443 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6444 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6445 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6448 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6449 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6451 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6452 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6453 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6454 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6456 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6457 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6459 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6460 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6461 S_028EE0_RESOURCE_LEVEL(1);
6463 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6464 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6465 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6468 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6469 S_028C68_MIP0_HEIGHT(height
- 1) |
6470 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6475 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6476 struct radv_image_view
*iview
)
6478 unsigned max_zplanes
= 0;
6480 assert(radv_image_is_tc_compat_htile(iview
->image
));
6482 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6483 /* Default value for 32-bit depth surfaces. */
6486 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6487 iview
->image
->info
.samples
> 1)
6490 max_zplanes
= max_zplanes
+ 1;
6492 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6493 /* Do not enable Z plane compression for 16-bit depth
6494 * surfaces because isn't supported on GFX8. Only
6495 * 32-bit depth surfaces are supported by the hardware.
6496 * This allows to maintain shader compatibility and to
6497 * reduce the number of depth decompressions.
6501 if (iview
->image
->info
.samples
<= 1)
6503 else if (iview
->image
->info
.samples
<= 4)
6514 radv_initialise_ds_surface(struct radv_device
*device
,
6515 struct radv_ds_buffer_info
*ds
,
6516 struct radv_image_view
*iview
)
6518 unsigned level
= iview
->base_mip
;
6519 unsigned format
, stencil_format
;
6520 uint64_t va
, s_offs
, z_offs
;
6521 bool stencil_only
= false;
6522 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6523 const struct radeon_surf
*surf
= &plane
->surface
;
6525 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6527 memset(ds
, 0, sizeof(*ds
));
6528 switch (iview
->image
->vk_format
) {
6529 case VK_FORMAT_D24_UNORM_S8_UINT
:
6530 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6531 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6532 ds
->offset_scale
= 2.0f
;
6534 case VK_FORMAT_D16_UNORM
:
6535 case VK_FORMAT_D16_UNORM_S8_UINT
:
6536 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6537 ds
->offset_scale
= 4.0f
;
6539 case VK_FORMAT_D32_SFLOAT
:
6540 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6541 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6542 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6543 ds
->offset_scale
= 1.0f
;
6545 case VK_FORMAT_S8_UINT
:
6546 stencil_only
= true;
6552 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6553 stencil_format
= surf
->has_stencil
?
6554 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6556 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6557 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6558 S_028008_SLICE_MAX(max_slice
);
6559 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6560 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6561 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6564 ds
->db_htile_data_base
= 0;
6565 ds
->db_htile_surface
= 0;
6567 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6568 s_offs
= z_offs
= va
;
6570 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6571 assert(surf
->u
.gfx9
.surf_offset
== 0);
6572 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6574 ds
->db_z_info
= S_028038_FORMAT(format
) |
6575 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6576 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6577 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6578 S_028038_ZRANGE_PRECISION(1);
6579 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6580 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6582 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6583 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6584 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6587 ds
->db_depth_view
|= S_028008_MIPID(level
);
6588 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6589 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6591 if (radv_htile_enabled(iview
->image
, level
)) {
6592 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6594 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6595 unsigned max_zplanes
=
6596 radv_calc_decompress_on_z_planes(device
, iview
);
6598 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6600 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6601 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6602 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6604 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6605 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6609 if (!surf
->has_stencil
)
6610 /* Use all of the htile_buffer for depth if there's no stencil. */
6611 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6612 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6613 iview
->image
->htile_offset
;
6614 ds
->db_htile_data_base
= va
>> 8;
6615 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6616 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6618 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6619 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6623 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6626 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6628 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6629 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6631 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6632 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6633 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6635 if (iview
->image
->info
.samples
> 1)
6636 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6638 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6639 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6640 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6641 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6642 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6643 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6644 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6645 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6648 tile_mode
= stencil_tile_mode
;
6650 ds
->db_depth_info
|=
6651 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6652 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6653 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6654 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6655 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6656 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6657 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6658 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6660 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6661 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6662 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6663 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6665 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6668 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6669 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6670 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6672 if (radv_htile_enabled(iview
->image
, level
)) {
6673 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6675 if (!surf
->has_stencil
&&
6676 !radv_image_is_tc_compat_htile(iview
->image
))
6677 /* Use all of the htile_buffer for depth if there's no stencil. */
6678 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6680 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6681 iview
->image
->htile_offset
;
6682 ds
->db_htile_data_base
= va
>> 8;
6683 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6685 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6686 unsigned max_zplanes
=
6687 radv_calc_decompress_on_z_planes(device
, iview
);
6689 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6690 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6695 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6696 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6699 VkResult
radv_CreateFramebuffer(
6701 const VkFramebufferCreateInfo
* pCreateInfo
,
6702 const VkAllocationCallbacks
* pAllocator
,
6703 VkFramebuffer
* pFramebuffer
)
6705 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6706 struct radv_framebuffer
*framebuffer
;
6707 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6708 vk_find_struct_const(pCreateInfo
->pNext
,
6709 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6711 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6713 size_t size
= sizeof(*framebuffer
);
6714 if (!imageless_create_info
)
6715 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6716 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6717 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6718 if (framebuffer
== NULL
)
6719 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6721 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6722 framebuffer
->width
= pCreateInfo
->width
;
6723 framebuffer
->height
= pCreateInfo
->height
;
6724 framebuffer
->layers
= pCreateInfo
->layers
;
6725 if (imageless_create_info
) {
6726 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6727 const VkFramebufferAttachmentImageInfo
*attachment
=
6728 imageless_create_info
->pAttachmentImageInfos
+ i
;
6729 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6730 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6731 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6734 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6735 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6736 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6737 framebuffer
->attachments
[i
] = iview
;
6738 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6739 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6740 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6744 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6748 void radv_DestroyFramebuffer(
6751 const VkAllocationCallbacks
* pAllocator
)
6753 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6754 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6758 vk_free2(&device
->alloc
, pAllocator
, fb
);
6761 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6763 switch (address_mode
) {
6764 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6765 return V_008F30_SQ_TEX_WRAP
;
6766 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6767 return V_008F30_SQ_TEX_MIRROR
;
6768 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6769 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6770 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6771 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6772 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6773 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6775 unreachable("illegal tex wrap mode");
6781 radv_tex_compare(VkCompareOp op
)
6784 case VK_COMPARE_OP_NEVER
:
6785 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6786 case VK_COMPARE_OP_LESS
:
6787 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6788 case VK_COMPARE_OP_EQUAL
:
6789 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6790 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6791 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6792 case VK_COMPARE_OP_GREATER
:
6793 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6794 case VK_COMPARE_OP_NOT_EQUAL
:
6795 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6796 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6797 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6798 case VK_COMPARE_OP_ALWAYS
:
6799 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6801 unreachable("illegal compare mode");
6807 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6810 case VK_FILTER_NEAREST
:
6811 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6812 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6813 case VK_FILTER_LINEAR
:
6814 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6815 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6816 case VK_FILTER_CUBIC_IMG
:
6818 fprintf(stderr
, "illegal texture filter");
6824 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6827 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6828 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6829 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6830 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6832 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6837 radv_tex_bordercolor(VkBorderColor bcolor
)
6840 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6841 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6842 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6843 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6844 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6845 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6846 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6847 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6848 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6856 radv_tex_aniso_filter(unsigned filter
)
6870 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6873 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6874 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6875 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6876 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6877 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6878 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6886 radv_get_max_anisotropy(struct radv_device
*device
,
6887 const VkSamplerCreateInfo
*pCreateInfo
)
6889 if (device
->force_aniso
>= 0)
6890 return device
->force_aniso
;
6892 if (pCreateInfo
->anisotropyEnable
&&
6893 pCreateInfo
->maxAnisotropy
> 1.0f
)
6894 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6900 radv_init_sampler(struct radv_device
*device
,
6901 struct radv_sampler
*sampler
,
6902 const VkSamplerCreateInfo
*pCreateInfo
)
6904 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6905 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6906 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6907 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6908 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6909 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6911 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6912 vk_find_struct_const(pCreateInfo
->pNext
,
6913 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6914 if (sampler_reduction
)
6915 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6917 if (pCreateInfo
->compareEnable
)
6918 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6920 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6921 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6922 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6923 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6924 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6925 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6926 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6927 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6928 S_008F30_DISABLE_CUBE_WRAP(0) |
6929 S_008F30_COMPAT_MODE(compat_mode
) |
6930 S_008F30_FILTER_MODE(filter_mode
));
6931 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6932 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6933 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6934 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6935 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6936 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6937 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6938 S_008F38_MIP_POINT_PRECLAMP(0));
6939 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6940 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
6942 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6943 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6945 sampler
->state
[2] |=
6946 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6947 S_008F38_FILTER_PREC_FIX(1) |
6948 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6952 VkResult
radv_CreateSampler(
6954 const VkSamplerCreateInfo
* pCreateInfo
,
6955 const VkAllocationCallbacks
* pAllocator
,
6956 VkSampler
* pSampler
)
6958 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6959 struct radv_sampler
*sampler
;
6961 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
6962 vk_find_struct_const(pCreateInfo
->pNext
,
6963 SAMPLER_YCBCR_CONVERSION_INFO
);
6965 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
6967 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
6968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6970 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6972 radv_init_sampler(device
, sampler
, pCreateInfo
);
6974 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
6975 *pSampler
= radv_sampler_to_handle(sampler
);
6980 void radv_DestroySampler(
6983 const VkAllocationCallbacks
* pAllocator
)
6985 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6986 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
6990 vk_free2(&device
->alloc
, pAllocator
, sampler
);
6993 /* vk_icd.h does not declare this function, so we declare it here to
6994 * suppress Wmissing-prototypes.
6996 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6997 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
6999 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7000 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7002 /* For the full details on loader interface versioning, see
7003 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7004 * What follows is a condensed summary, to help you navigate the large and
7005 * confusing official doc.
7007 * - Loader interface v0 is incompatible with later versions. We don't
7010 * - In loader interface v1:
7011 * - The first ICD entrypoint called by the loader is
7012 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7014 * - The ICD must statically expose no other Vulkan symbol unless it is
7015 * linked with -Bsymbolic.
7016 * - Each dispatchable Vulkan handle created by the ICD must be
7017 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7018 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7019 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7020 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7021 * such loader-managed surfaces.
7023 * - Loader interface v2 differs from v1 in:
7024 * - The first ICD entrypoint called by the loader is
7025 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7026 * statically expose this entrypoint.
7028 * - Loader interface v3 differs from v2 in:
7029 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7030 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7031 * because the loader no longer does so.
7033 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7037 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7038 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7041 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7042 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7044 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7046 /* At the moment, we support only the below handle types. */
7047 assert(pGetFdInfo
->handleType
==
7048 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7049 pGetFdInfo
->handleType
==
7050 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7052 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7054 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7058 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7059 VkExternalMemoryHandleTypeFlagBits handleType
,
7061 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7063 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7065 switch (handleType
) {
7066 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7067 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7071 /* The valid usage section for this function says:
7073 * "handleType must not be one of the handle types defined as
7076 * So opaque handle types fall into the default "unsupported" case.
7078 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7082 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7086 uint32_t syncobj_handle
= 0;
7087 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7089 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7092 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7094 *syncobj
= syncobj_handle
;
7100 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7104 /* If we create a syncobj we do it locally so that if we have an error, we don't
7105 * leave a syncobj in an undetermined state in the fence. */
7106 uint32_t syncobj_handle
= *syncobj
;
7107 if (!syncobj_handle
) {
7108 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7110 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7115 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7117 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7119 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7122 *syncobj
= syncobj_handle
;
7129 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7130 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7132 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7133 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7135 struct radv_semaphore_part
*dst
= NULL
;
7137 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7138 dst
= &sem
->temporary
;
7140 dst
= &sem
->permanent
;
7143 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7145 switch(pImportSemaphoreFdInfo
->handleType
) {
7146 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7147 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7149 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7150 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7153 unreachable("Unhandled semaphore handle type");
7156 if (result
== VK_SUCCESS
) {
7157 dst
->syncobj
= syncobj
;
7158 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7164 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7165 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7168 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7169 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7171 uint32_t syncobj_handle
;
7173 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7174 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7175 syncobj_handle
= sem
->temporary
.syncobj
;
7177 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7178 syncobj_handle
= sem
->permanent
.syncobj
;
7181 switch(pGetFdInfo
->handleType
) {
7182 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7183 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7185 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7186 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7188 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7189 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7191 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7196 unreachable("Unhandled semaphore handle type");
7200 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7204 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7205 VkPhysicalDevice physicalDevice
,
7206 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7207 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7209 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7210 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7212 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7213 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7214 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7215 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7217 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7218 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7219 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7220 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7221 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7222 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7223 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7224 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7225 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7226 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7227 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7228 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7229 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7231 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7232 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7233 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7237 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7238 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7240 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7241 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7242 uint32_t *syncobj_dst
= NULL
;
7245 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7246 syncobj_dst
= &fence
->temp_syncobj
;
7248 syncobj_dst
= &fence
->syncobj
;
7251 switch(pImportFenceFdInfo
->handleType
) {
7252 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7253 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7254 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7255 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7257 unreachable("Unhandled fence handle type");
7261 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7262 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7265 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7266 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7268 uint32_t syncobj_handle
;
7270 if (fence
->temp_syncobj
)
7271 syncobj_handle
= fence
->temp_syncobj
;
7273 syncobj_handle
= fence
->syncobj
;
7275 switch(pGetFdInfo
->handleType
) {
7276 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7277 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7279 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7280 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7282 if (fence
->temp_syncobj
) {
7283 close (fence
->temp_syncobj
);
7284 fence
->temp_syncobj
= 0;
7286 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7291 unreachable("Unhandled fence handle type");
7295 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7299 void radv_GetPhysicalDeviceExternalFenceProperties(
7300 VkPhysicalDevice physicalDevice
,
7301 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7302 VkExternalFenceProperties
*pExternalFenceProperties
)
7304 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7306 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7307 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7308 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7309 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7310 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7311 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7312 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7314 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7315 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7316 pExternalFenceProperties
->externalFenceFeatures
= 0;
7321 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7322 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7323 const VkAllocationCallbacks
* pAllocator
,
7324 VkDebugReportCallbackEXT
* pCallback
)
7326 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7327 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7328 pCreateInfo
, pAllocator
, &instance
->alloc
,
7333 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7334 VkDebugReportCallbackEXT _callback
,
7335 const VkAllocationCallbacks
* pAllocator
)
7337 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7338 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7339 _callback
, pAllocator
, &instance
->alloc
);
7343 radv_DebugReportMessageEXT(VkInstance _instance
,
7344 VkDebugReportFlagsEXT flags
,
7345 VkDebugReportObjectTypeEXT objectType
,
7348 int32_t messageCode
,
7349 const char* pLayerPrefix
,
7350 const char* pMessage
)
7352 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7353 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7354 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7358 radv_GetDeviceGroupPeerMemoryFeatures(
7361 uint32_t localDeviceIndex
,
7362 uint32_t remoteDeviceIndex
,
7363 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7365 assert(localDeviceIndex
== remoteDeviceIndex
);
7367 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7368 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7369 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7370 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7373 static const VkTimeDomainEXT radv_time_domains
[] = {
7374 VK_TIME_DOMAIN_DEVICE_EXT
,
7375 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7376 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7379 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7380 VkPhysicalDevice physicalDevice
,
7381 uint32_t *pTimeDomainCount
,
7382 VkTimeDomainEXT
*pTimeDomains
)
7385 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7387 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7388 vk_outarray_append(&out
, i
) {
7389 *i
= radv_time_domains
[d
];
7393 return vk_outarray_status(&out
);
7397 radv_clock_gettime(clockid_t clock_id
)
7399 struct timespec current
;
7402 ret
= clock_gettime(clock_id
, ¤t
);
7403 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7404 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7408 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7411 VkResult
radv_GetCalibratedTimestampsEXT(
7413 uint32_t timestampCount
,
7414 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7415 uint64_t *pTimestamps
,
7416 uint64_t *pMaxDeviation
)
7418 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7419 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7421 uint64_t begin
, end
;
7422 uint64_t max_clock_period
= 0;
7424 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7426 for (d
= 0; d
< timestampCount
; d
++) {
7427 switch (pTimestampInfos
[d
].timeDomain
) {
7428 case VK_TIME_DOMAIN_DEVICE_EXT
:
7429 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7431 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7432 max_clock_period
= MAX2(max_clock_period
, device_period
);
7434 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7435 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7436 max_clock_period
= MAX2(max_clock_period
, 1);
7439 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7440 pTimestamps
[d
] = begin
;
7448 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7451 * The maximum deviation is the sum of the interval over which we
7452 * perform the sampling and the maximum period of any sampled
7453 * clock. That's because the maximum skew between any two sampled
7454 * clock edges is when the sampled clock with the largest period is
7455 * sampled at the end of that period but right at the beginning of the
7456 * sampling interval and some other clock is sampled right at the
7457 * begining of its sampling period and right at the end of the
7458 * sampling interval. Let's assume the GPU has the longest clock
7459 * period and that the application is sampling GPU and monotonic:
7462 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7463 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7467 * GPU -----_____-----_____-----_____-----_____
7470 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7471 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7473 * Interval <----------------->
7474 * Deviation <-------------------------->
7478 * m = read(monotonic) 2
7481 * We round the sample interval up by one tick to cover sampling error
7482 * in the interval clock
7485 uint64_t sample_interval
= end
- begin
+ 1;
7487 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7492 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7493 VkPhysicalDevice physicalDevice
,
7494 VkSampleCountFlagBits samples
,
7495 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7497 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7498 VK_SAMPLE_COUNT_4_BIT
|
7499 VK_SAMPLE_COUNT_8_BIT
)) {
7500 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7502 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };