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radv: do not emit VGT_FLUSH on GFX10
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 /* Out-of-order primitive rasterization. */
367 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
368 device->rad_info.max_se >= 2;
369 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
370 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
371
372 device->dcc_msaa_allowed =
373 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
374
375 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
376 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
377 (device->rad_info.chip_class >= GFX8 &&
378 device->rad_info.me_fw_feature >= 41);
379
380 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
381 device->rad_info.chip_class >= GFX10;
382
383 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
384
385 radv_physical_device_init_mem_types(device);
386 radv_fill_device_extension_table(device, &device->supported_extensions);
387
388 device->bus_info = *drm_device->businfo.pci;
389
390 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
391 ac_print_gpu_info(&device->rad_info);
392
393 /* The WSI is structured as a layer on top of the driver, so this has
394 * to be the last part of initialization (at least until we get other
395 * semi-layers).
396 */
397 result = radv_init_wsi(device);
398 if (result != VK_SUCCESS) {
399 device->ws->destroy(device->ws);
400 vk_error(instance, result);
401 goto fail;
402 }
403
404 return VK_SUCCESS;
405
406 fail:
407 close(fd);
408 if (master_fd != -1)
409 close(master_fd);
410 return result;
411 }
412
413 static void
414 radv_physical_device_finish(struct radv_physical_device *device)
415 {
416 radv_finish_wsi(device);
417 device->ws->destroy(device->ws);
418 disk_cache_destroy(device->disk_cache);
419 close(device->local_fd);
420 if (device->master_fd != -1)
421 close(device->master_fd);
422 }
423
424 static void *
425 default_alloc_func(void *pUserData, size_t size, size_t align,
426 VkSystemAllocationScope allocationScope)
427 {
428 return malloc(size);
429 }
430
431 static void *
432 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
433 size_t align, VkSystemAllocationScope allocationScope)
434 {
435 return realloc(pOriginal, size);
436 }
437
438 static void
439 default_free_func(void *pUserData, void *pMemory)
440 {
441 free(pMemory);
442 }
443
444 static const VkAllocationCallbacks default_alloc = {
445 .pUserData = NULL,
446 .pfnAllocation = default_alloc_func,
447 .pfnReallocation = default_realloc_func,
448 .pfnFree = default_free_func,
449 };
450
451 static const struct debug_control radv_debug_options[] = {
452 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
453 {"nodcc", RADV_DEBUG_NO_DCC},
454 {"shaders", RADV_DEBUG_DUMP_SHADERS},
455 {"nocache", RADV_DEBUG_NO_CACHE},
456 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
457 {"nohiz", RADV_DEBUG_NO_HIZ},
458 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
459 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
460 {"allbos", RADV_DEBUG_ALL_BOS},
461 {"noibs", RADV_DEBUG_NO_IBS},
462 {"spirv", RADV_DEBUG_DUMP_SPIRV},
463 {"vmfaults", RADV_DEBUG_VM_FAULTS},
464 {"zerovram", RADV_DEBUG_ZERO_VRAM},
465 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
466 {"nosisched", RADV_DEBUG_NO_SISCHED},
467 {"preoptir", RADV_DEBUG_PREOPTIR},
468 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
469 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
470 {"info", RADV_DEBUG_INFO},
471 {"errors", RADV_DEBUG_ERRORS},
472 {"startup", RADV_DEBUG_STARTUP},
473 {"checkir", RADV_DEBUG_CHECKIR},
474 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
475 {"nobinning", RADV_DEBUG_NOBINNING},
476 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
477 {NULL, 0}
478 };
479
480 const char *
481 radv_get_debug_option_name(int id)
482 {
483 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
484 return radv_debug_options[id].string;
485 }
486
487 static const struct debug_control radv_perftest_options[] = {
488 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
489 {"sisched", RADV_PERFTEST_SISCHED},
490 {"localbos", RADV_PERFTEST_LOCAL_BOS},
491 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
492 {"bolist", RADV_PERFTEST_BO_LIST},
493 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
494 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
495 {NULL, 0}
496 };
497
498 const char *
499 radv_get_perftest_option_name(int id)
500 {
501 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
502 return radv_perftest_options[id].string;
503 }
504
505 static void
506 radv_handle_per_app_options(struct radv_instance *instance,
507 const VkApplicationInfo *info)
508 {
509 const char *name = info ? info->pApplicationName : NULL;
510
511 if (!name)
512 return;
513
514 if (!strcmp(name, "Talos - Linux - 32bit") ||
515 !strcmp(name, "Talos - Linux - 64bit")) {
516 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
517 /* Force enable LLVM sisched for Talos because it looks
518 * safe and it gives few more FPS.
519 */
520 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
521 }
522 } else if (!strcmp(name, "DOOM_VFR")) {
523 /* Work around a Doom VFR game bug */
524 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
525 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
526 /* Workaround for a WaW hazard when LLVM moves/merges
527 * load/store memory operations.
528 * See https://reviews.llvm.org/D61313
529 */
530 if (HAVE_LLVM < 0x900)
531 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
532 }
533 }
534
535 static int radv_get_instance_extension_index(const char *name)
536 {
537 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
538 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
539 return i;
540 }
541 return -1;
542 }
543
544 static const char radv_dri_options_xml[] =
545 DRI_CONF_BEGIN
546 DRI_CONF_SECTION_QUALITY
547 DRI_CONF_ADAPTIVE_SYNC("true")
548 DRI_CONF_SECTION_END
549 DRI_CONF_END;
550
551 static void radv_init_dri_options(struct radv_instance *instance)
552 {
553 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
554 driParseConfigFiles(&instance->dri_options,
555 &instance->available_dri_options,
556 0, "radv", NULL);
557 }
558
559 VkResult radv_CreateInstance(
560 const VkInstanceCreateInfo* pCreateInfo,
561 const VkAllocationCallbacks* pAllocator,
562 VkInstance* pInstance)
563 {
564 struct radv_instance *instance;
565 VkResult result;
566
567 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
568
569 uint32_t client_version;
570 if (pCreateInfo->pApplicationInfo &&
571 pCreateInfo->pApplicationInfo->apiVersion != 0) {
572 client_version = pCreateInfo->pApplicationInfo->apiVersion;
573 } else {
574 client_version = VK_API_VERSION_1_0;
575 }
576
577 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
578 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
579 if (!instance)
580 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
581
582 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
583
584 if (pAllocator)
585 instance->alloc = *pAllocator;
586 else
587 instance->alloc = default_alloc;
588
589 instance->apiVersion = client_version;
590 instance->physicalDeviceCount = -1;
591
592 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
593 radv_debug_options);
594
595 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
596 radv_perftest_options);
597
598
599 if (instance->debug_flags & RADV_DEBUG_STARTUP)
600 radv_logi("Created an instance");
601
602 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
603 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
604 int index = radv_get_instance_extension_index(ext_name);
605
606 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
607 vk_free2(&default_alloc, pAllocator, instance);
608 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
609 }
610
611 instance->enabled_extensions.extensions[index] = true;
612 }
613
614 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
615 if (result != VK_SUCCESS) {
616 vk_free2(&default_alloc, pAllocator, instance);
617 return vk_error(instance, result);
618 }
619
620 _mesa_locale_init();
621 glsl_type_singleton_init_or_ref();
622
623 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
624
625 radv_init_dri_options(instance);
626 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
627
628 *pInstance = radv_instance_to_handle(instance);
629
630 return VK_SUCCESS;
631 }
632
633 void radv_DestroyInstance(
634 VkInstance _instance,
635 const VkAllocationCallbacks* pAllocator)
636 {
637 RADV_FROM_HANDLE(radv_instance, instance, _instance);
638
639 if (!instance)
640 return;
641
642 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
643 radv_physical_device_finish(instance->physicalDevices + i);
644 }
645
646 VG(VALGRIND_DESTROY_MEMPOOL(instance));
647
648 glsl_type_singleton_decref();
649 _mesa_locale_fini();
650
651 driDestroyOptionCache(&instance->dri_options);
652 driDestroyOptionInfo(&instance->available_dri_options);
653
654 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
655
656 vk_free(&instance->alloc, instance);
657 }
658
659 static VkResult
660 radv_enumerate_devices(struct radv_instance *instance)
661 {
662 /* TODO: Check for more devices ? */
663 drmDevicePtr devices[8];
664 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
665 int max_devices;
666
667 instance->physicalDeviceCount = 0;
668
669 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
670
671 if (instance->debug_flags & RADV_DEBUG_STARTUP)
672 radv_logi("Found %d drm nodes", max_devices);
673
674 if (max_devices < 1)
675 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
676
677 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
678 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
679 devices[i]->bustype == DRM_BUS_PCI &&
680 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
681
682 result = radv_physical_device_init(instance->physicalDevices +
683 instance->physicalDeviceCount,
684 instance,
685 devices[i]);
686 if (result == VK_SUCCESS)
687 ++instance->physicalDeviceCount;
688 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
689 break;
690 }
691 }
692 drmFreeDevices(devices, max_devices);
693
694 return result;
695 }
696
697 VkResult radv_EnumeratePhysicalDevices(
698 VkInstance _instance,
699 uint32_t* pPhysicalDeviceCount,
700 VkPhysicalDevice* pPhysicalDevices)
701 {
702 RADV_FROM_HANDLE(radv_instance, instance, _instance);
703 VkResult result;
704
705 if (instance->physicalDeviceCount < 0) {
706 result = radv_enumerate_devices(instance);
707 if (result != VK_SUCCESS &&
708 result != VK_ERROR_INCOMPATIBLE_DRIVER)
709 return result;
710 }
711
712 if (!pPhysicalDevices) {
713 *pPhysicalDeviceCount = instance->physicalDeviceCount;
714 } else {
715 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
716 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
717 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
718 }
719
720 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
721 : VK_SUCCESS;
722 }
723
724 VkResult radv_EnumeratePhysicalDeviceGroups(
725 VkInstance _instance,
726 uint32_t* pPhysicalDeviceGroupCount,
727 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
728 {
729 RADV_FROM_HANDLE(radv_instance, instance, _instance);
730 VkResult result;
731
732 if (instance->physicalDeviceCount < 0) {
733 result = radv_enumerate_devices(instance);
734 if (result != VK_SUCCESS &&
735 result != VK_ERROR_INCOMPATIBLE_DRIVER)
736 return result;
737 }
738
739 if (!pPhysicalDeviceGroupProperties) {
740 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
741 } else {
742 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
743 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
744 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
745 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
746 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
747 }
748 }
749 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
750 : VK_SUCCESS;
751 }
752
753 void radv_GetPhysicalDeviceFeatures(
754 VkPhysicalDevice physicalDevice,
755 VkPhysicalDeviceFeatures* pFeatures)
756 {
757 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
758 memset(pFeatures, 0, sizeof(*pFeatures));
759
760 *pFeatures = (VkPhysicalDeviceFeatures) {
761 .robustBufferAccess = true,
762 .fullDrawIndexUint32 = true,
763 .imageCubeArray = true,
764 .independentBlend = true,
765 .geometryShader = pdevice->rad_info.chip_class < GFX10,
766 .tessellationShader = pdevice->rad_info.chip_class < GFX10,
767 .sampleRateShading = true,
768 .dualSrcBlend = true,
769 .logicOp = true,
770 .multiDrawIndirect = true,
771 .drawIndirectFirstInstance = true,
772 .depthClamp = true,
773 .depthBiasClamp = true,
774 .fillModeNonSolid = true,
775 .depthBounds = true,
776 .wideLines = true,
777 .largePoints = true,
778 .alphaToOne = true,
779 .multiViewport = true,
780 .samplerAnisotropy = true,
781 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
782 .textureCompressionASTC_LDR = false,
783 .textureCompressionBC = true,
784 .occlusionQueryPrecise = true,
785 .pipelineStatisticsQuery = true,
786 .vertexPipelineStoresAndAtomics = true,
787 .fragmentStoresAndAtomics = true,
788 .shaderTessellationAndGeometryPointSize = true,
789 .shaderImageGatherExtended = true,
790 .shaderStorageImageExtendedFormats = true,
791 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
792 .shaderUniformBufferArrayDynamicIndexing = true,
793 .shaderSampledImageArrayDynamicIndexing = true,
794 .shaderStorageBufferArrayDynamicIndexing = true,
795 .shaderStorageImageArrayDynamicIndexing = true,
796 .shaderStorageImageReadWithoutFormat = true,
797 .shaderStorageImageWriteWithoutFormat = true,
798 .shaderClipDistance = true,
799 .shaderCullDistance = true,
800 .shaderFloat64 = true,
801 .shaderInt64 = true,
802 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
803 .sparseBinding = true,
804 .variableMultisampleRate = true,
805 .inheritedQueries = true,
806 };
807 }
808
809 void radv_GetPhysicalDeviceFeatures2(
810 VkPhysicalDevice physicalDevice,
811 VkPhysicalDeviceFeatures2 *pFeatures)
812 {
813 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
814 vk_foreach_struct(ext, pFeatures->pNext) {
815 switch (ext->sType) {
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
817 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
818 features->variablePointersStorageBuffer = true;
819 features->variablePointers = true;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
823 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
824 features->multiview = true;
825 features->multiviewGeometryShader = true;
826 features->multiviewTessellationShader = true;
827 break;
828 }
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
830 VkPhysicalDeviceShaderDrawParametersFeatures *features =
831 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
832 features->shaderDrawParameters = true;
833 break;
834 }
835 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
836 VkPhysicalDeviceProtectedMemoryFeatures *features =
837 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
838 features->protectedMemory = false;
839 break;
840 }
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
842 VkPhysicalDevice16BitStorageFeatures *features =
843 (VkPhysicalDevice16BitStorageFeatures*)ext;
844 bool enabled = pdevice->rad_info.chip_class >= GFX8;
845 features->storageBuffer16BitAccess = enabled;
846 features->uniformAndStorageBuffer16BitAccess = enabled;
847 features->storagePushConstant16 = enabled;
848 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
852 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
853 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
854 features->samplerYcbcrConversion = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
858 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
859 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
860 features->shaderInputAttachmentArrayDynamicIndexing = true;
861 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
862 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
863 features->shaderUniformBufferArrayNonUniformIndexing = true;
864 features->shaderSampledImageArrayNonUniformIndexing = true;
865 features->shaderStorageBufferArrayNonUniformIndexing = true;
866 features->shaderStorageImageArrayNonUniformIndexing = true;
867 features->shaderInputAttachmentArrayNonUniformIndexing = true;
868 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
869 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
870 features->descriptorBindingUniformBufferUpdateAfterBind = true;
871 features->descriptorBindingSampledImageUpdateAfterBind = true;
872 features->descriptorBindingStorageImageUpdateAfterBind = true;
873 features->descriptorBindingStorageBufferUpdateAfterBind = true;
874 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
875 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
876 features->descriptorBindingUpdateUnusedWhilePending = true;
877 features->descriptorBindingPartiallyBound = true;
878 features->descriptorBindingVariableDescriptorCount = true;
879 features->runtimeDescriptorArray = true;
880 break;
881 }
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
883 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
884 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
885 features->conditionalRendering = true;
886 features->inheritedConditionalRendering = false;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
890 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
891 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
892 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
893 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
897 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
898 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
899 features->transformFeedback = true;
900 features->geometryStreams = true;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
904 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
905 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
906 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
910 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
911 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
912 features->memoryPriority = VK_TRUE;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
916 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
917 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
918 features->bufferDeviceAddress = true;
919 features->bufferDeviceAddressCaptureReplay = false;
920 features->bufferDeviceAddressMultiDevice = false;
921 break;
922 }
923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
924 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
925 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
926 features->depthClipEnable = true;
927 break;
928 }
929 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
930 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
931 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
932 features->hostQueryReset = true;
933 break;
934 }
935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
936 VkPhysicalDevice8BitStorageFeaturesKHR *features =
937 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
938 bool enabled = pdevice->rad_info.chip_class >= GFX8;
939 features->storageBuffer8BitAccess = enabled;
940 features->uniformAndStorageBuffer8BitAccess = enabled;
941 features->storagePushConstant8 = enabled;
942 break;
943 }
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
945 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
946 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
947 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
948 features->shaderInt8 = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
952 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
953 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
954 /* TODO: Enable this once the driver supports 64-bit
955 * compare&swap atomic operations.
956 */
957 features->shaderBufferInt64Atomics = false;
958 features->shaderSharedInt64Atomics = false;
959 break;
960 }
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
962 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
963 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
964
965 features->inlineUniformBlock = true;
966 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
970 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
971 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
972 features->computeDerivativeGroupQuads = false;
973 features->computeDerivativeGroupLinear = true;
974 break;
975 }
976 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
977 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
978 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
979 features->ycbcrImageArrays = true;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
983 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
984 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
985 features->uniformBufferStandardLayout = true;
986 break;
987 }
988 default:
989 break;
990 }
991 }
992 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
993 }
994
995 void radv_GetPhysicalDeviceProperties(
996 VkPhysicalDevice physicalDevice,
997 VkPhysicalDeviceProperties* pProperties)
998 {
999 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1000 VkSampleCountFlags sample_counts = 0xf;
1001
1002 /* make sure that the entire descriptor set is addressable with a signed
1003 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1004 * be at most 2 GiB. the combined image & samples object count as one of
1005 * both. This limit is for the pipeline layout, not for the set layout, but
1006 * there is no set limit, so we just set a pipeline limit. I don't think
1007 * any app is going to hit this soon. */
1008 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1009 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1010 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1011 32 /* sampler, largest when combined with image */ +
1012 64 /* sampled image */ +
1013 64 /* storage image */);
1014
1015 VkPhysicalDeviceLimits limits = {
1016 .maxImageDimension1D = (1 << 14),
1017 .maxImageDimension2D = (1 << 14),
1018 .maxImageDimension3D = (1 << 11),
1019 .maxImageDimensionCube = (1 << 14),
1020 .maxImageArrayLayers = (1 << 11),
1021 .maxTexelBufferElements = 128 * 1024 * 1024,
1022 .maxUniformBufferRange = UINT32_MAX,
1023 .maxStorageBufferRange = UINT32_MAX,
1024 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1025 .maxMemoryAllocationCount = UINT32_MAX,
1026 .maxSamplerAllocationCount = 64 * 1024,
1027 .bufferImageGranularity = 64, /* A cache line */
1028 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1029 .maxBoundDescriptorSets = MAX_SETS,
1030 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1031 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1032 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1033 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1034 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1035 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1036 .maxPerStageResources = max_descriptor_set_size,
1037 .maxDescriptorSetSamplers = max_descriptor_set_size,
1038 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1039 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1040 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1041 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1042 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1043 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1044 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1045 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1046 .maxVertexInputBindings = MAX_VBS,
1047 .maxVertexInputAttributeOffset = 2047,
1048 .maxVertexInputBindingStride = 2048,
1049 .maxVertexOutputComponents = 128,
1050 .maxTessellationGenerationLevel = 64,
1051 .maxTessellationPatchSize = 32,
1052 .maxTessellationControlPerVertexInputComponents = 128,
1053 .maxTessellationControlPerVertexOutputComponents = 128,
1054 .maxTessellationControlPerPatchOutputComponents = 120,
1055 .maxTessellationControlTotalOutputComponents = 4096,
1056 .maxTessellationEvaluationInputComponents = 128,
1057 .maxTessellationEvaluationOutputComponents = 128,
1058 .maxGeometryShaderInvocations = 127,
1059 .maxGeometryInputComponents = 64,
1060 .maxGeometryOutputComponents = 128,
1061 .maxGeometryOutputVertices = 256,
1062 .maxGeometryTotalOutputComponents = 1024,
1063 .maxFragmentInputComponents = 128,
1064 .maxFragmentOutputAttachments = 8,
1065 .maxFragmentDualSrcAttachments = 1,
1066 .maxFragmentCombinedOutputResources = 8,
1067 .maxComputeSharedMemorySize = 32768,
1068 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1069 .maxComputeWorkGroupInvocations = 2048,
1070 .maxComputeWorkGroupSize = {
1071 2048,
1072 2048,
1073 2048
1074 },
1075 .subPixelPrecisionBits = 8,
1076 .subTexelPrecisionBits = 8,
1077 .mipmapPrecisionBits = 8,
1078 .maxDrawIndexedIndexValue = UINT32_MAX,
1079 .maxDrawIndirectCount = UINT32_MAX,
1080 .maxSamplerLodBias = 16,
1081 .maxSamplerAnisotropy = 16,
1082 .maxViewports = MAX_VIEWPORTS,
1083 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1084 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1085 .viewportSubPixelBits = 8,
1086 .minMemoryMapAlignment = 4096, /* A page */
1087 .minTexelBufferOffsetAlignment = 1,
1088 .minUniformBufferOffsetAlignment = 4,
1089 .minStorageBufferOffsetAlignment = 4,
1090 .minTexelOffset = -32,
1091 .maxTexelOffset = 31,
1092 .minTexelGatherOffset = -32,
1093 .maxTexelGatherOffset = 31,
1094 .minInterpolationOffset = -2,
1095 .maxInterpolationOffset = 2,
1096 .subPixelInterpolationOffsetBits = 8,
1097 .maxFramebufferWidth = (1 << 14),
1098 .maxFramebufferHeight = (1 << 14),
1099 .maxFramebufferLayers = (1 << 10),
1100 .framebufferColorSampleCounts = sample_counts,
1101 .framebufferDepthSampleCounts = sample_counts,
1102 .framebufferStencilSampleCounts = sample_counts,
1103 .framebufferNoAttachmentsSampleCounts = sample_counts,
1104 .maxColorAttachments = MAX_RTS,
1105 .sampledImageColorSampleCounts = sample_counts,
1106 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1107 .sampledImageDepthSampleCounts = sample_counts,
1108 .sampledImageStencilSampleCounts = sample_counts,
1109 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1110 .maxSampleMaskWords = 1,
1111 .timestampComputeAndGraphics = true,
1112 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1113 .maxClipDistances = 8,
1114 .maxCullDistances = 8,
1115 .maxCombinedClipAndCullDistances = 8,
1116 .discreteQueuePriorities = 2,
1117 .pointSizeRange = { 0.0, 8192.0 },
1118 .lineWidthRange = { 0.0, 7.9921875 },
1119 .pointSizeGranularity = (1.0 / 8.0),
1120 .lineWidthGranularity = (1.0 / 128.0),
1121 .strictLines = false, /* FINISHME */
1122 .standardSampleLocations = true,
1123 .optimalBufferCopyOffsetAlignment = 128,
1124 .optimalBufferCopyRowPitchAlignment = 128,
1125 .nonCoherentAtomSize = 64,
1126 };
1127
1128 *pProperties = (VkPhysicalDeviceProperties) {
1129 .apiVersion = radv_physical_device_api_version(pdevice),
1130 .driverVersion = vk_get_driver_version(),
1131 .vendorID = ATI_VENDOR_ID,
1132 .deviceID = pdevice->rad_info.pci_id,
1133 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1134 .limits = limits,
1135 .sparseProperties = {0},
1136 };
1137
1138 strcpy(pProperties->deviceName, pdevice->name);
1139 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1140 }
1141
1142 void radv_GetPhysicalDeviceProperties2(
1143 VkPhysicalDevice physicalDevice,
1144 VkPhysicalDeviceProperties2 *pProperties)
1145 {
1146 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1147 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1148
1149 vk_foreach_struct(ext, pProperties->pNext) {
1150 switch (ext->sType) {
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1152 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1153 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1154 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1158 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1159 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1160 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1161 properties->deviceLUIDValid = false;
1162 break;
1163 }
1164 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1165 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1166 properties->maxMultiviewViewCount = MAX_VIEWS;
1167 properties->maxMultiviewInstanceIndex = INT_MAX;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1171 VkPhysicalDevicePointClippingProperties *properties =
1172 (VkPhysicalDevicePointClippingProperties*)ext;
1173 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1177 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1178 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1179 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1183 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1184 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1185 properties->minImportedHostPointerAlignment = 4096;
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1189 VkPhysicalDeviceSubgroupProperties *properties =
1190 (VkPhysicalDeviceSubgroupProperties*)ext;
1191 properties->subgroupSize = 64;
1192 properties->supportedStages = VK_SHADER_STAGE_ALL;
1193 properties->supportedOperations =
1194 VK_SUBGROUP_FEATURE_BASIC_BIT |
1195 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1196 VK_SUBGROUP_FEATURE_QUAD_BIT |
1197 VK_SUBGROUP_FEATURE_VOTE_BIT;
1198 if (pdevice->rad_info.chip_class >= GFX8) {
1199 properties->supportedOperations |=
1200 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1201 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1202 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1203 }
1204 properties->quadOperationsInAllStages = true;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1208 VkPhysicalDeviceMaintenance3Properties *properties =
1209 (VkPhysicalDeviceMaintenance3Properties*)ext;
1210 /* Make sure everything is addressable by a signed 32-bit int, and
1211 * our largest descriptors are 96 bytes. */
1212 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1213 /* Our buffer size fields allow only this much */
1214 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1218 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1219 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1220 /* GFX6-8 only support single channel min/max filter. */
1221 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1222 properties->filterMinmaxSingleComponentFormats = true;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1226 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1227 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1228
1229 /* Shader engines. */
1230 properties->shaderEngineCount =
1231 pdevice->rad_info.max_se;
1232 properties->shaderArraysPerEngineCount =
1233 pdevice->rad_info.max_sh_per_se;
1234 properties->computeUnitsPerShaderArray =
1235 pdevice->rad_info.num_good_cu_per_sh;
1236 properties->simdPerComputeUnit = 4;
1237 properties->wavefrontsPerSimd =
1238 pdevice->rad_info.family == CHIP_TONGA ||
1239 pdevice->rad_info.family == CHIP_ICELAND ||
1240 pdevice->rad_info.family == CHIP_POLARIS10 ||
1241 pdevice->rad_info.family == CHIP_POLARIS11 ||
1242 pdevice->rad_info.family == CHIP_POLARIS12 ||
1243 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1244 properties->wavefrontSize = 64;
1245
1246 /* SGPR. */
1247 properties->sgprsPerSimd =
1248 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1249 properties->minSgprAllocation =
1250 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1251 properties->maxSgprAllocation =
1252 pdevice->rad_info.family == CHIP_TONGA ||
1253 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1254 properties->sgprAllocationGranularity =
1255 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1256
1257 /* VGPR. */
1258 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1259 properties->minVgprAllocation = 4;
1260 properties->maxVgprAllocation = 256;
1261 properties->vgprAllocationGranularity = 4;
1262 break;
1263 }
1264 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1265 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1266 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1267 properties->maxVertexAttribDivisor = UINT32_MAX;
1268 break;
1269 }
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1271 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1272 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1273 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1274 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1275 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1276 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1277 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1278 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1279 properties->robustBufferAccessUpdateAfterBind = false;
1280 properties->quadDivergentImplicitLod = false;
1281
1282 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1283 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1284 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1285 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1286 32 /* sampler, largest when combined with image */ +
1287 64 /* sampled image */ +
1288 64 /* storage image */);
1289 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1290 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1291 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1292 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1295 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1296 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1297 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1299 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1301 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1302 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1303 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1304 break;
1305 }
1306 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1307 VkPhysicalDeviceProtectedMemoryProperties *properties =
1308 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1309 properties->protectedNoFault = false;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1313 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1314 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1315 properties->primitiveOverestimationSize = 0;
1316 properties->maxExtraPrimitiveOverestimationSize = 0;
1317 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1318 properties->primitiveUnderestimation = VK_FALSE;
1319 properties->conservativePointAndLineRasterization = VK_FALSE;
1320 properties->degenerateTrianglesRasterized = VK_FALSE;
1321 properties->degenerateLinesRasterized = VK_FALSE;
1322 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1323 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1324 break;
1325 }
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1327 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1328 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1329 properties->pciDomain = pdevice->bus_info.domain;
1330 properties->pciBus = pdevice->bus_info.bus;
1331 properties->pciDevice = pdevice->bus_info.dev;
1332 properties->pciFunction = pdevice->bus_info.func;
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1336 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1337 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1338
1339 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1340 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1341 strcpy(driver_props->driverName, "radv");
1342
1343 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1344 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1345 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1346 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1347
1348 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1349 .major = 1,
1350 .minor = 1,
1351 .subminor = 2,
1352 .patch = 0,
1353 };
1354 break;
1355 }
1356 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1357 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1358 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1359 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1360 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1361 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1362 properties->maxTransformFeedbackStreamDataSize = 512;
1363 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1364 properties->maxTransformFeedbackBufferDataStride = 512;
1365 properties->transformFeedbackQueries = true;
1366 properties->transformFeedbackStreamsLinesTriangles = true;
1367 properties->transformFeedbackRasterizationStreamSelect = false;
1368 properties->transformFeedbackDraw = true;
1369 break;
1370 }
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1372 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1373 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1374
1375 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1376 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1377 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1378 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1379 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1380 break;
1381 }
1382 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1383 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1384 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1385 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1386 VK_SAMPLE_COUNT_4_BIT |
1387 VK_SAMPLE_COUNT_8_BIT;
1388 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1389 properties->sampleLocationCoordinateRange[0] = 0.0f;
1390 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1391 properties->sampleLocationSubPixelBits = 4;
1392 properties->variableSampleLocations = VK_FALSE;
1393 break;
1394 }
1395 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1396 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1397 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1398
1399 /* We support all of the depth resolve modes */
1400 properties->supportedDepthResolveModes =
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1402 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1403 VK_RESOLVE_MODE_MIN_BIT_KHR |
1404 VK_RESOLVE_MODE_MAX_BIT_KHR;
1405
1406 /* Average doesn't make sense for stencil so we don't support that */
1407 properties->supportedStencilResolveModes =
1408 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1409 VK_RESOLVE_MODE_MIN_BIT_KHR |
1410 VK_RESOLVE_MODE_MAX_BIT_KHR;
1411
1412 properties->independentResolveNone = VK_TRUE;
1413 properties->independentResolve = VK_TRUE;
1414 break;
1415 }
1416 default:
1417 break;
1418 }
1419 }
1420 }
1421
1422 static void radv_get_physical_device_queue_family_properties(
1423 struct radv_physical_device* pdevice,
1424 uint32_t* pCount,
1425 VkQueueFamilyProperties** pQueueFamilyProperties)
1426 {
1427 int num_queue_families = 1;
1428 int idx;
1429 if (pdevice->rad_info.num_compute_rings > 0 &&
1430 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1431 num_queue_families++;
1432
1433 if (pQueueFamilyProperties == NULL) {
1434 *pCount = num_queue_families;
1435 return;
1436 }
1437
1438 if (!*pCount)
1439 return;
1440
1441 idx = 0;
1442 if (*pCount >= 1) {
1443 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1444 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1445 VK_QUEUE_COMPUTE_BIT |
1446 VK_QUEUE_TRANSFER_BIT |
1447 VK_QUEUE_SPARSE_BINDING_BIT,
1448 .queueCount = 1,
1449 .timestampValidBits = 64,
1450 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1451 };
1452 idx++;
1453 }
1454
1455 if (pdevice->rad_info.num_compute_rings > 0 &&
1456 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1457 if (*pCount > idx) {
1458 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1459 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1460 VK_QUEUE_TRANSFER_BIT |
1461 VK_QUEUE_SPARSE_BINDING_BIT,
1462 .queueCount = pdevice->rad_info.num_compute_rings,
1463 .timestampValidBits = 64,
1464 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1465 };
1466 idx++;
1467 }
1468 }
1469 *pCount = idx;
1470 }
1471
1472 void radv_GetPhysicalDeviceQueueFamilyProperties(
1473 VkPhysicalDevice physicalDevice,
1474 uint32_t* pCount,
1475 VkQueueFamilyProperties* pQueueFamilyProperties)
1476 {
1477 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1478 if (!pQueueFamilyProperties) {
1479 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1480 return;
1481 }
1482 VkQueueFamilyProperties *properties[] = {
1483 pQueueFamilyProperties + 0,
1484 pQueueFamilyProperties + 1,
1485 pQueueFamilyProperties + 2,
1486 };
1487 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1488 assert(*pCount <= 3);
1489 }
1490
1491 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1492 VkPhysicalDevice physicalDevice,
1493 uint32_t* pCount,
1494 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1495 {
1496 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1497 if (!pQueueFamilyProperties) {
1498 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1499 return;
1500 }
1501 VkQueueFamilyProperties *properties[] = {
1502 &pQueueFamilyProperties[0].queueFamilyProperties,
1503 &pQueueFamilyProperties[1].queueFamilyProperties,
1504 &pQueueFamilyProperties[2].queueFamilyProperties,
1505 };
1506 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1507 assert(*pCount <= 3);
1508 }
1509
1510 void radv_GetPhysicalDeviceMemoryProperties(
1511 VkPhysicalDevice physicalDevice,
1512 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1513 {
1514 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1515
1516 *pMemoryProperties = physical_device->memory_properties;
1517 }
1518
1519 static void
1520 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1521 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1522 {
1523 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1524 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1525 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1526 uint64_t vram_size = radv_get_vram_size(device);
1527 uint64_t gtt_size = device->rad_info.gart_size;
1528 uint64_t heap_budget, heap_usage;
1529
1530 /* For all memory heaps, the computation of budget is as follow:
1531 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1532 *
1533 * The Vulkan spec 1.1.97 says that the budget should include any
1534 * currently allocated device memory.
1535 *
1536 * Note that the application heap usages are not really accurate (eg.
1537 * in presence of shared buffers).
1538 */
1539 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1540 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1541
1542 switch (device->mem_type_indices[i]) {
1543 case RADV_MEM_TYPE_VRAM:
1544 heap_usage = device->ws->query_value(device->ws,
1545 RADEON_ALLOCATED_VRAM);
1546
1547 heap_budget = vram_size -
1548 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1549 heap_usage;
1550
1551 memoryBudget->heapBudget[heap_index] = heap_budget;
1552 memoryBudget->heapUsage[heap_index] = heap_usage;
1553 break;
1554 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1555 heap_usage = device->ws->query_value(device->ws,
1556 RADEON_ALLOCATED_VRAM_VIS);
1557
1558 heap_budget = visible_vram_size -
1559 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1560 heap_usage;
1561
1562 memoryBudget->heapBudget[heap_index] = heap_budget;
1563 memoryBudget->heapUsage[heap_index] = heap_usage;
1564 break;
1565 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1566 heap_usage = device->ws->query_value(device->ws,
1567 RADEON_ALLOCATED_GTT);
1568
1569 heap_budget = gtt_size -
1570 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1571 heap_usage;
1572
1573 memoryBudget->heapBudget[heap_index] = heap_budget;
1574 memoryBudget->heapUsage[heap_index] = heap_usage;
1575 break;
1576 default:
1577 break;
1578 }
1579 }
1580
1581 /* The heapBudget and heapUsage values must be zero for array elements
1582 * greater than or equal to
1583 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1584 */
1585 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1586 memoryBudget->heapBudget[i] = 0;
1587 memoryBudget->heapUsage[i] = 0;
1588 }
1589 }
1590
1591 void radv_GetPhysicalDeviceMemoryProperties2(
1592 VkPhysicalDevice physicalDevice,
1593 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1594 {
1595 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1596 &pMemoryProperties->memoryProperties);
1597
1598 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1599 vk_find_struct(pMemoryProperties->pNext,
1600 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1601 if (memory_budget)
1602 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1603 }
1604
1605 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1606 VkDevice _device,
1607 VkExternalMemoryHandleTypeFlagBits handleType,
1608 const void *pHostPointer,
1609 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612
1613 switch (handleType)
1614 {
1615 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1616 const struct radv_physical_device *physical_device = device->physical_device;
1617 uint32_t memoryTypeBits = 0;
1618 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1619 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1620 memoryTypeBits = (1 << i);
1621 break;
1622 }
1623 }
1624 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1625 return VK_SUCCESS;
1626 }
1627 default:
1628 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1629 }
1630 }
1631
1632 static enum radeon_ctx_priority
1633 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1634 {
1635 /* Default to MEDIUM when a specific global priority isn't requested */
1636 if (!pObj)
1637 return RADEON_CTX_PRIORITY_MEDIUM;
1638
1639 switch(pObj->globalPriority) {
1640 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1641 return RADEON_CTX_PRIORITY_REALTIME;
1642 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1643 return RADEON_CTX_PRIORITY_HIGH;
1644 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1645 return RADEON_CTX_PRIORITY_MEDIUM;
1646 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1647 return RADEON_CTX_PRIORITY_LOW;
1648 default:
1649 unreachable("Illegal global priority value");
1650 return RADEON_CTX_PRIORITY_INVALID;
1651 }
1652 }
1653
1654 static int
1655 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1656 uint32_t queue_family_index, int idx,
1657 VkDeviceQueueCreateFlags flags,
1658 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1659 {
1660 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1661 queue->device = device;
1662 queue->queue_family_index = queue_family_index;
1663 queue->queue_idx = idx;
1664 queue->priority = radv_get_queue_global_priority(global_priority);
1665 queue->flags = flags;
1666
1667 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1668 if (!queue->hw_ctx)
1669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1670
1671 return VK_SUCCESS;
1672 }
1673
1674 static void
1675 radv_queue_finish(struct radv_queue *queue)
1676 {
1677 if (queue->hw_ctx)
1678 queue->device->ws->ctx_destroy(queue->hw_ctx);
1679
1680 if (queue->initial_full_flush_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1682 if (queue->initial_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1684 if (queue->continue_preamble_cs)
1685 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1686 if (queue->descriptor_bo)
1687 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1688 if (queue->scratch_bo)
1689 queue->device->ws->buffer_destroy(queue->scratch_bo);
1690 if (queue->esgs_ring_bo)
1691 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1692 if (queue->gsvs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1694 if (queue->tess_rings_bo)
1695 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1696 if (queue->compute_scratch_bo)
1697 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1698 }
1699
1700 static void
1701 radv_bo_list_init(struct radv_bo_list *bo_list)
1702 {
1703 pthread_mutex_init(&bo_list->mutex, NULL);
1704 bo_list->list.count = bo_list->capacity = 0;
1705 bo_list->list.bos = NULL;
1706 }
1707
1708 static void
1709 radv_bo_list_finish(struct radv_bo_list *bo_list)
1710 {
1711 free(bo_list->list.bos);
1712 pthread_mutex_destroy(&bo_list->mutex);
1713 }
1714
1715 static VkResult radv_bo_list_add(struct radv_device *device,
1716 struct radeon_winsys_bo *bo)
1717 {
1718 struct radv_bo_list *bo_list = &device->bo_list;
1719
1720 if (bo->is_local)
1721 return VK_SUCCESS;
1722
1723 if (unlikely(!device->use_global_bo_list))
1724 return VK_SUCCESS;
1725
1726 pthread_mutex_lock(&bo_list->mutex);
1727 if (bo_list->list.count == bo_list->capacity) {
1728 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1729 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1730
1731 if (!data) {
1732 pthread_mutex_unlock(&bo_list->mutex);
1733 return VK_ERROR_OUT_OF_HOST_MEMORY;
1734 }
1735
1736 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1737 bo_list->capacity = capacity;
1738 }
1739
1740 bo_list->list.bos[bo_list->list.count++] = bo;
1741 pthread_mutex_unlock(&bo_list->mutex);
1742 return VK_SUCCESS;
1743 }
1744
1745 static void radv_bo_list_remove(struct radv_device *device,
1746 struct radeon_winsys_bo *bo)
1747 {
1748 struct radv_bo_list *bo_list = &device->bo_list;
1749
1750 if (bo->is_local)
1751 return;
1752
1753 if (unlikely(!device->use_global_bo_list))
1754 return;
1755
1756 pthread_mutex_lock(&bo_list->mutex);
1757 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1758 if (bo_list->list.bos[i] == bo) {
1759 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1760 --bo_list->list.count;
1761 break;
1762 }
1763 }
1764 pthread_mutex_unlock(&bo_list->mutex);
1765 }
1766
1767 static void
1768 radv_device_init_gs_info(struct radv_device *device)
1769 {
1770 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1771 device->physical_device->rad_info.family);
1772 }
1773
1774 static int radv_get_device_extension_index(const char *name)
1775 {
1776 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1777 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1778 return i;
1779 }
1780 return -1;
1781 }
1782
1783 static int
1784 radv_get_int_debug_option(const char *name, int default_value)
1785 {
1786 const char *str;
1787 int result;
1788
1789 str = getenv(name);
1790 if (!str) {
1791 result = default_value;
1792 } else {
1793 char *endptr;
1794
1795 result = strtol(str, &endptr, 0);
1796 if (str == endptr) {
1797 /* No digits founs. */
1798 result = default_value;
1799 }
1800 }
1801
1802 return result;
1803 }
1804
1805 VkResult radv_CreateDevice(
1806 VkPhysicalDevice physicalDevice,
1807 const VkDeviceCreateInfo* pCreateInfo,
1808 const VkAllocationCallbacks* pAllocator,
1809 VkDevice* pDevice)
1810 {
1811 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1812 VkResult result;
1813 struct radv_device *device;
1814
1815 bool keep_shader_info = false;
1816
1817 /* Check enabled features */
1818 if (pCreateInfo->pEnabledFeatures) {
1819 VkPhysicalDeviceFeatures supported_features;
1820 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1821 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1822 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1823 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1824 for (uint32_t i = 0; i < num_features; i++) {
1825 if (enabled_feature[i] && !supported_feature[i])
1826 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1827 }
1828 }
1829
1830 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1831 sizeof(*device), 8,
1832 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1833 if (!device)
1834 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1835
1836 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1837 device->instance = physical_device->instance;
1838 device->physical_device = physical_device;
1839
1840 device->ws = physical_device->ws;
1841 if (pAllocator)
1842 device->alloc = *pAllocator;
1843 else
1844 device->alloc = physical_device->instance->alloc;
1845
1846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1847 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1848 int index = radv_get_device_extension_index(ext_name);
1849 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1850 vk_free(&device->alloc, device);
1851 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1852 }
1853
1854 device->enabled_extensions.extensions[index] = true;
1855 }
1856
1857 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1858
1859 /* With update after bind we can't attach bo's to the command buffer
1860 * from the descriptor set anymore, so we have to use a global BO list.
1861 */
1862 device->use_global_bo_list =
1863 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1864 device->enabled_extensions.EXT_descriptor_indexing ||
1865 device->enabled_extensions.EXT_buffer_device_address;
1866
1867 mtx_init(&device->shader_slab_mutex, mtx_plain);
1868 list_inithead(&device->shader_slabs);
1869
1870 radv_bo_list_init(&device->bo_list);
1871
1872 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1873 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1874 uint32_t qfi = queue_create->queueFamilyIndex;
1875 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1876 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1877
1878 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1879
1880 device->queues[qfi] = vk_alloc(&device->alloc,
1881 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1882 if (!device->queues[qfi]) {
1883 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1884 goto fail;
1885 }
1886
1887 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1888
1889 device->queue_count[qfi] = queue_create->queueCount;
1890
1891 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1892 result = radv_queue_init(device, &device->queues[qfi][q],
1893 qfi, q, queue_create->flags,
1894 global_priority);
1895 if (result != VK_SUCCESS)
1896 goto fail;
1897 }
1898 }
1899
1900 /* TODO: Enable binning for GFX10. */
1901 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1902 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1903
1904 /* Disabled and not implemented for now. */
1905 device->dfsm_allowed = device->pbb_allowed &&
1906 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1907 device->physical_device->rad_info.family == CHIP_RAVEN2);
1908
1909 #ifdef ANDROID
1910 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1911 #endif
1912
1913 /* The maximum number of scratch waves. Scratch space isn't divided
1914 * evenly between CUs. The number is only a function of the number of CUs.
1915 * We can decrease the constant to decrease the scratch buffer size.
1916 *
1917 * sctx->scratch_waves must be >= the maximum possible size of
1918 * 1 threadgroup, so that the hw doesn't hang from being unable
1919 * to start any.
1920 *
1921 * The recommended value is 4 per CU at most. Higher numbers don't
1922 * bring much benefit, but they still occupy chip resources (think
1923 * async compute). I've seen ~2% performance difference between 4 and 32.
1924 */
1925 uint32_t max_threads_per_block = 2048;
1926 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1927 max_threads_per_block / 64);
1928
1929 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1930
1931 if (device->physical_device->rad_info.chip_class >= GFX7) {
1932 /* If the KMD allows it (there is a KMD hw register for it),
1933 * allow launching waves out-of-order.
1934 */
1935 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1936 }
1937
1938 radv_device_init_gs_info(device);
1939
1940 device->tess_offchip_block_dw_size =
1941 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1942 device->has_distributed_tess =
1943 device->physical_device->rad_info.chip_class >= GFX8 &&
1944 device->physical_device->rad_info.max_se >= 2;
1945
1946 if (getenv("RADV_TRACE_FILE")) {
1947 const char *filename = getenv("RADV_TRACE_FILE");
1948
1949 keep_shader_info = true;
1950
1951 if (!radv_init_trace(device))
1952 goto fail;
1953
1954 fprintf(stderr, "*****************************************************************************\n");
1955 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1956 fprintf(stderr, "*****************************************************************************\n");
1957
1958 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1959 radv_dump_enabled_options(device, stderr);
1960 }
1961
1962 device->keep_shader_info = keep_shader_info;
1963
1964 result = radv_device_init_meta(device);
1965 if (result != VK_SUCCESS)
1966 goto fail;
1967
1968 radv_device_init_msaa(device);
1969
1970 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1971 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1972 switch (family) {
1973 case RADV_QUEUE_GENERAL:
1974 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1975 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1976 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1977 break;
1978 case RADV_QUEUE_COMPUTE:
1979 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(device->empty_cs[family], 0);
1981 break;
1982 }
1983 device->ws->cs_finalize(device->empty_cs[family]);
1984 }
1985
1986 if (device->physical_device->rad_info.chip_class >= GFX7)
1987 cik_create_gfx_config(device);
1988
1989 VkPipelineCacheCreateInfo ci;
1990 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1991 ci.pNext = NULL;
1992 ci.flags = 0;
1993 ci.pInitialData = NULL;
1994 ci.initialDataSize = 0;
1995 VkPipelineCache pc;
1996 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1997 &ci, NULL, &pc);
1998 if (result != VK_SUCCESS)
1999 goto fail_meta;
2000
2001 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2002
2003 device->force_aniso =
2004 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2005 if (device->force_aniso >= 0) {
2006 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2007 1 << util_logbase2(device->force_aniso));
2008 }
2009
2010 *pDevice = radv_device_to_handle(device);
2011 return VK_SUCCESS;
2012
2013 fail_meta:
2014 radv_device_finish_meta(device);
2015 fail:
2016 radv_bo_list_finish(&device->bo_list);
2017
2018 if (device->trace_bo)
2019 device->ws->buffer_destroy(device->trace_bo);
2020
2021 if (device->gfx_init)
2022 device->ws->buffer_destroy(device->gfx_init);
2023
2024 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2025 for (unsigned q = 0; q < device->queue_count[i]; q++)
2026 radv_queue_finish(&device->queues[i][q]);
2027 if (device->queue_count[i])
2028 vk_free(&device->alloc, device->queues[i]);
2029 }
2030
2031 vk_free(&device->alloc, device);
2032 return result;
2033 }
2034
2035 void radv_DestroyDevice(
2036 VkDevice _device,
2037 const VkAllocationCallbacks* pAllocator)
2038 {
2039 RADV_FROM_HANDLE(radv_device, device, _device);
2040
2041 if (!device)
2042 return;
2043
2044 if (device->trace_bo)
2045 device->ws->buffer_destroy(device->trace_bo);
2046
2047 if (device->gfx_init)
2048 device->ws->buffer_destroy(device->gfx_init);
2049
2050 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2051 for (unsigned q = 0; q < device->queue_count[i]; q++)
2052 radv_queue_finish(&device->queues[i][q]);
2053 if (device->queue_count[i])
2054 vk_free(&device->alloc, device->queues[i]);
2055 if (device->empty_cs[i])
2056 device->ws->cs_destroy(device->empty_cs[i]);
2057 }
2058 radv_device_finish_meta(device);
2059
2060 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2061 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2062
2063 radv_destroy_shader_slabs(device);
2064
2065 radv_bo_list_finish(&device->bo_list);
2066 vk_free(&device->alloc, device);
2067 }
2068
2069 VkResult radv_EnumerateInstanceLayerProperties(
2070 uint32_t* pPropertyCount,
2071 VkLayerProperties* pProperties)
2072 {
2073 if (pProperties == NULL) {
2074 *pPropertyCount = 0;
2075 return VK_SUCCESS;
2076 }
2077
2078 /* None supported at this time */
2079 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2080 }
2081
2082 VkResult radv_EnumerateDeviceLayerProperties(
2083 VkPhysicalDevice physicalDevice,
2084 uint32_t* pPropertyCount,
2085 VkLayerProperties* pProperties)
2086 {
2087 if (pProperties == NULL) {
2088 *pPropertyCount = 0;
2089 return VK_SUCCESS;
2090 }
2091
2092 /* None supported at this time */
2093 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2094 }
2095
2096 void radv_GetDeviceQueue2(
2097 VkDevice _device,
2098 const VkDeviceQueueInfo2* pQueueInfo,
2099 VkQueue* pQueue)
2100 {
2101 RADV_FROM_HANDLE(radv_device, device, _device);
2102 struct radv_queue *queue;
2103
2104 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2105 if (pQueueInfo->flags != queue->flags) {
2106 /* From the Vulkan 1.1.70 spec:
2107 *
2108 * "The queue returned by vkGetDeviceQueue2 must have the same
2109 * flags value from this structure as that used at device
2110 * creation time in a VkDeviceQueueCreateInfo instance. If no
2111 * matching flags were specified at device creation time then
2112 * pQueue will return VK_NULL_HANDLE."
2113 */
2114 *pQueue = VK_NULL_HANDLE;
2115 return;
2116 }
2117
2118 *pQueue = radv_queue_to_handle(queue);
2119 }
2120
2121 void radv_GetDeviceQueue(
2122 VkDevice _device,
2123 uint32_t queueFamilyIndex,
2124 uint32_t queueIndex,
2125 VkQueue* pQueue)
2126 {
2127 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2128 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2129 .queueFamilyIndex = queueFamilyIndex,
2130 .queueIndex = queueIndex
2131 };
2132
2133 radv_GetDeviceQueue2(_device, &info, pQueue);
2134 }
2135
2136 static void
2137 fill_geom_tess_rings(struct radv_queue *queue,
2138 uint32_t *map,
2139 bool add_sample_positions,
2140 uint32_t esgs_ring_size,
2141 struct radeon_winsys_bo *esgs_ring_bo,
2142 uint32_t gsvs_ring_size,
2143 struct radeon_winsys_bo *gsvs_ring_bo,
2144 uint32_t tess_factor_ring_size,
2145 uint32_t tess_offchip_ring_offset,
2146 uint32_t tess_offchip_ring_size,
2147 struct radeon_winsys_bo *tess_rings_bo)
2148 {
2149 uint32_t *desc = &map[4];
2150
2151 if (esgs_ring_bo) {
2152 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2153
2154 /* stride 0, num records - size, add tid, swizzle, elsize4,
2155 index stride 64 */
2156 desc[0] = esgs_va;
2157 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2158 S_008F04_STRIDE(0) |
2159 S_008F04_SWIZZLE_ENABLE(true);
2160 desc[2] = esgs_ring_size;
2161 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2165 S_008F0C_ELEMENT_SIZE(1) |
2166 S_008F0C_INDEX_STRIDE(3) |
2167 S_008F0C_ADD_TID_ENABLE(true);
2168
2169 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2170 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2171 S_008F0C_OOB_SELECT(2) |
2172 S_008F0C_RESOURCE_LEVEL(1);
2173 } else {
2174 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2176 }
2177
2178 /* GS entry for ES->GS ring */
2179 /* stride 0, num records - size, elsize0,
2180 index stride 0 */
2181 desc[4] = esgs_va;
2182 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2183 S_008F04_STRIDE(0) |
2184 S_008F04_SWIZZLE_ENABLE(false);
2185 desc[6] = esgs_ring_size;
2186 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2187 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2188 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2189 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2190 S_008F0C_ELEMENT_SIZE(0) |
2191 S_008F0C_INDEX_STRIDE(0) |
2192 S_008F0C_ADD_TID_ENABLE(false);
2193
2194 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2195 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2196 S_008F0C_OOB_SELECT(2) |
2197 S_008F0C_RESOURCE_LEVEL(1);
2198 } else {
2199 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2201 }
2202 }
2203
2204 desc += 8;
2205
2206 if (gsvs_ring_bo) {
2207 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2208
2209 /* VS entry for GS->VS ring */
2210 /* stride 0, num records - size, elsize0,
2211 index stride 0 */
2212 desc[0] = gsvs_va;
2213 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2214 S_008F04_STRIDE(0) |
2215 S_008F04_SWIZZLE_ENABLE(false);
2216 desc[2] = gsvs_ring_size;
2217 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2218 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2219 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2220 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2221 S_008F0C_ELEMENT_SIZE(0) |
2222 S_008F0C_INDEX_STRIDE(0) |
2223 S_008F0C_ADD_TID_ENABLE(false);
2224
2225 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2226 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2227 S_008F0C_OOB_SELECT(2) |
2228 S_008F0C_RESOURCE_LEVEL(1);
2229 } else {
2230 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2232 }
2233
2234 /* stride gsvs_itemsize, num records 64
2235 elsize 4, index stride 16 */
2236 /* shader will patch stride and desc[2] */
2237 desc[4] = gsvs_va;
2238 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2239 S_008F04_STRIDE(0) |
2240 S_008F04_SWIZZLE_ENABLE(true);
2241 desc[6] = 0;
2242 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2246 S_008F0C_ELEMENT_SIZE(1) |
2247 S_008F0C_INDEX_STRIDE(1) |
2248 S_008F0C_ADD_TID_ENABLE(true);
2249
2250 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2251 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2254 } else {
2255 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2257 }
2258
2259 }
2260
2261 desc += 8;
2262
2263 if (tess_rings_bo) {
2264 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2265 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2266
2267 desc[0] = tess_va;
2268 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2269 S_008F04_STRIDE(0) |
2270 S_008F04_SWIZZLE_ENABLE(false);
2271 desc[2] = tess_factor_ring_size;
2272 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2273 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2274 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2275 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2276
2277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2278 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2279 S_008F0C_OOB_SELECT(3) |
2280 S_008F0C_RESOURCE_LEVEL(1);
2281 } else {
2282 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2284 }
2285
2286 desc[4] = tess_offchip_va;
2287 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2288 S_008F04_STRIDE(0) |
2289 S_008F04_SWIZZLE_ENABLE(false);
2290 desc[6] = tess_offchip_ring_size;
2291 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2292 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2293 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2294 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2295
2296 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2297 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2298 S_008F0C_OOB_SELECT(3) |
2299 S_008F0C_RESOURCE_LEVEL(1);
2300 } else {
2301 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2302 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2303 }
2304 }
2305
2306 desc += 8;
2307
2308 if (add_sample_positions) {
2309 /* add sample positions after all rings */
2310 memcpy(desc, queue->device->sample_locations_1x, 8);
2311 desc += 2;
2312 memcpy(desc, queue->device->sample_locations_2x, 16);
2313 desc += 4;
2314 memcpy(desc, queue->device->sample_locations_4x, 32);
2315 desc += 8;
2316 memcpy(desc, queue->device->sample_locations_8x, 64);
2317 }
2318 }
2319
2320 static unsigned
2321 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2322 {
2323 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2324 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2325 device->physical_device->rad_info.family != CHIP_STONEY;
2326 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2327 unsigned max_offchip_buffers;
2328 unsigned offchip_granularity;
2329 unsigned hs_offchip_param;
2330
2331 /*
2332 * Per RadeonSI:
2333 * This must be one less than the maximum number due to a hw limitation.
2334 * Various hardware bugs need thGFX7
2335 *
2336 * Per AMDVLK:
2337 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2338 * Gfx7 should limit max_offchip_buffers to 508
2339 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2340 *
2341 * Follow AMDVLK here.
2342 */
2343 if (device->physical_device->rad_info.chip_class >= GFX10) {
2344 max_offchip_buffers_per_se = 256;
2345 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2346 device->physical_device->rad_info.chip_class == GFX7 ||
2347 device->physical_device->rad_info.chip_class == GFX6)
2348 --max_offchip_buffers_per_se;
2349
2350 max_offchip_buffers = max_offchip_buffers_per_se *
2351 device->physical_device->rad_info.max_se;
2352
2353 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2354 * around by setting 4K granularity.
2355 */
2356 if (device->tess_offchip_block_dw_size == 4096) {
2357 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2358 offchip_granularity = V_03093C_X_4K_DWORDS;
2359 } else {
2360 assert(device->tess_offchip_block_dw_size == 8192);
2361 offchip_granularity = V_03093C_X_8K_DWORDS;
2362 }
2363
2364 switch (device->physical_device->rad_info.chip_class) {
2365 case GFX6:
2366 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2367 break;
2368 case GFX7:
2369 case GFX8:
2370 case GFX9:
2371 default:
2372 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2373 break;
2374 }
2375
2376 *max_offchip_buffers_p = max_offchip_buffers;
2377 if (device->physical_device->rad_info.chip_class >= GFX7) {
2378 if (device->physical_device->rad_info.chip_class >= GFX8)
2379 --max_offchip_buffers;
2380 hs_offchip_param =
2381 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2382 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2383 } else {
2384 hs_offchip_param =
2385 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2386 }
2387 return hs_offchip_param;
2388 }
2389
2390 static void
2391 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2392 struct radeon_winsys_bo *esgs_ring_bo,
2393 uint32_t esgs_ring_size,
2394 struct radeon_winsys_bo *gsvs_ring_bo,
2395 uint32_t gsvs_ring_size)
2396 {
2397 if (!esgs_ring_bo && !gsvs_ring_bo)
2398 return;
2399
2400 if (esgs_ring_bo)
2401 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2402
2403 if (gsvs_ring_bo)
2404 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2405
2406 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2407 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2408 radeon_emit(cs, esgs_ring_size >> 8);
2409 radeon_emit(cs, gsvs_ring_size >> 8);
2410 } else {
2411 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2412 radeon_emit(cs, esgs_ring_size >> 8);
2413 radeon_emit(cs, gsvs_ring_size >> 8);
2414 }
2415 }
2416
2417 static void
2418 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2419 unsigned hs_offchip_param, unsigned tf_ring_size,
2420 struct radeon_winsys_bo *tess_rings_bo)
2421 {
2422 uint64_t tf_va;
2423
2424 if (!tess_rings_bo)
2425 return;
2426
2427 tf_va = radv_buffer_get_va(tess_rings_bo);
2428
2429 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2430
2431 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2432 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2433 S_030938_SIZE(tf_ring_size / 4));
2434 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2435 tf_va >> 8);
2436
2437 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2438 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2439 S_030984_BASE_HI(tf_va >> 40));
2440 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2441 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2442 S_030944_BASE_HI(tf_va >> 40));
2443 }
2444 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2445 hs_offchip_param);
2446 } else {
2447 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2448 S_008988_SIZE(tf_ring_size / 4));
2449 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2450 tf_va >> 8);
2451 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2452 hs_offchip_param);
2453 }
2454 }
2455
2456 static void
2457 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2458 struct radeon_winsys_bo *compute_scratch_bo)
2459 {
2460 uint64_t scratch_va;
2461
2462 if (!compute_scratch_bo)
2463 return;
2464
2465 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2466
2467 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2468
2469 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2470 radeon_emit(cs, scratch_va);
2471 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2472 S_008F04_SWIZZLE_ENABLE(1));
2473 }
2474
2475 static void
2476 radv_emit_global_shader_pointers(struct radv_queue *queue,
2477 struct radeon_cmdbuf *cs,
2478 struct radeon_winsys_bo *descriptor_bo)
2479 {
2480 uint64_t va;
2481
2482 if (!descriptor_bo)
2483 return;
2484
2485 va = radv_buffer_get_va(descriptor_bo);
2486
2487 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2488
2489 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2490 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2491 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2492 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2493 R_00B430_SPI_SHADER_USER_DATA_HS_0};
2494
2495 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2496 radv_emit_shader_pointer(queue->device, cs, regs[i],
2497 va, true);
2498 }
2499 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2500 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2501 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2502 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2503 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2504
2505 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2506 radv_emit_shader_pointer(queue->device, cs, regs[i],
2507 va, true);
2508 }
2509 } else {
2510 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2511 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2512 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2513 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2514 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2515 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2516
2517 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2518 radv_emit_shader_pointer(queue->device, cs, regs[i],
2519 va, true);
2520 }
2521 }
2522 }
2523
2524 static void
2525 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2526 {
2527 struct radv_device *device = queue->device;
2528
2529 if (device->gfx_init) {
2530 uint64_t va = radv_buffer_get_va(device->gfx_init);
2531
2532 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2533 radeon_emit(cs, va);
2534 radeon_emit(cs, va >> 32);
2535 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2536
2537 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2538 } else {
2539 struct radv_physical_device *physical_device = device->physical_device;
2540 si_emit_graphics(physical_device, cs);
2541 }
2542 }
2543
2544 static void
2545 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2546 {
2547 struct radv_physical_device *physical_device = queue->device->physical_device;
2548 si_emit_compute(physical_device, cs);
2549 }
2550
2551 static VkResult
2552 radv_get_preamble_cs(struct radv_queue *queue,
2553 uint32_t scratch_size,
2554 uint32_t compute_scratch_size,
2555 uint32_t esgs_ring_size,
2556 uint32_t gsvs_ring_size,
2557 bool needs_tess_rings,
2558 bool needs_sample_positions,
2559 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2560 struct radeon_cmdbuf **initial_preamble_cs,
2561 struct radeon_cmdbuf **continue_preamble_cs)
2562 {
2563 struct radeon_winsys_bo *scratch_bo = NULL;
2564 struct radeon_winsys_bo *descriptor_bo = NULL;
2565 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2566 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2567 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2568 struct radeon_winsys_bo *tess_rings_bo = NULL;
2569 struct radeon_cmdbuf *dest_cs[3] = {0};
2570 bool add_tess_rings = false, add_sample_positions = false;
2571 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2572 unsigned max_offchip_buffers;
2573 unsigned hs_offchip_param = 0;
2574 unsigned tess_offchip_ring_offset;
2575 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2576 if (!queue->has_tess_rings) {
2577 if (needs_tess_rings)
2578 add_tess_rings = true;
2579 }
2580 if (!queue->has_sample_positions) {
2581 if (needs_sample_positions)
2582 add_sample_positions = true;
2583 }
2584 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2585 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2586 &max_offchip_buffers);
2587 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2588 tess_offchip_ring_size = max_offchip_buffers *
2589 queue->device->tess_offchip_block_dw_size * 4;
2590
2591 if (scratch_size <= queue->scratch_size &&
2592 compute_scratch_size <= queue->compute_scratch_size &&
2593 esgs_ring_size <= queue->esgs_ring_size &&
2594 gsvs_ring_size <= queue->gsvs_ring_size &&
2595 !add_tess_rings && !add_sample_positions &&
2596 queue->initial_preamble_cs) {
2597 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2598 *initial_preamble_cs = queue->initial_preamble_cs;
2599 *continue_preamble_cs = queue->continue_preamble_cs;
2600 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2601 *continue_preamble_cs = NULL;
2602 return VK_SUCCESS;
2603 }
2604
2605 if (scratch_size > queue->scratch_size) {
2606 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2607 scratch_size,
2608 4096,
2609 RADEON_DOMAIN_VRAM,
2610 ring_bo_flags,
2611 RADV_BO_PRIORITY_SCRATCH);
2612 if (!scratch_bo)
2613 goto fail;
2614 } else
2615 scratch_bo = queue->scratch_bo;
2616
2617 if (compute_scratch_size > queue->compute_scratch_size) {
2618 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2619 compute_scratch_size,
2620 4096,
2621 RADEON_DOMAIN_VRAM,
2622 ring_bo_flags,
2623 RADV_BO_PRIORITY_SCRATCH);
2624 if (!compute_scratch_bo)
2625 goto fail;
2626
2627 } else
2628 compute_scratch_bo = queue->compute_scratch_bo;
2629
2630 if (esgs_ring_size > queue->esgs_ring_size) {
2631 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2632 esgs_ring_size,
2633 4096,
2634 RADEON_DOMAIN_VRAM,
2635 ring_bo_flags,
2636 RADV_BO_PRIORITY_SCRATCH);
2637 if (!esgs_ring_bo)
2638 goto fail;
2639 } else {
2640 esgs_ring_bo = queue->esgs_ring_bo;
2641 esgs_ring_size = queue->esgs_ring_size;
2642 }
2643
2644 if (gsvs_ring_size > queue->gsvs_ring_size) {
2645 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2646 gsvs_ring_size,
2647 4096,
2648 RADEON_DOMAIN_VRAM,
2649 ring_bo_flags,
2650 RADV_BO_PRIORITY_SCRATCH);
2651 if (!gsvs_ring_bo)
2652 goto fail;
2653 } else {
2654 gsvs_ring_bo = queue->gsvs_ring_bo;
2655 gsvs_ring_size = queue->gsvs_ring_size;
2656 }
2657
2658 if (add_tess_rings) {
2659 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2660 tess_offchip_ring_offset + tess_offchip_ring_size,
2661 256,
2662 RADEON_DOMAIN_VRAM,
2663 ring_bo_flags,
2664 RADV_BO_PRIORITY_SCRATCH);
2665 if (!tess_rings_bo)
2666 goto fail;
2667 } else {
2668 tess_rings_bo = queue->tess_rings_bo;
2669 }
2670
2671 if (scratch_bo != queue->scratch_bo ||
2672 esgs_ring_bo != queue->esgs_ring_bo ||
2673 gsvs_ring_bo != queue->gsvs_ring_bo ||
2674 tess_rings_bo != queue->tess_rings_bo ||
2675 add_sample_positions) {
2676 uint32_t size = 0;
2677 if (gsvs_ring_bo || esgs_ring_bo ||
2678 tess_rings_bo || add_sample_positions) {
2679 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2680 if (add_sample_positions)
2681 size += 128; /* 64+32+16+8 = 120 bytes */
2682 }
2683 else if (scratch_bo)
2684 size = 8; /* 2 dword */
2685
2686 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2687 size,
2688 4096,
2689 RADEON_DOMAIN_VRAM,
2690 RADEON_FLAG_CPU_ACCESS |
2691 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2692 RADEON_FLAG_READ_ONLY,
2693 RADV_BO_PRIORITY_DESCRIPTOR);
2694 if (!descriptor_bo)
2695 goto fail;
2696 } else
2697 descriptor_bo = queue->descriptor_bo;
2698
2699 if (descriptor_bo != queue->descriptor_bo) {
2700 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2701
2702 if (scratch_bo) {
2703 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2704 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2705 S_008F04_SWIZZLE_ENABLE(1);
2706 map[0] = scratch_va;
2707 map[1] = rsrc1;
2708 }
2709
2710 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2711 fill_geom_tess_rings(queue, map, add_sample_positions,
2712 esgs_ring_size, esgs_ring_bo,
2713 gsvs_ring_size, gsvs_ring_bo,
2714 tess_factor_ring_size,
2715 tess_offchip_ring_offset,
2716 tess_offchip_ring_size,
2717 tess_rings_bo);
2718
2719 queue->device->ws->buffer_unmap(descriptor_bo);
2720 }
2721
2722 for(int i = 0; i < 3; ++i) {
2723 struct radeon_cmdbuf *cs = NULL;
2724 cs = queue->device->ws->cs_create(queue->device->ws,
2725 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2726 if (!cs)
2727 goto fail;
2728
2729 dest_cs[i] = cs;
2730
2731 if (scratch_bo)
2732 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2733
2734 /* Emit initial configuration. */
2735 switch (queue->queue_family_index) {
2736 case RADV_QUEUE_GENERAL:
2737 radv_init_graphics_state(cs, queue);
2738 break;
2739 case RADV_QUEUE_COMPUTE:
2740 radv_init_compute_state(cs, queue);
2741 break;
2742 case RADV_QUEUE_TRANSFER:
2743 break;
2744 }
2745
2746 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2747 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2748 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2749
2750 if (queue->device->physical_device->rad_info.chip_class < GFX10) {
2751 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2752 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2753 }
2754 }
2755
2756 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2757 gsvs_ring_bo, gsvs_ring_size);
2758 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2759 tess_factor_ring_size, tess_rings_bo);
2760 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2761 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2762
2763 if (i == 0) {
2764 si_cs_emit_cache_flush(cs,
2765 queue->device->physical_device->rad_info.chip_class,
2766 NULL, 0,
2767 queue->queue_family_index == RING_COMPUTE &&
2768 queue->device->physical_device->rad_info.chip_class >= GFX7,
2769 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2770 RADV_CMD_FLAG_INV_ICACHE |
2771 RADV_CMD_FLAG_INV_SCACHE |
2772 RADV_CMD_FLAG_INV_VCACHE |
2773 RADV_CMD_FLAG_INV_L2 |
2774 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2775 } else if (i == 1) {
2776 si_cs_emit_cache_flush(cs,
2777 queue->device->physical_device->rad_info.chip_class,
2778 NULL, 0,
2779 queue->queue_family_index == RING_COMPUTE &&
2780 queue->device->physical_device->rad_info.chip_class >= GFX7,
2781 RADV_CMD_FLAG_INV_ICACHE |
2782 RADV_CMD_FLAG_INV_SCACHE |
2783 RADV_CMD_FLAG_INV_VCACHE |
2784 RADV_CMD_FLAG_INV_L2 |
2785 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2786 }
2787
2788 if (!queue->device->ws->cs_finalize(cs))
2789 goto fail;
2790 }
2791
2792 if (queue->initial_full_flush_preamble_cs)
2793 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2794
2795 if (queue->initial_preamble_cs)
2796 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2797
2798 if (queue->continue_preamble_cs)
2799 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2800
2801 queue->initial_full_flush_preamble_cs = dest_cs[0];
2802 queue->initial_preamble_cs = dest_cs[1];
2803 queue->continue_preamble_cs = dest_cs[2];
2804
2805 if (scratch_bo != queue->scratch_bo) {
2806 if (queue->scratch_bo)
2807 queue->device->ws->buffer_destroy(queue->scratch_bo);
2808 queue->scratch_bo = scratch_bo;
2809 queue->scratch_size = scratch_size;
2810 }
2811
2812 if (compute_scratch_bo != queue->compute_scratch_bo) {
2813 if (queue->compute_scratch_bo)
2814 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2815 queue->compute_scratch_bo = compute_scratch_bo;
2816 queue->compute_scratch_size = compute_scratch_size;
2817 }
2818
2819 if (esgs_ring_bo != queue->esgs_ring_bo) {
2820 if (queue->esgs_ring_bo)
2821 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2822 queue->esgs_ring_bo = esgs_ring_bo;
2823 queue->esgs_ring_size = esgs_ring_size;
2824 }
2825
2826 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2827 if (queue->gsvs_ring_bo)
2828 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2829 queue->gsvs_ring_bo = gsvs_ring_bo;
2830 queue->gsvs_ring_size = gsvs_ring_size;
2831 }
2832
2833 if (tess_rings_bo != queue->tess_rings_bo) {
2834 queue->tess_rings_bo = tess_rings_bo;
2835 queue->has_tess_rings = true;
2836 }
2837
2838 if (descriptor_bo != queue->descriptor_bo) {
2839 if (queue->descriptor_bo)
2840 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2841
2842 queue->descriptor_bo = descriptor_bo;
2843 }
2844
2845 if (add_sample_positions)
2846 queue->has_sample_positions = true;
2847
2848 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2849 *initial_preamble_cs = queue->initial_preamble_cs;
2850 *continue_preamble_cs = queue->continue_preamble_cs;
2851 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2852 *continue_preamble_cs = NULL;
2853 return VK_SUCCESS;
2854 fail:
2855 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2856 if (dest_cs[i])
2857 queue->device->ws->cs_destroy(dest_cs[i]);
2858 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2859 queue->device->ws->buffer_destroy(descriptor_bo);
2860 if (scratch_bo && scratch_bo != queue->scratch_bo)
2861 queue->device->ws->buffer_destroy(scratch_bo);
2862 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2863 queue->device->ws->buffer_destroy(compute_scratch_bo);
2864 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2865 queue->device->ws->buffer_destroy(esgs_ring_bo);
2866 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2867 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2868 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2869 queue->device->ws->buffer_destroy(tess_rings_bo);
2870 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2871 }
2872
2873 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2874 struct radv_winsys_sem_counts *counts,
2875 int num_sems,
2876 const VkSemaphore *sems,
2877 VkFence _fence,
2878 bool reset_temp)
2879 {
2880 int syncobj_idx = 0, sem_idx = 0;
2881
2882 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2883 return VK_SUCCESS;
2884
2885 for (uint32_t i = 0; i < num_sems; i++) {
2886 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2887
2888 if (sem->temp_syncobj || sem->syncobj)
2889 counts->syncobj_count++;
2890 else
2891 counts->sem_count++;
2892 }
2893
2894 if (_fence != VK_NULL_HANDLE) {
2895 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2896 if (fence->temp_syncobj || fence->syncobj)
2897 counts->syncobj_count++;
2898 }
2899
2900 if (counts->syncobj_count) {
2901 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2902 if (!counts->syncobj)
2903 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2904 }
2905
2906 if (counts->sem_count) {
2907 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2908 if (!counts->sem) {
2909 free(counts->syncobj);
2910 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2911 }
2912 }
2913
2914 for (uint32_t i = 0; i < num_sems; i++) {
2915 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2916
2917 if (sem->temp_syncobj) {
2918 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2919 }
2920 else if (sem->syncobj)
2921 counts->syncobj[syncobj_idx++] = sem->syncobj;
2922 else {
2923 assert(sem->sem);
2924 counts->sem[sem_idx++] = sem->sem;
2925 }
2926 }
2927
2928 if (_fence != VK_NULL_HANDLE) {
2929 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2930 if (fence->temp_syncobj)
2931 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2932 else if (fence->syncobj)
2933 counts->syncobj[syncobj_idx++] = fence->syncobj;
2934 }
2935
2936 return VK_SUCCESS;
2937 }
2938
2939 static void
2940 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2941 {
2942 free(sem_info->wait.syncobj);
2943 free(sem_info->wait.sem);
2944 free(sem_info->signal.syncobj);
2945 free(sem_info->signal.sem);
2946 }
2947
2948
2949 static void radv_free_temp_syncobjs(struct radv_device *device,
2950 int num_sems,
2951 const VkSemaphore *sems)
2952 {
2953 for (uint32_t i = 0; i < num_sems; i++) {
2954 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2955
2956 if (sem->temp_syncobj) {
2957 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2958 sem->temp_syncobj = 0;
2959 }
2960 }
2961 }
2962
2963 static VkResult
2964 radv_alloc_sem_info(struct radv_instance *instance,
2965 struct radv_winsys_sem_info *sem_info,
2966 int num_wait_sems,
2967 const VkSemaphore *wait_sems,
2968 int num_signal_sems,
2969 const VkSemaphore *signal_sems,
2970 VkFence fence)
2971 {
2972 VkResult ret;
2973 memset(sem_info, 0, sizeof(*sem_info));
2974
2975 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2976 if (ret)
2977 return ret;
2978 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2979 if (ret)
2980 radv_free_sem_info(sem_info);
2981
2982 /* caller can override these */
2983 sem_info->cs_emit_wait = true;
2984 sem_info->cs_emit_signal = true;
2985 return ret;
2986 }
2987
2988 /* Signals fence as soon as all the work currently put on queue is done. */
2989 static VkResult radv_signal_fence(struct radv_queue *queue,
2990 struct radv_fence *fence)
2991 {
2992 int ret;
2993 VkResult result;
2994 struct radv_winsys_sem_info sem_info;
2995
2996 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2997 radv_fence_to_handle(fence));
2998 if (result != VK_SUCCESS)
2999 return result;
3000
3001 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3002 &queue->device->empty_cs[queue->queue_family_index],
3003 1, NULL, NULL, &sem_info, NULL,
3004 false, fence->fence);
3005 radv_free_sem_info(&sem_info);
3006
3007 if (ret)
3008 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3009
3010 return VK_SUCCESS;
3011 }
3012
3013 VkResult radv_QueueSubmit(
3014 VkQueue _queue,
3015 uint32_t submitCount,
3016 const VkSubmitInfo* pSubmits,
3017 VkFence _fence)
3018 {
3019 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3020 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3021 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3022 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3023 int ret;
3024 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3025 uint32_t scratch_size = 0;
3026 uint32_t compute_scratch_size = 0;
3027 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3028 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3029 VkResult result;
3030 bool fence_emitted = false;
3031 bool tess_rings_needed = false;
3032 bool sample_positions_needed = false;
3033
3034 /* Do this first so failing to allocate scratch buffers can't result in
3035 * partially executed submissions. */
3036 for (uint32_t i = 0; i < submitCount; i++) {
3037 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3038 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3039 pSubmits[i].pCommandBuffers[j]);
3040
3041 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3042 compute_scratch_size = MAX2(compute_scratch_size,
3043 cmd_buffer->compute_scratch_size_needed);
3044 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3045 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3046 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3047 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3048 }
3049 }
3050
3051 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3052 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3053 sample_positions_needed, &initial_flush_preamble_cs,
3054 &initial_preamble_cs, &continue_preamble_cs);
3055 if (result != VK_SUCCESS)
3056 return result;
3057
3058 for (uint32_t i = 0; i < submitCount; i++) {
3059 struct radeon_cmdbuf **cs_array;
3060 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3061 bool can_patch = true;
3062 uint32_t advance;
3063 struct radv_winsys_sem_info sem_info;
3064
3065 result = radv_alloc_sem_info(queue->device->instance,
3066 &sem_info,
3067 pSubmits[i].waitSemaphoreCount,
3068 pSubmits[i].pWaitSemaphores,
3069 pSubmits[i].signalSemaphoreCount,
3070 pSubmits[i].pSignalSemaphores,
3071 _fence);
3072 if (result != VK_SUCCESS)
3073 return result;
3074
3075 if (!pSubmits[i].commandBufferCount) {
3076 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3077 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3078 &queue->device->empty_cs[queue->queue_family_index],
3079 1, NULL, NULL,
3080 &sem_info, NULL,
3081 false, base_fence);
3082 if (ret) {
3083 radv_loge("failed to submit CS %d\n", i);
3084 abort();
3085 }
3086 fence_emitted = true;
3087 }
3088 radv_free_sem_info(&sem_info);
3089 continue;
3090 }
3091
3092 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3093 (pSubmits[i].commandBufferCount));
3094
3095 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3096 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3097 pSubmits[i].pCommandBuffers[j]);
3098 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3099
3100 cs_array[j] = cmd_buffer->cs;
3101 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3102 can_patch = false;
3103
3104 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3105 }
3106
3107 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3108 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3109 const struct radv_winsys_bo_list *bo_list = NULL;
3110
3111 advance = MIN2(max_cs_submission,
3112 pSubmits[i].commandBufferCount - j);
3113
3114 if (queue->device->trace_bo)
3115 *queue->device->trace_id_ptr = 0;
3116
3117 sem_info.cs_emit_wait = j == 0;
3118 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3119
3120 if (unlikely(queue->device->use_global_bo_list)) {
3121 pthread_mutex_lock(&queue->device->bo_list.mutex);
3122 bo_list = &queue->device->bo_list.list;
3123 }
3124
3125 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3126 advance, initial_preamble, continue_preamble_cs,
3127 &sem_info, bo_list,
3128 can_patch, base_fence);
3129
3130 if (unlikely(queue->device->use_global_bo_list))
3131 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3132
3133 if (ret) {
3134 radv_loge("failed to submit CS %d\n", i);
3135 abort();
3136 }
3137 fence_emitted = true;
3138 if (queue->device->trace_bo) {
3139 radv_check_gpu_hangs(queue, cs_array[j]);
3140 }
3141 }
3142
3143 radv_free_temp_syncobjs(queue->device,
3144 pSubmits[i].waitSemaphoreCount,
3145 pSubmits[i].pWaitSemaphores);
3146 radv_free_sem_info(&sem_info);
3147 free(cs_array);
3148 }
3149
3150 if (fence) {
3151 if (!fence_emitted) {
3152 result = radv_signal_fence(queue, fence);
3153 if (result != VK_SUCCESS)
3154 return result;
3155 }
3156 }
3157
3158 return VK_SUCCESS;
3159 }
3160
3161 VkResult radv_QueueWaitIdle(
3162 VkQueue _queue)
3163 {
3164 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3165
3166 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3167 radv_queue_family_to_ring(queue->queue_family_index),
3168 queue->queue_idx);
3169 return VK_SUCCESS;
3170 }
3171
3172 VkResult radv_DeviceWaitIdle(
3173 VkDevice _device)
3174 {
3175 RADV_FROM_HANDLE(radv_device, device, _device);
3176
3177 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3178 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3179 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3180 }
3181 }
3182 return VK_SUCCESS;
3183 }
3184
3185 VkResult radv_EnumerateInstanceExtensionProperties(
3186 const char* pLayerName,
3187 uint32_t* pPropertyCount,
3188 VkExtensionProperties* pProperties)
3189 {
3190 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3191
3192 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3193 if (radv_supported_instance_extensions.extensions[i]) {
3194 vk_outarray_append(&out, prop) {
3195 *prop = radv_instance_extensions[i];
3196 }
3197 }
3198 }
3199
3200 return vk_outarray_status(&out);
3201 }
3202
3203 VkResult radv_EnumerateDeviceExtensionProperties(
3204 VkPhysicalDevice physicalDevice,
3205 const char* pLayerName,
3206 uint32_t* pPropertyCount,
3207 VkExtensionProperties* pProperties)
3208 {
3209 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3210 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3211
3212 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3213 if (device->supported_extensions.extensions[i]) {
3214 vk_outarray_append(&out, prop) {
3215 *prop = radv_device_extensions[i];
3216 }
3217 }
3218 }
3219
3220 return vk_outarray_status(&out);
3221 }
3222
3223 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3224 VkInstance _instance,
3225 const char* pName)
3226 {
3227 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3228
3229 return radv_lookup_entrypoint_checked(pName,
3230 instance ? instance->apiVersion : 0,
3231 instance ? &instance->enabled_extensions : NULL,
3232 NULL);
3233 }
3234
3235 /* The loader wants us to expose a second GetInstanceProcAddr function
3236 * to work around certain LD_PRELOAD issues seen in apps.
3237 */
3238 PUBLIC
3239 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3240 VkInstance instance,
3241 const char* pName);
3242
3243 PUBLIC
3244 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3245 VkInstance instance,
3246 const char* pName)
3247 {
3248 return radv_GetInstanceProcAddr(instance, pName);
3249 }
3250
3251 PUBLIC
3252 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3253 VkInstance _instance,
3254 const char* pName);
3255
3256 PUBLIC
3257 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3258 VkInstance _instance,
3259 const char* pName)
3260 {
3261 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3262
3263 return radv_lookup_physical_device_entrypoint_checked(pName,
3264 instance ? instance->apiVersion : 0,
3265 instance ? &instance->enabled_extensions : NULL);
3266 }
3267
3268 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3269 VkDevice _device,
3270 const char* pName)
3271 {
3272 RADV_FROM_HANDLE(radv_device, device, _device);
3273
3274 return radv_lookup_entrypoint_checked(pName,
3275 device->instance->apiVersion,
3276 &device->instance->enabled_extensions,
3277 &device->enabled_extensions);
3278 }
3279
3280 bool radv_get_memory_fd(struct radv_device *device,
3281 struct radv_device_memory *memory,
3282 int *pFD)
3283 {
3284 struct radeon_bo_metadata metadata;
3285
3286 if (memory->image) {
3287 radv_init_metadata(device, memory->image, &metadata);
3288 device->ws->buffer_set_metadata(memory->bo, &metadata);
3289 }
3290
3291 return device->ws->buffer_get_fd(device->ws, memory->bo,
3292 pFD);
3293 }
3294
3295 static VkResult radv_alloc_memory(struct radv_device *device,
3296 const VkMemoryAllocateInfo* pAllocateInfo,
3297 const VkAllocationCallbacks* pAllocator,
3298 VkDeviceMemory* pMem)
3299 {
3300 struct radv_device_memory *mem;
3301 VkResult result;
3302 enum radeon_bo_domain domain;
3303 uint32_t flags = 0;
3304 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3305
3306 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3307
3308 if (pAllocateInfo->allocationSize == 0) {
3309 /* Apparently, this is allowed */
3310 *pMem = VK_NULL_HANDLE;
3311 return VK_SUCCESS;
3312 }
3313
3314 const VkImportMemoryFdInfoKHR *import_info =
3315 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3316 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3317 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3318 const VkExportMemoryAllocateInfo *export_info =
3319 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3320 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3321 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3322
3323 const struct wsi_memory_allocate_info *wsi_info =
3324 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3325
3326 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3327 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3328 if (mem == NULL)
3329 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3330
3331 if (wsi_info && wsi_info->implicit_sync)
3332 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3333
3334 if (dedicate_info) {
3335 mem->image = radv_image_from_handle(dedicate_info->image);
3336 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3337 } else {
3338 mem->image = NULL;
3339 mem->buffer = NULL;
3340 }
3341
3342 float priority_float = 0.5;
3343 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3344 vk_find_struct_const(pAllocateInfo->pNext,
3345 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3346 if (priority_ext)
3347 priority_float = priority_ext->priority;
3348
3349 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3350 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3351
3352 mem->user_ptr = NULL;
3353
3354 if (import_info) {
3355 assert(import_info->handleType ==
3356 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3357 import_info->handleType ==
3358 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3359 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3360 priority, NULL, NULL);
3361 if (!mem->bo) {
3362 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3363 goto fail;
3364 } else {
3365 close(import_info->fd);
3366 }
3367 } else if (host_ptr_info) {
3368 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3369 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3370 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3371 pAllocateInfo->allocationSize,
3372 priority);
3373 if (!mem->bo) {
3374 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3375 goto fail;
3376 } else {
3377 mem->user_ptr = host_ptr_info->pHostPointer;
3378 }
3379 } else {
3380 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3381 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3382 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3383 domain = RADEON_DOMAIN_GTT;
3384 else
3385 domain = RADEON_DOMAIN_VRAM;
3386
3387 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3388 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3389 else
3390 flags |= RADEON_FLAG_CPU_ACCESS;
3391
3392 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3393 flags |= RADEON_FLAG_GTT_WC;
3394
3395 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3396 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3397 if (device->use_global_bo_list) {
3398 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3399 }
3400 }
3401
3402 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3403 domain, flags, priority);
3404
3405 if (!mem->bo) {
3406 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3407 goto fail;
3408 }
3409 mem->type_index = mem_type_index;
3410 }
3411
3412 result = radv_bo_list_add(device, mem->bo);
3413 if (result != VK_SUCCESS)
3414 goto fail_bo;
3415
3416 *pMem = radv_device_memory_to_handle(mem);
3417
3418 return VK_SUCCESS;
3419
3420 fail_bo:
3421 device->ws->buffer_destroy(mem->bo);
3422 fail:
3423 vk_free2(&device->alloc, pAllocator, mem);
3424
3425 return result;
3426 }
3427
3428 VkResult radv_AllocateMemory(
3429 VkDevice _device,
3430 const VkMemoryAllocateInfo* pAllocateInfo,
3431 const VkAllocationCallbacks* pAllocator,
3432 VkDeviceMemory* pMem)
3433 {
3434 RADV_FROM_HANDLE(radv_device, device, _device);
3435 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3436 }
3437
3438 void radv_FreeMemory(
3439 VkDevice _device,
3440 VkDeviceMemory _mem,
3441 const VkAllocationCallbacks* pAllocator)
3442 {
3443 RADV_FROM_HANDLE(radv_device, device, _device);
3444 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3445
3446 if (mem == NULL)
3447 return;
3448
3449 radv_bo_list_remove(device, mem->bo);
3450 device->ws->buffer_destroy(mem->bo);
3451 mem->bo = NULL;
3452
3453 vk_free2(&device->alloc, pAllocator, mem);
3454 }
3455
3456 VkResult radv_MapMemory(
3457 VkDevice _device,
3458 VkDeviceMemory _memory,
3459 VkDeviceSize offset,
3460 VkDeviceSize size,
3461 VkMemoryMapFlags flags,
3462 void** ppData)
3463 {
3464 RADV_FROM_HANDLE(radv_device, device, _device);
3465 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3466
3467 if (mem == NULL) {
3468 *ppData = NULL;
3469 return VK_SUCCESS;
3470 }
3471
3472 if (mem->user_ptr)
3473 *ppData = mem->user_ptr;
3474 else
3475 *ppData = device->ws->buffer_map(mem->bo);
3476
3477 if (*ppData) {
3478 *ppData += offset;
3479 return VK_SUCCESS;
3480 }
3481
3482 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3483 }
3484
3485 void radv_UnmapMemory(
3486 VkDevice _device,
3487 VkDeviceMemory _memory)
3488 {
3489 RADV_FROM_HANDLE(radv_device, device, _device);
3490 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3491
3492 if (mem == NULL)
3493 return;
3494
3495 if (mem->user_ptr == NULL)
3496 device->ws->buffer_unmap(mem->bo);
3497 }
3498
3499 VkResult radv_FlushMappedMemoryRanges(
3500 VkDevice _device,
3501 uint32_t memoryRangeCount,
3502 const VkMappedMemoryRange* pMemoryRanges)
3503 {
3504 return VK_SUCCESS;
3505 }
3506
3507 VkResult radv_InvalidateMappedMemoryRanges(
3508 VkDevice _device,
3509 uint32_t memoryRangeCount,
3510 const VkMappedMemoryRange* pMemoryRanges)
3511 {
3512 return VK_SUCCESS;
3513 }
3514
3515 void radv_GetBufferMemoryRequirements(
3516 VkDevice _device,
3517 VkBuffer _buffer,
3518 VkMemoryRequirements* pMemoryRequirements)
3519 {
3520 RADV_FROM_HANDLE(radv_device, device, _device);
3521 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3522
3523 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3524
3525 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3526 pMemoryRequirements->alignment = 4096;
3527 else
3528 pMemoryRequirements->alignment = 16;
3529
3530 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3531 }
3532
3533 void radv_GetBufferMemoryRequirements2(
3534 VkDevice device,
3535 const VkBufferMemoryRequirementsInfo2 *pInfo,
3536 VkMemoryRequirements2 *pMemoryRequirements)
3537 {
3538 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3539 &pMemoryRequirements->memoryRequirements);
3540 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3541 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3542 switch (ext->sType) {
3543 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3544 VkMemoryDedicatedRequirements *req =
3545 (VkMemoryDedicatedRequirements *) ext;
3546 req->requiresDedicatedAllocation = buffer->shareable;
3547 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3548 break;
3549 }
3550 default:
3551 break;
3552 }
3553 }
3554 }
3555
3556 void radv_GetImageMemoryRequirements(
3557 VkDevice _device,
3558 VkImage _image,
3559 VkMemoryRequirements* pMemoryRequirements)
3560 {
3561 RADV_FROM_HANDLE(radv_device, device, _device);
3562 RADV_FROM_HANDLE(radv_image, image, _image);
3563
3564 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3565
3566 pMemoryRequirements->size = image->size;
3567 pMemoryRequirements->alignment = image->alignment;
3568 }
3569
3570 void radv_GetImageMemoryRequirements2(
3571 VkDevice device,
3572 const VkImageMemoryRequirementsInfo2 *pInfo,
3573 VkMemoryRequirements2 *pMemoryRequirements)
3574 {
3575 radv_GetImageMemoryRequirements(device, pInfo->image,
3576 &pMemoryRequirements->memoryRequirements);
3577
3578 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3579
3580 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3581 switch (ext->sType) {
3582 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3583 VkMemoryDedicatedRequirements *req =
3584 (VkMemoryDedicatedRequirements *) ext;
3585 req->requiresDedicatedAllocation = image->shareable;
3586 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3587 break;
3588 }
3589 default:
3590 break;
3591 }
3592 }
3593 }
3594
3595 void radv_GetImageSparseMemoryRequirements(
3596 VkDevice device,
3597 VkImage image,
3598 uint32_t* pSparseMemoryRequirementCount,
3599 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3600 {
3601 stub();
3602 }
3603
3604 void radv_GetImageSparseMemoryRequirements2(
3605 VkDevice device,
3606 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3607 uint32_t* pSparseMemoryRequirementCount,
3608 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3609 {
3610 stub();
3611 }
3612
3613 void radv_GetDeviceMemoryCommitment(
3614 VkDevice device,
3615 VkDeviceMemory memory,
3616 VkDeviceSize* pCommittedMemoryInBytes)
3617 {
3618 *pCommittedMemoryInBytes = 0;
3619 }
3620
3621 VkResult radv_BindBufferMemory2(VkDevice device,
3622 uint32_t bindInfoCount,
3623 const VkBindBufferMemoryInfo *pBindInfos)
3624 {
3625 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3626 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3627 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3628
3629 if (mem) {
3630 buffer->bo = mem->bo;
3631 buffer->offset = pBindInfos[i].memoryOffset;
3632 } else {
3633 buffer->bo = NULL;
3634 }
3635 }
3636 return VK_SUCCESS;
3637 }
3638
3639 VkResult radv_BindBufferMemory(
3640 VkDevice device,
3641 VkBuffer buffer,
3642 VkDeviceMemory memory,
3643 VkDeviceSize memoryOffset)
3644 {
3645 const VkBindBufferMemoryInfo info = {
3646 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3647 .buffer = buffer,
3648 .memory = memory,
3649 .memoryOffset = memoryOffset
3650 };
3651
3652 return radv_BindBufferMemory2(device, 1, &info);
3653 }
3654
3655 VkResult radv_BindImageMemory2(VkDevice device,
3656 uint32_t bindInfoCount,
3657 const VkBindImageMemoryInfo *pBindInfos)
3658 {
3659 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3660 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3661 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3662
3663 if (mem) {
3664 image->bo = mem->bo;
3665 image->offset = pBindInfos[i].memoryOffset;
3666 } else {
3667 image->bo = NULL;
3668 image->offset = 0;
3669 }
3670 }
3671 return VK_SUCCESS;
3672 }
3673
3674
3675 VkResult radv_BindImageMemory(
3676 VkDevice device,
3677 VkImage image,
3678 VkDeviceMemory memory,
3679 VkDeviceSize memoryOffset)
3680 {
3681 const VkBindImageMemoryInfo info = {
3682 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3683 .image = image,
3684 .memory = memory,
3685 .memoryOffset = memoryOffset
3686 };
3687
3688 return radv_BindImageMemory2(device, 1, &info);
3689 }
3690
3691
3692 static void
3693 radv_sparse_buffer_bind_memory(struct radv_device *device,
3694 const VkSparseBufferMemoryBindInfo *bind)
3695 {
3696 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3697
3698 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3699 struct radv_device_memory *mem = NULL;
3700
3701 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3702 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3703
3704 device->ws->buffer_virtual_bind(buffer->bo,
3705 bind->pBinds[i].resourceOffset,
3706 bind->pBinds[i].size,
3707 mem ? mem->bo : NULL,
3708 bind->pBinds[i].memoryOffset);
3709 }
3710 }
3711
3712 static void
3713 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3714 const VkSparseImageOpaqueMemoryBindInfo *bind)
3715 {
3716 RADV_FROM_HANDLE(radv_image, image, bind->image);
3717
3718 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3719 struct radv_device_memory *mem = NULL;
3720
3721 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3722 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3723
3724 device->ws->buffer_virtual_bind(image->bo,
3725 bind->pBinds[i].resourceOffset,
3726 bind->pBinds[i].size,
3727 mem ? mem->bo : NULL,
3728 bind->pBinds[i].memoryOffset);
3729 }
3730 }
3731
3732 VkResult radv_QueueBindSparse(
3733 VkQueue _queue,
3734 uint32_t bindInfoCount,
3735 const VkBindSparseInfo* pBindInfo,
3736 VkFence _fence)
3737 {
3738 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3739 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3740 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3741 bool fence_emitted = false;
3742 VkResult result;
3743 int ret;
3744
3745 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3746 struct radv_winsys_sem_info sem_info;
3747 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3748 radv_sparse_buffer_bind_memory(queue->device,
3749 pBindInfo[i].pBufferBinds + j);
3750 }
3751
3752 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3753 radv_sparse_image_opaque_bind_memory(queue->device,
3754 pBindInfo[i].pImageOpaqueBinds + j);
3755 }
3756
3757 VkResult result;
3758 result = radv_alloc_sem_info(queue->device->instance,
3759 &sem_info,
3760 pBindInfo[i].waitSemaphoreCount,
3761 pBindInfo[i].pWaitSemaphores,
3762 pBindInfo[i].signalSemaphoreCount,
3763 pBindInfo[i].pSignalSemaphores,
3764 _fence);
3765 if (result != VK_SUCCESS)
3766 return result;
3767
3768 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3769 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3770 &queue->device->empty_cs[queue->queue_family_index],
3771 1, NULL, NULL,
3772 &sem_info, NULL,
3773 false, base_fence);
3774 if (ret) {
3775 radv_loge("failed to submit CS %d\n", i);
3776 abort();
3777 }
3778
3779 fence_emitted = true;
3780 }
3781
3782 radv_free_sem_info(&sem_info);
3783
3784 }
3785
3786 if (fence) {
3787 if (!fence_emitted) {
3788 result = radv_signal_fence(queue, fence);
3789 if (result != VK_SUCCESS)
3790 return result;
3791 }
3792 }
3793
3794 return VK_SUCCESS;
3795 }
3796
3797 VkResult radv_CreateFence(
3798 VkDevice _device,
3799 const VkFenceCreateInfo* pCreateInfo,
3800 const VkAllocationCallbacks* pAllocator,
3801 VkFence* pFence)
3802 {
3803 RADV_FROM_HANDLE(radv_device, device, _device);
3804 const VkExportFenceCreateInfo *export =
3805 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3806 VkExternalFenceHandleTypeFlags handleTypes =
3807 export ? export->handleTypes : 0;
3808
3809 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3810 sizeof(*fence), 8,
3811 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3812
3813 if (!fence)
3814 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3815
3816 fence->fence_wsi = NULL;
3817 fence->temp_syncobj = 0;
3818 if (device->always_use_syncobj || handleTypes) {
3819 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3820 if (ret) {
3821 vk_free2(&device->alloc, pAllocator, fence);
3822 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3823 }
3824 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3825 device->ws->signal_syncobj(device->ws, fence->syncobj);
3826 }
3827 fence->fence = NULL;
3828 } else {
3829 fence->fence = device->ws->create_fence();
3830 if (!fence->fence) {
3831 vk_free2(&device->alloc, pAllocator, fence);
3832 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3833 }
3834 fence->syncobj = 0;
3835 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3836 device->ws->signal_fence(fence->fence);
3837 }
3838
3839 *pFence = radv_fence_to_handle(fence);
3840
3841 return VK_SUCCESS;
3842 }
3843
3844 void radv_DestroyFence(
3845 VkDevice _device,
3846 VkFence _fence,
3847 const VkAllocationCallbacks* pAllocator)
3848 {
3849 RADV_FROM_HANDLE(radv_device, device, _device);
3850 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3851
3852 if (!fence)
3853 return;
3854
3855 if (fence->temp_syncobj)
3856 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3857 if (fence->syncobj)
3858 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3859 if (fence->fence)
3860 device->ws->destroy_fence(fence->fence);
3861 if (fence->fence_wsi)
3862 fence->fence_wsi->destroy(fence->fence_wsi);
3863 vk_free2(&device->alloc, pAllocator, fence);
3864 }
3865
3866
3867 uint64_t radv_get_current_time(void)
3868 {
3869 struct timespec tv;
3870 clock_gettime(CLOCK_MONOTONIC, &tv);
3871 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3872 }
3873
3874 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3875 {
3876 uint64_t current_time = radv_get_current_time();
3877
3878 timeout = MIN2(UINT64_MAX - current_time, timeout);
3879
3880 return current_time + timeout;
3881 }
3882
3883
3884 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3885 uint32_t fenceCount, const VkFence *pFences)
3886 {
3887 for (uint32_t i = 0; i < fenceCount; ++i) {
3888 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3889 if (fence->fence == NULL || fence->syncobj ||
3890 fence->temp_syncobj || fence->fence_wsi ||
3891 (!device->ws->is_fence_waitable(fence->fence)))
3892 return false;
3893 }
3894 return true;
3895 }
3896
3897 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3898 {
3899 for (uint32_t i = 0; i < fenceCount; ++i) {
3900 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3901 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3902 return false;
3903 }
3904 return true;
3905 }
3906
3907 VkResult radv_WaitForFences(
3908 VkDevice _device,
3909 uint32_t fenceCount,
3910 const VkFence* pFences,
3911 VkBool32 waitAll,
3912 uint64_t timeout)
3913 {
3914 RADV_FROM_HANDLE(radv_device, device, _device);
3915 timeout = radv_get_absolute_timeout(timeout);
3916
3917 if (device->always_use_syncobj &&
3918 radv_all_fences_syncobj(fenceCount, pFences))
3919 {
3920 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3921 if (!handles)
3922 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3923
3924 for (uint32_t i = 0; i < fenceCount; ++i) {
3925 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3926 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3927 }
3928
3929 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3930
3931 free(handles);
3932 return success ? VK_SUCCESS : VK_TIMEOUT;
3933 }
3934
3935 if (!waitAll && fenceCount > 1) {
3936 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3937 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3938 uint32_t wait_count = 0;
3939 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3940 if (!fences)
3941 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3942
3943 for (uint32_t i = 0; i < fenceCount; ++i) {
3944 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3945
3946 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3947 free(fences);
3948 return VK_SUCCESS;
3949 }
3950
3951 fences[wait_count++] = fence->fence;
3952 }
3953
3954 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3955 waitAll, timeout - radv_get_current_time());
3956
3957 free(fences);
3958 return success ? VK_SUCCESS : VK_TIMEOUT;
3959 }
3960
3961 while(radv_get_current_time() <= timeout) {
3962 for (uint32_t i = 0; i < fenceCount; ++i) {
3963 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3964 return VK_SUCCESS;
3965 }
3966 }
3967 return VK_TIMEOUT;
3968 }
3969
3970 for (uint32_t i = 0; i < fenceCount; ++i) {
3971 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3972 bool expired = false;
3973
3974 if (fence->temp_syncobj) {
3975 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3976 return VK_TIMEOUT;
3977 continue;
3978 }
3979
3980 if (fence->syncobj) {
3981 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3982 return VK_TIMEOUT;
3983 continue;
3984 }
3985
3986 if (fence->fence) {
3987 if (!device->ws->is_fence_waitable(fence->fence)) {
3988 while(!device->ws->is_fence_waitable(fence->fence) &&
3989 radv_get_current_time() <= timeout)
3990 /* Do nothing */;
3991 }
3992
3993 expired = device->ws->fence_wait(device->ws,
3994 fence->fence,
3995 true, timeout);
3996 if (!expired)
3997 return VK_TIMEOUT;
3998 }
3999
4000 if (fence->fence_wsi) {
4001 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4002 if (result != VK_SUCCESS)
4003 return result;
4004 }
4005 }
4006
4007 return VK_SUCCESS;
4008 }
4009
4010 VkResult radv_ResetFences(VkDevice _device,
4011 uint32_t fenceCount,
4012 const VkFence *pFences)
4013 {
4014 RADV_FROM_HANDLE(radv_device, device, _device);
4015
4016 for (unsigned i = 0; i < fenceCount; ++i) {
4017 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4018 if (fence->fence)
4019 device->ws->reset_fence(fence->fence);
4020
4021 /* Per spec, we first restore the permanent payload, and then reset, so
4022 * having a temp syncobj should not skip resetting the permanent syncobj. */
4023 if (fence->temp_syncobj) {
4024 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4025 fence->temp_syncobj = 0;
4026 }
4027
4028 if (fence->syncobj) {
4029 device->ws->reset_syncobj(device->ws, fence->syncobj);
4030 }
4031 }
4032
4033 return VK_SUCCESS;
4034 }
4035
4036 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4037 {
4038 RADV_FROM_HANDLE(radv_device, device, _device);
4039 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4040
4041 if (fence->temp_syncobj) {
4042 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4043 return success ? VK_SUCCESS : VK_NOT_READY;
4044 }
4045
4046 if (fence->syncobj) {
4047 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4048 return success ? VK_SUCCESS : VK_NOT_READY;
4049 }
4050
4051 if (fence->fence) {
4052 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4053 return VK_NOT_READY;
4054 }
4055 if (fence->fence_wsi) {
4056 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4057
4058 if (result != VK_SUCCESS) {
4059 if (result == VK_TIMEOUT)
4060 return VK_NOT_READY;
4061 return result;
4062 }
4063 }
4064 return VK_SUCCESS;
4065 }
4066
4067
4068 // Queue semaphore functions
4069
4070 VkResult radv_CreateSemaphore(
4071 VkDevice _device,
4072 const VkSemaphoreCreateInfo* pCreateInfo,
4073 const VkAllocationCallbacks* pAllocator,
4074 VkSemaphore* pSemaphore)
4075 {
4076 RADV_FROM_HANDLE(radv_device, device, _device);
4077 const VkExportSemaphoreCreateInfo *export =
4078 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4079 VkExternalSemaphoreHandleTypeFlags handleTypes =
4080 export ? export->handleTypes : 0;
4081
4082 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4083 sizeof(*sem), 8,
4084 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4085 if (!sem)
4086 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4087
4088 sem->temp_syncobj = 0;
4089 /* create a syncobject if we are going to export this semaphore */
4090 if (device->always_use_syncobj || handleTypes) {
4091 assert (device->physical_device->rad_info.has_syncobj);
4092 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4093 if (ret) {
4094 vk_free2(&device->alloc, pAllocator, sem);
4095 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4096 }
4097 sem->sem = NULL;
4098 } else {
4099 sem->sem = device->ws->create_sem(device->ws);
4100 if (!sem->sem) {
4101 vk_free2(&device->alloc, pAllocator, sem);
4102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4103 }
4104 sem->syncobj = 0;
4105 }
4106
4107 *pSemaphore = radv_semaphore_to_handle(sem);
4108 return VK_SUCCESS;
4109 }
4110
4111 void radv_DestroySemaphore(
4112 VkDevice _device,
4113 VkSemaphore _semaphore,
4114 const VkAllocationCallbacks* pAllocator)
4115 {
4116 RADV_FROM_HANDLE(radv_device, device, _device);
4117 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4118 if (!_semaphore)
4119 return;
4120
4121 if (sem->syncobj)
4122 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4123 else
4124 device->ws->destroy_sem(sem->sem);
4125 vk_free2(&device->alloc, pAllocator, sem);
4126 }
4127
4128 VkResult radv_CreateEvent(
4129 VkDevice _device,
4130 const VkEventCreateInfo* pCreateInfo,
4131 const VkAllocationCallbacks* pAllocator,
4132 VkEvent* pEvent)
4133 {
4134 RADV_FROM_HANDLE(radv_device, device, _device);
4135 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4136 sizeof(*event), 8,
4137 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4138
4139 if (!event)
4140 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4141
4142 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4143 RADEON_DOMAIN_GTT,
4144 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4145 RADV_BO_PRIORITY_FENCE);
4146 if (!event->bo) {
4147 vk_free2(&device->alloc, pAllocator, event);
4148 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4149 }
4150
4151 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4152
4153 *pEvent = radv_event_to_handle(event);
4154
4155 return VK_SUCCESS;
4156 }
4157
4158 void radv_DestroyEvent(
4159 VkDevice _device,
4160 VkEvent _event,
4161 const VkAllocationCallbacks* pAllocator)
4162 {
4163 RADV_FROM_HANDLE(radv_device, device, _device);
4164 RADV_FROM_HANDLE(radv_event, event, _event);
4165
4166 if (!event)
4167 return;
4168 device->ws->buffer_destroy(event->bo);
4169 vk_free2(&device->alloc, pAllocator, event);
4170 }
4171
4172 VkResult radv_GetEventStatus(
4173 VkDevice _device,
4174 VkEvent _event)
4175 {
4176 RADV_FROM_HANDLE(radv_event, event, _event);
4177
4178 if (*event->map == 1)
4179 return VK_EVENT_SET;
4180 return VK_EVENT_RESET;
4181 }
4182
4183 VkResult radv_SetEvent(
4184 VkDevice _device,
4185 VkEvent _event)
4186 {
4187 RADV_FROM_HANDLE(radv_event, event, _event);
4188 *event->map = 1;
4189
4190 return VK_SUCCESS;
4191 }
4192
4193 VkResult radv_ResetEvent(
4194 VkDevice _device,
4195 VkEvent _event)
4196 {
4197 RADV_FROM_HANDLE(radv_event, event, _event);
4198 *event->map = 0;
4199
4200 return VK_SUCCESS;
4201 }
4202
4203 VkResult radv_CreateBuffer(
4204 VkDevice _device,
4205 const VkBufferCreateInfo* pCreateInfo,
4206 const VkAllocationCallbacks* pAllocator,
4207 VkBuffer* pBuffer)
4208 {
4209 RADV_FROM_HANDLE(radv_device, device, _device);
4210 struct radv_buffer *buffer;
4211
4212 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4213
4214 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4215 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4216 if (buffer == NULL)
4217 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4218
4219 buffer->size = pCreateInfo->size;
4220 buffer->usage = pCreateInfo->usage;
4221 buffer->bo = NULL;
4222 buffer->offset = 0;
4223 buffer->flags = pCreateInfo->flags;
4224
4225 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4226 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4227
4228 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4229 buffer->bo = device->ws->buffer_create(device->ws,
4230 align64(buffer->size, 4096),
4231 4096, 0, RADEON_FLAG_VIRTUAL,
4232 RADV_BO_PRIORITY_VIRTUAL);
4233 if (!buffer->bo) {
4234 vk_free2(&device->alloc, pAllocator, buffer);
4235 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4236 }
4237 }
4238
4239 *pBuffer = radv_buffer_to_handle(buffer);
4240
4241 return VK_SUCCESS;
4242 }
4243
4244 void radv_DestroyBuffer(
4245 VkDevice _device,
4246 VkBuffer _buffer,
4247 const VkAllocationCallbacks* pAllocator)
4248 {
4249 RADV_FROM_HANDLE(radv_device, device, _device);
4250 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4251
4252 if (!buffer)
4253 return;
4254
4255 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4256 device->ws->buffer_destroy(buffer->bo);
4257
4258 vk_free2(&device->alloc, pAllocator, buffer);
4259 }
4260
4261 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4262 VkDevice device,
4263 const VkBufferDeviceAddressInfoEXT* pInfo)
4264 {
4265 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4266 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4267 }
4268
4269
4270 static inline unsigned
4271 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4272 {
4273 if (stencil)
4274 return plane->surface.u.legacy.stencil_tiling_index[level];
4275 else
4276 return plane->surface.u.legacy.tiling_index[level];
4277 }
4278
4279 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4280 {
4281 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4282 }
4283
4284 static uint32_t
4285 radv_init_dcc_control_reg(struct radv_device *device,
4286 struct radv_image_view *iview)
4287 {
4288 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4289 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4290 unsigned max_compressed_block_size;
4291 unsigned independent_128b_blocks;
4292 unsigned independent_64b_blocks;
4293
4294 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4295 return 0;
4296
4297 if (!device->physical_device->rad_info.has_dedicated_vram) {
4298 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4299 * dGPU and 64 for APU because all of our APUs to date use
4300 * DIMMs which have a request granularity size of 64B while all
4301 * other chips have a 32B request size.
4302 */
4303 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4304 }
4305
4306 if (device->physical_device->rad_info.chip_class >= GFX10) {
4307 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4308 independent_64b_blocks = 0;
4309 independent_128b_blocks = 1;
4310 } else {
4311 independent_128b_blocks = 0;
4312
4313 if (iview->image->info.samples > 1) {
4314 if (iview->image->planes[0].surface.bpe == 1)
4315 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4316 else if (iview->image->planes[0].surface.bpe == 2)
4317 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4318 }
4319
4320 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4321 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4322 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4323 /* If this DCC image is potentially going to be used in texture
4324 * fetches, we need some special settings.
4325 */
4326 independent_64b_blocks = 1;
4327 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4328 } else {
4329 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4330 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4331 * big as possible for better compression state.
4332 */
4333 independent_64b_blocks = 0;
4334 max_compressed_block_size = max_uncompressed_block_size;
4335 }
4336 }
4337
4338 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4339 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4340 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4341 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4342 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4343 }
4344
4345 static void
4346 radv_initialise_color_surface(struct radv_device *device,
4347 struct radv_color_buffer_info *cb,
4348 struct radv_image_view *iview)
4349 {
4350 const struct vk_format_description *desc;
4351 unsigned ntype, format, swap, endian;
4352 unsigned blend_clamp = 0, blend_bypass = 0;
4353 uint64_t va;
4354 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4355 const struct radeon_surf *surf = &plane->surface;
4356
4357 desc = vk_format_description(iview->vk_format);
4358
4359 memset(cb, 0, sizeof(*cb));
4360
4361 /* Intensity is implemented as Red, so treat it that way. */
4362 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4363
4364 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4365
4366 cb->cb_color_base = va >> 8;
4367
4368 if (device->physical_device->rad_info.chip_class >= GFX9) {
4369 struct gfx9_surf_meta_flags meta;
4370 if (iview->image->dcc_offset)
4371 meta = surf->u.gfx9.dcc;
4372 else
4373 meta = surf->u.gfx9.cmask;
4374
4375 if (device->physical_device->rad_info.chip_class >= GFX10) {
4376 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4377 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4378 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4379 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4380 } else {
4381 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4382 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4383 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4384 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4385 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4386 }
4387
4388 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4389 cb->cb_color_base |= surf->tile_swizzle;
4390 } else {
4391 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4392 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4393
4394 cb->cb_color_base += level_info->offset >> 8;
4395 if (level_info->mode == RADEON_SURF_MODE_2D)
4396 cb->cb_color_base |= surf->tile_swizzle;
4397
4398 pitch_tile_max = level_info->nblk_x / 8 - 1;
4399 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4400 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4401
4402 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4403 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4404 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4405
4406 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4407
4408 if (radv_image_has_fmask(iview->image)) {
4409 if (device->physical_device->rad_info.chip_class >= GFX7)
4410 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4411 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4412 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4413 } else {
4414 /* This must be set for fast clear to work without FMASK. */
4415 if (device->physical_device->rad_info.chip_class >= GFX7)
4416 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4417 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4418 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4419 }
4420 }
4421
4422 /* CMASK variables */
4423 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4424 va += iview->image->cmask.offset;
4425 cb->cb_color_cmask = va >> 8;
4426
4427 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4428 va += iview->image->dcc_offset;
4429
4430 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4431 device->physical_device->rad_info.chip_class <= GFX8)
4432 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4433
4434 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4435 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4436
4437 cb->cb_dcc_base = va >> 8;
4438 cb->cb_dcc_base |= dcc_tile_swizzle;
4439
4440 /* GFX10 field has the same base shift as the GFX6 field. */
4441 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4442 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4443 S_028C6C_SLICE_MAX_GFX10(max_slice);
4444
4445 if (iview->image->info.samples > 1) {
4446 unsigned log_samples = util_logbase2(iview->image->info.samples);
4447
4448 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4449 S_028C74_NUM_FRAGMENTS(log_samples);
4450 }
4451
4452 if (radv_image_has_fmask(iview->image)) {
4453 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4454 cb->cb_color_fmask = va >> 8;
4455 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4456 } else {
4457 cb->cb_color_fmask = cb->cb_color_base;
4458 }
4459
4460 ntype = radv_translate_color_numformat(iview->vk_format,
4461 desc,
4462 vk_format_get_first_non_void_channel(iview->vk_format));
4463 format = radv_translate_colorformat(iview->vk_format);
4464 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4465 radv_finishme("Illegal color\n");
4466 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4467 endian = radv_colorformat_endian_swap(format);
4468
4469 /* blend clamp should be set for all NORM/SRGB types */
4470 if (ntype == V_028C70_NUMBER_UNORM ||
4471 ntype == V_028C70_NUMBER_SNORM ||
4472 ntype == V_028C70_NUMBER_SRGB)
4473 blend_clamp = 1;
4474
4475 /* set blend bypass according to docs if SINT/UINT or
4476 8/24 COLOR variants */
4477 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4478 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4479 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4480 blend_clamp = 0;
4481 blend_bypass = 1;
4482 }
4483 #if 0
4484 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4485 (format == V_028C70_COLOR_8 ||
4486 format == V_028C70_COLOR_8_8 ||
4487 format == V_028C70_COLOR_8_8_8_8))
4488 ->color_is_int8 = true;
4489 #endif
4490 cb->cb_color_info = S_028C70_FORMAT(format) |
4491 S_028C70_COMP_SWAP(swap) |
4492 S_028C70_BLEND_CLAMP(blend_clamp) |
4493 S_028C70_BLEND_BYPASS(blend_bypass) |
4494 S_028C70_SIMPLE_FLOAT(1) |
4495 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4496 ntype != V_028C70_NUMBER_SNORM &&
4497 ntype != V_028C70_NUMBER_SRGB &&
4498 format != V_028C70_COLOR_8_24 &&
4499 format != V_028C70_COLOR_24_8) |
4500 S_028C70_NUMBER_TYPE(ntype) |
4501 S_028C70_ENDIAN(endian);
4502 if (radv_image_has_fmask(iview->image)) {
4503 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4504 if (device->physical_device->rad_info.chip_class == GFX6) {
4505 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4506 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4507 }
4508
4509 if (radv_image_is_tc_compat_cmask(iview->image)) {
4510 /* Allow the texture block to read FMASK directly
4511 * without decompressing it. This bit must be cleared
4512 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4513 * otherwise the operation doesn't happen.
4514 */
4515 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4516
4517 /* Set CMASK into a tiling format that allows the
4518 * texture block to read it.
4519 */
4520 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4521 }
4522 }
4523
4524 if (radv_image_has_cmask(iview->image) &&
4525 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4526 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4527
4528 if (radv_dcc_enabled(iview->image, iview->base_mip))
4529 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4530
4531 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4532
4533 /* This must be set for fast clear to work without FMASK. */
4534 if (!radv_image_has_fmask(iview->image) &&
4535 device->physical_device->rad_info.chip_class == GFX6) {
4536 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4537 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4538 }
4539
4540 if (device->physical_device->rad_info.chip_class >= GFX9) {
4541 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4542
4543 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4544 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4545 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4546 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4547
4548 if (device->physical_device->rad_info.chip_class >= GFX10) {
4549 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4550
4551 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4552 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4553 S_028EE0_RESOURCE_LEVEL(1);
4554 } else {
4555 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4556 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4557 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4558 }
4559
4560 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4561 S_028C68_MIP0_HEIGHT(height - 1) |
4562 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4563 }
4564 }
4565
4566 static unsigned
4567 radv_calc_decompress_on_z_planes(struct radv_device *device,
4568 struct radv_image_view *iview)
4569 {
4570 unsigned max_zplanes = 0;
4571
4572 assert(radv_image_is_tc_compat_htile(iview->image));
4573
4574 if (device->physical_device->rad_info.chip_class >= GFX9) {
4575 /* Default value for 32-bit depth surfaces. */
4576 max_zplanes = 4;
4577
4578 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4579 iview->image->info.samples > 1)
4580 max_zplanes = 2;
4581
4582 max_zplanes = max_zplanes + 1;
4583 } else {
4584 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4585 /* Do not enable Z plane compression for 16-bit depth
4586 * surfaces because isn't supported on GFX8. Only
4587 * 32-bit depth surfaces are supported by the hardware.
4588 * This allows to maintain shader compatibility and to
4589 * reduce the number of depth decompressions.
4590 */
4591 max_zplanes = 1;
4592 } else {
4593 if (iview->image->info.samples <= 1)
4594 max_zplanes = 5;
4595 else if (iview->image->info.samples <= 4)
4596 max_zplanes = 3;
4597 else
4598 max_zplanes = 2;
4599 }
4600 }
4601
4602 return max_zplanes;
4603 }
4604
4605 static void
4606 radv_initialise_ds_surface(struct radv_device *device,
4607 struct radv_ds_buffer_info *ds,
4608 struct radv_image_view *iview)
4609 {
4610 unsigned level = iview->base_mip;
4611 unsigned format, stencil_format;
4612 uint64_t va, s_offs, z_offs;
4613 bool stencil_only = false;
4614 const struct radv_image_plane *plane = &iview->image->planes[0];
4615 const struct radeon_surf *surf = &plane->surface;
4616
4617 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4618
4619 memset(ds, 0, sizeof(*ds));
4620 switch (iview->image->vk_format) {
4621 case VK_FORMAT_D24_UNORM_S8_UINT:
4622 case VK_FORMAT_X8_D24_UNORM_PACK32:
4623 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4624 ds->offset_scale = 2.0f;
4625 break;
4626 case VK_FORMAT_D16_UNORM:
4627 case VK_FORMAT_D16_UNORM_S8_UINT:
4628 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4629 ds->offset_scale = 4.0f;
4630 break;
4631 case VK_FORMAT_D32_SFLOAT:
4632 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4633 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4634 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4635 ds->offset_scale = 1.0f;
4636 break;
4637 case VK_FORMAT_S8_UINT:
4638 stencil_only = true;
4639 break;
4640 default:
4641 break;
4642 }
4643
4644 format = radv_translate_dbformat(iview->image->vk_format);
4645 stencil_format = surf->has_stencil ?
4646 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4647
4648 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4649 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4650 S_028008_SLICE_MAX(max_slice);
4651 if (device->physical_device->rad_info.chip_class >= GFX10) {
4652 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4653 S_028008_SLICE_MAX_HI(max_slice >> 11);
4654 }
4655
4656 ds->db_htile_data_base = 0;
4657 ds->db_htile_surface = 0;
4658
4659 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4660 s_offs = z_offs = va;
4661
4662 if (device->physical_device->rad_info.chip_class >= GFX9) {
4663 assert(surf->u.gfx9.surf_offset == 0);
4664 s_offs += surf->u.gfx9.stencil_offset;
4665
4666 ds->db_z_info = S_028038_FORMAT(format) |
4667 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4668 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4669 S_028038_MAXMIP(iview->image->info.levels - 1) |
4670 S_028038_ZRANGE_PRECISION(1);
4671 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4672 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4673
4674 if (device->physical_device->rad_info.chip_class == GFX9) {
4675 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4676 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4677 }
4678
4679 ds->db_depth_view |= S_028008_MIPID(level);
4680 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4681 S_02801C_Y_MAX(iview->image->info.height - 1);
4682
4683 if (radv_htile_enabled(iview->image, level)) {
4684 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4685
4686 if (radv_image_is_tc_compat_htile(iview->image)) {
4687 unsigned max_zplanes =
4688 radv_calc_decompress_on_z_planes(device, iview);
4689
4690 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4691
4692 if (device->physical_device->rad_info.chip_class >= GFX10) {
4693 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4694 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4695 } else {
4696 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4697 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4698 }
4699 }
4700
4701 if (!surf->has_stencil)
4702 /* Use all of the htile_buffer for depth if there's no stencil. */
4703 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4704 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4705 iview->image->htile_offset;
4706 ds->db_htile_data_base = va >> 8;
4707 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4708 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4709
4710 if (device->physical_device->rad_info.chip_class == GFX9) {
4711 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4712 }
4713 }
4714 } else {
4715 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4716
4717 if (stencil_only)
4718 level_info = &surf->u.legacy.stencil_level[level];
4719
4720 z_offs += surf->u.legacy.level[level].offset;
4721 s_offs += surf->u.legacy.stencil_level[level].offset;
4722
4723 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4724 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4725 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4726
4727 if (iview->image->info.samples > 1)
4728 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4729
4730 if (device->physical_device->rad_info.chip_class >= GFX7) {
4731 struct radeon_info *info = &device->physical_device->rad_info;
4732 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4733 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4734 unsigned macro_index = surf->u.legacy.macro_tile_index;
4735 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4736 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4737 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4738
4739 if (stencil_only)
4740 tile_mode = stencil_tile_mode;
4741
4742 ds->db_depth_info |=
4743 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4744 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4745 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4746 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4747 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4748 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4749 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4750 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4751 } else {
4752 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4753 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4754 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4755 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4756 if (stencil_only)
4757 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4758 }
4759
4760 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4761 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4762 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4763
4764 if (radv_htile_enabled(iview->image, level)) {
4765 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4766
4767 if (!surf->has_stencil &&
4768 !radv_image_is_tc_compat_htile(iview->image))
4769 /* Use all of the htile_buffer for depth if there's no stencil. */
4770 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4771
4772 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4773 iview->image->htile_offset;
4774 ds->db_htile_data_base = va >> 8;
4775 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4776
4777 if (radv_image_is_tc_compat_htile(iview->image)) {
4778 unsigned max_zplanes =
4779 radv_calc_decompress_on_z_planes(device, iview);
4780
4781 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4782 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4783 }
4784 }
4785 }
4786
4787 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4788 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4789 }
4790
4791 VkResult radv_CreateFramebuffer(
4792 VkDevice _device,
4793 const VkFramebufferCreateInfo* pCreateInfo,
4794 const VkAllocationCallbacks* pAllocator,
4795 VkFramebuffer* pFramebuffer)
4796 {
4797 RADV_FROM_HANDLE(radv_device, device, _device);
4798 struct radv_framebuffer *framebuffer;
4799
4800 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4801
4802 size_t size = sizeof(*framebuffer) +
4803 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4804 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4805 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4806 if (framebuffer == NULL)
4807 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4808
4809 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4810 framebuffer->width = pCreateInfo->width;
4811 framebuffer->height = pCreateInfo->height;
4812 framebuffer->layers = pCreateInfo->layers;
4813 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4814 VkImageView _iview = pCreateInfo->pAttachments[i];
4815 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4816 framebuffer->attachments[i].attachment = iview;
4817 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4818 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4819 } else {
4820 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4821 }
4822 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4823 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4824 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4825 }
4826
4827 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4828 return VK_SUCCESS;
4829 }
4830
4831 void radv_DestroyFramebuffer(
4832 VkDevice _device,
4833 VkFramebuffer _fb,
4834 const VkAllocationCallbacks* pAllocator)
4835 {
4836 RADV_FROM_HANDLE(radv_device, device, _device);
4837 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4838
4839 if (!fb)
4840 return;
4841 vk_free2(&device->alloc, pAllocator, fb);
4842 }
4843
4844 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4845 {
4846 switch (address_mode) {
4847 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4848 return V_008F30_SQ_TEX_WRAP;
4849 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4850 return V_008F30_SQ_TEX_MIRROR;
4851 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4852 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4853 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4854 return V_008F30_SQ_TEX_CLAMP_BORDER;
4855 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4856 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4857 default:
4858 unreachable("illegal tex wrap mode");
4859 break;
4860 }
4861 }
4862
4863 static unsigned
4864 radv_tex_compare(VkCompareOp op)
4865 {
4866 switch (op) {
4867 case VK_COMPARE_OP_NEVER:
4868 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4869 case VK_COMPARE_OP_LESS:
4870 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4871 case VK_COMPARE_OP_EQUAL:
4872 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4873 case VK_COMPARE_OP_LESS_OR_EQUAL:
4874 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4875 case VK_COMPARE_OP_GREATER:
4876 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4877 case VK_COMPARE_OP_NOT_EQUAL:
4878 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4879 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4880 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4881 case VK_COMPARE_OP_ALWAYS:
4882 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4883 default:
4884 unreachable("illegal compare mode");
4885 break;
4886 }
4887 }
4888
4889 static unsigned
4890 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4891 {
4892 switch (filter) {
4893 case VK_FILTER_NEAREST:
4894 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4895 V_008F38_SQ_TEX_XY_FILTER_POINT);
4896 case VK_FILTER_LINEAR:
4897 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4898 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4899 case VK_FILTER_CUBIC_IMG:
4900 default:
4901 fprintf(stderr, "illegal texture filter");
4902 return 0;
4903 }
4904 }
4905
4906 static unsigned
4907 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4908 {
4909 switch (mode) {
4910 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4911 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4912 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4913 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4914 default:
4915 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4916 }
4917 }
4918
4919 static unsigned
4920 radv_tex_bordercolor(VkBorderColor bcolor)
4921 {
4922 switch (bcolor) {
4923 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4924 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4925 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4926 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4927 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4928 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4929 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4930 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4931 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4932 default:
4933 break;
4934 }
4935 return 0;
4936 }
4937
4938 static unsigned
4939 radv_tex_aniso_filter(unsigned filter)
4940 {
4941 if (filter < 2)
4942 return 0;
4943 if (filter < 4)
4944 return 1;
4945 if (filter < 8)
4946 return 2;
4947 if (filter < 16)
4948 return 3;
4949 return 4;
4950 }
4951
4952 static unsigned
4953 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4954 {
4955 switch (mode) {
4956 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4957 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4958 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4959 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4960 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4961 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4962 default:
4963 break;
4964 }
4965 return 0;
4966 }
4967
4968 static uint32_t
4969 radv_get_max_anisotropy(struct radv_device *device,
4970 const VkSamplerCreateInfo *pCreateInfo)
4971 {
4972 if (device->force_aniso >= 0)
4973 return device->force_aniso;
4974
4975 if (pCreateInfo->anisotropyEnable &&
4976 pCreateInfo->maxAnisotropy > 1.0f)
4977 return (uint32_t)pCreateInfo->maxAnisotropy;
4978
4979 return 0;
4980 }
4981
4982 static void
4983 radv_init_sampler(struct radv_device *device,
4984 struct radv_sampler *sampler,
4985 const VkSamplerCreateInfo *pCreateInfo)
4986 {
4987 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4988 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4989 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4990 device->physical_device->rad_info.chip_class == GFX9;
4991 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4992
4993 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4994 vk_find_struct_const(pCreateInfo->pNext,
4995 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4996 if (sampler_reduction)
4997 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4998
4999 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5000 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5001 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5002 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5003 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5004 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5005 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5006 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5007 S_008F30_DISABLE_CUBE_WRAP(0) |
5008 S_008F30_COMPAT_MODE(compat_mode) |
5009 S_008F30_FILTER_MODE(filter_mode));
5010 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5011 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5012 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5013 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5014 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5015 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5016 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5017 S_008F38_MIP_POINT_PRECLAMP(0));
5018 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5019 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5020
5021 if (device->physical_device->rad_info.chip_class >= GFX10) {
5022 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5023 } else {
5024 sampler->state[2] |=
5025 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5026 S_008F38_FILTER_PREC_FIX(1) |
5027 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5028 }
5029 }
5030
5031 VkResult radv_CreateSampler(
5032 VkDevice _device,
5033 const VkSamplerCreateInfo* pCreateInfo,
5034 const VkAllocationCallbacks* pAllocator,
5035 VkSampler* pSampler)
5036 {
5037 RADV_FROM_HANDLE(radv_device, device, _device);
5038 struct radv_sampler *sampler;
5039
5040 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5041 vk_find_struct_const(pCreateInfo->pNext,
5042 SAMPLER_YCBCR_CONVERSION_INFO);
5043
5044 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5045
5046 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5047 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5048 if (!sampler)
5049 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5050
5051 radv_init_sampler(device, sampler, pCreateInfo);
5052
5053 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5054 *pSampler = radv_sampler_to_handle(sampler);
5055
5056 return VK_SUCCESS;
5057 }
5058
5059 void radv_DestroySampler(
5060 VkDevice _device,
5061 VkSampler _sampler,
5062 const VkAllocationCallbacks* pAllocator)
5063 {
5064 RADV_FROM_HANDLE(radv_device, device, _device);
5065 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5066
5067 if (!sampler)
5068 return;
5069 vk_free2(&device->alloc, pAllocator, sampler);
5070 }
5071
5072 /* vk_icd.h does not declare this function, so we declare it here to
5073 * suppress Wmissing-prototypes.
5074 */
5075 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5076 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5077
5078 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5079 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5080 {
5081 /* For the full details on loader interface versioning, see
5082 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5083 * What follows is a condensed summary, to help you navigate the large and
5084 * confusing official doc.
5085 *
5086 * - Loader interface v0 is incompatible with later versions. We don't
5087 * support it.
5088 *
5089 * - In loader interface v1:
5090 * - The first ICD entrypoint called by the loader is
5091 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5092 * entrypoint.
5093 * - The ICD must statically expose no other Vulkan symbol unless it is
5094 * linked with -Bsymbolic.
5095 * - Each dispatchable Vulkan handle created by the ICD must be
5096 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5097 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5098 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5099 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5100 * such loader-managed surfaces.
5101 *
5102 * - Loader interface v2 differs from v1 in:
5103 * - The first ICD entrypoint called by the loader is
5104 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5105 * statically expose this entrypoint.
5106 *
5107 * - Loader interface v3 differs from v2 in:
5108 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5109 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5110 * because the loader no longer does so.
5111 */
5112 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5113 return VK_SUCCESS;
5114 }
5115
5116 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5117 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5118 int *pFD)
5119 {
5120 RADV_FROM_HANDLE(radv_device, device, _device);
5121 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5122
5123 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5124
5125 /* At the moment, we support only the below handle types. */
5126 assert(pGetFdInfo->handleType ==
5127 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5128 pGetFdInfo->handleType ==
5129 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5130
5131 bool ret = radv_get_memory_fd(device, memory, pFD);
5132 if (ret == false)
5133 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5134 return VK_SUCCESS;
5135 }
5136
5137 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5138 VkExternalMemoryHandleTypeFlagBits handleType,
5139 int fd,
5140 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5141 {
5142 RADV_FROM_HANDLE(radv_device, device, _device);
5143
5144 switch (handleType) {
5145 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5146 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5147 return VK_SUCCESS;
5148
5149 default:
5150 /* The valid usage section for this function says:
5151 *
5152 * "handleType must not be one of the handle types defined as
5153 * opaque."
5154 *
5155 * So opaque handle types fall into the default "unsupported" case.
5156 */
5157 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5158 }
5159 }
5160
5161 static VkResult radv_import_opaque_fd(struct radv_device *device,
5162 int fd,
5163 uint32_t *syncobj)
5164 {
5165 uint32_t syncobj_handle = 0;
5166 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5167 if (ret != 0)
5168 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5169
5170 if (*syncobj)
5171 device->ws->destroy_syncobj(device->ws, *syncobj);
5172
5173 *syncobj = syncobj_handle;
5174 close(fd);
5175
5176 return VK_SUCCESS;
5177 }
5178
5179 static VkResult radv_import_sync_fd(struct radv_device *device,
5180 int fd,
5181 uint32_t *syncobj)
5182 {
5183 /* If we create a syncobj we do it locally so that if we have an error, we don't
5184 * leave a syncobj in an undetermined state in the fence. */
5185 uint32_t syncobj_handle = *syncobj;
5186 if (!syncobj_handle) {
5187 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5188 if (ret) {
5189 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5190 }
5191 }
5192
5193 if (fd == -1) {
5194 device->ws->signal_syncobj(device->ws, syncobj_handle);
5195 } else {
5196 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5197 if (ret != 0)
5198 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5199 }
5200
5201 *syncobj = syncobj_handle;
5202 if (fd != -1)
5203 close(fd);
5204
5205 return VK_SUCCESS;
5206 }
5207
5208 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5209 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5210 {
5211 RADV_FROM_HANDLE(radv_device, device, _device);
5212 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5213 uint32_t *syncobj_dst = NULL;
5214
5215 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5216 syncobj_dst = &sem->temp_syncobj;
5217 } else {
5218 syncobj_dst = &sem->syncobj;
5219 }
5220
5221 switch(pImportSemaphoreFdInfo->handleType) {
5222 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5223 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5224 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5225 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5226 default:
5227 unreachable("Unhandled semaphore handle type");
5228 }
5229 }
5230
5231 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5232 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5233 int *pFd)
5234 {
5235 RADV_FROM_HANDLE(radv_device, device, _device);
5236 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5237 int ret;
5238 uint32_t syncobj_handle;
5239
5240 if (sem->temp_syncobj)
5241 syncobj_handle = sem->temp_syncobj;
5242 else
5243 syncobj_handle = sem->syncobj;
5244
5245 switch(pGetFdInfo->handleType) {
5246 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5247 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5248 break;
5249 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5250 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5251 if (!ret) {
5252 if (sem->temp_syncobj) {
5253 close (sem->temp_syncobj);
5254 sem->temp_syncobj = 0;
5255 } else {
5256 device->ws->reset_syncobj(device->ws, syncobj_handle);
5257 }
5258 }
5259 break;
5260 default:
5261 unreachable("Unhandled semaphore handle type");
5262 }
5263
5264 if (ret)
5265 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5266 return VK_SUCCESS;
5267 }
5268
5269 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5270 VkPhysicalDevice physicalDevice,
5271 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5272 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5273 {
5274 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5275
5276 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5277 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5278 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5279 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5280 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5281 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5282 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5283 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5284 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5285 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5286 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5287 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5288 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5289 } else {
5290 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5291 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5292 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5293 }
5294 }
5295
5296 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5297 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5298 {
5299 RADV_FROM_HANDLE(radv_device, device, _device);
5300 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5301 uint32_t *syncobj_dst = NULL;
5302
5303
5304 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5305 syncobj_dst = &fence->temp_syncobj;
5306 } else {
5307 syncobj_dst = &fence->syncobj;
5308 }
5309
5310 switch(pImportFenceFdInfo->handleType) {
5311 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5312 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5313 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5314 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5315 default:
5316 unreachable("Unhandled fence handle type");
5317 }
5318 }
5319
5320 VkResult radv_GetFenceFdKHR(VkDevice _device,
5321 const VkFenceGetFdInfoKHR *pGetFdInfo,
5322 int *pFd)
5323 {
5324 RADV_FROM_HANDLE(radv_device, device, _device);
5325 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5326 int ret;
5327 uint32_t syncobj_handle;
5328
5329 if (fence->temp_syncobj)
5330 syncobj_handle = fence->temp_syncobj;
5331 else
5332 syncobj_handle = fence->syncobj;
5333
5334 switch(pGetFdInfo->handleType) {
5335 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5336 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5337 break;
5338 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5339 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5340 if (!ret) {
5341 if (fence->temp_syncobj) {
5342 close (fence->temp_syncobj);
5343 fence->temp_syncobj = 0;
5344 } else {
5345 device->ws->reset_syncobj(device->ws, syncobj_handle);
5346 }
5347 }
5348 break;
5349 default:
5350 unreachable("Unhandled fence handle type");
5351 }
5352
5353 if (ret)
5354 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5355 return VK_SUCCESS;
5356 }
5357
5358 void radv_GetPhysicalDeviceExternalFenceProperties(
5359 VkPhysicalDevice physicalDevice,
5360 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5361 VkExternalFenceProperties *pExternalFenceProperties)
5362 {
5363 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5364
5365 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5366 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5367 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5368 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5369 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5370 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5371 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5372 } else {
5373 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5374 pExternalFenceProperties->compatibleHandleTypes = 0;
5375 pExternalFenceProperties->externalFenceFeatures = 0;
5376 }
5377 }
5378
5379 VkResult
5380 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5381 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5382 const VkAllocationCallbacks* pAllocator,
5383 VkDebugReportCallbackEXT* pCallback)
5384 {
5385 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5386 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5387 pCreateInfo, pAllocator, &instance->alloc,
5388 pCallback);
5389 }
5390
5391 void
5392 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5393 VkDebugReportCallbackEXT _callback,
5394 const VkAllocationCallbacks* pAllocator)
5395 {
5396 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5397 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5398 _callback, pAllocator, &instance->alloc);
5399 }
5400
5401 void
5402 radv_DebugReportMessageEXT(VkInstance _instance,
5403 VkDebugReportFlagsEXT flags,
5404 VkDebugReportObjectTypeEXT objectType,
5405 uint64_t object,
5406 size_t location,
5407 int32_t messageCode,
5408 const char* pLayerPrefix,
5409 const char* pMessage)
5410 {
5411 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5412 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5413 object, location, messageCode, pLayerPrefix, pMessage);
5414 }
5415
5416 void
5417 radv_GetDeviceGroupPeerMemoryFeatures(
5418 VkDevice device,
5419 uint32_t heapIndex,
5420 uint32_t localDeviceIndex,
5421 uint32_t remoteDeviceIndex,
5422 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5423 {
5424 assert(localDeviceIndex == remoteDeviceIndex);
5425
5426 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5427 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5428 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5429 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5430 }
5431
5432 static const VkTimeDomainEXT radv_time_domains[] = {
5433 VK_TIME_DOMAIN_DEVICE_EXT,
5434 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5435 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5436 };
5437
5438 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5439 VkPhysicalDevice physicalDevice,
5440 uint32_t *pTimeDomainCount,
5441 VkTimeDomainEXT *pTimeDomains)
5442 {
5443 int d;
5444 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5445
5446 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5447 vk_outarray_append(&out, i) {
5448 *i = radv_time_domains[d];
5449 }
5450 }
5451
5452 return vk_outarray_status(&out);
5453 }
5454
5455 static uint64_t
5456 radv_clock_gettime(clockid_t clock_id)
5457 {
5458 struct timespec current;
5459 int ret;
5460
5461 ret = clock_gettime(clock_id, &current);
5462 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5463 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5464 if (ret < 0)
5465 return 0;
5466
5467 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5468 }
5469
5470 VkResult radv_GetCalibratedTimestampsEXT(
5471 VkDevice _device,
5472 uint32_t timestampCount,
5473 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5474 uint64_t *pTimestamps,
5475 uint64_t *pMaxDeviation)
5476 {
5477 RADV_FROM_HANDLE(radv_device, device, _device);
5478 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5479 int d;
5480 uint64_t begin, end;
5481 uint64_t max_clock_period = 0;
5482
5483 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5484
5485 for (d = 0; d < timestampCount; d++) {
5486 switch (pTimestampInfos[d].timeDomain) {
5487 case VK_TIME_DOMAIN_DEVICE_EXT:
5488 pTimestamps[d] = device->ws->query_value(device->ws,
5489 RADEON_TIMESTAMP);
5490 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5491 max_clock_period = MAX2(max_clock_period, device_period);
5492 break;
5493 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5494 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5495 max_clock_period = MAX2(max_clock_period, 1);
5496 break;
5497
5498 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5499 pTimestamps[d] = begin;
5500 break;
5501 default:
5502 pTimestamps[d] = 0;
5503 break;
5504 }
5505 }
5506
5507 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5508
5509 /*
5510 * The maximum deviation is the sum of the interval over which we
5511 * perform the sampling and the maximum period of any sampled
5512 * clock. That's because the maximum skew between any two sampled
5513 * clock edges is when the sampled clock with the largest period is
5514 * sampled at the end of that period but right at the beginning of the
5515 * sampling interval and some other clock is sampled right at the
5516 * begining of its sampling period and right at the end of the
5517 * sampling interval. Let's assume the GPU has the longest clock
5518 * period and that the application is sampling GPU and monotonic:
5519 *
5520 * s e
5521 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5522 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5523 *
5524 * g
5525 * 0 1 2 3
5526 * GPU -----_____-----_____-----_____-----_____
5527 *
5528 * m
5529 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5530 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5531 *
5532 * Interval <----------------->
5533 * Deviation <-------------------------->
5534 *
5535 * s = read(raw) 2
5536 * g = read(GPU) 1
5537 * m = read(monotonic) 2
5538 * e = read(raw) b
5539 *
5540 * We round the sample interval up by one tick to cover sampling error
5541 * in the interval clock
5542 */
5543
5544 uint64_t sample_interval = end - begin + 1;
5545
5546 *pMaxDeviation = sample_interval + max_clock_period;
5547
5548 return VK_SUCCESS;
5549 }
5550
5551 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5552 VkPhysicalDevice physicalDevice,
5553 VkSampleCountFlagBits samples,
5554 VkMultisamplePropertiesEXT* pMultisampleProperties)
5555 {
5556 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5557 VK_SAMPLE_COUNT_4_BIT |
5558 VK_SAMPLE_COUNT_8_BIT)) {
5559 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5560 } else {
5561 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5562 }
5563 }