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radv: put back VGT_FLUSH at ring init on gfx10
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
367
368 /* Out-of-order primitive rasterization. */
369 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
370 device->rad_info.max_se >= 2;
371 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
372 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
373
374 device->dcc_msaa_allowed =
375 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
376
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
379 (device->rad_info.chip_class >= GFX8 &&
380 device->rad_info.me_fw_feature >= 41);
381
382 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
383 device->rad_info.chip_class >= GFX10;
384
385 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
386
387 radv_physical_device_init_mem_types(device);
388 radv_fill_device_extension_table(device, &device->supported_extensions);
389
390 device->bus_info = *drm_device->businfo.pci;
391
392 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
393 ac_print_gpu_info(&device->rad_info);
394
395 /* The WSI is structured as a layer on top of the driver, so this has
396 * to be the last part of initialization (at least until we get other
397 * semi-layers).
398 */
399 result = radv_init_wsi(device);
400 if (result != VK_SUCCESS) {
401 device->ws->destroy(device->ws);
402 vk_error(instance, result);
403 goto fail;
404 }
405
406 return VK_SUCCESS;
407
408 fail:
409 close(fd);
410 if (master_fd != -1)
411 close(master_fd);
412 return result;
413 }
414
415 static void
416 radv_physical_device_finish(struct radv_physical_device *device)
417 {
418 radv_finish_wsi(device);
419 device->ws->destroy(device->ws);
420 disk_cache_destroy(device->disk_cache);
421 close(device->local_fd);
422 if (device->master_fd != -1)
423 close(device->master_fd);
424 }
425
426 static void *
427 default_alloc_func(void *pUserData, size_t size, size_t align,
428 VkSystemAllocationScope allocationScope)
429 {
430 return malloc(size);
431 }
432
433 static void *
434 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
435 size_t align, VkSystemAllocationScope allocationScope)
436 {
437 return realloc(pOriginal, size);
438 }
439
440 static void
441 default_free_func(void *pUserData, void *pMemory)
442 {
443 free(pMemory);
444 }
445
446 static const VkAllocationCallbacks default_alloc = {
447 .pUserData = NULL,
448 .pfnAllocation = default_alloc_func,
449 .pfnReallocation = default_realloc_func,
450 .pfnFree = default_free_func,
451 };
452
453 static const struct debug_control radv_debug_options[] = {
454 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
455 {"nodcc", RADV_DEBUG_NO_DCC},
456 {"shaders", RADV_DEBUG_DUMP_SHADERS},
457 {"nocache", RADV_DEBUG_NO_CACHE},
458 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
459 {"nohiz", RADV_DEBUG_NO_HIZ},
460 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
461 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
462 {"allbos", RADV_DEBUG_ALL_BOS},
463 {"noibs", RADV_DEBUG_NO_IBS},
464 {"spirv", RADV_DEBUG_DUMP_SPIRV},
465 {"vmfaults", RADV_DEBUG_VM_FAULTS},
466 {"zerovram", RADV_DEBUG_ZERO_VRAM},
467 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
468 {"nosisched", RADV_DEBUG_NO_SISCHED},
469 {"preoptir", RADV_DEBUG_PREOPTIR},
470 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
471 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
472 {"info", RADV_DEBUG_INFO},
473 {"errors", RADV_DEBUG_ERRORS},
474 {"startup", RADV_DEBUG_STARTUP},
475 {"checkir", RADV_DEBUG_CHECKIR},
476 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
477 {"nobinning", RADV_DEBUG_NOBINNING},
478 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
479 {"nongg", RADV_DEBUG_NO_NGG},
480 {NULL, 0}
481 };
482
483 const char *
484 radv_get_debug_option_name(int id)
485 {
486 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
487 return radv_debug_options[id].string;
488 }
489
490 static const struct debug_control radv_perftest_options[] = {
491 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
492 {"sisched", RADV_PERFTEST_SISCHED},
493 {"localbos", RADV_PERFTEST_LOCAL_BOS},
494 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
495 {"bolist", RADV_PERFTEST_BO_LIST},
496 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
497 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
498 {NULL, 0}
499 };
500
501 const char *
502 radv_get_perftest_option_name(int id)
503 {
504 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
505 return radv_perftest_options[id].string;
506 }
507
508 static void
509 radv_handle_per_app_options(struct radv_instance *instance,
510 const VkApplicationInfo *info)
511 {
512 const char *name = info ? info->pApplicationName : NULL;
513
514 if (!name)
515 return;
516
517 if (!strcmp(name, "Talos - Linux - 32bit") ||
518 !strcmp(name, "Talos - Linux - 64bit")) {
519 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
520 /* Force enable LLVM sisched for Talos because it looks
521 * safe and it gives few more FPS.
522 */
523 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
524 }
525 } else if (!strcmp(name, "DOOM_VFR")) {
526 /* Work around a Doom VFR game bug */
527 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
528 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
529 /* Workaround for a WaW hazard when LLVM moves/merges
530 * load/store memory operations.
531 * See https://reviews.llvm.org/D61313
532 */
533 if (HAVE_LLVM < 0x900)
534 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
535 }
536 }
537
538 static int radv_get_instance_extension_index(const char *name)
539 {
540 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
541 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
542 return i;
543 }
544 return -1;
545 }
546
547 static const char radv_dri_options_xml[] =
548 DRI_CONF_BEGIN
549 DRI_CONF_SECTION_QUALITY
550 DRI_CONF_ADAPTIVE_SYNC("true")
551 DRI_CONF_SECTION_END
552 DRI_CONF_END;
553
554 static void radv_init_dri_options(struct radv_instance *instance)
555 {
556 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
557 driParseConfigFiles(&instance->dri_options,
558 &instance->available_dri_options,
559 0, "radv", NULL);
560 }
561
562 VkResult radv_CreateInstance(
563 const VkInstanceCreateInfo* pCreateInfo,
564 const VkAllocationCallbacks* pAllocator,
565 VkInstance* pInstance)
566 {
567 struct radv_instance *instance;
568 VkResult result;
569
570 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
571
572 uint32_t client_version;
573 if (pCreateInfo->pApplicationInfo &&
574 pCreateInfo->pApplicationInfo->apiVersion != 0) {
575 client_version = pCreateInfo->pApplicationInfo->apiVersion;
576 } else {
577 client_version = VK_API_VERSION_1_0;
578 }
579
580 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
581 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
582 if (!instance)
583 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
584
585 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
586
587 if (pAllocator)
588 instance->alloc = *pAllocator;
589 else
590 instance->alloc = default_alloc;
591
592 instance->apiVersion = client_version;
593 instance->physicalDeviceCount = -1;
594
595 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
596 radv_debug_options);
597
598 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
599 radv_perftest_options);
600
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Created an instance");
604
605 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
606 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
607 int index = radv_get_instance_extension_index(ext_name);
608
609 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
610 vk_free2(&default_alloc, pAllocator, instance);
611 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
612 }
613
614 instance->enabled_extensions.extensions[index] = true;
615 }
616
617 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
618 if (result != VK_SUCCESS) {
619 vk_free2(&default_alloc, pAllocator, instance);
620 return vk_error(instance, result);
621 }
622
623 _mesa_locale_init();
624 glsl_type_singleton_init_or_ref();
625
626 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
627
628 radv_init_dri_options(instance);
629 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
630
631 *pInstance = radv_instance_to_handle(instance);
632
633 return VK_SUCCESS;
634 }
635
636 void radv_DestroyInstance(
637 VkInstance _instance,
638 const VkAllocationCallbacks* pAllocator)
639 {
640 RADV_FROM_HANDLE(radv_instance, instance, _instance);
641
642 if (!instance)
643 return;
644
645 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
646 radv_physical_device_finish(instance->physicalDevices + i);
647 }
648
649 VG(VALGRIND_DESTROY_MEMPOOL(instance));
650
651 glsl_type_singleton_decref();
652 _mesa_locale_fini();
653
654 driDestroyOptionCache(&instance->dri_options);
655 driDestroyOptionInfo(&instance->available_dri_options);
656
657 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
658
659 vk_free(&instance->alloc, instance);
660 }
661
662 static VkResult
663 radv_enumerate_devices(struct radv_instance *instance)
664 {
665 /* TODO: Check for more devices ? */
666 drmDevicePtr devices[8];
667 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
668 int max_devices;
669
670 instance->physicalDeviceCount = 0;
671
672 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
673
674 if (instance->debug_flags & RADV_DEBUG_STARTUP)
675 radv_logi("Found %d drm nodes", max_devices);
676
677 if (max_devices < 1)
678 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
679
680 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
681 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
682 devices[i]->bustype == DRM_BUS_PCI &&
683 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
684
685 result = radv_physical_device_init(instance->physicalDevices +
686 instance->physicalDeviceCount,
687 instance,
688 devices[i]);
689 if (result == VK_SUCCESS)
690 ++instance->physicalDeviceCount;
691 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 break;
693 }
694 }
695 drmFreeDevices(devices, max_devices);
696
697 return result;
698 }
699
700 VkResult radv_EnumeratePhysicalDevices(
701 VkInstance _instance,
702 uint32_t* pPhysicalDeviceCount,
703 VkPhysicalDevice* pPhysicalDevices)
704 {
705 RADV_FROM_HANDLE(radv_instance, instance, _instance);
706 VkResult result;
707
708 if (instance->physicalDeviceCount < 0) {
709 result = radv_enumerate_devices(instance);
710 if (result != VK_SUCCESS &&
711 result != VK_ERROR_INCOMPATIBLE_DRIVER)
712 return result;
713 }
714
715 if (!pPhysicalDevices) {
716 *pPhysicalDeviceCount = instance->physicalDeviceCount;
717 } else {
718 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
719 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
720 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
721 }
722
723 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
724 : VK_SUCCESS;
725 }
726
727 VkResult radv_EnumeratePhysicalDeviceGroups(
728 VkInstance _instance,
729 uint32_t* pPhysicalDeviceGroupCount,
730 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
731 {
732 RADV_FROM_HANDLE(radv_instance, instance, _instance);
733 VkResult result;
734
735 if (instance->physicalDeviceCount < 0) {
736 result = radv_enumerate_devices(instance);
737 if (result != VK_SUCCESS &&
738 result != VK_ERROR_INCOMPATIBLE_DRIVER)
739 return result;
740 }
741
742 if (!pPhysicalDeviceGroupProperties) {
743 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
744 } else {
745 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
746 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
747 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
748 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
749 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
750 }
751 }
752 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
753 : VK_SUCCESS;
754 }
755
756 void radv_GetPhysicalDeviceFeatures(
757 VkPhysicalDevice physicalDevice,
758 VkPhysicalDeviceFeatures* pFeatures)
759 {
760 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
761 memset(pFeatures, 0, sizeof(*pFeatures));
762
763 *pFeatures = (VkPhysicalDeviceFeatures) {
764 .robustBufferAccess = true,
765 .fullDrawIndexUint32 = true,
766 .imageCubeArray = true,
767 .independentBlend = true,
768 .geometryShader = true,
769 .tessellationShader = true,
770 .sampleRateShading = true,
771 .dualSrcBlend = true,
772 .logicOp = true,
773 .multiDrawIndirect = true,
774 .drawIndirectFirstInstance = true,
775 .depthClamp = true,
776 .depthBiasClamp = true,
777 .fillModeNonSolid = true,
778 .depthBounds = true,
779 .wideLines = true,
780 .largePoints = true,
781 .alphaToOne = true,
782 .multiViewport = true,
783 .samplerAnisotropy = true,
784 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
785 .textureCompressionASTC_LDR = false,
786 .textureCompressionBC = true,
787 .occlusionQueryPrecise = true,
788 .pipelineStatisticsQuery = true,
789 .vertexPipelineStoresAndAtomics = true,
790 .fragmentStoresAndAtomics = true,
791 .shaderTessellationAndGeometryPointSize = true,
792 .shaderImageGatherExtended = true,
793 .shaderStorageImageExtendedFormats = true,
794 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
795 .shaderUniformBufferArrayDynamicIndexing = true,
796 .shaderSampledImageArrayDynamicIndexing = true,
797 .shaderStorageBufferArrayDynamicIndexing = true,
798 .shaderStorageImageArrayDynamicIndexing = true,
799 .shaderStorageImageReadWithoutFormat = true,
800 .shaderStorageImageWriteWithoutFormat = true,
801 .shaderClipDistance = true,
802 .shaderCullDistance = true,
803 .shaderFloat64 = true,
804 .shaderInt64 = true,
805 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
806 .sparseBinding = true,
807 .variableMultisampleRate = true,
808 .inheritedQueries = true,
809 };
810 }
811
812 void radv_GetPhysicalDeviceFeatures2(
813 VkPhysicalDevice physicalDevice,
814 VkPhysicalDeviceFeatures2 *pFeatures)
815 {
816 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
817 vk_foreach_struct(ext, pFeatures->pNext) {
818 switch (ext->sType) {
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
820 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
821 features->variablePointersStorageBuffer = true;
822 features->variablePointers = true;
823 break;
824 }
825 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
826 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
827 features->multiview = true;
828 features->multiviewGeometryShader = true;
829 features->multiviewTessellationShader = true;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
833 VkPhysicalDeviceShaderDrawParametersFeatures *features =
834 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
835 features->shaderDrawParameters = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
839 VkPhysicalDeviceProtectedMemoryFeatures *features =
840 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
841 features->protectedMemory = false;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
845 VkPhysicalDevice16BitStorageFeatures *features =
846 (VkPhysicalDevice16BitStorageFeatures*)ext;
847 bool enabled = pdevice->rad_info.chip_class >= GFX8;
848 features->storageBuffer16BitAccess = enabled;
849 features->uniformAndStorageBuffer16BitAccess = enabled;
850 features->storagePushConstant16 = enabled;
851 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
852 break;
853 }
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
855 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
856 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
857 features->samplerYcbcrConversion = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
861 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
862 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
863 features->shaderInputAttachmentArrayDynamicIndexing = true;
864 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
865 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
866 features->shaderUniformBufferArrayNonUniformIndexing = true;
867 features->shaderSampledImageArrayNonUniformIndexing = true;
868 features->shaderStorageBufferArrayNonUniformIndexing = true;
869 features->shaderStorageImageArrayNonUniformIndexing = true;
870 features->shaderInputAttachmentArrayNonUniformIndexing = true;
871 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
872 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
873 features->descriptorBindingUniformBufferUpdateAfterBind = true;
874 features->descriptorBindingSampledImageUpdateAfterBind = true;
875 features->descriptorBindingStorageImageUpdateAfterBind = true;
876 features->descriptorBindingStorageBufferUpdateAfterBind = true;
877 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
878 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
879 features->descriptorBindingUpdateUnusedWhilePending = true;
880 features->descriptorBindingPartiallyBound = true;
881 features->descriptorBindingVariableDescriptorCount = true;
882 features->runtimeDescriptorArray = true;
883 break;
884 }
885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
886 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
887 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
888 features->conditionalRendering = true;
889 features->inheritedConditionalRendering = false;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
893 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
894 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
895 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
896 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
897 break;
898 }
899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
900 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
901 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
902 features->transformFeedback = true;
903 features->geometryStreams = true;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
907 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
908 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
909 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
910 break;
911 }
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
913 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
914 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
915 features->memoryPriority = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
919 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
920 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
921 features->bufferDeviceAddress = true;
922 features->bufferDeviceAddressCaptureReplay = false;
923 features->bufferDeviceAddressMultiDevice = false;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
927 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
928 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
929 features->depthClipEnable = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
933 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
934 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
935 features->hostQueryReset = true;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
939 VkPhysicalDevice8BitStorageFeaturesKHR *features =
940 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
941 bool enabled = pdevice->rad_info.chip_class >= GFX8;
942 features->storageBuffer8BitAccess = enabled;
943 features->uniformAndStorageBuffer8BitAccess = enabled;
944 features->storagePushConstant8 = enabled;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
948 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
949 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
950 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
951 features->shaderInt8 = true;
952 break;
953 }
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
955 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
956 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
957 /* TODO: Enable this once the driver supports 64-bit
958 * compare&swap atomic operations.
959 */
960 features->shaderBufferInt64Atomics = false;
961 features->shaderSharedInt64Atomics = false;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
965 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
966 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
967
968 features->inlineUniformBlock = true;
969 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
973 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
974 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
975 features->computeDerivativeGroupQuads = false;
976 features->computeDerivativeGroupLinear = true;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
980 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
981 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
982 features->ycbcrImageArrays = true;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
986 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
987 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
988 features->uniformBufferStandardLayout = true;
989 break;
990 }
991 default:
992 break;
993 }
994 }
995 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
996 }
997
998 void radv_GetPhysicalDeviceProperties(
999 VkPhysicalDevice physicalDevice,
1000 VkPhysicalDeviceProperties* pProperties)
1001 {
1002 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1003 VkSampleCountFlags sample_counts = 0xf;
1004
1005 /* make sure that the entire descriptor set is addressable with a signed
1006 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1007 * be at most 2 GiB. the combined image & samples object count as one of
1008 * both. This limit is for the pipeline layout, not for the set layout, but
1009 * there is no set limit, so we just set a pipeline limit. I don't think
1010 * any app is going to hit this soon. */
1011 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1012 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1013 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1014 32 /* sampler, largest when combined with image */ +
1015 64 /* sampled image */ +
1016 64 /* storage image */);
1017
1018 VkPhysicalDeviceLimits limits = {
1019 .maxImageDimension1D = (1 << 14),
1020 .maxImageDimension2D = (1 << 14),
1021 .maxImageDimension3D = (1 << 11),
1022 .maxImageDimensionCube = (1 << 14),
1023 .maxImageArrayLayers = (1 << 11),
1024 .maxTexelBufferElements = 128 * 1024 * 1024,
1025 .maxUniformBufferRange = UINT32_MAX,
1026 .maxStorageBufferRange = UINT32_MAX,
1027 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1028 .maxMemoryAllocationCount = UINT32_MAX,
1029 .maxSamplerAllocationCount = 64 * 1024,
1030 .bufferImageGranularity = 64, /* A cache line */
1031 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1032 .maxBoundDescriptorSets = MAX_SETS,
1033 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1034 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1035 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1036 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1037 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1038 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1039 .maxPerStageResources = max_descriptor_set_size,
1040 .maxDescriptorSetSamplers = max_descriptor_set_size,
1041 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1042 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1043 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1044 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1045 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1046 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1047 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1048 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1049 .maxVertexInputBindings = MAX_VBS,
1050 .maxVertexInputAttributeOffset = 2047,
1051 .maxVertexInputBindingStride = 2048,
1052 .maxVertexOutputComponents = 128,
1053 .maxTessellationGenerationLevel = 64,
1054 .maxTessellationPatchSize = 32,
1055 .maxTessellationControlPerVertexInputComponents = 128,
1056 .maxTessellationControlPerVertexOutputComponents = 128,
1057 .maxTessellationControlPerPatchOutputComponents = 120,
1058 .maxTessellationControlTotalOutputComponents = 4096,
1059 .maxTessellationEvaluationInputComponents = 128,
1060 .maxTessellationEvaluationOutputComponents = 128,
1061 .maxGeometryShaderInvocations = 127,
1062 .maxGeometryInputComponents = 64,
1063 .maxGeometryOutputComponents = 128,
1064 .maxGeometryOutputVertices = 256,
1065 .maxGeometryTotalOutputComponents = 1024,
1066 .maxFragmentInputComponents = 128,
1067 .maxFragmentOutputAttachments = 8,
1068 .maxFragmentDualSrcAttachments = 1,
1069 .maxFragmentCombinedOutputResources = 8,
1070 .maxComputeSharedMemorySize = 32768,
1071 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1072 .maxComputeWorkGroupInvocations = 2048,
1073 .maxComputeWorkGroupSize = {
1074 2048,
1075 2048,
1076 2048
1077 },
1078 .subPixelPrecisionBits = 8,
1079 .subTexelPrecisionBits = 8,
1080 .mipmapPrecisionBits = 8,
1081 .maxDrawIndexedIndexValue = UINT32_MAX,
1082 .maxDrawIndirectCount = UINT32_MAX,
1083 .maxSamplerLodBias = 16,
1084 .maxSamplerAnisotropy = 16,
1085 .maxViewports = MAX_VIEWPORTS,
1086 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1087 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1088 .viewportSubPixelBits = 8,
1089 .minMemoryMapAlignment = 4096, /* A page */
1090 .minTexelBufferOffsetAlignment = 1,
1091 .minUniformBufferOffsetAlignment = 4,
1092 .minStorageBufferOffsetAlignment = 4,
1093 .minTexelOffset = -32,
1094 .maxTexelOffset = 31,
1095 .minTexelGatherOffset = -32,
1096 .maxTexelGatherOffset = 31,
1097 .minInterpolationOffset = -2,
1098 .maxInterpolationOffset = 2,
1099 .subPixelInterpolationOffsetBits = 8,
1100 .maxFramebufferWidth = (1 << 14),
1101 .maxFramebufferHeight = (1 << 14),
1102 .maxFramebufferLayers = (1 << 10),
1103 .framebufferColorSampleCounts = sample_counts,
1104 .framebufferDepthSampleCounts = sample_counts,
1105 .framebufferStencilSampleCounts = sample_counts,
1106 .framebufferNoAttachmentsSampleCounts = sample_counts,
1107 .maxColorAttachments = MAX_RTS,
1108 .sampledImageColorSampleCounts = sample_counts,
1109 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1110 .sampledImageDepthSampleCounts = sample_counts,
1111 .sampledImageStencilSampleCounts = sample_counts,
1112 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1113 .maxSampleMaskWords = 1,
1114 .timestampComputeAndGraphics = true,
1115 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1116 .maxClipDistances = 8,
1117 .maxCullDistances = 8,
1118 .maxCombinedClipAndCullDistances = 8,
1119 .discreteQueuePriorities = 2,
1120 .pointSizeRange = { 0.0, 8192.0 },
1121 .lineWidthRange = { 0.0, 7.9921875 },
1122 .pointSizeGranularity = (1.0 / 8.0),
1123 .lineWidthGranularity = (1.0 / 128.0),
1124 .strictLines = false, /* FINISHME */
1125 .standardSampleLocations = true,
1126 .optimalBufferCopyOffsetAlignment = 128,
1127 .optimalBufferCopyRowPitchAlignment = 128,
1128 .nonCoherentAtomSize = 64,
1129 };
1130
1131 *pProperties = (VkPhysicalDeviceProperties) {
1132 .apiVersion = radv_physical_device_api_version(pdevice),
1133 .driverVersion = vk_get_driver_version(),
1134 .vendorID = ATI_VENDOR_ID,
1135 .deviceID = pdevice->rad_info.pci_id,
1136 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1137 .limits = limits,
1138 .sparseProperties = {0},
1139 };
1140
1141 strcpy(pProperties->deviceName, pdevice->name);
1142 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1143 }
1144
1145 void radv_GetPhysicalDeviceProperties2(
1146 VkPhysicalDevice physicalDevice,
1147 VkPhysicalDeviceProperties2 *pProperties)
1148 {
1149 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1150 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1151
1152 vk_foreach_struct(ext, pProperties->pNext) {
1153 switch (ext->sType) {
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1155 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1156 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1157 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1161 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1162 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1163 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1164 properties->deviceLUIDValid = false;
1165 break;
1166 }
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1168 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1169 properties->maxMultiviewViewCount = MAX_VIEWS;
1170 properties->maxMultiviewInstanceIndex = INT_MAX;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1174 VkPhysicalDevicePointClippingProperties *properties =
1175 (VkPhysicalDevicePointClippingProperties*)ext;
1176 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1180 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1181 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1182 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1186 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1187 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1188 properties->minImportedHostPointerAlignment = 4096;
1189 break;
1190 }
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1192 VkPhysicalDeviceSubgroupProperties *properties =
1193 (VkPhysicalDeviceSubgroupProperties*)ext;
1194 properties->subgroupSize = 64;
1195 properties->supportedStages = VK_SHADER_STAGE_ALL;
1196 properties->supportedOperations =
1197 VK_SUBGROUP_FEATURE_BASIC_BIT |
1198 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1199 VK_SUBGROUP_FEATURE_QUAD_BIT |
1200 VK_SUBGROUP_FEATURE_VOTE_BIT;
1201 if (pdevice->rad_info.chip_class >= GFX8) {
1202 properties->supportedOperations |=
1203 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1204 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1205 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1206 }
1207 properties->quadOperationsInAllStages = true;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1211 VkPhysicalDeviceMaintenance3Properties *properties =
1212 (VkPhysicalDeviceMaintenance3Properties*)ext;
1213 /* Make sure everything is addressable by a signed 32-bit int, and
1214 * our largest descriptors are 96 bytes. */
1215 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1216 /* Our buffer size fields allow only this much */
1217 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1221 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1222 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1223 /* GFX6-8 only support single channel min/max filter. */
1224 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1225 properties->filterMinmaxSingleComponentFormats = true;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1229 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1230 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1231
1232 /* Shader engines. */
1233 properties->shaderEngineCount =
1234 pdevice->rad_info.max_se;
1235 properties->shaderArraysPerEngineCount =
1236 pdevice->rad_info.max_sh_per_se;
1237 properties->computeUnitsPerShaderArray =
1238 pdevice->rad_info.num_good_cu_per_sh;
1239 properties->simdPerComputeUnit = 4;
1240 properties->wavefrontsPerSimd =
1241 pdevice->rad_info.family == CHIP_TONGA ||
1242 pdevice->rad_info.family == CHIP_ICELAND ||
1243 pdevice->rad_info.family == CHIP_POLARIS10 ||
1244 pdevice->rad_info.family == CHIP_POLARIS11 ||
1245 pdevice->rad_info.family == CHIP_POLARIS12 ||
1246 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1247 properties->wavefrontSize = 64;
1248
1249 /* SGPR. */
1250 properties->sgprsPerSimd =
1251 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1252 properties->minSgprAllocation =
1253 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1254 properties->maxSgprAllocation =
1255 pdevice->rad_info.family == CHIP_TONGA ||
1256 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1257 properties->sgprAllocationGranularity =
1258 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1259
1260 /* VGPR. */
1261 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1262 properties->minVgprAllocation = 4;
1263 properties->maxVgprAllocation = 256;
1264 properties->vgprAllocationGranularity = 4;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1268 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1269 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1270 properties->maxVertexAttribDivisor = UINT32_MAX;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1274 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1275 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1276 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1277 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1278 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1279 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1280 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1281 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1282 properties->robustBufferAccessUpdateAfterBind = false;
1283 properties->quadDivergentImplicitLod = false;
1284
1285 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1286 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1287 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1289 32 /* sampler, largest when combined with image */ +
1290 64 /* sampled image */ +
1291 64 /* storage image */);
1292 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1295 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1296 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1297 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1298 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1299 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1301 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1302 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1303 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1304 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1305 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1306 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1310 VkPhysicalDeviceProtectedMemoryProperties *properties =
1311 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1312 properties->protectedNoFault = false;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1316 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1317 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1318 properties->primitiveOverestimationSize = 0;
1319 properties->maxExtraPrimitiveOverestimationSize = 0;
1320 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1321 properties->primitiveUnderestimation = VK_FALSE;
1322 properties->conservativePointAndLineRasterization = VK_FALSE;
1323 properties->degenerateTrianglesRasterized = VK_FALSE;
1324 properties->degenerateLinesRasterized = VK_FALSE;
1325 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1326 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1327 break;
1328 }
1329 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1330 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1331 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1332 properties->pciDomain = pdevice->bus_info.domain;
1333 properties->pciBus = pdevice->bus_info.bus;
1334 properties->pciDevice = pdevice->bus_info.dev;
1335 properties->pciFunction = pdevice->bus_info.func;
1336 break;
1337 }
1338 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1339 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1340 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1341
1342 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1343 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1344 strcpy(driver_props->driverName, "radv");
1345
1346 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1347 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1348 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1349 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1350
1351 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1352 .major = 1,
1353 .minor = 1,
1354 .subminor = 2,
1355 .patch = 0,
1356 };
1357 break;
1358 }
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1360 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1361 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1362 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1363 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1364 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1365 properties->maxTransformFeedbackStreamDataSize = 512;
1366 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1367 properties->maxTransformFeedbackBufferDataStride = 512;
1368 properties->transformFeedbackQueries = true;
1369 properties->transformFeedbackStreamsLinesTriangles = true;
1370 properties->transformFeedbackRasterizationStreamSelect = false;
1371 properties->transformFeedbackDraw = true;
1372 break;
1373 }
1374 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1375 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1376 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1377
1378 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1379 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1380 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1381 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1382 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1383 break;
1384 }
1385 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1386 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1387 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1388 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1389 VK_SAMPLE_COUNT_4_BIT |
1390 VK_SAMPLE_COUNT_8_BIT;
1391 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1392 properties->sampleLocationCoordinateRange[0] = 0.0f;
1393 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1394 properties->sampleLocationSubPixelBits = 4;
1395 properties->variableSampleLocations = VK_FALSE;
1396 break;
1397 }
1398 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1399 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1400 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1401
1402 /* We support all of the depth resolve modes */
1403 properties->supportedDepthResolveModes =
1404 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1405 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1406 VK_RESOLVE_MODE_MIN_BIT_KHR |
1407 VK_RESOLVE_MODE_MAX_BIT_KHR;
1408
1409 /* Average doesn't make sense for stencil so we don't support that */
1410 properties->supportedStencilResolveModes =
1411 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1412 VK_RESOLVE_MODE_MIN_BIT_KHR |
1413 VK_RESOLVE_MODE_MAX_BIT_KHR;
1414
1415 properties->independentResolveNone = VK_TRUE;
1416 properties->independentResolve = VK_TRUE;
1417 break;
1418 }
1419 default:
1420 break;
1421 }
1422 }
1423 }
1424
1425 static void radv_get_physical_device_queue_family_properties(
1426 struct radv_physical_device* pdevice,
1427 uint32_t* pCount,
1428 VkQueueFamilyProperties** pQueueFamilyProperties)
1429 {
1430 int num_queue_families = 1;
1431 int idx;
1432 if (pdevice->rad_info.num_compute_rings > 0 &&
1433 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1434 num_queue_families++;
1435
1436 if (pQueueFamilyProperties == NULL) {
1437 *pCount = num_queue_families;
1438 return;
1439 }
1440
1441 if (!*pCount)
1442 return;
1443
1444 idx = 0;
1445 if (*pCount >= 1) {
1446 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1447 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1448 VK_QUEUE_COMPUTE_BIT |
1449 VK_QUEUE_TRANSFER_BIT |
1450 VK_QUEUE_SPARSE_BINDING_BIT,
1451 .queueCount = 1,
1452 .timestampValidBits = 64,
1453 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1454 };
1455 idx++;
1456 }
1457
1458 if (pdevice->rad_info.num_compute_rings > 0 &&
1459 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1460 if (*pCount > idx) {
1461 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1462 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1463 VK_QUEUE_TRANSFER_BIT |
1464 VK_QUEUE_SPARSE_BINDING_BIT,
1465 .queueCount = pdevice->rad_info.num_compute_rings,
1466 .timestampValidBits = 64,
1467 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1468 };
1469 idx++;
1470 }
1471 }
1472 *pCount = idx;
1473 }
1474
1475 void radv_GetPhysicalDeviceQueueFamilyProperties(
1476 VkPhysicalDevice physicalDevice,
1477 uint32_t* pCount,
1478 VkQueueFamilyProperties* pQueueFamilyProperties)
1479 {
1480 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1481 if (!pQueueFamilyProperties) {
1482 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1483 return;
1484 }
1485 VkQueueFamilyProperties *properties[] = {
1486 pQueueFamilyProperties + 0,
1487 pQueueFamilyProperties + 1,
1488 pQueueFamilyProperties + 2,
1489 };
1490 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1491 assert(*pCount <= 3);
1492 }
1493
1494 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1495 VkPhysicalDevice physicalDevice,
1496 uint32_t* pCount,
1497 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1498 {
1499 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1500 if (!pQueueFamilyProperties) {
1501 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1502 return;
1503 }
1504 VkQueueFamilyProperties *properties[] = {
1505 &pQueueFamilyProperties[0].queueFamilyProperties,
1506 &pQueueFamilyProperties[1].queueFamilyProperties,
1507 &pQueueFamilyProperties[2].queueFamilyProperties,
1508 };
1509 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1510 assert(*pCount <= 3);
1511 }
1512
1513 void radv_GetPhysicalDeviceMemoryProperties(
1514 VkPhysicalDevice physicalDevice,
1515 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1516 {
1517 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1518
1519 *pMemoryProperties = physical_device->memory_properties;
1520 }
1521
1522 static void
1523 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1524 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1525 {
1526 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1527 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1528 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1529 uint64_t vram_size = radv_get_vram_size(device);
1530 uint64_t gtt_size = device->rad_info.gart_size;
1531 uint64_t heap_budget, heap_usage;
1532
1533 /* For all memory heaps, the computation of budget is as follow:
1534 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1535 *
1536 * The Vulkan spec 1.1.97 says that the budget should include any
1537 * currently allocated device memory.
1538 *
1539 * Note that the application heap usages are not really accurate (eg.
1540 * in presence of shared buffers).
1541 */
1542 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1543 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1544
1545 switch (device->mem_type_indices[i]) {
1546 case RADV_MEM_TYPE_VRAM:
1547 heap_usage = device->ws->query_value(device->ws,
1548 RADEON_ALLOCATED_VRAM);
1549
1550 heap_budget = vram_size -
1551 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1552 heap_usage;
1553
1554 memoryBudget->heapBudget[heap_index] = heap_budget;
1555 memoryBudget->heapUsage[heap_index] = heap_usage;
1556 break;
1557 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1558 heap_usage = device->ws->query_value(device->ws,
1559 RADEON_ALLOCATED_VRAM_VIS);
1560
1561 heap_budget = visible_vram_size -
1562 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1563 heap_usage;
1564
1565 memoryBudget->heapBudget[heap_index] = heap_budget;
1566 memoryBudget->heapUsage[heap_index] = heap_usage;
1567 break;
1568 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1569 heap_usage = device->ws->query_value(device->ws,
1570 RADEON_ALLOCATED_GTT);
1571
1572 heap_budget = gtt_size -
1573 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1574 heap_usage;
1575
1576 memoryBudget->heapBudget[heap_index] = heap_budget;
1577 memoryBudget->heapUsage[heap_index] = heap_usage;
1578 break;
1579 default:
1580 break;
1581 }
1582 }
1583
1584 /* The heapBudget and heapUsage values must be zero for array elements
1585 * greater than or equal to
1586 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1587 */
1588 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1589 memoryBudget->heapBudget[i] = 0;
1590 memoryBudget->heapUsage[i] = 0;
1591 }
1592 }
1593
1594 void radv_GetPhysicalDeviceMemoryProperties2(
1595 VkPhysicalDevice physicalDevice,
1596 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1597 {
1598 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1599 &pMemoryProperties->memoryProperties);
1600
1601 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1602 vk_find_struct(pMemoryProperties->pNext,
1603 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1604 if (memory_budget)
1605 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1606 }
1607
1608 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1609 VkDevice _device,
1610 VkExternalMemoryHandleTypeFlagBits handleType,
1611 const void *pHostPointer,
1612 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1613 {
1614 RADV_FROM_HANDLE(radv_device, device, _device);
1615
1616 switch (handleType)
1617 {
1618 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1619 const struct radv_physical_device *physical_device = device->physical_device;
1620 uint32_t memoryTypeBits = 0;
1621 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1622 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1623 memoryTypeBits = (1 << i);
1624 break;
1625 }
1626 }
1627 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1628 return VK_SUCCESS;
1629 }
1630 default:
1631 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1632 }
1633 }
1634
1635 static enum radeon_ctx_priority
1636 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1637 {
1638 /* Default to MEDIUM when a specific global priority isn't requested */
1639 if (!pObj)
1640 return RADEON_CTX_PRIORITY_MEDIUM;
1641
1642 switch(pObj->globalPriority) {
1643 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1644 return RADEON_CTX_PRIORITY_REALTIME;
1645 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1646 return RADEON_CTX_PRIORITY_HIGH;
1647 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1648 return RADEON_CTX_PRIORITY_MEDIUM;
1649 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1650 return RADEON_CTX_PRIORITY_LOW;
1651 default:
1652 unreachable("Illegal global priority value");
1653 return RADEON_CTX_PRIORITY_INVALID;
1654 }
1655 }
1656
1657 static int
1658 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1659 uint32_t queue_family_index, int idx,
1660 VkDeviceQueueCreateFlags flags,
1661 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1662 {
1663 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1664 queue->device = device;
1665 queue->queue_family_index = queue_family_index;
1666 queue->queue_idx = idx;
1667 queue->priority = radv_get_queue_global_priority(global_priority);
1668 queue->flags = flags;
1669
1670 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1671 if (!queue->hw_ctx)
1672 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1673
1674 return VK_SUCCESS;
1675 }
1676
1677 static void
1678 radv_queue_finish(struct radv_queue *queue)
1679 {
1680 if (queue->hw_ctx)
1681 queue->device->ws->ctx_destroy(queue->hw_ctx);
1682
1683 if (queue->initial_full_flush_preamble_cs)
1684 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1685 if (queue->initial_preamble_cs)
1686 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1687 if (queue->continue_preamble_cs)
1688 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1689 if (queue->descriptor_bo)
1690 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1691 if (queue->scratch_bo)
1692 queue->device->ws->buffer_destroy(queue->scratch_bo);
1693 if (queue->esgs_ring_bo)
1694 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1695 if (queue->gsvs_ring_bo)
1696 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1697 if (queue->tess_rings_bo)
1698 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1699 if (queue->compute_scratch_bo)
1700 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1701 }
1702
1703 static void
1704 radv_bo_list_init(struct radv_bo_list *bo_list)
1705 {
1706 pthread_mutex_init(&bo_list->mutex, NULL);
1707 bo_list->list.count = bo_list->capacity = 0;
1708 bo_list->list.bos = NULL;
1709 }
1710
1711 static void
1712 radv_bo_list_finish(struct radv_bo_list *bo_list)
1713 {
1714 free(bo_list->list.bos);
1715 pthread_mutex_destroy(&bo_list->mutex);
1716 }
1717
1718 static VkResult radv_bo_list_add(struct radv_device *device,
1719 struct radeon_winsys_bo *bo)
1720 {
1721 struct radv_bo_list *bo_list = &device->bo_list;
1722
1723 if (bo->is_local)
1724 return VK_SUCCESS;
1725
1726 if (unlikely(!device->use_global_bo_list))
1727 return VK_SUCCESS;
1728
1729 pthread_mutex_lock(&bo_list->mutex);
1730 if (bo_list->list.count == bo_list->capacity) {
1731 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1732 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1733
1734 if (!data) {
1735 pthread_mutex_unlock(&bo_list->mutex);
1736 return VK_ERROR_OUT_OF_HOST_MEMORY;
1737 }
1738
1739 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1740 bo_list->capacity = capacity;
1741 }
1742
1743 bo_list->list.bos[bo_list->list.count++] = bo;
1744 pthread_mutex_unlock(&bo_list->mutex);
1745 return VK_SUCCESS;
1746 }
1747
1748 static void radv_bo_list_remove(struct radv_device *device,
1749 struct radeon_winsys_bo *bo)
1750 {
1751 struct radv_bo_list *bo_list = &device->bo_list;
1752
1753 if (bo->is_local)
1754 return;
1755
1756 if (unlikely(!device->use_global_bo_list))
1757 return;
1758
1759 pthread_mutex_lock(&bo_list->mutex);
1760 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1761 if (bo_list->list.bos[i] == bo) {
1762 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1763 --bo_list->list.count;
1764 break;
1765 }
1766 }
1767 pthread_mutex_unlock(&bo_list->mutex);
1768 }
1769
1770 static void
1771 radv_device_init_gs_info(struct radv_device *device)
1772 {
1773 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1774 device->physical_device->rad_info.family);
1775 }
1776
1777 static int radv_get_device_extension_index(const char *name)
1778 {
1779 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1780 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1781 return i;
1782 }
1783 return -1;
1784 }
1785
1786 static int
1787 radv_get_int_debug_option(const char *name, int default_value)
1788 {
1789 const char *str;
1790 int result;
1791
1792 str = getenv(name);
1793 if (!str) {
1794 result = default_value;
1795 } else {
1796 char *endptr;
1797
1798 result = strtol(str, &endptr, 0);
1799 if (str == endptr) {
1800 /* No digits founs. */
1801 result = default_value;
1802 }
1803 }
1804
1805 return result;
1806 }
1807
1808 VkResult radv_CreateDevice(
1809 VkPhysicalDevice physicalDevice,
1810 const VkDeviceCreateInfo* pCreateInfo,
1811 const VkAllocationCallbacks* pAllocator,
1812 VkDevice* pDevice)
1813 {
1814 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1815 VkResult result;
1816 struct radv_device *device;
1817
1818 bool keep_shader_info = false;
1819
1820 /* Check enabled features */
1821 if (pCreateInfo->pEnabledFeatures) {
1822 VkPhysicalDeviceFeatures supported_features;
1823 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1824 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1825 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1826 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1827 for (uint32_t i = 0; i < num_features; i++) {
1828 if (enabled_feature[i] && !supported_feature[i])
1829 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1830 }
1831 }
1832
1833 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1834 sizeof(*device), 8,
1835 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1836 if (!device)
1837 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1838
1839 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1840 device->instance = physical_device->instance;
1841 device->physical_device = physical_device;
1842
1843 device->ws = physical_device->ws;
1844 if (pAllocator)
1845 device->alloc = *pAllocator;
1846 else
1847 device->alloc = physical_device->instance->alloc;
1848
1849 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1850 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1851 int index = radv_get_device_extension_index(ext_name);
1852 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1853 vk_free(&device->alloc, device);
1854 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1855 }
1856
1857 device->enabled_extensions.extensions[index] = true;
1858 }
1859
1860 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1861
1862 /* With update after bind we can't attach bo's to the command buffer
1863 * from the descriptor set anymore, so we have to use a global BO list.
1864 */
1865 device->use_global_bo_list =
1866 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1867 device->enabled_extensions.EXT_descriptor_indexing ||
1868 device->enabled_extensions.EXT_buffer_device_address;
1869
1870 mtx_init(&device->shader_slab_mutex, mtx_plain);
1871 list_inithead(&device->shader_slabs);
1872
1873 radv_bo_list_init(&device->bo_list);
1874
1875 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1876 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1877 uint32_t qfi = queue_create->queueFamilyIndex;
1878 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1879 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1880
1881 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1882
1883 device->queues[qfi] = vk_alloc(&device->alloc,
1884 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1885 if (!device->queues[qfi]) {
1886 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1887 goto fail;
1888 }
1889
1890 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1891
1892 device->queue_count[qfi] = queue_create->queueCount;
1893
1894 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1895 result = radv_queue_init(device, &device->queues[qfi][q],
1896 qfi, q, queue_create->flags,
1897 global_priority);
1898 if (result != VK_SUCCESS)
1899 goto fail;
1900 }
1901 }
1902
1903 /* TODO: Enable binning for GFX10. */
1904 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1905 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1906
1907 /* Disabled and not implemented for now. */
1908 device->dfsm_allowed = device->pbb_allowed &&
1909 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1910 device->physical_device->rad_info.family == CHIP_RAVEN2);
1911
1912 #ifdef ANDROID
1913 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1914 #endif
1915
1916 /* The maximum number of scratch waves. Scratch space isn't divided
1917 * evenly between CUs. The number is only a function of the number of CUs.
1918 * We can decrease the constant to decrease the scratch buffer size.
1919 *
1920 * sctx->scratch_waves must be >= the maximum possible size of
1921 * 1 threadgroup, so that the hw doesn't hang from being unable
1922 * to start any.
1923 *
1924 * The recommended value is 4 per CU at most. Higher numbers don't
1925 * bring much benefit, but they still occupy chip resources (think
1926 * async compute). I've seen ~2% performance difference between 4 and 32.
1927 */
1928 uint32_t max_threads_per_block = 2048;
1929 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1930 max_threads_per_block / 64);
1931
1932 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1933
1934 if (device->physical_device->rad_info.chip_class >= GFX7) {
1935 /* If the KMD allows it (there is a KMD hw register for it),
1936 * allow launching waves out-of-order.
1937 */
1938 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1939 }
1940
1941 radv_device_init_gs_info(device);
1942
1943 device->tess_offchip_block_dw_size =
1944 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1945 device->has_distributed_tess =
1946 device->physical_device->rad_info.chip_class >= GFX8 &&
1947 device->physical_device->rad_info.max_se >= 2;
1948
1949 if (getenv("RADV_TRACE_FILE")) {
1950 const char *filename = getenv("RADV_TRACE_FILE");
1951
1952 keep_shader_info = true;
1953
1954 if (!radv_init_trace(device))
1955 goto fail;
1956
1957 fprintf(stderr, "*****************************************************************************\n");
1958 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1959 fprintf(stderr, "*****************************************************************************\n");
1960
1961 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1962 radv_dump_enabled_options(device, stderr);
1963 }
1964
1965 device->keep_shader_info = keep_shader_info;
1966
1967 result = radv_device_init_meta(device);
1968 if (result != VK_SUCCESS)
1969 goto fail;
1970
1971 radv_device_init_msaa(device);
1972
1973 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1974 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1975 switch (family) {
1976 case RADV_QUEUE_GENERAL:
1977 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1978 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1979 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1980 break;
1981 case RADV_QUEUE_COMPUTE:
1982 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1983 radeon_emit(device->empty_cs[family], 0);
1984 break;
1985 }
1986 device->ws->cs_finalize(device->empty_cs[family]);
1987 }
1988
1989 if (device->physical_device->rad_info.chip_class >= GFX7)
1990 cik_create_gfx_config(device);
1991
1992 VkPipelineCacheCreateInfo ci;
1993 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1994 ci.pNext = NULL;
1995 ci.flags = 0;
1996 ci.pInitialData = NULL;
1997 ci.initialDataSize = 0;
1998 VkPipelineCache pc;
1999 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2000 &ci, NULL, &pc);
2001 if (result != VK_SUCCESS)
2002 goto fail_meta;
2003
2004 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2005
2006 device->force_aniso =
2007 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2008 if (device->force_aniso >= 0) {
2009 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2010 1 << util_logbase2(device->force_aniso));
2011 }
2012
2013 *pDevice = radv_device_to_handle(device);
2014 return VK_SUCCESS;
2015
2016 fail_meta:
2017 radv_device_finish_meta(device);
2018 fail:
2019 radv_bo_list_finish(&device->bo_list);
2020
2021 if (device->trace_bo)
2022 device->ws->buffer_destroy(device->trace_bo);
2023
2024 if (device->gfx_init)
2025 device->ws->buffer_destroy(device->gfx_init);
2026
2027 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2028 for (unsigned q = 0; q < device->queue_count[i]; q++)
2029 radv_queue_finish(&device->queues[i][q]);
2030 if (device->queue_count[i])
2031 vk_free(&device->alloc, device->queues[i]);
2032 }
2033
2034 vk_free(&device->alloc, device);
2035 return result;
2036 }
2037
2038 void radv_DestroyDevice(
2039 VkDevice _device,
2040 const VkAllocationCallbacks* pAllocator)
2041 {
2042 RADV_FROM_HANDLE(radv_device, device, _device);
2043
2044 if (!device)
2045 return;
2046
2047 if (device->trace_bo)
2048 device->ws->buffer_destroy(device->trace_bo);
2049
2050 if (device->gfx_init)
2051 device->ws->buffer_destroy(device->gfx_init);
2052
2053 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2054 for (unsigned q = 0; q < device->queue_count[i]; q++)
2055 radv_queue_finish(&device->queues[i][q]);
2056 if (device->queue_count[i])
2057 vk_free(&device->alloc, device->queues[i]);
2058 if (device->empty_cs[i])
2059 device->ws->cs_destroy(device->empty_cs[i]);
2060 }
2061 radv_device_finish_meta(device);
2062
2063 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2064 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2065
2066 radv_destroy_shader_slabs(device);
2067
2068 radv_bo_list_finish(&device->bo_list);
2069 vk_free(&device->alloc, device);
2070 }
2071
2072 VkResult radv_EnumerateInstanceLayerProperties(
2073 uint32_t* pPropertyCount,
2074 VkLayerProperties* pProperties)
2075 {
2076 if (pProperties == NULL) {
2077 *pPropertyCount = 0;
2078 return VK_SUCCESS;
2079 }
2080
2081 /* None supported at this time */
2082 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2083 }
2084
2085 VkResult radv_EnumerateDeviceLayerProperties(
2086 VkPhysicalDevice physicalDevice,
2087 uint32_t* pPropertyCount,
2088 VkLayerProperties* pProperties)
2089 {
2090 if (pProperties == NULL) {
2091 *pPropertyCount = 0;
2092 return VK_SUCCESS;
2093 }
2094
2095 /* None supported at this time */
2096 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2097 }
2098
2099 void radv_GetDeviceQueue2(
2100 VkDevice _device,
2101 const VkDeviceQueueInfo2* pQueueInfo,
2102 VkQueue* pQueue)
2103 {
2104 RADV_FROM_HANDLE(radv_device, device, _device);
2105 struct radv_queue *queue;
2106
2107 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2108 if (pQueueInfo->flags != queue->flags) {
2109 /* From the Vulkan 1.1.70 spec:
2110 *
2111 * "The queue returned by vkGetDeviceQueue2 must have the same
2112 * flags value from this structure as that used at device
2113 * creation time in a VkDeviceQueueCreateInfo instance. If no
2114 * matching flags were specified at device creation time then
2115 * pQueue will return VK_NULL_HANDLE."
2116 */
2117 *pQueue = VK_NULL_HANDLE;
2118 return;
2119 }
2120
2121 *pQueue = radv_queue_to_handle(queue);
2122 }
2123
2124 void radv_GetDeviceQueue(
2125 VkDevice _device,
2126 uint32_t queueFamilyIndex,
2127 uint32_t queueIndex,
2128 VkQueue* pQueue)
2129 {
2130 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2131 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2132 .queueFamilyIndex = queueFamilyIndex,
2133 .queueIndex = queueIndex
2134 };
2135
2136 radv_GetDeviceQueue2(_device, &info, pQueue);
2137 }
2138
2139 static void
2140 fill_geom_tess_rings(struct radv_queue *queue,
2141 uint32_t *map,
2142 bool add_sample_positions,
2143 uint32_t esgs_ring_size,
2144 struct radeon_winsys_bo *esgs_ring_bo,
2145 uint32_t gsvs_ring_size,
2146 struct radeon_winsys_bo *gsvs_ring_bo,
2147 uint32_t tess_factor_ring_size,
2148 uint32_t tess_offchip_ring_offset,
2149 uint32_t tess_offchip_ring_size,
2150 struct radeon_winsys_bo *tess_rings_bo)
2151 {
2152 uint32_t *desc = &map[4];
2153
2154 if (esgs_ring_bo) {
2155 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2156
2157 /* stride 0, num records - size, add tid, swizzle, elsize4,
2158 index stride 64 */
2159 desc[0] = esgs_va;
2160 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2161 S_008F04_STRIDE(0) |
2162 S_008F04_SWIZZLE_ENABLE(true);
2163 desc[2] = esgs_ring_size;
2164 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2165 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2166 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2167 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2168 S_008F0C_ELEMENT_SIZE(1) |
2169 S_008F0C_INDEX_STRIDE(3) |
2170 S_008F0C_ADD_TID_ENABLE(true);
2171
2172 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2173 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2174 S_008F0C_OOB_SELECT(2) |
2175 S_008F0C_RESOURCE_LEVEL(1);
2176 } else {
2177 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2178 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2179 }
2180
2181 /* GS entry for ES->GS ring */
2182 /* stride 0, num records - size, elsize0,
2183 index stride 0 */
2184 desc[4] = esgs_va;
2185 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2186 S_008F04_STRIDE(0) |
2187 S_008F04_SWIZZLE_ENABLE(false);
2188 desc[6] = esgs_ring_size;
2189 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2190 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2191 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2192 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2193 S_008F0C_ELEMENT_SIZE(0) |
2194 S_008F0C_INDEX_STRIDE(0) |
2195 S_008F0C_ADD_TID_ENABLE(false);
2196
2197 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2198 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2199 S_008F0C_OOB_SELECT(2) |
2200 S_008F0C_RESOURCE_LEVEL(1);
2201 } else {
2202 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2203 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2204 }
2205 }
2206
2207 desc += 8;
2208
2209 if (gsvs_ring_bo) {
2210 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2211
2212 /* VS entry for GS->VS ring */
2213 /* stride 0, num records - size, elsize0,
2214 index stride 0 */
2215 desc[0] = gsvs_va;
2216 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2217 S_008F04_STRIDE(0) |
2218 S_008F04_SWIZZLE_ENABLE(false);
2219 desc[2] = gsvs_ring_size;
2220 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2221 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2222 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2223 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2224 S_008F0C_ELEMENT_SIZE(0) |
2225 S_008F0C_INDEX_STRIDE(0) |
2226 S_008F0C_ADD_TID_ENABLE(false);
2227
2228 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2229 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2230 S_008F0C_OOB_SELECT(2) |
2231 S_008F0C_RESOURCE_LEVEL(1);
2232 } else {
2233 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2235 }
2236
2237 /* stride gsvs_itemsize, num records 64
2238 elsize 4, index stride 16 */
2239 /* shader will patch stride and desc[2] */
2240 desc[4] = gsvs_va;
2241 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2242 S_008F04_STRIDE(0) |
2243 S_008F04_SWIZZLE_ENABLE(true);
2244 desc[6] = 0;
2245 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2246 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2247 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2248 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2249 S_008F0C_ELEMENT_SIZE(1) |
2250 S_008F0C_INDEX_STRIDE(1) |
2251 S_008F0C_ADD_TID_ENABLE(true);
2252
2253 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2254 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2255 S_008F0C_OOB_SELECT(2) |
2256 S_008F0C_RESOURCE_LEVEL(1);
2257 } else {
2258 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2259 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2260 }
2261
2262 }
2263
2264 desc += 8;
2265
2266 if (tess_rings_bo) {
2267 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2268 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2269
2270 desc[0] = tess_va;
2271 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2272 S_008F04_STRIDE(0) |
2273 S_008F04_SWIZZLE_ENABLE(false);
2274 desc[2] = tess_factor_ring_size;
2275 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2276 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2277 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2278 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2279
2280 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2281 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2282 S_008F0C_OOB_SELECT(3) |
2283 S_008F0C_RESOURCE_LEVEL(1);
2284 } else {
2285 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2286 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2287 }
2288
2289 desc[4] = tess_offchip_va;
2290 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2291 S_008F04_STRIDE(0) |
2292 S_008F04_SWIZZLE_ENABLE(false);
2293 desc[6] = tess_offchip_ring_size;
2294 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2295 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2296 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2297 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2298
2299 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2300 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2301 S_008F0C_OOB_SELECT(3) |
2302 S_008F0C_RESOURCE_LEVEL(1);
2303 } else {
2304 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2306 }
2307 }
2308
2309 desc += 8;
2310
2311 if (add_sample_positions) {
2312 /* add sample positions after all rings */
2313 memcpy(desc, queue->device->sample_locations_1x, 8);
2314 desc += 2;
2315 memcpy(desc, queue->device->sample_locations_2x, 16);
2316 desc += 4;
2317 memcpy(desc, queue->device->sample_locations_4x, 32);
2318 desc += 8;
2319 memcpy(desc, queue->device->sample_locations_8x, 64);
2320 }
2321 }
2322
2323 static unsigned
2324 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2325 {
2326 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2327 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2328 device->physical_device->rad_info.family != CHIP_STONEY;
2329 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2330 unsigned max_offchip_buffers;
2331 unsigned offchip_granularity;
2332 unsigned hs_offchip_param;
2333
2334 /*
2335 * Per RadeonSI:
2336 * This must be one less than the maximum number due to a hw limitation.
2337 * Various hardware bugs need thGFX7
2338 *
2339 * Per AMDVLK:
2340 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2341 * Gfx7 should limit max_offchip_buffers to 508
2342 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2343 *
2344 * Follow AMDVLK here.
2345 */
2346 if (device->physical_device->rad_info.chip_class >= GFX10) {
2347 max_offchip_buffers_per_se = 256;
2348 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2349 device->physical_device->rad_info.chip_class == GFX7 ||
2350 device->physical_device->rad_info.chip_class == GFX6)
2351 --max_offchip_buffers_per_se;
2352
2353 max_offchip_buffers = max_offchip_buffers_per_se *
2354 device->physical_device->rad_info.max_se;
2355
2356 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2357 * around by setting 4K granularity.
2358 */
2359 if (device->tess_offchip_block_dw_size == 4096) {
2360 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2361 offchip_granularity = V_03093C_X_4K_DWORDS;
2362 } else {
2363 assert(device->tess_offchip_block_dw_size == 8192);
2364 offchip_granularity = V_03093C_X_8K_DWORDS;
2365 }
2366
2367 switch (device->physical_device->rad_info.chip_class) {
2368 case GFX6:
2369 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2370 break;
2371 case GFX7:
2372 case GFX8:
2373 case GFX9:
2374 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2375 break;
2376 case GFX10:
2377 break;
2378 default:
2379 break;
2380 }
2381
2382 *max_offchip_buffers_p = max_offchip_buffers;
2383 if (device->physical_device->rad_info.chip_class >= GFX7) {
2384 if (device->physical_device->rad_info.chip_class >= GFX8)
2385 --max_offchip_buffers;
2386 hs_offchip_param =
2387 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2388 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2389 } else {
2390 hs_offchip_param =
2391 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2392 }
2393 return hs_offchip_param;
2394 }
2395
2396 static void
2397 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2398 struct radeon_winsys_bo *esgs_ring_bo,
2399 uint32_t esgs_ring_size,
2400 struct radeon_winsys_bo *gsvs_ring_bo,
2401 uint32_t gsvs_ring_size)
2402 {
2403 if (!esgs_ring_bo && !gsvs_ring_bo)
2404 return;
2405
2406 if (esgs_ring_bo)
2407 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2408
2409 if (gsvs_ring_bo)
2410 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2411
2412 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2413 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2414 radeon_emit(cs, esgs_ring_size >> 8);
2415 radeon_emit(cs, gsvs_ring_size >> 8);
2416 } else {
2417 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2418 radeon_emit(cs, esgs_ring_size >> 8);
2419 radeon_emit(cs, gsvs_ring_size >> 8);
2420 }
2421 }
2422
2423 static void
2424 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2425 unsigned hs_offchip_param, unsigned tf_ring_size,
2426 struct radeon_winsys_bo *tess_rings_bo)
2427 {
2428 uint64_t tf_va;
2429
2430 if (!tess_rings_bo)
2431 return;
2432
2433 tf_va = radv_buffer_get_va(tess_rings_bo);
2434
2435 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2436
2437 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2438 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2439 S_030938_SIZE(tf_ring_size / 4));
2440 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2441 tf_va >> 8);
2442
2443 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2444 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2445 S_030984_BASE_HI(tf_va >> 40));
2446 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2447 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2448 S_030944_BASE_HI(tf_va >> 40));
2449 }
2450 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2451 hs_offchip_param);
2452 } else {
2453 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2454 S_008988_SIZE(tf_ring_size / 4));
2455 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2456 tf_va >> 8);
2457 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2458 hs_offchip_param);
2459 }
2460 }
2461
2462 static void
2463 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2464 struct radeon_winsys_bo *compute_scratch_bo)
2465 {
2466 uint64_t scratch_va;
2467
2468 if (!compute_scratch_bo)
2469 return;
2470
2471 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2472
2473 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2474
2475 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2476 radeon_emit(cs, scratch_va);
2477 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2478 S_008F04_SWIZZLE_ENABLE(1));
2479 }
2480
2481 static void
2482 radv_emit_global_shader_pointers(struct radv_queue *queue,
2483 struct radeon_cmdbuf *cs,
2484 struct radeon_winsys_bo *descriptor_bo)
2485 {
2486 uint64_t va;
2487
2488 if (!descriptor_bo)
2489 return;
2490
2491 va = radv_buffer_get_va(descriptor_bo);
2492
2493 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2494
2495 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2496 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2497 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2498 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2499 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2500
2501 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2502 radv_emit_shader_pointer(queue->device, cs, regs[i],
2503 va, true);
2504 }
2505 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2506 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2507 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2508 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2509 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2510
2511 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2512 radv_emit_shader_pointer(queue->device, cs, regs[i],
2513 va, true);
2514 }
2515 } else {
2516 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2517 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2518 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2519 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2520 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2521 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2522
2523 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2524 radv_emit_shader_pointer(queue->device, cs, regs[i],
2525 va, true);
2526 }
2527 }
2528 }
2529
2530 static void
2531 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2532 {
2533 struct radv_device *device = queue->device;
2534
2535 if (device->gfx_init) {
2536 uint64_t va = radv_buffer_get_va(device->gfx_init);
2537
2538 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2539 radeon_emit(cs, va);
2540 radeon_emit(cs, va >> 32);
2541 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2542
2543 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2544 } else {
2545 struct radv_physical_device *physical_device = device->physical_device;
2546 si_emit_graphics(physical_device, cs);
2547 }
2548 }
2549
2550 static void
2551 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2552 {
2553 struct radv_physical_device *physical_device = queue->device->physical_device;
2554 si_emit_compute(physical_device, cs);
2555 }
2556
2557 static VkResult
2558 radv_get_preamble_cs(struct radv_queue *queue,
2559 uint32_t scratch_size,
2560 uint32_t compute_scratch_size,
2561 uint32_t esgs_ring_size,
2562 uint32_t gsvs_ring_size,
2563 bool needs_tess_rings,
2564 bool needs_sample_positions,
2565 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2566 struct radeon_cmdbuf **initial_preamble_cs,
2567 struct radeon_cmdbuf **continue_preamble_cs)
2568 {
2569 struct radeon_winsys_bo *scratch_bo = NULL;
2570 struct radeon_winsys_bo *descriptor_bo = NULL;
2571 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2572 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2573 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2574 struct radeon_winsys_bo *tess_rings_bo = NULL;
2575 struct radeon_cmdbuf *dest_cs[3] = {0};
2576 bool add_tess_rings = false, add_sample_positions = false;
2577 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2578 unsigned max_offchip_buffers;
2579 unsigned hs_offchip_param = 0;
2580 unsigned tess_offchip_ring_offset;
2581 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2582 if (!queue->has_tess_rings) {
2583 if (needs_tess_rings)
2584 add_tess_rings = true;
2585 }
2586 if (!queue->has_sample_positions) {
2587 if (needs_sample_positions)
2588 add_sample_positions = true;
2589 }
2590 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2591 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2592 &max_offchip_buffers);
2593 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2594 tess_offchip_ring_size = max_offchip_buffers *
2595 queue->device->tess_offchip_block_dw_size * 4;
2596
2597 if (scratch_size <= queue->scratch_size &&
2598 compute_scratch_size <= queue->compute_scratch_size &&
2599 esgs_ring_size <= queue->esgs_ring_size &&
2600 gsvs_ring_size <= queue->gsvs_ring_size &&
2601 !add_tess_rings && !add_sample_positions &&
2602 queue->initial_preamble_cs) {
2603 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2604 *initial_preamble_cs = queue->initial_preamble_cs;
2605 *continue_preamble_cs = queue->continue_preamble_cs;
2606 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2607 *continue_preamble_cs = NULL;
2608 return VK_SUCCESS;
2609 }
2610
2611 if (scratch_size > queue->scratch_size) {
2612 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2613 scratch_size,
2614 4096,
2615 RADEON_DOMAIN_VRAM,
2616 ring_bo_flags,
2617 RADV_BO_PRIORITY_SCRATCH);
2618 if (!scratch_bo)
2619 goto fail;
2620 } else
2621 scratch_bo = queue->scratch_bo;
2622
2623 if (compute_scratch_size > queue->compute_scratch_size) {
2624 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2625 compute_scratch_size,
2626 4096,
2627 RADEON_DOMAIN_VRAM,
2628 ring_bo_flags,
2629 RADV_BO_PRIORITY_SCRATCH);
2630 if (!compute_scratch_bo)
2631 goto fail;
2632
2633 } else
2634 compute_scratch_bo = queue->compute_scratch_bo;
2635
2636 if (esgs_ring_size > queue->esgs_ring_size) {
2637 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2638 esgs_ring_size,
2639 4096,
2640 RADEON_DOMAIN_VRAM,
2641 ring_bo_flags,
2642 RADV_BO_PRIORITY_SCRATCH);
2643 if (!esgs_ring_bo)
2644 goto fail;
2645 } else {
2646 esgs_ring_bo = queue->esgs_ring_bo;
2647 esgs_ring_size = queue->esgs_ring_size;
2648 }
2649
2650 if (gsvs_ring_size > queue->gsvs_ring_size) {
2651 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2652 gsvs_ring_size,
2653 4096,
2654 RADEON_DOMAIN_VRAM,
2655 ring_bo_flags,
2656 RADV_BO_PRIORITY_SCRATCH);
2657 if (!gsvs_ring_bo)
2658 goto fail;
2659 } else {
2660 gsvs_ring_bo = queue->gsvs_ring_bo;
2661 gsvs_ring_size = queue->gsvs_ring_size;
2662 }
2663
2664 if (add_tess_rings) {
2665 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2666 tess_offchip_ring_offset + tess_offchip_ring_size,
2667 256,
2668 RADEON_DOMAIN_VRAM,
2669 ring_bo_flags,
2670 RADV_BO_PRIORITY_SCRATCH);
2671 if (!tess_rings_bo)
2672 goto fail;
2673 } else {
2674 tess_rings_bo = queue->tess_rings_bo;
2675 }
2676
2677 if (scratch_bo != queue->scratch_bo ||
2678 esgs_ring_bo != queue->esgs_ring_bo ||
2679 gsvs_ring_bo != queue->gsvs_ring_bo ||
2680 tess_rings_bo != queue->tess_rings_bo ||
2681 add_sample_positions) {
2682 uint32_t size = 0;
2683 if (gsvs_ring_bo || esgs_ring_bo ||
2684 tess_rings_bo || add_sample_positions) {
2685 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2686 if (add_sample_positions)
2687 size += 128; /* 64+32+16+8 = 120 bytes */
2688 }
2689 else if (scratch_bo)
2690 size = 8; /* 2 dword */
2691
2692 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2693 size,
2694 4096,
2695 RADEON_DOMAIN_VRAM,
2696 RADEON_FLAG_CPU_ACCESS |
2697 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2698 RADEON_FLAG_READ_ONLY,
2699 RADV_BO_PRIORITY_DESCRIPTOR);
2700 if (!descriptor_bo)
2701 goto fail;
2702 } else
2703 descriptor_bo = queue->descriptor_bo;
2704
2705 if (descriptor_bo != queue->descriptor_bo) {
2706 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2707
2708 if (scratch_bo) {
2709 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2710 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2711 S_008F04_SWIZZLE_ENABLE(1);
2712 map[0] = scratch_va;
2713 map[1] = rsrc1;
2714 }
2715
2716 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2717 fill_geom_tess_rings(queue, map, add_sample_positions,
2718 esgs_ring_size, esgs_ring_bo,
2719 gsvs_ring_size, gsvs_ring_bo,
2720 tess_factor_ring_size,
2721 tess_offchip_ring_offset,
2722 tess_offchip_ring_size,
2723 tess_rings_bo);
2724
2725 queue->device->ws->buffer_unmap(descriptor_bo);
2726 }
2727
2728 for(int i = 0; i < 3; ++i) {
2729 struct radeon_cmdbuf *cs = NULL;
2730 cs = queue->device->ws->cs_create(queue->device->ws,
2731 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2732 if (!cs)
2733 goto fail;
2734
2735 dest_cs[i] = cs;
2736
2737 if (scratch_bo)
2738 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2739
2740 /* Emit initial configuration. */
2741 switch (queue->queue_family_index) {
2742 case RADV_QUEUE_GENERAL:
2743 radv_init_graphics_state(cs, queue);
2744 break;
2745 case RADV_QUEUE_COMPUTE:
2746 radv_init_compute_state(cs, queue);
2747 break;
2748 case RADV_QUEUE_TRANSFER:
2749 break;
2750 }
2751
2752 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2753 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2754 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2755
2756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2757 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2758 }
2759
2760 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2761 gsvs_ring_bo, gsvs_ring_size);
2762 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2763 tess_factor_ring_size, tess_rings_bo);
2764 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2765 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2766
2767 if (i == 0) {
2768 si_cs_emit_cache_flush(cs,
2769 queue->device->physical_device->rad_info.chip_class,
2770 NULL, 0,
2771 queue->queue_family_index == RING_COMPUTE &&
2772 queue->device->physical_device->rad_info.chip_class >= GFX7,
2773 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2774 RADV_CMD_FLAG_INV_ICACHE |
2775 RADV_CMD_FLAG_INV_SCACHE |
2776 RADV_CMD_FLAG_INV_VCACHE |
2777 RADV_CMD_FLAG_INV_L2 |
2778 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2779 } else if (i == 1) {
2780 si_cs_emit_cache_flush(cs,
2781 queue->device->physical_device->rad_info.chip_class,
2782 NULL, 0,
2783 queue->queue_family_index == RING_COMPUTE &&
2784 queue->device->physical_device->rad_info.chip_class >= GFX7,
2785 RADV_CMD_FLAG_INV_ICACHE |
2786 RADV_CMD_FLAG_INV_SCACHE |
2787 RADV_CMD_FLAG_INV_VCACHE |
2788 RADV_CMD_FLAG_INV_L2 |
2789 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2790 }
2791
2792 if (!queue->device->ws->cs_finalize(cs))
2793 goto fail;
2794 }
2795
2796 if (queue->initial_full_flush_preamble_cs)
2797 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2798
2799 if (queue->initial_preamble_cs)
2800 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2801
2802 if (queue->continue_preamble_cs)
2803 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2804
2805 queue->initial_full_flush_preamble_cs = dest_cs[0];
2806 queue->initial_preamble_cs = dest_cs[1];
2807 queue->continue_preamble_cs = dest_cs[2];
2808
2809 if (scratch_bo != queue->scratch_bo) {
2810 if (queue->scratch_bo)
2811 queue->device->ws->buffer_destroy(queue->scratch_bo);
2812 queue->scratch_bo = scratch_bo;
2813 queue->scratch_size = scratch_size;
2814 }
2815
2816 if (compute_scratch_bo != queue->compute_scratch_bo) {
2817 if (queue->compute_scratch_bo)
2818 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2819 queue->compute_scratch_bo = compute_scratch_bo;
2820 queue->compute_scratch_size = compute_scratch_size;
2821 }
2822
2823 if (esgs_ring_bo != queue->esgs_ring_bo) {
2824 if (queue->esgs_ring_bo)
2825 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2826 queue->esgs_ring_bo = esgs_ring_bo;
2827 queue->esgs_ring_size = esgs_ring_size;
2828 }
2829
2830 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2831 if (queue->gsvs_ring_bo)
2832 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2833 queue->gsvs_ring_bo = gsvs_ring_bo;
2834 queue->gsvs_ring_size = gsvs_ring_size;
2835 }
2836
2837 if (tess_rings_bo != queue->tess_rings_bo) {
2838 queue->tess_rings_bo = tess_rings_bo;
2839 queue->has_tess_rings = true;
2840 }
2841
2842 if (descriptor_bo != queue->descriptor_bo) {
2843 if (queue->descriptor_bo)
2844 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2845
2846 queue->descriptor_bo = descriptor_bo;
2847 }
2848
2849 if (add_sample_positions)
2850 queue->has_sample_positions = true;
2851
2852 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2853 *initial_preamble_cs = queue->initial_preamble_cs;
2854 *continue_preamble_cs = queue->continue_preamble_cs;
2855 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2856 *continue_preamble_cs = NULL;
2857 return VK_SUCCESS;
2858 fail:
2859 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2860 if (dest_cs[i])
2861 queue->device->ws->cs_destroy(dest_cs[i]);
2862 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2863 queue->device->ws->buffer_destroy(descriptor_bo);
2864 if (scratch_bo && scratch_bo != queue->scratch_bo)
2865 queue->device->ws->buffer_destroy(scratch_bo);
2866 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2867 queue->device->ws->buffer_destroy(compute_scratch_bo);
2868 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2869 queue->device->ws->buffer_destroy(esgs_ring_bo);
2870 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2871 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2872 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2873 queue->device->ws->buffer_destroy(tess_rings_bo);
2874 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2875 }
2876
2877 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2878 struct radv_winsys_sem_counts *counts,
2879 int num_sems,
2880 const VkSemaphore *sems,
2881 VkFence _fence,
2882 bool reset_temp)
2883 {
2884 int syncobj_idx = 0, sem_idx = 0;
2885
2886 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2887 return VK_SUCCESS;
2888
2889 for (uint32_t i = 0; i < num_sems; i++) {
2890 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2891
2892 if (sem->temp_syncobj || sem->syncobj)
2893 counts->syncobj_count++;
2894 else
2895 counts->sem_count++;
2896 }
2897
2898 if (_fence != VK_NULL_HANDLE) {
2899 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2900 if (fence->temp_syncobj || fence->syncobj)
2901 counts->syncobj_count++;
2902 }
2903
2904 if (counts->syncobj_count) {
2905 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2906 if (!counts->syncobj)
2907 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2908 }
2909
2910 if (counts->sem_count) {
2911 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2912 if (!counts->sem) {
2913 free(counts->syncobj);
2914 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2915 }
2916 }
2917
2918 for (uint32_t i = 0; i < num_sems; i++) {
2919 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2920
2921 if (sem->temp_syncobj) {
2922 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2923 }
2924 else if (sem->syncobj)
2925 counts->syncobj[syncobj_idx++] = sem->syncobj;
2926 else {
2927 assert(sem->sem);
2928 counts->sem[sem_idx++] = sem->sem;
2929 }
2930 }
2931
2932 if (_fence != VK_NULL_HANDLE) {
2933 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2934 if (fence->temp_syncobj)
2935 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2936 else if (fence->syncobj)
2937 counts->syncobj[syncobj_idx++] = fence->syncobj;
2938 }
2939
2940 return VK_SUCCESS;
2941 }
2942
2943 static void
2944 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2945 {
2946 free(sem_info->wait.syncobj);
2947 free(sem_info->wait.sem);
2948 free(sem_info->signal.syncobj);
2949 free(sem_info->signal.sem);
2950 }
2951
2952
2953 static void radv_free_temp_syncobjs(struct radv_device *device,
2954 int num_sems,
2955 const VkSemaphore *sems)
2956 {
2957 for (uint32_t i = 0; i < num_sems; i++) {
2958 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2959
2960 if (sem->temp_syncobj) {
2961 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2962 sem->temp_syncobj = 0;
2963 }
2964 }
2965 }
2966
2967 static VkResult
2968 radv_alloc_sem_info(struct radv_instance *instance,
2969 struct radv_winsys_sem_info *sem_info,
2970 int num_wait_sems,
2971 const VkSemaphore *wait_sems,
2972 int num_signal_sems,
2973 const VkSemaphore *signal_sems,
2974 VkFence fence)
2975 {
2976 VkResult ret;
2977 memset(sem_info, 0, sizeof(*sem_info));
2978
2979 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2980 if (ret)
2981 return ret;
2982 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2983 if (ret)
2984 radv_free_sem_info(sem_info);
2985
2986 /* caller can override these */
2987 sem_info->cs_emit_wait = true;
2988 sem_info->cs_emit_signal = true;
2989 return ret;
2990 }
2991
2992 /* Signals fence as soon as all the work currently put on queue is done. */
2993 static VkResult radv_signal_fence(struct radv_queue *queue,
2994 struct radv_fence *fence)
2995 {
2996 int ret;
2997 VkResult result;
2998 struct radv_winsys_sem_info sem_info;
2999
3000 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3001 radv_fence_to_handle(fence));
3002 if (result != VK_SUCCESS)
3003 return result;
3004
3005 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3006 &queue->device->empty_cs[queue->queue_family_index],
3007 1, NULL, NULL, &sem_info, NULL,
3008 false, fence->fence);
3009 radv_free_sem_info(&sem_info);
3010
3011 if (ret)
3012 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3013
3014 return VK_SUCCESS;
3015 }
3016
3017 VkResult radv_QueueSubmit(
3018 VkQueue _queue,
3019 uint32_t submitCount,
3020 const VkSubmitInfo* pSubmits,
3021 VkFence _fence)
3022 {
3023 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3024 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3025 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3026 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3027 int ret;
3028 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3029 uint32_t scratch_size = 0;
3030 uint32_t compute_scratch_size = 0;
3031 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3032 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3033 VkResult result;
3034 bool fence_emitted = false;
3035 bool tess_rings_needed = false;
3036 bool sample_positions_needed = false;
3037
3038 /* Do this first so failing to allocate scratch buffers can't result in
3039 * partially executed submissions. */
3040 for (uint32_t i = 0; i < submitCount; i++) {
3041 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3042 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3043 pSubmits[i].pCommandBuffers[j]);
3044
3045 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3046 compute_scratch_size = MAX2(compute_scratch_size,
3047 cmd_buffer->compute_scratch_size_needed);
3048 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3049 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3050 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3051 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3052 }
3053 }
3054
3055 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3056 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3057 sample_positions_needed, &initial_flush_preamble_cs,
3058 &initial_preamble_cs, &continue_preamble_cs);
3059 if (result != VK_SUCCESS)
3060 return result;
3061
3062 for (uint32_t i = 0; i < submitCount; i++) {
3063 struct radeon_cmdbuf **cs_array;
3064 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3065 bool can_patch = true;
3066 uint32_t advance;
3067 struct radv_winsys_sem_info sem_info;
3068
3069 result = radv_alloc_sem_info(queue->device->instance,
3070 &sem_info,
3071 pSubmits[i].waitSemaphoreCount,
3072 pSubmits[i].pWaitSemaphores,
3073 pSubmits[i].signalSemaphoreCount,
3074 pSubmits[i].pSignalSemaphores,
3075 _fence);
3076 if (result != VK_SUCCESS)
3077 return result;
3078
3079 if (!pSubmits[i].commandBufferCount) {
3080 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3081 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3082 &queue->device->empty_cs[queue->queue_family_index],
3083 1, NULL, NULL,
3084 &sem_info, NULL,
3085 false, base_fence);
3086 if (ret) {
3087 radv_loge("failed to submit CS %d\n", i);
3088 abort();
3089 }
3090 fence_emitted = true;
3091 }
3092 radv_free_sem_info(&sem_info);
3093 continue;
3094 }
3095
3096 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3097 (pSubmits[i].commandBufferCount));
3098
3099 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3100 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3101 pSubmits[i].pCommandBuffers[j]);
3102 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3103
3104 cs_array[j] = cmd_buffer->cs;
3105 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3106 can_patch = false;
3107
3108 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3109 }
3110
3111 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3112 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3113 const struct radv_winsys_bo_list *bo_list = NULL;
3114
3115 advance = MIN2(max_cs_submission,
3116 pSubmits[i].commandBufferCount - j);
3117
3118 if (queue->device->trace_bo)
3119 *queue->device->trace_id_ptr = 0;
3120
3121 sem_info.cs_emit_wait = j == 0;
3122 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3123
3124 if (unlikely(queue->device->use_global_bo_list)) {
3125 pthread_mutex_lock(&queue->device->bo_list.mutex);
3126 bo_list = &queue->device->bo_list.list;
3127 }
3128
3129 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3130 advance, initial_preamble, continue_preamble_cs,
3131 &sem_info, bo_list,
3132 can_patch, base_fence);
3133
3134 if (unlikely(queue->device->use_global_bo_list))
3135 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3136
3137 if (ret) {
3138 radv_loge("failed to submit CS %d\n", i);
3139 abort();
3140 }
3141 fence_emitted = true;
3142 if (queue->device->trace_bo) {
3143 radv_check_gpu_hangs(queue, cs_array[j]);
3144 }
3145 }
3146
3147 radv_free_temp_syncobjs(queue->device,
3148 pSubmits[i].waitSemaphoreCount,
3149 pSubmits[i].pWaitSemaphores);
3150 radv_free_sem_info(&sem_info);
3151 free(cs_array);
3152 }
3153
3154 if (fence) {
3155 if (!fence_emitted) {
3156 result = radv_signal_fence(queue, fence);
3157 if (result != VK_SUCCESS)
3158 return result;
3159 }
3160 }
3161
3162 return VK_SUCCESS;
3163 }
3164
3165 VkResult radv_QueueWaitIdle(
3166 VkQueue _queue)
3167 {
3168 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3169
3170 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3171 radv_queue_family_to_ring(queue->queue_family_index),
3172 queue->queue_idx);
3173 return VK_SUCCESS;
3174 }
3175
3176 VkResult radv_DeviceWaitIdle(
3177 VkDevice _device)
3178 {
3179 RADV_FROM_HANDLE(radv_device, device, _device);
3180
3181 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3182 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3183 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3184 }
3185 }
3186 return VK_SUCCESS;
3187 }
3188
3189 VkResult radv_EnumerateInstanceExtensionProperties(
3190 const char* pLayerName,
3191 uint32_t* pPropertyCount,
3192 VkExtensionProperties* pProperties)
3193 {
3194 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3195
3196 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3197 if (radv_supported_instance_extensions.extensions[i]) {
3198 vk_outarray_append(&out, prop) {
3199 *prop = radv_instance_extensions[i];
3200 }
3201 }
3202 }
3203
3204 return vk_outarray_status(&out);
3205 }
3206
3207 VkResult radv_EnumerateDeviceExtensionProperties(
3208 VkPhysicalDevice physicalDevice,
3209 const char* pLayerName,
3210 uint32_t* pPropertyCount,
3211 VkExtensionProperties* pProperties)
3212 {
3213 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3214 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3215
3216 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3217 if (device->supported_extensions.extensions[i]) {
3218 vk_outarray_append(&out, prop) {
3219 *prop = radv_device_extensions[i];
3220 }
3221 }
3222 }
3223
3224 return vk_outarray_status(&out);
3225 }
3226
3227 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3228 VkInstance _instance,
3229 const char* pName)
3230 {
3231 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3232
3233 return radv_lookup_entrypoint_checked(pName,
3234 instance ? instance->apiVersion : 0,
3235 instance ? &instance->enabled_extensions : NULL,
3236 NULL);
3237 }
3238
3239 /* The loader wants us to expose a second GetInstanceProcAddr function
3240 * to work around certain LD_PRELOAD issues seen in apps.
3241 */
3242 PUBLIC
3243 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3244 VkInstance instance,
3245 const char* pName);
3246
3247 PUBLIC
3248 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3249 VkInstance instance,
3250 const char* pName)
3251 {
3252 return radv_GetInstanceProcAddr(instance, pName);
3253 }
3254
3255 PUBLIC
3256 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3257 VkInstance _instance,
3258 const char* pName);
3259
3260 PUBLIC
3261 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3262 VkInstance _instance,
3263 const char* pName)
3264 {
3265 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3266
3267 return radv_lookup_physical_device_entrypoint_checked(pName,
3268 instance ? instance->apiVersion : 0,
3269 instance ? &instance->enabled_extensions : NULL);
3270 }
3271
3272 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3273 VkDevice _device,
3274 const char* pName)
3275 {
3276 RADV_FROM_HANDLE(radv_device, device, _device);
3277
3278 return radv_lookup_entrypoint_checked(pName,
3279 device->instance->apiVersion,
3280 &device->instance->enabled_extensions,
3281 &device->enabled_extensions);
3282 }
3283
3284 bool radv_get_memory_fd(struct radv_device *device,
3285 struct radv_device_memory *memory,
3286 int *pFD)
3287 {
3288 struct radeon_bo_metadata metadata;
3289
3290 if (memory->image) {
3291 radv_init_metadata(device, memory->image, &metadata);
3292 device->ws->buffer_set_metadata(memory->bo, &metadata);
3293 }
3294
3295 return device->ws->buffer_get_fd(device->ws, memory->bo,
3296 pFD);
3297 }
3298
3299 static VkResult radv_alloc_memory(struct radv_device *device,
3300 const VkMemoryAllocateInfo* pAllocateInfo,
3301 const VkAllocationCallbacks* pAllocator,
3302 VkDeviceMemory* pMem)
3303 {
3304 struct radv_device_memory *mem;
3305 VkResult result;
3306 enum radeon_bo_domain domain;
3307 uint32_t flags = 0;
3308 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3309
3310 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3311
3312 if (pAllocateInfo->allocationSize == 0) {
3313 /* Apparently, this is allowed */
3314 *pMem = VK_NULL_HANDLE;
3315 return VK_SUCCESS;
3316 }
3317
3318 const VkImportMemoryFdInfoKHR *import_info =
3319 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3320 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3321 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3322 const VkExportMemoryAllocateInfo *export_info =
3323 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3324 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3325 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3326
3327 const struct wsi_memory_allocate_info *wsi_info =
3328 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3329
3330 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3331 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3332 if (mem == NULL)
3333 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3334
3335 if (wsi_info && wsi_info->implicit_sync)
3336 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3337
3338 if (dedicate_info) {
3339 mem->image = radv_image_from_handle(dedicate_info->image);
3340 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3341 } else {
3342 mem->image = NULL;
3343 mem->buffer = NULL;
3344 }
3345
3346 float priority_float = 0.5;
3347 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3348 vk_find_struct_const(pAllocateInfo->pNext,
3349 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3350 if (priority_ext)
3351 priority_float = priority_ext->priority;
3352
3353 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3354 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3355
3356 mem->user_ptr = NULL;
3357
3358 if (import_info) {
3359 assert(import_info->handleType ==
3360 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3361 import_info->handleType ==
3362 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3363 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3364 priority, NULL, NULL);
3365 if (!mem->bo) {
3366 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3367 goto fail;
3368 } else {
3369 close(import_info->fd);
3370 }
3371 } else if (host_ptr_info) {
3372 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3373 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3374 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3375 pAllocateInfo->allocationSize,
3376 priority);
3377 if (!mem->bo) {
3378 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3379 goto fail;
3380 } else {
3381 mem->user_ptr = host_ptr_info->pHostPointer;
3382 }
3383 } else {
3384 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3385 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3386 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3387 domain = RADEON_DOMAIN_GTT;
3388 else
3389 domain = RADEON_DOMAIN_VRAM;
3390
3391 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3392 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3393 else
3394 flags |= RADEON_FLAG_CPU_ACCESS;
3395
3396 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3397 flags |= RADEON_FLAG_GTT_WC;
3398
3399 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3400 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3401 if (device->use_global_bo_list) {
3402 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3403 }
3404 }
3405
3406 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3407 domain, flags, priority);
3408
3409 if (!mem->bo) {
3410 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3411 goto fail;
3412 }
3413 mem->type_index = mem_type_index;
3414 }
3415
3416 result = radv_bo_list_add(device, mem->bo);
3417 if (result != VK_SUCCESS)
3418 goto fail_bo;
3419
3420 *pMem = radv_device_memory_to_handle(mem);
3421
3422 return VK_SUCCESS;
3423
3424 fail_bo:
3425 device->ws->buffer_destroy(mem->bo);
3426 fail:
3427 vk_free2(&device->alloc, pAllocator, mem);
3428
3429 return result;
3430 }
3431
3432 VkResult radv_AllocateMemory(
3433 VkDevice _device,
3434 const VkMemoryAllocateInfo* pAllocateInfo,
3435 const VkAllocationCallbacks* pAllocator,
3436 VkDeviceMemory* pMem)
3437 {
3438 RADV_FROM_HANDLE(radv_device, device, _device);
3439 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3440 }
3441
3442 void radv_FreeMemory(
3443 VkDevice _device,
3444 VkDeviceMemory _mem,
3445 const VkAllocationCallbacks* pAllocator)
3446 {
3447 RADV_FROM_HANDLE(radv_device, device, _device);
3448 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3449
3450 if (mem == NULL)
3451 return;
3452
3453 radv_bo_list_remove(device, mem->bo);
3454 device->ws->buffer_destroy(mem->bo);
3455 mem->bo = NULL;
3456
3457 vk_free2(&device->alloc, pAllocator, mem);
3458 }
3459
3460 VkResult radv_MapMemory(
3461 VkDevice _device,
3462 VkDeviceMemory _memory,
3463 VkDeviceSize offset,
3464 VkDeviceSize size,
3465 VkMemoryMapFlags flags,
3466 void** ppData)
3467 {
3468 RADV_FROM_HANDLE(radv_device, device, _device);
3469 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3470
3471 if (mem == NULL) {
3472 *ppData = NULL;
3473 return VK_SUCCESS;
3474 }
3475
3476 if (mem->user_ptr)
3477 *ppData = mem->user_ptr;
3478 else
3479 *ppData = device->ws->buffer_map(mem->bo);
3480
3481 if (*ppData) {
3482 *ppData += offset;
3483 return VK_SUCCESS;
3484 }
3485
3486 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3487 }
3488
3489 void radv_UnmapMemory(
3490 VkDevice _device,
3491 VkDeviceMemory _memory)
3492 {
3493 RADV_FROM_HANDLE(radv_device, device, _device);
3494 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3495
3496 if (mem == NULL)
3497 return;
3498
3499 if (mem->user_ptr == NULL)
3500 device->ws->buffer_unmap(mem->bo);
3501 }
3502
3503 VkResult radv_FlushMappedMemoryRanges(
3504 VkDevice _device,
3505 uint32_t memoryRangeCount,
3506 const VkMappedMemoryRange* pMemoryRanges)
3507 {
3508 return VK_SUCCESS;
3509 }
3510
3511 VkResult radv_InvalidateMappedMemoryRanges(
3512 VkDevice _device,
3513 uint32_t memoryRangeCount,
3514 const VkMappedMemoryRange* pMemoryRanges)
3515 {
3516 return VK_SUCCESS;
3517 }
3518
3519 void radv_GetBufferMemoryRequirements(
3520 VkDevice _device,
3521 VkBuffer _buffer,
3522 VkMemoryRequirements* pMemoryRequirements)
3523 {
3524 RADV_FROM_HANDLE(radv_device, device, _device);
3525 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3526
3527 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3528
3529 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3530 pMemoryRequirements->alignment = 4096;
3531 else
3532 pMemoryRequirements->alignment = 16;
3533
3534 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3535 }
3536
3537 void radv_GetBufferMemoryRequirements2(
3538 VkDevice device,
3539 const VkBufferMemoryRequirementsInfo2 *pInfo,
3540 VkMemoryRequirements2 *pMemoryRequirements)
3541 {
3542 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3543 &pMemoryRequirements->memoryRequirements);
3544 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3545 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3546 switch (ext->sType) {
3547 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3548 VkMemoryDedicatedRequirements *req =
3549 (VkMemoryDedicatedRequirements *) ext;
3550 req->requiresDedicatedAllocation = buffer->shareable;
3551 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3552 break;
3553 }
3554 default:
3555 break;
3556 }
3557 }
3558 }
3559
3560 void radv_GetImageMemoryRequirements(
3561 VkDevice _device,
3562 VkImage _image,
3563 VkMemoryRequirements* pMemoryRequirements)
3564 {
3565 RADV_FROM_HANDLE(radv_device, device, _device);
3566 RADV_FROM_HANDLE(radv_image, image, _image);
3567
3568 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3569
3570 pMemoryRequirements->size = image->size;
3571 pMemoryRequirements->alignment = image->alignment;
3572 }
3573
3574 void radv_GetImageMemoryRequirements2(
3575 VkDevice device,
3576 const VkImageMemoryRequirementsInfo2 *pInfo,
3577 VkMemoryRequirements2 *pMemoryRequirements)
3578 {
3579 radv_GetImageMemoryRequirements(device, pInfo->image,
3580 &pMemoryRequirements->memoryRequirements);
3581
3582 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3583
3584 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3585 switch (ext->sType) {
3586 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3587 VkMemoryDedicatedRequirements *req =
3588 (VkMemoryDedicatedRequirements *) ext;
3589 req->requiresDedicatedAllocation = image->shareable;
3590 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3591 break;
3592 }
3593 default:
3594 break;
3595 }
3596 }
3597 }
3598
3599 void radv_GetImageSparseMemoryRequirements(
3600 VkDevice device,
3601 VkImage image,
3602 uint32_t* pSparseMemoryRequirementCount,
3603 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3604 {
3605 stub();
3606 }
3607
3608 void radv_GetImageSparseMemoryRequirements2(
3609 VkDevice device,
3610 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3611 uint32_t* pSparseMemoryRequirementCount,
3612 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3613 {
3614 stub();
3615 }
3616
3617 void radv_GetDeviceMemoryCommitment(
3618 VkDevice device,
3619 VkDeviceMemory memory,
3620 VkDeviceSize* pCommittedMemoryInBytes)
3621 {
3622 *pCommittedMemoryInBytes = 0;
3623 }
3624
3625 VkResult radv_BindBufferMemory2(VkDevice device,
3626 uint32_t bindInfoCount,
3627 const VkBindBufferMemoryInfo *pBindInfos)
3628 {
3629 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3630 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3631 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3632
3633 if (mem) {
3634 buffer->bo = mem->bo;
3635 buffer->offset = pBindInfos[i].memoryOffset;
3636 } else {
3637 buffer->bo = NULL;
3638 }
3639 }
3640 return VK_SUCCESS;
3641 }
3642
3643 VkResult radv_BindBufferMemory(
3644 VkDevice device,
3645 VkBuffer buffer,
3646 VkDeviceMemory memory,
3647 VkDeviceSize memoryOffset)
3648 {
3649 const VkBindBufferMemoryInfo info = {
3650 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3651 .buffer = buffer,
3652 .memory = memory,
3653 .memoryOffset = memoryOffset
3654 };
3655
3656 return radv_BindBufferMemory2(device, 1, &info);
3657 }
3658
3659 VkResult radv_BindImageMemory2(VkDevice device,
3660 uint32_t bindInfoCount,
3661 const VkBindImageMemoryInfo *pBindInfos)
3662 {
3663 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3664 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3665 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3666
3667 if (mem) {
3668 image->bo = mem->bo;
3669 image->offset = pBindInfos[i].memoryOffset;
3670 } else {
3671 image->bo = NULL;
3672 image->offset = 0;
3673 }
3674 }
3675 return VK_SUCCESS;
3676 }
3677
3678
3679 VkResult radv_BindImageMemory(
3680 VkDevice device,
3681 VkImage image,
3682 VkDeviceMemory memory,
3683 VkDeviceSize memoryOffset)
3684 {
3685 const VkBindImageMemoryInfo info = {
3686 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3687 .image = image,
3688 .memory = memory,
3689 .memoryOffset = memoryOffset
3690 };
3691
3692 return radv_BindImageMemory2(device, 1, &info);
3693 }
3694
3695
3696 static void
3697 radv_sparse_buffer_bind_memory(struct radv_device *device,
3698 const VkSparseBufferMemoryBindInfo *bind)
3699 {
3700 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3701
3702 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3703 struct radv_device_memory *mem = NULL;
3704
3705 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3706 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3707
3708 device->ws->buffer_virtual_bind(buffer->bo,
3709 bind->pBinds[i].resourceOffset,
3710 bind->pBinds[i].size,
3711 mem ? mem->bo : NULL,
3712 bind->pBinds[i].memoryOffset);
3713 }
3714 }
3715
3716 static void
3717 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3718 const VkSparseImageOpaqueMemoryBindInfo *bind)
3719 {
3720 RADV_FROM_HANDLE(radv_image, image, bind->image);
3721
3722 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3723 struct radv_device_memory *mem = NULL;
3724
3725 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3726 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3727
3728 device->ws->buffer_virtual_bind(image->bo,
3729 bind->pBinds[i].resourceOffset,
3730 bind->pBinds[i].size,
3731 mem ? mem->bo : NULL,
3732 bind->pBinds[i].memoryOffset);
3733 }
3734 }
3735
3736 VkResult radv_QueueBindSparse(
3737 VkQueue _queue,
3738 uint32_t bindInfoCount,
3739 const VkBindSparseInfo* pBindInfo,
3740 VkFence _fence)
3741 {
3742 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3743 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3744 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3745 bool fence_emitted = false;
3746 VkResult result;
3747 int ret;
3748
3749 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3750 struct radv_winsys_sem_info sem_info;
3751 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3752 radv_sparse_buffer_bind_memory(queue->device,
3753 pBindInfo[i].pBufferBinds + j);
3754 }
3755
3756 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3757 radv_sparse_image_opaque_bind_memory(queue->device,
3758 pBindInfo[i].pImageOpaqueBinds + j);
3759 }
3760
3761 VkResult result;
3762 result = radv_alloc_sem_info(queue->device->instance,
3763 &sem_info,
3764 pBindInfo[i].waitSemaphoreCount,
3765 pBindInfo[i].pWaitSemaphores,
3766 pBindInfo[i].signalSemaphoreCount,
3767 pBindInfo[i].pSignalSemaphores,
3768 _fence);
3769 if (result != VK_SUCCESS)
3770 return result;
3771
3772 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3773 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3774 &queue->device->empty_cs[queue->queue_family_index],
3775 1, NULL, NULL,
3776 &sem_info, NULL,
3777 false, base_fence);
3778 if (ret) {
3779 radv_loge("failed to submit CS %d\n", i);
3780 abort();
3781 }
3782
3783 fence_emitted = true;
3784 }
3785
3786 radv_free_sem_info(&sem_info);
3787
3788 }
3789
3790 if (fence) {
3791 if (!fence_emitted) {
3792 result = radv_signal_fence(queue, fence);
3793 if (result != VK_SUCCESS)
3794 return result;
3795 }
3796 }
3797
3798 return VK_SUCCESS;
3799 }
3800
3801 VkResult radv_CreateFence(
3802 VkDevice _device,
3803 const VkFenceCreateInfo* pCreateInfo,
3804 const VkAllocationCallbacks* pAllocator,
3805 VkFence* pFence)
3806 {
3807 RADV_FROM_HANDLE(radv_device, device, _device);
3808 const VkExportFenceCreateInfo *export =
3809 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3810 VkExternalFenceHandleTypeFlags handleTypes =
3811 export ? export->handleTypes : 0;
3812
3813 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3814 sizeof(*fence), 8,
3815 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3816
3817 if (!fence)
3818 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3819
3820 fence->fence_wsi = NULL;
3821 fence->temp_syncobj = 0;
3822 if (device->always_use_syncobj || handleTypes) {
3823 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3824 if (ret) {
3825 vk_free2(&device->alloc, pAllocator, fence);
3826 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3827 }
3828 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3829 device->ws->signal_syncobj(device->ws, fence->syncobj);
3830 }
3831 fence->fence = NULL;
3832 } else {
3833 fence->fence = device->ws->create_fence();
3834 if (!fence->fence) {
3835 vk_free2(&device->alloc, pAllocator, fence);
3836 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3837 }
3838 fence->syncobj = 0;
3839 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3840 device->ws->signal_fence(fence->fence);
3841 }
3842
3843 *pFence = radv_fence_to_handle(fence);
3844
3845 return VK_SUCCESS;
3846 }
3847
3848 void radv_DestroyFence(
3849 VkDevice _device,
3850 VkFence _fence,
3851 const VkAllocationCallbacks* pAllocator)
3852 {
3853 RADV_FROM_HANDLE(radv_device, device, _device);
3854 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3855
3856 if (!fence)
3857 return;
3858
3859 if (fence->temp_syncobj)
3860 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3861 if (fence->syncobj)
3862 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3863 if (fence->fence)
3864 device->ws->destroy_fence(fence->fence);
3865 if (fence->fence_wsi)
3866 fence->fence_wsi->destroy(fence->fence_wsi);
3867 vk_free2(&device->alloc, pAllocator, fence);
3868 }
3869
3870
3871 uint64_t radv_get_current_time(void)
3872 {
3873 struct timespec tv;
3874 clock_gettime(CLOCK_MONOTONIC, &tv);
3875 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3876 }
3877
3878 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3879 {
3880 uint64_t current_time = radv_get_current_time();
3881
3882 timeout = MIN2(UINT64_MAX - current_time, timeout);
3883
3884 return current_time + timeout;
3885 }
3886
3887
3888 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3889 uint32_t fenceCount, const VkFence *pFences)
3890 {
3891 for (uint32_t i = 0; i < fenceCount; ++i) {
3892 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3893 if (fence->fence == NULL || fence->syncobj ||
3894 fence->temp_syncobj || fence->fence_wsi ||
3895 (!device->ws->is_fence_waitable(fence->fence)))
3896 return false;
3897 }
3898 return true;
3899 }
3900
3901 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3902 {
3903 for (uint32_t i = 0; i < fenceCount; ++i) {
3904 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3905 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3906 return false;
3907 }
3908 return true;
3909 }
3910
3911 VkResult radv_WaitForFences(
3912 VkDevice _device,
3913 uint32_t fenceCount,
3914 const VkFence* pFences,
3915 VkBool32 waitAll,
3916 uint64_t timeout)
3917 {
3918 RADV_FROM_HANDLE(radv_device, device, _device);
3919 timeout = radv_get_absolute_timeout(timeout);
3920
3921 if (device->always_use_syncobj &&
3922 radv_all_fences_syncobj(fenceCount, pFences))
3923 {
3924 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3925 if (!handles)
3926 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3927
3928 for (uint32_t i = 0; i < fenceCount; ++i) {
3929 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3930 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3931 }
3932
3933 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3934
3935 free(handles);
3936 return success ? VK_SUCCESS : VK_TIMEOUT;
3937 }
3938
3939 if (!waitAll && fenceCount > 1) {
3940 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3941 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3942 uint32_t wait_count = 0;
3943 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3944 if (!fences)
3945 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3946
3947 for (uint32_t i = 0; i < fenceCount; ++i) {
3948 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3949
3950 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3951 free(fences);
3952 return VK_SUCCESS;
3953 }
3954
3955 fences[wait_count++] = fence->fence;
3956 }
3957
3958 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3959 waitAll, timeout - radv_get_current_time());
3960
3961 free(fences);
3962 return success ? VK_SUCCESS : VK_TIMEOUT;
3963 }
3964
3965 while(radv_get_current_time() <= timeout) {
3966 for (uint32_t i = 0; i < fenceCount; ++i) {
3967 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3968 return VK_SUCCESS;
3969 }
3970 }
3971 return VK_TIMEOUT;
3972 }
3973
3974 for (uint32_t i = 0; i < fenceCount; ++i) {
3975 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3976 bool expired = false;
3977
3978 if (fence->temp_syncobj) {
3979 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3980 return VK_TIMEOUT;
3981 continue;
3982 }
3983
3984 if (fence->syncobj) {
3985 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3986 return VK_TIMEOUT;
3987 continue;
3988 }
3989
3990 if (fence->fence) {
3991 if (!device->ws->is_fence_waitable(fence->fence)) {
3992 while(!device->ws->is_fence_waitable(fence->fence) &&
3993 radv_get_current_time() <= timeout)
3994 /* Do nothing */;
3995 }
3996
3997 expired = device->ws->fence_wait(device->ws,
3998 fence->fence,
3999 true, timeout);
4000 if (!expired)
4001 return VK_TIMEOUT;
4002 }
4003
4004 if (fence->fence_wsi) {
4005 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4006 if (result != VK_SUCCESS)
4007 return result;
4008 }
4009 }
4010
4011 return VK_SUCCESS;
4012 }
4013
4014 VkResult radv_ResetFences(VkDevice _device,
4015 uint32_t fenceCount,
4016 const VkFence *pFences)
4017 {
4018 RADV_FROM_HANDLE(radv_device, device, _device);
4019
4020 for (unsigned i = 0; i < fenceCount; ++i) {
4021 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4022 if (fence->fence)
4023 device->ws->reset_fence(fence->fence);
4024
4025 /* Per spec, we first restore the permanent payload, and then reset, so
4026 * having a temp syncobj should not skip resetting the permanent syncobj. */
4027 if (fence->temp_syncobj) {
4028 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4029 fence->temp_syncobj = 0;
4030 }
4031
4032 if (fence->syncobj) {
4033 device->ws->reset_syncobj(device->ws, fence->syncobj);
4034 }
4035 }
4036
4037 return VK_SUCCESS;
4038 }
4039
4040 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4041 {
4042 RADV_FROM_HANDLE(radv_device, device, _device);
4043 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4044
4045 if (fence->temp_syncobj) {
4046 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4047 return success ? VK_SUCCESS : VK_NOT_READY;
4048 }
4049
4050 if (fence->syncobj) {
4051 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4052 return success ? VK_SUCCESS : VK_NOT_READY;
4053 }
4054
4055 if (fence->fence) {
4056 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4057 return VK_NOT_READY;
4058 }
4059 if (fence->fence_wsi) {
4060 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4061
4062 if (result != VK_SUCCESS) {
4063 if (result == VK_TIMEOUT)
4064 return VK_NOT_READY;
4065 return result;
4066 }
4067 }
4068 return VK_SUCCESS;
4069 }
4070
4071
4072 // Queue semaphore functions
4073
4074 VkResult radv_CreateSemaphore(
4075 VkDevice _device,
4076 const VkSemaphoreCreateInfo* pCreateInfo,
4077 const VkAllocationCallbacks* pAllocator,
4078 VkSemaphore* pSemaphore)
4079 {
4080 RADV_FROM_HANDLE(radv_device, device, _device);
4081 const VkExportSemaphoreCreateInfo *export =
4082 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4083 VkExternalSemaphoreHandleTypeFlags handleTypes =
4084 export ? export->handleTypes : 0;
4085
4086 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4087 sizeof(*sem), 8,
4088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4089 if (!sem)
4090 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4091
4092 sem->temp_syncobj = 0;
4093 /* create a syncobject if we are going to export this semaphore */
4094 if (device->always_use_syncobj || handleTypes) {
4095 assert (device->physical_device->rad_info.has_syncobj);
4096 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4097 if (ret) {
4098 vk_free2(&device->alloc, pAllocator, sem);
4099 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4100 }
4101 sem->sem = NULL;
4102 } else {
4103 sem->sem = device->ws->create_sem(device->ws);
4104 if (!sem->sem) {
4105 vk_free2(&device->alloc, pAllocator, sem);
4106 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4107 }
4108 sem->syncobj = 0;
4109 }
4110
4111 *pSemaphore = radv_semaphore_to_handle(sem);
4112 return VK_SUCCESS;
4113 }
4114
4115 void radv_DestroySemaphore(
4116 VkDevice _device,
4117 VkSemaphore _semaphore,
4118 const VkAllocationCallbacks* pAllocator)
4119 {
4120 RADV_FROM_HANDLE(radv_device, device, _device);
4121 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4122 if (!_semaphore)
4123 return;
4124
4125 if (sem->syncobj)
4126 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4127 else
4128 device->ws->destroy_sem(sem->sem);
4129 vk_free2(&device->alloc, pAllocator, sem);
4130 }
4131
4132 VkResult radv_CreateEvent(
4133 VkDevice _device,
4134 const VkEventCreateInfo* pCreateInfo,
4135 const VkAllocationCallbacks* pAllocator,
4136 VkEvent* pEvent)
4137 {
4138 RADV_FROM_HANDLE(radv_device, device, _device);
4139 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4140 sizeof(*event), 8,
4141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4142
4143 if (!event)
4144 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4145
4146 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4147 RADEON_DOMAIN_GTT,
4148 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4149 RADV_BO_PRIORITY_FENCE);
4150 if (!event->bo) {
4151 vk_free2(&device->alloc, pAllocator, event);
4152 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4153 }
4154
4155 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4156
4157 *pEvent = radv_event_to_handle(event);
4158
4159 return VK_SUCCESS;
4160 }
4161
4162 void radv_DestroyEvent(
4163 VkDevice _device,
4164 VkEvent _event,
4165 const VkAllocationCallbacks* pAllocator)
4166 {
4167 RADV_FROM_HANDLE(radv_device, device, _device);
4168 RADV_FROM_HANDLE(radv_event, event, _event);
4169
4170 if (!event)
4171 return;
4172 device->ws->buffer_destroy(event->bo);
4173 vk_free2(&device->alloc, pAllocator, event);
4174 }
4175
4176 VkResult radv_GetEventStatus(
4177 VkDevice _device,
4178 VkEvent _event)
4179 {
4180 RADV_FROM_HANDLE(radv_event, event, _event);
4181
4182 if (*event->map == 1)
4183 return VK_EVENT_SET;
4184 return VK_EVENT_RESET;
4185 }
4186
4187 VkResult radv_SetEvent(
4188 VkDevice _device,
4189 VkEvent _event)
4190 {
4191 RADV_FROM_HANDLE(radv_event, event, _event);
4192 *event->map = 1;
4193
4194 return VK_SUCCESS;
4195 }
4196
4197 VkResult radv_ResetEvent(
4198 VkDevice _device,
4199 VkEvent _event)
4200 {
4201 RADV_FROM_HANDLE(radv_event, event, _event);
4202 *event->map = 0;
4203
4204 return VK_SUCCESS;
4205 }
4206
4207 VkResult radv_CreateBuffer(
4208 VkDevice _device,
4209 const VkBufferCreateInfo* pCreateInfo,
4210 const VkAllocationCallbacks* pAllocator,
4211 VkBuffer* pBuffer)
4212 {
4213 RADV_FROM_HANDLE(radv_device, device, _device);
4214 struct radv_buffer *buffer;
4215
4216 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4217
4218 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4219 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4220 if (buffer == NULL)
4221 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4222
4223 buffer->size = pCreateInfo->size;
4224 buffer->usage = pCreateInfo->usage;
4225 buffer->bo = NULL;
4226 buffer->offset = 0;
4227 buffer->flags = pCreateInfo->flags;
4228
4229 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4230 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4231
4232 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4233 buffer->bo = device->ws->buffer_create(device->ws,
4234 align64(buffer->size, 4096),
4235 4096, 0, RADEON_FLAG_VIRTUAL,
4236 RADV_BO_PRIORITY_VIRTUAL);
4237 if (!buffer->bo) {
4238 vk_free2(&device->alloc, pAllocator, buffer);
4239 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4240 }
4241 }
4242
4243 *pBuffer = radv_buffer_to_handle(buffer);
4244
4245 return VK_SUCCESS;
4246 }
4247
4248 void radv_DestroyBuffer(
4249 VkDevice _device,
4250 VkBuffer _buffer,
4251 const VkAllocationCallbacks* pAllocator)
4252 {
4253 RADV_FROM_HANDLE(radv_device, device, _device);
4254 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4255
4256 if (!buffer)
4257 return;
4258
4259 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4260 device->ws->buffer_destroy(buffer->bo);
4261
4262 vk_free2(&device->alloc, pAllocator, buffer);
4263 }
4264
4265 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4266 VkDevice device,
4267 const VkBufferDeviceAddressInfoEXT* pInfo)
4268 {
4269 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4270 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4271 }
4272
4273
4274 static inline unsigned
4275 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4276 {
4277 if (stencil)
4278 return plane->surface.u.legacy.stencil_tiling_index[level];
4279 else
4280 return plane->surface.u.legacy.tiling_index[level];
4281 }
4282
4283 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4284 {
4285 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4286 }
4287
4288 static uint32_t
4289 radv_init_dcc_control_reg(struct radv_device *device,
4290 struct radv_image_view *iview)
4291 {
4292 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4293 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4294 unsigned max_compressed_block_size;
4295 unsigned independent_128b_blocks;
4296 unsigned independent_64b_blocks;
4297
4298 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4299 return 0;
4300
4301 if (!device->physical_device->rad_info.has_dedicated_vram) {
4302 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4303 * dGPU and 64 for APU because all of our APUs to date use
4304 * DIMMs which have a request granularity size of 64B while all
4305 * other chips have a 32B request size.
4306 */
4307 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4308 }
4309
4310 if (device->physical_device->rad_info.chip_class >= GFX10) {
4311 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4312 independent_64b_blocks = 0;
4313 independent_128b_blocks = 1;
4314 } else {
4315 independent_128b_blocks = 0;
4316
4317 if (iview->image->info.samples > 1) {
4318 if (iview->image->planes[0].surface.bpe == 1)
4319 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4320 else if (iview->image->planes[0].surface.bpe == 2)
4321 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4322 }
4323
4324 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4325 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4326 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4327 /* If this DCC image is potentially going to be used in texture
4328 * fetches, we need some special settings.
4329 */
4330 independent_64b_blocks = 1;
4331 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4332 } else {
4333 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4334 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4335 * big as possible for better compression state.
4336 */
4337 independent_64b_blocks = 0;
4338 max_compressed_block_size = max_uncompressed_block_size;
4339 }
4340 }
4341
4342 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4343 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4344 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4345 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4346 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4347 }
4348
4349 static void
4350 radv_initialise_color_surface(struct radv_device *device,
4351 struct radv_color_buffer_info *cb,
4352 struct radv_image_view *iview)
4353 {
4354 const struct vk_format_description *desc;
4355 unsigned ntype, format, swap, endian;
4356 unsigned blend_clamp = 0, blend_bypass = 0;
4357 uint64_t va;
4358 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4359 const struct radeon_surf *surf = &plane->surface;
4360
4361 desc = vk_format_description(iview->vk_format);
4362
4363 memset(cb, 0, sizeof(*cb));
4364
4365 /* Intensity is implemented as Red, so treat it that way. */
4366 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4367
4368 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4369
4370 cb->cb_color_base = va >> 8;
4371
4372 if (device->physical_device->rad_info.chip_class >= GFX9) {
4373 struct gfx9_surf_meta_flags meta;
4374 if (iview->image->dcc_offset)
4375 meta = surf->u.gfx9.dcc;
4376 else
4377 meta = surf->u.gfx9.cmask;
4378
4379 if (device->physical_device->rad_info.chip_class >= GFX10) {
4380 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4381 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4382 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4383 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4384 } else {
4385 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4386 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4387 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4388 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4389 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4390 }
4391
4392 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4393 cb->cb_color_base |= surf->tile_swizzle;
4394 } else {
4395 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4396 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4397
4398 cb->cb_color_base += level_info->offset >> 8;
4399 if (level_info->mode == RADEON_SURF_MODE_2D)
4400 cb->cb_color_base |= surf->tile_swizzle;
4401
4402 pitch_tile_max = level_info->nblk_x / 8 - 1;
4403 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4404 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4405
4406 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4407 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4408 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4409
4410 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4411
4412 if (radv_image_has_fmask(iview->image)) {
4413 if (device->physical_device->rad_info.chip_class >= GFX7)
4414 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4415 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4416 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4417 } else {
4418 /* This must be set for fast clear to work without FMASK. */
4419 if (device->physical_device->rad_info.chip_class >= GFX7)
4420 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4421 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4422 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4423 }
4424 }
4425
4426 /* CMASK variables */
4427 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4428 va += iview->image->cmask.offset;
4429 cb->cb_color_cmask = va >> 8;
4430
4431 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4432 va += iview->image->dcc_offset;
4433
4434 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4435 device->physical_device->rad_info.chip_class <= GFX8)
4436 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4437
4438 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4439 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4440
4441 cb->cb_dcc_base = va >> 8;
4442 cb->cb_dcc_base |= dcc_tile_swizzle;
4443
4444 /* GFX10 field has the same base shift as the GFX6 field. */
4445 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4446 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4447 S_028C6C_SLICE_MAX_GFX10(max_slice);
4448
4449 if (iview->image->info.samples > 1) {
4450 unsigned log_samples = util_logbase2(iview->image->info.samples);
4451
4452 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4453 S_028C74_NUM_FRAGMENTS(log_samples);
4454 }
4455
4456 if (radv_image_has_fmask(iview->image)) {
4457 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4458 cb->cb_color_fmask = va >> 8;
4459 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4460 } else {
4461 cb->cb_color_fmask = cb->cb_color_base;
4462 }
4463
4464 ntype = radv_translate_color_numformat(iview->vk_format,
4465 desc,
4466 vk_format_get_first_non_void_channel(iview->vk_format));
4467 format = radv_translate_colorformat(iview->vk_format);
4468 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4469 radv_finishme("Illegal color\n");
4470 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4471 endian = radv_colorformat_endian_swap(format);
4472
4473 /* blend clamp should be set for all NORM/SRGB types */
4474 if (ntype == V_028C70_NUMBER_UNORM ||
4475 ntype == V_028C70_NUMBER_SNORM ||
4476 ntype == V_028C70_NUMBER_SRGB)
4477 blend_clamp = 1;
4478
4479 /* set blend bypass according to docs if SINT/UINT or
4480 8/24 COLOR variants */
4481 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4482 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4483 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4484 blend_clamp = 0;
4485 blend_bypass = 1;
4486 }
4487 #if 0
4488 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4489 (format == V_028C70_COLOR_8 ||
4490 format == V_028C70_COLOR_8_8 ||
4491 format == V_028C70_COLOR_8_8_8_8))
4492 ->color_is_int8 = true;
4493 #endif
4494 cb->cb_color_info = S_028C70_FORMAT(format) |
4495 S_028C70_COMP_SWAP(swap) |
4496 S_028C70_BLEND_CLAMP(blend_clamp) |
4497 S_028C70_BLEND_BYPASS(blend_bypass) |
4498 S_028C70_SIMPLE_FLOAT(1) |
4499 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4500 ntype != V_028C70_NUMBER_SNORM &&
4501 ntype != V_028C70_NUMBER_SRGB &&
4502 format != V_028C70_COLOR_8_24 &&
4503 format != V_028C70_COLOR_24_8) |
4504 S_028C70_NUMBER_TYPE(ntype) |
4505 S_028C70_ENDIAN(endian);
4506 if (radv_image_has_fmask(iview->image)) {
4507 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4508 if (device->physical_device->rad_info.chip_class == GFX6) {
4509 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4510 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4511 }
4512
4513 if (radv_image_is_tc_compat_cmask(iview->image)) {
4514 /* Allow the texture block to read FMASK directly
4515 * without decompressing it. This bit must be cleared
4516 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4517 * otherwise the operation doesn't happen.
4518 */
4519 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4520
4521 /* Set CMASK into a tiling format that allows the
4522 * texture block to read it.
4523 */
4524 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4525 }
4526 }
4527
4528 if (radv_image_has_cmask(iview->image) &&
4529 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4530 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4531
4532 if (radv_dcc_enabled(iview->image, iview->base_mip))
4533 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4534
4535 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4536
4537 /* This must be set for fast clear to work without FMASK. */
4538 if (!radv_image_has_fmask(iview->image) &&
4539 device->physical_device->rad_info.chip_class == GFX6) {
4540 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4541 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4542 }
4543
4544 if (device->physical_device->rad_info.chip_class >= GFX9) {
4545 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4546
4547 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4548 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4549 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4550 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4551
4552 if (device->physical_device->rad_info.chip_class >= GFX10) {
4553 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4554
4555 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4556 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4557 S_028EE0_RESOURCE_LEVEL(1);
4558 } else {
4559 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4560 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4561 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4562 }
4563
4564 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4565 S_028C68_MIP0_HEIGHT(height - 1) |
4566 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4567 }
4568 }
4569
4570 static unsigned
4571 radv_calc_decompress_on_z_planes(struct radv_device *device,
4572 struct radv_image_view *iview)
4573 {
4574 unsigned max_zplanes = 0;
4575
4576 assert(radv_image_is_tc_compat_htile(iview->image));
4577
4578 if (device->physical_device->rad_info.chip_class >= GFX9) {
4579 /* Default value for 32-bit depth surfaces. */
4580 max_zplanes = 4;
4581
4582 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4583 iview->image->info.samples > 1)
4584 max_zplanes = 2;
4585
4586 max_zplanes = max_zplanes + 1;
4587 } else {
4588 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4589 /* Do not enable Z plane compression for 16-bit depth
4590 * surfaces because isn't supported on GFX8. Only
4591 * 32-bit depth surfaces are supported by the hardware.
4592 * This allows to maintain shader compatibility and to
4593 * reduce the number of depth decompressions.
4594 */
4595 max_zplanes = 1;
4596 } else {
4597 if (iview->image->info.samples <= 1)
4598 max_zplanes = 5;
4599 else if (iview->image->info.samples <= 4)
4600 max_zplanes = 3;
4601 else
4602 max_zplanes = 2;
4603 }
4604 }
4605
4606 return max_zplanes;
4607 }
4608
4609 static void
4610 radv_initialise_ds_surface(struct radv_device *device,
4611 struct radv_ds_buffer_info *ds,
4612 struct radv_image_view *iview)
4613 {
4614 unsigned level = iview->base_mip;
4615 unsigned format, stencil_format;
4616 uint64_t va, s_offs, z_offs;
4617 bool stencil_only = false;
4618 const struct radv_image_plane *plane = &iview->image->planes[0];
4619 const struct radeon_surf *surf = &plane->surface;
4620
4621 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4622
4623 memset(ds, 0, sizeof(*ds));
4624 switch (iview->image->vk_format) {
4625 case VK_FORMAT_D24_UNORM_S8_UINT:
4626 case VK_FORMAT_X8_D24_UNORM_PACK32:
4627 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4628 ds->offset_scale = 2.0f;
4629 break;
4630 case VK_FORMAT_D16_UNORM:
4631 case VK_FORMAT_D16_UNORM_S8_UINT:
4632 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4633 ds->offset_scale = 4.0f;
4634 break;
4635 case VK_FORMAT_D32_SFLOAT:
4636 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4637 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4638 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4639 ds->offset_scale = 1.0f;
4640 break;
4641 case VK_FORMAT_S8_UINT:
4642 stencil_only = true;
4643 break;
4644 default:
4645 break;
4646 }
4647
4648 format = radv_translate_dbformat(iview->image->vk_format);
4649 stencil_format = surf->has_stencil ?
4650 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4651
4652 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4653 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4654 S_028008_SLICE_MAX(max_slice);
4655 if (device->physical_device->rad_info.chip_class >= GFX10) {
4656 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4657 S_028008_SLICE_MAX_HI(max_slice >> 11);
4658 }
4659
4660 ds->db_htile_data_base = 0;
4661 ds->db_htile_surface = 0;
4662
4663 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4664 s_offs = z_offs = va;
4665
4666 if (device->physical_device->rad_info.chip_class >= GFX9) {
4667 assert(surf->u.gfx9.surf_offset == 0);
4668 s_offs += surf->u.gfx9.stencil_offset;
4669
4670 ds->db_z_info = S_028038_FORMAT(format) |
4671 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4672 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4673 S_028038_MAXMIP(iview->image->info.levels - 1) |
4674 S_028038_ZRANGE_PRECISION(1);
4675 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4676 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4677
4678 if (device->physical_device->rad_info.chip_class == GFX9) {
4679 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4680 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4681 }
4682
4683 ds->db_depth_view |= S_028008_MIPID(level);
4684 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4685 S_02801C_Y_MAX(iview->image->info.height - 1);
4686
4687 if (radv_htile_enabled(iview->image, level)) {
4688 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4689
4690 if (radv_image_is_tc_compat_htile(iview->image)) {
4691 unsigned max_zplanes =
4692 radv_calc_decompress_on_z_planes(device, iview);
4693
4694 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4695
4696 if (device->physical_device->rad_info.chip_class >= GFX10) {
4697 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4698 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4699 } else {
4700 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4701 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4702 }
4703 }
4704
4705 if (!surf->has_stencil)
4706 /* Use all of the htile_buffer for depth if there's no stencil. */
4707 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4708 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4709 iview->image->htile_offset;
4710 ds->db_htile_data_base = va >> 8;
4711 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4712 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4713
4714 if (device->physical_device->rad_info.chip_class == GFX9) {
4715 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4716 }
4717 }
4718 } else {
4719 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4720
4721 if (stencil_only)
4722 level_info = &surf->u.legacy.stencil_level[level];
4723
4724 z_offs += surf->u.legacy.level[level].offset;
4725 s_offs += surf->u.legacy.stencil_level[level].offset;
4726
4727 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4728 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4729 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4730
4731 if (iview->image->info.samples > 1)
4732 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4733
4734 if (device->physical_device->rad_info.chip_class >= GFX7) {
4735 struct radeon_info *info = &device->physical_device->rad_info;
4736 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4737 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4738 unsigned macro_index = surf->u.legacy.macro_tile_index;
4739 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4740 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4741 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4742
4743 if (stencil_only)
4744 tile_mode = stencil_tile_mode;
4745
4746 ds->db_depth_info |=
4747 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4748 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4749 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4750 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4751 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4752 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4753 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4754 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4755 } else {
4756 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4757 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4758 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4759 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4760 if (stencil_only)
4761 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4762 }
4763
4764 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4765 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4766 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4767
4768 if (radv_htile_enabled(iview->image, level)) {
4769 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4770
4771 if (!surf->has_stencil &&
4772 !radv_image_is_tc_compat_htile(iview->image))
4773 /* Use all of the htile_buffer for depth if there's no stencil. */
4774 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4775
4776 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4777 iview->image->htile_offset;
4778 ds->db_htile_data_base = va >> 8;
4779 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4780
4781 if (radv_image_is_tc_compat_htile(iview->image)) {
4782 unsigned max_zplanes =
4783 radv_calc_decompress_on_z_planes(device, iview);
4784
4785 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4786 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4787 }
4788 }
4789 }
4790
4791 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4792 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4793 }
4794
4795 VkResult radv_CreateFramebuffer(
4796 VkDevice _device,
4797 const VkFramebufferCreateInfo* pCreateInfo,
4798 const VkAllocationCallbacks* pAllocator,
4799 VkFramebuffer* pFramebuffer)
4800 {
4801 RADV_FROM_HANDLE(radv_device, device, _device);
4802 struct radv_framebuffer *framebuffer;
4803
4804 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4805
4806 size_t size = sizeof(*framebuffer) +
4807 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4808 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4809 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4810 if (framebuffer == NULL)
4811 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4812
4813 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4814 framebuffer->width = pCreateInfo->width;
4815 framebuffer->height = pCreateInfo->height;
4816 framebuffer->layers = pCreateInfo->layers;
4817 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4818 VkImageView _iview = pCreateInfo->pAttachments[i];
4819 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4820 framebuffer->attachments[i].attachment = iview;
4821 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4822 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4823 } else {
4824 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4825 }
4826 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4827 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4828 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4829 }
4830
4831 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4832 return VK_SUCCESS;
4833 }
4834
4835 void radv_DestroyFramebuffer(
4836 VkDevice _device,
4837 VkFramebuffer _fb,
4838 const VkAllocationCallbacks* pAllocator)
4839 {
4840 RADV_FROM_HANDLE(radv_device, device, _device);
4841 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4842
4843 if (!fb)
4844 return;
4845 vk_free2(&device->alloc, pAllocator, fb);
4846 }
4847
4848 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4849 {
4850 switch (address_mode) {
4851 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4852 return V_008F30_SQ_TEX_WRAP;
4853 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4854 return V_008F30_SQ_TEX_MIRROR;
4855 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4856 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4857 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4858 return V_008F30_SQ_TEX_CLAMP_BORDER;
4859 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4860 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4861 default:
4862 unreachable("illegal tex wrap mode");
4863 break;
4864 }
4865 }
4866
4867 static unsigned
4868 radv_tex_compare(VkCompareOp op)
4869 {
4870 switch (op) {
4871 case VK_COMPARE_OP_NEVER:
4872 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4873 case VK_COMPARE_OP_LESS:
4874 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4875 case VK_COMPARE_OP_EQUAL:
4876 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4877 case VK_COMPARE_OP_LESS_OR_EQUAL:
4878 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4879 case VK_COMPARE_OP_GREATER:
4880 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4881 case VK_COMPARE_OP_NOT_EQUAL:
4882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4883 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4884 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4885 case VK_COMPARE_OP_ALWAYS:
4886 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4887 default:
4888 unreachable("illegal compare mode");
4889 break;
4890 }
4891 }
4892
4893 static unsigned
4894 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4895 {
4896 switch (filter) {
4897 case VK_FILTER_NEAREST:
4898 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4899 V_008F38_SQ_TEX_XY_FILTER_POINT);
4900 case VK_FILTER_LINEAR:
4901 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4902 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4903 case VK_FILTER_CUBIC_IMG:
4904 default:
4905 fprintf(stderr, "illegal texture filter");
4906 return 0;
4907 }
4908 }
4909
4910 static unsigned
4911 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4912 {
4913 switch (mode) {
4914 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4915 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4916 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4917 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4918 default:
4919 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4920 }
4921 }
4922
4923 static unsigned
4924 radv_tex_bordercolor(VkBorderColor bcolor)
4925 {
4926 switch (bcolor) {
4927 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4928 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4929 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4930 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4931 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4932 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4933 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4934 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4935 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4936 default:
4937 break;
4938 }
4939 return 0;
4940 }
4941
4942 static unsigned
4943 radv_tex_aniso_filter(unsigned filter)
4944 {
4945 if (filter < 2)
4946 return 0;
4947 if (filter < 4)
4948 return 1;
4949 if (filter < 8)
4950 return 2;
4951 if (filter < 16)
4952 return 3;
4953 return 4;
4954 }
4955
4956 static unsigned
4957 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4958 {
4959 switch (mode) {
4960 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4961 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4962 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4963 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4964 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4965 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4966 default:
4967 break;
4968 }
4969 return 0;
4970 }
4971
4972 static uint32_t
4973 radv_get_max_anisotropy(struct radv_device *device,
4974 const VkSamplerCreateInfo *pCreateInfo)
4975 {
4976 if (device->force_aniso >= 0)
4977 return device->force_aniso;
4978
4979 if (pCreateInfo->anisotropyEnable &&
4980 pCreateInfo->maxAnisotropy > 1.0f)
4981 return (uint32_t)pCreateInfo->maxAnisotropy;
4982
4983 return 0;
4984 }
4985
4986 static void
4987 radv_init_sampler(struct radv_device *device,
4988 struct radv_sampler *sampler,
4989 const VkSamplerCreateInfo *pCreateInfo)
4990 {
4991 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4992 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4993 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4994 device->physical_device->rad_info.chip_class == GFX9;
4995 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4996
4997 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4998 vk_find_struct_const(pCreateInfo->pNext,
4999 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5000 if (sampler_reduction)
5001 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5002
5003 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5004 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5005 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5006 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5007 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5008 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5009 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5010 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5011 S_008F30_DISABLE_CUBE_WRAP(0) |
5012 S_008F30_COMPAT_MODE(compat_mode) |
5013 S_008F30_FILTER_MODE(filter_mode));
5014 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5015 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5016 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5017 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5018 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5019 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5020 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5021 S_008F38_MIP_POINT_PRECLAMP(0));
5022 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5023 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5024
5025 if (device->physical_device->rad_info.chip_class >= GFX10) {
5026 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5027 } else {
5028 sampler->state[2] |=
5029 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5030 S_008F38_FILTER_PREC_FIX(1) |
5031 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5032 }
5033 }
5034
5035 VkResult radv_CreateSampler(
5036 VkDevice _device,
5037 const VkSamplerCreateInfo* pCreateInfo,
5038 const VkAllocationCallbacks* pAllocator,
5039 VkSampler* pSampler)
5040 {
5041 RADV_FROM_HANDLE(radv_device, device, _device);
5042 struct radv_sampler *sampler;
5043
5044 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5045 vk_find_struct_const(pCreateInfo->pNext,
5046 SAMPLER_YCBCR_CONVERSION_INFO);
5047
5048 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5049
5050 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5051 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5052 if (!sampler)
5053 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5054
5055 radv_init_sampler(device, sampler, pCreateInfo);
5056
5057 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5058 *pSampler = radv_sampler_to_handle(sampler);
5059
5060 return VK_SUCCESS;
5061 }
5062
5063 void radv_DestroySampler(
5064 VkDevice _device,
5065 VkSampler _sampler,
5066 const VkAllocationCallbacks* pAllocator)
5067 {
5068 RADV_FROM_HANDLE(radv_device, device, _device);
5069 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5070
5071 if (!sampler)
5072 return;
5073 vk_free2(&device->alloc, pAllocator, sampler);
5074 }
5075
5076 /* vk_icd.h does not declare this function, so we declare it here to
5077 * suppress Wmissing-prototypes.
5078 */
5079 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5080 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5081
5082 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5083 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5084 {
5085 /* For the full details on loader interface versioning, see
5086 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5087 * What follows is a condensed summary, to help you navigate the large and
5088 * confusing official doc.
5089 *
5090 * - Loader interface v0 is incompatible with later versions. We don't
5091 * support it.
5092 *
5093 * - In loader interface v1:
5094 * - The first ICD entrypoint called by the loader is
5095 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5096 * entrypoint.
5097 * - The ICD must statically expose no other Vulkan symbol unless it is
5098 * linked with -Bsymbolic.
5099 * - Each dispatchable Vulkan handle created by the ICD must be
5100 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5101 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5102 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5103 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5104 * such loader-managed surfaces.
5105 *
5106 * - Loader interface v2 differs from v1 in:
5107 * - The first ICD entrypoint called by the loader is
5108 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5109 * statically expose this entrypoint.
5110 *
5111 * - Loader interface v3 differs from v2 in:
5112 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5113 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5114 * because the loader no longer does so.
5115 */
5116 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5117 return VK_SUCCESS;
5118 }
5119
5120 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5121 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5122 int *pFD)
5123 {
5124 RADV_FROM_HANDLE(radv_device, device, _device);
5125 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5126
5127 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5128
5129 /* At the moment, we support only the below handle types. */
5130 assert(pGetFdInfo->handleType ==
5131 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5132 pGetFdInfo->handleType ==
5133 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5134
5135 bool ret = radv_get_memory_fd(device, memory, pFD);
5136 if (ret == false)
5137 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5138 return VK_SUCCESS;
5139 }
5140
5141 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5142 VkExternalMemoryHandleTypeFlagBits handleType,
5143 int fd,
5144 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5145 {
5146 RADV_FROM_HANDLE(radv_device, device, _device);
5147
5148 switch (handleType) {
5149 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5150 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5151 return VK_SUCCESS;
5152
5153 default:
5154 /* The valid usage section for this function says:
5155 *
5156 * "handleType must not be one of the handle types defined as
5157 * opaque."
5158 *
5159 * So opaque handle types fall into the default "unsupported" case.
5160 */
5161 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5162 }
5163 }
5164
5165 static VkResult radv_import_opaque_fd(struct radv_device *device,
5166 int fd,
5167 uint32_t *syncobj)
5168 {
5169 uint32_t syncobj_handle = 0;
5170 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5171 if (ret != 0)
5172 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5173
5174 if (*syncobj)
5175 device->ws->destroy_syncobj(device->ws, *syncobj);
5176
5177 *syncobj = syncobj_handle;
5178 close(fd);
5179
5180 return VK_SUCCESS;
5181 }
5182
5183 static VkResult radv_import_sync_fd(struct radv_device *device,
5184 int fd,
5185 uint32_t *syncobj)
5186 {
5187 /* If we create a syncobj we do it locally so that if we have an error, we don't
5188 * leave a syncobj in an undetermined state in the fence. */
5189 uint32_t syncobj_handle = *syncobj;
5190 if (!syncobj_handle) {
5191 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5192 if (ret) {
5193 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5194 }
5195 }
5196
5197 if (fd == -1) {
5198 device->ws->signal_syncobj(device->ws, syncobj_handle);
5199 } else {
5200 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5201 if (ret != 0)
5202 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5203 }
5204
5205 *syncobj = syncobj_handle;
5206 if (fd != -1)
5207 close(fd);
5208
5209 return VK_SUCCESS;
5210 }
5211
5212 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5213 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5214 {
5215 RADV_FROM_HANDLE(radv_device, device, _device);
5216 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5217 uint32_t *syncobj_dst = NULL;
5218
5219 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5220 syncobj_dst = &sem->temp_syncobj;
5221 } else {
5222 syncobj_dst = &sem->syncobj;
5223 }
5224
5225 switch(pImportSemaphoreFdInfo->handleType) {
5226 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5227 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5228 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5229 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5230 default:
5231 unreachable("Unhandled semaphore handle type");
5232 }
5233 }
5234
5235 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5236 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5237 int *pFd)
5238 {
5239 RADV_FROM_HANDLE(radv_device, device, _device);
5240 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5241 int ret;
5242 uint32_t syncobj_handle;
5243
5244 if (sem->temp_syncobj)
5245 syncobj_handle = sem->temp_syncobj;
5246 else
5247 syncobj_handle = sem->syncobj;
5248
5249 switch(pGetFdInfo->handleType) {
5250 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5251 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5252 break;
5253 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5254 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5255 if (!ret) {
5256 if (sem->temp_syncobj) {
5257 close (sem->temp_syncobj);
5258 sem->temp_syncobj = 0;
5259 } else {
5260 device->ws->reset_syncobj(device->ws, syncobj_handle);
5261 }
5262 }
5263 break;
5264 default:
5265 unreachable("Unhandled semaphore handle type");
5266 }
5267
5268 if (ret)
5269 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5270 return VK_SUCCESS;
5271 }
5272
5273 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5274 VkPhysicalDevice physicalDevice,
5275 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5276 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5277 {
5278 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5279
5280 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5281 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5282 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5283 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5284 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5285 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5286 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5287 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5288 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5289 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5290 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5291 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5292 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5293 } else {
5294 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5295 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5296 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5297 }
5298 }
5299
5300 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5301 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5302 {
5303 RADV_FROM_HANDLE(radv_device, device, _device);
5304 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5305 uint32_t *syncobj_dst = NULL;
5306
5307
5308 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5309 syncobj_dst = &fence->temp_syncobj;
5310 } else {
5311 syncobj_dst = &fence->syncobj;
5312 }
5313
5314 switch(pImportFenceFdInfo->handleType) {
5315 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5316 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5317 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5318 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5319 default:
5320 unreachable("Unhandled fence handle type");
5321 }
5322 }
5323
5324 VkResult radv_GetFenceFdKHR(VkDevice _device,
5325 const VkFenceGetFdInfoKHR *pGetFdInfo,
5326 int *pFd)
5327 {
5328 RADV_FROM_HANDLE(radv_device, device, _device);
5329 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5330 int ret;
5331 uint32_t syncobj_handle;
5332
5333 if (fence->temp_syncobj)
5334 syncobj_handle = fence->temp_syncobj;
5335 else
5336 syncobj_handle = fence->syncobj;
5337
5338 switch(pGetFdInfo->handleType) {
5339 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5340 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5341 break;
5342 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5343 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5344 if (!ret) {
5345 if (fence->temp_syncobj) {
5346 close (fence->temp_syncobj);
5347 fence->temp_syncobj = 0;
5348 } else {
5349 device->ws->reset_syncobj(device->ws, syncobj_handle);
5350 }
5351 }
5352 break;
5353 default:
5354 unreachable("Unhandled fence handle type");
5355 }
5356
5357 if (ret)
5358 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5359 return VK_SUCCESS;
5360 }
5361
5362 void radv_GetPhysicalDeviceExternalFenceProperties(
5363 VkPhysicalDevice physicalDevice,
5364 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5365 VkExternalFenceProperties *pExternalFenceProperties)
5366 {
5367 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5368
5369 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5370 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5371 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5372 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5373 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5374 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5375 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5376 } else {
5377 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5378 pExternalFenceProperties->compatibleHandleTypes = 0;
5379 pExternalFenceProperties->externalFenceFeatures = 0;
5380 }
5381 }
5382
5383 VkResult
5384 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5385 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5386 const VkAllocationCallbacks* pAllocator,
5387 VkDebugReportCallbackEXT* pCallback)
5388 {
5389 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5390 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5391 pCreateInfo, pAllocator, &instance->alloc,
5392 pCallback);
5393 }
5394
5395 void
5396 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5397 VkDebugReportCallbackEXT _callback,
5398 const VkAllocationCallbacks* pAllocator)
5399 {
5400 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5401 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5402 _callback, pAllocator, &instance->alloc);
5403 }
5404
5405 void
5406 radv_DebugReportMessageEXT(VkInstance _instance,
5407 VkDebugReportFlagsEXT flags,
5408 VkDebugReportObjectTypeEXT objectType,
5409 uint64_t object,
5410 size_t location,
5411 int32_t messageCode,
5412 const char* pLayerPrefix,
5413 const char* pMessage)
5414 {
5415 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5416 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5417 object, location, messageCode, pLayerPrefix, pMessage);
5418 }
5419
5420 void
5421 radv_GetDeviceGroupPeerMemoryFeatures(
5422 VkDevice device,
5423 uint32_t heapIndex,
5424 uint32_t localDeviceIndex,
5425 uint32_t remoteDeviceIndex,
5426 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5427 {
5428 assert(localDeviceIndex == remoteDeviceIndex);
5429
5430 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5431 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5432 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5433 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5434 }
5435
5436 static const VkTimeDomainEXT radv_time_domains[] = {
5437 VK_TIME_DOMAIN_DEVICE_EXT,
5438 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5439 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5440 };
5441
5442 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5443 VkPhysicalDevice physicalDevice,
5444 uint32_t *pTimeDomainCount,
5445 VkTimeDomainEXT *pTimeDomains)
5446 {
5447 int d;
5448 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5449
5450 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5451 vk_outarray_append(&out, i) {
5452 *i = radv_time_domains[d];
5453 }
5454 }
5455
5456 return vk_outarray_status(&out);
5457 }
5458
5459 static uint64_t
5460 radv_clock_gettime(clockid_t clock_id)
5461 {
5462 struct timespec current;
5463 int ret;
5464
5465 ret = clock_gettime(clock_id, &current);
5466 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5467 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5468 if (ret < 0)
5469 return 0;
5470
5471 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5472 }
5473
5474 VkResult radv_GetCalibratedTimestampsEXT(
5475 VkDevice _device,
5476 uint32_t timestampCount,
5477 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5478 uint64_t *pTimestamps,
5479 uint64_t *pMaxDeviation)
5480 {
5481 RADV_FROM_HANDLE(radv_device, device, _device);
5482 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5483 int d;
5484 uint64_t begin, end;
5485 uint64_t max_clock_period = 0;
5486
5487 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5488
5489 for (d = 0; d < timestampCount; d++) {
5490 switch (pTimestampInfos[d].timeDomain) {
5491 case VK_TIME_DOMAIN_DEVICE_EXT:
5492 pTimestamps[d] = device->ws->query_value(device->ws,
5493 RADEON_TIMESTAMP);
5494 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5495 max_clock_period = MAX2(max_clock_period, device_period);
5496 break;
5497 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5498 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5499 max_clock_period = MAX2(max_clock_period, 1);
5500 break;
5501
5502 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5503 pTimestamps[d] = begin;
5504 break;
5505 default:
5506 pTimestamps[d] = 0;
5507 break;
5508 }
5509 }
5510
5511 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5512
5513 /*
5514 * The maximum deviation is the sum of the interval over which we
5515 * perform the sampling and the maximum period of any sampled
5516 * clock. That's because the maximum skew between any two sampled
5517 * clock edges is when the sampled clock with the largest period is
5518 * sampled at the end of that period but right at the beginning of the
5519 * sampling interval and some other clock is sampled right at the
5520 * begining of its sampling period and right at the end of the
5521 * sampling interval. Let's assume the GPU has the longest clock
5522 * period and that the application is sampling GPU and monotonic:
5523 *
5524 * s e
5525 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5526 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5527 *
5528 * g
5529 * 0 1 2 3
5530 * GPU -----_____-----_____-----_____-----_____
5531 *
5532 * m
5533 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5534 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5535 *
5536 * Interval <----------------->
5537 * Deviation <-------------------------->
5538 *
5539 * s = read(raw) 2
5540 * g = read(GPU) 1
5541 * m = read(monotonic) 2
5542 * e = read(raw) b
5543 *
5544 * We round the sample interval up by one tick to cover sampling error
5545 * in the interval clock
5546 */
5547
5548 uint64_t sample_interval = end - begin + 1;
5549
5550 *pMaxDeviation = sample_interval + max_clock_period;
5551
5552 return VK_SUCCESS;
5553 }
5554
5555 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5556 VkPhysicalDevice physicalDevice,
5557 VkSampleCountFlagBits samples,
5558 VkMultisamplePropertiesEXT* pMultisampleProperties)
5559 {
5560 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5561 VK_SAMPLE_COUNT_4_BIT |
5562 VK_SAMPLE_COUNT_8_BIT)) {
5563 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5564 } else {
5565 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5566 }
5567 }