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radv: force enable VK_AMD_shader_ballot for Wolfenstein Youngblood
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2 ||
352 device->rad_info.family == CHIP_RENOIR;
353 }
354
355 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
356 * on GFX6.
357 */
358 device->has_clear_state = device->rad_info.chip_class >= GFX7;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
367
368 /* Out-of-order primitive rasterization. */
369 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
370 device->rad_info.max_se >= 2;
371 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
372 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
373
374 device->dcc_msaa_allowed =
375 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
376
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
379 (device->rad_info.chip_class >= GFX8 &&
380 device->rad_info.me_fw_feature >= 41);
381
382 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
383 device->rad_info.family == CHIP_RENOIR ||
384 device->rad_info.chip_class >= GFX10;
385
386 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
387 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
388
389 /* Determine the number of threads per wave for all stages. */
390 device->cs_wave_size = 64;
391 device->ps_wave_size = 64;
392 device->ge_wave_size = 64;
393
394 if (device->rad_info.chip_class >= GFX10) {
395 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
396 device->cs_wave_size = 32;
397
398 /* For pixel shaders, wave64 is recommanded. */
399 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
400 device->ps_wave_size = 32;
401
402 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
403 device->ge_wave_size = 32;
404 }
405
406 radv_physical_device_init_mem_types(device);
407 radv_fill_device_extension_table(device, &device->supported_extensions);
408
409 device->bus_info = *drm_device->businfo.pci;
410
411 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
412 ac_print_gpu_info(&device->rad_info);
413
414 /* The WSI is structured as a layer on top of the driver, so this has
415 * to be the last part of initialization (at least until we get other
416 * semi-layers).
417 */
418 result = radv_init_wsi(device);
419 if (result != VK_SUCCESS) {
420 device->ws->destroy(device->ws);
421 vk_error(instance, result);
422 goto fail;
423 }
424
425 return VK_SUCCESS;
426
427 fail:
428 close(fd);
429 if (master_fd != -1)
430 close(master_fd);
431 return result;
432 }
433
434 static void
435 radv_physical_device_finish(struct radv_physical_device *device)
436 {
437 radv_finish_wsi(device);
438 device->ws->destroy(device->ws);
439 disk_cache_destroy(device->disk_cache);
440 close(device->local_fd);
441 if (device->master_fd != -1)
442 close(device->master_fd);
443 }
444
445 static void *
446 default_alloc_func(void *pUserData, size_t size, size_t align,
447 VkSystemAllocationScope allocationScope)
448 {
449 return malloc(size);
450 }
451
452 static void *
453 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
454 size_t align, VkSystemAllocationScope allocationScope)
455 {
456 return realloc(pOriginal, size);
457 }
458
459 static void
460 default_free_func(void *pUserData, void *pMemory)
461 {
462 free(pMemory);
463 }
464
465 static const VkAllocationCallbacks default_alloc = {
466 .pUserData = NULL,
467 .pfnAllocation = default_alloc_func,
468 .pfnReallocation = default_realloc_func,
469 .pfnFree = default_free_func,
470 };
471
472 static const struct debug_control radv_debug_options[] = {
473 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
474 {"nodcc", RADV_DEBUG_NO_DCC},
475 {"shaders", RADV_DEBUG_DUMP_SHADERS},
476 {"nocache", RADV_DEBUG_NO_CACHE},
477 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
478 {"nohiz", RADV_DEBUG_NO_HIZ},
479 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
480 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
481 {"allbos", RADV_DEBUG_ALL_BOS},
482 {"noibs", RADV_DEBUG_NO_IBS},
483 {"spirv", RADV_DEBUG_DUMP_SPIRV},
484 {"vmfaults", RADV_DEBUG_VM_FAULTS},
485 {"zerovram", RADV_DEBUG_ZERO_VRAM},
486 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
487 {"nosisched", RADV_DEBUG_NO_SISCHED},
488 {"preoptir", RADV_DEBUG_PREOPTIR},
489 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
490 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
491 {"info", RADV_DEBUG_INFO},
492 {"errors", RADV_DEBUG_ERRORS},
493 {"startup", RADV_DEBUG_STARTUP},
494 {"checkir", RADV_DEBUG_CHECKIR},
495 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
496 {"nobinning", RADV_DEBUG_NOBINNING},
497 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
498 {"nongg", RADV_DEBUG_NO_NGG},
499 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
500 {NULL, 0}
501 };
502
503 const char *
504 radv_get_debug_option_name(int id)
505 {
506 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
507 return radv_debug_options[id].string;
508 }
509
510 static const struct debug_control radv_perftest_options[] = {
511 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
512 {"sisched", RADV_PERFTEST_SISCHED},
513 {"localbos", RADV_PERFTEST_LOCAL_BOS},
514 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
515 {"bolist", RADV_PERFTEST_BO_LIST},
516 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
517 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
518 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
519 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
520 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
521 {NULL, 0}
522 };
523
524 const char *
525 radv_get_perftest_option_name(int id)
526 {
527 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
528 return radv_perftest_options[id].string;
529 }
530
531 static void
532 radv_handle_per_app_options(struct radv_instance *instance,
533 const VkApplicationInfo *info)
534 {
535 const char *name = info ? info->pApplicationName : NULL;
536
537 if (!name)
538 return;
539
540 if (!strcmp(name, "Talos - Linux - 32bit") ||
541 !strcmp(name, "Talos - Linux - 64bit")) {
542 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
543 /* Force enable LLVM sisched for Talos because it looks
544 * safe and it gives few more FPS.
545 */
546 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
547 }
548 } else if (!strcmp(name, "DOOM_VFR")) {
549 /* Work around a Doom VFR game bug */
550 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
551 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
552 /* Workaround for a WaW hazard when LLVM moves/merges
553 * load/store memory operations.
554 * See https://reviews.llvm.org/D61313
555 */
556 if (HAVE_LLVM < 0x900)
557 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
558 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
559 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
560 /* Force enable VK_AMD_shader_ballot because it looks
561 * safe and it gives a nice boost (+20% on Vega 56 at
562 * this time).
563 */
564 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
565 }
566 }
567 }
568
569 static int radv_get_instance_extension_index(const char *name)
570 {
571 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
572 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
573 return i;
574 }
575 return -1;
576 }
577
578 static const char radv_dri_options_xml[] =
579 DRI_CONF_BEGIN
580 DRI_CONF_SECTION_QUALITY
581 DRI_CONF_ADAPTIVE_SYNC("true")
582 DRI_CONF_SECTION_END
583 DRI_CONF_END;
584
585 static void radv_init_dri_options(struct radv_instance *instance)
586 {
587 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
588 driParseConfigFiles(&instance->dri_options,
589 &instance->available_dri_options,
590 0, "radv", NULL);
591 }
592
593 VkResult radv_CreateInstance(
594 const VkInstanceCreateInfo* pCreateInfo,
595 const VkAllocationCallbacks* pAllocator,
596 VkInstance* pInstance)
597 {
598 struct radv_instance *instance;
599 VkResult result;
600
601 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
602
603 uint32_t client_version;
604 if (pCreateInfo->pApplicationInfo &&
605 pCreateInfo->pApplicationInfo->apiVersion != 0) {
606 client_version = pCreateInfo->pApplicationInfo->apiVersion;
607 } else {
608 client_version = VK_API_VERSION_1_0;
609 }
610
611 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
612 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
613 if (!instance)
614 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
615
616 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
617
618 if (pAllocator)
619 instance->alloc = *pAllocator;
620 else
621 instance->alloc = default_alloc;
622
623 instance->apiVersion = client_version;
624 instance->physicalDeviceCount = -1;
625
626 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
627 radv_debug_options);
628
629 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
630 radv_perftest_options);
631
632
633 if (instance->debug_flags & RADV_DEBUG_STARTUP)
634 radv_logi("Created an instance");
635
636 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
637 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
638 int index = radv_get_instance_extension_index(ext_name);
639
640 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
641 vk_free2(&default_alloc, pAllocator, instance);
642 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
643 }
644
645 instance->enabled_extensions.extensions[index] = true;
646 }
647
648 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
649 if (result != VK_SUCCESS) {
650 vk_free2(&default_alloc, pAllocator, instance);
651 return vk_error(instance, result);
652 }
653
654 _mesa_locale_init();
655 glsl_type_singleton_init_or_ref();
656
657 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
658
659 radv_init_dri_options(instance);
660 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
661
662 *pInstance = radv_instance_to_handle(instance);
663
664 return VK_SUCCESS;
665 }
666
667 void radv_DestroyInstance(
668 VkInstance _instance,
669 const VkAllocationCallbacks* pAllocator)
670 {
671 RADV_FROM_HANDLE(radv_instance, instance, _instance);
672
673 if (!instance)
674 return;
675
676 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
677 radv_physical_device_finish(instance->physicalDevices + i);
678 }
679
680 VG(VALGRIND_DESTROY_MEMPOOL(instance));
681
682 glsl_type_singleton_decref();
683 _mesa_locale_fini();
684
685 driDestroyOptionCache(&instance->dri_options);
686 driDestroyOptionInfo(&instance->available_dri_options);
687
688 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
689
690 vk_free(&instance->alloc, instance);
691 }
692
693 static VkResult
694 radv_enumerate_devices(struct radv_instance *instance)
695 {
696 /* TODO: Check for more devices ? */
697 drmDevicePtr devices[8];
698 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
699 int max_devices;
700
701 instance->physicalDeviceCount = 0;
702
703 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
704
705 if (instance->debug_flags & RADV_DEBUG_STARTUP)
706 radv_logi("Found %d drm nodes", max_devices);
707
708 if (max_devices < 1)
709 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
710
711 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
712 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
713 devices[i]->bustype == DRM_BUS_PCI &&
714 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
715
716 result = radv_physical_device_init(instance->physicalDevices +
717 instance->physicalDeviceCount,
718 instance,
719 devices[i]);
720 if (result == VK_SUCCESS)
721 ++instance->physicalDeviceCount;
722 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
723 break;
724 }
725 }
726 drmFreeDevices(devices, max_devices);
727
728 return result;
729 }
730
731 VkResult radv_EnumeratePhysicalDevices(
732 VkInstance _instance,
733 uint32_t* pPhysicalDeviceCount,
734 VkPhysicalDevice* pPhysicalDevices)
735 {
736 RADV_FROM_HANDLE(radv_instance, instance, _instance);
737 VkResult result;
738
739 if (instance->physicalDeviceCount < 0) {
740 result = radv_enumerate_devices(instance);
741 if (result != VK_SUCCESS &&
742 result != VK_ERROR_INCOMPATIBLE_DRIVER)
743 return result;
744 }
745
746 if (!pPhysicalDevices) {
747 *pPhysicalDeviceCount = instance->physicalDeviceCount;
748 } else {
749 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
750 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
751 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
752 }
753
754 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
755 : VK_SUCCESS;
756 }
757
758 VkResult radv_EnumeratePhysicalDeviceGroups(
759 VkInstance _instance,
760 uint32_t* pPhysicalDeviceGroupCount,
761 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
762 {
763 RADV_FROM_HANDLE(radv_instance, instance, _instance);
764 VkResult result;
765
766 if (instance->physicalDeviceCount < 0) {
767 result = radv_enumerate_devices(instance);
768 if (result != VK_SUCCESS &&
769 result != VK_ERROR_INCOMPATIBLE_DRIVER)
770 return result;
771 }
772
773 if (!pPhysicalDeviceGroupProperties) {
774 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
775 } else {
776 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
777 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
778 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
779 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
780 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
781 }
782 }
783 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
784 : VK_SUCCESS;
785 }
786
787 void radv_GetPhysicalDeviceFeatures(
788 VkPhysicalDevice physicalDevice,
789 VkPhysicalDeviceFeatures* pFeatures)
790 {
791 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
792 memset(pFeatures, 0, sizeof(*pFeatures));
793
794 *pFeatures = (VkPhysicalDeviceFeatures) {
795 .robustBufferAccess = true,
796 .fullDrawIndexUint32 = true,
797 .imageCubeArray = true,
798 .independentBlend = true,
799 .geometryShader = true,
800 .tessellationShader = true,
801 .sampleRateShading = true,
802 .dualSrcBlend = true,
803 .logicOp = true,
804 .multiDrawIndirect = true,
805 .drawIndirectFirstInstance = true,
806 .depthClamp = true,
807 .depthBiasClamp = true,
808 .fillModeNonSolid = true,
809 .depthBounds = true,
810 .wideLines = true,
811 .largePoints = true,
812 .alphaToOne = true,
813 .multiViewport = true,
814 .samplerAnisotropy = true,
815 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
816 .textureCompressionASTC_LDR = false,
817 .textureCompressionBC = true,
818 .occlusionQueryPrecise = true,
819 .pipelineStatisticsQuery = true,
820 .vertexPipelineStoresAndAtomics = true,
821 .fragmentStoresAndAtomics = true,
822 .shaderTessellationAndGeometryPointSize = true,
823 .shaderImageGatherExtended = true,
824 .shaderStorageImageExtendedFormats = true,
825 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
826 .shaderUniformBufferArrayDynamicIndexing = true,
827 .shaderSampledImageArrayDynamicIndexing = true,
828 .shaderStorageBufferArrayDynamicIndexing = true,
829 .shaderStorageImageArrayDynamicIndexing = true,
830 .shaderStorageImageReadWithoutFormat = true,
831 .shaderStorageImageWriteWithoutFormat = true,
832 .shaderClipDistance = true,
833 .shaderCullDistance = true,
834 .shaderFloat64 = true,
835 .shaderInt64 = true,
836 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
837 .sparseBinding = true,
838 .variableMultisampleRate = true,
839 .inheritedQueries = true,
840 };
841 }
842
843 void radv_GetPhysicalDeviceFeatures2(
844 VkPhysicalDevice physicalDevice,
845 VkPhysicalDeviceFeatures2 *pFeatures)
846 {
847 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
848 vk_foreach_struct(ext, pFeatures->pNext) {
849 switch (ext->sType) {
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
851 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
852 features->variablePointersStorageBuffer = true;
853 features->variablePointers = true;
854 break;
855 }
856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
857 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
858 features->multiview = true;
859 features->multiviewGeometryShader = true;
860 features->multiviewTessellationShader = true;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
864 VkPhysicalDeviceShaderDrawParametersFeatures *features =
865 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
866 features->shaderDrawParameters = true;
867 break;
868 }
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
870 VkPhysicalDeviceProtectedMemoryFeatures *features =
871 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
872 features->protectedMemory = false;
873 break;
874 }
875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
876 VkPhysicalDevice16BitStorageFeatures *features =
877 (VkPhysicalDevice16BitStorageFeatures*)ext;
878 bool enabled = pdevice->rad_info.chip_class >= GFX8;
879 features->storageBuffer16BitAccess = enabled;
880 features->uniformAndStorageBuffer16BitAccess = enabled;
881 features->storagePushConstant16 = enabled;
882 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
883 break;
884 }
885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
886 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
887 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
888 features->samplerYcbcrConversion = true;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
892 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
893 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
894 features->shaderInputAttachmentArrayDynamicIndexing = true;
895 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
896 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
897 features->shaderUniformBufferArrayNonUniformIndexing = true;
898 features->shaderSampledImageArrayNonUniformIndexing = true;
899 features->shaderStorageBufferArrayNonUniformIndexing = true;
900 features->shaderStorageImageArrayNonUniformIndexing = true;
901 features->shaderInputAttachmentArrayNonUniformIndexing = true;
902 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
903 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
904 features->descriptorBindingUniformBufferUpdateAfterBind = true;
905 features->descriptorBindingSampledImageUpdateAfterBind = true;
906 features->descriptorBindingStorageImageUpdateAfterBind = true;
907 features->descriptorBindingStorageBufferUpdateAfterBind = true;
908 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
909 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
910 features->descriptorBindingUpdateUnusedWhilePending = true;
911 features->descriptorBindingPartiallyBound = true;
912 features->descriptorBindingVariableDescriptorCount = true;
913 features->runtimeDescriptorArray = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
917 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
918 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
919 features->conditionalRendering = true;
920 features->inheritedConditionalRendering = false;
921 break;
922 }
923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
924 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
925 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
926 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
927 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
928 break;
929 }
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
931 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
932 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
933 features->transformFeedback = true;
934 features->geometryStreams = true;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
938 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
939 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
940 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
941 break;
942 }
943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
944 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
945 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
946 features->memoryPriority = VK_TRUE;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
950 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
951 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
952 features->bufferDeviceAddress = true;
953 features->bufferDeviceAddressCaptureReplay = false;
954 features->bufferDeviceAddressMultiDevice = false;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
958 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
959 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
960 features->depthClipEnable = true;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
964 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
965 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
966 features->hostQueryReset = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
970 VkPhysicalDevice8BitStorageFeaturesKHR *features =
971 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
972 bool enabled = pdevice->rad_info.chip_class >= GFX8;
973 features->storageBuffer8BitAccess = enabled;
974 features->uniformAndStorageBuffer8BitAccess = enabled;
975 features->storagePushConstant8 = enabled;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
979 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
980 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
981 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
982 features->shaderInt8 = true;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
986 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
987 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
988 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
989 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
993 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
994 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
995
996 features->inlineUniformBlock = true;
997 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
998 break;
999 }
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1001 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1002 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1003 features->computeDerivativeGroupQuads = false;
1004 features->computeDerivativeGroupLinear = true;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1008 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1009 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1010 features->ycbcrImageArrays = true;
1011 break;
1012 }
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1014 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1015 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1016 features->uniformBufferStandardLayout = true;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1020 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1021 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1022 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1023 break;
1024 }
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1026 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1027 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1028 features->imagelessFramebuffer = true;
1029 break;
1030 }
1031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1032 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1033 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1034 features->pipelineExecutableInfo = true;
1035 break;
1036 }
1037 default:
1038 break;
1039 }
1040 }
1041 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1042 }
1043
1044 void radv_GetPhysicalDeviceProperties(
1045 VkPhysicalDevice physicalDevice,
1046 VkPhysicalDeviceProperties* pProperties)
1047 {
1048 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1049 VkSampleCountFlags sample_counts = 0xf;
1050
1051 /* make sure that the entire descriptor set is addressable with a signed
1052 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1053 * be at most 2 GiB. the combined image & samples object count as one of
1054 * both. This limit is for the pipeline layout, not for the set layout, but
1055 * there is no set limit, so we just set a pipeline limit. I don't think
1056 * any app is going to hit this soon. */
1057 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1058 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1059 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1060 32 /* sampler, largest when combined with image */ +
1061 64 /* sampled image */ +
1062 64 /* storage image */);
1063
1064 VkPhysicalDeviceLimits limits = {
1065 .maxImageDimension1D = (1 << 14),
1066 .maxImageDimension2D = (1 << 14),
1067 .maxImageDimension3D = (1 << 11),
1068 .maxImageDimensionCube = (1 << 14),
1069 .maxImageArrayLayers = (1 << 11),
1070 .maxTexelBufferElements = 128 * 1024 * 1024,
1071 .maxUniformBufferRange = UINT32_MAX,
1072 .maxStorageBufferRange = UINT32_MAX,
1073 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1074 .maxMemoryAllocationCount = UINT32_MAX,
1075 .maxSamplerAllocationCount = 64 * 1024,
1076 .bufferImageGranularity = 64, /* A cache line */
1077 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1078 .maxBoundDescriptorSets = MAX_SETS,
1079 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1080 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1081 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1082 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1083 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1084 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1085 .maxPerStageResources = max_descriptor_set_size,
1086 .maxDescriptorSetSamplers = max_descriptor_set_size,
1087 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1088 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1089 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1090 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1091 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1092 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1093 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1094 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1095 .maxVertexInputBindings = MAX_VBS,
1096 .maxVertexInputAttributeOffset = 2047,
1097 .maxVertexInputBindingStride = 2048,
1098 .maxVertexOutputComponents = 128,
1099 .maxTessellationGenerationLevel = 64,
1100 .maxTessellationPatchSize = 32,
1101 .maxTessellationControlPerVertexInputComponents = 128,
1102 .maxTessellationControlPerVertexOutputComponents = 128,
1103 .maxTessellationControlPerPatchOutputComponents = 120,
1104 .maxTessellationControlTotalOutputComponents = 4096,
1105 .maxTessellationEvaluationInputComponents = 128,
1106 .maxTessellationEvaluationOutputComponents = 128,
1107 .maxGeometryShaderInvocations = 127,
1108 .maxGeometryInputComponents = 64,
1109 .maxGeometryOutputComponents = 128,
1110 .maxGeometryOutputVertices = 256,
1111 .maxGeometryTotalOutputComponents = 1024,
1112 .maxFragmentInputComponents = 128,
1113 .maxFragmentOutputAttachments = 8,
1114 .maxFragmentDualSrcAttachments = 1,
1115 .maxFragmentCombinedOutputResources = 8,
1116 .maxComputeSharedMemorySize = 32768,
1117 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1118 .maxComputeWorkGroupInvocations = 2048,
1119 .maxComputeWorkGroupSize = {
1120 2048,
1121 2048,
1122 2048
1123 },
1124 .subPixelPrecisionBits = 8,
1125 .subTexelPrecisionBits = 8,
1126 .mipmapPrecisionBits = 8,
1127 .maxDrawIndexedIndexValue = UINT32_MAX,
1128 .maxDrawIndirectCount = UINT32_MAX,
1129 .maxSamplerLodBias = 16,
1130 .maxSamplerAnisotropy = 16,
1131 .maxViewports = MAX_VIEWPORTS,
1132 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1133 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1134 .viewportSubPixelBits = 8,
1135 .minMemoryMapAlignment = 4096, /* A page */
1136 .minTexelBufferOffsetAlignment = 1,
1137 .minUniformBufferOffsetAlignment = 4,
1138 .minStorageBufferOffsetAlignment = 4,
1139 .minTexelOffset = -32,
1140 .maxTexelOffset = 31,
1141 .minTexelGatherOffset = -32,
1142 .maxTexelGatherOffset = 31,
1143 .minInterpolationOffset = -2,
1144 .maxInterpolationOffset = 2,
1145 .subPixelInterpolationOffsetBits = 8,
1146 .maxFramebufferWidth = (1 << 14),
1147 .maxFramebufferHeight = (1 << 14),
1148 .maxFramebufferLayers = (1 << 10),
1149 .framebufferColorSampleCounts = sample_counts,
1150 .framebufferDepthSampleCounts = sample_counts,
1151 .framebufferStencilSampleCounts = sample_counts,
1152 .framebufferNoAttachmentsSampleCounts = sample_counts,
1153 .maxColorAttachments = MAX_RTS,
1154 .sampledImageColorSampleCounts = sample_counts,
1155 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1156 .sampledImageDepthSampleCounts = sample_counts,
1157 .sampledImageStencilSampleCounts = sample_counts,
1158 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1159 .maxSampleMaskWords = 1,
1160 .timestampComputeAndGraphics = true,
1161 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1162 .maxClipDistances = 8,
1163 .maxCullDistances = 8,
1164 .maxCombinedClipAndCullDistances = 8,
1165 .discreteQueuePriorities = 2,
1166 .pointSizeRange = { 0.0, 8192.0 },
1167 .lineWidthRange = { 0.0, 7.9921875 },
1168 .pointSizeGranularity = (1.0 / 8.0),
1169 .lineWidthGranularity = (1.0 / 128.0),
1170 .strictLines = false, /* FINISHME */
1171 .standardSampleLocations = true,
1172 .optimalBufferCopyOffsetAlignment = 128,
1173 .optimalBufferCopyRowPitchAlignment = 128,
1174 .nonCoherentAtomSize = 64,
1175 };
1176
1177 *pProperties = (VkPhysicalDeviceProperties) {
1178 .apiVersion = radv_physical_device_api_version(pdevice),
1179 .driverVersion = vk_get_driver_version(),
1180 .vendorID = ATI_VENDOR_ID,
1181 .deviceID = pdevice->rad_info.pci_id,
1182 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1183 .limits = limits,
1184 .sparseProperties = {0},
1185 };
1186
1187 strcpy(pProperties->deviceName, pdevice->name);
1188 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1189 }
1190
1191 void radv_GetPhysicalDeviceProperties2(
1192 VkPhysicalDevice physicalDevice,
1193 VkPhysicalDeviceProperties2 *pProperties)
1194 {
1195 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1196 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1197
1198 vk_foreach_struct(ext, pProperties->pNext) {
1199 switch (ext->sType) {
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1201 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1202 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1203 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1204 break;
1205 }
1206 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1207 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1208 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1209 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1210 properties->deviceLUIDValid = false;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1214 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1215 properties->maxMultiviewViewCount = MAX_VIEWS;
1216 properties->maxMultiviewInstanceIndex = INT_MAX;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1220 VkPhysicalDevicePointClippingProperties *properties =
1221 (VkPhysicalDevicePointClippingProperties*)ext;
1222 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1226 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1227 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1228 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1232 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1233 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1234 properties->minImportedHostPointerAlignment = 4096;
1235 break;
1236 }
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1238 VkPhysicalDeviceSubgroupProperties *properties =
1239 (VkPhysicalDeviceSubgroupProperties*)ext;
1240 properties->subgroupSize = 64;
1241 properties->supportedStages = VK_SHADER_STAGE_ALL;
1242 properties->supportedOperations =
1243 VK_SUBGROUP_FEATURE_BASIC_BIT |
1244 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1245 VK_SUBGROUP_FEATURE_QUAD_BIT |
1246 VK_SUBGROUP_FEATURE_VOTE_BIT;
1247 if (pdevice->rad_info.chip_class >= GFX8) {
1248 properties->supportedOperations |=
1249 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1250 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1251 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1252 }
1253 properties->quadOperationsInAllStages = true;
1254 break;
1255 }
1256 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1257 VkPhysicalDeviceMaintenance3Properties *properties =
1258 (VkPhysicalDeviceMaintenance3Properties*)ext;
1259 /* Make sure everything is addressable by a signed 32-bit int, and
1260 * our largest descriptors are 96 bytes. */
1261 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1262 /* Our buffer size fields allow only this much */
1263 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1264 break;
1265 }
1266 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1267 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1268 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1269 /* GFX6-8 only support single channel min/max filter. */
1270 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1271 properties->filterMinmaxSingleComponentFormats = true;
1272 break;
1273 }
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1275 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1276 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1277
1278 /* Shader engines. */
1279 properties->shaderEngineCount =
1280 pdevice->rad_info.max_se;
1281 properties->shaderArraysPerEngineCount =
1282 pdevice->rad_info.max_sh_per_se;
1283 properties->computeUnitsPerShaderArray =
1284 pdevice->rad_info.num_good_cu_per_sh;
1285 properties->simdPerComputeUnit = 4;
1286 properties->wavefrontsPerSimd =
1287 pdevice->rad_info.family == CHIP_TONGA ||
1288 pdevice->rad_info.family == CHIP_ICELAND ||
1289 pdevice->rad_info.family == CHIP_POLARIS10 ||
1290 pdevice->rad_info.family == CHIP_POLARIS11 ||
1291 pdevice->rad_info.family == CHIP_POLARIS12 ||
1292 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1293 properties->wavefrontSize = 64;
1294
1295 /* SGPR. */
1296 properties->sgprsPerSimd =
1297 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1298 properties->minSgprAllocation =
1299 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1300 properties->maxSgprAllocation =
1301 pdevice->rad_info.family == CHIP_TONGA ||
1302 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1303 properties->sgprAllocationGranularity =
1304 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1305
1306 /* VGPR. */
1307 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1308 properties->minVgprAllocation = 4;
1309 properties->maxVgprAllocation = 256;
1310 properties->vgprAllocationGranularity = 4;
1311 break;
1312 }
1313 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1314 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1315 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1316 properties->maxVertexAttribDivisor = UINT32_MAX;
1317 break;
1318 }
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1320 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1321 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1322 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1323 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1324 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1325 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1326 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1327 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1328 properties->robustBufferAccessUpdateAfterBind = false;
1329 properties->quadDivergentImplicitLod = false;
1330
1331 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1332 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1333 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1334 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1335 32 /* sampler, largest when combined with image */ +
1336 64 /* sampled image */ +
1337 64 /* storage image */);
1338 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1339 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1340 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1341 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1342 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1343 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1344 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1345 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1346 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1347 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1348 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1349 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1350 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1351 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1352 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1353 break;
1354 }
1355 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1356 VkPhysicalDeviceProtectedMemoryProperties *properties =
1357 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1358 properties->protectedNoFault = false;
1359 break;
1360 }
1361 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1362 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1363 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1364 properties->primitiveOverestimationSize = 0;
1365 properties->maxExtraPrimitiveOverestimationSize = 0;
1366 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1367 properties->primitiveUnderestimation = VK_FALSE;
1368 properties->conservativePointAndLineRasterization = VK_FALSE;
1369 properties->degenerateTrianglesRasterized = VK_FALSE;
1370 properties->degenerateLinesRasterized = VK_FALSE;
1371 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1372 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1373 break;
1374 }
1375 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1376 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1377 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1378 properties->pciDomain = pdevice->bus_info.domain;
1379 properties->pciBus = pdevice->bus_info.bus;
1380 properties->pciDevice = pdevice->bus_info.dev;
1381 properties->pciFunction = pdevice->bus_info.func;
1382 break;
1383 }
1384 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1385 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1386 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1387
1388 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1389 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1390 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1391 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1392 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1393
1394 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1395 .major = 1,
1396 .minor = 1,
1397 .subminor = 2,
1398 .patch = 0,
1399 };
1400 break;
1401 }
1402 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1403 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1404 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1405 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1406 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1407 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1408 properties->maxTransformFeedbackStreamDataSize = 512;
1409 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1410 properties->maxTransformFeedbackBufferDataStride = 512;
1411 properties->transformFeedbackQueries = true;
1412 properties->transformFeedbackStreamsLinesTriangles = true;
1413 properties->transformFeedbackRasterizationStreamSelect = false;
1414 properties->transformFeedbackDraw = true;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1418 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1419 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1420
1421 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1422 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1423 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1424 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1425 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1426 break;
1427 }
1428 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1429 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1430 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1431 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1432 VK_SAMPLE_COUNT_4_BIT |
1433 VK_SAMPLE_COUNT_8_BIT;
1434 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1435 properties->sampleLocationCoordinateRange[0] = 0.0f;
1436 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1437 properties->sampleLocationSubPixelBits = 4;
1438 properties->variableSampleLocations = VK_FALSE;
1439 break;
1440 }
1441 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1442 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1443 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1444
1445 /* We support all of the depth resolve modes */
1446 properties->supportedDepthResolveModes =
1447 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1448 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1449 VK_RESOLVE_MODE_MIN_BIT_KHR |
1450 VK_RESOLVE_MODE_MAX_BIT_KHR;
1451
1452 /* Average doesn't make sense for stencil so we don't support that */
1453 properties->supportedStencilResolveModes =
1454 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1455 VK_RESOLVE_MODE_MIN_BIT_KHR |
1456 VK_RESOLVE_MODE_MAX_BIT_KHR;
1457
1458 properties->independentResolveNone = VK_TRUE;
1459 properties->independentResolve = VK_TRUE;
1460 break;
1461 }
1462 default:
1463 break;
1464 }
1465 }
1466 }
1467
1468 static void radv_get_physical_device_queue_family_properties(
1469 struct radv_physical_device* pdevice,
1470 uint32_t* pCount,
1471 VkQueueFamilyProperties** pQueueFamilyProperties)
1472 {
1473 int num_queue_families = 1;
1474 int idx;
1475 if (pdevice->rad_info.num_compute_rings > 0 &&
1476 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1477 num_queue_families++;
1478
1479 if (pQueueFamilyProperties == NULL) {
1480 *pCount = num_queue_families;
1481 return;
1482 }
1483
1484 if (!*pCount)
1485 return;
1486
1487 idx = 0;
1488 if (*pCount >= 1) {
1489 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1490 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1491 VK_QUEUE_COMPUTE_BIT |
1492 VK_QUEUE_TRANSFER_BIT |
1493 VK_QUEUE_SPARSE_BINDING_BIT,
1494 .queueCount = 1,
1495 .timestampValidBits = 64,
1496 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1497 };
1498 idx++;
1499 }
1500
1501 if (pdevice->rad_info.num_compute_rings > 0 &&
1502 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1503 if (*pCount > idx) {
1504 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1505 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1506 VK_QUEUE_TRANSFER_BIT |
1507 VK_QUEUE_SPARSE_BINDING_BIT,
1508 .queueCount = pdevice->rad_info.num_compute_rings,
1509 .timestampValidBits = 64,
1510 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1511 };
1512 idx++;
1513 }
1514 }
1515 *pCount = idx;
1516 }
1517
1518 void radv_GetPhysicalDeviceQueueFamilyProperties(
1519 VkPhysicalDevice physicalDevice,
1520 uint32_t* pCount,
1521 VkQueueFamilyProperties* pQueueFamilyProperties)
1522 {
1523 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1524 if (!pQueueFamilyProperties) {
1525 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1526 return;
1527 }
1528 VkQueueFamilyProperties *properties[] = {
1529 pQueueFamilyProperties + 0,
1530 pQueueFamilyProperties + 1,
1531 pQueueFamilyProperties + 2,
1532 };
1533 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1534 assert(*pCount <= 3);
1535 }
1536
1537 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1538 VkPhysicalDevice physicalDevice,
1539 uint32_t* pCount,
1540 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1541 {
1542 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1543 if (!pQueueFamilyProperties) {
1544 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1545 return;
1546 }
1547 VkQueueFamilyProperties *properties[] = {
1548 &pQueueFamilyProperties[0].queueFamilyProperties,
1549 &pQueueFamilyProperties[1].queueFamilyProperties,
1550 &pQueueFamilyProperties[2].queueFamilyProperties,
1551 };
1552 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1553 assert(*pCount <= 3);
1554 }
1555
1556 void radv_GetPhysicalDeviceMemoryProperties(
1557 VkPhysicalDevice physicalDevice,
1558 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1559 {
1560 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1561
1562 *pMemoryProperties = physical_device->memory_properties;
1563 }
1564
1565 static void
1566 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1567 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1568 {
1569 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1570 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1571 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1572 uint64_t vram_size = radv_get_vram_size(device);
1573 uint64_t gtt_size = device->rad_info.gart_size;
1574 uint64_t heap_budget, heap_usage;
1575
1576 /* For all memory heaps, the computation of budget is as follow:
1577 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1578 *
1579 * The Vulkan spec 1.1.97 says that the budget should include any
1580 * currently allocated device memory.
1581 *
1582 * Note that the application heap usages are not really accurate (eg.
1583 * in presence of shared buffers).
1584 */
1585 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1586 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1587
1588 switch (device->mem_type_indices[i]) {
1589 case RADV_MEM_TYPE_VRAM:
1590 heap_usage = device->ws->query_value(device->ws,
1591 RADEON_ALLOCATED_VRAM);
1592
1593 heap_budget = vram_size -
1594 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1595 heap_usage;
1596
1597 memoryBudget->heapBudget[heap_index] = heap_budget;
1598 memoryBudget->heapUsage[heap_index] = heap_usage;
1599 break;
1600 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1601 heap_usage = device->ws->query_value(device->ws,
1602 RADEON_ALLOCATED_VRAM_VIS);
1603
1604 heap_budget = visible_vram_size -
1605 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1606 heap_usage;
1607
1608 memoryBudget->heapBudget[heap_index] = heap_budget;
1609 memoryBudget->heapUsage[heap_index] = heap_usage;
1610 break;
1611 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1612 heap_usage = device->ws->query_value(device->ws,
1613 RADEON_ALLOCATED_GTT);
1614
1615 heap_budget = gtt_size -
1616 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1617 heap_usage;
1618
1619 memoryBudget->heapBudget[heap_index] = heap_budget;
1620 memoryBudget->heapUsage[heap_index] = heap_usage;
1621 break;
1622 default:
1623 break;
1624 }
1625 }
1626
1627 /* The heapBudget and heapUsage values must be zero for array elements
1628 * greater than or equal to
1629 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1630 */
1631 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1632 memoryBudget->heapBudget[i] = 0;
1633 memoryBudget->heapUsage[i] = 0;
1634 }
1635 }
1636
1637 void radv_GetPhysicalDeviceMemoryProperties2(
1638 VkPhysicalDevice physicalDevice,
1639 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1640 {
1641 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1642 &pMemoryProperties->memoryProperties);
1643
1644 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1645 vk_find_struct(pMemoryProperties->pNext,
1646 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1647 if (memory_budget)
1648 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1649 }
1650
1651 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1652 VkDevice _device,
1653 VkExternalMemoryHandleTypeFlagBits handleType,
1654 const void *pHostPointer,
1655 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1656 {
1657 RADV_FROM_HANDLE(radv_device, device, _device);
1658
1659 switch (handleType)
1660 {
1661 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1662 const struct radv_physical_device *physical_device = device->physical_device;
1663 uint32_t memoryTypeBits = 0;
1664 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1665 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1666 memoryTypeBits = (1 << i);
1667 break;
1668 }
1669 }
1670 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1671 return VK_SUCCESS;
1672 }
1673 default:
1674 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1675 }
1676 }
1677
1678 static enum radeon_ctx_priority
1679 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1680 {
1681 /* Default to MEDIUM when a specific global priority isn't requested */
1682 if (!pObj)
1683 return RADEON_CTX_PRIORITY_MEDIUM;
1684
1685 switch(pObj->globalPriority) {
1686 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1687 return RADEON_CTX_PRIORITY_REALTIME;
1688 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1689 return RADEON_CTX_PRIORITY_HIGH;
1690 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1691 return RADEON_CTX_PRIORITY_MEDIUM;
1692 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1693 return RADEON_CTX_PRIORITY_LOW;
1694 default:
1695 unreachable("Illegal global priority value");
1696 return RADEON_CTX_PRIORITY_INVALID;
1697 }
1698 }
1699
1700 static int
1701 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1702 uint32_t queue_family_index, int idx,
1703 VkDeviceQueueCreateFlags flags,
1704 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1705 {
1706 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1707 queue->device = device;
1708 queue->queue_family_index = queue_family_index;
1709 queue->queue_idx = idx;
1710 queue->priority = radv_get_queue_global_priority(global_priority);
1711 queue->flags = flags;
1712
1713 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1714 if (!queue->hw_ctx)
1715 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1716
1717 return VK_SUCCESS;
1718 }
1719
1720 static void
1721 radv_queue_finish(struct radv_queue *queue)
1722 {
1723 if (queue->hw_ctx)
1724 queue->device->ws->ctx_destroy(queue->hw_ctx);
1725
1726 if (queue->initial_full_flush_preamble_cs)
1727 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1728 if (queue->initial_preamble_cs)
1729 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1730 if (queue->continue_preamble_cs)
1731 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1732 if (queue->descriptor_bo)
1733 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1734 if (queue->scratch_bo)
1735 queue->device->ws->buffer_destroy(queue->scratch_bo);
1736 if (queue->esgs_ring_bo)
1737 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1738 if (queue->gsvs_ring_bo)
1739 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1740 if (queue->tess_rings_bo)
1741 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1742 if (queue->compute_scratch_bo)
1743 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1744 }
1745
1746 static void
1747 radv_bo_list_init(struct radv_bo_list *bo_list)
1748 {
1749 pthread_mutex_init(&bo_list->mutex, NULL);
1750 bo_list->list.count = bo_list->capacity = 0;
1751 bo_list->list.bos = NULL;
1752 }
1753
1754 static void
1755 radv_bo_list_finish(struct radv_bo_list *bo_list)
1756 {
1757 free(bo_list->list.bos);
1758 pthread_mutex_destroy(&bo_list->mutex);
1759 }
1760
1761 static VkResult radv_bo_list_add(struct radv_device *device,
1762 struct radeon_winsys_bo *bo)
1763 {
1764 struct radv_bo_list *bo_list = &device->bo_list;
1765
1766 if (bo->is_local)
1767 return VK_SUCCESS;
1768
1769 if (unlikely(!device->use_global_bo_list))
1770 return VK_SUCCESS;
1771
1772 pthread_mutex_lock(&bo_list->mutex);
1773 if (bo_list->list.count == bo_list->capacity) {
1774 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1775 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1776
1777 if (!data) {
1778 pthread_mutex_unlock(&bo_list->mutex);
1779 return VK_ERROR_OUT_OF_HOST_MEMORY;
1780 }
1781
1782 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1783 bo_list->capacity = capacity;
1784 }
1785
1786 bo_list->list.bos[bo_list->list.count++] = bo;
1787 pthread_mutex_unlock(&bo_list->mutex);
1788 return VK_SUCCESS;
1789 }
1790
1791 static void radv_bo_list_remove(struct radv_device *device,
1792 struct radeon_winsys_bo *bo)
1793 {
1794 struct radv_bo_list *bo_list = &device->bo_list;
1795
1796 if (bo->is_local)
1797 return;
1798
1799 if (unlikely(!device->use_global_bo_list))
1800 return;
1801
1802 pthread_mutex_lock(&bo_list->mutex);
1803 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1804 if (bo_list->list.bos[i] == bo) {
1805 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1806 --bo_list->list.count;
1807 break;
1808 }
1809 }
1810 pthread_mutex_unlock(&bo_list->mutex);
1811 }
1812
1813 static void
1814 radv_device_init_gs_info(struct radv_device *device)
1815 {
1816 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1817 device->physical_device->rad_info.family);
1818 }
1819
1820 static int radv_get_device_extension_index(const char *name)
1821 {
1822 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1823 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1824 return i;
1825 }
1826 return -1;
1827 }
1828
1829 static int
1830 radv_get_int_debug_option(const char *name, int default_value)
1831 {
1832 const char *str;
1833 int result;
1834
1835 str = getenv(name);
1836 if (!str) {
1837 result = default_value;
1838 } else {
1839 char *endptr;
1840
1841 result = strtol(str, &endptr, 0);
1842 if (str == endptr) {
1843 /* No digits founs. */
1844 result = default_value;
1845 }
1846 }
1847
1848 return result;
1849 }
1850
1851 VkResult radv_CreateDevice(
1852 VkPhysicalDevice physicalDevice,
1853 const VkDeviceCreateInfo* pCreateInfo,
1854 const VkAllocationCallbacks* pAllocator,
1855 VkDevice* pDevice)
1856 {
1857 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1858 VkResult result;
1859 struct radv_device *device;
1860
1861 bool keep_shader_info = false;
1862
1863 /* Check enabled features */
1864 if (pCreateInfo->pEnabledFeatures) {
1865 VkPhysicalDeviceFeatures supported_features;
1866 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1867 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1868 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1869 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1870 for (uint32_t i = 0; i < num_features; i++) {
1871 if (enabled_feature[i] && !supported_feature[i])
1872 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1873 }
1874 }
1875
1876 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1877 sizeof(*device), 8,
1878 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1879 if (!device)
1880 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1881
1882 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1883 device->instance = physical_device->instance;
1884 device->physical_device = physical_device;
1885
1886 device->ws = physical_device->ws;
1887 if (pAllocator)
1888 device->alloc = *pAllocator;
1889 else
1890 device->alloc = physical_device->instance->alloc;
1891
1892 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1893 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1894 int index = radv_get_device_extension_index(ext_name);
1895 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1896 vk_free(&device->alloc, device);
1897 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1898 }
1899
1900 device->enabled_extensions.extensions[index] = true;
1901 }
1902
1903 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1904
1905 /* With update after bind we can't attach bo's to the command buffer
1906 * from the descriptor set anymore, so we have to use a global BO list.
1907 */
1908 device->use_global_bo_list =
1909 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1910 device->enabled_extensions.EXT_descriptor_indexing ||
1911 device->enabled_extensions.EXT_buffer_device_address;
1912
1913 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1914 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1915
1916 mtx_init(&device->shader_slab_mutex, mtx_plain);
1917 list_inithead(&device->shader_slabs);
1918
1919 radv_bo_list_init(&device->bo_list);
1920
1921 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1922 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1923 uint32_t qfi = queue_create->queueFamilyIndex;
1924 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1925 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1926
1927 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1928
1929 device->queues[qfi] = vk_alloc(&device->alloc,
1930 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1931 if (!device->queues[qfi]) {
1932 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1933 goto fail;
1934 }
1935
1936 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1937
1938 device->queue_count[qfi] = queue_create->queueCount;
1939
1940 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1941 result = radv_queue_init(device, &device->queues[qfi][q],
1942 qfi, q, queue_create->flags,
1943 global_priority);
1944 if (result != VK_SUCCESS)
1945 goto fail;
1946 }
1947 }
1948
1949 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1950 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1951
1952 device->dfsm_allowed = device->pbb_allowed &&
1953 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1954 device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1955 device->physical_device->rad_info.family == CHIP_RENOIR);
1956
1957 #ifdef ANDROID
1958 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1959 #endif
1960
1961 /* The maximum number of scratch waves. Scratch space isn't divided
1962 * evenly between CUs. The number is only a function of the number of CUs.
1963 * We can decrease the constant to decrease the scratch buffer size.
1964 *
1965 * sctx->scratch_waves must be >= the maximum possible size of
1966 * 1 threadgroup, so that the hw doesn't hang from being unable
1967 * to start any.
1968 *
1969 * The recommended value is 4 per CU at most. Higher numbers don't
1970 * bring much benefit, but they still occupy chip resources (think
1971 * async compute). I've seen ~2% performance difference between 4 and 32.
1972 */
1973 uint32_t max_threads_per_block = 2048;
1974 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1975 max_threads_per_block / 64);
1976
1977 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1978 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1979
1980 if (device->physical_device->rad_info.chip_class >= GFX7) {
1981 /* If the KMD allows it (there is a KMD hw register for it),
1982 * allow launching waves out-of-order.
1983 */
1984 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1985 }
1986
1987 radv_device_init_gs_info(device);
1988
1989 device->tess_offchip_block_dw_size =
1990 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1991 device->has_distributed_tess =
1992 device->physical_device->rad_info.chip_class >= GFX8 &&
1993 device->physical_device->rad_info.max_se >= 2;
1994
1995 if (getenv("RADV_TRACE_FILE")) {
1996 const char *filename = getenv("RADV_TRACE_FILE");
1997
1998 keep_shader_info = true;
1999
2000 if (!radv_init_trace(device))
2001 goto fail;
2002
2003 fprintf(stderr, "*****************************************************************************\n");
2004 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2005 fprintf(stderr, "*****************************************************************************\n");
2006
2007 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2008 radv_dump_enabled_options(device, stderr);
2009 }
2010
2011 device->keep_shader_info = keep_shader_info;
2012
2013 result = radv_device_init_meta(device);
2014 if (result != VK_SUCCESS)
2015 goto fail;
2016
2017 radv_device_init_msaa(device);
2018
2019 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2020 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2021 switch (family) {
2022 case RADV_QUEUE_GENERAL:
2023 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2024 if (device->physical_device->rad_info.drm_minor < 6) {
2025 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2026 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2027 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2028 }
2029 break;
2030 case RADV_QUEUE_COMPUTE:
2031 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2032 radeon_emit(device->empty_cs[family], 0);
2033 break;
2034 }
2035 device->ws->cs_finalize(device->empty_cs[family]);
2036 }
2037
2038 if (device->physical_device->rad_info.chip_class >= GFX7)
2039 cik_create_gfx_config(device);
2040
2041 VkPipelineCacheCreateInfo ci;
2042 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2043 ci.pNext = NULL;
2044 ci.flags = 0;
2045 ci.pInitialData = NULL;
2046 ci.initialDataSize = 0;
2047 VkPipelineCache pc;
2048 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2049 &ci, NULL, &pc);
2050 if (result != VK_SUCCESS)
2051 goto fail_meta;
2052
2053 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2054
2055 device->force_aniso =
2056 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2057 if (device->force_aniso >= 0) {
2058 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2059 1 << util_logbase2(device->force_aniso));
2060 }
2061
2062 *pDevice = radv_device_to_handle(device);
2063 return VK_SUCCESS;
2064
2065 fail_meta:
2066 radv_device_finish_meta(device);
2067 fail:
2068 radv_bo_list_finish(&device->bo_list);
2069
2070 if (device->trace_bo)
2071 device->ws->buffer_destroy(device->trace_bo);
2072
2073 if (device->gfx_init)
2074 device->ws->buffer_destroy(device->gfx_init);
2075
2076 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2077 for (unsigned q = 0; q < device->queue_count[i]; q++)
2078 radv_queue_finish(&device->queues[i][q]);
2079 if (device->queue_count[i])
2080 vk_free(&device->alloc, device->queues[i]);
2081 }
2082
2083 vk_free(&device->alloc, device);
2084 return result;
2085 }
2086
2087 void radv_DestroyDevice(
2088 VkDevice _device,
2089 const VkAllocationCallbacks* pAllocator)
2090 {
2091 RADV_FROM_HANDLE(radv_device, device, _device);
2092
2093 if (!device)
2094 return;
2095
2096 if (device->trace_bo)
2097 device->ws->buffer_destroy(device->trace_bo);
2098
2099 if (device->gfx_init)
2100 device->ws->buffer_destroy(device->gfx_init);
2101
2102 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2103 for (unsigned q = 0; q < device->queue_count[i]; q++)
2104 radv_queue_finish(&device->queues[i][q]);
2105 if (device->queue_count[i])
2106 vk_free(&device->alloc, device->queues[i]);
2107 if (device->empty_cs[i])
2108 device->ws->cs_destroy(device->empty_cs[i]);
2109 }
2110 radv_device_finish_meta(device);
2111
2112 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2113 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2114
2115 radv_destroy_shader_slabs(device);
2116
2117 radv_bo_list_finish(&device->bo_list);
2118 vk_free(&device->alloc, device);
2119 }
2120
2121 VkResult radv_EnumerateInstanceLayerProperties(
2122 uint32_t* pPropertyCount,
2123 VkLayerProperties* pProperties)
2124 {
2125 if (pProperties == NULL) {
2126 *pPropertyCount = 0;
2127 return VK_SUCCESS;
2128 }
2129
2130 /* None supported at this time */
2131 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2132 }
2133
2134 VkResult radv_EnumerateDeviceLayerProperties(
2135 VkPhysicalDevice physicalDevice,
2136 uint32_t* pPropertyCount,
2137 VkLayerProperties* pProperties)
2138 {
2139 if (pProperties == NULL) {
2140 *pPropertyCount = 0;
2141 return VK_SUCCESS;
2142 }
2143
2144 /* None supported at this time */
2145 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2146 }
2147
2148 void radv_GetDeviceQueue2(
2149 VkDevice _device,
2150 const VkDeviceQueueInfo2* pQueueInfo,
2151 VkQueue* pQueue)
2152 {
2153 RADV_FROM_HANDLE(radv_device, device, _device);
2154 struct radv_queue *queue;
2155
2156 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2157 if (pQueueInfo->flags != queue->flags) {
2158 /* From the Vulkan 1.1.70 spec:
2159 *
2160 * "The queue returned by vkGetDeviceQueue2 must have the same
2161 * flags value from this structure as that used at device
2162 * creation time in a VkDeviceQueueCreateInfo instance. If no
2163 * matching flags were specified at device creation time then
2164 * pQueue will return VK_NULL_HANDLE."
2165 */
2166 *pQueue = VK_NULL_HANDLE;
2167 return;
2168 }
2169
2170 *pQueue = radv_queue_to_handle(queue);
2171 }
2172
2173 void radv_GetDeviceQueue(
2174 VkDevice _device,
2175 uint32_t queueFamilyIndex,
2176 uint32_t queueIndex,
2177 VkQueue* pQueue)
2178 {
2179 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2180 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2181 .queueFamilyIndex = queueFamilyIndex,
2182 .queueIndex = queueIndex
2183 };
2184
2185 radv_GetDeviceQueue2(_device, &info, pQueue);
2186 }
2187
2188 static void
2189 fill_geom_tess_rings(struct radv_queue *queue,
2190 uint32_t *map,
2191 bool add_sample_positions,
2192 uint32_t esgs_ring_size,
2193 struct radeon_winsys_bo *esgs_ring_bo,
2194 uint32_t gsvs_ring_size,
2195 struct radeon_winsys_bo *gsvs_ring_bo,
2196 uint32_t tess_factor_ring_size,
2197 uint32_t tess_offchip_ring_offset,
2198 uint32_t tess_offchip_ring_size,
2199 struct radeon_winsys_bo *tess_rings_bo)
2200 {
2201 uint32_t *desc = &map[4];
2202
2203 if (esgs_ring_bo) {
2204 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2205
2206 /* stride 0, num records - size, add tid, swizzle, elsize4,
2207 index stride 64 */
2208 desc[0] = esgs_va;
2209 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2210 S_008F04_SWIZZLE_ENABLE(true);
2211 desc[2] = esgs_ring_size;
2212 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2213 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2214 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2215 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2216 S_008F0C_INDEX_STRIDE(3) |
2217 S_008F0C_ADD_TID_ENABLE(1);
2218
2219 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2220 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2221 S_008F0C_OOB_SELECT(2) |
2222 S_008F0C_RESOURCE_LEVEL(1);
2223 } else {
2224 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2225 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2226 S_008F0C_ELEMENT_SIZE(1);
2227 }
2228
2229 /* GS entry for ES->GS ring */
2230 /* stride 0, num records - size, elsize0,
2231 index stride 0 */
2232 desc[4] = esgs_va;
2233 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2234 desc[6] = esgs_ring_size;
2235 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2236 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2237 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2238 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2239
2240 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2241 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2242 S_008F0C_OOB_SELECT(2) |
2243 S_008F0C_RESOURCE_LEVEL(1);
2244 } else {
2245 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2246 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2247 }
2248 }
2249
2250 desc += 8;
2251
2252 if (gsvs_ring_bo) {
2253 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2254
2255 /* VS entry for GS->VS ring */
2256 /* stride 0, num records - size, elsize0,
2257 index stride 0 */
2258 desc[0] = gsvs_va;
2259 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2260 desc[2] = gsvs_ring_size;
2261 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2262 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2263 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2264 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2265
2266 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2267 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2268 S_008F0C_OOB_SELECT(2) |
2269 S_008F0C_RESOURCE_LEVEL(1);
2270 } else {
2271 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2272 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2273 }
2274
2275 /* stride gsvs_itemsize, num records 64
2276 elsize 4, index stride 16 */
2277 /* shader will patch stride and desc[2] */
2278 desc[4] = gsvs_va;
2279 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2280 S_008F04_SWIZZLE_ENABLE(1);
2281 desc[6] = 0;
2282 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2283 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2284 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2285 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2286 S_008F0C_INDEX_STRIDE(1) |
2287 S_008F0C_ADD_TID_ENABLE(true);
2288
2289 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2290 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2291 S_008F0C_OOB_SELECT(2) |
2292 S_008F0C_RESOURCE_LEVEL(1);
2293 } else {
2294 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2295 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2296 S_008F0C_ELEMENT_SIZE(1);
2297 }
2298
2299 }
2300
2301 desc += 8;
2302
2303 if (tess_rings_bo) {
2304 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2305 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2306
2307 desc[0] = tess_va;
2308 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2309 desc[2] = tess_factor_ring_size;
2310 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2311 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2312 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2313 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2314
2315 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2316 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2317 S_008F0C_OOB_SELECT(3) |
2318 S_008F0C_RESOURCE_LEVEL(1);
2319 } else {
2320 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2321 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2322 }
2323
2324 desc[4] = tess_offchip_va;
2325 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2326 desc[6] = tess_offchip_ring_size;
2327 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2328 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2329 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2330 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2331
2332 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2333 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2334 S_008F0C_OOB_SELECT(3) |
2335 S_008F0C_RESOURCE_LEVEL(1);
2336 } else {
2337 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2338 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2339 }
2340 }
2341
2342 desc += 8;
2343
2344 if (add_sample_positions) {
2345 /* add sample positions after all rings */
2346 memcpy(desc, queue->device->sample_locations_1x, 8);
2347 desc += 2;
2348 memcpy(desc, queue->device->sample_locations_2x, 16);
2349 desc += 4;
2350 memcpy(desc, queue->device->sample_locations_4x, 32);
2351 desc += 8;
2352 memcpy(desc, queue->device->sample_locations_8x, 64);
2353 }
2354 }
2355
2356 static unsigned
2357 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2358 {
2359 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2360 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2361 device->physical_device->rad_info.family != CHIP_STONEY;
2362 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2363 unsigned max_offchip_buffers;
2364 unsigned offchip_granularity;
2365 unsigned hs_offchip_param;
2366
2367 /*
2368 * Per RadeonSI:
2369 * This must be one less than the maximum number due to a hw limitation.
2370 * Various hardware bugs need thGFX7
2371 *
2372 * Per AMDVLK:
2373 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2374 * Gfx7 should limit max_offchip_buffers to 508
2375 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2376 *
2377 * Follow AMDVLK here.
2378 */
2379 if (device->physical_device->rad_info.chip_class >= GFX10) {
2380 max_offchip_buffers_per_se = 256;
2381 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2382 device->physical_device->rad_info.chip_class == GFX7 ||
2383 device->physical_device->rad_info.chip_class == GFX6)
2384 --max_offchip_buffers_per_se;
2385
2386 max_offchip_buffers = max_offchip_buffers_per_se *
2387 device->physical_device->rad_info.max_se;
2388
2389 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2390 * around by setting 4K granularity.
2391 */
2392 if (device->tess_offchip_block_dw_size == 4096) {
2393 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2394 offchip_granularity = V_03093C_X_4K_DWORDS;
2395 } else {
2396 assert(device->tess_offchip_block_dw_size == 8192);
2397 offchip_granularity = V_03093C_X_8K_DWORDS;
2398 }
2399
2400 switch (device->physical_device->rad_info.chip_class) {
2401 case GFX6:
2402 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2403 break;
2404 case GFX7:
2405 case GFX8:
2406 case GFX9:
2407 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2408 break;
2409 case GFX10:
2410 break;
2411 default:
2412 break;
2413 }
2414
2415 *max_offchip_buffers_p = max_offchip_buffers;
2416 if (device->physical_device->rad_info.chip_class >= GFX7) {
2417 if (device->physical_device->rad_info.chip_class >= GFX8)
2418 --max_offchip_buffers;
2419 hs_offchip_param =
2420 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2421 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2422 } else {
2423 hs_offchip_param =
2424 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2425 }
2426 return hs_offchip_param;
2427 }
2428
2429 static void
2430 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2431 struct radeon_winsys_bo *esgs_ring_bo,
2432 uint32_t esgs_ring_size,
2433 struct radeon_winsys_bo *gsvs_ring_bo,
2434 uint32_t gsvs_ring_size)
2435 {
2436 if (!esgs_ring_bo && !gsvs_ring_bo)
2437 return;
2438
2439 if (esgs_ring_bo)
2440 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2441
2442 if (gsvs_ring_bo)
2443 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2444
2445 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2446 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2447 radeon_emit(cs, esgs_ring_size >> 8);
2448 radeon_emit(cs, gsvs_ring_size >> 8);
2449 } else {
2450 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2451 radeon_emit(cs, esgs_ring_size >> 8);
2452 radeon_emit(cs, gsvs_ring_size >> 8);
2453 }
2454 }
2455
2456 static void
2457 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2458 unsigned hs_offchip_param, unsigned tf_ring_size,
2459 struct radeon_winsys_bo *tess_rings_bo)
2460 {
2461 uint64_t tf_va;
2462
2463 if (!tess_rings_bo)
2464 return;
2465
2466 tf_va = radv_buffer_get_va(tess_rings_bo);
2467
2468 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2469
2470 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2471 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2472 S_030938_SIZE(tf_ring_size / 4));
2473 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2474 tf_va >> 8);
2475
2476 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2477 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2478 S_030984_BASE_HI(tf_va >> 40));
2479 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2480 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2481 S_030944_BASE_HI(tf_va >> 40));
2482 }
2483 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2484 hs_offchip_param);
2485 } else {
2486 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2487 S_008988_SIZE(tf_ring_size / 4));
2488 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2489 tf_va >> 8);
2490 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2491 hs_offchip_param);
2492 }
2493 }
2494
2495 static void
2496 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2497 struct radeon_winsys_bo *compute_scratch_bo)
2498 {
2499 uint64_t scratch_va;
2500
2501 if (!compute_scratch_bo)
2502 return;
2503
2504 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2505
2506 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2507
2508 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2509 radeon_emit(cs, scratch_va);
2510 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2511 S_008F04_SWIZZLE_ENABLE(1));
2512 }
2513
2514 static void
2515 radv_emit_global_shader_pointers(struct radv_queue *queue,
2516 struct radeon_cmdbuf *cs,
2517 struct radeon_winsys_bo *descriptor_bo)
2518 {
2519 uint64_t va;
2520
2521 if (!descriptor_bo)
2522 return;
2523
2524 va = radv_buffer_get_va(descriptor_bo);
2525
2526 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2527
2528 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2529 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2530 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2531 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2532 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2533
2534 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2535 radv_emit_shader_pointer(queue->device, cs, regs[i],
2536 va, true);
2537 }
2538 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2539 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2540 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2541 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2542 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2543
2544 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2545 radv_emit_shader_pointer(queue->device, cs, regs[i],
2546 va, true);
2547 }
2548 } else {
2549 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2550 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2551 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2552 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2553 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2554 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2555
2556 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2557 radv_emit_shader_pointer(queue->device, cs, regs[i],
2558 va, true);
2559 }
2560 }
2561 }
2562
2563 static void
2564 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2565 {
2566 struct radv_device *device = queue->device;
2567
2568 if (device->gfx_init) {
2569 uint64_t va = radv_buffer_get_va(device->gfx_init);
2570
2571 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2572 radeon_emit(cs, va);
2573 radeon_emit(cs, va >> 32);
2574 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2575
2576 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2577 } else {
2578 struct radv_physical_device *physical_device = device->physical_device;
2579 si_emit_graphics(physical_device, cs);
2580 }
2581 }
2582
2583 static void
2584 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2585 {
2586 struct radv_physical_device *physical_device = queue->device->physical_device;
2587 si_emit_compute(physical_device, cs);
2588 }
2589
2590 static VkResult
2591 radv_get_preamble_cs(struct radv_queue *queue,
2592 uint32_t scratch_size,
2593 uint32_t compute_scratch_size,
2594 uint32_t esgs_ring_size,
2595 uint32_t gsvs_ring_size,
2596 bool needs_tess_rings,
2597 bool needs_sample_positions,
2598 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2599 struct radeon_cmdbuf **initial_preamble_cs,
2600 struct radeon_cmdbuf **continue_preamble_cs)
2601 {
2602 struct radeon_winsys_bo *scratch_bo = NULL;
2603 struct radeon_winsys_bo *descriptor_bo = NULL;
2604 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2605 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2606 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2607 struct radeon_winsys_bo *tess_rings_bo = NULL;
2608 struct radeon_cmdbuf *dest_cs[3] = {0};
2609 bool add_tess_rings = false, add_sample_positions = false;
2610 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2611 unsigned max_offchip_buffers;
2612 unsigned hs_offchip_param = 0;
2613 unsigned tess_offchip_ring_offset;
2614 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2615 if (!queue->has_tess_rings) {
2616 if (needs_tess_rings)
2617 add_tess_rings = true;
2618 }
2619 if (!queue->has_sample_positions) {
2620 if (needs_sample_positions)
2621 add_sample_positions = true;
2622 }
2623 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2624 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2625 &max_offchip_buffers);
2626 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2627 tess_offchip_ring_size = max_offchip_buffers *
2628 queue->device->tess_offchip_block_dw_size * 4;
2629
2630 if (scratch_size <= queue->scratch_size &&
2631 compute_scratch_size <= queue->compute_scratch_size &&
2632 esgs_ring_size <= queue->esgs_ring_size &&
2633 gsvs_ring_size <= queue->gsvs_ring_size &&
2634 !add_tess_rings && !add_sample_positions &&
2635 queue->initial_preamble_cs) {
2636 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2637 *initial_preamble_cs = queue->initial_preamble_cs;
2638 *continue_preamble_cs = queue->continue_preamble_cs;
2639 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2640 *continue_preamble_cs = NULL;
2641 return VK_SUCCESS;
2642 }
2643
2644 if (scratch_size > queue->scratch_size) {
2645 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2646 scratch_size,
2647 4096,
2648 RADEON_DOMAIN_VRAM,
2649 ring_bo_flags,
2650 RADV_BO_PRIORITY_SCRATCH);
2651 if (!scratch_bo)
2652 goto fail;
2653 } else
2654 scratch_bo = queue->scratch_bo;
2655
2656 if (compute_scratch_size > queue->compute_scratch_size) {
2657 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2658 compute_scratch_size,
2659 4096,
2660 RADEON_DOMAIN_VRAM,
2661 ring_bo_flags,
2662 RADV_BO_PRIORITY_SCRATCH);
2663 if (!compute_scratch_bo)
2664 goto fail;
2665
2666 } else
2667 compute_scratch_bo = queue->compute_scratch_bo;
2668
2669 if (esgs_ring_size > queue->esgs_ring_size) {
2670 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2671 esgs_ring_size,
2672 4096,
2673 RADEON_DOMAIN_VRAM,
2674 ring_bo_flags,
2675 RADV_BO_PRIORITY_SCRATCH);
2676 if (!esgs_ring_bo)
2677 goto fail;
2678 } else {
2679 esgs_ring_bo = queue->esgs_ring_bo;
2680 esgs_ring_size = queue->esgs_ring_size;
2681 }
2682
2683 if (gsvs_ring_size > queue->gsvs_ring_size) {
2684 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2685 gsvs_ring_size,
2686 4096,
2687 RADEON_DOMAIN_VRAM,
2688 ring_bo_flags,
2689 RADV_BO_PRIORITY_SCRATCH);
2690 if (!gsvs_ring_bo)
2691 goto fail;
2692 } else {
2693 gsvs_ring_bo = queue->gsvs_ring_bo;
2694 gsvs_ring_size = queue->gsvs_ring_size;
2695 }
2696
2697 if (add_tess_rings) {
2698 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2699 tess_offchip_ring_offset + tess_offchip_ring_size,
2700 256,
2701 RADEON_DOMAIN_VRAM,
2702 ring_bo_flags,
2703 RADV_BO_PRIORITY_SCRATCH);
2704 if (!tess_rings_bo)
2705 goto fail;
2706 } else {
2707 tess_rings_bo = queue->tess_rings_bo;
2708 }
2709
2710 if (scratch_bo != queue->scratch_bo ||
2711 esgs_ring_bo != queue->esgs_ring_bo ||
2712 gsvs_ring_bo != queue->gsvs_ring_bo ||
2713 tess_rings_bo != queue->tess_rings_bo ||
2714 add_sample_positions) {
2715 uint32_t size = 0;
2716 if (gsvs_ring_bo || esgs_ring_bo ||
2717 tess_rings_bo || add_sample_positions) {
2718 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2719 if (add_sample_positions)
2720 size += 128; /* 64+32+16+8 = 120 bytes */
2721 }
2722 else if (scratch_bo)
2723 size = 8; /* 2 dword */
2724
2725 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2726 size,
2727 4096,
2728 RADEON_DOMAIN_VRAM,
2729 RADEON_FLAG_CPU_ACCESS |
2730 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2731 RADEON_FLAG_READ_ONLY,
2732 RADV_BO_PRIORITY_DESCRIPTOR);
2733 if (!descriptor_bo)
2734 goto fail;
2735 } else
2736 descriptor_bo = queue->descriptor_bo;
2737
2738 if (descriptor_bo != queue->descriptor_bo) {
2739 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2740
2741 if (scratch_bo) {
2742 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2743 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2744 S_008F04_SWIZZLE_ENABLE(1);
2745 map[0] = scratch_va;
2746 map[1] = rsrc1;
2747 }
2748
2749 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2750 fill_geom_tess_rings(queue, map, add_sample_positions,
2751 esgs_ring_size, esgs_ring_bo,
2752 gsvs_ring_size, gsvs_ring_bo,
2753 tess_factor_ring_size,
2754 tess_offchip_ring_offset,
2755 tess_offchip_ring_size,
2756 tess_rings_bo);
2757
2758 queue->device->ws->buffer_unmap(descriptor_bo);
2759 }
2760
2761 for(int i = 0; i < 3; ++i) {
2762 struct radeon_cmdbuf *cs = NULL;
2763 cs = queue->device->ws->cs_create(queue->device->ws,
2764 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2765 if (!cs)
2766 goto fail;
2767
2768 dest_cs[i] = cs;
2769
2770 if (scratch_bo)
2771 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2772
2773 /* Emit initial configuration. */
2774 switch (queue->queue_family_index) {
2775 case RADV_QUEUE_GENERAL:
2776 radv_init_graphics_state(cs, queue);
2777 break;
2778 case RADV_QUEUE_COMPUTE:
2779 radv_init_compute_state(cs, queue);
2780 break;
2781 case RADV_QUEUE_TRANSFER:
2782 break;
2783 }
2784
2785 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2786 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2787 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2788
2789 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2790 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2791 }
2792
2793 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2794 gsvs_ring_bo, gsvs_ring_size);
2795 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2796 tess_factor_ring_size, tess_rings_bo);
2797 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2798 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2799
2800 if (i == 0) {
2801 si_cs_emit_cache_flush(cs,
2802 queue->device->physical_device->rad_info.chip_class,
2803 NULL, 0,
2804 queue->queue_family_index == RING_COMPUTE &&
2805 queue->device->physical_device->rad_info.chip_class >= GFX7,
2806 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2807 RADV_CMD_FLAG_INV_ICACHE |
2808 RADV_CMD_FLAG_INV_SCACHE |
2809 RADV_CMD_FLAG_INV_VCACHE |
2810 RADV_CMD_FLAG_INV_L2 |
2811 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2812 } else if (i == 1) {
2813 si_cs_emit_cache_flush(cs,
2814 queue->device->physical_device->rad_info.chip_class,
2815 NULL, 0,
2816 queue->queue_family_index == RING_COMPUTE &&
2817 queue->device->physical_device->rad_info.chip_class >= GFX7,
2818 RADV_CMD_FLAG_INV_ICACHE |
2819 RADV_CMD_FLAG_INV_SCACHE |
2820 RADV_CMD_FLAG_INV_VCACHE |
2821 RADV_CMD_FLAG_INV_L2 |
2822 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2823 }
2824
2825 if (!queue->device->ws->cs_finalize(cs))
2826 goto fail;
2827 }
2828
2829 if (queue->initial_full_flush_preamble_cs)
2830 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2831
2832 if (queue->initial_preamble_cs)
2833 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2834
2835 if (queue->continue_preamble_cs)
2836 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2837
2838 queue->initial_full_flush_preamble_cs = dest_cs[0];
2839 queue->initial_preamble_cs = dest_cs[1];
2840 queue->continue_preamble_cs = dest_cs[2];
2841
2842 if (scratch_bo != queue->scratch_bo) {
2843 if (queue->scratch_bo)
2844 queue->device->ws->buffer_destroy(queue->scratch_bo);
2845 queue->scratch_bo = scratch_bo;
2846 queue->scratch_size = scratch_size;
2847 }
2848
2849 if (compute_scratch_bo != queue->compute_scratch_bo) {
2850 if (queue->compute_scratch_bo)
2851 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2852 queue->compute_scratch_bo = compute_scratch_bo;
2853 queue->compute_scratch_size = compute_scratch_size;
2854 }
2855
2856 if (esgs_ring_bo != queue->esgs_ring_bo) {
2857 if (queue->esgs_ring_bo)
2858 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2859 queue->esgs_ring_bo = esgs_ring_bo;
2860 queue->esgs_ring_size = esgs_ring_size;
2861 }
2862
2863 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2864 if (queue->gsvs_ring_bo)
2865 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2866 queue->gsvs_ring_bo = gsvs_ring_bo;
2867 queue->gsvs_ring_size = gsvs_ring_size;
2868 }
2869
2870 if (tess_rings_bo != queue->tess_rings_bo) {
2871 queue->tess_rings_bo = tess_rings_bo;
2872 queue->has_tess_rings = true;
2873 }
2874
2875 if (descriptor_bo != queue->descriptor_bo) {
2876 if (queue->descriptor_bo)
2877 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2878
2879 queue->descriptor_bo = descriptor_bo;
2880 }
2881
2882 if (add_sample_positions)
2883 queue->has_sample_positions = true;
2884
2885 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2886 *initial_preamble_cs = queue->initial_preamble_cs;
2887 *continue_preamble_cs = queue->continue_preamble_cs;
2888 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2889 *continue_preamble_cs = NULL;
2890 return VK_SUCCESS;
2891 fail:
2892 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2893 if (dest_cs[i])
2894 queue->device->ws->cs_destroy(dest_cs[i]);
2895 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2896 queue->device->ws->buffer_destroy(descriptor_bo);
2897 if (scratch_bo && scratch_bo != queue->scratch_bo)
2898 queue->device->ws->buffer_destroy(scratch_bo);
2899 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2900 queue->device->ws->buffer_destroy(compute_scratch_bo);
2901 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2902 queue->device->ws->buffer_destroy(esgs_ring_bo);
2903 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2904 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2905 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2906 queue->device->ws->buffer_destroy(tess_rings_bo);
2907 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2908 }
2909
2910 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2911 struct radv_winsys_sem_counts *counts,
2912 int num_sems,
2913 const VkSemaphore *sems,
2914 VkFence _fence,
2915 bool reset_temp)
2916 {
2917 int syncobj_idx = 0, sem_idx = 0;
2918
2919 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2920 return VK_SUCCESS;
2921
2922 for (uint32_t i = 0; i < num_sems; i++) {
2923 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2924
2925 if (sem->temp_syncobj || sem->syncobj)
2926 counts->syncobj_count++;
2927 else
2928 counts->sem_count++;
2929 }
2930
2931 if (_fence != VK_NULL_HANDLE) {
2932 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2933 if (fence->temp_syncobj || fence->syncobj)
2934 counts->syncobj_count++;
2935 }
2936
2937 if (counts->syncobj_count) {
2938 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2939 if (!counts->syncobj)
2940 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2941 }
2942
2943 if (counts->sem_count) {
2944 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2945 if (!counts->sem) {
2946 free(counts->syncobj);
2947 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2948 }
2949 }
2950
2951 for (uint32_t i = 0; i < num_sems; i++) {
2952 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2953
2954 if (sem->temp_syncobj) {
2955 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2956 }
2957 else if (sem->syncobj)
2958 counts->syncobj[syncobj_idx++] = sem->syncobj;
2959 else {
2960 assert(sem->sem);
2961 counts->sem[sem_idx++] = sem->sem;
2962 }
2963 }
2964
2965 if (_fence != VK_NULL_HANDLE) {
2966 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2967 if (fence->temp_syncobj)
2968 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2969 else if (fence->syncobj)
2970 counts->syncobj[syncobj_idx++] = fence->syncobj;
2971 }
2972
2973 return VK_SUCCESS;
2974 }
2975
2976 static void
2977 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2978 {
2979 free(sem_info->wait.syncobj);
2980 free(sem_info->wait.sem);
2981 free(sem_info->signal.syncobj);
2982 free(sem_info->signal.sem);
2983 }
2984
2985
2986 static void radv_free_temp_syncobjs(struct radv_device *device,
2987 int num_sems,
2988 const VkSemaphore *sems)
2989 {
2990 for (uint32_t i = 0; i < num_sems; i++) {
2991 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2992
2993 if (sem->temp_syncobj) {
2994 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2995 sem->temp_syncobj = 0;
2996 }
2997 }
2998 }
2999
3000 static VkResult
3001 radv_alloc_sem_info(struct radv_instance *instance,
3002 struct radv_winsys_sem_info *sem_info,
3003 int num_wait_sems,
3004 const VkSemaphore *wait_sems,
3005 int num_signal_sems,
3006 const VkSemaphore *signal_sems,
3007 VkFence fence)
3008 {
3009 VkResult ret;
3010 memset(sem_info, 0, sizeof(*sem_info));
3011
3012 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3013 if (ret)
3014 return ret;
3015 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3016 if (ret)
3017 radv_free_sem_info(sem_info);
3018
3019 /* caller can override these */
3020 sem_info->cs_emit_wait = true;
3021 sem_info->cs_emit_signal = true;
3022 return ret;
3023 }
3024
3025 /* Signals fence as soon as all the work currently put on queue is done. */
3026 static VkResult radv_signal_fence(struct radv_queue *queue,
3027 struct radv_fence *fence)
3028 {
3029 int ret;
3030 VkResult result;
3031 struct radv_winsys_sem_info sem_info;
3032
3033 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3034 radv_fence_to_handle(fence));
3035 if (result != VK_SUCCESS)
3036 return result;
3037
3038 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3039 &queue->device->empty_cs[queue->queue_family_index],
3040 1, NULL, NULL, &sem_info, NULL,
3041 false, fence->fence);
3042 radv_free_sem_info(&sem_info);
3043
3044 if (ret)
3045 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3046
3047 return VK_SUCCESS;
3048 }
3049
3050 VkResult radv_QueueSubmit(
3051 VkQueue _queue,
3052 uint32_t submitCount,
3053 const VkSubmitInfo* pSubmits,
3054 VkFence _fence)
3055 {
3056 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3057 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3058 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3059 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3060 int ret;
3061 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3062 uint32_t scratch_size = 0;
3063 uint32_t compute_scratch_size = 0;
3064 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3065 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3066 VkResult result;
3067 bool fence_emitted = false;
3068 bool tess_rings_needed = false;
3069 bool sample_positions_needed = false;
3070
3071 /* Do this first so failing to allocate scratch buffers can't result in
3072 * partially executed submissions. */
3073 for (uint32_t i = 0; i < submitCount; i++) {
3074 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3075 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3076 pSubmits[i].pCommandBuffers[j]);
3077
3078 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3079 compute_scratch_size = MAX2(compute_scratch_size,
3080 cmd_buffer->compute_scratch_size_needed);
3081 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3082 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3083 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3084 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3085 }
3086 }
3087
3088 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3089 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3090 sample_positions_needed, &initial_flush_preamble_cs,
3091 &initial_preamble_cs, &continue_preamble_cs);
3092 if (result != VK_SUCCESS)
3093 return result;
3094
3095 for (uint32_t i = 0; i < submitCount; i++) {
3096 struct radeon_cmdbuf **cs_array;
3097 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3098 bool can_patch = true;
3099 uint32_t advance;
3100 struct radv_winsys_sem_info sem_info;
3101
3102 result = radv_alloc_sem_info(queue->device->instance,
3103 &sem_info,
3104 pSubmits[i].waitSemaphoreCount,
3105 pSubmits[i].pWaitSemaphores,
3106 pSubmits[i].signalSemaphoreCount,
3107 pSubmits[i].pSignalSemaphores,
3108 _fence);
3109 if (result != VK_SUCCESS)
3110 return result;
3111
3112 if (!pSubmits[i].commandBufferCount) {
3113 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3114 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3115 &queue->device->empty_cs[queue->queue_family_index],
3116 1, NULL, NULL,
3117 &sem_info, NULL,
3118 false, base_fence);
3119 if (ret) {
3120 radv_loge("failed to submit CS %d\n", i);
3121 abort();
3122 }
3123 fence_emitted = true;
3124 }
3125 radv_free_sem_info(&sem_info);
3126 continue;
3127 }
3128
3129 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3130 (pSubmits[i].commandBufferCount));
3131
3132 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3134 pSubmits[i].pCommandBuffers[j]);
3135 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3136
3137 cs_array[j] = cmd_buffer->cs;
3138 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3139 can_patch = false;
3140
3141 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3142 }
3143
3144 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3145 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3146 const struct radv_winsys_bo_list *bo_list = NULL;
3147
3148 advance = MIN2(max_cs_submission,
3149 pSubmits[i].commandBufferCount - j);
3150
3151 if (queue->device->trace_bo)
3152 *queue->device->trace_id_ptr = 0;
3153
3154 sem_info.cs_emit_wait = j == 0;
3155 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3156
3157 if (unlikely(queue->device->use_global_bo_list)) {
3158 pthread_mutex_lock(&queue->device->bo_list.mutex);
3159 bo_list = &queue->device->bo_list.list;
3160 }
3161
3162 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3163 advance, initial_preamble, continue_preamble_cs,
3164 &sem_info, bo_list,
3165 can_patch, base_fence);
3166
3167 if (unlikely(queue->device->use_global_bo_list))
3168 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3169
3170 if (ret) {
3171 radv_loge("failed to submit CS %d\n", i);
3172 abort();
3173 }
3174 fence_emitted = true;
3175 if (queue->device->trace_bo) {
3176 radv_check_gpu_hangs(queue, cs_array[j]);
3177 }
3178 }
3179
3180 radv_free_temp_syncobjs(queue->device,
3181 pSubmits[i].waitSemaphoreCount,
3182 pSubmits[i].pWaitSemaphores);
3183 radv_free_sem_info(&sem_info);
3184 free(cs_array);
3185 }
3186
3187 if (fence) {
3188 if (!fence_emitted) {
3189 result = radv_signal_fence(queue, fence);
3190 if (result != VK_SUCCESS)
3191 return result;
3192 }
3193 }
3194
3195 return VK_SUCCESS;
3196 }
3197
3198 VkResult radv_QueueWaitIdle(
3199 VkQueue _queue)
3200 {
3201 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3202
3203 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3204 radv_queue_family_to_ring(queue->queue_family_index),
3205 queue->queue_idx);
3206 return VK_SUCCESS;
3207 }
3208
3209 VkResult radv_DeviceWaitIdle(
3210 VkDevice _device)
3211 {
3212 RADV_FROM_HANDLE(radv_device, device, _device);
3213
3214 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3215 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3216 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3217 }
3218 }
3219 return VK_SUCCESS;
3220 }
3221
3222 VkResult radv_EnumerateInstanceExtensionProperties(
3223 const char* pLayerName,
3224 uint32_t* pPropertyCount,
3225 VkExtensionProperties* pProperties)
3226 {
3227 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3228
3229 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3230 if (radv_supported_instance_extensions.extensions[i]) {
3231 vk_outarray_append(&out, prop) {
3232 *prop = radv_instance_extensions[i];
3233 }
3234 }
3235 }
3236
3237 return vk_outarray_status(&out);
3238 }
3239
3240 VkResult radv_EnumerateDeviceExtensionProperties(
3241 VkPhysicalDevice physicalDevice,
3242 const char* pLayerName,
3243 uint32_t* pPropertyCount,
3244 VkExtensionProperties* pProperties)
3245 {
3246 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3247 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3248
3249 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3250 if (device->supported_extensions.extensions[i]) {
3251 vk_outarray_append(&out, prop) {
3252 *prop = radv_device_extensions[i];
3253 }
3254 }
3255 }
3256
3257 return vk_outarray_status(&out);
3258 }
3259
3260 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3261 VkInstance _instance,
3262 const char* pName)
3263 {
3264 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3265
3266 return radv_lookup_entrypoint_checked(pName,
3267 instance ? instance->apiVersion : 0,
3268 instance ? &instance->enabled_extensions : NULL,
3269 NULL);
3270 }
3271
3272 /* The loader wants us to expose a second GetInstanceProcAddr function
3273 * to work around certain LD_PRELOAD issues seen in apps.
3274 */
3275 PUBLIC
3276 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3277 VkInstance instance,
3278 const char* pName);
3279
3280 PUBLIC
3281 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3282 VkInstance instance,
3283 const char* pName)
3284 {
3285 return radv_GetInstanceProcAddr(instance, pName);
3286 }
3287
3288 PUBLIC
3289 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3290 VkInstance _instance,
3291 const char* pName);
3292
3293 PUBLIC
3294 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3295 VkInstance _instance,
3296 const char* pName)
3297 {
3298 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3299
3300 return radv_lookup_physical_device_entrypoint_checked(pName,
3301 instance ? instance->apiVersion : 0,
3302 instance ? &instance->enabled_extensions : NULL);
3303 }
3304
3305 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3306 VkDevice _device,
3307 const char* pName)
3308 {
3309 RADV_FROM_HANDLE(radv_device, device, _device);
3310
3311 return radv_lookup_entrypoint_checked(pName,
3312 device->instance->apiVersion,
3313 &device->instance->enabled_extensions,
3314 &device->enabled_extensions);
3315 }
3316
3317 bool radv_get_memory_fd(struct radv_device *device,
3318 struct radv_device_memory *memory,
3319 int *pFD)
3320 {
3321 struct radeon_bo_metadata metadata;
3322
3323 if (memory->image) {
3324 radv_init_metadata(device, memory->image, &metadata);
3325 device->ws->buffer_set_metadata(memory->bo, &metadata);
3326 }
3327
3328 return device->ws->buffer_get_fd(device->ws, memory->bo,
3329 pFD);
3330 }
3331
3332 static VkResult radv_alloc_memory(struct radv_device *device,
3333 const VkMemoryAllocateInfo* pAllocateInfo,
3334 const VkAllocationCallbacks* pAllocator,
3335 VkDeviceMemory* pMem)
3336 {
3337 struct radv_device_memory *mem;
3338 VkResult result;
3339 enum radeon_bo_domain domain;
3340 uint32_t flags = 0;
3341 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3342
3343 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3344
3345 if (pAllocateInfo->allocationSize == 0) {
3346 /* Apparently, this is allowed */
3347 *pMem = VK_NULL_HANDLE;
3348 return VK_SUCCESS;
3349 }
3350
3351 const VkImportMemoryFdInfoKHR *import_info =
3352 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3353 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3354 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3355 const VkExportMemoryAllocateInfo *export_info =
3356 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3357 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3358 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3359
3360 const struct wsi_memory_allocate_info *wsi_info =
3361 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3362
3363 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3364 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3365 if (mem == NULL)
3366 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3367
3368 if (wsi_info && wsi_info->implicit_sync)
3369 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3370
3371 if (dedicate_info) {
3372 mem->image = radv_image_from_handle(dedicate_info->image);
3373 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3374 } else {
3375 mem->image = NULL;
3376 mem->buffer = NULL;
3377 }
3378
3379 float priority_float = 0.5;
3380 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3381 vk_find_struct_const(pAllocateInfo->pNext,
3382 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3383 if (priority_ext)
3384 priority_float = priority_ext->priority;
3385
3386 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3387 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3388
3389 mem->user_ptr = NULL;
3390
3391 if (import_info) {
3392 assert(import_info->handleType ==
3393 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3394 import_info->handleType ==
3395 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3396 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3397 priority, NULL, NULL);
3398 if (!mem->bo) {
3399 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3400 goto fail;
3401 } else {
3402 close(import_info->fd);
3403 }
3404 } else if (host_ptr_info) {
3405 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3406 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3407 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3408 pAllocateInfo->allocationSize,
3409 priority);
3410 if (!mem->bo) {
3411 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3412 goto fail;
3413 } else {
3414 mem->user_ptr = host_ptr_info->pHostPointer;
3415 }
3416 } else {
3417 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3418 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3419 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3420 domain = RADEON_DOMAIN_GTT;
3421 else
3422 domain = RADEON_DOMAIN_VRAM;
3423
3424 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3425 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3426 else
3427 flags |= RADEON_FLAG_CPU_ACCESS;
3428
3429 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3430 flags |= RADEON_FLAG_GTT_WC;
3431
3432 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3433 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3434 if (device->use_global_bo_list) {
3435 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3436 }
3437 }
3438
3439 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3440 domain, flags, priority);
3441
3442 if (!mem->bo) {
3443 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3444 goto fail;
3445 }
3446 mem->type_index = mem_type_index;
3447 }
3448
3449 result = radv_bo_list_add(device, mem->bo);
3450 if (result != VK_SUCCESS)
3451 goto fail_bo;
3452
3453 *pMem = radv_device_memory_to_handle(mem);
3454
3455 return VK_SUCCESS;
3456
3457 fail_bo:
3458 device->ws->buffer_destroy(mem->bo);
3459 fail:
3460 vk_free2(&device->alloc, pAllocator, mem);
3461
3462 return result;
3463 }
3464
3465 VkResult radv_AllocateMemory(
3466 VkDevice _device,
3467 const VkMemoryAllocateInfo* pAllocateInfo,
3468 const VkAllocationCallbacks* pAllocator,
3469 VkDeviceMemory* pMem)
3470 {
3471 RADV_FROM_HANDLE(radv_device, device, _device);
3472 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3473 }
3474
3475 void radv_FreeMemory(
3476 VkDevice _device,
3477 VkDeviceMemory _mem,
3478 const VkAllocationCallbacks* pAllocator)
3479 {
3480 RADV_FROM_HANDLE(radv_device, device, _device);
3481 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3482
3483 if (mem == NULL)
3484 return;
3485
3486 radv_bo_list_remove(device, mem->bo);
3487 device->ws->buffer_destroy(mem->bo);
3488 mem->bo = NULL;
3489
3490 vk_free2(&device->alloc, pAllocator, mem);
3491 }
3492
3493 VkResult radv_MapMemory(
3494 VkDevice _device,
3495 VkDeviceMemory _memory,
3496 VkDeviceSize offset,
3497 VkDeviceSize size,
3498 VkMemoryMapFlags flags,
3499 void** ppData)
3500 {
3501 RADV_FROM_HANDLE(radv_device, device, _device);
3502 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3503
3504 if (mem == NULL) {
3505 *ppData = NULL;
3506 return VK_SUCCESS;
3507 }
3508
3509 if (mem->user_ptr)
3510 *ppData = mem->user_ptr;
3511 else
3512 *ppData = device->ws->buffer_map(mem->bo);
3513
3514 if (*ppData) {
3515 *ppData += offset;
3516 return VK_SUCCESS;
3517 }
3518
3519 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3520 }
3521
3522 void radv_UnmapMemory(
3523 VkDevice _device,
3524 VkDeviceMemory _memory)
3525 {
3526 RADV_FROM_HANDLE(radv_device, device, _device);
3527 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3528
3529 if (mem == NULL)
3530 return;
3531
3532 if (mem->user_ptr == NULL)
3533 device->ws->buffer_unmap(mem->bo);
3534 }
3535
3536 VkResult radv_FlushMappedMemoryRanges(
3537 VkDevice _device,
3538 uint32_t memoryRangeCount,
3539 const VkMappedMemoryRange* pMemoryRanges)
3540 {
3541 return VK_SUCCESS;
3542 }
3543
3544 VkResult radv_InvalidateMappedMemoryRanges(
3545 VkDevice _device,
3546 uint32_t memoryRangeCount,
3547 const VkMappedMemoryRange* pMemoryRanges)
3548 {
3549 return VK_SUCCESS;
3550 }
3551
3552 void radv_GetBufferMemoryRequirements(
3553 VkDevice _device,
3554 VkBuffer _buffer,
3555 VkMemoryRequirements* pMemoryRequirements)
3556 {
3557 RADV_FROM_HANDLE(radv_device, device, _device);
3558 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3559
3560 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3561
3562 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3563 pMemoryRequirements->alignment = 4096;
3564 else
3565 pMemoryRequirements->alignment = 16;
3566
3567 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3568 }
3569
3570 void radv_GetBufferMemoryRequirements2(
3571 VkDevice device,
3572 const VkBufferMemoryRequirementsInfo2 *pInfo,
3573 VkMemoryRequirements2 *pMemoryRequirements)
3574 {
3575 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3576 &pMemoryRequirements->memoryRequirements);
3577 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3578 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3579 switch (ext->sType) {
3580 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3581 VkMemoryDedicatedRequirements *req =
3582 (VkMemoryDedicatedRequirements *) ext;
3583 req->requiresDedicatedAllocation = buffer->shareable;
3584 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3585 break;
3586 }
3587 default:
3588 break;
3589 }
3590 }
3591 }
3592
3593 void radv_GetImageMemoryRequirements(
3594 VkDevice _device,
3595 VkImage _image,
3596 VkMemoryRequirements* pMemoryRequirements)
3597 {
3598 RADV_FROM_HANDLE(radv_device, device, _device);
3599 RADV_FROM_HANDLE(radv_image, image, _image);
3600
3601 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3602
3603 pMemoryRequirements->size = image->size;
3604 pMemoryRequirements->alignment = image->alignment;
3605 }
3606
3607 void radv_GetImageMemoryRequirements2(
3608 VkDevice device,
3609 const VkImageMemoryRequirementsInfo2 *pInfo,
3610 VkMemoryRequirements2 *pMemoryRequirements)
3611 {
3612 radv_GetImageMemoryRequirements(device, pInfo->image,
3613 &pMemoryRequirements->memoryRequirements);
3614
3615 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3616
3617 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3618 switch (ext->sType) {
3619 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3620 VkMemoryDedicatedRequirements *req =
3621 (VkMemoryDedicatedRequirements *) ext;
3622 req->requiresDedicatedAllocation = image->shareable;
3623 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3624 break;
3625 }
3626 default:
3627 break;
3628 }
3629 }
3630 }
3631
3632 void radv_GetImageSparseMemoryRequirements(
3633 VkDevice device,
3634 VkImage image,
3635 uint32_t* pSparseMemoryRequirementCount,
3636 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3637 {
3638 stub();
3639 }
3640
3641 void radv_GetImageSparseMemoryRequirements2(
3642 VkDevice device,
3643 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3644 uint32_t* pSparseMemoryRequirementCount,
3645 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3646 {
3647 stub();
3648 }
3649
3650 void radv_GetDeviceMemoryCommitment(
3651 VkDevice device,
3652 VkDeviceMemory memory,
3653 VkDeviceSize* pCommittedMemoryInBytes)
3654 {
3655 *pCommittedMemoryInBytes = 0;
3656 }
3657
3658 VkResult radv_BindBufferMemory2(VkDevice device,
3659 uint32_t bindInfoCount,
3660 const VkBindBufferMemoryInfo *pBindInfos)
3661 {
3662 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3663 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3664 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3665
3666 if (mem) {
3667 buffer->bo = mem->bo;
3668 buffer->offset = pBindInfos[i].memoryOffset;
3669 } else {
3670 buffer->bo = NULL;
3671 }
3672 }
3673 return VK_SUCCESS;
3674 }
3675
3676 VkResult radv_BindBufferMemory(
3677 VkDevice device,
3678 VkBuffer buffer,
3679 VkDeviceMemory memory,
3680 VkDeviceSize memoryOffset)
3681 {
3682 const VkBindBufferMemoryInfo info = {
3683 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3684 .buffer = buffer,
3685 .memory = memory,
3686 .memoryOffset = memoryOffset
3687 };
3688
3689 return radv_BindBufferMemory2(device, 1, &info);
3690 }
3691
3692 VkResult radv_BindImageMemory2(VkDevice device,
3693 uint32_t bindInfoCount,
3694 const VkBindImageMemoryInfo *pBindInfos)
3695 {
3696 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3697 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3698 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3699
3700 if (mem) {
3701 image->bo = mem->bo;
3702 image->offset = pBindInfos[i].memoryOffset;
3703 } else {
3704 image->bo = NULL;
3705 image->offset = 0;
3706 }
3707 }
3708 return VK_SUCCESS;
3709 }
3710
3711
3712 VkResult radv_BindImageMemory(
3713 VkDevice device,
3714 VkImage image,
3715 VkDeviceMemory memory,
3716 VkDeviceSize memoryOffset)
3717 {
3718 const VkBindImageMemoryInfo info = {
3719 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3720 .image = image,
3721 .memory = memory,
3722 .memoryOffset = memoryOffset
3723 };
3724
3725 return radv_BindImageMemory2(device, 1, &info);
3726 }
3727
3728
3729 static void
3730 radv_sparse_buffer_bind_memory(struct radv_device *device,
3731 const VkSparseBufferMemoryBindInfo *bind)
3732 {
3733 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3734
3735 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3736 struct radv_device_memory *mem = NULL;
3737
3738 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3739 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3740
3741 device->ws->buffer_virtual_bind(buffer->bo,
3742 bind->pBinds[i].resourceOffset,
3743 bind->pBinds[i].size,
3744 mem ? mem->bo : NULL,
3745 bind->pBinds[i].memoryOffset);
3746 }
3747 }
3748
3749 static void
3750 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3751 const VkSparseImageOpaqueMemoryBindInfo *bind)
3752 {
3753 RADV_FROM_HANDLE(radv_image, image, bind->image);
3754
3755 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3756 struct radv_device_memory *mem = NULL;
3757
3758 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3759 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3760
3761 device->ws->buffer_virtual_bind(image->bo,
3762 bind->pBinds[i].resourceOffset,
3763 bind->pBinds[i].size,
3764 mem ? mem->bo : NULL,
3765 bind->pBinds[i].memoryOffset);
3766 }
3767 }
3768
3769 VkResult radv_QueueBindSparse(
3770 VkQueue _queue,
3771 uint32_t bindInfoCount,
3772 const VkBindSparseInfo* pBindInfo,
3773 VkFence _fence)
3774 {
3775 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3776 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3777 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3778 bool fence_emitted = false;
3779 VkResult result;
3780 int ret;
3781
3782 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3783 struct radv_winsys_sem_info sem_info;
3784 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3785 radv_sparse_buffer_bind_memory(queue->device,
3786 pBindInfo[i].pBufferBinds + j);
3787 }
3788
3789 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3790 radv_sparse_image_opaque_bind_memory(queue->device,
3791 pBindInfo[i].pImageOpaqueBinds + j);
3792 }
3793
3794 VkResult result;
3795 result = radv_alloc_sem_info(queue->device->instance,
3796 &sem_info,
3797 pBindInfo[i].waitSemaphoreCount,
3798 pBindInfo[i].pWaitSemaphores,
3799 pBindInfo[i].signalSemaphoreCount,
3800 pBindInfo[i].pSignalSemaphores,
3801 _fence);
3802 if (result != VK_SUCCESS)
3803 return result;
3804
3805 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3806 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3807 &queue->device->empty_cs[queue->queue_family_index],
3808 1, NULL, NULL,
3809 &sem_info, NULL,
3810 false, base_fence);
3811 if (ret) {
3812 radv_loge("failed to submit CS %d\n", i);
3813 abort();
3814 }
3815
3816 fence_emitted = true;
3817 }
3818
3819 radv_free_sem_info(&sem_info);
3820
3821 }
3822
3823 if (fence) {
3824 if (!fence_emitted) {
3825 result = radv_signal_fence(queue, fence);
3826 if (result != VK_SUCCESS)
3827 return result;
3828 }
3829 }
3830
3831 return VK_SUCCESS;
3832 }
3833
3834 VkResult radv_CreateFence(
3835 VkDevice _device,
3836 const VkFenceCreateInfo* pCreateInfo,
3837 const VkAllocationCallbacks* pAllocator,
3838 VkFence* pFence)
3839 {
3840 RADV_FROM_HANDLE(radv_device, device, _device);
3841 const VkExportFenceCreateInfo *export =
3842 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3843 VkExternalFenceHandleTypeFlags handleTypes =
3844 export ? export->handleTypes : 0;
3845
3846 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3847 sizeof(*fence), 8,
3848 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3849
3850 if (!fence)
3851 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3852
3853 fence->fence_wsi = NULL;
3854 fence->temp_syncobj = 0;
3855 if (device->always_use_syncobj || handleTypes) {
3856 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3857 if (ret) {
3858 vk_free2(&device->alloc, pAllocator, fence);
3859 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3860 }
3861 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3862 device->ws->signal_syncobj(device->ws, fence->syncobj);
3863 }
3864 fence->fence = NULL;
3865 } else {
3866 fence->fence = device->ws->create_fence();
3867 if (!fence->fence) {
3868 vk_free2(&device->alloc, pAllocator, fence);
3869 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3870 }
3871 fence->syncobj = 0;
3872 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3873 device->ws->signal_fence(fence->fence);
3874 }
3875
3876 *pFence = radv_fence_to_handle(fence);
3877
3878 return VK_SUCCESS;
3879 }
3880
3881 void radv_DestroyFence(
3882 VkDevice _device,
3883 VkFence _fence,
3884 const VkAllocationCallbacks* pAllocator)
3885 {
3886 RADV_FROM_HANDLE(radv_device, device, _device);
3887 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3888
3889 if (!fence)
3890 return;
3891
3892 if (fence->temp_syncobj)
3893 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3894 if (fence->syncobj)
3895 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3896 if (fence->fence)
3897 device->ws->destroy_fence(fence->fence);
3898 if (fence->fence_wsi)
3899 fence->fence_wsi->destroy(fence->fence_wsi);
3900 vk_free2(&device->alloc, pAllocator, fence);
3901 }
3902
3903
3904 uint64_t radv_get_current_time(void)
3905 {
3906 struct timespec tv;
3907 clock_gettime(CLOCK_MONOTONIC, &tv);
3908 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3909 }
3910
3911 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3912 {
3913 uint64_t current_time = radv_get_current_time();
3914
3915 timeout = MIN2(UINT64_MAX - current_time, timeout);
3916
3917 return current_time + timeout;
3918 }
3919
3920
3921 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3922 uint32_t fenceCount, const VkFence *pFences)
3923 {
3924 for (uint32_t i = 0; i < fenceCount; ++i) {
3925 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3926 if (fence->fence == NULL || fence->syncobj ||
3927 fence->temp_syncobj || fence->fence_wsi ||
3928 (!device->ws->is_fence_waitable(fence->fence)))
3929 return false;
3930 }
3931 return true;
3932 }
3933
3934 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3935 {
3936 for (uint32_t i = 0; i < fenceCount; ++i) {
3937 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3938 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3939 return false;
3940 }
3941 return true;
3942 }
3943
3944 VkResult radv_WaitForFences(
3945 VkDevice _device,
3946 uint32_t fenceCount,
3947 const VkFence* pFences,
3948 VkBool32 waitAll,
3949 uint64_t timeout)
3950 {
3951 RADV_FROM_HANDLE(radv_device, device, _device);
3952 timeout = radv_get_absolute_timeout(timeout);
3953
3954 if (device->always_use_syncobj &&
3955 radv_all_fences_syncobj(fenceCount, pFences))
3956 {
3957 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3958 if (!handles)
3959 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3960
3961 for (uint32_t i = 0; i < fenceCount; ++i) {
3962 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3963 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3964 }
3965
3966 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3967
3968 free(handles);
3969 return success ? VK_SUCCESS : VK_TIMEOUT;
3970 }
3971
3972 if (!waitAll && fenceCount > 1) {
3973 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3974 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3975 uint32_t wait_count = 0;
3976 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3977 if (!fences)
3978 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3979
3980 for (uint32_t i = 0; i < fenceCount; ++i) {
3981 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3982
3983 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3984 free(fences);
3985 return VK_SUCCESS;
3986 }
3987
3988 fences[wait_count++] = fence->fence;
3989 }
3990
3991 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3992 waitAll, timeout - radv_get_current_time());
3993
3994 free(fences);
3995 return success ? VK_SUCCESS : VK_TIMEOUT;
3996 }
3997
3998 while(radv_get_current_time() <= timeout) {
3999 for (uint32_t i = 0; i < fenceCount; ++i) {
4000 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4001 return VK_SUCCESS;
4002 }
4003 }
4004 return VK_TIMEOUT;
4005 }
4006
4007 for (uint32_t i = 0; i < fenceCount; ++i) {
4008 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4009 bool expired = false;
4010
4011 if (fence->temp_syncobj) {
4012 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4013 return VK_TIMEOUT;
4014 continue;
4015 }
4016
4017 if (fence->syncobj) {
4018 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4019 return VK_TIMEOUT;
4020 continue;
4021 }
4022
4023 if (fence->fence) {
4024 if (!device->ws->is_fence_waitable(fence->fence)) {
4025 while(!device->ws->is_fence_waitable(fence->fence) &&
4026 radv_get_current_time() <= timeout)
4027 /* Do nothing */;
4028 }
4029
4030 expired = device->ws->fence_wait(device->ws,
4031 fence->fence,
4032 true, timeout);
4033 if (!expired)
4034 return VK_TIMEOUT;
4035 }
4036
4037 if (fence->fence_wsi) {
4038 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4039 if (result != VK_SUCCESS)
4040 return result;
4041 }
4042 }
4043
4044 return VK_SUCCESS;
4045 }
4046
4047 VkResult radv_ResetFences(VkDevice _device,
4048 uint32_t fenceCount,
4049 const VkFence *pFences)
4050 {
4051 RADV_FROM_HANDLE(radv_device, device, _device);
4052
4053 for (unsigned i = 0; i < fenceCount; ++i) {
4054 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4055 if (fence->fence)
4056 device->ws->reset_fence(fence->fence);
4057
4058 /* Per spec, we first restore the permanent payload, and then reset, so
4059 * having a temp syncobj should not skip resetting the permanent syncobj. */
4060 if (fence->temp_syncobj) {
4061 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4062 fence->temp_syncobj = 0;
4063 }
4064
4065 if (fence->syncobj) {
4066 device->ws->reset_syncobj(device->ws, fence->syncobj);
4067 }
4068 }
4069
4070 return VK_SUCCESS;
4071 }
4072
4073 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4074 {
4075 RADV_FROM_HANDLE(radv_device, device, _device);
4076 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4077
4078 if (fence->temp_syncobj) {
4079 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4080 return success ? VK_SUCCESS : VK_NOT_READY;
4081 }
4082
4083 if (fence->syncobj) {
4084 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4085 return success ? VK_SUCCESS : VK_NOT_READY;
4086 }
4087
4088 if (fence->fence) {
4089 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4090 return VK_NOT_READY;
4091 }
4092 if (fence->fence_wsi) {
4093 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4094
4095 if (result != VK_SUCCESS) {
4096 if (result == VK_TIMEOUT)
4097 return VK_NOT_READY;
4098 return result;
4099 }
4100 }
4101 return VK_SUCCESS;
4102 }
4103
4104
4105 // Queue semaphore functions
4106
4107 VkResult radv_CreateSemaphore(
4108 VkDevice _device,
4109 const VkSemaphoreCreateInfo* pCreateInfo,
4110 const VkAllocationCallbacks* pAllocator,
4111 VkSemaphore* pSemaphore)
4112 {
4113 RADV_FROM_HANDLE(radv_device, device, _device);
4114 const VkExportSemaphoreCreateInfo *export =
4115 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4116 VkExternalSemaphoreHandleTypeFlags handleTypes =
4117 export ? export->handleTypes : 0;
4118
4119 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4120 sizeof(*sem), 8,
4121 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4122 if (!sem)
4123 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4124
4125 sem->temp_syncobj = 0;
4126 /* create a syncobject if we are going to export this semaphore */
4127 if (device->always_use_syncobj || handleTypes) {
4128 assert (device->physical_device->rad_info.has_syncobj);
4129 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4130 if (ret) {
4131 vk_free2(&device->alloc, pAllocator, sem);
4132 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4133 }
4134 sem->sem = NULL;
4135 } else {
4136 sem->sem = device->ws->create_sem(device->ws);
4137 if (!sem->sem) {
4138 vk_free2(&device->alloc, pAllocator, sem);
4139 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4140 }
4141 sem->syncobj = 0;
4142 }
4143
4144 *pSemaphore = radv_semaphore_to_handle(sem);
4145 return VK_SUCCESS;
4146 }
4147
4148 void radv_DestroySemaphore(
4149 VkDevice _device,
4150 VkSemaphore _semaphore,
4151 const VkAllocationCallbacks* pAllocator)
4152 {
4153 RADV_FROM_HANDLE(radv_device, device, _device);
4154 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4155 if (!_semaphore)
4156 return;
4157
4158 if (sem->syncobj)
4159 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4160 else
4161 device->ws->destroy_sem(sem->sem);
4162 vk_free2(&device->alloc, pAllocator, sem);
4163 }
4164
4165 VkResult radv_CreateEvent(
4166 VkDevice _device,
4167 const VkEventCreateInfo* pCreateInfo,
4168 const VkAllocationCallbacks* pAllocator,
4169 VkEvent* pEvent)
4170 {
4171 RADV_FROM_HANDLE(radv_device, device, _device);
4172 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4173 sizeof(*event), 8,
4174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4175
4176 if (!event)
4177 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4178
4179 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4180 RADEON_DOMAIN_GTT,
4181 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4182 RADV_BO_PRIORITY_FENCE);
4183 if (!event->bo) {
4184 vk_free2(&device->alloc, pAllocator, event);
4185 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4186 }
4187
4188 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4189
4190 *pEvent = radv_event_to_handle(event);
4191
4192 return VK_SUCCESS;
4193 }
4194
4195 void radv_DestroyEvent(
4196 VkDevice _device,
4197 VkEvent _event,
4198 const VkAllocationCallbacks* pAllocator)
4199 {
4200 RADV_FROM_HANDLE(radv_device, device, _device);
4201 RADV_FROM_HANDLE(radv_event, event, _event);
4202
4203 if (!event)
4204 return;
4205 device->ws->buffer_destroy(event->bo);
4206 vk_free2(&device->alloc, pAllocator, event);
4207 }
4208
4209 VkResult radv_GetEventStatus(
4210 VkDevice _device,
4211 VkEvent _event)
4212 {
4213 RADV_FROM_HANDLE(radv_event, event, _event);
4214
4215 if (*event->map == 1)
4216 return VK_EVENT_SET;
4217 return VK_EVENT_RESET;
4218 }
4219
4220 VkResult radv_SetEvent(
4221 VkDevice _device,
4222 VkEvent _event)
4223 {
4224 RADV_FROM_HANDLE(radv_event, event, _event);
4225 *event->map = 1;
4226
4227 return VK_SUCCESS;
4228 }
4229
4230 VkResult radv_ResetEvent(
4231 VkDevice _device,
4232 VkEvent _event)
4233 {
4234 RADV_FROM_HANDLE(radv_event, event, _event);
4235 *event->map = 0;
4236
4237 return VK_SUCCESS;
4238 }
4239
4240 VkResult radv_CreateBuffer(
4241 VkDevice _device,
4242 const VkBufferCreateInfo* pCreateInfo,
4243 const VkAllocationCallbacks* pAllocator,
4244 VkBuffer* pBuffer)
4245 {
4246 RADV_FROM_HANDLE(radv_device, device, _device);
4247 struct radv_buffer *buffer;
4248
4249 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4250
4251 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4252 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4253 if (buffer == NULL)
4254 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4255
4256 buffer->size = pCreateInfo->size;
4257 buffer->usage = pCreateInfo->usage;
4258 buffer->bo = NULL;
4259 buffer->offset = 0;
4260 buffer->flags = pCreateInfo->flags;
4261
4262 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4263 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4264
4265 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4266 buffer->bo = device->ws->buffer_create(device->ws,
4267 align64(buffer->size, 4096),
4268 4096, 0, RADEON_FLAG_VIRTUAL,
4269 RADV_BO_PRIORITY_VIRTUAL);
4270 if (!buffer->bo) {
4271 vk_free2(&device->alloc, pAllocator, buffer);
4272 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4273 }
4274 }
4275
4276 *pBuffer = radv_buffer_to_handle(buffer);
4277
4278 return VK_SUCCESS;
4279 }
4280
4281 void radv_DestroyBuffer(
4282 VkDevice _device,
4283 VkBuffer _buffer,
4284 const VkAllocationCallbacks* pAllocator)
4285 {
4286 RADV_FROM_HANDLE(radv_device, device, _device);
4287 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4288
4289 if (!buffer)
4290 return;
4291
4292 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4293 device->ws->buffer_destroy(buffer->bo);
4294
4295 vk_free2(&device->alloc, pAllocator, buffer);
4296 }
4297
4298 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4299 VkDevice device,
4300 const VkBufferDeviceAddressInfoEXT* pInfo)
4301 {
4302 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4303 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4304 }
4305
4306
4307 static inline unsigned
4308 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4309 {
4310 if (stencil)
4311 return plane->surface.u.legacy.stencil_tiling_index[level];
4312 else
4313 return plane->surface.u.legacy.tiling_index[level];
4314 }
4315
4316 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4317 {
4318 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4319 }
4320
4321 static uint32_t
4322 radv_init_dcc_control_reg(struct radv_device *device,
4323 struct radv_image_view *iview)
4324 {
4325 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4326 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4327 unsigned max_compressed_block_size;
4328 unsigned independent_128b_blocks;
4329 unsigned independent_64b_blocks;
4330
4331 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4332 return 0;
4333
4334 if (!device->physical_device->rad_info.has_dedicated_vram) {
4335 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4336 * dGPU and 64 for APU because all of our APUs to date use
4337 * DIMMs which have a request granularity size of 64B while all
4338 * other chips have a 32B request size.
4339 */
4340 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4341 }
4342
4343 if (device->physical_device->rad_info.chip_class >= GFX10) {
4344 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4345 independent_64b_blocks = 0;
4346 independent_128b_blocks = 1;
4347 } else {
4348 independent_128b_blocks = 0;
4349
4350 if (iview->image->info.samples > 1) {
4351 if (iview->image->planes[0].surface.bpe == 1)
4352 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4353 else if (iview->image->planes[0].surface.bpe == 2)
4354 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4355 }
4356
4357 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4358 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4359 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4360 /* If this DCC image is potentially going to be used in texture
4361 * fetches, we need some special settings.
4362 */
4363 independent_64b_blocks = 1;
4364 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4365 } else {
4366 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4367 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4368 * big as possible for better compression state.
4369 */
4370 independent_64b_blocks = 0;
4371 max_compressed_block_size = max_uncompressed_block_size;
4372 }
4373 }
4374
4375 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4376 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4377 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4378 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4379 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4380 }
4381
4382 void
4383 radv_initialise_color_surface(struct radv_device *device,
4384 struct radv_color_buffer_info *cb,
4385 struct radv_image_view *iview)
4386 {
4387 const struct vk_format_description *desc;
4388 unsigned ntype, format, swap, endian;
4389 unsigned blend_clamp = 0, blend_bypass = 0;
4390 uint64_t va;
4391 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4392 const struct radeon_surf *surf = &plane->surface;
4393
4394 desc = vk_format_description(iview->vk_format);
4395
4396 memset(cb, 0, sizeof(*cb));
4397
4398 /* Intensity is implemented as Red, so treat it that way. */
4399 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4400
4401 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4402
4403 cb->cb_color_base = va >> 8;
4404
4405 if (device->physical_device->rad_info.chip_class >= GFX9) {
4406 struct gfx9_surf_meta_flags meta;
4407 if (iview->image->dcc_offset)
4408 meta = surf->u.gfx9.dcc;
4409 else
4410 meta = surf->u.gfx9.cmask;
4411
4412 if (device->physical_device->rad_info.chip_class >= GFX10) {
4413 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4414 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4415 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4416 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4417 } else {
4418 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4419 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4420 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4421 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4422 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4423 }
4424
4425 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4426 cb->cb_color_base |= surf->tile_swizzle;
4427 } else {
4428 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4429 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4430
4431 cb->cb_color_base += level_info->offset >> 8;
4432 if (level_info->mode == RADEON_SURF_MODE_2D)
4433 cb->cb_color_base |= surf->tile_swizzle;
4434
4435 pitch_tile_max = level_info->nblk_x / 8 - 1;
4436 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4437 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4438
4439 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4440 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4441 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4442
4443 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4444
4445 if (radv_image_has_fmask(iview->image)) {
4446 if (device->physical_device->rad_info.chip_class >= GFX7)
4447 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4448 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4449 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4450 } else {
4451 /* This must be set for fast clear to work without FMASK. */
4452 if (device->physical_device->rad_info.chip_class >= GFX7)
4453 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4454 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4455 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4456 }
4457 }
4458
4459 /* CMASK variables */
4460 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4461 va += iview->image->cmask_offset;
4462 cb->cb_color_cmask = va >> 8;
4463
4464 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4465 va += iview->image->dcc_offset;
4466
4467 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4468 device->physical_device->rad_info.chip_class <= GFX8)
4469 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4470
4471 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4472 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4473
4474 cb->cb_dcc_base = va >> 8;
4475 cb->cb_dcc_base |= dcc_tile_swizzle;
4476
4477 /* GFX10 field has the same base shift as the GFX6 field. */
4478 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4479 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4480 S_028C6C_SLICE_MAX_GFX10(max_slice);
4481
4482 if (iview->image->info.samples > 1) {
4483 unsigned log_samples = util_logbase2(iview->image->info.samples);
4484
4485 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4486 S_028C74_NUM_FRAGMENTS(log_samples);
4487 }
4488
4489 if (radv_image_has_fmask(iview->image)) {
4490 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4491 cb->cb_color_fmask = va >> 8;
4492 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4493 } else {
4494 cb->cb_color_fmask = cb->cb_color_base;
4495 }
4496
4497 ntype = radv_translate_color_numformat(iview->vk_format,
4498 desc,
4499 vk_format_get_first_non_void_channel(iview->vk_format));
4500 format = radv_translate_colorformat(iview->vk_format);
4501 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4502 radv_finishme("Illegal color\n");
4503 swap = radv_translate_colorswap(iview->vk_format, false);
4504 endian = radv_colorformat_endian_swap(format);
4505
4506 /* blend clamp should be set for all NORM/SRGB types */
4507 if (ntype == V_028C70_NUMBER_UNORM ||
4508 ntype == V_028C70_NUMBER_SNORM ||
4509 ntype == V_028C70_NUMBER_SRGB)
4510 blend_clamp = 1;
4511
4512 /* set blend bypass according to docs if SINT/UINT or
4513 8/24 COLOR variants */
4514 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4515 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4516 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4517 blend_clamp = 0;
4518 blend_bypass = 1;
4519 }
4520 #if 0
4521 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4522 (format == V_028C70_COLOR_8 ||
4523 format == V_028C70_COLOR_8_8 ||
4524 format == V_028C70_COLOR_8_8_8_8))
4525 ->color_is_int8 = true;
4526 #endif
4527 cb->cb_color_info = S_028C70_FORMAT(format) |
4528 S_028C70_COMP_SWAP(swap) |
4529 S_028C70_BLEND_CLAMP(blend_clamp) |
4530 S_028C70_BLEND_BYPASS(blend_bypass) |
4531 S_028C70_SIMPLE_FLOAT(1) |
4532 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4533 ntype != V_028C70_NUMBER_SNORM &&
4534 ntype != V_028C70_NUMBER_SRGB &&
4535 format != V_028C70_COLOR_8_24 &&
4536 format != V_028C70_COLOR_24_8) |
4537 S_028C70_NUMBER_TYPE(ntype) |
4538 S_028C70_ENDIAN(endian);
4539 if (radv_image_has_fmask(iview->image)) {
4540 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4541 if (device->physical_device->rad_info.chip_class == GFX6) {
4542 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4543 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4544 }
4545
4546 if (radv_image_is_tc_compat_cmask(iview->image)) {
4547 /* Allow the texture block to read FMASK directly
4548 * without decompressing it. This bit must be cleared
4549 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4550 * otherwise the operation doesn't happen.
4551 */
4552 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4553
4554 /* Set CMASK into a tiling format that allows the
4555 * texture block to read it.
4556 */
4557 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4558 }
4559 }
4560
4561 if (radv_image_has_cmask(iview->image) &&
4562 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4563 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4564
4565 if (radv_dcc_enabled(iview->image, iview->base_mip))
4566 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4567
4568 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4569
4570 /* This must be set for fast clear to work without FMASK. */
4571 if (!radv_image_has_fmask(iview->image) &&
4572 device->physical_device->rad_info.chip_class == GFX6) {
4573 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4574 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4575 }
4576
4577 if (device->physical_device->rad_info.chip_class >= GFX9) {
4578 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4579
4580 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4581 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4582 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4583 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4584
4585 if (device->physical_device->rad_info.chip_class >= GFX10) {
4586 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4587
4588 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4589 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4590 S_028EE0_RESOURCE_LEVEL(1);
4591 } else {
4592 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4593 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4594 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4595 }
4596
4597 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4598 S_028C68_MIP0_HEIGHT(height - 1) |
4599 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4600 }
4601 }
4602
4603 static unsigned
4604 radv_calc_decompress_on_z_planes(struct radv_device *device,
4605 struct radv_image_view *iview)
4606 {
4607 unsigned max_zplanes = 0;
4608
4609 assert(radv_image_is_tc_compat_htile(iview->image));
4610
4611 if (device->physical_device->rad_info.chip_class >= GFX9) {
4612 /* Default value for 32-bit depth surfaces. */
4613 max_zplanes = 4;
4614
4615 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4616 iview->image->info.samples > 1)
4617 max_zplanes = 2;
4618
4619 max_zplanes = max_zplanes + 1;
4620 } else {
4621 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4622 /* Do not enable Z plane compression for 16-bit depth
4623 * surfaces because isn't supported on GFX8. Only
4624 * 32-bit depth surfaces are supported by the hardware.
4625 * This allows to maintain shader compatibility and to
4626 * reduce the number of depth decompressions.
4627 */
4628 max_zplanes = 1;
4629 } else {
4630 if (iview->image->info.samples <= 1)
4631 max_zplanes = 5;
4632 else if (iview->image->info.samples <= 4)
4633 max_zplanes = 3;
4634 else
4635 max_zplanes = 2;
4636 }
4637 }
4638
4639 return max_zplanes;
4640 }
4641
4642 void
4643 radv_initialise_ds_surface(struct radv_device *device,
4644 struct radv_ds_buffer_info *ds,
4645 struct radv_image_view *iview)
4646 {
4647 unsigned level = iview->base_mip;
4648 unsigned format, stencil_format;
4649 uint64_t va, s_offs, z_offs;
4650 bool stencil_only = false;
4651 const struct radv_image_plane *plane = &iview->image->planes[0];
4652 const struct radeon_surf *surf = &plane->surface;
4653
4654 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4655
4656 memset(ds, 0, sizeof(*ds));
4657 switch (iview->image->vk_format) {
4658 case VK_FORMAT_D24_UNORM_S8_UINT:
4659 case VK_FORMAT_X8_D24_UNORM_PACK32:
4660 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4661 ds->offset_scale = 2.0f;
4662 break;
4663 case VK_FORMAT_D16_UNORM:
4664 case VK_FORMAT_D16_UNORM_S8_UINT:
4665 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4666 ds->offset_scale = 4.0f;
4667 break;
4668 case VK_FORMAT_D32_SFLOAT:
4669 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4670 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4671 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4672 ds->offset_scale = 1.0f;
4673 break;
4674 case VK_FORMAT_S8_UINT:
4675 stencil_only = true;
4676 break;
4677 default:
4678 break;
4679 }
4680
4681 format = radv_translate_dbformat(iview->image->vk_format);
4682 stencil_format = surf->has_stencil ?
4683 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4684
4685 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4686 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4687 S_028008_SLICE_MAX(max_slice);
4688 if (device->physical_device->rad_info.chip_class >= GFX10) {
4689 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4690 S_028008_SLICE_MAX_HI(max_slice >> 11);
4691 }
4692
4693 ds->db_htile_data_base = 0;
4694 ds->db_htile_surface = 0;
4695
4696 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4697 s_offs = z_offs = va;
4698
4699 if (device->physical_device->rad_info.chip_class >= GFX9) {
4700 assert(surf->u.gfx9.surf_offset == 0);
4701 s_offs += surf->u.gfx9.stencil_offset;
4702
4703 ds->db_z_info = S_028038_FORMAT(format) |
4704 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4705 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4706 S_028038_MAXMIP(iview->image->info.levels - 1) |
4707 S_028038_ZRANGE_PRECISION(1);
4708 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4709 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4710
4711 if (device->physical_device->rad_info.chip_class == GFX9) {
4712 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4713 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4714 }
4715
4716 ds->db_depth_view |= S_028008_MIPID(level);
4717 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4718 S_02801C_Y_MAX(iview->image->info.height - 1);
4719
4720 if (radv_htile_enabled(iview->image, level)) {
4721 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4722
4723 if (radv_image_is_tc_compat_htile(iview->image)) {
4724 unsigned max_zplanes =
4725 radv_calc_decompress_on_z_planes(device, iview);
4726
4727 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4728
4729 if (device->physical_device->rad_info.chip_class >= GFX10) {
4730 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4731 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4732 } else {
4733 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4734 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4735 }
4736 }
4737
4738 if (!surf->has_stencil)
4739 /* Use all of the htile_buffer for depth if there's no stencil. */
4740 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4741 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4742 iview->image->htile_offset;
4743 ds->db_htile_data_base = va >> 8;
4744 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4745 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4746
4747 if (device->physical_device->rad_info.chip_class == GFX9) {
4748 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4749 }
4750 }
4751 } else {
4752 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4753
4754 if (stencil_only)
4755 level_info = &surf->u.legacy.stencil_level[level];
4756
4757 z_offs += surf->u.legacy.level[level].offset;
4758 s_offs += surf->u.legacy.stencil_level[level].offset;
4759
4760 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4761 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4762 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4763
4764 if (iview->image->info.samples > 1)
4765 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4766
4767 if (device->physical_device->rad_info.chip_class >= GFX7) {
4768 struct radeon_info *info = &device->physical_device->rad_info;
4769 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4770 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4771 unsigned macro_index = surf->u.legacy.macro_tile_index;
4772 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4773 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4774 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4775
4776 if (stencil_only)
4777 tile_mode = stencil_tile_mode;
4778
4779 ds->db_depth_info |=
4780 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4781 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4782 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4783 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4784 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4785 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4786 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4787 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4788 } else {
4789 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4790 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4791 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4792 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4793 if (stencil_only)
4794 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4795 }
4796
4797 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4798 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4799 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4800
4801 if (radv_htile_enabled(iview->image, level)) {
4802 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4803
4804 if (!surf->has_stencil &&
4805 !radv_image_is_tc_compat_htile(iview->image))
4806 /* Use all of the htile_buffer for depth if there's no stencil. */
4807 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4808
4809 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4810 iview->image->htile_offset;
4811 ds->db_htile_data_base = va >> 8;
4812 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4813
4814 if (radv_image_is_tc_compat_htile(iview->image)) {
4815 unsigned max_zplanes =
4816 radv_calc_decompress_on_z_planes(device, iview);
4817
4818 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4819 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4820 }
4821 }
4822 }
4823
4824 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4825 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4826 }
4827
4828 VkResult radv_CreateFramebuffer(
4829 VkDevice _device,
4830 const VkFramebufferCreateInfo* pCreateInfo,
4831 const VkAllocationCallbacks* pAllocator,
4832 VkFramebuffer* pFramebuffer)
4833 {
4834 RADV_FROM_HANDLE(radv_device, device, _device);
4835 struct radv_framebuffer *framebuffer;
4836 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4837 vk_find_struct_const(pCreateInfo->pNext,
4838 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4839
4840 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4841
4842 size_t size = sizeof(*framebuffer);
4843 if (!imageless_create_info)
4844 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4845 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4846 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4847 if (framebuffer == NULL)
4848 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4849
4850 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4851 framebuffer->width = pCreateInfo->width;
4852 framebuffer->height = pCreateInfo->height;
4853 framebuffer->layers = pCreateInfo->layers;
4854 if (imageless_create_info) {
4855 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4856 const VkFramebufferAttachmentImageInfoKHR *attachment =
4857 imageless_create_info->pAttachmentImageInfos + i;
4858 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4859 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4860 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4861 }
4862 } else {
4863 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4864 VkImageView _iview = pCreateInfo->pAttachments[i];
4865 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4866 framebuffer->attachments[i] = iview;
4867 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4868 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4869 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4870 }
4871 }
4872
4873 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4874 return VK_SUCCESS;
4875 }
4876
4877 void radv_DestroyFramebuffer(
4878 VkDevice _device,
4879 VkFramebuffer _fb,
4880 const VkAllocationCallbacks* pAllocator)
4881 {
4882 RADV_FROM_HANDLE(radv_device, device, _device);
4883 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4884
4885 if (!fb)
4886 return;
4887 vk_free2(&device->alloc, pAllocator, fb);
4888 }
4889
4890 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4891 {
4892 switch (address_mode) {
4893 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4894 return V_008F30_SQ_TEX_WRAP;
4895 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4896 return V_008F30_SQ_TEX_MIRROR;
4897 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4898 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4899 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4900 return V_008F30_SQ_TEX_CLAMP_BORDER;
4901 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4902 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4903 default:
4904 unreachable("illegal tex wrap mode");
4905 break;
4906 }
4907 }
4908
4909 static unsigned
4910 radv_tex_compare(VkCompareOp op)
4911 {
4912 switch (op) {
4913 case VK_COMPARE_OP_NEVER:
4914 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4915 case VK_COMPARE_OP_LESS:
4916 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4917 case VK_COMPARE_OP_EQUAL:
4918 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4919 case VK_COMPARE_OP_LESS_OR_EQUAL:
4920 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4921 case VK_COMPARE_OP_GREATER:
4922 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4923 case VK_COMPARE_OP_NOT_EQUAL:
4924 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4925 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4926 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4927 case VK_COMPARE_OP_ALWAYS:
4928 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4929 default:
4930 unreachable("illegal compare mode");
4931 break;
4932 }
4933 }
4934
4935 static unsigned
4936 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4937 {
4938 switch (filter) {
4939 case VK_FILTER_NEAREST:
4940 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4941 V_008F38_SQ_TEX_XY_FILTER_POINT);
4942 case VK_FILTER_LINEAR:
4943 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4944 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4945 case VK_FILTER_CUBIC_IMG:
4946 default:
4947 fprintf(stderr, "illegal texture filter");
4948 return 0;
4949 }
4950 }
4951
4952 static unsigned
4953 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4954 {
4955 switch (mode) {
4956 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4957 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4958 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4959 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4960 default:
4961 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4962 }
4963 }
4964
4965 static unsigned
4966 radv_tex_bordercolor(VkBorderColor bcolor)
4967 {
4968 switch (bcolor) {
4969 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4970 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4971 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4972 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4973 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4974 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4975 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4976 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4977 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4978 default:
4979 break;
4980 }
4981 return 0;
4982 }
4983
4984 static unsigned
4985 radv_tex_aniso_filter(unsigned filter)
4986 {
4987 if (filter < 2)
4988 return 0;
4989 if (filter < 4)
4990 return 1;
4991 if (filter < 8)
4992 return 2;
4993 if (filter < 16)
4994 return 3;
4995 return 4;
4996 }
4997
4998 static unsigned
4999 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5000 {
5001 switch (mode) {
5002 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5003 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5004 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5005 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5006 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5007 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5008 default:
5009 break;
5010 }
5011 return 0;
5012 }
5013
5014 static uint32_t
5015 radv_get_max_anisotropy(struct radv_device *device,
5016 const VkSamplerCreateInfo *pCreateInfo)
5017 {
5018 if (device->force_aniso >= 0)
5019 return device->force_aniso;
5020
5021 if (pCreateInfo->anisotropyEnable &&
5022 pCreateInfo->maxAnisotropy > 1.0f)
5023 return (uint32_t)pCreateInfo->maxAnisotropy;
5024
5025 return 0;
5026 }
5027
5028 static void
5029 radv_init_sampler(struct radv_device *device,
5030 struct radv_sampler *sampler,
5031 const VkSamplerCreateInfo *pCreateInfo)
5032 {
5033 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5034 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5035 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5036 device->physical_device->rad_info.chip_class == GFX9;
5037 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5038
5039 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5040 vk_find_struct_const(pCreateInfo->pNext,
5041 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5042 if (sampler_reduction)
5043 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5044
5045 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5046 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5047 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5048 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5049 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5050 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5051 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5052 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5053 S_008F30_DISABLE_CUBE_WRAP(0) |
5054 S_008F30_COMPAT_MODE(compat_mode) |
5055 S_008F30_FILTER_MODE(filter_mode));
5056 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5057 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5058 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5059 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5060 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5061 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5062 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5063 S_008F38_MIP_POINT_PRECLAMP(0));
5064 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5065 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5066
5067 if (device->physical_device->rad_info.chip_class >= GFX10) {
5068 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5069 } else {
5070 sampler->state[2] |=
5071 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5072 S_008F38_FILTER_PREC_FIX(1) |
5073 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5074 }
5075 }
5076
5077 VkResult radv_CreateSampler(
5078 VkDevice _device,
5079 const VkSamplerCreateInfo* pCreateInfo,
5080 const VkAllocationCallbacks* pAllocator,
5081 VkSampler* pSampler)
5082 {
5083 RADV_FROM_HANDLE(radv_device, device, _device);
5084 struct radv_sampler *sampler;
5085
5086 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5087 vk_find_struct_const(pCreateInfo->pNext,
5088 SAMPLER_YCBCR_CONVERSION_INFO);
5089
5090 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5091
5092 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5093 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5094 if (!sampler)
5095 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5096
5097 radv_init_sampler(device, sampler, pCreateInfo);
5098
5099 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5100 *pSampler = radv_sampler_to_handle(sampler);
5101
5102 return VK_SUCCESS;
5103 }
5104
5105 void radv_DestroySampler(
5106 VkDevice _device,
5107 VkSampler _sampler,
5108 const VkAllocationCallbacks* pAllocator)
5109 {
5110 RADV_FROM_HANDLE(radv_device, device, _device);
5111 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5112
5113 if (!sampler)
5114 return;
5115 vk_free2(&device->alloc, pAllocator, sampler);
5116 }
5117
5118 /* vk_icd.h does not declare this function, so we declare it here to
5119 * suppress Wmissing-prototypes.
5120 */
5121 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5122 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5123
5124 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5125 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5126 {
5127 /* For the full details on loader interface versioning, see
5128 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5129 * What follows is a condensed summary, to help you navigate the large and
5130 * confusing official doc.
5131 *
5132 * - Loader interface v0 is incompatible with later versions. We don't
5133 * support it.
5134 *
5135 * - In loader interface v1:
5136 * - The first ICD entrypoint called by the loader is
5137 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5138 * entrypoint.
5139 * - The ICD must statically expose no other Vulkan symbol unless it is
5140 * linked with -Bsymbolic.
5141 * - Each dispatchable Vulkan handle created by the ICD must be
5142 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5143 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5144 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5145 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5146 * such loader-managed surfaces.
5147 *
5148 * - Loader interface v2 differs from v1 in:
5149 * - The first ICD entrypoint called by the loader is
5150 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5151 * statically expose this entrypoint.
5152 *
5153 * - Loader interface v3 differs from v2 in:
5154 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5155 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5156 * because the loader no longer does so.
5157 */
5158 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5159 return VK_SUCCESS;
5160 }
5161
5162 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5163 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5164 int *pFD)
5165 {
5166 RADV_FROM_HANDLE(radv_device, device, _device);
5167 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5168
5169 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5170
5171 /* At the moment, we support only the below handle types. */
5172 assert(pGetFdInfo->handleType ==
5173 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5174 pGetFdInfo->handleType ==
5175 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5176
5177 bool ret = radv_get_memory_fd(device, memory, pFD);
5178 if (ret == false)
5179 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5180 return VK_SUCCESS;
5181 }
5182
5183 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5184 VkExternalMemoryHandleTypeFlagBits handleType,
5185 int fd,
5186 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5187 {
5188 RADV_FROM_HANDLE(radv_device, device, _device);
5189
5190 switch (handleType) {
5191 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5192 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5193 return VK_SUCCESS;
5194
5195 default:
5196 /* The valid usage section for this function says:
5197 *
5198 * "handleType must not be one of the handle types defined as
5199 * opaque."
5200 *
5201 * So opaque handle types fall into the default "unsupported" case.
5202 */
5203 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5204 }
5205 }
5206
5207 static VkResult radv_import_opaque_fd(struct radv_device *device,
5208 int fd,
5209 uint32_t *syncobj)
5210 {
5211 uint32_t syncobj_handle = 0;
5212 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5213 if (ret != 0)
5214 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5215
5216 if (*syncobj)
5217 device->ws->destroy_syncobj(device->ws, *syncobj);
5218
5219 *syncobj = syncobj_handle;
5220 close(fd);
5221
5222 return VK_SUCCESS;
5223 }
5224
5225 static VkResult radv_import_sync_fd(struct radv_device *device,
5226 int fd,
5227 uint32_t *syncobj)
5228 {
5229 /* If we create a syncobj we do it locally so that if we have an error, we don't
5230 * leave a syncobj in an undetermined state in the fence. */
5231 uint32_t syncobj_handle = *syncobj;
5232 if (!syncobj_handle) {
5233 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5234 if (ret) {
5235 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5236 }
5237 }
5238
5239 if (fd == -1) {
5240 device->ws->signal_syncobj(device->ws, syncobj_handle);
5241 } else {
5242 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5243 if (ret != 0)
5244 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5245 }
5246
5247 *syncobj = syncobj_handle;
5248 if (fd != -1)
5249 close(fd);
5250
5251 return VK_SUCCESS;
5252 }
5253
5254 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5255 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5256 {
5257 RADV_FROM_HANDLE(radv_device, device, _device);
5258 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5259 uint32_t *syncobj_dst = NULL;
5260
5261 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5262 syncobj_dst = &sem->temp_syncobj;
5263 } else {
5264 syncobj_dst = &sem->syncobj;
5265 }
5266
5267 switch(pImportSemaphoreFdInfo->handleType) {
5268 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5269 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5270 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5271 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5272 default:
5273 unreachable("Unhandled semaphore handle type");
5274 }
5275 }
5276
5277 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5278 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5279 int *pFd)
5280 {
5281 RADV_FROM_HANDLE(radv_device, device, _device);
5282 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5283 int ret;
5284 uint32_t syncobj_handle;
5285
5286 if (sem->temp_syncobj)
5287 syncobj_handle = sem->temp_syncobj;
5288 else
5289 syncobj_handle = sem->syncobj;
5290
5291 switch(pGetFdInfo->handleType) {
5292 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5293 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5294 break;
5295 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5296 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5297 if (!ret) {
5298 if (sem->temp_syncobj) {
5299 close (sem->temp_syncobj);
5300 sem->temp_syncobj = 0;
5301 } else {
5302 device->ws->reset_syncobj(device->ws, syncobj_handle);
5303 }
5304 }
5305 break;
5306 default:
5307 unreachable("Unhandled semaphore handle type");
5308 }
5309
5310 if (ret)
5311 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5312 return VK_SUCCESS;
5313 }
5314
5315 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5316 VkPhysicalDevice physicalDevice,
5317 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5318 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5319 {
5320 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5321
5322 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5323 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5324 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5325 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5326 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5327 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5328 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5329 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5330 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5331 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5332 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5333 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5334 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5335 } else {
5336 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5337 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5338 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5339 }
5340 }
5341
5342 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5343 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5344 {
5345 RADV_FROM_HANDLE(radv_device, device, _device);
5346 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5347 uint32_t *syncobj_dst = NULL;
5348
5349
5350 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5351 syncobj_dst = &fence->temp_syncobj;
5352 } else {
5353 syncobj_dst = &fence->syncobj;
5354 }
5355
5356 switch(pImportFenceFdInfo->handleType) {
5357 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5358 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5359 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5360 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5361 default:
5362 unreachable("Unhandled fence handle type");
5363 }
5364 }
5365
5366 VkResult radv_GetFenceFdKHR(VkDevice _device,
5367 const VkFenceGetFdInfoKHR *pGetFdInfo,
5368 int *pFd)
5369 {
5370 RADV_FROM_HANDLE(radv_device, device, _device);
5371 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5372 int ret;
5373 uint32_t syncobj_handle;
5374
5375 if (fence->temp_syncobj)
5376 syncobj_handle = fence->temp_syncobj;
5377 else
5378 syncobj_handle = fence->syncobj;
5379
5380 switch(pGetFdInfo->handleType) {
5381 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5382 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5383 break;
5384 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5385 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5386 if (!ret) {
5387 if (fence->temp_syncobj) {
5388 close (fence->temp_syncobj);
5389 fence->temp_syncobj = 0;
5390 } else {
5391 device->ws->reset_syncobj(device->ws, syncobj_handle);
5392 }
5393 }
5394 break;
5395 default:
5396 unreachable("Unhandled fence handle type");
5397 }
5398
5399 if (ret)
5400 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5401 return VK_SUCCESS;
5402 }
5403
5404 void radv_GetPhysicalDeviceExternalFenceProperties(
5405 VkPhysicalDevice physicalDevice,
5406 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5407 VkExternalFenceProperties *pExternalFenceProperties)
5408 {
5409 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5410
5411 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5412 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5413 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5414 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5415 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5416 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5417 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5418 } else {
5419 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5420 pExternalFenceProperties->compatibleHandleTypes = 0;
5421 pExternalFenceProperties->externalFenceFeatures = 0;
5422 }
5423 }
5424
5425 VkResult
5426 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5427 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5428 const VkAllocationCallbacks* pAllocator,
5429 VkDebugReportCallbackEXT* pCallback)
5430 {
5431 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5432 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5433 pCreateInfo, pAllocator, &instance->alloc,
5434 pCallback);
5435 }
5436
5437 void
5438 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5439 VkDebugReportCallbackEXT _callback,
5440 const VkAllocationCallbacks* pAllocator)
5441 {
5442 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5443 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5444 _callback, pAllocator, &instance->alloc);
5445 }
5446
5447 void
5448 radv_DebugReportMessageEXT(VkInstance _instance,
5449 VkDebugReportFlagsEXT flags,
5450 VkDebugReportObjectTypeEXT objectType,
5451 uint64_t object,
5452 size_t location,
5453 int32_t messageCode,
5454 const char* pLayerPrefix,
5455 const char* pMessage)
5456 {
5457 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5458 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5459 object, location, messageCode, pLayerPrefix, pMessage);
5460 }
5461
5462 void
5463 radv_GetDeviceGroupPeerMemoryFeatures(
5464 VkDevice device,
5465 uint32_t heapIndex,
5466 uint32_t localDeviceIndex,
5467 uint32_t remoteDeviceIndex,
5468 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5469 {
5470 assert(localDeviceIndex == remoteDeviceIndex);
5471
5472 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5473 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5474 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5475 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5476 }
5477
5478 static const VkTimeDomainEXT radv_time_domains[] = {
5479 VK_TIME_DOMAIN_DEVICE_EXT,
5480 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5481 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5482 };
5483
5484 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5485 VkPhysicalDevice physicalDevice,
5486 uint32_t *pTimeDomainCount,
5487 VkTimeDomainEXT *pTimeDomains)
5488 {
5489 int d;
5490 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5491
5492 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5493 vk_outarray_append(&out, i) {
5494 *i = radv_time_domains[d];
5495 }
5496 }
5497
5498 return vk_outarray_status(&out);
5499 }
5500
5501 static uint64_t
5502 radv_clock_gettime(clockid_t clock_id)
5503 {
5504 struct timespec current;
5505 int ret;
5506
5507 ret = clock_gettime(clock_id, &current);
5508 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5509 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5510 if (ret < 0)
5511 return 0;
5512
5513 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5514 }
5515
5516 VkResult radv_GetCalibratedTimestampsEXT(
5517 VkDevice _device,
5518 uint32_t timestampCount,
5519 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5520 uint64_t *pTimestamps,
5521 uint64_t *pMaxDeviation)
5522 {
5523 RADV_FROM_HANDLE(radv_device, device, _device);
5524 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5525 int d;
5526 uint64_t begin, end;
5527 uint64_t max_clock_period = 0;
5528
5529 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5530
5531 for (d = 0; d < timestampCount; d++) {
5532 switch (pTimestampInfos[d].timeDomain) {
5533 case VK_TIME_DOMAIN_DEVICE_EXT:
5534 pTimestamps[d] = device->ws->query_value(device->ws,
5535 RADEON_TIMESTAMP);
5536 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5537 max_clock_period = MAX2(max_clock_period, device_period);
5538 break;
5539 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5540 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5541 max_clock_period = MAX2(max_clock_period, 1);
5542 break;
5543
5544 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5545 pTimestamps[d] = begin;
5546 break;
5547 default:
5548 pTimestamps[d] = 0;
5549 break;
5550 }
5551 }
5552
5553 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5554
5555 /*
5556 * The maximum deviation is the sum of the interval over which we
5557 * perform the sampling and the maximum period of any sampled
5558 * clock. That's because the maximum skew between any two sampled
5559 * clock edges is when the sampled clock with the largest period is
5560 * sampled at the end of that period but right at the beginning of the
5561 * sampling interval and some other clock is sampled right at the
5562 * begining of its sampling period and right at the end of the
5563 * sampling interval. Let's assume the GPU has the longest clock
5564 * period and that the application is sampling GPU and monotonic:
5565 *
5566 * s e
5567 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5568 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5569 *
5570 * g
5571 * 0 1 2 3
5572 * GPU -----_____-----_____-----_____-----_____
5573 *
5574 * m
5575 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5576 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5577 *
5578 * Interval <----------------->
5579 * Deviation <-------------------------->
5580 *
5581 * s = read(raw) 2
5582 * g = read(GPU) 1
5583 * m = read(monotonic) 2
5584 * e = read(raw) b
5585 *
5586 * We round the sample interval up by one tick to cover sampling error
5587 * in the interval clock
5588 */
5589
5590 uint64_t sample_interval = end - begin + 1;
5591
5592 *pMaxDeviation = sample_interval + max_clock_period;
5593
5594 return VK_SUCCESS;
5595 }
5596
5597 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5598 VkPhysicalDevice physicalDevice,
5599 VkSampleCountFlagBits samples,
5600 VkMultisamplePropertiesEXT* pMultisampleProperties)
5601 {
5602 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5603 VK_SAMPLE_COUNT_4_BIT |
5604 VK_SAMPLE_COUNT_8_BIT)) {
5605 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5606 } else {
5607 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5608 }
5609 }