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radv: fix tile swizzle regression on mipmaps.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 {
102 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 {
106 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
107 .specVersion = 1,
108 },
109 };
110
111 static const VkExtensionProperties common_device_extensions[] = {
112 {
113 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
134 .specVersion = 68,
135 },
136 {
137 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 {
161 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
162 .specVersion = 1,
163 },
164 {
165 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
166 .specVersion = 1,
167 },
168 };
169 static const VkExtensionProperties ext_sema_device_extensions[] = {
170 {
171 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
172 .specVersion = 1,
173 },
174 {
175 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
176 .specVersion = 1,
177 },
178 };
179
180 static VkResult
181 radv_extensions_register(struct radv_instance *instance,
182 struct radv_extensions *extensions,
183 const VkExtensionProperties *new_ext,
184 uint32_t num_ext)
185 {
186 size_t new_size;
187 VkExtensionProperties *new_ptr;
188
189 assert(new_ext && num_ext > 0);
190
191 if (!new_ext)
192 return VK_ERROR_INITIALIZATION_FAILED;
193
194 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
195 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
196 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
197
198 /* Old array continues to be valid, update nothing */
199 if (!new_ptr)
200 return VK_ERROR_OUT_OF_HOST_MEMORY;
201
202 memcpy(&new_ptr[extensions->num_ext], new_ext,
203 num_ext * sizeof(VkExtensionProperties));
204 extensions->ext_array = new_ptr;
205 extensions->num_ext += num_ext;
206
207 return VK_SUCCESS;
208 }
209
210 static void
211 radv_extensions_finish(struct radv_instance *instance,
212 struct radv_extensions *extensions)
213 {
214 assert(extensions);
215
216 if (!extensions)
217 radv_loge("Attemted to free invalid extension struct\n");
218
219 if (extensions->ext_array)
220 vk_free(&instance->alloc, extensions->ext_array);
221 }
222
223 static bool
224 is_extension_enabled(const VkExtensionProperties *extensions,
225 size_t num_ext,
226 const char *name)
227 {
228 assert(extensions && name);
229
230 for (uint32_t i = 0; i < num_ext; i++) {
231 if (strcmp(name, extensions[i].extensionName) == 0)
232 return true;
233 }
234
235 return false;
236 }
237
238 static const char *
239 get_chip_name(enum radeon_family family)
240 {
241 switch (family) {
242 case CHIP_TAHITI: return "AMD RADV TAHITI";
243 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
244 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
245 case CHIP_OLAND: return "AMD RADV OLAND";
246 case CHIP_HAINAN: return "AMD RADV HAINAN";
247 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
248 case CHIP_KAVERI: return "AMD RADV KAVERI";
249 case CHIP_KABINI: return "AMD RADV KABINI";
250 case CHIP_HAWAII: return "AMD RADV HAWAII";
251 case CHIP_MULLINS: return "AMD RADV MULLINS";
252 case CHIP_TONGA: return "AMD RADV TONGA";
253 case CHIP_ICELAND: return "AMD RADV ICELAND";
254 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
255 case CHIP_FIJI: return "AMD RADV FIJI";
256 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
257 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
258 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
259 case CHIP_STONEY: return "AMD RADV STONEY";
260 case CHIP_VEGA10: return "AMD RADV VEGA";
261 case CHIP_RAVEN: return "AMD RADV RAVEN";
262 default: return "AMD RADV unknown";
263 }
264 }
265
266 static VkResult
267 radv_physical_device_init(struct radv_physical_device *device,
268 struct radv_instance *instance,
269 drmDevicePtr drm_device)
270 {
271 const char *path = drm_device->nodes[DRM_NODE_RENDER];
272 VkResult result;
273 drmVersionPtr version;
274 int fd;
275
276 fd = open(path, O_RDWR | O_CLOEXEC);
277 if (fd < 0)
278 return VK_ERROR_INCOMPATIBLE_DRIVER;
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
284 "failed to get version %s: %m", path);
285 }
286
287 if (strcmp(version->name, "amdgpu")) {
288 drmFreeVersion(version);
289 close(fd);
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
295 device->instance = instance;
296 assert(strlen(path) < ARRAY_SIZE(device->path));
297 strncpy(device->path, path, ARRAY_SIZE(device->path));
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = VK_ERROR_INCOMPATIBLE_DRIVER;
303 goto fail;
304 }
305
306 device->local_fd = fd;
307 device->ws->query_info(device->ws, &device->rad_info);
308 result = radv_init_wsi(device);
309 if (result != VK_SUCCESS) {
310 device->ws->destroy(device->ws);
311 goto fail;
312 }
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 radv_finish_wsi(device);
316 device->ws->destroy(device->ws);
317 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 result = radv_extensions_register(instance,
323 &device->extensions,
324 common_device_extensions,
325 ARRAY_SIZE(common_device_extensions));
326 if (result != VK_SUCCESS)
327 goto fail;
328
329 if (device->rad_info.has_syncobj) {
330 result = radv_extensions_register(instance,
331 &device->extensions,
332 ext_sema_device_extensions,
333 ARRAY_SIZE(ext_sema_device_extensions));
334 if (result != VK_SUCCESS)
335 goto fail;
336 }
337
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 device->name = get_chip_name(device->rad_info.family);
340
341 radv_get_device_uuid(drm_device, device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
347 }
348
349 return VK_SUCCESS;
350
351 fail:
352 close(fd);
353 return result;
354 }
355
356 static void
357 radv_physical_device_finish(struct radv_physical_device *device)
358 {
359 radv_extensions_finish(device->instance, &device->extensions);
360 radv_finish_wsi(device);
361 device->ws->destroy(device->ws);
362 close(device->local_fd);
363 }
364
365 static void *
366 default_alloc_func(void *pUserData, size_t size, size_t align,
367 VkSystemAllocationScope allocationScope)
368 {
369 return malloc(size);
370 }
371
372 static void *
373 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
374 size_t align, VkSystemAllocationScope allocationScope)
375 {
376 return realloc(pOriginal, size);
377 }
378
379 static void
380 default_free_func(void *pUserData, void *pMemory)
381 {
382 free(pMemory);
383 }
384
385 static const VkAllocationCallbacks default_alloc = {
386 .pUserData = NULL,
387 .pfnAllocation = default_alloc_func,
388 .pfnReallocation = default_realloc_func,
389 .pfnFree = default_free_func,
390 };
391
392 static const struct debug_control radv_debug_options[] = {
393 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
394 {"nodcc", RADV_DEBUG_NO_DCC},
395 {"shaders", RADV_DEBUG_DUMP_SHADERS},
396 {"nocache", RADV_DEBUG_NO_CACHE},
397 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
398 {"nohiz", RADV_DEBUG_NO_HIZ},
399 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
400 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
401 {"allbos", RADV_DEBUG_ALL_BOS},
402 {"noibs", RADV_DEBUG_NO_IBS},
403 {NULL, 0}
404 };
405
406 static const struct debug_control radv_perftest_options[] = {
407 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
408 {"sisched", RADV_PERFTEST_SISCHED},
409 {NULL, 0}
410 };
411
412 VkResult radv_CreateInstance(
413 const VkInstanceCreateInfo* pCreateInfo,
414 const VkAllocationCallbacks* pAllocator,
415 VkInstance* pInstance)
416 {
417 struct radv_instance *instance;
418
419 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
420
421 uint32_t client_version;
422 if (pCreateInfo->pApplicationInfo &&
423 pCreateInfo->pApplicationInfo->apiVersion != 0) {
424 client_version = pCreateInfo->pApplicationInfo->apiVersion;
425 } else {
426 client_version = VK_MAKE_VERSION(1, 0, 0);
427 }
428
429 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
430 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
431 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
432 "Client requested version %d.%d.%d",
433 VK_VERSION_MAJOR(client_version),
434 VK_VERSION_MINOR(client_version),
435 VK_VERSION_PATCH(client_version));
436 }
437
438 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
439 if (!is_extension_enabled(instance_extensions,
440 ARRAY_SIZE(instance_extensions),
441 pCreateInfo->ppEnabledExtensionNames[i]))
442 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
443 }
444
445 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
446 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
447 if (!instance)
448 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
449
450 memset(instance, 0, sizeof(*instance));
451
452 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
453
454 if (pAllocator)
455 instance->alloc = *pAllocator;
456 else
457 instance->alloc = default_alloc;
458
459 instance->apiVersion = client_version;
460 instance->physicalDeviceCount = -1;
461
462 _mesa_locale_init();
463
464 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
465
466 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
467 radv_debug_options);
468
469 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
470 radv_perftest_options);
471
472 *pInstance = radv_instance_to_handle(instance);
473
474 return VK_SUCCESS;
475 }
476
477 void radv_DestroyInstance(
478 VkInstance _instance,
479 const VkAllocationCallbacks* pAllocator)
480 {
481 RADV_FROM_HANDLE(radv_instance, instance, _instance);
482
483 if (!instance)
484 return;
485
486 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
487 radv_physical_device_finish(instance->physicalDevices + i);
488 }
489
490 VG(VALGRIND_DESTROY_MEMPOOL(instance));
491
492 _mesa_locale_fini();
493
494 vk_free(&instance->alloc, instance);
495 }
496
497 static VkResult
498 radv_enumerate_devices(struct radv_instance *instance)
499 {
500 /* TODO: Check for more devices ? */
501 drmDevicePtr devices[8];
502 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
503 int max_devices;
504
505 instance->physicalDeviceCount = 0;
506
507 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
508 if (max_devices < 1)
509 return VK_ERROR_INCOMPATIBLE_DRIVER;
510
511 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
512 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
513 devices[i]->bustype == DRM_BUS_PCI &&
514 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
515
516 result = radv_physical_device_init(instance->physicalDevices +
517 instance->physicalDeviceCount,
518 instance,
519 devices[i]);
520 if (result == VK_SUCCESS)
521 ++instance->physicalDeviceCount;
522 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
523 break;
524 }
525 }
526 drmFreeDevices(devices, max_devices);
527
528 return result;
529 }
530
531 VkResult radv_EnumeratePhysicalDevices(
532 VkInstance _instance,
533 uint32_t* pPhysicalDeviceCount,
534 VkPhysicalDevice* pPhysicalDevices)
535 {
536 RADV_FROM_HANDLE(radv_instance, instance, _instance);
537 VkResult result;
538
539 if (instance->physicalDeviceCount < 0) {
540 result = radv_enumerate_devices(instance);
541 if (result != VK_SUCCESS &&
542 result != VK_ERROR_INCOMPATIBLE_DRIVER)
543 return result;
544 }
545
546 if (!pPhysicalDevices) {
547 *pPhysicalDeviceCount = instance->physicalDeviceCount;
548 } else {
549 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
550 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
551 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
552 }
553
554 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
555 : VK_SUCCESS;
556 }
557
558 void radv_GetPhysicalDeviceFeatures(
559 VkPhysicalDevice physicalDevice,
560 VkPhysicalDeviceFeatures* pFeatures)
561 {
562 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
563 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
564 memset(pFeatures, 0, sizeof(*pFeatures));
565
566 *pFeatures = (VkPhysicalDeviceFeatures) {
567 .robustBufferAccess = true,
568 .fullDrawIndexUint32 = true,
569 .imageCubeArray = true,
570 .independentBlend = true,
571 .geometryShader = !is_gfx9,
572 .tessellationShader = !is_gfx9,
573 .sampleRateShading = true,
574 .dualSrcBlend = true,
575 .logicOp = true,
576 .multiDrawIndirect = true,
577 .drawIndirectFirstInstance = true,
578 .depthClamp = true,
579 .depthBiasClamp = true,
580 .fillModeNonSolid = true,
581 .depthBounds = true,
582 .wideLines = true,
583 .largePoints = true,
584 .alphaToOne = true,
585 .multiViewport = true,
586 .samplerAnisotropy = true,
587 .textureCompressionETC2 = false,
588 .textureCompressionASTC_LDR = false,
589 .textureCompressionBC = true,
590 .occlusionQueryPrecise = true,
591 .pipelineStatisticsQuery = true,
592 .vertexPipelineStoresAndAtomics = true,
593 .fragmentStoresAndAtomics = true,
594 .shaderTessellationAndGeometryPointSize = true,
595 .shaderImageGatherExtended = true,
596 .shaderStorageImageExtendedFormats = true,
597 .shaderStorageImageMultisample = false,
598 .shaderUniformBufferArrayDynamicIndexing = true,
599 .shaderSampledImageArrayDynamicIndexing = true,
600 .shaderStorageBufferArrayDynamicIndexing = true,
601 .shaderStorageImageArrayDynamicIndexing = true,
602 .shaderStorageImageReadWithoutFormat = true,
603 .shaderStorageImageWriteWithoutFormat = true,
604 .shaderClipDistance = true,
605 .shaderCullDistance = true,
606 .shaderFloat64 = true,
607 .shaderInt64 = true,
608 .shaderInt16 = false,
609 .sparseBinding = true,
610 .variableMultisampleRate = true,
611 .inheritedQueries = true,
612 };
613 }
614
615 void radv_GetPhysicalDeviceFeatures2KHR(
616 VkPhysicalDevice physicalDevice,
617 VkPhysicalDeviceFeatures2KHR *pFeatures)
618 {
619 vk_foreach_struct(ext, pFeatures->pNext) {
620 switch (ext->sType) {
621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
622 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
623 features->variablePointersStorageBuffer = true;
624 features->variablePointers = false;
625 break;
626 }
627 default:
628 break;
629 }
630 }
631 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
632 }
633
634 void radv_GetPhysicalDeviceProperties(
635 VkPhysicalDevice physicalDevice,
636 VkPhysicalDeviceProperties* pProperties)
637 {
638 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
639 VkSampleCountFlags sample_counts = 0xf;
640
641 /* make sure that the entire descriptor set is addressable with a signed
642 * 32-bit int. So the sum of all limits scaled by descriptor size has to
643 * be at most 2 GiB. the combined image & samples object count as one of
644 * both. This limit is for the pipeline layout, not for the set layout, but
645 * there is no set limit, so we just set a pipeline limit. I don't think
646 * any app is going to hit this soon. */
647 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
648 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
649 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
650 32 /* sampler, largest when combined with image */ +
651 64 /* sampled image */ +
652 64 /* storage image */);
653
654 VkPhysicalDeviceLimits limits = {
655 .maxImageDimension1D = (1 << 14),
656 .maxImageDimension2D = (1 << 14),
657 .maxImageDimension3D = (1 << 11),
658 .maxImageDimensionCube = (1 << 14),
659 .maxImageArrayLayers = (1 << 11),
660 .maxTexelBufferElements = 128 * 1024 * 1024,
661 .maxUniformBufferRange = UINT32_MAX,
662 .maxStorageBufferRange = UINT32_MAX,
663 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
664 .maxMemoryAllocationCount = UINT32_MAX,
665 .maxSamplerAllocationCount = 64 * 1024,
666 .bufferImageGranularity = 64, /* A cache line */
667 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
668 .maxBoundDescriptorSets = MAX_SETS,
669 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
670 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
671 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
672 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
673 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
674 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
675 .maxPerStageResources = max_descriptor_set_size,
676 .maxDescriptorSetSamplers = max_descriptor_set_size,
677 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
678 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
679 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
680 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
681 .maxDescriptorSetSampledImages = max_descriptor_set_size,
682 .maxDescriptorSetStorageImages = max_descriptor_set_size,
683 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
684 .maxVertexInputAttributes = 32,
685 .maxVertexInputBindings = 32,
686 .maxVertexInputAttributeOffset = 2047,
687 .maxVertexInputBindingStride = 2048,
688 .maxVertexOutputComponents = 128,
689 .maxTessellationGenerationLevel = 64,
690 .maxTessellationPatchSize = 32,
691 .maxTessellationControlPerVertexInputComponents = 128,
692 .maxTessellationControlPerVertexOutputComponents = 128,
693 .maxTessellationControlPerPatchOutputComponents = 120,
694 .maxTessellationControlTotalOutputComponents = 4096,
695 .maxTessellationEvaluationInputComponents = 128,
696 .maxTessellationEvaluationOutputComponents = 128,
697 .maxGeometryShaderInvocations = 127,
698 .maxGeometryInputComponents = 64,
699 .maxGeometryOutputComponents = 128,
700 .maxGeometryOutputVertices = 256,
701 .maxGeometryTotalOutputComponents = 1024,
702 .maxFragmentInputComponents = 128,
703 .maxFragmentOutputAttachments = 8,
704 .maxFragmentDualSrcAttachments = 1,
705 .maxFragmentCombinedOutputResources = 8,
706 .maxComputeSharedMemorySize = 32768,
707 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
708 .maxComputeWorkGroupInvocations = 2048,
709 .maxComputeWorkGroupSize = {
710 2048,
711 2048,
712 2048
713 },
714 .subPixelPrecisionBits = 4 /* FIXME */,
715 .subTexelPrecisionBits = 4 /* FIXME */,
716 .mipmapPrecisionBits = 4 /* FIXME */,
717 .maxDrawIndexedIndexValue = UINT32_MAX,
718 .maxDrawIndirectCount = UINT32_MAX,
719 .maxSamplerLodBias = 16,
720 .maxSamplerAnisotropy = 16,
721 .maxViewports = MAX_VIEWPORTS,
722 .maxViewportDimensions = { (1 << 14), (1 << 14) },
723 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
724 .viewportSubPixelBits = 13, /* We take a float? */
725 .minMemoryMapAlignment = 4096, /* A page */
726 .minTexelBufferOffsetAlignment = 1,
727 .minUniformBufferOffsetAlignment = 4,
728 .minStorageBufferOffsetAlignment = 4,
729 .minTexelOffset = -32,
730 .maxTexelOffset = 31,
731 .minTexelGatherOffset = -32,
732 .maxTexelGatherOffset = 31,
733 .minInterpolationOffset = -2,
734 .maxInterpolationOffset = 2,
735 .subPixelInterpolationOffsetBits = 8,
736 .maxFramebufferWidth = (1 << 14),
737 .maxFramebufferHeight = (1 << 14),
738 .maxFramebufferLayers = (1 << 10),
739 .framebufferColorSampleCounts = sample_counts,
740 .framebufferDepthSampleCounts = sample_counts,
741 .framebufferStencilSampleCounts = sample_counts,
742 .framebufferNoAttachmentsSampleCounts = sample_counts,
743 .maxColorAttachments = MAX_RTS,
744 .sampledImageColorSampleCounts = sample_counts,
745 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
746 .sampledImageDepthSampleCounts = sample_counts,
747 .sampledImageStencilSampleCounts = sample_counts,
748 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
749 .maxSampleMaskWords = 1,
750 .timestampComputeAndGraphics = true,
751 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
752 .maxClipDistances = 8,
753 .maxCullDistances = 8,
754 .maxCombinedClipAndCullDistances = 8,
755 .discreteQueuePriorities = 1,
756 .pointSizeRange = { 0.125, 255.875 },
757 .lineWidthRange = { 0.0, 7.9921875 },
758 .pointSizeGranularity = (1.0 / 8.0),
759 .lineWidthGranularity = (1.0 / 128.0),
760 .strictLines = false, /* FINISHME */
761 .standardSampleLocations = true,
762 .optimalBufferCopyOffsetAlignment = 128,
763 .optimalBufferCopyRowPitchAlignment = 128,
764 .nonCoherentAtomSize = 64,
765 };
766
767 *pProperties = (VkPhysicalDeviceProperties) {
768 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
769 .driverVersion = vk_get_driver_version(),
770 .vendorID = 0x1002,
771 .deviceID = pdevice->rad_info.pci_id,
772 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
773 .limits = limits,
774 .sparseProperties = {0},
775 };
776
777 strcpy(pProperties->deviceName, pdevice->name);
778 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
779 }
780
781 void radv_GetPhysicalDeviceProperties2KHR(
782 VkPhysicalDevice physicalDevice,
783 VkPhysicalDeviceProperties2KHR *pProperties)
784 {
785 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
786 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
787
788 vk_foreach_struct(ext, pProperties->pNext) {
789 switch (ext->sType) {
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
791 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
792 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
793 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
797 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
798 radv_device_get_cache_uuid(0, properties->driverUUID);
799 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
800 properties->deviceLUIDValid = false;
801 break;
802 }
803 default:
804 break;
805 }
806 }
807 }
808
809 static void radv_get_physical_device_queue_family_properties(
810 struct radv_physical_device* pdevice,
811 uint32_t* pCount,
812 VkQueueFamilyProperties** pQueueFamilyProperties)
813 {
814 int num_queue_families = 1;
815 int idx;
816 if (pdevice->rad_info.num_compute_rings > 0 &&
817 pdevice->rad_info.chip_class >= CIK &&
818 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
819 num_queue_families++;
820
821 if (pQueueFamilyProperties == NULL) {
822 *pCount = num_queue_families;
823 return;
824 }
825
826 if (!*pCount)
827 return;
828
829 idx = 0;
830 if (*pCount >= 1) {
831 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
832 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
833 VK_QUEUE_COMPUTE_BIT |
834 VK_QUEUE_TRANSFER_BIT |
835 VK_QUEUE_SPARSE_BINDING_BIT,
836 .queueCount = 1,
837 .timestampValidBits = 64,
838 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
839 };
840 idx++;
841 }
842
843 if (pdevice->rad_info.num_compute_rings > 0 &&
844 pdevice->rad_info.chip_class >= CIK &&
845 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
846 if (*pCount > idx) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_COMPUTE_BIT |
849 VK_QUEUE_TRANSFER_BIT |
850 VK_QUEUE_SPARSE_BINDING_BIT,
851 .queueCount = pdevice->rad_info.num_compute_rings,
852 .timestampValidBits = 64,
853 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
854 };
855 idx++;
856 }
857 }
858 *pCount = idx;
859 }
860
861 void radv_GetPhysicalDeviceQueueFamilyProperties(
862 VkPhysicalDevice physicalDevice,
863 uint32_t* pCount,
864 VkQueueFamilyProperties* pQueueFamilyProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 if (!pQueueFamilyProperties) {
868 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
869 return;
870 }
871 VkQueueFamilyProperties *properties[] = {
872 pQueueFamilyProperties + 0,
873 pQueueFamilyProperties + 1,
874 pQueueFamilyProperties + 2,
875 };
876 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
877 assert(*pCount <= 3);
878 }
879
880 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
881 VkPhysicalDevice physicalDevice,
882 uint32_t* pCount,
883 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 if (!pQueueFamilyProperties) {
887 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
888 return;
889 }
890 VkQueueFamilyProperties *properties[] = {
891 &pQueueFamilyProperties[0].queueFamilyProperties,
892 &pQueueFamilyProperties[1].queueFamilyProperties,
893 &pQueueFamilyProperties[2].queueFamilyProperties,
894 };
895 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
896 assert(*pCount <= 3);
897 }
898
899 void radv_GetPhysicalDeviceMemoryProperties(
900 VkPhysicalDevice physicalDevice,
901 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
902 {
903 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
904
905 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
906
907 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
908 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
909 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
910 .heapIndex = RADV_MEM_HEAP_VRAM,
911 };
912 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
913 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
914 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
915 .heapIndex = RADV_MEM_HEAP_GTT,
916 };
917 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
918 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
919 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
920 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
921 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
922 };
923 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
924 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
925 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
926 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
927 .heapIndex = RADV_MEM_HEAP_GTT,
928 };
929
930 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
931 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
932 physical_device->rad_info.vram_vis_size);
933
934 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
935 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
936 .size = physical_device->rad_info.vram_size -
937 visible_vram_size,
938 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
939 };
940 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
941 .size = visible_vram_size,
942 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
943 };
944 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
945 .size = physical_device->rad_info.gart_size,
946 .flags = 0,
947 };
948 }
949
950 void radv_GetPhysicalDeviceMemoryProperties2KHR(
951 VkPhysicalDevice physicalDevice,
952 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
953 {
954 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
955 &pMemoryProperties->memoryProperties);
956 }
957
958 static int
959 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
960 int queue_family_index, int idx)
961 {
962 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
963 queue->device = device;
964 queue->queue_family_index = queue_family_index;
965 queue->queue_idx = idx;
966
967 queue->hw_ctx = device->ws->ctx_create(device->ws);
968 if (!queue->hw_ctx)
969 return VK_ERROR_OUT_OF_HOST_MEMORY;
970
971 return VK_SUCCESS;
972 }
973
974 static void
975 radv_queue_finish(struct radv_queue *queue)
976 {
977 if (queue->hw_ctx)
978 queue->device->ws->ctx_destroy(queue->hw_ctx);
979
980 if (queue->initial_preamble_cs)
981 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
982 if (queue->continue_preamble_cs)
983 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
984 if (queue->descriptor_bo)
985 queue->device->ws->buffer_destroy(queue->descriptor_bo);
986 if (queue->scratch_bo)
987 queue->device->ws->buffer_destroy(queue->scratch_bo);
988 if (queue->esgs_ring_bo)
989 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
990 if (queue->gsvs_ring_bo)
991 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
992 if (queue->tess_factor_ring_bo)
993 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
994 if (queue->tess_offchip_ring_bo)
995 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
996 if (queue->compute_scratch_bo)
997 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
998 }
999
1000 static void
1001 radv_device_init_gs_info(struct radv_device *device)
1002 {
1003 switch (device->physical_device->rad_info.family) {
1004 case CHIP_OLAND:
1005 case CHIP_HAINAN:
1006 case CHIP_KAVERI:
1007 case CHIP_KABINI:
1008 case CHIP_MULLINS:
1009 case CHIP_ICELAND:
1010 case CHIP_CARRIZO:
1011 case CHIP_STONEY:
1012 device->gs_table_depth = 16;
1013 return;
1014 case CHIP_TAHITI:
1015 case CHIP_PITCAIRN:
1016 case CHIP_VERDE:
1017 case CHIP_BONAIRE:
1018 case CHIP_HAWAII:
1019 case CHIP_TONGA:
1020 case CHIP_FIJI:
1021 case CHIP_POLARIS10:
1022 case CHIP_POLARIS11:
1023 case CHIP_POLARIS12:
1024 case CHIP_VEGA10:
1025 case CHIP_RAVEN:
1026 device->gs_table_depth = 32;
1027 return;
1028 default:
1029 unreachable("unknown GPU");
1030 }
1031 }
1032
1033 VkResult radv_CreateDevice(
1034 VkPhysicalDevice physicalDevice,
1035 const VkDeviceCreateInfo* pCreateInfo,
1036 const VkAllocationCallbacks* pAllocator,
1037 VkDevice* pDevice)
1038 {
1039 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1040 VkResult result;
1041 struct radv_device *device;
1042
1043 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1044 if (!is_extension_enabled(physical_device->extensions.ext_array,
1045 physical_device->extensions.num_ext,
1046 pCreateInfo->ppEnabledExtensionNames[i]))
1047 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1048 }
1049
1050 /* Check enabled features */
1051 if (pCreateInfo->pEnabledFeatures) {
1052 VkPhysicalDeviceFeatures supported_features;
1053 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1054 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1055 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1056 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1057 for (uint32_t i = 0; i < num_features; i++) {
1058 if (enabled_feature[i] && !supported_feature[i])
1059 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1060 }
1061 }
1062
1063 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1064 sizeof(*device), 8,
1065 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1066 if (!device)
1067 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1068
1069 memset(device, 0, sizeof(*device));
1070
1071 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1072 device->instance = physical_device->instance;
1073 device->physical_device = physical_device;
1074
1075 device->debug_flags = device->instance->debug_flags;
1076
1077 device->ws = physical_device->ws;
1078 if (pAllocator)
1079 device->alloc = *pAllocator;
1080 else
1081 device->alloc = physical_device->instance->alloc;
1082
1083 mtx_init(&device->shader_slab_mutex, mtx_plain);
1084 list_inithead(&device->shader_slabs);
1085
1086 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1087 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1088 uint32_t qfi = queue_create->queueFamilyIndex;
1089
1090 device->queues[qfi] = vk_alloc(&device->alloc,
1091 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1092 if (!device->queues[qfi]) {
1093 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1094 goto fail;
1095 }
1096
1097 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1098
1099 device->queue_count[qfi] = queue_create->queueCount;
1100
1101 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1102 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1103 if (result != VK_SUCCESS)
1104 goto fail;
1105 }
1106 }
1107
1108 #if HAVE_LLVM < 0x0400
1109 device->llvm_supports_spill = false;
1110 #else
1111 device->llvm_supports_spill = true;
1112 #endif
1113
1114 /* The maximum number of scratch waves. Scratch space isn't divided
1115 * evenly between CUs. The number is only a function of the number of CUs.
1116 * We can decrease the constant to decrease the scratch buffer size.
1117 *
1118 * sctx->scratch_waves must be >= the maximum posible size of
1119 * 1 threadgroup, so that the hw doesn't hang from being unable
1120 * to start any.
1121 *
1122 * The recommended value is 4 per CU at most. Higher numbers don't
1123 * bring much benefit, but they still occupy chip resources (think
1124 * async compute). I've seen ~2% performance difference between 4 and 32.
1125 */
1126 uint32_t max_threads_per_block = 2048;
1127 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1128 max_threads_per_block / 64);
1129
1130 radv_device_init_gs_info(device);
1131
1132 device->tess_offchip_block_dw_size =
1133 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1134 device->has_distributed_tess =
1135 device->physical_device->rad_info.chip_class >= VI &&
1136 device->physical_device->rad_info.max_se >= 2;
1137
1138 result = radv_device_init_meta(device);
1139 if (result != VK_SUCCESS)
1140 goto fail;
1141
1142 radv_device_init_msaa(device);
1143
1144 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1145 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1146 switch (family) {
1147 case RADV_QUEUE_GENERAL:
1148 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1149 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1150 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1151 break;
1152 case RADV_QUEUE_COMPUTE:
1153 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1154 radeon_emit(device->empty_cs[family], 0);
1155 break;
1156 }
1157 device->ws->cs_finalize(device->empty_cs[family]);
1158
1159 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1160 switch (family) {
1161 case RADV_QUEUE_GENERAL:
1162 case RADV_QUEUE_COMPUTE:
1163 si_cs_emit_cache_flush(device->flush_cs[family],
1164 false,
1165 device->physical_device->rad_info.chip_class,
1166 NULL, 0,
1167 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1168 RADV_CMD_FLAG_INV_ICACHE |
1169 RADV_CMD_FLAG_INV_SMEM_L1 |
1170 RADV_CMD_FLAG_INV_VMEM_L1 |
1171 RADV_CMD_FLAG_INV_GLOBAL_L2);
1172 break;
1173 }
1174 device->ws->cs_finalize(device->flush_cs[family]);
1175
1176 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1177 switch (family) {
1178 case RADV_QUEUE_GENERAL:
1179 case RADV_QUEUE_COMPUTE:
1180 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1181 false,
1182 device->physical_device->rad_info.chip_class,
1183 NULL, 0,
1184 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1185 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1186 RADV_CMD_FLAG_INV_ICACHE |
1187 RADV_CMD_FLAG_INV_SMEM_L1 |
1188 RADV_CMD_FLAG_INV_VMEM_L1 |
1189 RADV_CMD_FLAG_INV_GLOBAL_L2);
1190 break;
1191 }
1192 device->ws->cs_finalize(device->flush_shader_cs[family]);
1193 }
1194
1195 if (getenv("RADV_TRACE_FILE")) {
1196 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1197 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1198 if (!device->trace_bo)
1199 goto fail;
1200
1201 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1202 if (!device->trace_id_ptr)
1203 goto fail;
1204 }
1205
1206 if (device->physical_device->rad_info.chip_class >= CIK)
1207 cik_create_gfx_config(device);
1208
1209 VkPipelineCacheCreateInfo ci;
1210 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1211 ci.pNext = NULL;
1212 ci.flags = 0;
1213 ci.pInitialData = NULL;
1214 ci.initialDataSize = 0;
1215 VkPipelineCache pc;
1216 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1217 &ci, NULL, &pc);
1218 if (result != VK_SUCCESS)
1219 goto fail;
1220
1221 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1222
1223 *pDevice = radv_device_to_handle(device);
1224 return VK_SUCCESS;
1225
1226 fail:
1227 if (device->trace_bo)
1228 device->ws->buffer_destroy(device->trace_bo);
1229
1230 if (device->gfx_init)
1231 device->ws->buffer_destroy(device->gfx_init);
1232
1233 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1234 for (unsigned q = 0; q < device->queue_count[i]; q++)
1235 radv_queue_finish(&device->queues[i][q]);
1236 if (device->queue_count[i])
1237 vk_free(&device->alloc, device->queues[i]);
1238 }
1239
1240 vk_free(&device->alloc, device);
1241 return result;
1242 }
1243
1244 void radv_DestroyDevice(
1245 VkDevice _device,
1246 const VkAllocationCallbacks* pAllocator)
1247 {
1248 RADV_FROM_HANDLE(radv_device, device, _device);
1249
1250 if (!device)
1251 return;
1252
1253 if (device->trace_bo)
1254 device->ws->buffer_destroy(device->trace_bo);
1255
1256 if (device->gfx_init)
1257 device->ws->buffer_destroy(device->gfx_init);
1258
1259 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1260 for (unsigned q = 0; q < device->queue_count[i]; q++)
1261 radv_queue_finish(&device->queues[i][q]);
1262 if (device->queue_count[i])
1263 vk_free(&device->alloc, device->queues[i]);
1264 if (device->empty_cs[i])
1265 device->ws->cs_destroy(device->empty_cs[i]);
1266 if (device->flush_cs[i])
1267 device->ws->cs_destroy(device->flush_cs[i]);
1268 if (device->flush_shader_cs[i])
1269 device->ws->cs_destroy(device->flush_shader_cs[i]);
1270 }
1271 radv_device_finish_meta(device);
1272
1273 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1274 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1275
1276 radv_destroy_shader_slabs(device);
1277
1278 vk_free(&device->alloc, device);
1279 }
1280
1281 VkResult radv_EnumerateInstanceExtensionProperties(
1282 const char* pLayerName,
1283 uint32_t* pPropertyCount,
1284 VkExtensionProperties* pProperties)
1285 {
1286 if (pProperties == NULL) {
1287 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1288 return VK_SUCCESS;
1289 }
1290
1291 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1292 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1293
1294 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1295 return VK_INCOMPLETE;
1296
1297 return VK_SUCCESS;
1298 }
1299
1300 VkResult radv_EnumerateDeviceExtensionProperties(
1301 VkPhysicalDevice physicalDevice,
1302 const char* pLayerName,
1303 uint32_t* pPropertyCount,
1304 VkExtensionProperties* pProperties)
1305 {
1306 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1307
1308 if (pProperties == NULL) {
1309 *pPropertyCount = pdevice->extensions.num_ext;
1310 return VK_SUCCESS;
1311 }
1312
1313 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1314 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1315
1316 if (*pPropertyCount < pdevice->extensions.num_ext)
1317 return VK_INCOMPLETE;
1318
1319 return VK_SUCCESS;
1320 }
1321
1322 VkResult radv_EnumerateInstanceLayerProperties(
1323 uint32_t* pPropertyCount,
1324 VkLayerProperties* pProperties)
1325 {
1326 if (pProperties == NULL) {
1327 *pPropertyCount = 0;
1328 return VK_SUCCESS;
1329 }
1330
1331 /* None supported at this time */
1332 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1333 }
1334
1335 VkResult radv_EnumerateDeviceLayerProperties(
1336 VkPhysicalDevice physicalDevice,
1337 uint32_t* pPropertyCount,
1338 VkLayerProperties* pProperties)
1339 {
1340 if (pProperties == NULL) {
1341 *pPropertyCount = 0;
1342 return VK_SUCCESS;
1343 }
1344
1345 /* None supported at this time */
1346 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1347 }
1348
1349 void radv_GetDeviceQueue(
1350 VkDevice _device,
1351 uint32_t queueFamilyIndex,
1352 uint32_t queueIndex,
1353 VkQueue* pQueue)
1354 {
1355 RADV_FROM_HANDLE(radv_device, device, _device);
1356
1357 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1358 }
1359
1360 static void radv_dump_trace(struct radv_device *device,
1361 struct radeon_winsys_cs *cs)
1362 {
1363 const char *filename = getenv("RADV_TRACE_FILE");
1364 FILE *f = fopen(filename, "w");
1365 if (!f) {
1366 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1367 return;
1368 }
1369
1370 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1371 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1372 fclose(f);
1373 }
1374
1375 static void
1376 fill_geom_tess_rings(struct radv_queue *queue,
1377 uint32_t *map,
1378 bool add_sample_positions,
1379 uint32_t esgs_ring_size,
1380 struct radeon_winsys_bo *esgs_ring_bo,
1381 uint32_t gsvs_ring_size,
1382 struct radeon_winsys_bo *gsvs_ring_bo,
1383 uint32_t tess_factor_ring_size,
1384 struct radeon_winsys_bo *tess_factor_ring_bo,
1385 uint32_t tess_offchip_ring_size,
1386 struct radeon_winsys_bo *tess_offchip_ring_bo)
1387 {
1388 uint64_t esgs_va = 0, gsvs_va = 0;
1389 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1390 uint32_t *desc = &map[4];
1391
1392 if (esgs_ring_bo)
1393 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1394 if (gsvs_ring_bo)
1395 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1396 if (tess_factor_ring_bo)
1397 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1398 if (tess_offchip_ring_bo)
1399 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1400
1401 /* stride 0, num records - size, add tid, swizzle, elsize4,
1402 index stride 64 */
1403 desc[0] = esgs_va;
1404 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1405 S_008F04_STRIDE(0) |
1406 S_008F04_SWIZZLE_ENABLE(true);
1407 desc[2] = esgs_ring_size;
1408 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1409 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1410 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1411 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1412 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1413 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1414 S_008F0C_ELEMENT_SIZE(1) |
1415 S_008F0C_INDEX_STRIDE(3) |
1416 S_008F0C_ADD_TID_ENABLE(true);
1417
1418 desc += 4;
1419 /* GS entry for ES->GS ring */
1420 /* stride 0, num records - size, elsize0,
1421 index stride 0 */
1422 desc[0] = esgs_va;
1423 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1424 S_008F04_STRIDE(0) |
1425 S_008F04_SWIZZLE_ENABLE(false);
1426 desc[2] = esgs_ring_size;
1427 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1428 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1429 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1430 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1431 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1432 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1433 S_008F0C_ELEMENT_SIZE(0) |
1434 S_008F0C_INDEX_STRIDE(0) |
1435 S_008F0C_ADD_TID_ENABLE(false);
1436
1437 desc += 4;
1438 /* VS entry for GS->VS ring */
1439 /* stride 0, num records - size, elsize0,
1440 index stride 0 */
1441 desc[0] = gsvs_va;
1442 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1443 S_008F04_STRIDE(0) |
1444 S_008F04_SWIZZLE_ENABLE(false);
1445 desc[2] = gsvs_ring_size;
1446 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1447 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1448 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1449 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1450 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1451 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1452 S_008F0C_ELEMENT_SIZE(0) |
1453 S_008F0C_INDEX_STRIDE(0) |
1454 S_008F0C_ADD_TID_ENABLE(false);
1455 desc += 4;
1456
1457 /* stride gsvs_itemsize, num records 64
1458 elsize 4, index stride 16 */
1459 /* shader will patch stride and desc[2] */
1460 desc[0] = gsvs_va;
1461 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1462 S_008F04_STRIDE(0) |
1463 S_008F04_SWIZZLE_ENABLE(true);
1464 desc[2] = 0;
1465 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1466 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1467 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1468 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1469 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1470 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1471 S_008F0C_ELEMENT_SIZE(1) |
1472 S_008F0C_INDEX_STRIDE(1) |
1473 S_008F0C_ADD_TID_ENABLE(true);
1474 desc += 4;
1475
1476 desc[0] = tess_factor_va;
1477 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1478 S_008F04_STRIDE(0) |
1479 S_008F04_SWIZZLE_ENABLE(false);
1480 desc[2] = tess_factor_ring_size;
1481 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1482 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1483 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1484 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1485 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1486 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1487 S_008F0C_ELEMENT_SIZE(0) |
1488 S_008F0C_INDEX_STRIDE(0) |
1489 S_008F0C_ADD_TID_ENABLE(false);
1490 desc += 4;
1491
1492 desc[0] = tess_offchip_va;
1493 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1494 S_008F04_STRIDE(0) |
1495 S_008F04_SWIZZLE_ENABLE(false);
1496 desc[2] = tess_offchip_ring_size;
1497 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1498 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1499 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1500 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1501 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1502 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1503 S_008F0C_ELEMENT_SIZE(0) |
1504 S_008F0C_INDEX_STRIDE(0) |
1505 S_008F0C_ADD_TID_ENABLE(false);
1506 desc += 4;
1507
1508 /* add sample positions after all rings */
1509 memcpy(desc, queue->device->sample_locations_1x, 8);
1510 desc += 2;
1511 memcpy(desc, queue->device->sample_locations_2x, 16);
1512 desc += 4;
1513 memcpy(desc, queue->device->sample_locations_4x, 32);
1514 desc += 8;
1515 memcpy(desc, queue->device->sample_locations_8x, 64);
1516 desc += 16;
1517 memcpy(desc, queue->device->sample_locations_16x, 128);
1518 }
1519
1520 static unsigned
1521 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1522 {
1523 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1524 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1525 device->physical_device->rad_info.family != CHIP_STONEY;
1526 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1527 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1528 device->physical_device->rad_info.max_se;
1529 unsigned offchip_granularity;
1530 unsigned hs_offchip_param;
1531 switch (device->tess_offchip_block_dw_size) {
1532 default:
1533 assert(0);
1534 /* fall through */
1535 case 8192:
1536 offchip_granularity = V_03093C_X_8K_DWORDS;
1537 break;
1538 case 4096:
1539 offchip_granularity = V_03093C_X_4K_DWORDS;
1540 break;
1541 }
1542
1543 switch (device->physical_device->rad_info.chip_class) {
1544 case SI:
1545 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1546 break;
1547 case CIK:
1548 case VI:
1549 case GFX9:
1550 default:
1551 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1552 break;
1553 }
1554
1555 *max_offchip_buffers_p = max_offchip_buffers;
1556 if (device->physical_device->rad_info.chip_class >= CIK) {
1557 if (device->physical_device->rad_info.chip_class >= VI)
1558 --max_offchip_buffers;
1559 hs_offchip_param =
1560 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1561 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1562 } else {
1563 hs_offchip_param =
1564 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1565 }
1566 return hs_offchip_param;
1567 }
1568
1569 static VkResult
1570 radv_get_preamble_cs(struct radv_queue *queue,
1571 uint32_t scratch_size,
1572 uint32_t compute_scratch_size,
1573 uint32_t esgs_ring_size,
1574 uint32_t gsvs_ring_size,
1575 bool needs_tess_rings,
1576 bool needs_sample_positions,
1577 struct radeon_winsys_cs **initial_preamble_cs,
1578 struct radeon_winsys_cs **continue_preamble_cs)
1579 {
1580 struct radeon_winsys_bo *scratch_bo = NULL;
1581 struct radeon_winsys_bo *descriptor_bo = NULL;
1582 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1583 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1584 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1585 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1586 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1587 struct radeon_winsys_cs *dest_cs[2] = {0};
1588 bool add_tess_rings = false, add_sample_positions = false;
1589 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1590 unsigned max_offchip_buffers;
1591 unsigned hs_offchip_param = 0;
1592 if (!queue->has_tess_rings) {
1593 if (needs_tess_rings)
1594 add_tess_rings = true;
1595 }
1596 if (!queue->has_sample_positions) {
1597 if (needs_sample_positions)
1598 add_sample_positions = true;
1599 }
1600 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1601 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1602 &max_offchip_buffers);
1603 tess_offchip_ring_size = max_offchip_buffers *
1604 queue->device->tess_offchip_block_dw_size * 4;
1605
1606 if (scratch_size <= queue->scratch_size &&
1607 compute_scratch_size <= queue->compute_scratch_size &&
1608 esgs_ring_size <= queue->esgs_ring_size &&
1609 gsvs_ring_size <= queue->gsvs_ring_size &&
1610 !add_tess_rings && !add_sample_positions &&
1611 queue->initial_preamble_cs) {
1612 *initial_preamble_cs = queue->initial_preamble_cs;
1613 *continue_preamble_cs = queue->continue_preamble_cs;
1614 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1615 *continue_preamble_cs = NULL;
1616 return VK_SUCCESS;
1617 }
1618
1619 if (scratch_size > queue->scratch_size) {
1620 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1621 scratch_size,
1622 4096,
1623 RADEON_DOMAIN_VRAM,
1624 RADEON_FLAG_NO_CPU_ACCESS);
1625 if (!scratch_bo)
1626 goto fail;
1627 } else
1628 scratch_bo = queue->scratch_bo;
1629
1630 if (compute_scratch_size > queue->compute_scratch_size) {
1631 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1632 compute_scratch_size,
1633 4096,
1634 RADEON_DOMAIN_VRAM,
1635 RADEON_FLAG_NO_CPU_ACCESS);
1636 if (!compute_scratch_bo)
1637 goto fail;
1638
1639 } else
1640 compute_scratch_bo = queue->compute_scratch_bo;
1641
1642 if (esgs_ring_size > queue->esgs_ring_size) {
1643 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1644 esgs_ring_size,
1645 4096,
1646 RADEON_DOMAIN_VRAM,
1647 RADEON_FLAG_NO_CPU_ACCESS);
1648 if (!esgs_ring_bo)
1649 goto fail;
1650 } else {
1651 esgs_ring_bo = queue->esgs_ring_bo;
1652 esgs_ring_size = queue->esgs_ring_size;
1653 }
1654
1655 if (gsvs_ring_size > queue->gsvs_ring_size) {
1656 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1657 gsvs_ring_size,
1658 4096,
1659 RADEON_DOMAIN_VRAM,
1660 RADEON_FLAG_NO_CPU_ACCESS);
1661 if (!gsvs_ring_bo)
1662 goto fail;
1663 } else {
1664 gsvs_ring_bo = queue->gsvs_ring_bo;
1665 gsvs_ring_size = queue->gsvs_ring_size;
1666 }
1667
1668 if (add_tess_rings) {
1669 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1670 tess_factor_ring_size,
1671 256,
1672 RADEON_DOMAIN_VRAM,
1673 RADEON_FLAG_NO_CPU_ACCESS);
1674 if (!tess_factor_ring_bo)
1675 goto fail;
1676 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1677 tess_offchip_ring_size,
1678 256,
1679 RADEON_DOMAIN_VRAM,
1680 RADEON_FLAG_NO_CPU_ACCESS);
1681 if (!tess_offchip_ring_bo)
1682 goto fail;
1683 } else {
1684 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1685 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1686 }
1687
1688 if (scratch_bo != queue->scratch_bo ||
1689 esgs_ring_bo != queue->esgs_ring_bo ||
1690 gsvs_ring_bo != queue->gsvs_ring_bo ||
1691 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1692 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1693 uint32_t size = 0;
1694 if (gsvs_ring_bo || esgs_ring_bo ||
1695 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1696 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1697 if (add_sample_positions)
1698 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1699 }
1700 else if (scratch_bo)
1701 size = 8; /* 2 dword */
1702
1703 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1704 size,
1705 4096,
1706 RADEON_DOMAIN_VRAM,
1707 RADEON_FLAG_CPU_ACCESS);
1708 if (!descriptor_bo)
1709 goto fail;
1710 } else
1711 descriptor_bo = queue->descriptor_bo;
1712
1713 for(int i = 0; i < 2; ++i) {
1714 struct radeon_winsys_cs *cs = NULL;
1715 cs = queue->device->ws->cs_create(queue->device->ws,
1716 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1717 if (!cs)
1718 goto fail;
1719
1720 dest_cs[i] = cs;
1721
1722 if (scratch_bo)
1723 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1724
1725 if (esgs_ring_bo)
1726 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1727
1728 if (gsvs_ring_bo)
1729 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1730
1731 if (tess_factor_ring_bo)
1732 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1733
1734 if (tess_offchip_ring_bo)
1735 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1736
1737 if (descriptor_bo)
1738 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1739
1740 if (descriptor_bo != queue->descriptor_bo) {
1741 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1742
1743 if (scratch_bo) {
1744 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1745 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1746 S_008F04_SWIZZLE_ENABLE(1);
1747 map[0] = scratch_va;
1748 map[1] = rsrc1;
1749 }
1750
1751 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1752 add_sample_positions)
1753 fill_geom_tess_rings(queue, map, add_sample_positions,
1754 esgs_ring_size, esgs_ring_bo,
1755 gsvs_ring_size, gsvs_ring_bo,
1756 tess_factor_ring_size, tess_factor_ring_bo,
1757 tess_offchip_ring_size, tess_offchip_ring_bo);
1758
1759 queue->device->ws->buffer_unmap(descriptor_bo);
1760 }
1761
1762 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1763 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1764 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1765 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1766 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1767 }
1768
1769 if (esgs_ring_bo || gsvs_ring_bo) {
1770 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1771 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1772 radeon_emit(cs, esgs_ring_size >> 8);
1773 radeon_emit(cs, gsvs_ring_size >> 8);
1774 } else {
1775 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1776 radeon_emit(cs, esgs_ring_size >> 8);
1777 radeon_emit(cs, gsvs_ring_size >> 8);
1778 }
1779 }
1780
1781 if (tess_factor_ring_bo) {
1782 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1783 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1784 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1785 S_030938_SIZE(tess_factor_ring_size / 4));
1786 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1787 tf_va >> 8);
1788 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1789 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1790 tf_va >> 40);
1791 }
1792 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1793 } else {
1794 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1795 S_008988_SIZE(tess_factor_ring_size / 4));
1796 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1797 tf_va >> 8);
1798 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1799 hs_offchip_param);
1800 }
1801 }
1802
1803 if (descriptor_bo) {
1804 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1805 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1806 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1807 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1808 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1809 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1810
1811 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1812
1813 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1814 radeon_set_sh_reg_seq(cs, regs[i], 2);
1815 radeon_emit(cs, va);
1816 radeon_emit(cs, va >> 32);
1817 }
1818 }
1819
1820 if (compute_scratch_bo) {
1821 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1822 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1823 S_008F04_SWIZZLE_ENABLE(1);
1824
1825 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1826
1827 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1828 radeon_emit(cs, scratch_va);
1829 radeon_emit(cs, rsrc1);
1830 }
1831
1832 if (!i) {
1833 si_cs_emit_cache_flush(cs,
1834 false,
1835 queue->device->physical_device->rad_info.chip_class,
1836 NULL, 0,
1837 queue->queue_family_index == RING_COMPUTE &&
1838 queue->device->physical_device->rad_info.chip_class >= CIK,
1839 RADV_CMD_FLAG_INV_ICACHE |
1840 RADV_CMD_FLAG_INV_SMEM_L1 |
1841 RADV_CMD_FLAG_INV_VMEM_L1 |
1842 RADV_CMD_FLAG_INV_GLOBAL_L2);
1843 }
1844
1845 if (!queue->device->ws->cs_finalize(cs))
1846 goto fail;
1847 }
1848
1849 if (queue->initial_preamble_cs)
1850 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1851
1852 if (queue->continue_preamble_cs)
1853 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1854
1855 queue->initial_preamble_cs = dest_cs[0];
1856 queue->continue_preamble_cs = dest_cs[1];
1857
1858 if (scratch_bo != queue->scratch_bo) {
1859 if (queue->scratch_bo)
1860 queue->device->ws->buffer_destroy(queue->scratch_bo);
1861 queue->scratch_bo = scratch_bo;
1862 queue->scratch_size = scratch_size;
1863 }
1864
1865 if (compute_scratch_bo != queue->compute_scratch_bo) {
1866 if (queue->compute_scratch_bo)
1867 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1868 queue->compute_scratch_bo = compute_scratch_bo;
1869 queue->compute_scratch_size = compute_scratch_size;
1870 }
1871
1872 if (esgs_ring_bo != queue->esgs_ring_bo) {
1873 if (queue->esgs_ring_bo)
1874 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1875 queue->esgs_ring_bo = esgs_ring_bo;
1876 queue->esgs_ring_size = esgs_ring_size;
1877 }
1878
1879 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1880 if (queue->gsvs_ring_bo)
1881 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1882 queue->gsvs_ring_bo = gsvs_ring_bo;
1883 queue->gsvs_ring_size = gsvs_ring_size;
1884 }
1885
1886 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1887 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1888 }
1889
1890 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1891 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1892 queue->has_tess_rings = true;
1893 }
1894
1895 if (descriptor_bo != queue->descriptor_bo) {
1896 if (queue->descriptor_bo)
1897 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1898
1899 queue->descriptor_bo = descriptor_bo;
1900 }
1901
1902 if (add_sample_positions)
1903 queue->has_sample_positions = true;
1904
1905 *initial_preamble_cs = queue->initial_preamble_cs;
1906 *continue_preamble_cs = queue->continue_preamble_cs;
1907 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1908 *continue_preamble_cs = NULL;
1909 return VK_SUCCESS;
1910 fail:
1911 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1912 if (dest_cs[i])
1913 queue->device->ws->cs_destroy(dest_cs[i]);
1914 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1915 queue->device->ws->buffer_destroy(descriptor_bo);
1916 if (scratch_bo && scratch_bo != queue->scratch_bo)
1917 queue->device->ws->buffer_destroy(scratch_bo);
1918 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1919 queue->device->ws->buffer_destroy(compute_scratch_bo);
1920 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1921 queue->device->ws->buffer_destroy(esgs_ring_bo);
1922 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1923 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1924 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1925 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1926 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1927 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1928 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1929 }
1930
1931 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1932 int num_sems,
1933 const VkSemaphore *sems,
1934 bool reset_temp)
1935 {
1936 int syncobj_idx = 0, sem_idx = 0;
1937
1938 if (num_sems == 0)
1939 return VK_SUCCESS;
1940 for (uint32_t i = 0; i < num_sems; i++) {
1941 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1942
1943 if (sem->temp_syncobj || sem->syncobj)
1944 counts->syncobj_count++;
1945 else
1946 counts->sem_count++;
1947 }
1948
1949 if (counts->syncobj_count) {
1950 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1951 if (!counts->syncobj)
1952 return VK_ERROR_OUT_OF_HOST_MEMORY;
1953 }
1954
1955 if (counts->sem_count) {
1956 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1957 if (!counts->sem) {
1958 free(counts->syncobj);
1959 return VK_ERROR_OUT_OF_HOST_MEMORY;
1960 }
1961 }
1962
1963 for (uint32_t i = 0; i < num_sems; i++) {
1964 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1965
1966 if (sem->temp_syncobj) {
1967 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1968 if (reset_temp) {
1969 /* after we wait on a temp import - drop it */
1970 sem->temp_syncobj = 0;
1971 }
1972 }
1973 else if (sem->syncobj)
1974 counts->syncobj[syncobj_idx++] = sem->syncobj;
1975 else {
1976 assert(sem->sem);
1977 counts->sem[sem_idx++] = sem->sem;
1978 }
1979 }
1980
1981 return VK_SUCCESS;
1982 }
1983
1984 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1985 {
1986 free(sem_info->wait.syncobj);
1987 free(sem_info->wait.sem);
1988 free(sem_info->signal.syncobj);
1989 free(sem_info->signal.sem);
1990 }
1991
1992 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1993 int num_wait_sems,
1994 const VkSemaphore *wait_sems,
1995 int num_signal_sems,
1996 const VkSemaphore *signal_sems)
1997 {
1998 VkResult ret;
1999 memset(sem_info, 0, sizeof(*sem_info));
2000
2001 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2002 if (ret)
2003 return ret;
2004 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2005 if (ret)
2006 radv_free_sem_info(sem_info);
2007
2008 /* caller can override these */
2009 sem_info->cs_emit_wait = true;
2010 sem_info->cs_emit_signal = true;
2011 return ret;
2012 }
2013
2014 VkResult radv_QueueSubmit(
2015 VkQueue _queue,
2016 uint32_t submitCount,
2017 const VkSubmitInfo* pSubmits,
2018 VkFence _fence)
2019 {
2020 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2021 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2022 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2023 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2024 int ret;
2025 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2026 uint32_t scratch_size = 0;
2027 uint32_t compute_scratch_size = 0;
2028 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2029 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
2030 VkResult result;
2031 bool fence_emitted = false;
2032 bool tess_rings_needed = false;
2033 bool sample_positions_needed = false;
2034
2035 /* Do this first so failing to allocate scratch buffers can't result in
2036 * partially executed submissions. */
2037 for (uint32_t i = 0; i < submitCount; i++) {
2038 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2039 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2040 pSubmits[i].pCommandBuffers[j]);
2041
2042 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2043 compute_scratch_size = MAX2(compute_scratch_size,
2044 cmd_buffer->compute_scratch_size_needed);
2045 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2046 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2047 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2048 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2049 }
2050 }
2051
2052 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2053 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2054 sample_positions_needed,
2055 &initial_preamble_cs, &continue_preamble_cs);
2056 if (result != VK_SUCCESS)
2057 return result;
2058
2059 for (uint32_t i = 0; i < submitCount; i++) {
2060 struct radeon_winsys_cs **cs_array;
2061 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2062 bool can_patch = !do_flush;
2063 uint32_t advance;
2064 struct radv_winsys_sem_info sem_info;
2065
2066 result = radv_alloc_sem_info(&sem_info,
2067 pSubmits[i].waitSemaphoreCount,
2068 pSubmits[i].pWaitSemaphores,
2069 pSubmits[i].signalSemaphoreCount,
2070 pSubmits[i].pSignalSemaphores);
2071 if (result != VK_SUCCESS)
2072 return result;
2073
2074 if (!pSubmits[i].commandBufferCount) {
2075 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2076 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2077 &queue->device->empty_cs[queue->queue_family_index],
2078 1, NULL, NULL,
2079 &sem_info,
2080 false, base_fence);
2081 if (ret) {
2082 radv_loge("failed to submit CS %d\n", i);
2083 abort();
2084 }
2085 fence_emitted = true;
2086 }
2087 radv_free_sem_info(&sem_info);
2088 continue;
2089 }
2090
2091 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2092 (pSubmits[i].commandBufferCount + do_flush));
2093
2094 if(do_flush)
2095 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
2096 queue->device->flush_shader_cs[queue->queue_family_index] :
2097 queue->device->flush_cs[queue->queue_family_index];
2098
2099 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2100 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2101 pSubmits[i].pCommandBuffers[j]);
2102 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2103
2104 cs_array[j + do_flush] = cmd_buffer->cs;
2105 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2106 can_patch = false;
2107 }
2108
2109 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
2110 advance = MIN2(max_cs_submission,
2111 pSubmits[i].commandBufferCount + do_flush - j);
2112
2113 if (queue->device->trace_bo)
2114 *queue->device->trace_id_ptr = 0;
2115
2116 sem_info.cs_emit_wait = j == 0;
2117 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount + do_flush;
2118
2119 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2120 advance, initial_preamble_cs, continue_preamble_cs,
2121 &sem_info,
2122 can_patch, base_fence);
2123
2124 if (ret) {
2125 radv_loge("failed to submit CS %d\n", i);
2126 abort();
2127 }
2128 fence_emitted = true;
2129 if (queue->device->trace_bo) {
2130 bool success = queue->device->ws->ctx_wait_idle(
2131 queue->hw_ctx,
2132 radv_queue_family_to_ring(
2133 queue->queue_family_index),
2134 queue->queue_idx);
2135
2136 if (!success) { /* Hang */
2137 radv_dump_trace(queue->device, cs_array[j]);
2138 abort();
2139 }
2140 }
2141 }
2142
2143 radv_free_sem_info(&sem_info);
2144 free(cs_array);
2145 }
2146
2147 if (fence) {
2148 if (!fence_emitted) {
2149 struct radv_winsys_sem_info sem_info = {0};
2150 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2151 &queue->device->empty_cs[queue->queue_family_index],
2152 1, NULL, NULL, &sem_info,
2153 false, base_fence);
2154 }
2155 fence->submitted = true;
2156 }
2157
2158 return VK_SUCCESS;
2159 }
2160
2161 VkResult radv_QueueWaitIdle(
2162 VkQueue _queue)
2163 {
2164 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2165
2166 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2167 radv_queue_family_to_ring(queue->queue_family_index),
2168 queue->queue_idx);
2169 return VK_SUCCESS;
2170 }
2171
2172 VkResult radv_DeviceWaitIdle(
2173 VkDevice _device)
2174 {
2175 RADV_FROM_HANDLE(radv_device, device, _device);
2176
2177 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2178 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2179 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2180 }
2181 }
2182 return VK_SUCCESS;
2183 }
2184
2185 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2186 VkInstance instance,
2187 const char* pName)
2188 {
2189 return radv_lookup_entrypoint(pName);
2190 }
2191
2192 /* The loader wants us to expose a second GetInstanceProcAddr function
2193 * to work around certain LD_PRELOAD issues seen in apps.
2194 */
2195 PUBLIC
2196 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2197 VkInstance instance,
2198 const char* pName);
2199
2200 PUBLIC
2201 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2202 VkInstance instance,
2203 const char* pName)
2204 {
2205 return radv_GetInstanceProcAddr(instance, pName);
2206 }
2207
2208 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2209 VkDevice device,
2210 const char* pName)
2211 {
2212 return radv_lookup_entrypoint(pName);
2213 }
2214
2215 bool radv_get_memory_fd(struct radv_device *device,
2216 struct radv_device_memory *memory,
2217 int *pFD)
2218 {
2219 struct radeon_bo_metadata metadata;
2220
2221 if (memory->image) {
2222 radv_init_metadata(device, memory->image, &metadata);
2223 device->ws->buffer_set_metadata(memory->bo, &metadata);
2224 }
2225
2226 return device->ws->buffer_get_fd(device->ws, memory->bo,
2227 pFD);
2228 }
2229
2230 VkResult radv_AllocateMemory(
2231 VkDevice _device,
2232 const VkMemoryAllocateInfo* pAllocateInfo,
2233 const VkAllocationCallbacks* pAllocator,
2234 VkDeviceMemory* pMem)
2235 {
2236 RADV_FROM_HANDLE(radv_device, device, _device);
2237 struct radv_device_memory *mem;
2238 VkResult result;
2239 enum radeon_bo_domain domain;
2240 uint32_t flags = 0;
2241
2242 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2243
2244 if (pAllocateInfo->allocationSize == 0) {
2245 /* Apparently, this is allowed */
2246 *pMem = VK_NULL_HANDLE;
2247 return VK_SUCCESS;
2248 }
2249
2250 const VkImportMemoryFdInfoKHR *import_info =
2251 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2252 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2253 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2254
2255 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2256 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2257 if (mem == NULL)
2258 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2259
2260 if (dedicate_info) {
2261 mem->image = radv_image_from_handle(dedicate_info->image);
2262 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2263 } else {
2264 mem->image = NULL;
2265 mem->buffer = NULL;
2266 }
2267
2268 if (import_info) {
2269 assert(import_info->handleType ==
2270 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2271 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2272 NULL, NULL);
2273 if (!mem->bo) {
2274 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2275 goto fail;
2276 } else {
2277 close(import_info->fd);
2278 goto out_success;
2279 }
2280 }
2281
2282 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2283 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2284 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2285 domain = RADEON_DOMAIN_GTT;
2286 else
2287 domain = RADEON_DOMAIN_VRAM;
2288
2289 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2290 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2291 else
2292 flags |= RADEON_FLAG_CPU_ACCESS;
2293
2294 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2295 flags |= RADEON_FLAG_GTT_WC;
2296
2297 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2298 domain, flags);
2299
2300 if (!mem->bo) {
2301 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2302 goto fail;
2303 }
2304 mem->type_index = pAllocateInfo->memoryTypeIndex;
2305 out_success:
2306 *pMem = radv_device_memory_to_handle(mem);
2307
2308 return VK_SUCCESS;
2309
2310 fail:
2311 vk_free2(&device->alloc, pAllocator, mem);
2312
2313 return result;
2314 }
2315
2316 void radv_FreeMemory(
2317 VkDevice _device,
2318 VkDeviceMemory _mem,
2319 const VkAllocationCallbacks* pAllocator)
2320 {
2321 RADV_FROM_HANDLE(radv_device, device, _device);
2322 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2323
2324 if (mem == NULL)
2325 return;
2326
2327 device->ws->buffer_destroy(mem->bo);
2328 mem->bo = NULL;
2329
2330 vk_free2(&device->alloc, pAllocator, mem);
2331 }
2332
2333 VkResult radv_MapMemory(
2334 VkDevice _device,
2335 VkDeviceMemory _memory,
2336 VkDeviceSize offset,
2337 VkDeviceSize size,
2338 VkMemoryMapFlags flags,
2339 void** ppData)
2340 {
2341 RADV_FROM_HANDLE(radv_device, device, _device);
2342 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2343
2344 if (mem == NULL) {
2345 *ppData = NULL;
2346 return VK_SUCCESS;
2347 }
2348
2349 *ppData = device->ws->buffer_map(mem->bo);
2350 if (*ppData) {
2351 *ppData += offset;
2352 return VK_SUCCESS;
2353 }
2354
2355 return VK_ERROR_MEMORY_MAP_FAILED;
2356 }
2357
2358 void radv_UnmapMemory(
2359 VkDevice _device,
2360 VkDeviceMemory _memory)
2361 {
2362 RADV_FROM_HANDLE(radv_device, device, _device);
2363 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2364
2365 if (mem == NULL)
2366 return;
2367
2368 device->ws->buffer_unmap(mem->bo);
2369 }
2370
2371 VkResult radv_FlushMappedMemoryRanges(
2372 VkDevice _device,
2373 uint32_t memoryRangeCount,
2374 const VkMappedMemoryRange* pMemoryRanges)
2375 {
2376 return VK_SUCCESS;
2377 }
2378
2379 VkResult radv_InvalidateMappedMemoryRanges(
2380 VkDevice _device,
2381 uint32_t memoryRangeCount,
2382 const VkMappedMemoryRange* pMemoryRanges)
2383 {
2384 return VK_SUCCESS;
2385 }
2386
2387 void radv_GetBufferMemoryRequirements(
2388 VkDevice device,
2389 VkBuffer _buffer,
2390 VkMemoryRequirements* pMemoryRequirements)
2391 {
2392 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2393
2394 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2395
2396 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2397 pMemoryRequirements->alignment = 4096;
2398 else
2399 pMemoryRequirements->alignment = 16;
2400
2401 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2402 }
2403
2404 void radv_GetBufferMemoryRequirements2KHR(
2405 VkDevice device,
2406 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2407 VkMemoryRequirements2KHR* pMemoryRequirements)
2408 {
2409 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2410 &pMemoryRequirements->memoryRequirements);
2411
2412 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2413 switch (ext->sType) {
2414 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2415 VkMemoryDedicatedRequirementsKHR *req =
2416 (VkMemoryDedicatedRequirementsKHR *) ext;
2417 req->requiresDedicatedAllocation = false;
2418 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2419 break;
2420 }
2421 default:
2422 break;
2423 }
2424 }
2425 }
2426
2427 void radv_GetImageMemoryRequirements(
2428 VkDevice device,
2429 VkImage _image,
2430 VkMemoryRequirements* pMemoryRequirements)
2431 {
2432 RADV_FROM_HANDLE(radv_image, image, _image);
2433
2434 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2435
2436 pMemoryRequirements->size = image->size;
2437 pMemoryRequirements->alignment = image->alignment;
2438 }
2439
2440 void radv_GetImageMemoryRequirements2KHR(
2441 VkDevice device,
2442 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2443 VkMemoryRequirements2KHR* pMemoryRequirements)
2444 {
2445 radv_GetImageMemoryRequirements(device, pInfo->image,
2446 &pMemoryRequirements->memoryRequirements);
2447
2448 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2449
2450 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2451 switch (ext->sType) {
2452 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2453 VkMemoryDedicatedRequirementsKHR *req =
2454 (VkMemoryDedicatedRequirementsKHR *) ext;
2455 req->requiresDedicatedAllocation = image->shareable;
2456 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2457 break;
2458 }
2459 default:
2460 break;
2461 }
2462 }
2463 }
2464
2465 void radv_GetImageSparseMemoryRequirements(
2466 VkDevice device,
2467 VkImage image,
2468 uint32_t* pSparseMemoryRequirementCount,
2469 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2470 {
2471 stub();
2472 }
2473
2474 void radv_GetImageSparseMemoryRequirements2KHR(
2475 VkDevice device,
2476 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2477 uint32_t* pSparseMemoryRequirementCount,
2478 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2479 {
2480 stub();
2481 }
2482
2483 void radv_GetDeviceMemoryCommitment(
2484 VkDevice device,
2485 VkDeviceMemory memory,
2486 VkDeviceSize* pCommittedMemoryInBytes)
2487 {
2488 *pCommittedMemoryInBytes = 0;
2489 }
2490
2491 VkResult radv_BindBufferMemory(
2492 VkDevice device,
2493 VkBuffer _buffer,
2494 VkDeviceMemory _memory,
2495 VkDeviceSize memoryOffset)
2496 {
2497 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2498 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2499
2500 if (mem) {
2501 buffer->bo = mem->bo;
2502 buffer->offset = memoryOffset;
2503 } else {
2504 buffer->bo = NULL;
2505 buffer->offset = 0;
2506 }
2507
2508 return VK_SUCCESS;
2509 }
2510
2511 VkResult radv_BindImageMemory(
2512 VkDevice device,
2513 VkImage _image,
2514 VkDeviceMemory _memory,
2515 VkDeviceSize memoryOffset)
2516 {
2517 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2518 RADV_FROM_HANDLE(radv_image, image, _image);
2519
2520 if (mem) {
2521 image->bo = mem->bo;
2522 image->offset = memoryOffset;
2523 } else {
2524 image->bo = NULL;
2525 image->offset = 0;
2526 }
2527
2528 return VK_SUCCESS;
2529 }
2530
2531
2532 static void
2533 radv_sparse_buffer_bind_memory(struct radv_device *device,
2534 const VkSparseBufferMemoryBindInfo *bind)
2535 {
2536 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2537
2538 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2539 struct radv_device_memory *mem = NULL;
2540
2541 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2542 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2543
2544 device->ws->buffer_virtual_bind(buffer->bo,
2545 bind->pBinds[i].resourceOffset,
2546 bind->pBinds[i].size,
2547 mem ? mem->bo : NULL,
2548 bind->pBinds[i].memoryOffset);
2549 }
2550 }
2551
2552 static void
2553 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2554 const VkSparseImageOpaqueMemoryBindInfo *bind)
2555 {
2556 RADV_FROM_HANDLE(radv_image, image, bind->image);
2557
2558 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2559 struct radv_device_memory *mem = NULL;
2560
2561 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2562 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2563
2564 device->ws->buffer_virtual_bind(image->bo,
2565 bind->pBinds[i].resourceOffset,
2566 bind->pBinds[i].size,
2567 mem ? mem->bo : NULL,
2568 bind->pBinds[i].memoryOffset);
2569 }
2570 }
2571
2572 VkResult radv_QueueBindSparse(
2573 VkQueue _queue,
2574 uint32_t bindInfoCount,
2575 const VkBindSparseInfo* pBindInfo,
2576 VkFence _fence)
2577 {
2578 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2579 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2580 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2581 bool fence_emitted = false;
2582
2583 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2584 struct radv_winsys_sem_info sem_info;
2585 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2586 radv_sparse_buffer_bind_memory(queue->device,
2587 pBindInfo[i].pBufferBinds + j);
2588 }
2589
2590 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2591 radv_sparse_image_opaque_bind_memory(queue->device,
2592 pBindInfo[i].pImageOpaqueBinds + j);
2593 }
2594
2595 VkResult result;
2596 result = radv_alloc_sem_info(&sem_info,
2597 pBindInfo[i].waitSemaphoreCount,
2598 pBindInfo[i].pWaitSemaphores,
2599 pBindInfo[i].signalSemaphoreCount,
2600 pBindInfo[i].pSignalSemaphores);
2601 if (result != VK_SUCCESS)
2602 return result;
2603
2604 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2605 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2606 &queue->device->empty_cs[queue->queue_family_index],
2607 1, NULL, NULL,
2608 &sem_info,
2609 false, base_fence);
2610 fence_emitted = true;
2611 if (fence)
2612 fence->submitted = true;
2613 }
2614
2615 radv_free_sem_info(&sem_info);
2616
2617 }
2618
2619 if (fence && !fence_emitted) {
2620 fence->signalled = true;
2621 }
2622
2623 return VK_SUCCESS;
2624 }
2625
2626 VkResult radv_CreateFence(
2627 VkDevice _device,
2628 const VkFenceCreateInfo* pCreateInfo,
2629 const VkAllocationCallbacks* pAllocator,
2630 VkFence* pFence)
2631 {
2632 RADV_FROM_HANDLE(radv_device, device, _device);
2633 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2634 sizeof(*fence), 8,
2635 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2636
2637 if (!fence)
2638 return VK_ERROR_OUT_OF_HOST_MEMORY;
2639
2640 memset(fence, 0, sizeof(*fence));
2641 fence->submitted = false;
2642 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2643 fence->fence = device->ws->create_fence();
2644 if (!fence->fence) {
2645 vk_free2(&device->alloc, pAllocator, fence);
2646 return VK_ERROR_OUT_OF_HOST_MEMORY;
2647 }
2648
2649 *pFence = radv_fence_to_handle(fence);
2650
2651 return VK_SUCCESS;
2652 }
2653
2654 void radv_DestroyFence(
2655 VkDevice _device,
2656 VkFence _fence,
2657 const VkAllocationCallbacks* pAllocator)
2658 {
2659 RADV_FROM_HANDLE(radv_device, device, _device);
2660 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2661
2662 if (!fence)
2663 return;
2664 device->ws->destroy_fence(fence->fence);
2665 vk_free2(&device->alloc, pAllocator, fence);
2666 }
2667
2668 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2669 {
2670 uint64_t current_time;
2671 struct timespec tv;
2672
2673 clock_gettime(CLOCK_MONOTONIC, &tv);
2674 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2675
2676 timeout = MIN2(UINT64_MAX - current_time, timeout);
2677
2678 return current_time + timeout;
2679 }
2680
2681 VkResult radv_WaitForFences(
2682 VkDevice _device,
2683 uint32_t fenceCount,
2684 const VkFence* pFences,
2685 VkBool32 waitAll,
2686 uint64_t timeout)
2687 {
2688 RADV_FROM_HANDLE(radv_device, device, _device);
2689 timeout = radv_get_absolute_timeout(timeout);
2690
2691 if (!waitAll && fenceCount > 1) {
2692 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2693 }
2694
2695 for (uint32_t i = 0; i < fenceCount; ++i) {
2696 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2697 bool expired = false;
2698
2699 if (fence->signalled)
2700 continue;
2701
2702 if (!fence->submitted)
2703 return VK_TIMEOUT;
2704
2705 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2706 if (!expired)
2707 return VK_TIMEOUT;
2708
2709 fence->signalled = true;
2710 }
2711
2712 return VK_SUCCESS;
2713 }
2714
2715 VkResult radv_ResetFences(VkDevice device,
2716 uint32_t fenceCount,
2717 const VkFence *pFences)
2718 {
2719 for (unsigned i = 0; i < fenceCount; ++i) {
2720 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2721 fence->submitted = fence->signalled = false;
2722 }
2723
2724 return VK_SUCCESS;
2725 }
2726
2727 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2728 {
2729 RADV_FROM_HANDLE(radv_device, device, _device);
2730 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2731
2732 if (fence->signalled)
2733 return VK_SUCCESS;
2734 if (!fence->submitted)
2735 return VK_NOT_READY;
2736
2737 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2738 return VK_NOT_READY;
2739
2740 return VK_SUCCESS;
2741 }
2742
2743
2744 // Queue semaphore functions
2745
2746 VkResult radv_CreateSemaphore(
2747 VkDevice _device,
2748 const VkSemaphoreCreateInfo* pCreateInfo,
2749 const VkAllocationCallbacks* pAllocator,
2750 VkSemaphore* pSemaphore)
2751 {
2752 RADV_FROM_HANDLE(radv_device, device, _device);
2753 const VkExportSemaphoreCreateInfoKHR *export =
2754 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2755 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2756 export ? export->handleTypes : 0;
2757
2758 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2759 sizeof(*sem), 8,
2760 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2761 if (!sem)
2762 return VK_ERROR_OUT_OF_HOST_MEMORY;
2763
2764 sem->temp_syncobj = 0;
2765 /* create a syncobject if we are going to export this semaphore */
2766 if (handleTypes) {
2767 assert (device->physical_device->rad_info.has_syncobj);
2768 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2769 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2770 if (ret) {
2771 vk_free2(&device->alloc, pAllocator, sem);
2772 return VK_ERROR_OUT_OF_HOST_MEMORY;
2773 }
2774 sem->sem = NULL;
2775 } else {
2776 sem->sem = device->ws->create_sem(device->ws);
2777 if (!sem->sem) {
2778 vk_free2(&device->alloc, pAllocator, sem);
2779 return VK_ERROR_OUT_OF_HOST_MEMORY;
2780 }
2781 sem->syncobj = 0;
2782 }
2783
2784 *pSemaphore = radv_semaphore_to_handle(sem);
2785 return VK_SUCCESS;
2786 }
2787
2788 void radv_DestroySemaphore(
2789 VkDevice _device,
2790 VkSemaphore _semaphore,
2791 const VkAllocationCallbacks* pAllocator)
2792 {
2793 RADV_FROM_HANDLE(radv_device, device, _device);
2794 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2795 if (!_semaphore)
2796 return;
2797
2798 if (sem->syncobj)
2799 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2800 else
2801 device->ws->destroy_sem(sem->sem);
2802 vk_free2(&device->alloc, pAllocator, sem);
2803 }
2804
2805 VkResult radv_CreateEvent(
2806 VkDevice _device,
2807 const VkEventCreateInfo* pCreateInfo,
2808 const VkAllocationCallbacks* pAllocator,
2809 VkEvent* pEvent)
2810 {
2811 RADV_FROM_HANDLE(radv_device, device, _device);
2812 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2813 sizeof(*event), 8,
2814 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2815
2816 if (!event)
2817 return VK_ERROR_OUT_OF_HOST_MEMORY;
2818
2819 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2820 RADEON_DOMAIN_GTT,
2821 RADEON_FLAG_CPU_ACCESS);
2822 if (!event->bo) {
2823 vk_free2(&device->alloc, pAllocator, event);
2824 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2825 }
2826
2827 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2828
2829 *pEvent = radv_event_to_handle(event);
2830
2831 return VK_SUCCESS;
2832 }
2833
2834 void radv_DestroyEvent(
2835 VkDevice _device,
2836 VkEvent _event,
2837 const VkAllocationCallbacks* pAllocator)
2838 {
2839 RADV_FROM_HANDLE(radv_device, device, _device);
2840 RADV_FROM_HANDLE(radv_event, event, _event);
2841
2842 if (!event)
2843 return;
2844 device->ws->buffer_destroy(event->bo);
2845 vk_free2(&device->alloc, pAllocator, event);
2846 }
2847
2848 VkResult radv_GetEventStatus(
2849 VkDevice _device,
2850 VkEvent _event)
2851 {
2852 RADV_FROM_HANDLE(radv_event, event, _event);
2853
2854 if (*event->map == 1)
2855 return VK_EVENT_SET;
2856 return VK_EVENT_RESET;
2857 }
2858
2859 VkResult radv_SetEvent(
2860 VkDevice _device,
2861 VkEvent _event)
2862 {
2863 RADV_FROM_HANDLE(radv_event, event, _event);
2864 *event->map = 1;
2865
2866 return VK_SUCCESS;
2867 }
2868
2869 VkResult radv_ResetEvent(
2870 VkDevice _device,
2871 VkEvent _event)
2872 {
2873 RADV_FROM_HANDLE(radv_event, event, _event);
2874 *event->map = 0;
2875
2876 return VK_SUCCESS;
2877 }
2878
2879 VkResult radv_CreateBuffer(
2880 VkDevice _device,
2881 const VkBufferCreateInfo* pCreateInfo,
2882 const VkAllocationCallbacks* pAllocator,
2883 VkBuffer* pBuffer)
2884 {
2885 RADV_FROM_HANDLE(radv_device, device, _device);
2886 struct radv_buffer *buffer;
2887
2888 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2889
2890 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2891 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2892 if (buffer == NULL)
2893 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2894
2895 buffer->size = pCreateInfo->size;
2896 buffer->usage = pCreateInfo->usage;
2897 buffer->bo = NULL;
2898 buffer->offset = 0;
2899 buffer->flags = pCreateInfo->flags;
2900
2901 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2902 buffer->bo = device->ws->buffer_create(device->ws,
2903 align64(buffer->size, 4096),
2904 4096, 0, RADEON_FLAG_VIRTUAL);
2905 if (!buffer->bo) {
2906 vk_free2(&device->alloc, pAllocator, buffer);
2907 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2908 }
2909 }
2910
2911 *pBuffer = radv_buffer_to_handle(buffer);
2912
2913 return VK_SUCCESS;
2914 }
2915
2916 void radv_DestroyBuffer(
2917 VkDevice _device,
2918 VkBuffer _buffer,
2919 const VkAllocationCallbacks* pAllocator)
2920 {
2921 RADV_FROM_HANDLE(radv_device, device, _device);
2922 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2923
2924 if (!buffer)
2925 return;
2926
2927 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2928 device->ws->buffer_destroy(buffer->bo);
2929
2930 vk_free2(&device->alloc, pAllocator, buffer);
2931 }
2932
2933 static inline unsigned
2934 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2935 {
2936 if (stencil)
2937 return image->surface.u.legacy.stencil_tiling_index[level];
2938 else
2939 return image->surface.u.legacy.tiling_index[level];
2940 }
2941
2942 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2943 {
2944 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2945 }
2946
2947 static void
2948 radv_initialise_color_surface(struct radv_device *device,
2949 struct radv_color_buffer_info *cb,
2950 struct radv_image_view *iview)
2951 {
2952 const struct vk_format_description *desc;
2953 unsigned ntype, format, swap, endian;
2954 unsigned blend_clamp = 0, blend_bypass = 0;
2955 uint64_t va;
2956 const struct radeon_surf *surf = &iview->image->surface;
2957
2958 desc = vk_format_description(iview->vk_format);
2959
2960 memset(cb, 0, sizeof(*cb));
2961
2962 /* Intensity is implemented as Red, so treat it that way. */
2963 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2964
2965 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2966
2967 cb->cb_color_base = va >> 8;
2968
2969 if (device->physical_device->rad_info.chip_class >= GFX9) {
2970 struct gfx9_surf_meta_flags meta;
2971 if (iview->image->dcc_offset)
2972 meta = iview->image->surface.u.gfx9.dcc;
2973 else
2974 meta = iview->image->surface.u.gfx9.cmask;
2975
2976 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2977 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2978 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2979 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2980
2981 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2982 } else {
2983 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2984 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2985
2986 cb->cb_color_base += level_info->offset >> 8;
2987 if (level_info->mode == RADEON_SURF_MODE_2D)
2988 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2989
2990 pitch_tile_max = level_info->nblk_x / 8 - 1;
2991 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2992 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2993
2994 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2995 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2996 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2997
2998 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2999 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3000
3001 if (iview->image->fmask.size) {
3002 if (device->physical_device->rad_info.chip_class >= CIK)
3003 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3004 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3005 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3006 } else {
3007 /* This must be set for fast clear to work without FMASK. */
3008 if (device->physical_device->rad_info.chip_class >= CIK)
3009 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3010 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3011 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3012 }
3013 }
3014
3015 /* CMASK variables */
3016 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3017 va += iview->image->cmask.offset;
3018 cb->cb_color_cmask = va >> 8;
3019
3020 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3021 va += iview->image->dcc_offset;
3022 cb->cb_dcc_base = va >> 8;
3023 if (device->physical_device->rad_info.chip_class < GFX9)
3024 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3025
3026 uint32_t max_slice = radv_surface_layer_count(iview);
3027 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3028 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3029
3030 if (iview->image->info.samples > 1) {
3031 unsigned log_samples = util_logbase2(iview->image->info.samples);
3032
3033 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3034 S_028C74_NUM_FRAGMENTS(log_samples);
3035 }
3036
3037 if (iview->image->fmask.size) {
3038 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3039 cb->cb_color_fmask = va >> 8;
3040 if (device->physical_device->rad_info.chip_class < GFX9)
3041 cb->cb_color_fmask |= iview->image->surface.tile_swizzle;
3042 } else {
3043 cb->cb_color_fmask = cb->cb_color_base;
3044 }
3045
3046 ntype = radv_translate_color_numformat(iview->vk_format,
3047 desc,
3048 vk_format_get_first_non_void_channel(iview->vk_format));
3049 format = radv_translate_colorformat(iview->vk_format);
3050 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3051 radv_finishme("Illegal color\n");
3052 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3053 endian = radv_colorformat_endian_swap(format);
3054
3055 /* blend clamp should be set for all NORM/SRGB types */
3056 if (ntype == V_028C70_NUMBER_UNORM ||
3057 ntype == V_028C70_NUMBER_SNORM ||
3058 ntype == V_028C70_NUMBER_SRGB)
3059 blend_clamp = 1;
3060
3061 /* set blend bypass according to docs if SINT/UINT or
3062 8/24 COLOR variants */
3063 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3064 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3065 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3066 blend_clamp = 0;
3067 blend_bypass = 1;
3068 }
3069 #if 0
3070 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3071 (format == V_028C70_COLOR_8 ||
3072 format == V_028C70_COLOR_8_8 ||
3073 format == V_028C70_COLOR_8_8_8_8))
3074 ->color_is_int8 = true;
3075 #endif
3076 cb->cb_color_info = S_028C70_FORMAT(format) |
3077 S_028C70_COMP_SWAP(swap) |
3078 S_028C70_BLEND_CLAMP(blend_clamp) |
3079 S_028C70_BLEND_BYPASS(blend_bypass) |
3080 S_028C70_SIMPLE_FLOAT(1) |
3081 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3082 ntype != V_028C70_NUMBER_SNORM &&
3083 ntype != V_028C70_NUMBER_SRGB &&
3084 format != V_028C70_COLOR_8_24 &&
3085 format != V_028C70_COLOR_24_8) |
3086 S_028C70_NUMBER_TYPE(ntype) |
3087 S_028C70_ENDIAN(endian);
3088 if (iview->image->info.samples > 1)
3089 if (iview->image->fmask.size)
3090 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3091
3092 if (iview->image->cmask.size &&
3093 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3094 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3095
3096 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3097 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3098
3099 if (device->physical_device->rad_info.chip_class >= VI) {
3100 unsigned max_uncompressed_block_size = 2;
3101 if (iview->image->info.samples > 1) {
3102 if (iview->image->surface.bpe == 1)
3103 max_uncompressed_block_size = 0;
3104 else if (iview->image->surface.bpe == 2)
3105 max_uncompressed_block_size = 1;
3106 }
3107
3108 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3109 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3110 }
3111
3112 /* This must be set for fast clear to work without FMASK. */
3113 if (!iview->image->fmask.size &&
3114 device->physical_device->rad_info.chip_class == SI) {
3115 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3116 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3117 }
3118
3119 if (device->physical_device->rad_info.chip_class >= GFX9) {
3120 uint32_t max_slice = radv_surface_layer_count(iview);
3121 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3122
3123 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3124 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3125 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3126 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
3127 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
3128 S_028C68_MAX_MIP(iview->image->info.levels);
3129
3130 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3131
3132 }
3133 }
3134
3135 static void
3136 radv_initialise_ds_surface(struct radv_device *device,
3137 struct radv_ds_buffer_info *ds,
3138 struct radv_image_view *iview)
3139 {
3140 unsigned level = iview->base_mip;
3141 unsigned format, stencil_format;
3142 uint64_t va, s_offs, z_offs;
3143 bool stencil_only = false;
3144 memset(ds, 0, sizeof(*ds));
3145 switch (iview->image->vk_format) {
3146 case VK_FORMAT_D24_UNORM_S8_UINT:
3147 case VK_FORMAT_X8_D24_UNORM_PACK32:
3148 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3149 ds->offset_scale = 2.0f;
3150 break;
3151 case VK_FORMAT_D16_UNORM:
3152 case VK_FORMAT_D16_UNORM_S8_UINT:
3153 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3154 ds->offset_scale = 4.0f;
3155 break;
3156 case VK_FORMAT_D32_SFLOAT:
3157 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3158 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3159 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3160 ds->offset_scale = 1.0f;
3161 break;
3162 case VK_FORMAT_S8_UINT:
3163 stencil_only = true;
3164 break;
3165 default:
3166 break;
3167 }
3168
3169 format = radv_translate_dbformat(iview->image->vk_format);
3170 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
3171 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3172
3173 uint32_t max_slice = radv_surface_layer_count(iview);
3174 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3175 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3176
3177 ds->db_htile_data_base = 0;
3178 ds->db_htile_surface = 0;
3179
3180 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3181 s_offs = z_offs = va;
3182
3183 if (device->physical_device->rad_info.chip_class >= GFX9) {
3184 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3185 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3186
3187 ds->db_z_info = S_028038_FORMAT(format) |
3188 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3189 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3190 S_028038_MAXMIP(iview->image->info.levels - 1);
3191 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3192 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3193
3194 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3195 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3196 ds->db_depth_view |= S_028008_MIPID(level);
3197
3198 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3199 S_02801C_Y_MAX(iview->image->info.height - 1);
3200
3201 /* Only use HTILE for the first level. */
3202 if (iview->image->surface.htile_size && !level) {
3203 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3204
3205 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3206 /* Use all of the htile_buffer for depth if there's no stencil. */
3207 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3208 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3209 iview->image->htile_offset;
3210 ds->db_htile_data_base = va >> 8;
3211 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3212 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3213 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3214 }
3215 } else {
3216 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3217
3218 if (stencil_only)
3219 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3220
3221 z_offs += iview->image->surface.u.legacy.level[level].offset;
3222 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3223
3224 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3225 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3226 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3227
3228 if (iview->image->info.samples > 1)
3229 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3230
3231 if (device->physical_device->rad_info.chip_class >= CIK) {
3232 struct radeon_info *info = &device->physical_device->rad_info;
3233 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3234 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3235 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3236 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3237 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3238 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3239
3240 if (stencil_only)
3241 tile_mode = stencil_tile_mode;
3242
3243 ds->db_depth_info |=
3244 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3245 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3246 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3247 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3248 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3249 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3250 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3251 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3252 } else {
3253 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3254 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3255 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3256 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3257 if (stencil_only)
3258 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3259 }
3260
3261 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3262 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3263 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3264
3265 if (iview->image->surface.htile_size && !level) {
3266 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3267
3268 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3269 /* Use all of the htile_buffer for depth if there's no stencil. */
3270 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3271
3272 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3273 iview->image->htile_offset;
3274 ds->db_htile_data_base = va >> 8;
3275 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3276 }
3277 }
3278
3279 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3280 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3281 }
3282
3283 VkResult radv_CreateFramebuffer(
3284 VkDevice _device,
3285 const VkFramebufferCreateInfo* pCreateInfo,
3286 const VkAllocationCallbacks* pAllocator,
3287 VkFramebuffer* pFramebuffer)
3288 {
3289 RADV_FROM_HANDLE(radv_device, device, _device);
3290 struct radv_framebuffer *framebuffer;
3291
3292 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3293
3294 size_t size = sizeof(*framebuffer) +
3295 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3296 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3297 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3298 if (framebuffer == NULL)
3299 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3300
3301 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3302 framebuffer->width = pCreateInfo->width;
3303 framebuffer->height = pCreateInfo->height;
3304 framebuffer->layers = pCreateInfo->layers;
3305 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3306 VkImageView _iview = pCreateInfo->pAttachments[i];
3307 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3308 framebuffer->attachments[i].attachment = iview;
3309 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3310 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3311 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3312 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3313 }
3314 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3315 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3316 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3317 }
3318
3319 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3320 return VK_SUCCESS;
3321 }
3322
3323 void radv_DestroyFramebuffer(
3324 VkDevice _device,
3325 VkFramebuffer _fb,
3326 const VkAllocationCallbacks* pAllocator)
3327 {
3328 RADV_FROM_HANDLE(radv_device, device, _device);
3329 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3330
3331 if (!fb)
3332 return;
3333 vk_free2(&device->alloc, pAllocator, fb);
3334 }
3335
3336 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3337 {
3338 switch (address_mode) {
3339 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3340 return V_008F30_SQ_TEX_WRAP;
3341 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3342 return V_008F30_SQ_TEX_MIRROR;
3343 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3344 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3345 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3346 return V_008F30_SQ_TEX_CLAMP_BORDER;
3347 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3348 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3349 default:
3350 unreachable("illegal tex wrap mode");
3351 break;
3352 }
3353 }
3354
3355 static unsigned
3356 radv_tex_compare(VkCompareOp op)
3357 {
3358 switch (op) {
3359 case VK_COMPARE_OP_NEVER:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3361 case VK_COMPARE_OP_LESS:
3362 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3363 case VK_COMPARE_OP_EQUAL:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3365 case VK_COMPARE_OP_LESS_OR_EQUAL:
3366 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3367 case VK_COMPARE_OP_GREATER:
3368 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3369 case VK_COMPARE_OP_NOT_EQUAL:
3370 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3371 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3372 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3373 case VK_COMPARE_OP_ALWAYS:
3374 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3375 default:
3376 unreachable("illegal compare mode");
3377 break;
3378 }
3379 }
3380
3381 static unsigned
3382 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3383 {
3384 switch (filter) {
3385 case VK_FILTER_NEAREST:
3386 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3387 V_008F38_SQ_TEX_XY_FILTER_POINT);
3388 case VK_FILTER_LINEAR:
3389 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3390 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3391 case VK_FILTER_CUBIC_IMG:
3392 default:
3393 fprintf(stderr, "illegal texture filter");
3394 return 0;
3395 }
3396 }
3397
3398 static unsigned
3399 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3400 {
3401 switch (mode) {
3402 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3403 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3404 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3405 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3406 default:
3407 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3408 }
3409 }
3410
3411 static unsigned
3412 radv_tex_bordercolor(VkBorderColor bcolor)
3413 {
3414 switch (bcolor) {
3415 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3416 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3417 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3418 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3419 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3420 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3421 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3422 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3423 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3424 default:
3425 break;
3426 }
3427 return 0;
3428 }
3429
3430 static unsigned
3431 radv_tex_aniso_filter(unsigned filter)
3432 {
3433 if (filter < 2)
3434 return 0;
3435 if (filter < 4)
3436 return 1;
3437 if (filter < 8)
3438 return 2;
3439 if (filter < 16)
3440 return 3;
3441 return 4;
3442 }
3443
3444 static void
3445 radv_init_sampler(struct radv_device *device,
3446 struct radv_sampler *sampler,
3447 const VkSamplerCreateInfo *pCreateInfo)
3448 {
3449 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3450 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3451 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3452 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3453
3454 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3455 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3456 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3457 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3458 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3459 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3460 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3461 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3462 S_008F30_DISABLE_CUBE_WRAP(0) |
3463 S_008F30_COMPAT_MODE(is_vi));
3464 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3465 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3466 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3467 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3468 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3469 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3470 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3471 S_008F38_MIP_POINT_PRECLAMP(0) |
3472 S_008F38_DISABLE_LSB_CEIL(1) |
3473 S_008F38_FILTER_PREC_FIX(1) |
3474 S_008F38_ANISO_OVERRIDE(is_vi));
3475 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3476 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3477 }
3478
3479 VkResult radv_CreateSampler(
3480 VkDevice _device,
3481 const VkSamplerCreateInfo* pCreateInfo,
3482 const VkAllocationCallbacks* pAllocator,
3483 VkSampler* pSampler)
3484 {
3485 RADV_FROM_HANDLE(radv_device, device, _device);
3486 struct radv_sampler *sampler;
3487
3488 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3489
3490 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3491 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3492 if (!sampler)
3493 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3494
3495 radv_init_sampler(device, sampler, pCreateInfo);
3496 *pSampler = radv_sampler_to_handle(sampler);
3497
3498 return VK_SUCCESS;
3499 }
3500
3501 void radv_DestroySampler(
3502 VkDevice _device,
3503 VkSampler _sampler,
3504 const VkAllocationCallbacks* pAllocator)
3505 {
3506 RADV_FROM_HANDLE(radv_device, device, _device);
3507 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3508
3509 if (!sampler)
3510 return;
3511 vk_free2(&device->alloc, pAllocator, sampler);
3512 }
3513
3514 /* vk_icd.h does not declare this function, so we declare it here to
3515 * suppress Wmissing-prototypes.
3516 */
3517 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3518 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3519
3520 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3521 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3522 {
3523 /* For the full details on loader interface versioning, see
3524 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3525 * What follows is a condensed summary, to help you navigate the large and
3526 * confusing official doc.
3527 *
3528 * - Loader interface v0 is incompatible with later versions. We don't
3529 * support it.
3530 *
3531 * - In loader interface v1:
3532 * - The first ICD entrypoint called by the loader is
3533 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3534 * entrypoint.
3535 * - The ICD must statically expose no other Vulkan symbol unless it is
3536 * linked with -Bsymbolic.
3537 * - Each dispatchable Vulkan handle created by the ICD must be
3538 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3539 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3540 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3541 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3542 * such loader-managed surfaces.
3543 *
3544 * - Loader interface v2 differs from v1 in:
3545 * - The first ICD entrypoint called by the loader is
3546 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3547 * statically expose this entrypoint.
3548 *
3549 * - Loader interface v3 differs from v2 in:
3550 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3551 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3552 * because the loader no longer does so.
3553 */
3554 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3555 return VK_SUCCESS;
3556 }
3557
3558 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3559 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3560 int *pFD)
3561 {
3562 RADV_FROM_HANDLE(radv_device, device, _device);
3563 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3564
3565 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3566
3567 /* We support only one handle type. */
3568 assert(pGetFdInfo->handleType ==
3569 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3570
3571 bool ret = radv_get_memory_fd(device, memory, pFD);
3572 if (ret == false)
3573 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3574 return VK_SUCCESS;
3575 }
3576
3577 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3578 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3579 int fd,
3580 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3581 {
3582 /* The valid usage section for this function says:
3583 *
3584 * "handleType must not be one of the handle types defined as opaque."
3585 *
3586 * Since we only handle opaque handles for now, there are no FD properties.
3587 */
3588 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3589 }
3590
3591 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3592 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3593 {
3594 RADV_FROM_HANDLE(radv_device, device, _device);
3595 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3596 uint32_t syncobj_handle = 0;
3597 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3598
3599 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3600 if (ret != 0)
3601 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3602
3603 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3604 sem->temp_syncobj = syncobj_handle;
3605 } else {
3606 sem->syncobj = syncobj_handle;
3607 }
3608 close(pImportSemaphoreFdInfo->fd);
3609 return VK_SUCCESS;
3610 }
3611
3612 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3613 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3614 int *pFd)
3615 {
3616 RADV_FROM_HANDLE(radv_device, device, _device);
3617 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3618 int ret;
3619 uint32_t syncobj_handle;
3620
3621 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3622 if (sem->temp_syncobj)
3623 syncobj_handle = sem->temp_syncobj;
3624 else
3625 syncobj_handle = sem->syncobj;
3626 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3627 if (ret)
3628 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3629 return VK_SUCCESS;
3630 }
3631
3632 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3633 VkPhysicalDevice physicalDevice,
3634 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3635 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3636 {
3637 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3638 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3639 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3640 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3641 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3642 } else {
3643 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3644 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3645 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3646 }
3647 }