projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: rename physical_device->uuid[] to cache_uuid[]
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 {
102 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 {
106 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
107 .specVersion = 1,
108 },
109 };
110
111 static const VkExtensionProperties common_device_extensions[] = {
112 {
113 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
134 .specVersion = 68,
135 },
136 {
137 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 {
161 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
162 .specVersion = 1,
163 },
164 {
165 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
166 .specVersion = 1,
167 },
168 };
169 static const VkExtensionProperties ext_sema_device_extensions[] = {
170 {
171 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
172 .specVersion = 1,
173 },
174 {
175 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
176 .specVersion = 1,
177 },
178 };
179
180 static VkResult
181 radv_extensions_register(struct radv_instance *instance,
182 struct radv_extensions *extensions,
183 const VkExtensionProperties *new_ext,
184 uint32_t num_ext)
185 {
186 size_t new_size;
187 VkExtensionProperties *new_ptr;
188
189 assert(new_ext && num_ext > 0);
190
191 if (!new_ext)
192 return VK_ERROR_INITIALIZATION_FAILED;
193
194 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
195 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
196 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
197
198 /* Old array continues to be valid, update nothing */
199 if (!new_ptr)
200 return VK_ERROR_OUT_OF_HOST_MEMORY;
201
202 memcpy(&new_ptr[extensions->num_ext], new_ext,
203 num_ext * sizeof(VkExtensionProperties));
204 extensions->ext_array = new_ptr;
205 extensions->num_ext += num_ext;
206
207 return VK_SUCCESS;
208 }
209
210 static void
211 radv_extensions_finish(struct radv_instance *instance,
212 struct radv_extensions *extensions)
213 {
214 assert(extensions);
215
216 if (!extensions)
217 radv_loge("Attemted to free invalid extension struct\n");
218
219 if (extensions->ext_array)
220 vk_free(&instance->alloc, extensions->ext_array);
221 }
222
223 static bool
224 is_extension_enabled(const VkExtensionProperties *extensions,
225 size_t num_ext,
226 const char *name)
227 {
228 assert(extensions && name);
229
230 for (uint32_t i = 0; i < num_ext; i++) {
231 if (strcmp(name, extensions[i].extensionName) == 0)
232 return true;
233 }
234
235 return false;
236 }
237
238 static const char *
239 get_chip_name(enum radeon_family family)
240 {
241 switch (family) {
242 case CHIP_TAHITI: return "AMD RADV TAHITI";
243 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
244 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
245 case CHIP_OLAND: return "AMD RADV OLAND";
246 case CHIP_HAINAN: return "AMD RADV HAINAN";
247 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
248 case CHIP_KAVERI: return "AMD RADV KAVERI";
249 case CHIP_KABINI: return "AMD RADV KABINI";
250 case CHIP_HAWAII: return "AMD RADV HAWAII";
251 case CHIP_MULLINS: return "AMD RADV MULLINS";
252 case CHIP_TONGA: return "AMD RADV TONGA";
253 case CHIP_ICELAND: return "AMD RADV ICELAND";
254 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
255 case CHIP_FIJI: return "AMD RADV FIJI";
256 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
257 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
258 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
259 case CHIP_STONEY: return "AMD RADV STONEY";
260 case CHIP_VEGA10: return "AMD RADV VEGA";
261 case CHIP_RAVEN: return "AMD RADV RAVEN";
262 default: return "AMD RADV unknown";
263 }
264 }
265
266 static VkResult
267 radv_physical_device_init(struct radv_physical_device *device,
268 struct radv_instance *instance,
269 drmDevicePtr drm_device)
270 {
271 const char *path = drm_device->nodes[DRM_NODE_RENDER];
272 VkResult result;
273 drmVersionPtr version;
274 int fd;
275
276 fd = open(path, O_RDWR | O_CLOEXEC);
277 if (fd < 0)
278 return VK_ERROR_INCOMPATIBLE_DRIVER;
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
284 "failed to get version %s: %m", path);
285 }
286
287 if (strcmp(version->name, "amdgpu")) {
288 drmFreeVersion(version);
289 close(fd);
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
295 device->instance = instance;
296 assert(strlen(path) < ARRAY_SIZE(device->path));
297 strncpy(device->path, path, ARRAY_SIZE(device->path));
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = VK_ERROR_INCOMPATIBLE_DRIVER;
303 goto fail;
304 }
305
306 device->local_fd = fd;
307 device->ws->query_info(device->ws, &device->rad_info);
308 result = radv_init_wsi(device);
309 if (result != VK_SUCCESS) {
310 device->ws->destroy(device->ws);
311 goto fail;
312 }
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 radv_finish_wsi(device);
316 device->ws->destroy(device->ws);
317 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 result = radv_extensions_register(instance,
323 &device->extensions,
324 common_device_extensions,
325 ARRAY_SIZE(common_device_extensions));
326 if (result != VK_SUCCESS)
327 goto fail;
328
329 if (device->rad_info.has_syncobj) {
330 result = radv_extensions_register(instance,
331 &device->extensions,
332 ext_sema_device_extensions,
333 ARRAY_SIZE(ext_sema_device_extensions));
334 if (result != VK_SUCCESS)
335 goto fail;
336 }
337
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 device->name = get_chip_name(device->rad_info.family);
340
341 radv_get_device_uuid(drm_device, device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
347 }
348
349 return VK_SUCCESS;
350
351 fail:
352 close(fd);
353 return result;
354 }
355
356 static void
357 radv_physical_device_finish(struct radv_physical_device *device)
358 {
359 radv_extensions_finish(device->instance, &device->extensions);
360 radv_finish_wsi(device);
361 device->ws->destroy(device->ws);
362 close(device->local_fd);
363 }
364
365 static void *
366 default_alloc_func(void *pUserData, size_t size, size_t align,
367 VkSystemAllocationScope allocationScope)
368 {
369 return malloc(size);
370 }
371
372 static void *
373 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
374 size_t align, VkSystemAllocationScope allocationScope)
375 {
376 return realloc(pOriginal, size);
377 }
378
379 static void
380 default_free_func(void *pUserData, void *pMemory)
381 {
382 free(pMemory);
383 }
384
385 static const VkAllocationCallbacks default_alloc = {
386 .pUserData = NULL,
387 .pfnAllocation = default_alloc_func,
388 .pfnReallocation = default_realloc_func,
389 .pfnFree = default_free_func,
390 };
391
392 static const struct debug_control radv_debug_options[] = {
393 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
394 {"nodcc", RADV_DEBUG_NO_DCC},
395 {"shaders", RADV_DEBUG_DUMP_SHADERS},
396 {"nocache", RADV_DEBUG_NO_CACHE},
397 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
398 {"nohiz", RADV_DEBUG_NO_HIZ},
399 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
400 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
401 {"allbos", RADV_DEBUG_ALL_BOS},
402 {"noibs", RADV_DEBUG_NO_IBS},
403 {NULL, 0}
404 };
405
406 static const struct debug_control radv_perftest_options[] = {
407 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
408 {"sisched", RADV_PERFTEST_SISCHED},
409 {NULL, 0}
410 };
411
412 VkResult radv_CreateInstance(
413 const VkInstanceCreateInfo* pCreateInfo,
414 const VkAllocationCallbacks* pAllocator,
415 VkInstance* pInstance)
416 {
417 struct radv_instance *instance;
418
419 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
420
421 uint32_t client_version;
422 if (pCreateInfo->pApplicationInfo &&
423 pCreateInfo->pApplicationInfo->apiVersion != 0) {
424 client_version = pCreateInfo->pApplicationInfo->apiVersion;
425 } else {
426 client_version = VK_MAKE_VERSION(1, 0, 0);
427 }
428
429 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
430 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
431 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
432 "Client requested version %d.%d.%d",
433 VK_VERSION_MAJOR(client_version),
434 VK_VERSION_MINOR(client_version),
435 VK_VERSION_PATCH(client_version));
436 }
437
438 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
439 if (!is_extension_enabled(instance_extensions,
440 ARRAY_SIZE(instance_extensions),
441 pCreateInfo->ppEnabledExtensionNames[i]))
442 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
443 }
444
445 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
446 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
447 if (!instance)
448 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
449
450 memset(instance, 0, sizeof(*instance));
451
452 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
453
454 if (pAllocator)
455 instance->alloc = *pAllocator;
456 else
457 instance->alloc = default_alloc;
458
459 instance->apiVersion = client_version;
460 instance->physicalDeviceCount = -1;
461
462 _mesa_locale_init();
463
464 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
465
466 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
467 radv_debug_options);
468
469 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
470 radv_perftest_options);
471
472 *pInstance = radv_instance_to_handle(instance);
473
474 return VK_SUCCESS;
475 }
476
477 void radv_DestroyInstance(
478 VkInstance _instance,
479 const VkAllocationCallbacks* pAllocator)
480 {
481 RADV_FROM_HANDLE(radv_instance, instance, _instance);
482
483 if (!instance)
484 return;
485
486 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
487 radv_physical_device_finish(instance->physicalDevices + i);
488 }
489
490 VG(VALGRIND_DESTROY_MEMPOOL(instance));
491
492 _mesa_locale_fini();
493
494 vk_free(&instance->alloc, instance);
495 }
496
497 static VkResult
498 radv_enumerate_devices(struct radv_instance *instance)
499 {
500 /* TODO: Check for more devices ? */
501 drmDevicePtr devices[8];
502 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
503 int max_devices;
504
505 instance->physicalDeviceCount = 0;
506
507 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
508 if (max_devices < 1)
509 return VK_ERROR_INCOMPATIBLE_DRIVER;
510
511 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
512 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
513 devices[i]->bustype == DRM_BUS_PCI &&
514 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
515
516 result = radv_physical_device_init(instance->physicalDevices +
517 instance->physicalDeviceCount,
518 instance,
519 devices[i]);
520 if (result == VK_SUCCESS)
521 ++instance->physicalDeviceCount;
522 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
523 break;
524 }
525 }
526 drmFreeDevices(devices, max_devices);
527
528 return result;
529 }
530
531 VkResult radv_EnumeratePhysicalDevices(
532 VkInstance _instance,
533 uint32_t* pPhysicalDeviceCount,
534 VkPhysicalDevice* pPhysicalDevices)
535 {
536 RADV_FROM_HANDLE(radv_instance, instance, _instance);
537 VkResult result;
538
539 if (instance->physicalDeviceCount < 0) {
540 result = radv_enumerate_devices(instance);
541 if (result != VK_SUCCESS &&
542 result != VK_ERROR_INCOMPATIBLE_DRIVER)
543 return result;
544 }
545
546 if (!pPhysicalDevices) {
547 *pPhysicalDeviceCount = instance->physicalDeviceCount;
548 } else {
549 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
550 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
551 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
552 }
553
554 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
555 : VK_SUCCESS;
556 }
557
558 void radv_GetPhysicalDeviceFeatures(
559 VkPhysicalDevice physicalDevice,
560 VkPhysicalDeviceFeatures* pFeatures)
561 {
562 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
563 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
564 memset(pFeatures, 0, sizeof(*pFeatures));
565
566 *pFeatures = (VkPhysicalDeviceFeatures) {
567 .robustBufferAccess = true,
568 .fullDrawIndexUint32 = true,
569 .imageCubeArray = true,
570 .independentBlend = true,
571 .geometryShader = !is_gfx9,
572 .tessellationShader = !is_gfx9,
573 .sampleRateShading = true,
574 .dualSrcBlend = true,
575 .logicOp = true,
576 .multiDrawIndirect = true,
577 .drawIndirectFirstInstance = true,
578 .depthClamp = true,
579 .depthBiasClamp = true,
580 .fillModeNonSolid = true,
581 .depthBounds = true,
582 .wideLines = true,
583 .largePoints = true,
584 .alphaToOne = true,
585 .multiViewport = true,
586 .samplerAnisotropy = true,
587 .textureCompressionETC2 = false,
588 .textureCompressionASTC_LDR = false,
589 .textureCompressionBC = true,
590 .occlusionQueryPrecise = true,
591 .pipelineStatisticsQuery = true,
592 .vertexPipelineStoresAndAtomics = true,
593 .fragmentStoresAndAtomics = true,
594 .shaderTessellationAndGeometryPointSize = true,
595 .shaderImageGatherExtended = true,
596 .shaderStorageImageExtendedFormats = true,
597 .shaderStorageImageMultisample = false,
598 .shaderUniformBufferArrayDynamicIndexing = true,
599 .shaderSampledImageArrayDynamicIndexing = true,
600 .shaderStorageBufferArrayDynamicIndexing = true,
601 .shaderStorageImageArrayDynamicIndexing = true,
602 .shaderStorageImageReadWithoutFormat = true,
603 .shaderStorageImageWriteWithoutFormat = true,
604 .shaderClipDistance = true,
605 .shaderCullDistance = true,
606 .shaderFloat64 = true,
607 .shaderInt64 = true,
608 .shaderInt16 = false,
609 .sparseBinding = true,
610 .variableMultisampleRate = true,
611 .inheritedQueries = true,
612 };
613 }
614
615 void radv_GetPhysicalDeviceFeatures2KHR(
616 VkPhysicalDevice physicalDevice,
617 VkPhysicalDeviceFeatures2KHR *pFeatures)
618 {
619 vk_foreach_struct(ext, pFeatures->pNext) {
620 switch (ext->sType) {
621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
622 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
623 features->variablePointersStorageBuffer = true;
624 features->variablePointers = false;
625 break;
626 }
627 default:
628 break;
629 }
630 }
631 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
632 }
633
634 void radv_GetPhysicalDeviceProperties(
635 VkPhysicalDevice physicalDevice,
636 VkPhysicalDeviceProperties* pProperties)
637 {
638 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
639 VkSampleCountFlags sample_counts = 0xf;
640
641 /* make sure that the entire descriptor set is addressable with a signed
642 * 32-bit int. So the sum of all limits scaled by descriptor size has to
643 * be at most 2 GiB. the combined image & samples object count as one of
644 * both. This limit is for the pipeline layout, not for the set layout, but
645 * there is no set limit, so we just set a pipeline limit. I don't think
646 * any app is going to hit this soon. */
647 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
648 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
649 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
650 32 /* sampler, largest when combined with image */ +
651 64 /* sampled image */ +
652 64 /* storage image */);
653
654 VkPhysicalDeviceLimits limits = {
655 .maxImageDimension1D = (1 << 14),
656 .maxImageDimension2D = (1 << 14),
657 .maxImageDimension3D = (1 << 11),
658 .maxImageDimensionCube = (1 << 14),
659 .maxImageArrayLayers = (1 << 11),
660 .maxTexelBufferElements = 128 * 1024 * 1024,
661 .maxUniformBufferRange = UINT32_MAX,
662 .maxStorageBufferRange = UINT32_MAX,
663 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
664 .maxMemoryAllocationCount = UINT32_MAX,
665 .maxSamplerAllocationCount = 64 * 1024,
666 .bufferImageGranularity = 64, /* A cache line */
667 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
668 .maxBoundDescriptorSets = MAX_SETS,
669 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
670 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
671 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
672 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
673 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
674 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
675 .maxPerStageResources = max_descriptor_set_size,
676 .maxDescriptorSetSamplers = max_descriptor_set_size,
677 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
678 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
679 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
680 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
681 .maxDescriptorSetSampledImages = max_descriptor_set_size,
682 .maxDescriptorSetStorageImages = max_descriptor_set_size,
683 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
684 .maxVertexInputAttributes = 32,
685 .maxVertexInputBindings = 32,
686 .maxVertexInputAttributeOffset = 2047,
687 .maxVertexInputBindingStride = 2048,
688 .maxVertexOutputComponents = 128,
689 .maxTessellationGenerationLevel = 64,
690 .maxTessellationPatchSize = 32,
691 .maxTessellationControlPerVertexInputComponents = 128,
692 .maxTessellationControlPerVertexOutputComponents = 128,
693 .maxTessellationControlPerPatchOutputComponents = 120,
694 .maxTessellationControlTotalOutputComponents = 4096,
695 .maxTessellationEvaluationInputComponents = 128,
696 .maxTessellationEvaluationOutputComponents = 128,
697 .maxGeometryShaderInvocations = 127,
698 .maxGeometryInputComponents = 64,
699 .maxGeometryOutputComponents = 128,
700 .maxGeometryOutputVertices = 256,
701 .maxGeometryTotalOutputComponents = 1024,
702 .maxFragmentInputComponents = 128,
703 .maxFragmentOutputAttachments = 8,
704 .maxFragmentDualSrcAttachments = 1,
705 .maxFragmentCombinedOutputResources = 8,
706 .maxComputeSharedMemorySize = 32768,
707 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
708 .maxComputeWorkGroupInvocations = 2048,
709 .maxComputeWorkGroupSize = {
710 2048,
711 2048,
712 2048
713 },
714 .subPixelPrecisionBits = 4 /* FIXME */,
715 .subTexelPrecisionBits = 4 /* FIXME */,
716 .mipmapPrecisionBits = 4 /* FIXME */,
717 .maxDrawIndexedIndexValue = UINT32_MAX,
718 .maxDrawIndirectCount = UINT32_MAX,
719 .maxSamplerLodBias = 16,
720 .maxSamplerAnisotropy = 16,
721 .maxViewports = MAX_VIEWPORTS,
722 .maxViewportDimensions = { (1 << 14), (1 << 14) },
723 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
724 .viewportSubPixelBits = 13, /* We take a float? */
725 .minMemoryMapAlignment = 4096, /* A page */
726 .minTexelBufferOffsetAlignment = 1,
727 .minUniformBufferOffsetAlignment = 4,
728 .minStorageBufferOffsetAlignment = 4,
729 .minTexelOffset = -32,
730 .maxTexelOffset = 31,
731 .minTexelGatherOffset = -32,
732 .maxTexelGatherOffset = 31,
733 .minInterpolationOffset = -2,
734 .maxInterpolationOffset = 2,
735 .subPixelInterpolationOffsetBits = 8,
736 .maxFramebufferWidth = (1 << 14),
737 .maxFramebufferHeight = (1 << 14),
738 .maxFramebufferLayers = (1 << 10),
739 .framebufferColorSampleCounts = sample_counts,
740 .framebufferDepthSampleCounts = sample_counts,
741 .framebufferStencilSampleCounts = sample_counts,
742 .framebufferNoAttachmentsSampleCounts = sample_counts,
743 .maxColorAttachments = MAX_RTS,
744 .sampledImageColorSampleCounts = sample_counts,
745 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
746 .sampledImageDepthSampleCounts = sample_counts,
747 .sampledImageStencilSampleCounts = sample_counts,
748 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
749 .maxSampleMaskWords = 1,
750 .timestampComputeAndGraphics = true,
751 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
752 .maxClipDistances = 8,
753 .maxCullDistances = 8,
754 .maxCombinedClipAndCullDistances = 8,
755 .discreteQueuePriorities = 1,
756 .pointSizeRange = { 0.125, 255.875 },
757 .lineWidthRange = { 0.0, 7.9921875 },
758 .pointSizeGranularity = (1.0 / 8.0),
759 .lineWidthGranularity = (1.0 / 128.0),
760 .strictLines = false, /* FINISHME */
761 .standardSampleLocations = true,
762 .optimalBufferCopyOffsetAlignment = 128,
763 .optimalBufferCopyRowPitchAlignment = 128,
764 .nonCoherentAtomSize = 64,
765 };
766
767 *pProperties = (VkPhysicalDeviceProperties) {
768 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
769 .driverVersion = vk_get_driver_version(),
770 .vendorID = 0x1002,
771 .deviceID = pdevice->rad_info.pci_id,
772 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
773 .limits = limits,
774 .sparseProperties = {0},
775 };
776
777 strcpy(pProperties->deviceName, pdevice->name);
778 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
779 }
780
781 void radv_GetPhysicalDeviceProperties2KHR(
782 VkPhysicalDevice physicalDevice,
783 VkPhysicalDeviceProperties2KHR *pProperties)
784 {
785 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
786 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
787
788 vk_foreach_struct(ext, pProperties->pNext) {
789 switch (ext->sType) {
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
791 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
792 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
793 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
797 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
798 radv_device_get_cache_uuid(0, properties->driverUUID);
799 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
800 properties->deviceLUIDValid = false;
801 break;
802 }
803 default:
804 break;
805 }
806 }
807 }
808
809 static void radv_get_physical_device_queue_family_properties(
810 struct radv_physical_device* pdevice,
811 uint32_t* pCount,
812 VkQueueFamilyProperties** pQueueFamilyProperties)
813 {
814 int num_queue_families = 1;
815 int idx;
816 if (pdevice->rad_info.num_compute_rings > 0 &&
817 pdevice->rad_info.chip_class >= CIK &&
818 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
819 num_queue_families++;
820
821 if (pQueueFamilyProperties == NULL) {
822 *pCount = num_queue_families;
823 return;
824 }
825
826 if (!*pCount)
827 return;
828
829 idx = 0;
830 if (*pCount >= 1) {
831 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
832 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
833 VK_QUEUE_COMPUTE_BIT |
834 VK_QUEUE_TRANSFER_BIT |
835 VK_QUEUE_SPARSE_BINDING_BIT,
836 .queueCount = 1,
837 .timestampValidBits = 64,
838 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
839 };
840 idx++;
841 }
842
843 if (pdevice->rad_info.num_compute_rings > 0 &&
844 pdevice->rad_info.chip_class >= CIK &&
845 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
846 if (*pCount > idx) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_COMPUTE_BIT |
849 VK_QUEUE_TRANSFER_BIT |
850 VK_QUEUE_SPARSE_BINDING_BIT,
851 .queueCount = pdevice->rad_info.num_compute_rings,
852 .timestampValidBits = 64,
853 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
854 };
855 idx++;
856 }
857 }
858 *pCount = idx;
859 }
860
861 void radv_GetPhysicalDeviceQueueFamilyProperties(
862 VkPhysicalDevice physicalDevice,
863 uint32_t* pCount,
864 VkQueueFamilyProperties* pQueueFamilyProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 if (!pQueueFamilyProperties) {
868 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
869 return;
870 }
871 VkQueueFamilyProperties *properties[] = {
872 pQueueFamilyProperties + 0,
873 pQueueFamilyProperties + 1,
874 pQueueFamilyProperties + 2,
875 };
876 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
877 assert(*pCount <= 3);
878 }
879
880 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
881 VkPhysicalDevice physicalDevice,
882 uint32_t* pCount,
883 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 if (!pQueueFamilyProperties) {
887 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
888 return;
889 }
890 VkQueueFamilyProperties *properties[] = {
891 &pQueueFamilyProperties[0].queueFamilyProperties,
892 &pQueueFamilyProperties[1].queueFamilyProperties,
893 &pQueueFamilyProperties[2].queueFamilyProperties,
894 };
895 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
896 assert(*pCount <= 3);
897 }
898
899 void radv_GetPhysicalDeviceMemoryProperties(
900 VkPhysicalDevice physicalDevice,
901 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
902 {
903 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
904
905 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
906
907 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
908 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
909 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
910 .heapIndex = RADV_MEM_HEAP_VRAM,
911 };
912 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
913 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
914 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
915 .heapIndex = RADV_MEM_HEAP_GTT,
916 };
917 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
918 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
919 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
920 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
921 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
922 };
923 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
924 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
925 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
926 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
927 .heapIndex = RADV_MEM_HEAP_GTT,
928 };
929
930 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
931
932 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
933 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
934 .size = physical_device->rad_info.vram_size -
935 physical_device->rad_info.vram_vis_size,
936 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
937 };
938 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
939 .size = physical_device->rad_info.vram_vis_size,
940 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
941 };
942 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
943 .size = physical_device->rad_info.gart_size,
944 .flags = 0,
945 };
946 }
947
948 void radv_GetPhysicalDeviceMemoryProperties2KHR(
949 VkPhysicalDevice physicalDevice,
950 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
951 {
952 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
953 &pMemoryProperties->memoryProperties);
954 }
955
956 static int
957 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
958 int queue_family_index, int idx)
959 {
960 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
961 queue->device = device;
962 queue->queue_family_index = queue_family_index;
963 queue->queue_idx = idx;
964
965 queue->hw_ctx = device->ws->ctx_create(device->ws);
966 if (!queue->hw_ctx)
967 return VK_ERROR_OUT_OF_HOST_MEMORY;
968
969 return VK_SUCCESS;
970 }
971
972 static void
973 radv_queue_finish(struct radv_queue *queue)
974 {
975 if (queue->hw_ctx)
976 queue->device->ws->ctx_destroy(queue->hw_ctx);
977
978 if (queue->initial_preamble_cs)
979 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
980 if (queue->continue_preamble_cs)
981 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
982 if (queue->descriptor_bo)
983 queue->device->ws->buffer_destroy(queue->descriptor_bo);
984 if (queue->scratch_bo)
985 queue->device->ws->buffer_destroy(queue->scratch_bo);
986 if (queue->esgs_ring_bo)
987 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
988 if (queue->gsvs_ring_bo)
989 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
990 if (queue->tess_factor_ring_bo)
991 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
992 if (queue->tess_offchip_ring_bo)
993 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
994 if (queue->compute_scratch_bo)
995 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
996 }
997
998 static void
999 radv_device_init_gs_info(struct radv_device *device)
1000 {
1001 switch (device->physical_device->rad_info.family) {
1002 case CHIP_OLAND:
1003 case CHIP_HAINAN:
1004 case CHIP_KAVERI:
1005 case CHIP_KABINI:
1006 case CHIP_MULLINS:
1007 case CHIP_ICELAND:
1008 case CHIP_CARRIZO:
1009 case CHIP_STONEY:
1010 device->gs_table_depth = 16;
1011 return;
1012 case CHIP_TAHITI:
1013 case CHIP_PITCAIRN:
1014 case CHIP_VERDE:
1015 case CHIP_BONAIRE:
1016 case CHIP_HAWAII:
1017 case CHIP_TONGA:
1018 case CHIP_FIJI:
1019 case CHIP_POLARIS10:
1020 case CHIP_POLARIS11:
1021 case CHIP_POLARIS12:
1022 case CHIP_VEGA10:
1023 case CHIP_RAVEN:
1024 device->gs_table_depth = 32;
1025 return;
1026 default:
1027 unreachable("unknown GPU");
1028 }
1029 }
1030
1031 VkResult radv_CreateDevice(
1032 VkPhysicalDevice physicalDevice,
1033 const VkDeviceCreateInfo* pCreateInfo,
1034 const VkAllocationCallbacks* pAllocator,
1035 VkDevice* pDevice)
1036 {
1037 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1038 VkResult result;
1039 struct radv_device *device;
1040
1041 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1042 if (!is_extension_enabled(physical_device->extensions.ext_array,
1043 physical_device->extensions.num_ext,
1044 pCreateInfo->ppEnabledExtensionNames[i]))
1045 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1046 }
1047
1048 /* Check enabled features */
1049 if (pCreateInfo->pEnabledFeatures) {
1050 VkPhysicalDeviceFeatures supported_features;
1051 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1052 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1053 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1054 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1055 for (uint32_t i = 0; i < num_features; i++) {
1056 if (enabled_feature[i] && !supported_feature[i])
1057 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1058 }
1059 }
1060
1061 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1062 sizeof(*device), 8,
1063 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1064 if (!device)
1065 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1066
1067 memset(device, 0, sizeof(*device));
1068
1069 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1070 device->instance = physical_device->instance;
1071 device->physical_device = physical_device;
1072
1073 device->debug_flags = device->instance->debug_flags;
1074
1075 device->ws = physical_device->ws;
1076 if (pAllocator)
1077 device->alloc = *pAllocator;
1078 else
1079 device->alloc = physical_device->instance->alloc;
1080
1081 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1082 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1083 uint32_t qfi = queue_create->queueFamilyIndex;
1084
1085 device->queues[qfi] = vk_alloc(&device->alloc,
1086 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1087 if (!device->queues[qfi]) {
1088 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1089 goto fail;
1090 }
1091
1092 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1093
1094 device->queue_count[qfi] = queue_create->queueCount;
1095
1096 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1097 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1098 if (result != VK_SUCCESS)
1099 goto fail;
1100 }
1101 }
1102
1103 #if HAVE_LLVM < 0x0400
1104 device->llvm_supports_spill = false;
1105 #else
1106 device->llvm_supports_spill = true;
1107 #endif
1108
1109 /* The maximum number of scratch waves. Scratch space isn't divided
1110 * evenly between CUs. The number is only a function of the number of CUs.
1111 * We can decrease the constant to decrease the scratch buffer size.
1112 *
1113 * sctx->scratch_waves must be >= the maximum posible size of
1114 * 1 threadgroup, so that the hw doesn't hang from being unable
1115 * to start any.
1116 *
1117 * The recommended value is 4 per CU at most. Higher numbers don't
1118 * bring much benefit, but they still occupy chip resources (think
1119 * async compute). I've seen ~2% performance difference between 4 and 32.
1120 */
1121 uint32_t max_threads_per_block = 2048;
1122 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1123 max_threads_per_block / 64);
1124
1125 radv_device_init_gs_info(device);
1126
1127 device->tess_offchip_block_dw_size =
1128 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1129 device->has_distributed_tess =
1130 device->physical_device->rad_info.chip_class >= VI &&
1131 device->physical_device->rad_info.max_se >= 2;
1132
1133 result = radv_device_init_meta(device);
1134 if (result != VK_SUCCESS)
1135 goto fail;
1136
1137 radv_device_init_msaa(device);
1138
1139 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1140 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1141 switch (family) {
1142 case RADV_QUEUE_GENERAL:
1143 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1144 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1145 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1146 break;
1147 case RADV_QUEUE_COMPUTE:
1148 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1149 radeon_emit(device->empty_cs[family], 0);
1150 break;
1151 }
1152 device->ws->cs_finalize(device->empty_cs[family]);
1153
1154 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1155 switch (family) {
1156 case RADV_QUEUE_GENERAL:
1157 case RADV_QUEUE_COMPUTE:
1158 si_cs_emit_cache_flush(device->flush_cs[family],
1159 false,
1160 device->physical_device->rad_info.chip_class,
1161 NULL, 0,
1162 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1163 RADV_CMD_FLAG_INV_ICACHE |
1164 RADV_CMD_FLAG_INV_SMEM_L1 |
1165 RADV_CMD_FLAG_INV_VMEM_L1 |
1166 RADV_CMD_FLAG_INV_GLOBAL_L2);
1167 break;
1168 }
1169 device->ws->cs_finalize(device->flush_cs[family]);
1170
1171 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1172 switch (family) {
1173 case RADV_QUEUE_GENERAL:
1174 case RADV_QUEUE_COMPUTE:
1175 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1176 false,
1177 device->physical_device->rad_info.chip_class,
1178 NULL, 0,
1179 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1180 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1181 RADV_CMD_FLAG_INV_ICACHE |
1182 RADV_CMD_FLAG_INV_SMEM_L1 |
1183 RADV_CMD_FLAG_INV_VMEM_L1 |
1184 RADV_CMD_FLAG_INV_GLOBAL_L2);
1185 break;
1186 }
1187 device->ws->cs_finalize(device->flush_shader_cs[family]);
1188 }
1189
1190 if (getenv("RADV_TRACE_FILE")) {
1191 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1192 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1193 if (!device->trace_bo)
1194 goto fail;
1195
1196 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1197 if (!device->trace_id_ptr)
1198 goto fail;
1199 }
1200
1201 if (device->physical_device->rad_info.chip_class >= CIK)
1202 cik_create_gfx_config(device);
1203
1204 VkPipelineCacheCreateInfo ci;
1205 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1206 ci.pNext = NULL;
1207 ci.flags = 0;
1208 ci.pInitialData = NULL;
1209 ci.initialDataSize = 0;
1210 VkPipelineCache pc;
1211 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1212 &ci, NULL, &pc);
1213 if (result != VK_SUCCESS)
1214 goto fail;
1215
1216 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1217
1218 *pDevice = radv_device_to_handle(device);
1219 return VK_SUCCESS;
1220
1221 fail:
1222 if (device->trace_bo)
1223 device->ws->buffer_destroy(device->trace_bo);
1224
1225 if (device->gfx_init)
1226 device->ws->buffer_destroy(device->gfx_init);
1227
1228 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1229 for (unsigned q = 0; q < device->queue_count[i]; q++)
1230 radv_queue_finish(&device->queues[i][q]);
1231 if (device->queue_count[i])
1232 vk_free(&device->alloc, device->queues[i]);
1233 }
1234
1235 vk_free(&device->alloc, device);
1236 return result;
1237 }
1238
1239 void radv_DestroyDevice(
1240 VkDevice _device,
1241 const VkAllocationCallbacks* pAllocator)
1242 {
1243 RADV_FROM_HANDLE(radv_device, device, _device);
1244
1245 if (!device)
1246 return;
1247
1248 if (device->trace_bo)
1249 device->ws->buffer_destroy(device->trace_bo);
1250
1251 if (device->gfx_init)
1252 device->ws->buffer_destroy(device->gfx_init);
1253
1254 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1255 for (unsigned q = 0; q < device->queue_count[i]; q++)
1256 radv_queue_finish(&device->queues[i][q]);
1257 if (device->queue_count[i])
1258 vk_free(&device->alloc, device->queues[i]);
1259 if (device->empty_cs[i])
1260 device->ws->cs_destroy(device->empty_cs[i]);
1261 if (device->flush_cs[i])
1262 device->ws->cs_destroy(device->flush_cs[i]);
1263 if (device->flush_shader_cs[i])
1264 device->ws->cs_destroy(device->flush_shader_cs[i]);
1265 }
1266 radv_device_finish_meta(device);
1267
1268 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1269 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1270
1271 vk_free(&device->alloc, device);
1272 }
1273
1274 VkResult radv_EnumerateInstanceExtensionProperties(
1275 const char* pLayerName,
1276 uint32_t* pPropertyCount,
1277 VkExtensionProperties* pProperties)
1278 {
1279 if (pProperties == NULL) {
1280 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1281 return VK_SUCCESS;
1282 }
1283
1284 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1285 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1286
1287 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1288 return VK_INCOMPLETE;
1289
1290 return VK_SUCCESS;
1291 }
1292
1293 VkResult radv_EnumerateDeviceExtensionProperties(
1294 VkPhysicalDevice physicalDevice,
1295 const char* pLayerName,
1296 uint32_t* pPropertyCount,
1297 VkExtensionProperties* pProperties)
1298 {
1299 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1300
1301 if (pProperties == NULL) {
1302 *pPropertyCount = pdevice->extensions.num_ext;
1303 return VK_SUCCESS;
1304 }
1305
1306 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1307 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1308
1309 if (*pPropertyCount < pdevice->extensions.num_ext)
1310 return VK_INCOMPLETE;
1311
1312 return VK_SUCCESS;
1313 }
1314
1315 VkResult radv_EnumerateInstanceLayerProperties(
1316 uint32_t* pPropertyCount,
1317 VkLayerProperties* pProperties)
1318 {
1319 if (pProperties == NULL) {
1320 *pPropertyCount = 0;
1321 return VK_SUCCESS;
1322 }
1323
1324 /* None supported at this time */
1325 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1326 }
1327
1328 VkResult radv_EnumerateDeviceLayerProperties(
1329 VkPhysicalDevice physicalDevice,
1330 uint32_t* pPropertyCount,
1331 VkLayerProperties* pProperties)
1332 {
1333 if (pProperties == NULL) {
1334 *pPropertyCount = 0;
1335 return VK_SUCCESS;
1336 }
1337
1338 /* None supported at this time */
1339 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1340 }
1341
1342 void radv_GetDeviceQueue(
1343 VkDevice _device,
1344 uint32_t queueFamilyIndex,
1345 uint32_t queueIndex,
1346 VkQueue* pQueue)
1347 {
1348 RADV_FROM_HANDLE(radv_device, device, _device);
1349
1350 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1351 }
1352
1353 static void radv_dump_trace(struct radv_device *device,
1354 struct radeon_winsys_cs *cs)
1355 {
1356 const char *filename = getenv("RADV_TRACE_FILE");
1357 FILE *f = fopen(filename, "w");
1358 if (!f) {
1359 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1360 return;
1361 }
1362
1363 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1364 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1365 fclose(f);
1366 }
1367
1368 static void
1369 fill_geom_tess_rings(struct radv_queue *queue,
1370 uint32_t *map,
1371 bool add_sample_positions,
1372 uint32_t esgs_ring_size,
1373 struct radeon_winsys_bo *esgs_ring_bo,
1374 uint32_t gsvs_ring_size,
1375 struct radeon_winsys_bo *gsvs_ring_bo,
1376 uint32_t tess_factor_ring_size,
1377 struct radeon_winsys_bo *tess_factor_ring_bo,
1378 uint32_t tess_offchip_ring_size,
1379 struct radeon_winsys_bo *tess_offchip_ring_bo)
1380 {
1381 uint64_t esgs_va = 0, gsvs_va = 0;
1382 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1383 uint32_t *desc = &map[4];
1384
1385 if (esgs_ring_bo)
1386 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1387 if (gsvs_ring_bo)
1388 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1389 if (tess_factor_ring_bo)
1390 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1391 if (tess_offchip_ring_bo)
1392 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1393
1394 /* stride 0, num records - size, add tid, swizzle, elsize4,
1395 index stride 64 */
1396 desc[0] = esgs_va;
1397 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1398 S_008F04_STRIDE(0) |
1399 S_008F04_SWIZZLE_ENABLE(true);
1400 desc[2] = esgs_ring_size;
1401 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1402 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1403 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1404 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1405 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1406 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1407 S_008F0C_ELEMENT_SIZE(1) |
1408 S_008F0C_INDEX_STRIDE(3) |
1409 S_008F0C_ADD_TID_ENABLE(true);
1410
1411 desc += 4;
1412 /* GS entry for ES->GS ring */
1413 /* stride 0, num records - size, elsize0,
1414 index stride 0 */
1415 desc[0] = esgs_va;
1416 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1417 S_008F04_STRIDE(0) |
1418 S_008F04_SWIZZLE_ENABLE(false);
1419 desc[2] = esgs_ring_size;
1420 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1421 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1422 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1423 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1424 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1425 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1426 S_008F0C_ELEMENT_SIZE(0) |
1427 S_008F0C_INDEX_STRIDE(0) |
1428 S_008F0C_ADD_TID_ENABLE(false);
1429
1430 desc += 4;
1431 /* VS entry for GS->VS ring */
1432 /* stride 0, num records - size, elsize0,
1433 index stride 0 */
1434 desc[0] = gsvs_va;
1435 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1436 S_008F04_STRIDE(0) |
1437 S_008F04_SWIZZLE_ENABLE(false);
1438 desc[2] = gsvs_ring_size;
1439 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1440 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1441 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1442 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1443 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1444 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1445 S_008F0C_ELEMENT_SIZE(0) |
1446 S_008F0C_INDEX_STRIDE(0) |
1447 S_008F0C_ADD_TID_ENABLE(false);
1448 desc += 4;
1449
1450 /* stride gsvs_itemsize, num records 64
1451 elsize 4, index stride 16 */
1452 /* shader will patch stride and desc[2] */
1453 desc[0] = gsvs_va;
1454 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1455 S_008F04_STRIDE(0) |
1456 S_008F04_SWIZZLE_ENABLE(true);
1457 desc[2] = 0;
1458 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1459 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1460 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1461 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1462 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1463 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1464 S_008F0C_ELEMENT_SIZE(1) |
1465 S_008F0C_INDEX_STRIDE(1) |
1466 S_008F0C_ADD_TID_ENABLE(true);
1467 desc += 4;
1468
1469 desc[0] = tess_factor_va;
1470 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1471 S_008F04_STRIDE(0) |
1472 S_008F04_SWIZZLE_ENABLE(false);
1473 desc[2] = tess_factor_ring_size;
1474 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1475 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1476 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1477 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1478 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1479 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1480 S_008F0C_ELEMENT_SIZE(0) |
1481 S_008F0C_INDEX_STRIDE(0) |
1482 S_008F0C_ADD_TID_ENABLE(false);
1483 desc += 4;
1484
1485 desc[0] = tess_offchip_va;
1486 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1487 S_008F04_STRIDE(0) |
1488 S_008F04_SWIZZLE_ENABLE(false);
1489 desc[2] = tess_offchip_ring_size;
1490 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1491 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1492 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1493 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1494 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1495 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1496 S_008F0C_ELEMENT_SIZE(0) |
1497 S_008F0C_INDEX_STRIDE(0) |
1498 S_008F0C_ADD_TID_ENABLE(false);
1499 desc += 4;
1500
1501 /* add sample positions after all rings */
1502 memcpy(desc, queue->device->sample_locations_1x, 8);
1503 desc += 2;
1504 memcpy(desc, queue->device->sample_locations_2x, 16);
1505 desc += 4;
1506 memcpy(desc, queue->device->sample_locations_4x, 32);
1507 desc += 8;
1508 memcpy(desc, queue->device->sample_locations_8x, 64);
1509 desc += 16;
1510 memcpy(desc, queue->device->sample_locations_16x, 128);
1511 }
1512
1513 static unsigned
1514 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1515 {
1516 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1517 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1518 device->physical_device->rad_info.family != CHIP_STONEY;
1519 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1520 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1521 device->physical_device->rad_info.max_se;
1522 unsigned offchip_granularity;
1523 unsigned hs_offchip_param;
1524 switch (device->tess_offchip_block_dw_size) {
1525 default:
1526 assert(0);
1527 /* fall through */
1528 case 8192:
1529 offchip_granularity = V_03093C_X_8K_DWORDS;
1530 break;
1531 case 4096:
1532 offchip_granularity = V_03093C_X_4K_DWORDS;
1533 break;
1534 }
1535
1536 switch (device->physical_device->rad_info.chip_class) {
1537 case SI:
1538 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1539 break;
1540 case CIK:
1541 case VI:
1542 case GFX9:
1543 default:
1544 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1545 break;
1546 }
1547
1548 *max_offchip_buffers_p = max_offchip_buffers;
1549 if (device->physical_device->rad_info.chip_class >= CIK) {
1550 if (device->physical_device->rad_info.chip_class >= VI)
1551 --max_offchip_buffers;
1552 hs_offchip_param =
1553 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1554 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1555 } else {
1556 hs_offchip_param =
1557 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1558 }
1559 return hs_offchip_param;
1560 }
1561
1562 static VkResult
1563 radv_get_preamble_cs(struct radv_queue *queue,
1564 uint32_t scratch_size,
1565 uint32_t compute_scratch_size,
1566 uint32_t esgs_ring_size,
1567 uint32_t gsvs_ring_size,
1568 bool needs_tess_rings,
1569 bool needs_sample_positions,
1570 struct radeon_winsys_cs **initial_preamble_cs,
1571 struct radeon_winsys_cs **continue_preamble_cs)
1572 {
1573 struct radeon_winsys_bo *scratch_bo = NULL;
1574 struct radeon_winsys_bo *descriptor_bo = NULL;
1575 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1576 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1577 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1578 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1579 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1580 struct radeon_winsys_cs *dest_cs[2] = {0};
1581 bool add_tess_rings = false, add_sample_positions = false;
1582 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1583 unsigned max_offchip_buffers;
1584 unsigned hs_offchip_param = 0;
1585 if (!queue->has_tess_rings) {
1586 if (needs_tess_rings)
1587 add_tess_rings = true;
1588 }
1589 if (!queue->has_sample_positions) {
1590 if (needs_sample_positions)
1591 add_sample_positions = true;
1592 }
1593 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1594 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1595 &max_offchip_buffers);
1596 tess_offchip_ring_size = max_offchip_buffers *
1597 queue->device->tess_offchip_block_dw_size * 4;
1598
1599 if (scratch_size <= queue->scratch_size &&
1600 compute_scratch_size <= queue->compute_scratch_size &&
1601 esgs_ring_size <= queue->esgs_ring_size &&
1602 gsvs_ring_size <= queue->gsvs_ring_size &&
1603 !add_tess_rings && !add_sample_positions &&
1604 queue->initial_preamble_cs) {
1605 *initial_preamble_cs = queue->initial_preamble_cs;
1606 *continue_preamble_cs = queue->continue_preamble_cs;
1607 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1608 *continue_preamble_cs = NULL;
1609 return VK_SUCCESS;
1610 }
1611
1612 if (scratch_size > queue->scratch_size) {
1613 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1614 scratch_size,
1615 4096,
1616 RADEON_DOMAIN_VRAM,
1617 RADEON_FLAG_NO_CPU_ACCESS);
1618 if (!scratch_bo)
1619 goto fail;
1620 } else
1621 scratch_bo = queue->scratch_bo;
1622
1623 if (compute_scratch_size > queue->compute_scratch_size) {
1624 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1625 compute_scratch_size,
1626 4096,
1627 RADEON_DOMAIN_VRAM,
1628 RADEON_FLAG_NO_CPU_ACCESS);
1629 if (!compute_scratch_bo)
1630 goto fail;
1631
1632 } else
1633 compute_scratch_bo = queue->compute_scratch_bo;
1634
1635 if (esgs_ring_size > queue->esgs_ring_size) {
1636 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1637 esgs_ring_size,
1638 4096,
1639 RADEON_DOMAIN_VRAM,
1640 RADEON_FLAG_NO_CPU_ACCESS);
1641 if (!esgs_ring_bo)
1642 goto fail;
1643 } else {
1644 esgs_ring_bo = queue->esgs_ring_bo;
1645 esgs_ring_size = queue->esgs_ring_size;
1646 }
1647
1648 if (gsvs_ring_size > queue->gsvs_ring_size) {
1649 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1650 gsvs_ring_size,
1651 4096,
1652 RADEON_DOMAIN_VRAM,
1653 RADEON_FLAG_NO_CPU_ACCESS);
1654 if (!gsvs_ring_bo)
1655 goto fail;
1656 } else {
1657 gsvs_ring_bo = queue->gsvs_ring_bo;
1658 gsvs_ring_size = queue->gsvs_ring_size;
1659 }
1660
1661 if (add_tess_rings) {
1662 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1663 tess_factor_ring_size,
1664 256,
1665 RADEON_DOMAIN_VRAM,
1666 RADEON_FLAG_NO_CPU_ACCESS);
1667 if (!tess_factor_ring_bo)
1668 goto fail;
1669 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1670 tess_offchip_ring_size,
1671 256,
1672 RADEON_DOMAIN_VRAM,
1673 RADEON_FLAG_NO_CPU_ACCESS);
1674 if (!tess_offchip_ring_bo)
1675 goto fail;
1676 } else {
1677 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1678 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1679 }
1680
1681 if (scratch_bo != queue->scratch_bo ||
1682 esgs_ring_bo != queue->esgs_ring_bo ||
1683 gsvs_ring_bo != queue->gsvs_ring_bo ||
1684 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1685 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1686 uint32_t size = 0;
1687 if (gsvs_ring_bo || esgs_ring_bo ||
1688 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1689 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1690 if (add_sample_positions)
1691 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1692 }
1693 else if (scratch_bo)
1694 size = 8; /* 2 dword */
1695
1696 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1697 size,
1698 4096,
1699 RADEON_DOMAIN_VRAM,
1700 RADEON_FLAG_CPU_ACCESS);
1701 if (!descriptor_bo)
1702 goto fail;
1703 } else
1704 descriptor_bo = queue->descriptor_bo;
1705
1706 for(int i = 0; i < 2; ++i) {
1707 struct radeon_winsys_cs *cs = NULL;
1708 cs = queue->device->ws->cs_create(queue->device->ws,
1709 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1710 if (!cs)
1711 goto fail;
1712
1713 dest_cs[i] = cs;
1714
1715 if (scratch_bo)
1716 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1717
1718 if (esgs_ring_bo)
1719 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1720
1721 if (gsvs_ring_bo)
1722 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1723
1724 if (tess_factor_ring_bo)
1725 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1726
1727 if (tess_offchip_ring_bo)
1728 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1729
1730 if (descriptor_bo)
1731 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1732
1733 if (descriptor_bo != queue->descriptor_bo) {
1734 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1735
1736 if (scratch_bo) {
1737 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1738 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1739 S_008F04_SWIZZLE_ENABLE(1);
1740 map[0] = scratch_va;
1741 map[1] = rsrc1;
1742 }
1743
1744 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1745 add_sample_positions)
1746 fill_geom_tess_rings(queue, map, add_sample_positions,
1747 esgs_ring_size, esgs_ring_bo,
1748 gsvs_ring_size, gsvs_ring_bo,
1749 tess_factor_ring_size, tess_factor_ring_bo,
1750 tess_offchip_ring_size, tess_offchip_ring_bo);
1751
1752 queue->device->ws->buffer_unmap(descriptor_bo);
1753 }
1754
1755 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1757 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1759 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1760 }
1761
1762 if (esgs_ring_bo || gsvs_ring_bo) {
1763 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1764 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1765 radeon_emit(cs, esgs_ring_size >> 8);
1766 radeon_emit(cs, gsvs_ring_size >> 8);
1767 } else {
1768 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1769 radeon_emit(cs, esgs_ring_size >> 8);
1770 radeon_emit(cs, gsvs_ring_size >> 8);
1771 }
1772 }
1773
1774 if (tess_factor_ring_bo) {
1775 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1776 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1777 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1778 S_030938_SIZE(tess_factor_ring_size / 4));
1779 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1780 tf_va >> 8);
1781 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1782 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1783 tf_va >> 40);
1784 }
1785 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1786 } else {
1787 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1788 S_008988_SIZE(tess_factor_ring_size / 4));
1789 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1790 tf_va >> 8);
1791 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1792 hs_offchip_param);
1793 }
1794 }
1795
1796 if (descriptor_bo) {
1797 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1798 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1799 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1800 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1801 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1802 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1803
1804 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1805
1806 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1807 radeon_set_sh_reg_seq(cs, regs[i], 2);
1808 radeon_emit(cs, va);
1809 radeon_emit(cs, va >> 32);
1810 }
1811 }
1812
1813 if (compute_scratch_bo) {
1814 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1815 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1816 S_008F04_SWIZZLE_ENABLE(1);
1817
1818 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1819
1820 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1821 radeon_emit(cs, scratch_va);
1822 radeon_emit(cs, rsrc1);
1823 }
1824
1825 if (!i) {
1826 si_cs_emit_cache_flush(cs,
1827 false,
1828 queue->device->physical_device->rad_info.chip_class,
1829 NULL, 0,
1830 queue->queue_family_index == RING_COMPUTE &&
1831 queue->device->physical_device->rad_info.chip_class >= CIK,
1832 RADV_CMD_FLAG_INV_ICACHE |
1833 RADV_CMD_FLAG_INV_SMEM_L1 |
1834 RADV_CMD_FLAG_INV_VMEM_L1 |
1835 RADV_CMD_FLAG_INV_GLOBAL_L2);
1836 }
1837
1838 if (!queue->device->ws->cs_finalize(cs))
1839 goto fail;
1840 }
1841
1842 if (queue->initial_preamble_cs)
1843 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1844
1845 if (queue->continue_preamble_cs)
1846 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1847
1848 queue->initial_preamble_cs = dest_cs[0];
1849 queue->continue_preamble_cs = dest_cs[1];
1850
1851 if (scratch_bo != queue->scratch_bo) {
1852 if (queue->scratch_bo)
1853 queue->device->ws->buffer_destroy(queue->scratch_bo);
1854 queue->scratch_bo = scratch_bo;
1855 queue->scratch_size = scratch_size;
1856 }
1857
1858 if (compute_scratch_bo != queue->compute_scratch_bo) {
1859 if (queue->compute_scratch_bo)
1860 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1861 queue->compute_scratch_bo = compute_scratch_bo;
1862 queue->compute_scratch_size = compute_scratch_size;
1863 }
1864
1865 if (esgs_ring_bo != queue->esgs_ring_bo) {
1866 if (queue->esgs_ring_bo)
1867 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1868 queue->esgs_ring_bo = esgs_ring_bo;
1869 queue->esgs_ring_size = esgs_ring_size;
1870 }
1871
1872 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1873 if (queue->gsvs_ring_bo)
1874 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1875 queue->gsvs_ring_bo = gsvs_ring_bo;
1876 queue->gsvs_ring_size = gsvs_ring_size;
1877 }
1878
1879 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1880 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1881 }
1882
1883 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1884 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1885 queue->has_tess_rings = true;
1886 }
1887
1888 if (descriptor_bo != queue->descriptor_bo) {
1889 if (queue->descriptor_bo)
1890 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1891
1892 queue->descriptor_bo = descriptor_bo;
1893 }
1894
1895 if (add_sample_positions)
1896 queue->has_sample_positions = true;
1897
1898 *initial_preamble_cs = queue->initial_preamble_cs;
1899 *continue_preamble_cs = queue->continue_preamble_cs;
1900 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1901 *continue_preamble_cs = NULL;
1902 return VK_SUCCESS;
1903 fail:
1904 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1905 if (dest_cs[i])
1906 queue->device->ws->cs_destroy(dest_cs[i]);
1907 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1908 queue->device->ws->buffer_destroy(descriptor_bo);
1909 if (scratch_bo && scratch_bo != queue->scratch_bo)
1910 queue->device->ws->buffer_destroy(scratch_bo);
1911 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1912 queue->device->ws->buffer_destroy(compute_scratch_bo);
1913 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1914 queue->device->ws->buffer_destroy(esgs_ring_bo);
1915 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1916 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1917 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1918 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1919 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1920 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1921 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1922 }
1923
1924 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1925 int num_sems,
1926 const VkSemaphore *sems,
1927 bool reset_temp)
1928 {
1929 int syncobj_idx = 0, sem_idx = 0;
1930
1931 if (num_sems == 0)
1932 return VK_SUCCESS;
1933 for (uint32_t i = 0; i < num_sems; i++) {
1934 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1935
1936 if (sem->temp_syncobj || sem->syncobj)
1937 counts->syncobj_count++;
1938 else
1939 counts->sem_count++;
1940 }
1941
1942 if (counts->syncobj_count) {
1943 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1944 if (!counts->syncobj)
1945 return VK_ERROR_OUT_OF_HOST_MEMORY;
1946 }
1947
1948 if (counts->sem_count) {
1949 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1950 if (!counts->sem) {
1951 free(counts->syncobj);
1952 return VK_ERROR_OUT_OF_HOST_MEMORY;
1953 }
1954 }
1955
1956 for (uint32_t i = 0; i < num_sems; i++) {
1957 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1958
1959 if (sem->temp_syncobj) {
1960 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1961 if (reset_temp) {
1962 /* after we wait on a temp import - drop it */
1963 sem->temp_syncobj = 0;
1964 }
1965 }
1966 else if (sem->syncobj)
1967 counts->syncobj[syncobj_idx++] = sem->syncobj;
1968 else {
1969 assert(sem->sem);
1970 counts->sem[sem_idx++] = sem->sem;
1971 }
1972 }
1973
1974 return VK_SUCCESS;
1975 }
1976
1977 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1978 {
1979 free(sem_info->wait.syncobj);
1980 free(sem_info->wait.sem);
1981 free(sem_info->signal.syncobj);
1982 free(sem_info->signal.sem);
1983 }
1984
1985 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1986 int num_wait_sems,
1987 const VkSemaphore *wait_sems,
1988 int num_signal_sems,
1989 const VkSemaphore *signal_sems)
1990 {
1991 VkResult ret;
1992 memset(sem_info, 0, sizeof(*sem_info));
1993
1994 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1995 if (ret)
1996 return ret;
1997 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1998 if (ret)
1999 radv_free_sem_info(sem_info);
2000
2001 /* caller can override these */
2002 sem_info->cs_emit_wait = true;
2003 sem_info->cs_emit_signal = true;
2004 return ret;
2005 }
2006
2007 VkResult radv_QueueSubmit(
2008 VkQueue _queue,
2009 uint32_t submitCount,
2010 const VkSubmitInfo* pSubmits,
2011 VkFence _fence)
2012 {
2013 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2014 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2015 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2016 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2017 int ret;
2018 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2019 uint32_t scratch_size = 0;
2020 uint32_t compute_scratch_size = 0;
2021 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2022 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
2023 VkResult result;
2024 bool fence_emitted = false;
2025 bool tess_rings_needed = false;
2026 bool sample_positions_needed = false;
2027
2028 /* Do this first so failing to allocate scratch buffers can't result in
2029 * partially executed submissions. */
2030 for (uint32_t i = 0; i < submitCount; i++) {
2031 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2033 pSubmits[i].pCommandBuffers[j]);
2034
2035 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2036 compute_scratch_size = MAX2(compute_scratch_size,
2037 cmd_buffer->compute_scratch_size_needed);
2038 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2039 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2040 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2041 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2042 }
2043 }
2044
2045 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2046 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2047 sample_positions_needed,
2048 &initial_preamble_cs, &continue_preamble_cs);
2049 if (result != VK_SUCCESS)
2050 return result;
2051
2052 for (uint32_t i = 0; i < submitCount; i++) {
2053 struct radeon_winsys_cs **cs_array;
2054 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2055 bool can_patch = !do_flush;
2056 uint32_t advance;
2057 struct radv_winsys_sem_info sem_info;
2058
2059 result = radv_alloc_sem_info(&sem_info,
2060 pSubmits[i].waitSemaphoreCount,
2061 pSubmits[i].pWaitSemaphores,
2062 pSubmits[i].signalSemaphoreCount,
2063 pSubmits[i].pSignalSemaphores);
2064 if (result != VK_SUCCESS)
2065 return result;
2066
2067 if (!pSubmits[i].commandBufferCount) {
2068 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2069 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2070 &queue->device->empty_cs[queue->queue_family_index],
2071 1, NULL, NULL,
2072 &sem_info,
2073 false, base_fence);
2074 if (ret) {
2075 radv_loge("failed to submit CS %d\n", i);
2076 abort();
2077 }
2078 fence_emitted = true;
2079 }
2080 radv_free_sem_info(&sem_info);
2081 continue;
2082 }
2083
2084 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2085 (pSubmits[i].commandBufferCount + do_flush));
2086
2087 if(do_flush)
2088 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
2089 queue->device->flush_shader_cs[queue->queue_family_index] :
2090 queue->device->flush_cs[queue->queue_family_index];
2091
2092 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2093 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2094 pSubmits[i].pCommandBuffers[j]);
2095 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2096
2097 cs_array[j + do_flush] = cmd_buffer->cs;
2098 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2099 can_patch = false;
2100 }
2101
2102 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
2103 advance = MIN2(max_cs_submission,
2104 pSubmits[i].commandBufferCount + do_flush - j);
2105
2106 if (queue->device->trace_bo)
2107 *queue->device->trace_id_ptr = 0;
2108
2109 sem_info.cs_emit_wait = j == 0;
2110 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount + do_flush;
2111
2112 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2113 advance, initial_preamble_cs, continue_preamble_cs,
2114 &sem_info,
2115 can_patch, base_fence);
2116
2117 if (ret) {
2118 radv_loge("failed to submit CS %d\n", i);
2119 abort();
2120 }
2121 fence_emitted = true;
2122 if (queue->device->trace_bo) {
2123 bool success = queue->device->ws->ctx_wait_idle(
2124 queue->hw_ctx,
2125 radv_queue_family_to_ring(
2126 queue->queue_family_index),
2127 queue->queue_idx);
2128
2129 if (!success) { /* Hang */
2130 radv_dump_trace(queue->device, cs_array[j]);
2131 abort();
2132 }
2133 }
2134 }
2135
2136 radv_free_sem_info(&sem_info);
2137 free(cs_array);
2138 }
2139
2140 if (fence) {
2141 if (!fence_emitted) {
2142 struct radv_winsys_sem_info sem_info = {0};
2143 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2144 &queue->device->empty_cs[queue->queue_family_index],
2145 1, NULL, NULL, &sem_info,
2146 false, base_fence);
2147 }
2148 fence->submitted = true;
2149 }
2150
2151 return VK_SUCCESS;
2152 }
2153
2154 VkResult radv_QueueWaitIdle(
2155 VkQueue _queue)
2156 {
2157 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2158
2159 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2160 radv_queue_family_to_ring(queue->queue_family_index),
2161 queue->queue_idx);
2162 return VK_SUCCESS;
2163 }
2164
2165 VkResult radv_DeviceWaitIdle(
2166 VkDevice _device)
2167 {
2168 RADV_FROM_HANDLE(radv_device, device, _device);
2169
2170 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2171 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2172 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2173 }
2174 }
2175 return VK_SUCCESS;
2176 }
2177
2178 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2179 VkInstance instance,
2180 const char* pName)
2181 {
2182 return radv_lookup_entrypoint(pName);
2183 }
2184
2185 /* The loader wants us to expose a second GetInstanceProcAddr function
2186 * to work around certain LD_PRELOAD issues seen in apps.
2187 */
2188 PUBLIC
2189 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2190 VkInstance instance,
2191 const char* pName);
2192
2193 PUBLIC
2194 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2195 VkInstance instance,
2196 const char* pName)
2197 {
2198 return radv_GetInstanceProcAddr(instance, pName);
2199 }
2200
2201 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2202 VkDevice device,
2203 const char* pName)
2204 {
2205 return radv_lookup_entrypoint(pName);
2206 }
2207
2208 bool radv_get_memory_fd(struct radv_device *device,
2209 struct radv_device_memory *memory,
2210 int *pFD)
2211 {
2212 struct radeon_bo_metadata metadata;
2213
2214 if (memory->image) {
2215 radv_init_metadata(device, memory->image, &metadata);
2216 device->ws->buffer_set_metadata(memory->bo, &metadata);
2217 }
2218
2219 return device->ws->buffer_get_fd(device->ws, memory->bo,
2220 pFD);
2221 }
2222
2223 VkResult radv_AllocateMemory(
2224 VkDevice _device,
2225 const VkMemoryAllocateInfo* pAllocateInfo,
2226 const VkAllocationCallbacks* pAllocator,
2227 VkDeviceMemory* pMem)
2228 {
2229 RADV_FROM_HANDLE(radv_device, device, _device);
2230 struct radv_device_memory *mem;
2231 VkResult result;
2232 enum radeon_bo_domain domain;
2233 uint32_t flags = 0;
2234
2235 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2236
2237 if (pAllocateInfo->allocationSize == 0) {
2238 /* Apparently, this is allowed */
2239 *pMem = VK_NULL_HANDLE;
2240 return VK_SUCCESS;
2241 }
2242
2243 const VkImportMemoryFdInfoKHR *import_info =
2244 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2245 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2246 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2247
2248 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2249 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2250 if (mem == NULL)
2251 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2252
2253 if (dedicate_info) {
2254 mem->image = radv_image_from_handle(dedicate_info->image);
2255 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2256 } else {
2257 mem->image = NULL;
2258 mem->buffer = NULL;
2259 }
2260
2261 if (import_info) {
2262 assert(import_info->handleType ==
2263 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2264 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2265 NULL, NULL);
2266 if (!mem->bo) {
2267 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2268 goto fail;
2269 } else {
2270 close(import_info->fd);
2271 goto out_success;
2272 }
2273 }
2274
2275 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2276 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2277 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2278 domain = RADEON_DOMAIN_GTT;
2279 else
2280 domain = RADEON_DOMAIN_VRAM;
2281
2282 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2283 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2284 else
2285 flags |= RADEON_FLAG_CPU_ACCESS;
2286
2287 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2288 flags |= RADEON_FLAG_GTT_WC;
2289
2290 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2291 domain, flags);
2292
2293 if (!mem->bo) {
2294 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2295 goto fail;
2296 }
2297 mem->type_index = pAllocateInfo->memoryTypeIndex;
2298 out_success:
2299 *pMem = radv_device_memory_to_handle(mem);
2300
2301 return VK_SUCCESS;
2302
2303 fail:
2304 vk_free2(&device->alloc, pAllocator, mem);
2305
2306 return result;
2307 }
2308
2309 void radv_FreeMemory(
2310 VkDevice _device,
2311 VkDeviceMemory _mem,
2312 const VkAllocationCallbacks* pAllocator)
2313 {
2314 RADV_FROM_HANDLE(radv_device, device, _device);
2315 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2316
2317 if (mem == NULL)
2318 return;
2319
2320 device->ws->buffer_destroy(mem->bo);
2321 mem->bo = NULL;
2322
2323 vk_free2(&device->alloc, pAllocator, mem);
2324 }
2325
2326 VkResult radv_MapMemory(
2327 VkDevice _device,
2328 VkDeviceMemory _memory,
2329 VkDeviceSize offset,
2330 VkDeviceSize size,
2331 VkMemoryMapFlags flags,
2332 void** ppData)
2333 {
2334 RADV_FROM_HANDLE(radv_device, device, _device);
2335 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2336
2337 if (mem == NULL) {
2338 *ppData = NULL;
2339 return VK_SUCCESS;
2340 }
2341
2342 *ppData = device->ws->buffer_map(mem->bo);
2343 if (*ppData) {
2344 *ppData += offset;
2345 return VK_SUCCESS;
2346 }
2347
2348 return VK_ERROR_MEMORY_MAP_FAILED;
2349 }
2350
2351 void radv_UnmapMemory(
2352 VkDevice _device,
2353 VkDeviceMemory _memory)
2354 {
2355 RADV_FROM_HANDLE(radv_device, device, _device);
2356 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2357
2358 if (mem == NULL)
2359 return;
2360
2361 device->ws->buffer_unmap(mem->bo);
2362 }
2363
2364 VkResult radv_FlushMappedMemoryRanges(
2365 VkDevice _device,
2366 uint32_t memoryRangeCount,
2367 const VkMappedMemoryRange* pMemoryRanges)
2368 {
2369 return VK_SUCCESS;
2370 }
2371
2372 VkResult radv_InvalidateMappedMemoryRanges(
2373 VkDevice _device,
2374 uint32_t memoryRangeCount,
2375 const VkMappedMemoryRange* pMemoryRanges)
2376 {
2377 return VK_SUCCESS;
2378 }
2379
2380 void radv_GetBufferMemoryRequirements(
2381 VkDevice device,
2382 VkBuffer _buffer,
2383 VkMemoryRequirements* pMemoryRequirements)
2384 {
2385 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2386
2387 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2388
2389 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2390 pMemoryRequirements->alignment = 4096;
2391 else
2392 pMemoryRequirements->alignment = 16;
2393
2394 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2395 }
2396
2397 void radv_GetBufferMemoryRequirements2KHR(
2398 VkDevice device,
2399 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2400 VkMemoryRequirements2KHR* pMemoryRequirements)
2401 {
2402 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2403 &pMemoryRequirements->memoryRequirements);
2404
2405 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2406 switch (ext->sType) {
2407 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2408 VkMemoryDedicatedRequirementsKHR *req =
2409 (VkMemoryDedicatedRequirementsKHR *) ext;
2410 req->requiresDedicatedAllocation = false;
2411 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2412 break;
2413 }
2414 default:
2415 break;
2416 }
2417 }
2418 }
2419
2420 void radv_GetImageMemoryRequirements(
2421 VkDevice device,
2422 VkImage _image,
2423 VkMemoryRequirements* pMemoryRequirements)
2424 {
2425 RADV_FROM_HANDLE(radv_image, image, _image);
2426
2427 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2428
2429 pMemoryRequirements->size = image->size;
2430 pMemoryRequirements->alignment = image->alignment;
2431 }
2432
2433 void radv_GetImageMemoryRequirements2KHR(
2434 VkDevice device,
2435 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2436 VkMemoryRequirements2KHR* pMemoryRequirements)
2437 {
2438 radv_GetImageMemoryRequirements(device, pInfo->image,
2439 &pMemoryRequirements->memoryRequirements);
2440
2441 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2442
2443 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2444 switch (ext->sType) {
2445 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2446 VkMemoryDedicatedRequirementsKHR *req =
2447 (VkMemoryDedicatedRequirementsKHR *) ext;
2448 req->requiresDedicatedAllocation = image->shareable;
2449 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2450 break;
2451 }
2452 default:
2453 break;
2454 }
2455 }
2456 }
2457
2458 void radv_GetImageSparseMemoryRequirements(
2459 VkDevice device,
2460 VkImage image,
2461 uint32_t* pSparseMemoryRequirementCount,
2462 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2463 {
2464 stub();
2465 }
2466
2467 void radv_GetImageSparseMemoryRequirements2KHR(
2468 VkDevice device,
2469 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2470 uint32_t* pSparseMemoryRequirementCount,
2471 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2472 {
2473 stub();
2474 }
2475
2476 void radv_GetDeviceMemoryCommitment(
2477 VkDevice device,
2478 VkDeviceMemory memory,
2479 VkDeviceSize* pCommittedMemoryInBytes)
2480 {
2481 *pCommittedMemoryInBytes = 0;
2482 }
2483
2484 VkResult radv_BindBufferMemory(
2485 VkDevice device,
2486 VkBuffer _buffer,
2487 VkDeviceMemory _memory,
2488 VkDeviceSize memoryOffset)
2489 {
2490 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2491 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2492
2493 if (mem) {
2494 buffer->bo = mem->bo;
2495 buffer->offset = memoryOffset;
2496 } else {
2497 buffer->bo = NULL;
2498 buffer->offset = 0;
2499 }
2500
2501 return VK_SUCCESS;
2502 }
2503
2504 VkResult radv_BindImageMemory(
2505 VkDevice device,
2506 VkImage _image,
2507 VkDeviceMemory _memory,
2508 VkDeviceSize memoryOffset)
2509 {
2510 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2511 RADV_FROM_HANDLE(radv_image, image, _image);
2512
2513 if (mem) {
2514 image->bo = mem->bo;
2515 image->offset = memoryOffset;
2516 } else {
2517 image->bo = NULL;
2518 image->offset = 0;
2519 }
2520
2521 return VK_SUCCESS;
2522 }
2523
2524
2525 static void
2526 radv_sparse_buffer_bind_memory(struct radv_device *device,
2527 const VkSparseBufferMemoryBindInfo *bind)
2528 {
2529 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2530
2531 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2532 struct radv_device_memory *mem = NULL;
2533
2534 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2535 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2536
2537 device->ws->buffer_virtual_bind(buffer->bo,
2538 bind->pBinds[i].resourceOffset,
2539 bind->pBinds[i].size,
2540 mem ? mem->bo : NULL,
2541 bind->pBinds[i].memoryOffset);
2542 }
2543 }
2544
2545 static void
2546 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2547 const VkSparseImageOpaqueMemoryBindInfo *bind)
2548 {
2549 RADV_FROM_HANDLE(radv_image, image, bind->image);
2550
2551 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2552 struct radv_device_memory *mem = NULL;
2553
2554 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2555 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2556
2557 device->ws->buffer_virtual_bind(image->bo,
2558 bind->pBinds[i].resourceOffset,
2559 bind->pBinds[i].size,
2560 mem ? mem->bo : NULL,
2561 bind->pBinds[i].memoryOffset);
2562 }
2563 }
2564
2565 VkResult radv_QueueBindSparse(
2566 VkQueue _queue,
2567 uint32_t bindInfoCount,
2568 const VkBindSparseInfo* pBindInfo,
2569 VkFence _fence)
2570 {
2571 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2572 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2573 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2574 bool fence_emitted = false;
2575
2576 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2577 struct radv_winsys_sem_info sem_info;
2578 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2579 radv_sparse_buffer_bind_memory(queue->device,
2580 pBindInfo[i].pBufferBinds + j);
2581 }
2582
2583 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2584 radv_sparse_image_opaque_bind_memory(queue->device,
2585 pBindInfo[i].pImageOpaqueBinds + j);
2586 }
2587
2588 VkResult result;
2589 result = radv_alloc_sem_info(&sem_info,
2590 pBindInfo[i].waitSemaphoreCount,
2591 pBindInfo[i].pWaitSemaphores,
2592 pBindInfo[i].signalSemaphoreCount,
2593 pBindInfo[i].pSignalSemaphores);
2594 if (result != VK_SUCCESS)
2595 return result;
2596
2597 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2598 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2599 &queue->device->empty_cs[queue->queue_family_index],
2600 1, NULL, NULL,
2601 &sem_info,
2602 false, base_fence);
2603 fence_emitted = true;
2604 if (fence)
2605 fence->submitted = true;
2606 }
2607
2608 radv_free_sem_info(&sem_info);
2609
2610 }
2611
2612 if (fence && !fence_emitted) {
2613 fence->signalled = true;
2614 }
2615
2616 return VK_SUCCESS;
2617 }
2618
2619 VkResult radv_CreateFence(
2620 VkDevice _device,
2621 const VkFenceCreateInfo* pCreateInfo,
2622 const VkAllocationCallbacks* pAllocator,
2623 VkFence* pFence)
2624 {
2625 RADV_FROM_HANDLE(radv_device, device, _device);
2626 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2627 sizeof(*fence), 8,
2628 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2629
2630 if (!fence)
2631 return VK_ERROR_OUT_OF_HOST_MEMORY;
2632
2633 memset(fence, 0, sizeof(*fence));
2634 fence->submitted = false;
2635 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2636 fence->fence = device->ws->create_fence();
2637 if (!fence->fence) {
2638 vk_free2(&device->alloc, pAllocator, fence);
2639 return VK_ERROR_OUT_OF_HOST_MEMORY;
2640 }
2641
2642 *pFence = radv_fence_to_handle(fence);
2643
2644 return VK_SUCCESS;
2645 }
2646
2647 void radv_DestroyFence(
2648 VkDevice _device,
2649 VkFence _fence,
2650 const VkAllocationCallbacks* pAllocator)
2651 {
2652 RADV_FROM_HANDLE(radv_device, device, _device);
2653 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2654
2655 if (!fence)
2656 return;
2657 device->ws->destroy_fence(fence->fence);
2658 vk_free2(&device->alloc, pAllocator, fence);
2659 }
2660
2661 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2662 {
2663 uint64_t current_time;
2664 struct timespec tv;
2665
2666 clock_gettime(CLOCK_MONOTONIC, &tv);
2667 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2668
2669 timeout = MIN2(UINT64_MAX - current_time, timeout);
2670
2671 return current_time + timeout;
2672 }
2673
2674 VkResult radv_WaitForFences(
2675 VkDevice _device,
2676 uint32_t fenceCount,
2677 const VkFence* pFences,
2678 VkBool32 waitAll,
2679 uint64_t timeout)
2680 {
2681 RADV_FROM_HANDLE(radv_device, device, _device);
2682 timeout = radv_get_absolute_timeout(timeout);
2683
2684 if (!waitAll && fenceCount > 1) {
2685 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2686 }
2687
2688 for (uint32_t i = 0; i < fenceCount; ++i) {
2689 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2690 bool expired = false;
2691
2692 if (fence->signalled)
2693 continue;
2694
2695 if (!fence->submitted)
2696 return VK_TIMEOUT;
2697
2698 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2699 if (!expired)
2700 return VK_TIMEOUT;
2701
2702 fence->signalled = true;
2703 }
2704
2705 return VK_SUCCESS;
2706 }
2707
2708 VkResult radv_ResetFences(VkDevice device,
2709 uint32_t fenceCount,
2710 const VkFence *pFences)
2711 {
2712 for (unsigned i = 0; i < fenceCount; ++i) {
2713 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2714 fence->submitted = fence->signalled = false;
2715 }
2716
2717 return VK_SUCCESS;
2718 }
2719
2720 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2721 {
2722 RADV_FROM_HANDLE(radv_device, device, _device);
2723 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2724
2725 if (fence->signalled)
2726 return VK_SUCCESS;
2727 if (!fence->submitted)
2728 return VK_NOT_READY;
2729
2730 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2731 return VK_NOT_READY;
2732
2733 return VK_SUCCESS;
2734 }
2735
2736
2737 // Queue semaphore functions
2738
2739 VkResult radv_CreateSemaphore(
2740 VkDevice _device,
2741 const VkSemaphoreCreateInfo* pCreateInfo,
2742 const VkAllocationCallbacks* pAllocator,
2743 VkSemaphore* pSemaphore)
2744 {
2745 RADV_FROM_HANDLE(radv_device, device, _device);
2746 const VkExportSemaphoreCreateInfoKHR *export =
2747 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2748 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2749 export ? export->handleTypes : 0;
2750
2751 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2752 sizeof(*sem), 8,
2753 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2754 if (!sem)
2755 return VK_ERROR_OUT_OF_HOST_MEMORY;
2756
2757 sem->temp_syncobj = 0;
2758 /* create a syncobject if we are going to export this semaphore */
2759 if (handleTypes) {
2760 assert (device->physical_device->rad_info.has_syncobj);
2761 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2762 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2763 if (ret) {
2764 vk_free2(&device->alloc, pAllocator, sem);
2765 return VK_ERROR_OUT_OF_HOST_MEMORY;
2766 }
2767 sem->sem = NULL;
2768 } else {
2769 sem->sem = device->ws->create_sem(device->ws);
2770 if (!sem->sem) {
2771 vk_free2(&device->alloc, pAllocator, sem);
2772 return VK_ERROR_OUT_OF_HOST_MEMORY;
2773 }
2774 sem->syncobj = 0;
2775 }
2776
2777 *pSemaphore = radv_semaphore_to_handle(sem);
2778 return VK_SUCCESS;
2779 }
2780
2781 void radv_DestroySemaphore(
2782 VkDevice _device,
2783 VkSemaphore _semaphore,
2784 const VkAllocationCallbacks* pAllocator)
2785 {
2786 RADV_FROM_HANDLE(radv_device, device, _device);
2787 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2788 if (!_semaphore)
2789 return;
2790
2791 if (sem->syncobj)
2792 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2793 else
2794 device->ws->destroy_sem(sem->sem);
2795 vk_free2(&device->alloc, pAllocator, sem);
2796 }
2797
2798 VkResult radv_CreateEvent(
2799 VkDevice _device,
2800 const VkEventCreateInfo* pCreateInfo,
2801 const VkAllocationCallbacks* pAllocator,
2802 VkEvent* pEvent)
2803 {
2804 RADV_FROM_HANDLE(radv_device, device, _device);
2805 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2806 sizeof(*event), 8,
2807 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2808
2809 if (!event)
2810 return VK_ERROR_OUT_OF_HOST_MEMORY;
2811
2812 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2813 RADEON_DOMAIN_GTT,
2814 RADEON_FLAG_CPU_ACCESS);
2815 if (!event->bo) {
2816 vk_free2(&device->alloc, pAllocator, event);
2817 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2818 }
2819
2820 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2821
2822 *pEvent = radv_event_to_handle(event);
2823
2824 return VK_SUCCESS;
2825 }
2826
2827 void radv_DestroyEvent(
2828 VkDevice _device,
2829 VkEvent _event,
2830 const VkAllocationCallbacks* pAllocator)
2831 {
2832 RADV_FROM_HANDLE(radv_device, device, _device);
2833 RADV_FROM_HANDLE(radv_event, event, _event);
2834
2835 if (!event)
2836 return;
2837 device->ws->buffer_destroy(event->bo);
2838 vk_free2(&device->alloc, pAllocator, event);
2839 }
2840
2841 VkResult radv_GetEventStatus(
2842 VkDevice _device,
2843 VkEvent _event)
2844 {
2845 RADV_FROM_HANDLE(radv_event, event, _event);
2846
2847 if (*event->map == 1)
2848 return VK_EVENT_SET;
2849 return VK_EVENT_RESET;
2850 }
2851
2852 VkResult radv_SetEvent(
2853 VkDevice _device,
2854 VkEvent _event)
2855 {
2856 RADV_FROM_HANDLE(radv_event, event, _event);
2857 *event->map = 1;
2858
2859 return VK_SUCCESS;
2860 }
2861
2862 VkResult radv_ResetEvent(
2863 VkDevice _device,
2864 VkEvent _event)
2865 {
2866 RADV_FROM_HANDLE(radv_event, event, _event);
2867 *event->map = 0;
2868
2869 return VK_SUCCESS;
2870 }
2871
2872 VkResult radv_CreateBuffer(
2873 VkDevice _device,
2874 const VkBufferCreateInfo* pCreateInfo,
2875 const VkAllocationCallbacks* pAllocator,
2876 VkBuffer* pBuffer)
2877 {
2878 RADV_FROM_HANDLE(radv_device, device, _device);
2879 struct radv_buffer *buffer;
2880
2881 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2882
2883 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2884 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2885 if (buffer == NULL)
2886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2887
2888 buffer->size = pCreateInfo->size;
2889 buffer->usage = pCreateInfo->usage;
2890 buffer->bo = NULL;
2891 buffer->offset = 0;
2892 buffer->flags = pCreateInfo->flags;
2893
2894 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2895 buffer->bo = device->ws->buffer_create(device->ws,
2896 align64(buffer->size, 4096),
2897 4096, 0, RADEON_FLAG_VIRTUAL);
2898 if (!buffer->bo) {
2899 vk_free2(&device->alloc, pAllocator, buffer);
2900 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2901 }
2902 }
2903
2904 *pBuffer = radv_buffer_to_handle(buffer);
2905
2906 return VK_SUCCESS;
2907 }
2908
2909 void radv_DestroyBuffer(
2910 VkDevice _device,
2911 VkBuffer _buffer,
2912 const VkAllocationCallbacks* pAllocator)
2913 {
2914 RADV_FROM_HANDLE(radv_device, device, _device);
2915 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2916
2917 if (!buffer)
2918 return;
2919
2920 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2921 device->ws->buffer_destroy(buffer->bo);
2922
2923 vk_free2(&device->alloc, pAllocator, buffer);
2924 }
2925
2926 static inline unsigned
2927 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2928 {
2929 if (stencil)
2930 return image->surface.u.legacy.stencil_tiling_index[level];
2931 else
2932 return image->surface.u.legacy.tiling_index[level];
2933 }
2934
2935 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2936 {
2937 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2938 }
2939
2940 static void
2941 radv_initialise_color_surface(struct radv_device *device,
2942 struct radv_color_buffer_info *cb,
2943 struct radv_image_view *iview)
2944 {
2945 const struct vk_format_description *desc;
2946 unsigned ntype, format, swap, endian;
2947 unsigned blend_clamp = 0, blend_bypass = 0;
2948 uint64_t va;
2949 const struct radeon_surf *surf = &iview->image->surface;
2950
2951 desc = vk_format_description(iview->vk_format);
2952
2953 memset(cb, 0, sizeof(*cb));
2954
2955 /* Intensity is implemented as Red, so treat it that way. */
2956 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2957
2958 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2959
2960 if (device->physical_device->rad_info.chip_class >= GFX9) {
2961 struct gfx9_surf_meta_flags meta;
2962 if (iview->image->dcc_offset)
2963 meta = iview->image->surface.u.gfx9.dcc;
2964 else
2965 meta = iview->image->surface.u.gfx9.cmask;
2966
2967 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2968 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2969 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2970 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2971
2972 va += iview->image->surface.u.gfx9.surf_offset >> 8;
2973 } else {
2974 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2975 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2976
2977 va += level_info->offset;
2978
2979 pitch_tile_max = level_info->nblk_x / 8 - 1;
2980 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2981 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2982
2983 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2984 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2985 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2986
2987 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2988 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2989
2990 if (iview->image->fmask.size) {
2991 if (device->physical_device->rad_info.chip_class >= CIK)
2992 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2993 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2994 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2995 } else {
2996 /* This must be set for fast clear to work without FMASK. */
2997 if (device->physical_device->rad_info.chip_class >= CIK)
2998 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2999 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3000 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3001 }
3002 }
3003
3004 cb->cb_color_base = va >> 8;
3005 if (device->physical_device->rad_info.chip_class < GFX9)
3006 cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
3007 /* CMASK variables */
3008 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3009 va += iview->image->cmask.offset;
3010 cb->cb_color_cmask = va >> 8;
3011
3012 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3013 va += iview->image->dcc_offset;
3014 cb->cb_dcc_base = va >> 8;
3015 if (device->physical_device->rad_info.chip_class < GFX9)
3016 cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
3017
3018 uint32_t max_slice = radv_surface_layer_count(iview);
3019 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3020 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3021
3022 if (iview->image->info.samples > 1) {
3023 unsigned log_samples = util_logbase2(iview->image->info.samples);
3024
3025 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3026 S_028C74_NUM_FRAGMENTS(log_samples);
3027 }
3028
3029 if (iview->image->fmask.size) {
3030 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3031 cb->cb_color_fmask = va >> 8;
3032 if (device->physical_device->rad_info.chip_class < GFX9)
3033 cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
3034 } else {
3035 cb->cb_color_fmask = cb->cb_color_base;
3036 }
3037
3038 ntype = radv_translate_color_numformat(iview->vk_format,
3039 desc,
3040 vk_format_get_first_non_void_channel(iview->vk_format));
3041 format = radv_translate_colorformat(iview->vk_format);
3042 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3043 radv_finishme("Illegal color\n");
3044 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3045 endian = radv_colorformat_endian_swap(format);
3046
3047 /* blend clamp should be set for all NORM/SRGB types */
3048 if (ntype == V_028C70_NUMBER_UNORM ||
3049 ntype == V_028C70_NUMBER_SNORM ||
3050 ntype == V_028C70_NUMBER_SRGB)
3051 blend_clamp = 1;
3052
3053 /* set blend bypass according to docs if SINT/UINT or
3054 8/24 COLOR variants */
3055 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3056 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3057 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3058 blend_clamp = 0;
3059 blend_bypass = 1;
3060 }
3061 #if 0
3062 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3063 (format == V_028C70_COLOR_8 ||
3064 format == V_028C70_COLOR_8_8 ||
3065 format == V_028C70_COLOR_8_8_8_8))
3066 ->color_is_int8 = true;
3067 #endif
3068 cb->cb_color_info = S_028C70_FORMAT(format) |
3069 S_028C70_COMP_SWAP(swap) |
3070 S_028C70_BLEND_CLAMP(blend_clamp) |
3071 S_028C70_BLEND_BYPASS(blend_bypass) |
3072 S_028C70_SIMPLE_FLOAT(1) |
3073 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3074 ntype != V_028C70_NUMBER_SNORM &&
3075 ntype != V_028C70_NUMBER_SRGB &&
3076 format != V_028C70_COLOR_8_24 &&
3077 format != V_028C70_COLOR_24_8) |
3078 S_028C70_NUMBER_TYPE(ntype) |
3079 S_028C70_ENDIAN(endian);
3080 if (iview->image->info.samples > 1)
3081 if (iview->image->fmask.size)
3082 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3083
3084 if (iview->image->cmask.size &&
3085 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3086 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3087
3088 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3089 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3090
3091 if (device->physical_device->rad_info.chip_class >= VI) {
3092 unsigned max_uncompressed_block_size = 2;
3093 if (iview->image->info.samples > 1) {
3094 if (iview->image->surface.bpe == 1)
3095 max_uncompressed_block_size = 0;
3096 else if (iview->image->surface.bpe == 2)
3097 max_uncompressed_block_size = 1;
3098 }
3099
3100 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3101 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3102 }
3103
3104 /* This must be set for fast clear to work without FMASK. */
3105 if (!iview->image->fmask.size &&
3106 device->physical_device->rad_info.chip_class == SI) {
3107 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3108 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3109 }
3110
3111 if (device->physical_device->rad_info.chip_class >= GFX9) {
3112 uint32_t max_slice = radv_surface_layer_count(iview);
3113 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3114
3115 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3116 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3117 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3118 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
3119 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
3120 S_028C68_MAX_MIP(iview->image->info.levels);
3121
3122 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3123
3124 }
3125 }
3126
3127 static void
3128 radv_initialise_ds_surface(struct radv_device *device,
3129 struct radv_ds_buffer_info *ds,
3130 struct radv_image_view *iview)
3131 {
3132 unsigned level = iview->base_mip;
3133 unsigned format, stencil_format;
3134 uint64_t va, s_offs, z_offs;
3135 bool stencil_only = false;
3136 memset(ds, 0, sizeof(*ds));
3137 switch (iview->image->vk_format) {
3138 case VK_FORMAT_D24_UNORM_S8_UINT:
3139 case VK_FORMAT_X8_D24_UNORM_PACK32:
3140 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3141 ds->offset_scale = 2.0f;
3142 break;
3143 case VK_FORMAT_D16_UNORM:
3144 case VK_FORMAT_D16_UNORM_S8_UINT:
3145 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3146 ds->offset_scale = 4.0f;
3147 break;
3148 case VK_FORMAT_D32_SFLOAT:
3149 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3150 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3151 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3152 ds->offset_scale = 1.0f;
3153 break;
3154 case VK_FORMAT_S8_UINT:
3155 stencil_only = true;
3156 break;
3157 default:
3158 break;
3159 }
3160
3161 format = radv_translate_dbformat(iview->image->vk_format);
3162 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
3163 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3164
3165 uint32_t max_slice = radv_surface_layer_count(iview);
3166 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3167 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3168
3169 ds->db_htile_data_base = 0;
3170 ds->db_htile_surface = 0;
3171
3172 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3173 s_offs = z_offs = va;
3174
3175 if (device->physical_device->rad_info.chip_class >= GFX9) {
3176 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3177 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3178
3179 ds->db_z_info = S_028038_FORMAT(format) |
3180 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3181 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3182 S_028038_MAXMIP(iview->image->info.levels - 1);
3183 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3184 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3185
3186 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3187 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3188 ds->db_depth_view |= S_028008_MIPID(level);
3189
3190 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3191 S_02801C_Y_MAX(iview->image->info.height - 1);
3192
3193 /* Only use HTILE for the first level. */
3194 if (iview->image->surface.htile_size && !level) {
3195 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3196
3197 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3198 /* Use all of the htile_buffer for depth if there's no stencil. */
3199 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3200 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3201 iview->image->htile_offset;
3202 ds->db_htile_data_base = va >> 8;
3203 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3204 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3205 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3206 }
3207 } else {
3208 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3209
3210 if (stencil_only)
3211 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3212
3213 z_offs += iview->image->surface.u.legacy.level[level].offset;
3214 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3215
3216 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3217 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3218 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3219
3220 if (iview->image->info.samples > 1)
3221 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3222
3223 if (device->physical_device->rad_info.chip_class >= CIK) {
3224 struct radeon_info *info = &device->physical_device->rad_info;
3225 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3226 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3227 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3228 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3229 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3230 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3231
3232 if (stencil_only)
3233 tile_mode = stencil_tile_mode;
3234
3235 ds->db_depth_info |=
3236 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3237 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3238 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3239 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3240 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3241 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3242 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3243 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3244 } else {
3245 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3246 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3247 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3248 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3249 }
3250
3251 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3252 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3253 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3254
3255 if (iview->image->surface.htile_size && !level) {
3256 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3257
3258 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3259 /* Use all of the htile_buffer for depth if there's no stencil. */
3260 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3261
3262 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3263 iview->image->htile_offset;
3264 ds->db_htile_data_base = va >> 8;
3265 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3266 }
3267 }
3268
3269 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3270 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3271 }
3272
3273 VkResult radv_CreateFramebuffer(
3274 VkDevice _device,
3275 const VkFramebufferCreateInfo* pCreateInfo,
3276 const VkAllocationCallbacks* pAllocator,
3277 VkFramebuffer* pFramebuffer)
3278 {
3279 RADV_FROM_HANDLE(radv_device, device, _device);
3280 struct radv_framebuffer *framebuffer;
3281
3282 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3283
3284 size_t size = sizeof(*framebuffer) +
3285 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3286 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3287 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3288 if (framebuffer == NULL)
3289 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3290
3291 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3292 framebuffer->width = pCreateInfo->width;
3293 framebuffer->height = pCreateInfo->height;
3294 framebuffer->layers = pCreateInfo->layers;
3295 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3296 VkImageView _iview = pCreateInfo->pAttachments[i];
3297 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3298 framebuffer->attachments[i].attachment = iview;
3299 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3300 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3301 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3302 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3303 }
3304 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3305 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3306 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3307 }
3308
3309 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3310 return VK_SUCCESS;
3311 }
3312
3313 void radv_DestroyFramebuffer(
3314 VkDevice _device,
3315 VkFramebuffer _fb,
3316 const VkAllocationCallbacks* pAllocator)
3317 {
3318 RADV_FROM_HANDLE(radv_device, device, _device);
3319 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3320
3321 if (!fb)
3322 return;
3323 vk_free2(&device->alloc, pAllocator, fb);
3324 }
3325
3326 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3327 {
3328 switch (address_mode) {
3329 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3330 return V_008F30_SQ_TEX_WRAP;
3331 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3332 return V_008F30_SQ_TEX_MIRROR;
3333 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3334 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3335 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3336 return V_008F30_SQ_TEX_CLAMP_BORDER;
3337 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3338 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3339 default:
3340 unreachable("illegal tex wrap mode");
3341 break;
3342 }
3343 }
3344
3345 static unsigned
3346 radv_tex_compare(VkCompareOp op)
3347 {
3348 switch (op) {
3349 case VK_COMPARE_OP_NEVER:
3350 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3351 case VK_COMPARE_OP_LESS:
3352 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3353 case VK_COMPARE_OP_EQUAL:
3354 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3355 case VK_COMPARE_OP_LESS_OR_EQUAL:
3356 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3357 case VK_COMPARE_OP_GREATER:
3358 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3359 case VK_COMPARE_OP_NOT_EQUAL:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3361 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3362 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3363 case VK_COMPARE_OP_ALWAYS:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3365 default:
3366 unreachable("illegal compare mode");
3367 break;
3368 }
3369 }
3370
3371 static unsigned
3372 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3373 {
3374 switch (filter) {
3375 case VK_FILTER_NEAREST:
3376 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3377 V_008F38_SQ_TEX_XY_FILTER_POINT);
3378 case VK_FILTER_LINEAR:
3379 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3380 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3381 case VK_FILTER_CUBIC_IMG:
3382 default:
3383 fprintf(stderr, "illegal texture filter");
3384 return 0;
3385 }
3386 }
3387
3388 static unsigned
3389 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3390 {
3391 switch (mode) {
3392 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3393 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3394 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3395 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3396 default:
3397 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3398 }
3399 }
3400
3401 static unsigned
3402 radv_tex_bordercolor(VkBorderColor bcolor)
3403 {
3404 switch (bcolor) {
3405 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3406 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3407 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3408 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3409 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3410 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3411 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3412 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3413 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3414 default:
3415 break;
3416 }
3417 return 0;
3418 }
3419
3420 static unsigned
3421 radv_tex_aniso_filter(unsigned filter)
3422 {
3423 if (filter < 2)
3424 return 0;
3425 if (filter < 4)
3426 return 1;
3427 if (filter < 8)
3428 return 2;
3429 if (filter < 16)
3430 return 3;
3431 return 4;
3432 }
3433
3434 static void
3435 radv_init_sampler(struct radv_device *device,
3436 struct radv_sampler *sampler,
3437 const VkSamplerCreateInfo *pCreateInfo)
3438 {
3439 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3440 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3441 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3442 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3443
3444 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3445 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3446 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3447 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3448 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3449 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3450 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3451 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3452 S_008F30_DISABLE_CUBE_WRAP(0) |
3453 S_008F30_COMPAT_MODE(is_vi));
3454 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3455 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3456 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3457 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3458 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3459 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3460 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3461 S_008F38_MIP_POINT_PRECLAMP(0) |
3462 S_008F38_DISABLE_LSB_CEIL(1) |
3463 S_008F38_FILTER_PREC_FIX(1) |
3464 S_008F38_ANISO_OVERRIDE(is_vi));
3465 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3466 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3467 }
3468
3469 VkResult radv_CreateSampler(
3470 VkDevice _device,
3471 const VkSamplerCreateInfo* pCreateInfo,
3472 const VkAllocationCallbacks* pAllocator,
3473 VkSampler* pSampler)
3474 {
3475 RADV_FROM_HANDLE(radv_device, device, _device);
3476 struct radv_sampler *sampler;
3477
3478 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3479
3480 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3481 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3482 if (!sampler)
3483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3484
3485 radv_init_sampler(device, sampler, pCreateInfo);
3486 *pSampler = radv_sampler_to_handle(sampler);
3487
3488 return VK_SUCCESS;
3489 }
3490
3491 void radv_DestroySampler(
3492 VkDevice _device,
3493 VkSampler _sampler,
3494 const VkAllocationCallbacks* pAllocator)
3495 {
3496 RADV_FROM_HANDLE(radv_device, device, _device);
3497 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3498
3499 if (!sampler)
3500 return;
3501 vk_free2(&device->alloc, pAllocator, sampler);
3502 }
3503
3504 /* vk_icd.h does not declare this function, so we declare it here to
3505 * suppress Wmissing-prototypes.
3506 */
3507 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3508 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3509
3510 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3511 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3512 {
3513 /* For the full details on loader interface versioning, see
3514 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3515 * What follows is a condensed summary, to help you navigate the large and
3516 * confusing official doc.
3517 *
3518 * - Loader interface v0 is incompatible with later versions. We don't
3519 * support it.
3520 *
3521 * - In loader interface v1:
3522 * - The first ICD entrypoint called by the loader is
3523 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3524 * entrypoint.
3525 * - The ICD must statically expose no other Vulkan symbol unless it is
3526 * linked with -Bsymbolic.
3527 * - Each dispatchable Vulkan handle created by the ICD must be
3528 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3529 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3530 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3531 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3532 * such loader-managed surfaces.
3533 *
3534 * - Loader interface v2 differs from v1 in:
3535 * - The first ICD entrypoint called by the loader is
3536 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3537 * statically expose this entrypoint.
3538 *
3539 * - Loader interface v3 differs from v2 in:
3540 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3541 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3542 * because the loader no longer does so.
3543 */
3544 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3545 return VK_SUCCESS;
3546 }
3547
3548 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3549 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3550 int *pFD)
3551 {
3552 RADV_FROM_HANDLE(radv_device, device, _device);
3553 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3554
3555 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3556
3557 /* We support only one handle type. */
3558 assert(pGetFdInfo->handleType ==
3559 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3560
3561 bool ret = radv_get_memory_fd(device, memory, pFD);
3562 if (ret == false)
3563 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3564 return VK_SUCCESS;
3565 }
3566
3567 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3568 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3569 int fd,
3570 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3571 {
3572 /* The valid usage section for this function says:
3573 *
3574 * "handleType must not be one of the handle types defined as opaque."
3575 *
3576 * Since we only handle opaque handles for now, there are no FD properties.
3577 */
3578 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3579 }
3580
3581 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3582 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3583 {
3584 RADV_FROM_HANDLE(radv_device, device, _device);
3585 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3586 uint32_t syncobj_handle = 0;
3587 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3588
3589 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3590 if (ret != 0)
3591 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3592
3593 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3594 sem->temp_syncobj = syncobj_handle;
3595 } else {
3596 sem->syncobj = syncobj_handle;
3597 }
3598 close(pImportSemaphoreFdInfo->fd);
3599 return VK_SUCCESS;
3600 }
3601
3602 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3603 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3604 int *pFd)
3605 {
3606 RADV_FROM_HANDLE(radv_device, device, _device);
3607 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3608 int ret;
3609 uint32_t syncobj_handle;
3610
3611 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3612 if (sem->temp_syncobj)
3613 syncobj_handle = sem->temp_syncobj;
3614 else
3615 syncobj_handle = sem->syncobj;
3616 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3617 if (ret)
3618 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3619 return VK_SUCCESS;
3620 }
3621
3622 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3623 VkPhysicalDevice physicalDevice,
3624 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3625 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3626 {
3627 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3628 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3629 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3630 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3631 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3632 } else {
3633 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3634 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3635 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3636 }
3637 }