2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_is_mem_type_vram(enum radv_mem_type type
)
135 return type
== RADV_MEM_TYPE_VRAM
||
136 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
140 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
142 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
143 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
148 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
149 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
155 return type
== RADV_MEM_TYPE_GTT_CACHED
||
156 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
160 radv_is_mem_type_uncached(enum radv_mem_type type
)
162 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
163 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
164 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
169 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
172 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
173 uint64_t vram_size
= radv_get_vram_size(device
);
174 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
175 device
->memory_properties
.memoryHeapCount
= 0;
177 vram_index
= device
->memory_properties
.memoryHeapCount
++;
178 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
180 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 if (visible_vram_size
) {
184 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
185 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
186 .size
= visible_vram_size
,
187 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
190 if (device
->rad_info
.gart_size
> 0) {
191 gart_index
= device
->memory_properties
.memoryHeapCount
++;
192 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
193 .size
= device
->rad_info
.gart_size
,
194 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
199 unsigned type_count
= 0;
200 if (vram_index
>= 0) {
201 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
202 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
203 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
204 .heapIndex
= vram_index
,
207 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
212 .heapIndex
= gart_index
,
215 if (visible_vram_index
>= 0) {
216 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
221 .heapIndex
= visible_vram_index
,
224 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
230 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
231 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
234 .heapIndex
= gart_index
,
237 if (gart_index
>= 0) {
238 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
239 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
240 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
243 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
244 .heapIndex
= gart_index
,
247 device
->memory_properties
.memoryTypeCount
= type_count
;
249 if (device
->rad_info
.has_l2_uncached
) {
250 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
251 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
253 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
255 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
256 enum radv_mem_type mem_type_id
;
258 switch (device
->mem_type_indices
[i
]) {
259 case RADV_MEM_TYPE_VRAM
:
260 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
263 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
266 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
268 case RADV_MEM_TYPE_GTT_CACHED
:
269 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
272 unreachable("invalid memory type");
275 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
279 device
->mem_type_indices
[type_count
] = mem_type_id
;
280 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
281 .propertyFlags
= property_flags
,
282 .heapIndex
= mem_type
.heapIndex
,
286 device
->memory_properties
.memoryTypeCount
= type_count
;
291 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
293 const char *family
= getenv("RADV_FORCE_FAMILY");
299 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
300 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
301 /* Override family and chip_class. */
302 device
->rad_info
.family
= i
;
303 device
->rad_info
.name
= "OVERRIDDEN";
305 if (i
>= CHIP_NAVI10
)
306 device
->rad_info
.chip_class
= GFX10
;
307 else if (i
>= CHIP_VEGA10
)
308 device
->rad_info
.chip_class
= GFX9
;
309 else if (i
>= CHIP_TONGA
)
310 device
->rad_info
.chip_class
= GFX8
;
311 else if (i
>= CHIP_BONAIRE
)
312 device
->rad_info
.chip_class
= GFX7
;
314 device
->rad_info
.chip_class
= GFX6
;
316 /* Don't submit any IBs. */
317 device
->instance
->debug_flags
|= RADV_DEBUG_NOOP
;
322 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
327 radv_physical_device_init(struct radv_physical_device
*device
,
328 struct radv_instance
*instance
,
329 drmDevicePtr drm_device
)
331 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
333 drmVersionPtr version
;
337 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
339 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
340 radv_logi("Could not open device '%s'", path
);
342 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
345 version
= drmGetVersion(fd
);
349 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
350 radv_logi("Could not get the kernel driver version for device '%s'", path
);
352 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
353 "failed to get version %s: %m", path
);
356 if (strcmp(version
->name
, "amdgpu")) {
357 drmFreeVersion(version
);
360 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
361 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
363 return VK_ERROR_INCOMPATIBLE_DRIVER
;
365 drmFreeVersion(version
);
367 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
368 radv_logi("Found compatible device '%s'.", path
);
370 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
371 device
->instance
= instance
;
373 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
374 instance
->perftest_flags
);
376 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
380 if (instance
->enabled_extensions
.KHR_display
) {
381 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
382 if (master_fd
>= 0) {
383 uint32_t accel_working
= 0;
384 struct drm_amdgpu_info request
= {
385 .return_pointer
= (uintptr_t)&accel_working
,
386 .return_size
= sizeof(accel_working
),
387 .query
= AMDGPU_INFO_ACCEL_WORKING
390 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
397 device
->master_fd
= master_fd
;
398 device
->local_fd
= fd
;
399 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
401 radv_handle_env_var_force_family(device
);
403 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
405 snprintf(device
->name
, sizeof(device
->name
),
406 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
407 device
->rad_info
.name
);
409 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
410 device
->ws
->destroy(device
->ws
);
411 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
412 "cannot generate UUID");
416 /* These flags affect shader compilation. */
417 uint64_t shader_env_flags
= (device
->use_aco
? 0x2 : 0);
419 /* The gpu id is already embedded in the uuid so we just pass "radv"
420 * when creating the cache.
422 char buf
[VK_UUID_SIZE
* 2 + 1];
423 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
424 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
426 if (device
->rad_info
.chip_class
< GFX8
)
427 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
429 radv_get_driver_uuid(&device
->driver_uuid
);
430 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
432 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
433 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
435 device
->dcc_msaa_allowed
=
436 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
438 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
439 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
441 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
442 device
->rad_info
.family
!= CHIP_NAVI14
&&
443 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
444 if (device
->use_aco
&& device
->use_ngg
) {
445 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
446 device
->use_ngg
= false;
449 device
->use_ngg_streamout
= false;
451 /* Determine the number of threads per wave for all stages. */
452 device
->cs_wave_size
= 64;
453 device
->ps_wave_size
= 64;
454 device
->ge_wave_size
= 64;
456 if (device
->rad_info
.chip_class
>= GFX10
) {
457 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
458 device
->cs_wave_size
= 32;
460 /* For pixel shaders, wave64 is recommanded. */
461 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
462 device
->ps_wave_size
= 32;
464 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
465 device
->ge_wave_size
= 32;
468 radv_physical_device_init_mem_types(device
);
469 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
471 device
->bus_info
= *drm_device
->businfo
.pci
;
473 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
474 ac_print_gpu_info(&device
->rad_info
);
476 /* The WSI is structured as a layer on top of the driver, so this has
477 * to be the last part of initialization (at least until we get other
480 result
= radv_init_wsi(device
);
481 if (result
!= VK_SUCCESS
) {
482 device
->ws
->destroy(device
->ws
);
483 vk_error(instance
, result
);
497 radv_physical_device_finish(struct radv_physical_device
*device
)
499 radv_finish_wsi(device
);
500 device
->ws
->destroy(device
->ws
);
501 disk_cache_destroy(device
->disk_cache
);
502 close(device
->local_fd
);
503 if (device
->master_fd
!= -1)
504 close(device
->master_fd
);
508 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
509 VkSystemAllocationScope allocationScope
)
515 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
516 size_t align
, VkSystemAllocationScope allocationScope
)
518 return realloc(pOriginal
, size
);
522 default_free_func(void *pUserData
, void *pMemory
)
527 static const VkAllocationCallbacks default_alloc
= {
529 .pfnAllocation
= default_alloc_func
,
530 .pfnReallocation
= default_realloc_func
,
531 .pfnFree
= default_free_func
,
534 static const struct debug_control radv_debug_options
[] = {
535 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
536 {"nodcc", RADV_DEBUG_NO_DCC
},
537 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
538 {"nocache", RADV_DEBUG_NO_CACHE
},
539 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
540 {"nohiz", RADV_DEBUG_NO_HIZ
},
541 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
542 {"allbos", RADV_DEBUG_ALL_BOS
},
543 {"noibs", RADV_DEBUG_NO_IBS
},
544 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
545 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
546 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
547 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
548 {"preoptir", RADV_DEBUG_PREOPTIR
},
549 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
550 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
551 {"info", RADV_DEBUG_INFO
},
552 {"errors", RADV_DEBUG_ERRORS
},
553 {"startup", RADV_DEBUG_STARTUP
},
554 {"checkir", RADV_DEBUG_CHECKIR
},
555 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
556 {"nobinning", RADV_DEBUG_NOBINNING
},
557 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
558 {"nongg", RADV_DEBUG_NO_NGG
},
559 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
560 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
561 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
562 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
563 {"noop", RADV_DEBUG_NOOP
},
568 radv_get_debug_option_name(int id
)
570 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
571 return radv_debug_options
[id
].string
;
574 static const struct debug_control radv_perftest_options
[] = {
575 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
576 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
577 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
578 {"bolist", RADV_PERFTEST_BO_LIST
},
579 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
580 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
581 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
582 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
583 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
584 {"dfsm", RADV_PERFTEST_DFSM
},
585 {"aco", RADV_PERFTEST_ACO
},
590 radv_get_perftest_option_name(int id
)
592 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
593 return radv_perftest_options
[id
].string
;
597 radv_handle_per_app_options(struct radv_instance
*instance
,
598 const VkApplicationInfo
*info
)
600 const char *name
= info
? info
->pApplicationName
: NULL
;
605 if (!strcmp(name
, "DOOM_VFR")) {
606 /* Work around a Doom VFR game bug */
607 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
608 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
609 /* Workaround for a WaW hazard when LLVM moves/merges
610 * load/store memory operations.
611 * See https://reviews.llvm.org/D61313
613 if (LLVM_VERSION_MAJOR
< 9)
614 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
615 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
616 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
617 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
618 /* Force enable VK_AMD_shader_ballot because it looks
619 * safe and it gives a nice boost (+20% on Vega 56 at
620 * this time). It also prevents corruption on LLVM.
622 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
624 } else if (!strcmp(name
, "Fledge")) {
626 * Zero VRAM for "The Surge 2"
628 * This avoid a hang when when rendering any level. Likely
629 * uninitialized data in an indirect draw.
631 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
635 static int radv_get_instance_extension_index(const char *name
)
637 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
638 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
644 static const char radv_dri_options_xml
[] =
646 DRI_CONF_SECTION_PERFORMANCE
647 DRI_CONF_ADAPTIVE_SYNC("true")
648 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
649 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
652 DRI_CONF_SECTION_DEBUG
653 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
657 static void radv_init_dri_options(struct radv_instance
*instance
)
659 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
660 driParseConfigFiles(&instance
->dri_options
,
661 &instance
->available_dri_options
,
663 instance
->engineName
,
664 instance
->engineVersion
);
667 VkResult
radv_CreateInstance(
668 const VkInstanceCreateInfo
* pCreateInfo
,
669 const VkAllocationCallbacks
* pAllocator
,
670 VkInstance
* pInstance
)
672 struct radv_instance
*instance
;
675 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
677 uint32_t client_version
;
678 if (pCreateInfo
->pApplicationInfo
&&
679 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
680 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
682 client_version
= VK_API_VERSION_1_0
;
685 const char *engine_name
= NULL
;
686 uint32_t engine_version
= 0;
687 if (pCreateInfo
->pApplicationInfo
) {
688 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
689 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
692 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
693 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
695 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
697 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
700 instance
->alloc
= *pAllocator
;
702 instance
->alloc
= default_alloc
;
704 instance
->apiVersion
= client_version
;
705 instance
->physicalDeviceCount
= -1;
707 /* Get secure compile thread count. NOTE: We cap this at 32 */
708 #define MAX_SC_PROCS 32
709 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
711 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
713 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
716 /* Disable memory cache when secure compile is set */
717 if (radv_device_use_secure_compile(instance
))
718 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
720 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
721 radv_perftest_options
);
723 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
724 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
726 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
727 radv_logi("Created an instance");
729 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
730 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
731 int index
= radv_get_instance_extension_index(ext_name
);
733 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
734 vk_free2(&default_alloc
, pAllocator
, instance
);
735 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
738 instance
->enabled_extensions
.extensions
[index
] = true;
741 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
742 if (result
!= VK_SUCCESS
) {
743 vk_free2(&default_alloc
, pAllocator
, instance
);
744 return vk_error(instance
, result
);
747 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
748 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
749 instance
->engineVersion
= engine_version
;
751 glsl_type_singleton_init_or_ref();
753 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
755 radv_init_dri_options(instance
);
756 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
758 *pInstance
= radv_instance_to_handle(instance
);
763 void radv_DestroyInstance(
764 VkInstance _instance
,
765 const VkAllocationCallbacks
* pAllocator
)
767 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
772 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
773 radv_physical_device_finish(instance
->physicalDevices
+ i
);
776 vk_free(&instance
->alloc
, instance
->engineName
);
778 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
780 glsl_type_singleton_decref();
782 driDestroyOptionCache(&instance
->dri_options
);
783 driDestroyOptionInfo(&instance
->available_dri_options
);
785 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
787 vk_free(&instance
->alloc
, instance
);
791 radv_enumerate_devices(struct radv_instance
*instance
)
793 /* TODO: Check for more devices ? */
794 drmDevicePtr devices
[8];
795 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
798 instance
->physicalDeviceCount
= 0;
800 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
802 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
803 radv_logi("Found %d drm nodes", max_devices
);
806 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
808 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
809 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
810 devices
[i
]->bustype
== DRM_BUS_PCI
&&
811 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
813 result
= radv_physical_device_init(instance
->physicalDevices
+
814 instance
->physicalDeviceCount
,
817 if (result
== VK_SUCCESS
)
818 ++instance
->physicalDeviceCount
;
819 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
823 drmFreeDevices(devices
, max_devices
);
828 VkResult
radv_EnumeratePhysicalDevices(
829 VkInstance _instance
,
830 uint32_t* pPhysicalDeviceCount
,
831 VkPhysicalDevice
* pPhysicalDevices
)
833 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
836 if (instance
->physicalDeviceCount
< 0) {
837 result
= radv_enumerate_devices(instance
);
838 if (result
!= VK_SUCCESS
&&
839 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
843 if (!pPhysicalDevices
) {
844 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
846 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
847 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
848 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
851 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
855 VkResult
radv_EnumeratePhysicalDeviceGroups(
856 VkInstance _instance
,
857 uint32_t* pPhysicalDeviceGroupCount
,
858 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
860 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
863 if (instance
->physicalDeviceCount
< 0) {
864 result
= radv_enumerate_devices(instance
);
865 if (result
!= VK_SUCCESS
&&
866 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
870 if (!pPhysicalDeviceGroupProperties
) {
871 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
873 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
874 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
875 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
876 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
877 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
880 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
884 void radv_GetPhysicalDeviceFeatures(
885 VkPhysicalDevice physicalDevice
,
886 VkPhysicalDeviceFeatures
* pFeatures
)
888 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
889 memset(pFeatures
, 0, sizeof(*pFeatures
));
891 *pFeatures
= (VkPhysicalDeviceFeatures
) {
892 .robustBufferAccess
= true,
893 .fullDrawIndexUint32
= true,
894 .imageCubeArray
= true,
895 .independentBlend
= true,
896 .geometryShader
= true,
897 .tessellationShader
= true,
898 .sampleRateShading
= true,
899 .dualSrcBlend
= true,
901 .multiDrawIndirect
= true,
902 .drawIndirectFirstInstance
= true,
904 .depthBiasClamp
= true,
905 .fillModeNonSolid
= true,
910 .multiViewport
= true,
911 .samplerAnisotropy
= true,
912 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
913 .textureCompressionASTC_LDR
= false,
914 .textureCompressionBC
= true,
915 .occlusionQueryPrecise
= true,
916 .pipelineStatisticsQuery
= true,
917 .vertexPipelineStoresAndAtomics
= true,
918 .fragmentStoresAndAtomics
= true,
919 .shaderTessellationAndGeometryPointSize
= true,
920 .shaderImageGatherExtended
= true,
921 .shaderStorageImageExtendedFormats
= true,
922 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
923 .shaderUniformBufferArrayDynamicIndexing
= true,
924 .shaderSampledImageArrayDynamicIndexing
= true,
925 .shaderStorageBufferArrayDynamicIndexing
= true,
926 .shaderStorageImageArrayDynamicIndexing
= true,
927 .shaderStorageImageReadWithoutFormat
= true,
928 .shaderStorageImageWriteWithoutFormat
= true,
929 .shaderClipDistance
= true,
930 .shaderCullDistance
= true,
931 .shaderFloat64
= true,
933 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
934 .sparseBinding
= true,
935 .variableMultisampleRate
= true,
936 .inheritedQueries
= true,
940 void radv_GetPhysicalDeviceFeatures2(
941 VkPhysicalDevice physicalDevice
,
942 VkPhysicalDeviceFeatures2
*pFeatures
)
944 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
945 vk_foreach_struct(ext
, pFeatures
->pNext
) {
946 switch (ext
->sType
) {
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
948 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
949 features
->variablePointersStorageBuffer
= true;
950 features
->variablePointers
= true;
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
954 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
955 features
->multiview
= true;
956 features
->multiviewGeometryShader
= true;
957 features
->multiviewTessellationShader
= true;
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
961 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
962 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
963 features
->shaderDrawParameters
= true;
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
967 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
968 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
969 features
->protectedMemory
= false;
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
973 VkPhysicalDevice16BitStorageFeatures
*features
=
974 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
975 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
976 features
->storageBuffer16BitAccess
= enabled
;
977 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
978 features
->storagePushConstant16
= enabled
;
979 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
983 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
984 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
985 features
->samplerYcbcrConversion
= true;
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
989 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
990 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
991 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
992 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
993 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
994 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
995 features
->shaderSampledImageArrayNonUniformIndexing
= true;
996 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
997 features
->shaderStorageImageArrayNonUniformIndexing
= true;
998 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
999 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1000 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1001 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1002 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1003 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1004 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1005 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1006 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1007 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1008 features
->descriptorBindingPartiallyBound
= true;
1009 features
->descriptorBindingVariableDescriptorCount
= true;
1010 features
->runtimeDescriptorArray
= true;
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1014 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1015 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1016 features
->conditionalRendering
= true;
1017 features
->inheritedConditionalRendering
= false;
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1021 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1022 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1023 features
->vertexAttributeInstanceRateDivisor
= true;
1024 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1028 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1029 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1030 features
->transformFeedback
= true;
1031 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1035 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1036 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1037 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1041 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1042 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1043 features
->memoryPriority
= true;
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1047 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1048 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1049 features
->bufferDeviceAddress
= true;
1050 features
->bufferDeviceAddressCaptureReplay
= false;
1051 features
->bufferDeviceAddressMultiDevice
= false;
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1055 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1056 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1057 features
->bufferDeviceAddress
= true;
1058 features
->bufferDeviceAddressCaptureReplay
= false;
1059 features
->bufferDeviceAddressMultiDevice
= false;
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1063 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1064 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1065 features
->depthClipEnable
= true;
1068 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1069 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1070 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1071 features
->hostQueryReset
= true;
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1075 VkPhysicalDevice8BitStorageFeatures
*features
=
1076 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1077 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1078 features
->storageBuffer8BitAccess
= enabled
;
1079 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1080 features
->storagePushConstant8
= enabled
;
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1084 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1085 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1086 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1087 features
->shaderInt8
= !pdevice
->use_aco
;
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1091 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1092 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1093 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1094 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1098 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1099 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1100 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1104 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1105 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1107 features
->inlineUniformBlock
= true;
1108 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1111 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1112 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1113 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1114 features
->computeDerivativeGroupQuads
= false;
1115 features
->computeDerivativeGroupLinear
= true;
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1119 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1120 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1121 features
->ycbcrImageArrays
= true;
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1125 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1126 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1127 features
->uniformBufferStandardLayout
= true;
1130 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1131 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1132 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1133 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1136 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1137 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1138 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1139 features
->imagelessFramebuffer
= true;
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1143 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1144 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1145 features
->pipelineExecutableInfo
= true;
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1149 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1150 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1151 features
->shaderSubgroupClock
= true;
1152 features
->shaderDeviceClock
= false;
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1156 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1157 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1158 features
->texelBufferAlignment
= true;
1161 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1162 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1163 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1164 features
->timelineSemaphore
= true;
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1168 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1169 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1170 features
->subgroupSizeControl
= true;
1171 features
->computeFullSubgroups
= true;
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1175 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1176 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1177 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1181 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1182 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1183 features
->shaderSubgroupExtendedTypes
= true;
1186 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1187 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1188 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1189 features
->separateDepthStencilLayouts
= true;
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1193 VkPhysicalDeviceVulkan11Features
*features
=
1194 (VkPhysicalDeviceVulkan11Features
*)ext
;
1195 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1196 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1197 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1198 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1199 features
->multiview
= true;
1200 features
->multiviewGeometryShader
= true;
1201 features
->multiviewTessellationShader
= true;
1202 features
->variablePointersStorageBuffer
= true;
1203 features
->variablePointers
= true;
1204 features
->protectedMemory
= false;
1205 features
->samplerYcbcrConversion
= true;
1206 features
->shaderDrawParameters
= true;
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1210 VkPhysicalDeviceVulkan12Features
*features
=
1211 (VkPhysicalDeviceVulkan12Features
*)ext
;
1212 features
->samplerMirrorClampToEdge
= true;
1213 features
->drawIndirectCount
= true;
1214 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1215 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1216 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1217 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1218 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1219 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1220 features
->shaderInt8
= !pdevice
->use_aco
;
1221 features
->descriptorIndexing
= true;
1222 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1223 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1224 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1225 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1226 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1227 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1228 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1229 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1230 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1231 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1232 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1233 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1234 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1235 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1236 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1237 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1238 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1239 features
->descriptorBindingPartiallyBound
= true;
1240 features
->descriptorBindingVariableDescriptorCount
= true;
1241 features
->runtimeDescriptorArray
= true;
1242 features
->samplerFilterMinmax
= pdevice
->rad_info
.chip_class
>= GFX7
;
1243 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1244 features
->imagelessFramebuffer
= true;
1245 features
->uniformBufferStandardLayout
= true;
1246 features
->shaderSubgroupExtendedTypes
= true;
1247 features
->separateDepthStencilLayouts
= true;
1248 features
->hostQueryReset
= true;
1249 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1250 features
->bufferDeviceAddress
= true;
1251 features
->bufferDeviceAddressCaptureReplay
= false;
1252 features
->bufferDeviceAddressMultiDevice
= false;
1253 features
->vulkanMemoryModel
= false;
1254 features
->vulkanMemoryModelDeviceScope
= false;
1255 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1256 features
->shaderOutputViewportIndex
= true;
1257 features
->shaderOutputLayer
= true;
1258 features
->subgroupBroadcastDynamicId
= true;
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1262 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1263 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1264 features
->rectangularLines
= false;
1265 features
->bresenhamLines
= true;
1266 features
->smoothLines
= false;
1267 features
->stippledRectangularLines
= false;
1268 features
->stippledBresenhamLines
= true;
1269 features
->stippledSmoothLines
= false;
1276 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1280 radv_max_descriptor_set_size()
1282 /* make sure that the entire descriptor set is addressable with a signed
1283 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1284 * be at most 2 GiB. the combined image & samples object count as one of
1285 * both. This limit is for the pipeline layout, not for the set layout, but
1286 * there is no set limit, so we just set a pipeline limit. I don't think
1287 * any app is going to hit this soon. */
1288 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1289 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1290 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1291 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1292 32 /* sampler, largest when combined with image */ +
1293 64 /* sampled image */ +
1294 64 /* storage image */);
1297 void radv_GetPhysicalDeviceProperties(
1298 VkPhysicalDevice physicalDevice
,
1299 VkPhysicalDeviceProperties
* pProperties
)
1301 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1302 VkSampleCountFlags sample_counts
= 0xf;
1304 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1306 VkPhysicalDeviceLimits limits
= {
1307 .maxImageDimension1D
= (1 << 14),
1308 .maxImageDimension2D
= (1 << 14),
1309 .maxImageDimension3D
= (1 << 11),
1310 .maxImageDimensionCube
= (1 << 14),
1311 .maxImageArrayLayers
= (1 << 11),
1312 .maxTexelBufferElements
= 128 * 1024 * 1024,
1313 .maxUniformBufferRange
= UINT32_MAX
,
1314 .maxStorageBufferRange
= UINT32_MAX
,
1315 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1316 .maxMemoryAllocationCount
= UINT32_MAX
,
1317 .maxSamplerAllocationCount
= 64 * 1024,
1318 .bufferImageGranularity
= 64, /* A cache line */
1319 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1320 .maxBoundDescriptorSets
= MAX_SETS
,
1321 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1322 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1323 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1324 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1325 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1326 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1327 .maxPerStageResources
= max_descriptor_set_size
,
1328 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1329 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1330 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1331 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1332 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1333 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1334 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1335 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1336 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1337 .maxVertexInputBindings
= MAX_VBS
,
1338 .maxVertexInputAttributeOffset
= 2047,
1339 .maxVertexInputBindingStride
= 2048,
1340 .maxVertexOutputComponents
= 128,
1341 .maxTessellationGenerationLevel
= 64,
1342 .maxTessellationPatchSize
= 32,
1343 .maxTessellationControlPerVertexInputComponents
= 128,
1344 .maxTessellationControlPerVertexOutputComponents
= 128,
1345 .maxTessellationControlPerPatchOutputComponents
= 120,
1346 .maxTessellationControlTotalOutputComponents
= 4096,
1347 .maxTessellationEvaluationInputComponents
= 128,
1348 .maxTessellationEvaluationOutputComponents
= 128,
1349 .maxGeometryShaderInvocations
= 127,
1350 .maxGeometryInputComponents
= 64,
1351 .maxGeometryOutputComponents
= 128,
1352 .maxGeometryOutputVertices
= 256,
1353 .maxGeometryTotalOutputComponents
= 1024,
1354 .maxFragmentInputComponents
= 128,
1355 .maxFragmentOutputAttachments
= 8,
1356 .maxFragmentDualSrcAttachments
= 1,
1357 .maxFragmentCombinedOutputResources
= 8,
1358 .maxComputeSharedMemorySize
= 32768,
1359 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1360 .maxComputeWorkGroupInvocations
= 1024,
1361 .maxComputeWorkGroupSize
= {
1366 .subPixelPrecisionBits
= 8,
1367 .subTexelPrecisionBits
= 8,
1368 .mipmapPrecisionBits
= 8,
1369 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1370 .maxDrawIndirectCount
= UINT32_MAX
,
1371 .maxSamplerLodBias
= 16,
1372 .maxSamplerAnisotropy
= 16,
1373 .maxViewports
= MAX_VIEWPORTS
,
1374 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1375 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1376 .viewportSubPixelBits
= 8,
1377 .minMemoryMapAlignment
= 4096, /* A page */
1378 .minTexelBufferOffsetAlignment
= 4,
1379 .minUniformBufferOffsetAlignment
= 4,
1380 .minStorageBufferOffsetAlignment
= 4,
1381 .minTexelOffset
= -32,
1382 .maxTexelOffset
= 31,
1383 .minTexelGatherOffset
= -32,
1384 .maxTexelGatherOffset
= 31,
1385 .minInterpolationOffset
= -2,
1386 .maxInterpolationOffset
= 2,
1387 .subPixelInterpolationOffsetBits
= 8,
1388 .maxFramebufferWidth
= (1 << 14),
1389 .maxFramebufferHeight
= (1 << 14),
1390 .maxFramebufferLayers
= (1 << 10),
1391 .framebufferColorSampleCounts
= sample_counts
,
1392 .framebufferDepthSampleCounts
= sample_counts
,
1393 .framebufferStencilSampleCounts
= sample_counts
,
1394 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1395 .maxColorAttachments
= MAX_RTS
,
1396 .sampledImageColorSampleCounts
= sample_counts
,
1397 .sampledImageIntegerSampleCounts
= sample_counts
,
1398 .sampledImageDepthSampleCounts
= sample_counts
,
1399 .sampledImageStencilSampleCounts
= sample_counts
,
1400 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1401 .maxSampleMaskWords
= 1,
1402 .timestampComputeAndGraphics
= true,
1403 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1404 .maxClipDistances
= 8,
1405 .maxCullDistances
= 8,
1406 .maxCombinedClipAndCullDistances
= 8,
1407 .discreteQueuePriorities
= 2,
1408 .pointSizeRange
= { 0.0, 8192.0 },
1409 .lineWidthRange
= { 0.0, 8192.0 },
1410 .pointSizeGranularity
= (1.0 / 8.0),
1411 .lineWidthGranularity
= (1.0 / 8.0),
1412 .strictLines
= false, /* FINISHME */
1413 .standardSampleLocations
= true,
1414 .optimalBufferCopyOffsetAlignment
= 128,
1415 .optimalBufferCopyRowPitchAlignment
= 128,
1416 .nonCoherentAtomSize
= 64,
1419 *pProperties
= (VkPhysicalDeviceProperties
) {
1420 .apiVersion
= radv_physical_device_api_version(pdevice
),
1421 .driverVersion
= vk_get_driver_version(),
1422 .vendorID
= ATI_VENDOR_ID
,
1423 .deviceID
= pdevice
->rad_info
.pci_id
,
1424 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1426 .sparseProperties
= {0},
1429 strcpy(pProperties
->deviceName
, pdevice
->name
);
1430 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1434 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1435 VkPhysicalDeviceVulkan11Properties
*p
)
1437 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1439 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1440 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1441 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1442 /* The LUID is for Windows. */
1443 p
->deviceLUIDValid
= false;
1444 p
->deviceNodeMask
= 0;
1446 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1447 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1448 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1449 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1450 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1451 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1452 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1453 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1455 if (pdevice
->rad_info
.chip_class
== GFX8
||
1456 pdevice
->rad_info
.chip_class
== GFX9
) {
1457 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1458 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1460 p
->subgroupQuadOperationsInAllStages
= true;
1462 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1463 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1464 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1465 p
->protectedNoFault
= false;
1466 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1467 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1471 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1472 VkPhysicalDeviceVulkan12Properties
*p
)
1474 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1476 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1477 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1478 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1479 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1480 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1481 p
->conformanceVersion
= (VkConformanceVersion
) {
1488 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1489 * controlled by the same config register.
1491 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1492 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1494 /* Do not allow both preserving and flushing denorms because different
1495 * shaders in the same pipeline can have different settings and this
1496 * won't work for merged shaders. To make it work, this requires LLVM
1497 * support for changing the register. The same logic applies for the
1498 * rounding modes because they are configured with the same config
1499 * register. TODO: we can enable a lot of these for ACO when it
1500 * supports all stages.
1502 p
->shaderDenormFlushToZeroFloat32
= true;
1503 p
->shaderDenormPreserveFloat32
= false;
1504 p
->shaderRoundingModeRTEFloat32
= true;
1505 p
->shaderRoundingModeRTZFloat32
= false;
1506 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1508 p
->shaderDenormFlushToZeroFloat16
= false;
1509 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1510 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1511 p
->shaderRoundingModeRTZFloat16
= false;
1512 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1514 p
->shaderDenormFlushToZeroFloat64
= false;
1515 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1516 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1517 p
->shaderRoundingModeRTZFloat64
= false;
1518 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1520 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1521 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1522 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1523 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1524 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1525 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1526 p
->robustBufferAccessUpdateAfterBind
= false;
1527 p
->quadDivergentImplicitLod
= false;
1529 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1530 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1531 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1532 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1533 32 /* sampler, largest when combined with image */ +
1534 64 /* sampled image */ +
1535 64 /* storage image */);
1536 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1537 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1538 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1539 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1540 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1541 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1542 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1543 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1544 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1545 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1546 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1547 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1548 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1549 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1550 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1552 /* We support all of the depth resolve modes */
1553 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1554 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1555 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1556 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1558 /* Average doesn't make sense for stencil so we don't support that */
1559 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1560 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1561 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1563 p
->independentResolveNone
= true;
1564 p
->independentResolve
= true;
1566 /* GFX6-8 only support single channel min/max filter. */
1567 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1568 p
->filterMinmaxSingleComponentFormats
= true;
1570 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1572 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1575 void radv_GetPhysicalDeviceProperties2(
1576 VkPhysicalDevice physicalDevice
,
1577 VkPhysicalDeviceProperties2
*pProperties
)
1579 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1580 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1582 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1583 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1585 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1587 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1588 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1590 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1592 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1593 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1594 sizeof(core_##major##_##minor.core_property))
1596 #define CORE_PROPERTY(major, minor, property) \
1597 CORE_RENAMED_PROPERTY(major, minor, property, property)
1599 vk_foreach_struct(ext
, pProperties
->pNext
) {
1600 switch (ext
->sType
) {
1601 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1602 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1603 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1604 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1607 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1608 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1609 CORE_PROPERTY(1, 1, deviceUUID
);
1610 CORE_PROPERTY(1, 1, driverUUID
);
1611 CORE_PROPERTY(1, 1, deviceLUID
);
1612 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1615 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1616 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1617 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1618 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1622 VkPhysicalDevicePointClippingProperties
*properties
=
1623 (VkPhysicalDevicePointClippingProperties
*)ext
;
1624 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1627 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1628 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1629 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1630 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1633 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1634 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1635 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1636 properties
->minImportedHostPointerAlignment
= 4096;
1639 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1640 VkPhysicalDeviceSubgroupProperties
*properties
=
1641 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1642 CORE_PROPERTY(1, 1, subgroupSize
);
1643 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1644 subgroupSupportedStages
);
1645 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1646 subgroupSupportedOperations
);
1647 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1648 subgroupQuadOperationsInAllStages
);
1651 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1652 VkPhysicalDeviceMaintenance3Properties
*properties
=
1653 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1654 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1655 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1658 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1659 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1660 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1661 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1662 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1665 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1666 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1667 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1669 /* Shader engines. */
1670 properties
->shaderEngineCount
=
1671 pdevice
->rad_info
.max_se
;
1672 properties
->shaderArraysPerEngineCount
=
1673 pdevice
->rad_info
.max_sh_per_se
;
1674 properties
->computeUnitsPerShaderArray
=
1675 pdevice
->rad_info
.num_good_cu_per_sh
;
1676 properties
->simdPerComputeUnit
= 4;
1677 properties
->wavefrontsPerSimd
=
1678 pdevice
->rad_info
.family
== CHIP_TONGA
||
1679 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1680 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1681 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1682 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1683 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1684 properties
->wavefrontSize
= 64;
1687 properties
->sgprsPerSimd
=
1688 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1689 properties
->minSgprAllocation
=
1690 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1691 properties
->maxSgprAllocation
=
1692 pdevice
->rad_info
.family
== CHIP_TONGA
||
1693 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1694 properties
->sgprAllocationGranularity
=
1695 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1698 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1699 properties
->minVgprAllocation
= 4;
1700 properties
->maxVgprAllocation
= 256;
1701 properties
->vgprAllocationGranularity
= 4;
1704 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1705 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1706 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1708 properties
->shaderCoreFeatures
= 0;
1709 properties
->activeComputeUnitCount
=
1710 pdevice
->rad_info
.num_good_compute_units
;
1713 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1714 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1715 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1716 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1719 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1720 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1721 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1722 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1723 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1724 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1725 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1726 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1727 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1728 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1729 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1730 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1731 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1732 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1733 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1734 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1735 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1736 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1737 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1738 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1739 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1740 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1741 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1742 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1743 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1744 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1747 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1748 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1749 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1750 CORE_PROPERTY(1, 1, protectedNoFault
);
1753 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1754 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1755 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1756 properties
->primitiveOverestimationSize
= 0;
1757 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1758 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1759 properties
->primitiveUnderestimation
= false;
1760 properties
->conservativePointAndLineRasterization
= false;
1761 properties
->degenerateTrianglesRasterized
= false;
1762 properties
->degenerateLinesRasterized
= false;
1763 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1764 properties
->conservativeRasterizationPostDepthCoverage
= false;
1767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1768 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1769 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1770 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1771 properties
->pciBus
= pdevice
->bus_info
.bus
;
1772 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1773 properties
->pciFunction
= pdevice
->bus_info
.func
;
1776 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1777 VkPhysicalDeviceDriverProperties
*properties
=
1778 (VkPhysicalDeviceDriverProperties
*) ext
;
1779 CORE_PROPERTY(1, 2, driverID
);
1780 CORE_PROPERTY(1, 2, driverName
);
1781 CORE_PROPERTY(1, 2, driverInfo
);
1782 CORE_PROPERTY(1, 2, conformanceVersion
);
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1786 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1787 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1788 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1789 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1790 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1791 properties
->maxTransformFeedbackStreamDataSize
= 512;
1792 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1793 properties
->maxTransformFeedbackBufferDataStride
= 512;
1794 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1795 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1796 properties
->transformFeedbackRasterizationStreamSelect
= false;
1797 properties
->transformFeedbackDraw
= true;
1800 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1801 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1802 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1804 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1805 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1806 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1807 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1808 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1812 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1813 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1814 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1815 VK_SAMPLE_COUNT_4_BIT
|
1816 VK_SAMPLE_COUNT_8_BIT
;
1817 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1818 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1819 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1820 properties
->sampleLocationSubPixelBits
= 4;
1821 properties
->variableSampleLocations
= false;
1824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1825 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1826 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1827 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1828 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1829 CORE_PROPERTY(1, 2, independentResolveNone
);
1830 CORE_PROPERTY(1, 2, independentResolve
);
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1834 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1835 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1836 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1837 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1838 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1839 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1843 VkPhysicalDeviceFloatControlsProperties
*properties
=
1844 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1845 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1846 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1847 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1848 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1849 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1850 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1851 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1852 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1853 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1854 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1855 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1856 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1857 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1858 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1859 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1860 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1861 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1865 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1866 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1867 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1871 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1872 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1873 props
->minSubgroupSize
= 64;
1874 props
->maxSubgroupSize
= 64;
1875 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1876 props
->requiredSubgroupSizeStages
= 0;
1878 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1879 /* Only GFX10+ supports wave32. */
1880 props
->minSubgroupSize
= 32;
1881 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1886 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1888 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1889 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1892 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1893 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1894 props
->lineSubPixelPrecisionBits
= 4;
1903 static void radv_get_physical_device_queue_family_properties(
1904 struct radv_physical_device
* pdevice
,
1906 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1908 int num_queue_families
= 1;
1910 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1911 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1912 num_queue_families
++;
1914 if (pQueueFamilyProperties
== NULL
) {
1915 *pCount
= num_queue_families
;
1924 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1925 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1926 VK_QUEUE_COMPUTE_BIT
|
1927 VK_QUEUE_TRANSFER_BIT
|
1928 VK_QUEUE_SPARSE_BINDING_BIT
,
1930 .timestampValidBits
= 64,
1931 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1936 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1937 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1938 if (*pCount
> idx
) {
1939 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1940 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1941 VK_QUEUE_TRANSFER_BIT
|
1942 VK_QUEUE_SPARSE_BINDING_BIT
,
1943 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1944 .timestampValidBits
= 64,
1945 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1953 void radv_GetPhysicalDeviceQueueFamilyProperties(
1954 VkPhysicalDevice physicalDevice
,
1956 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1958 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1959 if (!pQueueFamilyProperties
) {
1960 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1963 VkQueueFamilyProperties
*properties
[] = {
1964 pQueueFamilyProperties
+ 0,
1965 pQueueFamilyProperties
+ 1,
1966 pQueueFamilyProperties
+ 2,
1968 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1969 assert(*pCount
<= 3);
1972 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1973 VkPhysicalDevice physicalDevice
,
1975 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1977 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1978 if (!pQueueFamilyProperties
) {
1979 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1982 VkQueueFamilyProperties
*properties
[] = {
1983 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1984 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1985 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1987 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1988 assert(*pCount
<= 3);
1991 void radv_GetPhysicalDeviceMemoryProperties(
1992 VkPhysicalDevice physicalDevice
,
1993 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1995 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1997 *pMemoryProperties
= physical_device
->memory_properties
;
2001 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2002 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2004 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2005 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2006 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2007 uint64_t vram_size
= radv_get_vram_size(device
);
2008 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2009 uint64_t heap_budget
, heap_usage
;
2011 /* For all memory heaps, the computation of budget is as follow:
2012 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2014 * The Vulkan spec 1.1.97 says that the budget should include any
2015 * currently allocated device memory.
2017 * Note that the application heap usages are not really accurate (eg.
2018 * in presence of shared buffers).
2020 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2021 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2023 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2024 heap_usage
= device
->ws
->query_value(device
->ws
,
2025 RADEON_ALLOCATED_VRAM
);
2027 heap_budget
= vram_size
-
2028 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2031 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2032 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2033 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2034 heap_usage
= device
->ws
->query_value(device
->ws
,
2035 RADEON_ALLOCATED_VRAM_VIS
);
2037 heap_budget
= visible_vram_size
-
2038 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2041 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2042 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2043 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2044 heap_usage
= device
->ws
->query_value(device
->ws
,
2045 RADEON_ALLOCATED_GTT
);
2047 heap_budget
= gtt_size
-
2048 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2051 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2052 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2056 /* The heapBudget and heapUsage values must be zero for array elements
2057 * greater than or equal to
2058 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2060 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2061 memoryBudget
->heapBudget
[i
] = 0;
2062 memoryBudget
->heapUsage
[i
] = 0;
2066 void radv_GetPhysicalDeviceMemoryProperties2(
2067 VkPhysicalDevice physicalDevice
,
2068 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2070 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2071 &pMemoryProperties
->memoryProperties
);
2073 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2074 vk_find_struct(pMemoryProperties
->pNext
,
2075 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2077 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2080 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2082 VkExternalMemoryHandleTypeFlagBits handleType
,
2083 const void *pHostPointer
,
2084 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2086 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2090 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2091 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2092 uint32_t memoryTypeBits
= 0;
2093 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2094 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2095 memoryTypeBits
= (1 << i
);
2099 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2103 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2107 static enum radeon_ctx_priority
2108 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2110 /* Default to MEDIUM when a specific global priority isn't requested */
2112 return RADEON_CTX_PRIORITY_MEDIUM
;
2114 switch(pObj
->globalPriority
) {
2115 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2116 return RADEON_CTX_PRIORITY_REALTIME
;
2117 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2118 return RADEON_CTX_PRIORITY_HIGH
;
2119 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2120 return RADEON_CTX_PRIORITY_MEDIUM
;
2121 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2122 return RADEON_CTX_PRIORITY_LOW
;
2124 unreachable("Illegal global priority value");
2125 return RADEON_CTX_PRIORITY_INVALID
;
2130 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2131 uint32_t queue_family_index
, int idx
,
2132 VkDeviceQueueCreateFlags flags
,
2133 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2135 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2136 queue
->device
= device
;
2137 queue
->queue_family_index
= queue_family_index
;
2138 queue
->queue_idx
= idx
;
2139 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2140 queue
->flags
= flags
;
2142 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2144 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2146 list_inithead(&queue
->pending_submissions
);
2147 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2153 radv_queue_finish(struct radv_queue
*queue
)
2155 pthread_mutex_destroy(&queue
->pending_mutex
);
2158 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2160 if (queue
->initial_full_flush_preamble_cs
)
2161 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2162 if (queue
->initial_preamble_cs
)
2163 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2164 if (queue
->continue_preamble_cs
)
2165 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2166 if (queue
->descriptor_bo
)
2167 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2168 if (queue
->scratch_bo
)
2169 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2170 if (queue
->esgs_ring_bo
)
2171 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2172 if (queue
->gsvs_ring_bo
)
2173 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2174 if (queue
->tess_rings_bo
)
2175 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2177 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2178 if (queue
->gds_oa_bo
)
2179 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2180 if (queue
->compute_scratch_bo
)
2181 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2185 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2187 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2188 bo_list
->list
.count
= bo_list
->capacity
= 0;
2189 bo_list
->list
.bos
= NULL
;
2193 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2195 free(bo_list
->list
.bos
);
2196 pthread_mutex_destroy(&bo_list
->mutex
);
2199 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2200 struct radeon_winsys_bo
*bo
)
2202 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2207 if (unlikely(!device
->use_global_bo_list
))
2210 pthread_mutex_lock(&bo_list
->mutex
);
2211 if (bo_list
->list
.count
== bo_list
->capacity
) {
2212 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2213 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2216 pthread_mutex_unlock(&bo_list
->mutex
);
2217 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2220 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2221 bo_list
->capacity
= capacity
;
2224 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2225 pthread_mutex_unlock(&bo_list
->mutex
);
2229 static void radv_bo_list_remove(struct radv_device
*device
,
2230 struct radeon_winsys_bo
*bo
)
2232 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2237 if (unlikely(!device
->use_global_bo_list
))
2240 pthread_mutex_lock(&bo_list
->mutex
);
2241 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2242 if (bo_list
->list
.bos
[i
] == bo
) {
2243 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2244 --bo_list
->list
.count
;
2248 pthread_mutex_unlock(&bo_list
->mutex
);
2252 radv_device_init_gs_info(struct radv_device
*device
)
2254 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2255 device
->physical_device
->rad_info
.family
);
2258 static int radv_get_device_extension_index(const char *name
)
2260 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2261 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2268 radv_get_int_debug_option(const char *name
, int default_value
)
2275 result
= default_value
;
2279 result
= strtol(str
, &endptr
, 0);
2280 if (str
== endptr
) {
2281 /* No digits founs. */
2282 result
= default_value
;
2289 static int install_seccomp_filter() {
2291 struct sock_filter filter
[] = {
2292 /* Check arch is 64bit x86 */
2293 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2294 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2296 /* Futex is required for mutex locks */
2297 #if defined __NR__newselect
2298 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2299 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2300 #elif defined __NR_select
2301 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2302 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2304 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2305 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2308 /* Allow system exit calls for the forked process */
2309 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2310 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2312 /* Allow system read calls */
2313 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2314 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2316 /* Allow system write calls */
2317 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2318 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2320 /* Allow system brk calls (we need this for malloc) */
2321 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2322 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2324 /* Futex is required for mutex locks */
2325 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2326 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2328 /* Return error if we hit a system call not on the whitelist */
2329 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2331 /* Allow whitelisted system calls */
2332 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2335 struct sock_fprog prog
= {
2336 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2340 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2343 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2349 /* Helper function with timeout support for reading from the pipe between
2350 * processes used for secure compile.
2352 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2361 /* We can't rely on the value of tv after calling select() so
2362 * we must reset it on each iteration of the loop.
2367 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2373 ssize_t bytes_read
= read(fd
, buf
, size
);
2382 /* select timeout */
2388 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2392 d
= opendir("/proc/self/fd");
2395 int dir_fd
= dirfd(d
);
2397 while ((dir
= readdir(d
)) != NULL
) {
2398 if (dir
->d_name
[0] == '.')
2401 int fd
= atoi(dir
->d_name
);
2406 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2407 if (keep_fds
[i
] == fd
)
2419 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2420 int *fd_server
, int *fd_client
,
2421 unsigned process
, bool make_fifo
)
2423 bool result
= false;
2424 char *fifo_server_path
= NULL
;
2425 char *fifo_client_path
= NULL
;
2427 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2428 goto open_fifo_exit
;
2430 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2431 goto open_fifo_exit
;
2434 int file1
= mkfifo(fifo_server_path
, 0666);
2436 goto open_fifo_exit
;
2438 int file2
= mkfifo(fifo_client_path
, 0666);
2440 goto open_fifo_exit
;
2443 *fd_server
= open(fifo_server_path
, O_RDWR
);
2445 goto open_fifo_exit
;
2447 *fd_client
= open(fifo_client_path
, O_RDWR
);
2448 if(*fd_client
< 1) {
2450 goto open_fifo_exit
;
2456 free(fifo_server_path
);
2457 free(fifo_client_path
);
2462 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2463 int fd_idle_device_output
)
2465 int fd_secure_input
;
2466 int fd_secure_output
;
2467 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2472 enum radv_secure_compile_type sc_type
;
2474 const int needed_fds
[] = {
2477 fd_idle_device_output
,
2480 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2481 install_seccomp_filter() == -1) {
2482 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2484 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2485 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2486 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2489 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2491 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2492 goto secure_compile_exit
;
2495 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2497 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2498 struct radv_pipeline
*pipeline
;
2499 bool sc_read
= true;
2501 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2502 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2504 pipeline
->device
= device
;
2506 /* Read pipeline layout */
2507 struct radv_pipeline_layout layout
;
2508 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2509 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2511 goto secure_compile_exit
;
2513 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2514 uint32_t layout_size
;
2515 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2517 goto secure_compile_exit
;
2519 layout
.set
[set
].layout
= malloc(layout_size
);
2520 layout
.set
[set
].layout
->layout_size
= layout_size
;
2521 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2522 layout
.set
[set
].layout
->layout_size
, true);
2525 pipeline
->layout
= &layout
;
2527 /* Read pipeline key */
2528 struct radv_pipeline_key key
;
2529 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2531 /* Read pipeline create flags */
2532 VkPipelineCreateFlags flags
;
2533 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2535 /* Read stage and shader information */
2536 uint32_t num_stages
;
2537 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2538 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2540 goto secure_compile_exit
;
2542 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2545 gl_shader_stage stage
;
2546 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2548 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2550 /* Read entry point name */
2552 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2554 goto secure_compile_exit
;
2556 char *ep_name
= malloc(name_size
);
2557 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2558 pStage
->pName
= ep_name
;
2560 /* Read shader module */
2562 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2564 goto secure_compile_exit
;
2566 struct radv_shader_module
*module
= malloc(module_size
);
2567 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2568 pStage
->module
= radv_shader_module_to_handle(module
);
2570 /* Read specialization info */
2572 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2574 goto secure_compile_exit
;
2576 if (has_spec_info
) {
2577 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2578 pStage
->pSpecializationInfo
= specInfo
;
2580 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2582 goto secure_compile_exit
;
2584 void *si_data
= malloc(specInfo
->dataSize
);
2585 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2586 specInfo
->pData
= si_data
;
2588 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2590 goto secure_compile_exit
;
2592 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2593 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2594 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2596 goto secure_compile_exit
;
2599 specInfo
->pMapEntries
= mapEntries
;
2602 pStages
[stage
] = pStage
;
2605 /* Compile the shaders */
2606 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2607 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2609 /* free memory allocated above */
2610 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2611 free(layout
.set
[set
].layout
);
2613 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2617 free((void *) pStages
[i
]->pName
);
2618 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2619 if (pStages
[i
]->pSpecializationInfo
) {
2620 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2621 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2622 free((void *) pStages
[i
]->pSpecializationInfo
);
2624 free((void *) pStages
[i
]);
2627 vk_free(&device
->alloc
, pipeline
);
2629 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2630 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2632 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2633 goto secure_compile_exit
;
2637 secure_compile_exit
:
2638 close(fd_secure_input
);
2639 close(fd_secure_output
);
2640 close(fd_idle_device_output
);
2644 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2646 int fd_secure_input
[2];
2647 int fd_secure_output
[2];
2649 /* create pipe descriptors (used to communicate between processes) */
2650 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2651 return RADV_SC_TYPE_INIT_FAILURE
;
2655 if ((sc_pid
= fork()) == 0) {
2656 device
->sc_state
->secure_compile_thread_counter
= process
;
2657 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2660 return RADV_SC_TYPE_INIT_FAILURE
;
2662 /* Read the init result returned from the secure process */
2663 enum radv_secure_compile_type sc_type
;
2664 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2666 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2667 close(fd_secure_input
[0]);
2668 close(fd_secure_input
[1]);
2669 close(fd_secure_output
[1]);
2670 close(fd_secure_output
[0]);
2672 waitpid(sc_pid
, &status
, 0);
2674 return RADV_SC_TYPE_INIT_FAILURE
;
2676 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2677 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2679 close(fd_secure_input
[0]);
2680 close(fd_secure_input
[1]);
2681 close(fd_secure_output
[1]);
2682 close(fd_secure_output
[0]);
2685 waitpid(sc_pid
, &status
, 0);
2689 return RADV_SC_TYPE_INIT_SUCCESS
;
2692 /* Run a bare bones fork of a device that was forked right after its creation.
2693 * This device will have low overhead when it is forked again before each
2694 * pipeline compilation. This device sits idle and its only job is to fork
2697 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2698 int fd_secure_input
, int fd_secure_output
)
2700 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2701 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2702 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2704 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2707 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2709 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2710 sc_type
= fork_secure_compile_device(device
, process
);
2712 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2713 goto secure_compile_exit
;
2715 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2716 goto secure_compile_exit
;
2720 secure_compile_exit
:
2721 close(fd_secure_input
);
2722 close(fd_secure_output
);
2726 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2728 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2730 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2731 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2733 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2734 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2737 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2740 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2742 device
->sc_state
= vk_zalloc(&device
->alloc
,
2743 sizeof(struct radv_secure_compile_state
),
2744 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2746 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2748 pid_t upid
= getpid();
2749 time_t seconds
= time(NULL
);
2752 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2753 return VK_ERROR_INITIALIZATION_FAILED
;
2755 device
->sc_state
->uid
= uid
;
2757 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2758 int fd_secure_input
[MAX_SC_PROCS
][2];
2759 int fd_secure_output
[MAX_SC_PROCS
][2];
2761 /* create pipe descriptors (used to communicate between processes) */
2762 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2763 if (pipe(fd_secure_input
[i
]) == -1 ||
2764 pipe(fd_secure_output
[i
]) == -1) {
2765 return VK_ERROR_INITIALIZATION_FAILED
;
2769 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2770 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2771 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2773 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2774 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2775 device
->sc_state
->secure_compile_thread_counter
= process
;
2776 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2778 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2779 return VK_ERROR_INITIALIZATION_FAILED
;
2781 /* Read the init result returned from the secure process */
2782 enum radv_secure_compile_type sc_type
;
2783 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2786 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2787 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2788 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2789 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2792 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2793 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2796 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2797 close(fd_secure_input
[process
][0]);
2798 close(fd_secure_input
[process
][1]);
2799 close(fd_secure_output
[process
][1]);
2800 close(fd_secure_output
[process
][0]);
2802 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2804 /* Destroy any forks that were created sucessfully */
2805 for (unsigned i
= 0; i
< process
; i
++) {
2806 destroy_secure_compile_device(device
, i
);
2809 return VK_ERROR_INITIALIZATION_FAILED
;
2817 radv_create_pthread_cond(pthread_cond_t
*cond
)
2819 pthread_condattr_t condattr
;
2820 if (pthread_condattr_init(&condattr
)) {
2821 return VK_ERROR_INITIALIZATION_FAILED
;
2824 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2825 pthread_condattr_destroy(&condattr
);
2826 return VK_ERROR_INITIALIZATION_FAILED
;
2828 if (pthread_cond_init(cond
, &condattr
)) {
2829 pthread_condattr_destroy(&condattr
);
2830 return VK_ERROR_INITIALIZATION_FAILED
;
2832 pthread_condattr_destroy(&condattr
);
2836 VkResult
radv_CreateDevice(
2837 VkPhysicalDevice physicalDevice
,
2838 const VkDeviceCreateInfo
* pCreateInfo
,
2839 const VkAllocationCallbacks
* pAllocator
,
2842 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2844 struct radv_device
*device
;
2846 bool keep_shader_info
= false;
2848 /* Check enabled features */
2849 if (pCreateInfo
->pEnabledFeatures
) {
2850 VkPhysicalDeviceFeatures supported_features
;
2851 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2852 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2853 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2854 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2855 for (uint32_t i
= 0; i
< num_features
; i
++) {
2856 if (enabled_feature
[i
] && !supported_feature
[i
])
2857 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2861 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2863 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2865 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2867 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2868 device
->instance
= physical_device
->instance
;
2869 device
->physical_device
= physical_device
;
2871 device
->ws
= physical_device
->ws
;
2873 device
->alloc
= *pAllocator
;
2875 device
->alloc
= physical_device
->instance
->alloc
;
2877 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2878 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2879 int index
= radv_get_device_extension_index(ext_name
);
2880 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2881 vk_free(&device
->alloc
, device
);
2882 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2885 device
->enabled_extensions
.extensions
[index
] = true;
2888 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2890 /* With update after bind we can't attach bo's to the command buffer
2891 * from the descriptor set anymore, so we have to use a global BO list.
2893 device
->use_global_bo_list
=
2894 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2895 device
->enabled_extensions
.EXT_descriptor_indexing
||
2896 device
->enabled_extensions
.EXT_buffer_device_address
||
2897 device
->enabled_extensions
.KHR_buffer_device_address
;
2899 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2900 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2902 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2903 list_inithead(&device
->shader_slabs
);
2905 radv_bo_list_init(&device
->bo_list
);
2907 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2908 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2909 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2910 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2911 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2913 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2915 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2916 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2917 if (!device
->queues
[qfi
]) {
2918 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2922 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2924 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2926 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2927 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2928 qfi
, q
, queue_create
->flags
,
2930 if (result
!= VK_SUCCESS
)
2935 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2936 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2938 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2939 device
->dfsm_allowed
= device
->pbb_allowed
&&
2940 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2942 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2944 /* The maximum number of scratch waves. Scratch space isn't divided
2945 * evenly between CUs. The number is only a function of the number of CUs.
2946 * We can decrease the constant to decrease the scratch buffer size.
2948 * sctx->scratch_waves must be >= the maximum possible size of
2949 * 1 threadgroup, so that the hw doesn't hang from being unable
2952 * The recommended value is 4 per CU at most. Higher numbers don't
2953 * bring much benefit, but they still occupy chip resources (think
2954 * async compute). I've seen ~2% performance difference between 4 and 32.
2956 uint32_t max_threads_per_block
= 2048;
2957 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2958 max_threads_per_block
/ 64);
2960 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2962 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2963 /* If the KMD allows it (there is a KMD hw register for it),
2964 * allow launching waves out-of-order.
2966 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2969 radv_device_init_gs_info(device
);
2971 device
->tess_offchip_block_dw_size
=
2972 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2974 if (getenv("RADV_TRACE_FILE")) {
2975 const char *filename
= getenv("RADV_TRACE_FILE");
2977 keep_shader_info
= true;
2979 if (!radv_init_trace(device
))
2982 fprintf(stderr
, "*****************************************************************************\n");
2983 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2984 fprintf(stderr
, "*****************************************************************************\n");
2986 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2987 radv_dump_enabled_options(device
, stderr
);
2990 /* Temporarily disable secure compile while we create meta shaders, etc */
2991 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2993 device
->instance
->num_sc_threads
= 0;
2995 device
->keep_shader_info
= keep_shader_info
;
2996 result
= radv_device_init_meta(device
);
2997 if (result
!= VK_SUCCESS
)
3000 radv_device_init_msaa(device
);
3002 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
3003 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3005 case RADV_QUEUE_GENERAL
:
3006 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3007 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3008 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3010 case RADV_QUEUE_COMPUTE
:
3011 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3012 radeon_emit(device
->empty_cs
[family
], 0);
3015 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3018 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3019 cik_create_gfx_config(device
);
3021 VkPipelineCacheCreateInfo ci
;
3022 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3025 ci
.pInitialData
= NULL
;
3026 ci
.initialDataSize
= 0;
3028 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3030 if (result
!= VK_SUCCESS
)
3033 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3035 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3036 if (result
!= VK_SUCCESS
)
3037 goto fail_mem_cache
;
3039 device
->force_aniso
=
3040 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3041 if (device
->force_aniso
>= 0) {
3042 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3043 1 << util_logbase2(device
->force_aniso
));
3046 /* Fork device for secure compile as required */
3047 device
->instance
->num_sc_threads
= sc_threads
;
3048 if (radv_device_use_secure_compile(device
->instance
)) {
3050 result
= fork_secure_compile_idle_device(device
);
3051 if (result
!= VK_SUCCESS
)
3055 *pDevice
= radv_device_to_handle(device
);
3059 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3061 radv_device_finish_meta(device
);
3063 radv_bo_list_finish(&device
->bo_list
);
3065 if (device
->trace_bo
)
3066 device
->ws
->buffer_destroy(device
->trace_bo
);
3068 if (device
->gfx_init
)
3069 device
->ws
->buffer_destroy(device
->gfx_init
);
3071 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3072 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3073 radv_queue_finish(&device
->queues
[i
][q
]);
3074 if (device
->queue_count
[i
])
3075 vk_free(&device
->alloc
, device
->queues
[i
]);
3078 vk_free(&device
->alloc
, device
);
3082 void radv_DestroyDevice(
3084 const VkAllocationCallbacks
* pAllocator
)
3086 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3091 if (device
->trace_bo
)
3092 device
->ws
->buffer_destroy(device
->trace_bo
);
3094 if (device
->gfx_init
)
3095 device
->ws
->buffer_destroy(device
->gfx_init
);
3097 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3098 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3099 radv_queue_finish(&device
->queues
[i
][q
]);
3100 if (device
->queue_count
[i
])
3101 vk_free(&device
->alloc
, device
->queues
[i
]);
3102 if (device
->empty_cs
[i
])
3103 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3105 radv_device_finish_meta(device
);
3107 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3108 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3110 radv_destroy_shader_slabs(device
);
3112 pthread_cond_destroy(&device
->timeline_cond
);
3113 radv_bo_list_finish(&device
->bo_list
);
3114 if (radv_device_use_secure_compile(device
->instance
)) {
3115 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3116 destroy_secure_compile_device(device
, i
);
3120 if (device
->sc_state
) {
3121 free(device
->sc_state
->uid
);
3122 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3124 vk_free(&device
->alloc
, device
->sc_state
);
3125 vk_free(&device
->alloc
, device
);
3128 VkResult
radv_EnumerateInstanceLayerProperties(
3129 uint32_t* pPropertyCount
,
3130 VkLayerProperties
* pProperties
)
3132 if (pProperties
== NULL
) {
3133 *pPropertyCount
= 0;
3137 /* None supported at this time */
3138 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3141 VkResult
radv_EnumerateDeviceLayerProperties(
3142 VkPhysicalDevice physicalDevice
,
3143 uint32_t* pPropertyCount
,
3144 VkLayerProperties
* pProperties
)
3146 if (pProperties
== NULL
) {
3147 *pPropertyCount
= 0;
3151 /* None supported at this time */
3152 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3155 void radv_GetDeviceQueue2(
3157 const VkDeviceQueueInfo2
* pQueueInfo
,
3160 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3161 struct radv_queue
*queue
;
3163 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3164 if (pQueueInfo
->flags
!= queue
->flags
) {
3165 /* From the Vulkan 1.1.70 spec:
3167 * "The queue returned by vkGetDeviceQueue2 must have the same
3168 * flags value from this structure as that used at device
3169 * creation time in a VkDeviceQueueCreateInfo instance. If no
3170 * matching flags were specified at device creation time then
3171 * pQueue will return VK_NULL_HANDLE."
3173 *pQueue
= VK_NULL_HANDLE
;
3177 *pQueue
= radv_queue_to_handle(queue
);
3180 void radv_GetDeviceQueue(
3182 uint32_t queueFamilyIndex
,
3183 uint32_t queueIndex
,
3186 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3187 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3188 .queueFamilyIndex
= queueFamilyIndex
,
3189 .queueIndex
= queueIndex
3192 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3196 fill_geom_tess_rings(struct radv_queue
*queue
,
3198 bool add_sample_positions
,
3199 uint32_t esgs_ring_size
,
3200 struct radeon_winsys_bo
*esgs_ring_bo
,
3201 uint32_t gsvs_ring_size
,
3202 struct radeon_winsys_bo
*gsvs_ring_bo
,
3203 uint32_t tess_factor_ring_size
,
3204 uint32_t tess_offchip_ring_offset
,
3205 uint32_t tess_offchip_ring_size
,
3206 struct radeon_winsys_bo
*tess_rings_bo
)
3208 uint32_t *desc
= &map
[4];
3211 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3213 /* stride 0, num records - size, add tid, swizzle, elsize4,
3216 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3217 S_008F04_SWIZZLE_ENABLE(true);
3218 desc
[2] = esgs_ring_size
;
3219 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3220 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3222 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3223 S_008F0C_INDEX_STRIDE(3) |
3224 S_008F0C_ADD_TID_ENABLE(1);
3226 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3227 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3228 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3229 S_008F0C_RESOURCE_LEVEL(1);
3231 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3232 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3233 S_008F0C_ELEMENT_SIZE(1);
3236 /* GS entry for ES->GS ring */
3237 /* stride 0, num records - size, elsize0,
3240 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3241 desc
[6] = esgs_ring_size
;
3242 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3247 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3248 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3249 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3250 S_008F0C_RESOURCE_LEVEL(1);
3252 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3253 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3260 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3262 /* VS entry for GS->VS ring */
3263 /* stride 0, num records - size, elsize0,
3266 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3267 desc
[2] = gsvs_ring_size
;
3268 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3269 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3270 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3271 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3273 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3274 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3275 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3276 S_008F0C_RESOURCE_LEVEL(1);
3278 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3279 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3282 /* stride gsvs_itemsize, num records 64
3283 elsize 4, index stride 16 */
3284 /* shader will patch stride and desc[2] */
3286 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3287 S_008F04_SWIZZLE_ENABLE(1);
3289 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3290 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3291 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3292 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3293 S_008F0C_INDEX_STRIDE(1) |
3294 S_008F0C_ADD_TID_ENABLE(true);
3296 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3297 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3298 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3299 S_008F0C_RESOURCE_LEVEL(1);
3301 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3302 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3303 S_008F0C_ELEMENT_SIZE(1);
3310 if (tess_rings_bo
) {
3311 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3312 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3315 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3316 desc
[2] = tess_factor_ring_size
;
3317 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3318 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3319 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3320 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3322 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3323 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3324 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3325 S_008F0C_RESOURCE_LEVEL(1);
3327 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3328 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3331 desc
[4] = tess_offchip_va
;
3332 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3333 desc
[6] = tess_offchip_ring_size
;
3334 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3335 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3336 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3337 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3339 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3340 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3341 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3342 S_008F0C_RESOURCE_LEVEL(1);
3344 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3345 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3351 if (add_sample_positions
) {
3352 /* add sample positions after all rings */
3353 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3355 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3357 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3359 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3364 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3366 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3367 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3368 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3369 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3370 unsigned max_offchip_buffers
;
3371 unsigned offchip_granularity
;
3372 unsigned hs_offchip_param
;
3376 * This must be one less than the maximum number due to a hw limitation.
3377 * Various hardware bugs need thGFX7
3380 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3381 * Gfx7 should limit max_offchip_buffers to 508
3382 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3384 * Follow AMDVLK here.
3386 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3387 max_offchip_buffers_per_se
= 256;
3388 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3389 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3390 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3391 --max_offchip_buffers_per_se
;
3393 max_offchip_buffers
= max_offchip_buffers_per_se
*
3394 device
->physical_device
->rad_info
.max_se
;
3396 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3397 * around by setting 4K granularity.
3399 if (device
->tess_offchip_block_dw_size
== 4096) {
3400 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3401 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3403 assert(device
->tess_offchip_block_dw_size
== 8192);
3404 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3407 switch (device
->physical_device
->rad_info
.chip_class
) {
3409 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3414 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3422 *max_offchip_buffers_p
= max_offchip_buffers
;
3423 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3424 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3425 --max_offchip_buffers
;
3427 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3428 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3431 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3433 return hs_offchip_param
;
3437 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3438 struct radeon_winsys_bo
*esgs_ring_bo
,
3439 uint32_t esgs_ring_size
,
3440 struct radeon_winsys_bo
*gsvs_ring_bo
,
3441 uint32_t gsvs_ring_size
)
3443 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3447 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3450 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3452 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3453 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3454 radeon_emit(cs
, esgs_ring_size
>> 8);
3455 radeon_emit(cs
, gsvs_ring_size
>> 8);
3457 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3458 radeon_emit(cs
, esgs_ring_size
>> 8);
3459 radeon_emit(cs
, gsvs_ring_size
>> 8);
3464 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3465 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3466 struct radeon_winsys_bo
*tess_rings_bo
)
3473 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3475 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3477 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3478 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3479 S_030938_SIZE(tf_ring_size
/ 4));
3480 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3483 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3484 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3485 S_030984_BASE_HI(tf_va
>> 40));
3486 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3487 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3488 S_030944_BASE_HI(tf_va
>> 40));
3490 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3493 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3494 S_008988_SIZE(tf_ring_size
/ 4));
3495 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3497 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3503 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3504 uint32_t size_per_wave
, uint32_t waves
,
3505 struct radeon_winsys_bo
*scratch_bo
)
3507 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3513 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3515 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3516 S_0286E8_WAVES(waves
) |
3517 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3521 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3522 uint32_t size_per_wave
, uint32_t waves
,
3523 struct radeon_winsys_bo
*compute_scratch_bo
)
3525 uint64_t scratch_va
;
3527 if (!compute_scratch_bo
)
3530 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3532 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3534 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3535 radeon_emit(cs
, scratch_va
);
3536 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3537 S_008F04_SWIZZLE_ENABLE(1));
3539 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3540 S_00B860_WAVES(waves
) |
3541 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3545 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3546 struct radeon_cmdbuf
*cs
,
3547 struct radeon_winsys_bo
*descriptor_bo
)
3554 va
= radv_buffer_get_va(descriptor_bo
);
3556 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3558 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3559 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3560 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3561 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3562 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3564 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3565 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3568 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3569 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3570 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3571 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3572 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3574 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3575 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3579 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3580 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3581 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3582 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3583 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3584 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3586 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3587 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3594 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3596 struct radv_device
*device
= queue
->device
;
3598 if (device
->gfx_init
) {
3599 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3601 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3602 radeon_emit(cs
, va
);
3603 radeon_emit(cs
, va
>> 32);
3604 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3606 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3608 struct radv_physical_device
*physical_device
= device
->physical_device
;
3609 si_emit_graphics(physical_device
, cs
);
3614 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3616 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3617 si_emit_compute(physical_device
, cs
);
3621 radv_get_preamble_cs(struct radv_queue
*queue
,
3622 uint32_t scratch_size_per_wave
,
3623 uint32_t scratch_waves
,
3624 uint32_t compute_scratch_size_per_wave
,
3625 uint32_t compute_scratch_waves
,
3626 uint32_t esgs_ring_size
,
3627 uint32_t gsvs_ring_size
,
3628 bool needs_tess_rings
,
3631 bool needs_sample_positions
,
3632 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3633 struct radeon_cmdbuf
**initial_preamble_cs
,
3634 struct radeon_cmdbuf
**continue_preamble_cs
)
3636 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3637 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3638 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3639 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3640 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3641 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3642 struct radeon_winsys_bo
*gds_bo
= NULL
;
3643 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3644 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3645 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3646 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3647 unsigned max_offchip_buffers
;
3648 unsigned hs_offchip_param
= 0;
3649 unsigned tess_offchip_ring_offset
;
3650 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3651 if (!queue
->has_tess_rings
) {
3652 if (needs_tess_rings
)
3653 add_tess_rings
= true;
3655 if (!queue
->has_gds
) {
3659 if (!queue
->has_gds_oa
) {
3663 if (!queue
->has_sample_positions
) {
3664 if (needs_sample_positions
)
3665 add_sample_positions
= true;
3667 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3668 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3669 &max_offchip_buffers
);
3670 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3671 tess_offchip_ring_size
= max_offchip_buffers
*
3672 queue
->device
->tess_offchip_block_dw_size
* 4;
3674 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3675 if (scratch_size_per_wave
)
3676 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3680 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3681 if (compute_scratch_size_per_wave
)
3682 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3684 compute_scratch_waves
= 0;
3686 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3687 scratch_waves
<= queue
->scratch_waves
&&
3688 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3689 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3690 esgs_ring_size
<= queue
->esgs_ring_size
&&
3691 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3692 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3693 queue
->initial_preamble_cs
) {
3694 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3695 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3696 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3697 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3698 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3699 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3700 *continue_preamble_cs
= NULL
;
3704 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3705 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3706 if (scratch_size
> queue_scratch_size
) {
3707 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3712 RADV_BO_PRIORITY_SCRATCH
);
3716 scratch_bo
= queue
->scratch_bo
;
3718 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3719 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3720 if (compute_scratch_size
> compute_queue_scratch_size
) {
3721 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3722 compute_scratch_size
,
3726 RADV_BO_PRIORITY_SCRATCH
);
3727 if (!compute_scratch_bo
)
3731 compute_scratch_bo
= queue
->compute_scratch_bo
;
3733 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3734 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3739 RADV_BO_PRIORITY_SCRATCH
);
3743 esgs_ring_bo
= queue
->esgs_ring_bo
;
3744 esgs_ring_size
= queue
->esgs_ring_size
;
3747 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3748 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3753 RADV_BO_PRIORITY_SCRATCH
);
3757 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3758 gsvs_ring_size
= queue
->gsvs_ring_size
;
3761 if (add_tess_rings
) {
3762 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3763 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3767 RADV_BO_PRIORITY_SCRATCH
);
3771 tess_rings_bo
= queue
->tess_rings_bo
;
3775 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3777 /* 4 streamout GDS counters.
3778 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3780 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3784 RADV_BO_PRIORITY_SCRATCH
);
3788 gds_bo
= queue
->gds_bo
;
3792 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3794 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3798 RADV_BO_PRIORITY_SCRATCH
);
3802 gds_oa_bo
= queue
->gds_oa_bo
;
3805 if (scratch_bo
!= queue
->scratch_bo
||
3806 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3807 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3808 tess_rings_bo
!= queue
->tess_rings_bo
||
3809 add_sample_positions
) {
3811 if (gsvs_ring_bo
|| esgs_ring_bo
||
3812 tess_rings_bo
|| add_sample_positions
) {
3813 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3814 if (add_sample_positions
)
3815 size
+= 128; /* 64+32+16+8 = 120 bytes */
3817 else if (scratch_bo
)
3818 size
= 8; /* 2 dword */
3820 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3824 RADEON_FLAG_CPU_ACCESS
|
3825 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3826 RADEON_FLAG_READ_ONLY
,
3827 RADV_BO_PRIORITY_DESCRIPTOR
);
3831 descriptor_bo
= queue
->descriptor_bo
;
3833 if (descriptor_bo
!= queue
->descriptor_bo
) {
3834 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3837 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3838 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3839 S_008F04_SWIZZLE_ENABLE(1);
3840 map
[0] = scratch_va
;
3844 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3845 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3846 esgs_ring_size
, esgs_ring_bo
,
3847 gsvs_ring_size
, gsvs_ring_bo
,
3848 tess_factor_ring_size
,
3849 tess_offchip_ring_offset
,
3850 tess_offchip_ring_size
,
3853 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3856 for(int i
= 0; i
< 3; ++i
) {
3857 struct radeon_cmdbuf
*cs
= NULL
;
3858 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3859 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3866 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3868 /* Emit initial configuration. */
3869 switch (queue
->queue_family_index
) {
3870 case RADV_QUEUE_GENERAL
:
3871 radv_init_graphics_state(cs
, queue
);
3873 case RADV_QUEUE_COMPUTE
:
3874 radv_init_compute_state(cs
, queue
);
3876 case RADV_QUEUE_TRANSFER
:
3880 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3881 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3882 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3884 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3885 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3888 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3889 gsvs_ring_bo
, gsvs_ring_size
);
3890 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3891 tess_factor_ring_size
, tess_rings_bo
);
3892 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3893 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3894 compute_scratch_waves
, compute_scratch_bo
);
3895 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3896 scratch_waves
, scratch_bo
);
3899 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3901 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3904 si_cs_emit_cache_flush(cs
,
3905 queue
->device
->physical_device
->rad_info
.chip_class
,
3907 queue
->queue_family_index
== RING_COMPUTE
&&
3908 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3909 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3910 RADV_CMD_FLAG_INV_ICACHE
|
3911 RADV_CMD_FLAG_INV_SCACHE
|
3912 RADV_CMD_FLAG_INV_VCACHE
|
3913 RADV_CMD_FLAG_INV_L2
|
3914 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3915 } else if (i
== 1) {
3916 si_cs_emit_cache_flush(cs
,
3917 queue
->device
->physical_device
->rad_info
.chip_class
,
3919 queue
->queue_family_index
== RING_COMPUTE
&&
3920 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3921 RADV_CMD_FLAG_INV_ICACHE
|
3922 RADV_CMD_FLAG_INV_SCACHE
|
3923 RADV_CMD_FLAG_INV_VCACHE
|
3924 RADV_CMD_FLAG_INV_L2
|
3925 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3928 if (!queue
->device
->ws
->cs_finalize(cs
))
3932 if (queue
->initial_full_flush_preamble_cs
)
3933 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3935 if (queue
->initial_preamble_cs
)
3936 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3938 if (queue
->continue_preamble_cs
)
3939 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3941 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3942 queue
->initial_preamble_cs
= dest_cs
[1];
3943 queue
->continue_preamble_cs
= dest_cs
[2];
3945 if (scratch_bo
!= queue
->scratch_bo
) {
3946 if (queue
->scratch_bo
)
3947 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3948 queue
->scratch_bo
= scratch_bo
;
3950 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3951 queue
->scratch_waves
= scratch_waves
;
3953 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3954 if (queue
->compute_scratch_bo
)
3955 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3956 queue
->compute_scratch_bo
= compute_scratch_bo
;
3958 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3959 queue
->compute_scratch_waves
= compute_scratch_waves
;
3961 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3962 if (queue
->esgs_ring_bo
)
3963 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3964 queue
->esgs_ring_bo
= esgs_ring_bo
;
3965 queue
->esgs_ring_size
= esgs_ring_size
;
3968 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3969 if (queue
->gsvs_ring_bo
)
3970 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3971 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3972 queue
->gsvs_ring_size
= gsvs_ring_size
;
3975 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3976 queue
->tess_rings_bo
= tess_rings_bo
;
3977 queue
->has_tess_rings
= true;
3980 if (gds_bo
!= queue
->gds_bo
) {
3981 queue
->gds_bo
= gds_bo
;
3982 queue
->has_gds
= true;
3985 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3986 queue
->gds_oa_bo
= gds_oa_bo
;
3987 queue
->has_gds_oa
= true;
3990 if (descriptor_bo
!= queue
->descriptor_bo
) {
3991 if (queue
->descriptor_bo
)
3992 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3994 queue
->descriptor_bo
= descriptor_bo
;
3997 if (add_sample_positions
)
3998 queue
->has_sample_positions
= true;
4000 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
4001 *initial_preamble_cs
= queue
->initial_preamble_cs
;
4002 *continue_preamble_cs
= queue
->continue_preamble_cs
;
4003 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
4004 *continue_preamble_cs
= NULL
;
4007 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4009 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4010 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4011 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4012 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4013 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4014 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4015 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4016 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4017 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4018 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4019 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4020 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4021 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4022 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4023 queue
->device
->ws
->buffer_destroy(gds_bo
);
4024 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4025 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4027 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4030 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4031 struct radv_winsys_sem_counts
*counts
,
4033 struct radv_semaphore_part
**sems
,
4034 const uint64_t *timeline_values
,
4038 int syncobj_idx
= 0, sem_idx
= 0;
4040 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4043 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4044 switch(sems
[i
]->kind
) {
4045 case RADV_SEMAPHORE_SYNCOBJ
:
4046 counts
->syncobj_count
++;
4048 case RADV_SEMAPHORE_WINSYS
:
4049 counts
->sem_count
++;
4051 case RADV_SEMAPHORE_NONE
:
4053 case RADV_SEMAPHORE_TIMELINE
:
4054 counts
->syncobj_count
++;
4059 if (_fence
!= VK_NULL_HANDLE
) {
4060 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4061 if (fence
->temp_syncobj
|| fence
->syncobj
)
4062 counts
->syncobj_count
++;
4065 if (counts
->syncobj_count
) {
4066 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4067 if (!counts
->syncobj
)
4068 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4071 if (counts
->sem_count
) {
4072 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4074 free(counts
->syncobj
);
4075 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4079 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4080 switch(sems
[i
]->kind
) {
4081 case RADV_SEMAPHORE_NONE
:
4082 unreachable("Empty semaphore");
4084 case RADV_SEMAPHORE_SYNCOBJ
:
4085 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4087 case RADV_SEMAPHORE_WINSYS
:
4088 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4090 case RADV_SEMAPHORE_TIMELINE
: {
4091 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4092 struct radv_timeline_point
*point
= NULL
;
4094 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4096 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4099 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4102 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4104 /* Explicitly remove the semaphore so we might not find
4105 * a point later post-submit. */
4113 if (_fence
!= VK_NULL_HANDLE
) {
4114 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4115 if (fence
->temp_syncobj
)
4116 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4117 else if (fence
->syncobj
)
4118 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4121 assert(syncobj_idx
<= counts
->syncobj_count
);
4122 counts
->syncobj_count
= syncobj_idx
;
4128 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4130 free(sem_info
->wait
.syncobj
);
4131 free(sem_info
->wait
.sem
);
4132 free(sem_info
->signal
.syncobj
);
4133 free(sem_info
->signal
.sem
);
4137 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4139 struct radv_semaphore_part
*sems
)
4141 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4142 radv_destroy_semaphore_part(device
, sems
+ i
);
4147 radv_alloc_sem_info(struct radv_device
*device
,
4148 struct radv_winsys_sem_info
*sem_info
,
4150 struct radv_semaphore_part
**wait_sems
,
4151 const uint64_t *wait_values
,
4152 int num_signal_sems
,
4153 struct radv_semaphore_part
**signal_sems
,
4154 const uint64_t *signal_values
,
4158 memset(sem_info
, 0, sizeof(*sem_info
));
4160 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4163 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4165 radv_free_sem_info(sem_info
);
4167 /* caller can override these */
4168 sem_info
->cs_emit_wait
= true;
4169 sem_info
->cs_emit_signal
= true;
4174 radv_finalize_timelines(struct radv_device
*device
,
4175 uint32_t num_wait_sems
,
4176 struct radv_semaphore_part
**wait_sems
,
4177 const uint64_t *wait_values
,
4178 uint32_t num_signal_sems
,
4179 struct radv_semaphore_part
**signal_sems
,
4180 const uint64_t *signal_values
,
4181 struct list_head
*processing_list
)
4183 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4184 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4185 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4186 struct radv_timeline_point
*point
=
4187 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4188 point
->wait_count
-= 2;
4189 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4192 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4193 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4194 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4195 struct radv_timeline_point
*point
=
4196 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4197 signal_sems
[i
]->timeline
.highest_submitted
=
4198 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4199 point
->wait_count
-= 2;
4200 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4201 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4207 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4208 const VkSparseBufferMemoryBindInfo
*bind
)
4210 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4212 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4213 struct radv_device_memory
*mem
= NULL
;
4215 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4216 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4218 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4219 bind
->pBinds
[i
].resourceOffset
,
4220 bind
->pBinds
[i
].size
,
4221 mem
? mem
->bo
: NULL
,
4222 bind
->pBinds
[i
].memoryOffset
);
4227 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4228 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4230 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4232 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4233 struct radv_device_memory
*mem
= NULL
;
4235 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4236 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4238 device
->ws
->buffer_virtual_bind(image
->bo
,
4239 bind
->pBinds
[i
].resourceOffset
,
4240 bind
->pBinds
[i
].size
,
4241 mem
? mem
->bo
: NULL
,
4242 bind
->pBinds
[i
].memoryOffset
);
4247 radv_get_preambles(struct radv_queue
*queue
,
4248 const VkCommandBuffer
*cmd_buffers
,
4249 uint32_t cmd_buffer_count
,
4250 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4251 struct radeon_cmdbuf
**initial_preamble_cs
,
4252 struct radeon_cmdbuf
**continue_preamble_cs
)
4254 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4255 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4256 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4257 bool tess_rings_needed
= false;
4258 bool gds_needed
= false;
4259 bool gds_oa_needed
= false;
4260 bool sample_positions_needed
= false;
4262 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4263 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4266 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4267 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4268 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4269 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4270 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4271 cmd_buffer
->compute_scratch_waves_wanted
);
4272 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4273 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4274 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4275 gds_needed
|= cmd_buffer
->gds_needed
;
4276 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4277 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4280 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4281 compute_scratch_size_per_wave
, compute_waves_wanted
,
4282 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4283 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4284 initial_full_flush_preamble_cs
,
4285 initial_preamble_cs
, continue_preamble_cs
);
4288 struct radv_deferred_queue_submission
{
4289 struct radv_queue
*queue
;
4290 VkCommandBuffer
*cmd_buffers
;
4291 uint32_t cmd_buffer_count
;
4293 /* Sparse bindings that happen on a queue. */
4294 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4295 uint32_t buffer_bind_count
;
4296 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4297 uint32_t image_opaque_bind_count
;
4300 VkShaderStageFlags wait_dst_stage_mask
;
4301 struct radv_semaphore_part
**wait_semaphores
;
4302 uint32_t wait_semaphore_count
;
4303 struct radv_semaphore_part
**signal_semaphores
;
4304 uint32_t signal_semaphore_count
;
4307 uint64_t *wait_values
;
4308 uint64_t *signal_values
;
4310 struct radv_semaphore_part
*temporary_semaphore_parts
;
4311 uint32_t temporary_semaphore_part_count
;
4313 struct list_head queue_pending_list
;
4314 uint32_t submission_wait_count
;
4315 struct radv_timeline_waiter
*wait_nodes
;
4317 struct list_head processing_list
;
4320 struct radv_queue_submission
{
4321 const VkCommandBuffer
*cmd_buffers
;
4322 uint32_t cmd_buffer_count
;
4324 /* Sparse bindings that happen on a queue. */
4325 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4326 uint32_t buffer_bind_count
;
4327 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4328 uint32_t image_opaque_bind_count
;
4331 VkPipelineStageFlags wait_dst_stage_mask
;
4332 const VkSemaphore
*wait_semaphores
;
4333 uint32_t wait_semaphore_count
;
4334 const VkSemaphore
*signal_semaphores
;
4335 uint32_t signal_semaphore_count
;
4338 const uint64_t *wait_values
;
4339 uint32_t wait_value_count
;
4340 const uint64_t *signal_values
;
4341 uint32_t signal_value_count
;
4345 radv_create_deferred_submission(struct radv_queue
*queue
,
4346 const struct radv_queue_submission
*submission
,
4347 struct radv_deferred_queue_submission
**out
)
4349 struct radv_deferred_queue_submission
*deferred
= NULL
;
4350 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4352 uint32_t temporary_count
= 0;
4353 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4354 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4355 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4359 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4360 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4361 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4362 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4363 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4364 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4365 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4366 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4367 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4369 deferred
= calloc(1, size
);
4371 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4373 deferred
->queue
= queue
;
4375 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4376 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4377 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4378 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4380 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4381 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4382 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4383 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4385 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4386 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4387 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4388 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4390 deferred
->flush_caches
= submission
->flush_caches
;
4391 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4393 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4394 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4396 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4397 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4399 deferred
->fence
= submission
->fence
;
4401 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4402 deferred
->temporary_semaphore_part_count
= temporary_count
;
4404 uint32_t temporary_idx
= 0;
4405 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4406 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4407 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4408 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4409 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4410 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4413 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4416 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4417 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4418 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4419 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4421 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4425 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4426 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4427 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4428 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4430 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4431 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4432 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4433 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4440 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4441 struct list_head
*processing_list
)
4443 uint32_t wait_cnt
= 0;
4444 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4445 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4446 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4447 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4448 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4450 waiter
->value
= submission
->wait_values
[i
];
4451 waiter
->submission
= submission
;
4452 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4455 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4459 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4461 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4462 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4464 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4466 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4467 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4469 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4470 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4471 list_addtail(&submission
->processing_list
, processing_list
);
4476 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4477 struct list_head
*processing_list
)
4479 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4480 list_del(&submission
->queue_pending_list
);
4482 /* trigger the next submission in the queue. */
4483 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4484 struct radv_deferred_queue_submission
*next_submission
=
4485 list_first_entry(&submission
->queue
->pending_submissions
,
4486 struct radv_deferred_queue_submission
,
4487 queue_pending_list
);
4488 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4489 list_addtail(&next_submission
->processing_list
, processing_list
);
4492 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4494 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4498 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4499 struct list_head
*processing_list
)
4501 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4502 struct radv_queue
*queue
= submission
->queue
;
4503 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4504 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4505 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4506 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4507 bool can_patch
= true;
4509 struct radv_winsys_sem_info sem_info
;
4512 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4513 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4514 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4516 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4517 submission
->cmd_buffer_count
,
4518 &initial_preamble_cs
,
4519 &initial_flush_preamble_cs
,
4520 &continue_preamble_cs
);
4521 if (result
!= VK_SUCCESS
)
4524 result
= radv_alloc_sem_info(queue
->device
,
4526 submission
->wait_semaphore_count
,
4527 submission
->wait_semaphores
,
4528 submission
->wait_values
,
4529 submission
->signal_semaphore_count
,
4530 submission
->signal_semaphores
,
4531 submission
->signal_values
,
4533 if (result
!= VK_SUCCESS
)
4536 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4537 radv_sparse_buffer_bind_memory(queue
->device
,
4538 submission
->buffer_binds
+ i
);
4541 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4542 radv_sparse_image_opaque_bind_memory(queue
->device
,
4543 submission
->image_opaque_binds
+ i
);
4546 if (!submission
->cmd_buffer_count
) {
4547 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4548 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4553 radv_loge("failed to submit CS\n");
4559 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4560 (submission
->cmd_buffer_count
));
4562 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4563 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4564 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4566 cs_array
[j
] = cmd_buffer
->cs
;
4567 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4570 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4573 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4574 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4575 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4577 advance
= MIN2(max_cs_submission
,
4578 submission
->cmd_buffer_count
- j
);
4580 if (queue
->device
->trace_bo
)
4581 *queue
->device
->trace_id_ptr
= 0;
4583 sem_info
.cs_emit_wait
= j
== 0;
4584 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4586 if (unlikely(queue
->device
->use_global_bo_list
)) {
4587 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4588 bo_list
= &queue
->device
->bo_list
.list
;
4591 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4592 advance
, initial_preamble
, continue_preamble_cs
,
4594 can_patch
, base_fence
);
4596 if (unlikely(queue
->device
->use_global_bo_list
))
4597 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4600 radv_loge("failed to submit CS\n");
4603 if (queue
->device
->trace_bo
) {
4604 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4612 radv_free_temp_syncobjs(queue
->device
,
4613 submission
->temporary_semaphore_part_count
,
4614 submission
->temporary_semaphore_parts
);
4615 radv_finalize_timelines(queue
->device
,
4616 submission
->wait_semaphore_count
,
4617 submission
->wait_semaphores
,
4618 submission
->wait_values
,
4619 submission
->signal_semaphore_count
,
4620 submission
->signal_semaphores
,
4621 submission
->signal_values
,
4623 /* Has to happen after timeline finalization to make sure the
4624 * condition variable is only triggered when timelines and queue have
4626 radv_queue_submission_update_queue(submission
, processing_list
);
4627 radv_free_sem_info(&sem_info
);
4632 radv_free_temp_syncobjs(queue
->device
,
4633 submission
->temporary_semaphore_part_count
,
4634 submission
->temporary_semaphore_parts
);
4636 return VK_ERROR_DEVICE_LOST
;
4640 radv_process_submissions(struct list_head
*processing_list
)
4642 while(!list_is_empty(processing_list
)) {
4643 struct radv_deferred_queue_submission
*submission
=
4644 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4645 list_del(&submission
->processing_list
);
4647 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4648 if (result
!= VK_SUCCESS
)
4654 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4655 const struct radv_queue_submission
*submission
)
4657 struct radv_deferred_queue_submission
*deferred
= NULL
;
4659 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4660 if (result
!= VK_SUCCESS
)
4663 struct list_head processing_list
;
4664 list_inithead(&processing_list
);
4666 radv_queue_enqueue_submission(deferred
, &processing_list
);
4667 return radv_process_submissions(&processing_list
);
4670 /* Signals fence as soon as all the work currently put on queue is done. */
4671 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4674 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4679 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4681 return info
->commandBufferCount
||
4682 info
->waitSemaphoreCount
||
4683 info
->signalSemaphoreCount
;
4686 VkResult
radv_QueueSubmit(
4688 uint32_t submitCount
,
4689 const VkSubmitInfo
* pSubmits
,
4692 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4694 uint32_t fence_idx
= 0;
4695 bool flushed_caches
= false;
4697 if (fence
!= VK_NULL_HANDLE
) {
4698 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4699 if (radv_submit_has_effects(pSubmits
+ i
))
4702 fence_idx
= UINT32_MAX
;
4704 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4705 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4708 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4709 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4710 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4713 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4714 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4716 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4717 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4718 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4719 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4720 .flush_caches
= !flushed_caches
,
4721 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4722 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4723 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4724 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4725 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4726 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4727 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4728 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4729 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4731 if (result
!= VK_SUCCESS
)
4734 flushed_caches
= true;
4737 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4738 result
= radv_signal_fence(queue
, fence
);
4739 if (result
!= VK_SUCCESS
)
4746 VkResult
radv_QueueWaitIdle(
4749 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4751 pthread_mutex_lock(&queue
->pending_mutex
);
4752 while (!list_is_empty(&queue
->pending_submissions
)) {
4753 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4755 pthread_mutex_unlock(&queue
->pending_mutex
);
4757 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4758 radv_queue_family_to_ring(queue
->queue_family_index
),
4763 VkResult
radv_DeviceWaitIdle(
4766 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4768 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4769 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4770 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4776 VkResult
radv_EnumerateInstanceExtensionProperties(
4777 const char* pLayerName
,
4778 uint32_t* pPropertyCount
,
4779 VkExtensionProperties
* pProperties
)
4781 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4783 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4784 if (radv_supported_instance_extensions
.extensions
[i
]) {
4785 vk_outarray_append(&out
, prop
) {
4786 *prop
= radv_instance_extensions
[i
];
4791 return vk_outarray_status(&out
);
4794 VkResult
radv_EnumerateDeviceExtensionProperties(
4795 VkPhysicalDevice physicalDevice
,
4796 const char* pLayerName
,
4797 uint32_t* pPropertyCount
,
4798 VkExtensionProperties
* pProperties
)
4800 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4801 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4803 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4804 if (device
->supported_extensions
.extensions
[i
]) {
4805 vk_outarray_append(&out
, prop
) {
4806 *prop
= radv_device_extensions
[i
];
4811 return vk_outarray_status(&out
);
4814 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4815 VkInstance _instance
,
4818 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4819 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4822 return radv_lookup_entrypoint_unchecked(pName
);
4824 return radv_lookup_entrypoint_checked(pName
,
4825 instance
? instance
->apiVersion
: 0,
4826 instance
? &instance
->enabled_extensions
: NULL
,
4831 /* The loader wants us to expose a second GetInstanceProcAddr function
4832 * to work around certain LD_PRELOAD issues seen in apps.
4835 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4836 VkInstance instance
,
4840 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4841 VkInstance instance
,
4844 return radv_GetInstanceProcAddr(instance
, pName
);
4848 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4849 VkInstance _instance
,
4853 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4854 VkInstance _instance
,
4857 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4859 return radv_lookup_physical_device_entrypoint_checked(pName
,
4860 instance
? instance
->apiVersion
: 0,
4861 instance
? &instance
->enabled_extensions
: NULL
);
4864 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4868 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4869 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4872 return radv_lookup_entrypoint_unchecked(pName
);
4874 return radv_lookup_entrypoint_checked(pName
,
4875 device
->instance
->apiVersion
,
4876 &device
->instance
->enabled_extensions
,
4877 &device
->enabled_extensions
);
4881 bool radv_get_memory_fd(struct radv_device
*device
,
4882 struct radv_device_memory
*memory
,
4885 struct radeon_bo_metadata metadata
;
4887 if (memory
->image
) {
4888 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4889 radv_init_metadata(device
, memory
->image
, &metadata
);
4890 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4893 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4898 static void radv_free_memory(struct radv_device
*device
,
4899 const VkAllocationCallbacks
* pAllocator
,
4900 struct radv_device_memory
*mem
)
4905 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4906 if (mem
->android_hardware_buffer
)
4907 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4911 radv_bo_list_remove(device
, mem
->bo
);
4912 device
->ws
->buffer_destroy(mem
->bo
);
4916 vk_free2(&device
->alloc
, pAllocator
, mem
);
4919 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4920 const VkMemoryAllocateInfo
* pAllocateInfo
,
4921 const VkAllocationCallbacks
* pAllocator
,
4922 VkDeviceMemory
* pMem
)
4924 struct radv_device_memory
*mem
;
4926 enum radeon_bo_domain domain
;
4928 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
4930 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4932 const VkImportMemoryFdInfoKHR
*import_info
=
4933 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4934 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4935 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4936 const VkExportMemoryAllocateInfo
*export_info
=
4937 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4938 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4939 vk_find_struct_const(pAllocateInfo
->pNext
,
4940 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4941 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4942 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4944 const struct wsi_memory_allocate_info
*wsi_info
=
4945 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4947 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4948 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4949 /* Apparently, this is allowed */
4950 *pMem
= VK_NULL_HANDLE
;
4954 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4957 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4959 if (wsi_info
&& wsi_info
->implicit_sync
)
4960 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4962 if (dedicate_info
) {
4963 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4964 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4970 float priority_float
= 0.5;
4971 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4972 vk_find_struct_const(pAllocateInfo
->pNext
,
4973 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4975 priority_float
= priority_ext
->priority
;
4977 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4978 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4980 mem
->user_ptr
= NULL
;
4983 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4984 mem
->android_hardware_buffer
= NULL
;
4987 if (ahb_import_info
) {
4988 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4989 if (result
!= VK_SUCCESS
)
4991 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4992 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4993 if (result
!= VK_SUCCESS
)
4995 } else if (import_info
) {
4996 assert(import_info
->handleType
==
4997 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4998 import_info
->handleType
==
4999 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5000 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5003 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5006 close(import_info
->fd
);
5008 } else if (host_ptr_info
) {
5009 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5010 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5011 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5012 pAllocateInfo
->allocationSize
,
5015 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5018 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5021 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5022 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5023 radv_is_mem_type_gtt_cached(mem_type_index
))
5024 domain
= RADEON_DOMAIN_GTT
;
5026 domain
= RADEON_DOMAIN_VRAM
;
5028 if (radv_is_mem_type_vram(mem_type_index
))
5029 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5031 flags
|= RADEON_FLAG_CPU_ACCESS
;
5033 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5034 flags
|= RADEON_FLAG_GTT_WC
;
5036 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5037 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5038 if (device
->use_global_bo_list
) {
5039 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5043 if (radv_is_mem_type_uncached(mem_type_index
)) {
5044 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5045 flags
|= RADEON_FLAG_VA_UNCACHED
;
5048 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5049 domain
, flags
, priority
);
5052 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5055 mem
->type_index
= mem_type_index
;
5058 result
= radv_bo_list_add(device
, mem
->bo
);
5059 if (result
!= VK_SUCCESS
)
5062 *pMem
= radv_device_memory_to_handle(mem
);
5067 radv_free_memory(device
, pAllocator
,mem
);
5072 VkResult
radv_AllocateMemory(
5074 const VkMemoryAllocateInfo
* pAllocateInfo
,
5075 const VkAllocationCallbacks
* pAllocator
,
5076 VkDeviceMemory
* pMem
)
5078 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5079 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5082 void radv_FreeMemory(
5084 VkDeviceMemory _mem
,
5085 const VkAllocationCallbacks
* pAllocator
)
5087 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5088 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5090 radv_free_memory(device
, pAllocator
, mem
);
5093 VkResult
radv_MapMemory(
5095 VkDeviceMemory _memory
,
5096 VkDeviceSize offset
,
5098 VkMemoryMapFlags flags
,
5101 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5102 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5110 *ppData
= mem
->user_ptr
;
5112 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5119 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5122 void radv_UnmapMemory(
5124 VkDeviceMemory _memory
)
5126 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5127 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5132 if (mem
->user_ptr
== NULL
)
5133 device
->ws
->buffer_unmap(mem
->bo
);
5136 VkResult
radv_FlushMappedMemoryRanges(
5138 uint32_t memoryRangeCount
,
5139 const VkMappedMemoryRange
* pMemoryRanges
)
5144 VkResult
radv_InvalidateMappedMemoryRanges(
5146 uint32_t memoryRangeCount
,
5147 const VkMappedMemoryRange
* pMemoryRanges
)
5152 void radv_GetBufferMemoryRequirements(
5155 VkMemoryRequirements
* pMemoryRequirements
)
5157 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5158 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5160 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5162 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5163 pMemoryRequirements
->alignment
= 4096;
5165 pMemoryRequirements
->alignment
= 16;
5167 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5170 void radv_GetBufferMemoryRequirements2(
5172 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5173 VkMemoryRequirements2
*pMemoryRequirements
)
5175 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5176 &pMemoryRequirements
->memoryRequirements
);
5177 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5178 switch (ext
->sType
) {
5179 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5180 VkMemoryDedicatedRequirements
*req
=
5181 (VkMemoryDedicatedRequirements
*) ext
;
5182 req
->requiresDedicatedAllocation
= false;
5183 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5192 void radv_GetImageMemoryRequirements(
5195 VkMemoryRequirements
* pMemoryRequirements
)
5197 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5198 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5200 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5202 pMemoryRequirements
->size
= image
->size
;
5203 pMemoryRequirements
->alignment
= image
->alignment
;
5206 void radv_GetImageMemoryRequirements2(
5208 const VkImageMemoryRequirementsInfo2
*pInfo
,
5209 VkMemoryRequirements2
*pMemoryRequirements
)
5211 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5212 &pMemoryRequirements
->memoryRequirements
);
5214 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5216 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5217 switch (ext
->sType
) {
5218 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5219 VkMemoryDedicatedRequirements
*req
=
5220 (VkMemoryDedicatedRequirements
*) ext
;
5221 req
->requiresDedicatedAllocation
= image
->shareable
&&
5222 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5223 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5232 void radv_GetImageSparseMemoryRequirements(
5235 uint32_t* pSparseMemoryRequirementCount
,
5236 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5241 void radv_GetImageSparseMemoryRequirements2(
5243 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5244 uint32_t* pSparseMemoryRequirementCount
,
5245 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5250 void radv_GetDeviceMemoryCommitment(
5252 VkDeviceMemory memory
,
5253 VkDeviceSize
* pCommittedMemoryInBytes
)
5255 *pCommittedMemoryInBytes
= 0;
5258 VkResult
radv_BindBufferMemory2(VkDevice device
,
5259 uint32_t bindInfoCount
,
5260 const VkBindBufferMemoryInfo
*pBindInfos
)
5262 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5263 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5264 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5267 buffer
->bo
= mem
->bo
;
5268 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5276 VkResult
radv_BindBufferMemory(
5279 VkDeviceMemory memory
,
5280 VkDeviceSize memoryOffset
)
5282 const VkBindBufferMemoryInfo info
= {
5283 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5286 .memoryOffset
= memoryOffset
5289 return radv_BindBufferMemory2(device
, 1, &info
);
5292 VkResult
radv_BindImageMemory2(VkDevice device
,
5293 uint32_t bindInfoCount
,
5294 const VkBindImageMemoryInfo
*pBindInfos
)
5296 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5297 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5298 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5301 image
->bo
= mem
->bo
;
5302 image
->offset
= pBindInfos
[i
].memoryOffset
;
5312 VkResult
radv_BindImageMemory(
5315 VkDeviceMemory memory
,
5316 VkDeviceSize memoryOffset
)
5318 const VkBindImageMemoryInfo info
= {
5319 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5322 .memoryOffset
= memoryOffset
5325 return radv_BindImageMemory2(device
, 1, &info
);
5328 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5330 return info
->bufferBindCount
||
5331 info
->imageOpaqueBindCount
||
5332 info
->imageBindCount
||
5333 info
->waitSemaphoreCount
||
5334 info
->signalSemaphoreCount
;
5337 VkResult
radv_QueueBindSparse(
5339 uint32_t bindInfoCount
,
5340 const VkBindSparseInfo
* pBindInfo
,
5343 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5345 uint32_t fence_idx
= 0;
5347 if (fence
!= VK_NULL_HANDLE
) {
5348 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5349 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5352 fence_idx
= UINT32_MAX
;
5354 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5355 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5358 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5359 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5361 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5362 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5363 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5364 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5365 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5366 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5367 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5368 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5369 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5370 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5371 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5372 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5373 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5374 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5377 if (result
!= VK_SUCCESS
)
5381 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5382 result
= radv_signal_fence(queue
, fence
);
5383 if (result
!= VK_SUCCESS
)
5390 VkResult
radv_CreateFence(
5392 const VkFenceCreateInfo
* pCreateInfo
,
5393 const VkAllocationCallbacks
* pAllocator
,
5396 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5397 const VkExportFenceCreateInfo
*export
=
5398 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5399 VkExternalFenceHandleTypeFlags handleTypes
=
5400 export
? export
->handleTypes
: 0;
5402 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5407 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5409 fence
->fence_wsi
= NULL
;
5410 fence
->temp_syncobj
= 0;
5411 if (device
->always_use_syncobj
|| handleTypes
) {
5412 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5414 vk_free2(&device
->alloc
, pAllocator
, fence
);
5415 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5417 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5418 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5420 fence
->fence
= NULL
;
5422 fence
->fence
= device
->ws
->create_fence();
5423 if (!fence
->fence
) {
5424 vk_free2(&device
->alloc
, pAllocator
, fence
);
5425 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5428 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5429 device
->ws
->signal_fence(fence
->fence
);
5432 *pFence
= radv_fence_to_handle(fence
);
5437 void radv_DestroyFence(
5440 const VkAllocationCallbacks
* pAllocator
)
5442 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5443 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5448 if (fence
->temp_syncobj
)
5449 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5451 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5453 device
->ws
->destroy_fence(fence
->fence
);
5454 if (fence
->fence_wsi
)
5455 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5456 vk_free2(&device
->alloc
, pAllocator
, fence
);
5460 uint64_t radv_get_current_time(void)
5463 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5464 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5467 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5469 uint64_t current_time
= radv_get_current_time();
5471 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5473 return current_time
+ timeout
;
5477 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5478 uint32_t fenceCount
, const VkFence
*pFences
)
5480 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5481 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5482 if (fence
->fence
== NULL
|| fence
->syncobj
||
5483 fence
->temp_syncobj
|| fence
->fence_wsi
||
5484 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5490 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5492 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5493 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5494 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5500 VkResult
radv_WaitForFences(
5502 uint32_t fenceCount
,
5503 const VkFence
* pFences
,
5507 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5508 timeout
= radv_get_absolute_timeout(timeout
);
5510 if (device
->always_use_syncobj
&&
5511 radv_all_fences_syncobj(fenceCount
, pFences
))
5513 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5515 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5517 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5518 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5519 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5522 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5525 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5528 if (!waitAll
&& fenceCount
> 1) {
5529 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5530 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5531 uint32_t wait_count
= 0;
5532 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5534 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5536 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5537 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5539 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5544 fences
[wait_count
++] = fence
->fence
;
5547 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5548 waitAll
, timeout
- radv_get_current_time());
5551 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5554 while(radv_get_current_time() <= timeout
) {
5555 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5556 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5563 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5564 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5565 bool expired
= false;
5567 if (fence
->temp_syncobj
) {
5568 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5573 if (fence
->syncobj
) {
5574 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5580 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5581 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5582 radv_get_current_time() <= timeout
)
5586 expired
= device
->ws
->fence_wait(device
->ws
,
5593 if (fence
->fence_wsi
) {
5594 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5595 if (result
!= VK_SUCCESS
)
5603 VkResult
radv_ResetFences(VkDevice _device
,
5604 uint32_t fenceCount
,
5605 const VkFence
*pFences
)
5607 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5609 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5610 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5612 device
->ws
->reset_fence(fence
->fence
);
5614 /* Per spec, we first restore the permanent payload, and then reset, so
5615 * having a temp syncobj should not skip resetting the permanent syncobj. */
5616 if (fence
->temp_syncobj
) {
5617 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5618 fence
->temp_syncobj
= 0;
5621 if (fence
->syncobj
) {
5622 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5629 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5631 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5632 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5634 if (fence
->temp_syncobj
) {
5635 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5636 return success
? VK_SUCCESS
: VK_NOT_READY
;
5639 if (fence
->syncobj
) {
5640 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5641 return success
? VK_SUCCESS
: VK_NOT_READY
;
5645 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5646 return VK_NOT_READY
;
5648 if (fence
->fence_wsi
) {
5649 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5651 if (result
!= VK_SUCCESS
) {
5652 if (result
== VK_TIMEOUT
)
5653 return VK_NOT_READY
;
5661 // Queue semaphore functions
5664 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5666 timeline
->highest_signaled
= value
;
5667 timeline
->highest_submitted
= value
;
5668 list_inithead(&timeline
->points
);
5669 list_inithead(&timeline
->free_points
);
5670 list_inithead(&timeline
->waiters
);
5671 pthread_mutex_init(&timeline
->mutex
, NULL
);
5675 radv_destroy_timeline(struct radv_device
*device
,
5676 struct radv_timeline
*timeline
)
5678 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5679 &timeline
->free_points
, list
) {
5680 list_del(&point
->list
);
5681 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5684 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5685 &timeline
->points
, list
) {
5686 list_del(&point
->list
);
5687 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5690 pthread_mutex_destroy(&timeline
->mutex
);
5694 radv_timeline_gc_locked(struct radv_device
*device
,
5695 struct radv_timeline
*timeline
)
5697 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5698 &timeline
->points
, list
) {
5699 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5702 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5703 timeline
->highest_signaled
= point
->value
;
5704 list_del(&point
->list
);
5705 list_add(&point
->list
, &timeline
->free_points
);
5710 static struct radv_timeline_point
*
5711 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5712 struct radv_timeline
*timeline
,
5715 radv_timeline_gc_locked(device
, timeline
);
5717 if (p
<= timeline
->highest_signaled
)
5720 list_for_each_entry(struct radv_timeline_point
, point
,
5721 &timeline
->points
, list
) {
5722 if (point
->value
>= p
) {
5723 ++point
->wait_count
;
5730 static struct radv_timeline_point
*
5731 radv_timeline_add_point_locked(struct radv_device
*device
,
5732 struct radv_timeline
*timeline
,
5735 radv_timeline_gc_locked(device
, timeline
);
5737 struct radv_timeline_point
*ret
= NULL
;
5738 struct radv_timeline_point
*prev
= NULL
;
5740 if (p
<= timeline
->highest_signaled
)
5743 list_for_each_entry(struct radv_timeline_point
, point
,
5744 &timeline
->points
, list
) {
5745 if (point
->value
== p
) {
5749 if (point
->value
< p
)
5753 if (list_is_empty(&timeline
->free_points
)) {
5754 ret
= malloc(sizeof(struct radv_timeline_point
));
5755 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5757 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5758 list_del(&ret
->list
);
5760 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5764 ret
->wait_count
= 1;
5767 list_add(&ret
->list
, &prev
->list
);
5769 list_addtail(&ret
->list
, &timeline
->points
);
5776 radv_timeline_wait_locked(struct radv_device
*device
,
5777 struct radv_timeline
*timeline
,
5779 uint64_t abs_timeout
)
5781 while(timeline
->highest_submitted
< value
) {
5782 struct timespec abstime
;
5783 timespec_from_nsec(&abstime
, abs_timeout
);
5785 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5787 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5791 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5795 pthread_mutex_unlock(&timeline
->mutex
);
5797 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5799 pthread_mutex_lock(&timeline
->mutex
);
5800 point
->wait_count
--;
5801 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5805 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5806 struct list_head
*processing_list
)
5808 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5809 &timeline
->waiters
, list
) {
5810 if (waiter
->value
> timeline
->highest_submitted
)
5813 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5814 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5816 list_del(&waiter
->list
);
5821 void radv_destroy_semaphore_part(struct radv_device
*device
,
5822 struct radv_semaphore_part
*part
)
5824 switch(part
->kind
) {
5825 case RADV_SEMAPHORE_NONE
:
5827 case RADV_SEMAPHORE_WINSYS
:
5828 device
->ws
->destroy_sem(part
->ws_sem
);
5830 case RADV_SEMAPHORE_TIMELINE
:
5831 radv_destroy_timeline(device
, &part
->timeline
);
5833 case RADV_SEMAPHORE_SYNCOBJ
:
5834 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5837 part
->kind
= RADV_SEMAPHORE_NONE
;
5840 static VkSemaphoreTypeKHR
5841 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5843 const VkSemaphoreTypeCreateInfo
*type_info
=
5844 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5847 return VK_SEMAPHORE_TYPE_BINARY
;
5850 *initial_value
= type_info
->initialValue
;
5851 return type_info
->semaphoreType
;
5854 VkResult
radv_CreateSemaphore(
5856 const VkSemaphoreCreateInfo
* pCreateInfo
,
5857 const VkAllocationCallbacks
* pAllocator
,
5858 VkSemaphore
* pSemaphore
)
5860 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5861 const VkExportSemaphoreCreateInfo
*export
=
5862 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5863 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5864 export
? export
->handleTypes
: 0;
5865 uint64_t initial_value
= 0;
5866 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5868 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5870 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5872 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5874 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5875 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5877 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5878 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5879 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5880 } else if (device
->always_use_syncobj
|| handleTypes
) {
5881 assert (device
->physical_device
->rad_info
.has_syncobj
);
5882 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
5884 vk_free2(&device
->alloc
, pAllocator
, sem
);
5885 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5887 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5889 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5890 if (!sem
->permanent
.ws_sem
) {
5891 vk_free2(&device
->alloc
, pAllocator
, sem
);
5892 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5894 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5897 *pSemaphore
= radv_semaphore_to_handle(sem
);
5901 void radv_DestroySemaphore(
5903 VkSemaphore _semaphore
,
5904 const VkAllocationCallbacks
* pAllocator
)
5906 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5907 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5911 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5912 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5913 vk_free2(&device
->alloc
, pAllocator
, sem
);
5917 radv_GetSemaphoreCounterValue(VkDevice _device
,
5918 VkSemaphore _semaphore
,
5921 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5922 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5924 struct radv_semaphore_part
*part
=
5925 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5927 switch (part
->kind
) {
5928 case RADV_SEMAPHORE_TIMELINE
: {
5929 pthread_mutex_lock(&part
->timeline
.mutex
);
5930 radv_timeline_gc_locked(device
, &part
->timeline
);
5931 *pValue
= part
->timeline
.highest_signaled
;
5932 pthread_mutex_unlock(&part
->timeline
.mutex
);
5935 case RADV_SEMAPHORE_NONE
:
5936 case RADV_SEMAPHORE_SYNCOBJ
:
5937 case RADV_SEMAPHORE_WINSYS
:
5938 unreachable("Invalid semaphore type");
5940 unreachable("Unhandled semaphore type");
5945 radv_wait_timelines(struct radv_device
*device
,
5946 const VkSemaphoreWaitInfo
* pWaitInfo
,
5947 uint64_t abs_timeout
)
5949 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5951 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5952 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5953 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5954 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5955 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5957 if (result
== VK_SUCCESS
)
5960 if (radv_get_current_time() > abs_timeout
)
5965 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5966 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5967 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5968 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5969 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5971 if (result
!= VK_SUCCESS
)
5977 radv_WaitSemaphores(VkDevice _device
,
5978 const VkSemaphoreWaitInfo
* pWaitInfo
,
5981 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5982 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5983 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5987 radv_SignalSemaphore(VkDevice _device
,
5988 const VkSemaphoreSignalInfo
* pSignalInfo
)
5990 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5991 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
5993 struct radv_semaphore_part
*part
=
5994 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5996 switch(part
->kind
) {
5997 case RADV_SEMAPHORE_TIMELINE
: {
5998 pthread_mutex_lock(&part
->timeline
.mutex
);
5999 radv_timeline_gc_locked(device
, &part
->timeline
);
6000 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6001 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6003 struct list_head processing_list
;
6004 list_inithead(&processing_list
);
6005 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6006 pthread_mutex_unlock(&part
->timeline
.mutex
);
6008 return radv_process_submissions(&processing_list
);
6010 case RADV_SEMAPHORE_NONE
:
6011 case RADV_SEMAPHORE_SYNCOBJ
:
6012 case RADV_SEMAPHORE_WINSYS
:
6013 unreachable("Invalid semaphore type");
6020 VkResult
radv_CreateEvent(
6022 const VkEventCreateInfo
* pCreateInfo
,
6023 const VkAllocationCallbacks
* pAllocator
,
6026 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6027 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6029 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6032 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6034 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6036 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6037 RADV_BO_PRIORITY_FENCE
);
6039 vk_free2(&device
->alloc
, pAllocator
, event
);
6040 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6043 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6045 *pEvent
= radv_event_to_handle(event
);
6050 void radv_DestroyEvent(
6053 const VkAllocationCallbacks
* pAllocator
)
6055 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6056 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6060 device
->ws
->buffer_destroy(event
->bo
);
6061 vk_free2(&device
->alloc
, pAllocator
, event
);
6064 VkResult
radv_GetEventStatus(
6068 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6070 if (*event
->map
== 1)
6071 return VK_EVENT_SET
;
6072 return VK_EVENT_RESET
;
6075 VkResult
radv_SetEvent(
6079 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6085 VkResult
radv_ResetEvent(
6089 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6095 VkResult
radv_CreateBuffer(
6097 const VkBufferCreateInfo
* pCreateInfo
,
6098 const VkAllocationCallbacks
* pAllocator
,
6101 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6102 struct radv_buffer
*buffer
;
6104 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6106 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6107 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6109 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6111 buffer
->size
= pCreateInfo
->size
;
6112 buffer
->usage
= pCreateInfo
->usage
;
6115 buffer
->flags
= pCreateInfo
->flags
;
6117 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6118 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6120 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6121 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6122 align64(buffer
->size
, 4096),
6123 4096, 0, RADEON_FLAG_VIRTUAL
,
6124 RADV_BO_PRIORITY_VIRTUAL
);
6126 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6127 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6131 *pBuffer
= radv_buffer_to_handle(buffer
);
6136 void radv_DestroyBuffer(
6139 const VkAllocationCallbacks
* pAllocator
)
6141 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6142 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6147 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6148 device
->ws
->buffer_destroy(buffer
->bo
);
6150 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6153 VkDeviceAddress
radv_GetBufferDeviceAddress(
6155 const VkBufferDeviceAddressInfo
* pInfo
)
6157 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6158 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6162 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6163 const VkBufferDeviceAddressInfo
* pInfo
)
6168 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6169 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6174 static inline unsigned
6175 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6178 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6180 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6183 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6185 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6189 radv_init_dcc_control_reg(struct radv_device
*device
,
6190 struct radv_image_view
*iview
)
6192 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6193 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6194 unsigned max_compressed_block_size
;
6195 unsigned independent_128b_blocks
;
6196 unsigned independent_64b_blocks
;
6198 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6201 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6202 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6203 * dGPU and 64 for APU because all of our APUs to date use
6204 * DIMMs which have a request granularity size of 64B while all
6205 * other chips have a 32B request size.
6207 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6210 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6211 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6212 independent_64b_blocks
= 0;
6213 independent_128b_blocks
= 1;
6215 independent_128b_blocks
= 0;
6217 if (iview
->image
->info
.samples
> 1) {
6218 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6219 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6220 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6221 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6224 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6225 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6226 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6227 /* If this DCC image is potentially going to be used in texture
6228 * fetches, we need some special settings.
6230 independent_64b_blocks
= 1;
6231 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6233 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6234 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6235 * big as possible for better compression state.
6237 independent_64b_blocks
= 0;
6238 max_compressed_block_size
= max_uncompressed_block_size
;
6242 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6243 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6244 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6245 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6246 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6250 radv_initialise_color_surface(struct radv_device
*device
,
6251 struct radv_color_buffer_info
*cb
,
6252 struct radv_image_view
*iview
)
6254 const struct vk_format_description
*desc
;
6255 unsigned ntype
, format
, swap
, endian
;
6256 unsigned blend_clamp
= 0, blend_bypass
= 0;
6258 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6259 const struct radeon_surf
*surf
= &plane
->surface
;
6261 desc
= vk_format_description(iview
->vk_format
);
6263 memset(cb
, 0, sizeof(*cb
));
6265 /* Intensity is implemented as Red, so treat it that way. */
6266 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6268 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6270 cb
->cb_color_base
= va
>> 8;
6272 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6273 struct gfx9_surf_meta_flags meta
;
6274 if (iview
->image
->dcc_offset
)
6275 meta
= surf
->u
.gfx9
.dcc
;
6277 meta
= surf
->u
.gfx9
.cmask
;
6279 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6280 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6281 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6282 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6283 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6285 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6286 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6287 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6288 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6289 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6292 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6293 cb
->cb_color_base
|= surf
->tile_swizzle
;
6295 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6296 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6298 cb
->cb_color_base
+= level_info
->offset
>> 8;
6299 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6300 cb
->cb_color_base
|= surf
->tile_swizzle
;
6302 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6303 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6304 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6306 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6307 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6308 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6310 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6312 if (radv_image_has_fmask(iview
->image
)) {
6313 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6314 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6315 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6316 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6318 /* This must be set for fast clear to work without FMASK. */
6319 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6320 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6321 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6322 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6326 /* CMASK variables */
6327 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6328 va
+= iview
->image
->cmask_offset
;
6329 cb
->cb_color_cmask
= va
>> 8;
6331 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6332 va
+= iview
->image
->dcc_offset
;
6334 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6335 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6336 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6338 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6339 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6341 cb
->cb_dcc_base
= va
>> 8;
6342 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6344 /* GFX10 field has the same base shift as the GFX6 field. */
6345 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6346 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6347 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6349 if (iview
->image
->info
.samples
> 1) {
6350 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6352 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6353 S_028C74_NUM_FRAGMENTS(log_samples
);
6356 if (radv_image_has_fmask(iview
->image
)) {
6357 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6358 cb
->cb_color_fmask
= va
>> 8;
6359 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6361 cb
->cb_color_fmask
= cb
->cb_color_base
;
6364 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6366 vk_format_get_first_non_void_channel(iview
->vk_format
));
6367 format
= radv_translate_colorformat(iview
->vk_format
);
6368 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6369 radv_finishme("Illegal color\n");
6370 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6371 endian
= radv_colorformat_endian_swap(format
);
6373 /* blend clamp should be set for all NORM/SRGB types */
6374 if (ntype
== V_028C70_NUMBER_UNORM
||
6375 ntype
== V_028C70_NUMBER_SNORM
||
6376 ntype
== V_028C70_NUMBER_SRGB
)
6379 /* set blend bypass according to docs if SINT/UINT or
6380 8/24 COLOR variants */
6381 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6382 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6383 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6388 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6389 (format
== V_028C70_COLOR_8
||
6390 format
== V_028C70_COLOR_8_8
||
6391 format
== V_028C70_COLOR_8_8_8_8
))
6392 ->color_is_int8
= true;
6394 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6395 S_028C70_COMP_SWAP(swap
) |
6396 S_028C70_BLEND_CLAMP(blend_clamp
) |
6397 S_028C70_BLEND_BYPASS(blend_bypass
) |
6398 S_028C70_SIMPLE_FLOAT(1) |
6399 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6400 ntype
!= V_028C70_NUMBER_SNORM
&&
6401 ntype
!= V_028C70_NUMBER_SRGB
&&
6402 format
!= V_028C70_COLOR_8_24
&&
6403 format
!= V_028C70_COLOR_24_8
) |
6404 S_028C70_NUMBER_TYPE(ntype
) |
6405 S_028C70_ENDIAN(endian
);
6406 if (radv_image_has_fmask(iview
->image
)) {
6407 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6408 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6409 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6410 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6413 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6414 /* Allow the texture block to read FMASK directly
6415 * without decompressing it. This bit must be cleared
6416 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6417 * otherwise the operation doesn't happen.
6419 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6421 /* Set CMASK into a tiling format that allows the
6422 * texture block to read it.
6424 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6428 if (radv_image_has_cmask(iview
->image
) &&
6429 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6430 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6432 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6433 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6435 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6437 /* This must be set for fast clear to work without FMASK. */
6438 if (!radv_image_has_fmask(iview
->image
) &&
6439 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6440 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6441 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6444 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6445 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6447 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6448 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6449 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6450 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6452 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6453 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6455 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6456 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6457 S_028EE0_RESOURCE_LEVEL(1);
6459 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6460 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6461 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6464 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6465 S_028C68_MIP0_HEIGHT(height
- 1) |
6466 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6471 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6472 struct radv_image_view
*iview
)
6474 unsigned max_zplanes
= 0;
6476 assert(radv_image_is_tc_compat_htile(iview
->image
));
6478 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6479 /* Default value for 32-bit depth surfaces. */
6482 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6483 iview
->image
->info
.samples
> 1)
6486 max_zplanes
= max_zplanes
+ 1;
6488 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6489 /* Do not enable Z plane compression for 16-bit depth
6490 * surfaces because isn't supported on GFX8. Only
6491 * 32-bit depth surfaces are supported by the hardware.
6492 * This allows to maintain shader compatibility and to
6493 * reduce the number of depth decompressions.
6497 if (iview
->image
->info
.samples
<= 1)
6499 else if (iview
->image
->info
.samples
<= 4)
6510 radv_initialise_ds_surface(struct radv_device
*device
,
6511 struct radv_ds_buffer_info
*ds
,
6512 struct radv_image_view
*iview
)
6514 unsigned level
= iview
->base_mip
;
6515 unsigned format
, stencil_format
;
6516 uint64_t va
, s_offs
, z_offs
;
6517 bool stencil_only
= false;
6518 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6519 const struct radeon_surf
*surf
= &plane
->surface
;
6521 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6523 memset(ds
, 0, sizeof(*ds
));
6524 switch (iview
->image
->vk_format
) {
6525 case VK_FORMAT_D24_UNORM_S8_UINT
:
6526 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6527 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6528 ds
->offset_scale
= 2.0f
;
6530 case VK_FORMAT_D16_UNORM
:
6531 case VK_FORMAT_D16_UNORM_S8_UINT
:
6532 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6533 ds
->offset_scale
= 4.0f
;
6535 case VK_FORMAT_D32_SFLOAT
:
6536 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6537 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6538 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6539 ds
->offset_scale
= 1.0f
;
6541 case VK_FORMAT_S8_UINT
:
6542 stencil_only
= true;
6548 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6549 stencil_format
= surf
->has_stencil
?
6550 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6552 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6553 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6554 S_028008_SLICE_MAX(max_slice
);
6555 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6556 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6557 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6560 ds
->db_htile_data_base
= 0;
6561 ds
->db_htile_surface
= 0;
6563 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6564 s_offs
= z_offs
= va
;
6566 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6567 assert(surf
->u
.gfx9
.surf_offset
== 0);
6568 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6570 ds
->db_z_info
= S_028038_FORMAT(format
) |
6571 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6572 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6573 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6574 S_028038_ZRANGE_PRECISION(1);
6575 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6576 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6578 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6579 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6580 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6583 ds
->db_depth_view
|= S_028008_MIPID(level
);
6584 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6585 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6587 if (radv_htile_enabled(iview
->image
, level
)) {
6588 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6590 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6591 unsigned max_zplanes
=
6592 radv_calc_decompress_on_z_planes(device
, iview
);
6594 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6596 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6597 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6598 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6600 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6601 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6605 if (!surf
->has_stencil
)
6606 /* Use all of the htile_buffer for depth if there's no stencil. */
6607 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6608 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6609 iview
->image
->htile_offset
;
6610 ds
->db_htile_data_base
= va
>> 8;
6611 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6612 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6614 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6615 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6619 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6622 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6624 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6625 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6627 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6628 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6629 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6631 if (iview
->image
->info
.samples
> 1)
6632 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6634 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6635 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6636 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6637 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6638 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6639 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6640 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6641 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6644 tile_mode
= stencil_tile_mode
;
6646 ds
->db_depth_info
|=
6647 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6648 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6649 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6650 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6651 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6652 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6653 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6654 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6656 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6657 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6658 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6659 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6661 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6664 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6665 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6666 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6668 if (radv_htile_enabled(iview
->image
, level
)) {
6669 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6671 if (!surf
->has_stencil
&&
6672 !radv_image_is_tc_compat_htile(iview
->image
))
6673 /* Use all of the htile_buffer for depth if there's no stencil. */
6674 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6676 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6677 iview
->image
->htile_offset
;
6678 ds
->db_htile_data_base
= va
>> 8;
6679 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6681 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6682 unsigned max_zplanes
=
6683 radv_calc_decompress_on_z_planes(device
, iview
);
6685 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6686 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6691 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6692 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6695 VkResult
radv_CreateFramebuffer(
6697 const VkFramebufferCreateInfo
* pCreateInfo
,
6698 const VkAllocationCallbacks
* pAllocator
,
6699 VkFramebuffer
* pFramebuffer
)
6701 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6702 struct radv_framebuffer
*framebuffer
;
6703 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6704 vk_find_struct_const(pCreateInfo
->pNext
,
6705 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6707 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6709 size_t size
= sizeof(*framebuffer
);
6710 if (!imageless_create_info
)
6711 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6712 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6713 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6714 if (framebuffer
== NULL
)
6715 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6717 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6718 framebuffer
->width
= pCreateInfo
->width
;
6719 framebuffer
->height
= pCreateInfo
->height
;
6720 framebuffer
->layers
= pCreateInfo
->layers
;
6721 if (imageless_create_info
) {
6722 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6723 const VkFramebufferAttachmentImageInfo
*attachment
=
6724 imageless_create_info
->pAttachmentImageInfos
+ i
;
6725 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6726 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6727 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6730 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6731 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6732 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6733 framebuffer
->attachments
[i
] = iview
;
6734 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6735 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6736 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6740 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6744 void radv_DestroyFramebuffer(
6747 const VkAllocationCallbacks
* pAllocator
)
6749 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6750 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6754 vk_free2(&device
->alloc
, pAllocator
, fb
);
6757 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6759 switch (address_mode
) {
6760 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6761 return V_008F30_SQ_TEX_WRAP
;
6762 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6763 return V_008F30_SQ_TEX_MIRROR
;
6764 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6765 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6766 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6767 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6768 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6769 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6771 unreachable("illegal tex wrap mode");
6777 radv_tex_compare(VkCompareOp op
)
6780 case VK_COMPARE_OP_NEVER
:
6781 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6782 case VK_COMPARE_OP_LESS
:
6783 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6784 case VK_COMPARE_OP_EQUAL
:
6785 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6786 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6787 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6788 case VK_COMPARE_OP_GREATER
:
6789 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6790 case VK_COMPARE_OP_NOT_EQUAL
:
6791 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6792 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6793 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6794 case VK_COMPARE_OP_ALWAYS
:
6795 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6797 unreachable("illegal compare mode");
6803 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6806 case VK_FILTER_NEAREST
:
6807 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6808 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6809 case VK_FILTER_LINEAR
:
6810 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6811 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6812 case VK_FILTER_CUBIC_IMG
:
6814 fprintf(stderr
, "illegal texture filter");
6820 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6823 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6824 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6825 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6826 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6828 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6833 radv_tex_bordercolor(VkBorderColor bcolor
)
6836 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6837 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6838 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6839 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6840 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6841 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6842 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6843 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6844 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6852 radv_tex_aniso_filter(unsigned filter
)
6866 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6869 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6870 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6871 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6872 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6873 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6874 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6882 radv_get_max_anisotropy(struct radv_device
*device
,
6883 const VkSamplerCreateInfo
*pCreateInfo
)
6885 if (device
->force_aniso
>= 0)
6886 return device
->force_aniso
;
6888 if (pCreateInfo
->anisotropyEnable
&&
6889 pCreateInfo
->maxAnisotropy
> 1.0f
)
6890 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6896 radv_init_sampler(struct radv_device
*device
,
6897 struct radv_sampler
*sampler
,
6898 const VkSamplerCreateInfo
*pCreateInfo
)
6900 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6901 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6902 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6903 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6904 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6905 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6907 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6908 vk_find_struct_const(pCreateInfo
->pNext
,
6909 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6910 if (sampler_reduction
)
6911 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6913 if (pCreateInfo
->compareEnable
)
6914 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6916 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6917 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6918 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6919 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6920 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6921 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6922 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6923 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6924 S_008F30_DISABLE_CUBE_WRAP(0) |
6925 S_008F30_COMPAT_MODE(compat_mode
) |
6926 S_008F30_FILTER_MODE(filter_mode
));
6927 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6928 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6929 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6930 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6931 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6932 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6933 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6934 S_008F38_MIP_POINT_PRECLAMP(0));
6935 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6936 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
6938 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6939 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6941 sampler
->state
[2] |=
6942 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6943 S_008F38_FILTER_PREC_FIX(1) |
6944 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6948 VkResult
radv_CreateSampler(
6950 const VkSamplerCreateInfo
* pCreateInfo
,
6951 const VkAllocationCallbacks
* pAllocator
,
6952 VkSampler
* pSampler
)
6954 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6955 struct radv_sampler
*sampler
;
6957 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
6958 vk_find_struct_const(pCreateInfo
->pNext
,
6959 SAMPLER_YCBCR_CONVERSION_INFO
);
6961 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
6963 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
6964 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6966 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6968 radv_init_sampler(device
, sampler
, pCreateInfo
);
6970 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
6971 *pSampler
= radv_sampler_to_handle(sampler
);
6976 void radv_DestroySampler(
6979 const VkAllocationCallbacks
* pAllocator
)
6981 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6982 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
6986 vk_free2(&device
->alloc
, pAllocator
, sampler
);
6989 /* vk_icd.h does not declare this function, so we declare it here to
6990 * suppress Wmissing-prototypes.
6992 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6993 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
6995 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6996 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
6998 /* For the full details on loader interface versioning, see
6999 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7000 * What follows is a condensed summary, to help you navigate the large and
7001 * confusing official doc.
7003 * - Loader interface v0 is incompatible with later versions. We don't
7006 * - In loader interface v1:
7007 * - The first ICD entrypoint called by the loader is
7008 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7010 * - The ICD must statically expose no other Vulkan symbol unless it is
7011 * linked with -Bsymbolic.
7012 * - Each dispatchable Vulkan handle created by the ICD must be
7013 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7014 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7015 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7016 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7017 * such loader-managed surfaces.
7019 * - Loader interface v2 differs from v1 in:
7020 * - The first ICD entrypoint called by the loader is
7021 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7022 * statically expose this entrypoint.
7024 * - Loader interface v3 differs from v2 in:
7025 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7026 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7027 * because the loader no longer does so.
7029 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7033 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7034 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7037 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7038 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7040 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7042 /* At the moment, we support only the below handle types. */
7043 assert(pGetFdInfo
->handleType
==
7044 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7045 pGetFdInfo
->handleType
==
7046 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7048 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7050 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7054 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7055 VkExternalMemoryHandleTypeFlagBits handleType
,
7057 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7059 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7061 switch (handleType
) {
7062 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7063 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7067 /* The valid usage section for this function says:
7069 * "handleType must not be one of the handle types defined as
7072 * So opaque handle types fall into the default "unsupported" case.
7074 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7078 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7082 uint32_t syncobj_handle
= 0;
7083 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7085 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7088 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7090 *syncobj
= syncobj_handle
;
7096 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7100 /* If we create a syncobj we do it locally so that if we have an error, we don't
7101 * leave a syncobj in an undetermined state in the fence. */
7102 uint32_t syncobj_handle
= *syncobj
;
7103 if (!syncobj_handle
) {
7104 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7106 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7111 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7113 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7115 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7118 *syncobj
= syncobj_handle
;
7125 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7126 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7128 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7129 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7131 struct radv_semaphore_part
*dst
= NULL
;
7133 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7134 dst
= &sem
->temporary
;
7136 dst
= &sem
->permanent
;
7139 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7141 switch(pImportSemaphoreFdInfo
->handleType
) {
7142 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7143 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7145 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7146 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7149 unreachable("Unhandled semaphore handle type");
7152 if (result
== VK_SUCCESS
) {
7153 dst
->syncobj
= syncobj
;
7154 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7160 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7161 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7164 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7165 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7167 uint32_t syncobj_handle
;
7169 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7170 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7171 syncobj_handle
= sem
->temporary
.syncobj
;
7173 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7174 syncobj_handle
= sem
->permanent
.syncobj
;
7177 switch(pGetFdInfo
->handleType
) {
7178 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7179 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7181 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7182 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7184 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7185 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7187 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7192 unreachable("Unhandled semaphore handle type");
7196 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7200 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7201 VkPhysicalDevice physicalDevice
,
7202 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7203 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7205 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7206 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7208 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7209 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7210 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7211 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7213 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7214 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7215 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7216 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7217 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7218 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7219 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7220 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7221 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7222 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7223 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7224 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7225 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7227 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7228 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7229 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7233 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7234 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7236 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7237 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7238 uint32_t *syncobj_dst
= NULL
;
7241 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7242 syncobj_dst
= &fence
->temp_syncobj
;
7244 syncobj_dst
= &fence
->syncobj
;
7247 switch(pImportFenceFdInfo
->handleType
) {
7248 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7249 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7250 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7251 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7253 unreachable("Unhandled fence handle type");
7257 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7258 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7261 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7262 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7264 uint32_t syncobj_handle
;
7266 if (fence
->temp_syncobj
)
7267 syncobj_handle
= fence
->temp_syncobj
;
7269 syncobj_handle
= fence
->syncobj
;
7271 switch(pGetFdInfo
->handleType
) {
7272 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7273 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7275 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7276 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7278 if (fence
->temp_syncobj
) {
7279 close (fence
->temp_syncobj
);
7280 fence
->temp_syncobj
= 0;
7282 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7287 unreachable("Unhandled fence handle type");
7291 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7295 void radv_GetPhysicalDeviceExternalFenceProperties(
7296 VkPhysicalDevice physicalDevice
,
7297 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7298 VkExternalFenceProperties
*pExternalFenceProperties
)
7300 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7302 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7303 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7304 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7305 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7306 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7307 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7308 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7310 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7311 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7312 pExternalFenceProperties
->externalFenceFeatures
= 0;
7317 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7318 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7319 const VkAllocationCallbacks
* pAllocator
,
7320 VkDebugReportCallbackEXT
* pCallback
)
7322 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7323 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7324 pCreateInfo
, pAllocator
, &instance
->alloc
,
7329 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7330 VkDebugReportCallbackEXT _callback
,
7331 const VkAllocationCallbacks
* pAllocator
)
7333 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7334 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7335 _callback
, pAllocator
, &instance
->alloc
);
7339 radv_DebugReportMessageEXT(VkInstance _instance
,
7340 VkDebugReportFlagsEXT flags
,
7341 VkDebugReportObjectTypeEXT objectType
,
7344 int32_t messageCode
,
7345 const char* pLayerPrefix
,
7346 const char* pMessage
)
7348 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7349 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7350 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7354 radv_GetDeviceGroupPeerMemoryFeatures(
7357 uint32_t localDeviceIndex
,
7358 uint32_t remoteDeviceIndex
,
7359 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7361 assert(localDeviceIndex
== remoteDeviceIndex
);
7363 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7364 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7365 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7366 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7369 static const VkTimeDomainEXT radv_time_domains
[] = {
7370 VK_TIME_DOMAIN_DEVICE_EXT
,
7371 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7372 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7375 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7376 VkPhysicalDevice physicalDevice
,
7377 uint32_t *pTimeDomainCount
,
7378 VkTimeDomainEXT
*pTimeDomains
)
7381 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7383 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7384 vk_outarray_append(&out
, i
) {
7385 *i
= radv_time_domains
[d
];
7389 return vk_outarray_status(&out
);
7393 radv_clock_gettime(clockid_t clock_id
)
7395 struct timespec current
;
7398 ret
= clock_gettime(clock_id
, ¤t
);
7399 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7400 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7404 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7407 VkResult
radv_GetCalibratedTimestampsEXT(
7409 uint32_t timestampCount
,
7410 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7411 uint64_t *pTimestamps
,
7412 uint64_t *pMaxDeviation
)
7414 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7415 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7417 uint64_t begin
, end
;
7418 uint64_t max_clock_period
= 0;
7420 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7422 for (d
= 0; d
< timestampCount
; d
++) {
7423 switch (pTimestampInfos
[d
].timeDomain
) {
7424 case VK_TIME_DOMAIN_DEVICE_EXT
:
7425 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7427 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7428 max_clock_period
= MAX2(max_clock_period
, device_period
);
7430 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7431 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7432 max_clock_period
= MAX2(max_clock_period
, 1);
7435 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7436 pTimestamps
[d
] = begin
;
7444 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7447 * The maximum deviation is the sum of the interval over which we
7448 * perform the sampling and the maximum period of any sampled
7449 * clock. That's because the maximum skew between any two sampled
7450 * clock edges is when the sampled clock with the largest period is
7451 * sampled at the end of that period but right at the beginning of the
7452 * sampling interval and some other clock is sampled right at the
7453 * begining of its sampling period and right at the end of the
7454 * sampling interval. Let's assume the GPU has the longest clock
7455 * period and that the application is sampling GPU and monotonic:
7458 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7459 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7463 * GPU -----_____-----_____-----_____-----_____
7466 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7467 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7469 * Interval <----------------->
7470 * Deviation <-------------------------->
7474 * m = read(monotonic) 2
7477 * We round the sample interval up by one tick to cover sampling error
7478 * in the interval clock
7481 uint64_t sample_interval
= end
- begin
+ 1;
7483 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7488 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7489 VkPhysicalDevice physicalDevice
,
7490 VkSampleCountFlagBits samples
,
7491 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7493 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7494 VK_SAMPLE_COUNT_4_BIT
|
7495 VK_SAMPLE_COUNT_8_BIT
)) {
7496 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7498 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };