2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
55 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
58 unsigned char sha1
[20];
59 unsigned ptr_size
= sizeof(void*);
61 memset(uuid
, 0, VK_UUID_SIZE
);
62 _mesa_sha1_init(&ctx
);
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
68 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
69 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
70 _mesa_sha1_final(&ctx
, sha1
);
72 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
77 radv_get_driver_uuid(void *uuid
)
79 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
83 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
85 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
89 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
91 const char *chip_string
;
94 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
98 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
101 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
102 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS
: chip_string
= "AMD RADV MULLINS"; break;
104 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
105 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
112 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
115 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
116 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
117 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
118 default: chip_string
= "AMD RADV unknown"; break;
121 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
125 radv_get_visible_vram_size(struct radv_physical_device
*device
)
127 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
131 radv_get_vram_size(struct radv_physical_device
*device
)
133 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
137 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
139 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
140 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
141 uint64_t vram_size
= radv_get_vram_size(device
);
142 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
143 device
->memory_properties
.memoryHeapCount
= 0;
145 vram_index
= device
->memory_properties
.memoryHeapCount
++;
146 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
148 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
151 if (visible_vram_size
) {
152 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
153 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
154 .size
= visible_vram_size
,
155 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
158 if (device
->rad_info
.gart_size
> 0) {
159 gart_index
= device
->memory_properties
.memoryHeapCount
++;
160 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
161 .size
= device
->rad_info
.gart_size
,
162 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
166 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
167 unsigned type_count
= 0;
168 if (vram_index
>= 0) {
169 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
170 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
171 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
172 .heapIndex
= vram_index
,
175 if (gart_index
>= 0) {
176 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
177 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
178 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
180 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
181 .heapIndex
= gart_index
,
184 if (visible_vram_index
>= 0) {
185 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
186 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
187 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
190 .heapIndex
= visible_vram_index
,
193 if (gart_index
>= 0) {
194 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
195 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
196 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
197 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
198 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
199 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
200 .heapIndex
= gart_index
,
203 device
->memory_properties
.memoryTypeCount
= type_count
;
207 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
209 const char *family
= getenv("RADV_FORCE_FAMILY");
215 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
216 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
217 /* Override family and chip_class. */
218 device
->rad_info
.family
= i
;
220 if (i
>= CHIP_VEGA10
)
221 device
->rad_info
.chip_class
= GFX9
;
222 else if (i
>= CHIP_TONGA
)
223 device
->rad_info
.chip_class
= GFX8
;
224 else if (i
>= CHIP_BONAIRE
)
225 device
->rad_info
.chip_class
= GFX7
;
227 device
->rad_info
.chip_class
= GFX6
;
233 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
238 radv_physical_device_init(struct radv_physical_device
*device
,
239 struct radv_instance
*instance
,
240 drmDevicePtr drm_device
)
242 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
244 drmVersionPtr version
;
248 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
250 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
251 radv_logi("Could not open device '%s'", path
);
253 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
256 version
= drmGetVersion(fd
);
260 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
261 radv_logi("Could not get the kernel driver version for device '%s'", path
);
263 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
264 "failed to get version %s: %m", path
);
267 if (strcmp(version
->name
, "amdgpu")) {
268 drmFreeVersion(version
);
271 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
274 return VK_ERROR_INCOMPATIBLE_DRIVER
;
276 drmFreeVersion(version
);
278 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
279 radv_logi("Found compatible device '%s'.", path
);
281 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
282 device
->instance
= instance
;
284 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
285 instance
->perftest_flags
);
287 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
291 if (instance
->enabled_extensions
.KHR_display
) {
292 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
293 if (master_fd
>= 0) {
294 uint32_t accel_working
= 0;
295 struct drm_amdgpu_info request
= {
296 .return_pointer
= (uintptr_t)&accel_working
,
297 .return_size
= sizeof(accel_working
),
298 .query
= AMDGPU_INFO_ACCEL_WORKING
301 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
308 device
->master_fd
= master_fd
;
309 device
->local_fd
= fd
;
310 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
312 radv_handle_env_var_force_family(device
);
314 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
316 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
317 device
->ws
->destroy(device
->ws
);
318 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
319 "cannot generate UUID");
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags
=
325 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
326 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
331 char buf
[VK_UUID_SIZE
* 2 + 1];
332 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
333 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
335 if (device
->rad_info
.chip_class
< GFX8
||
336 device
->rad_info
.chip_class
> GFX9
)
337 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 radv_get_driver_uuid(&device
->driver_uuid
);
340 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
342 if (device
->rad_info
.family
== CHIP_STONEY
||
343 device
->rad_info
.chip_class
>= GFX9
) {
344 device
->has_rbplus
= true;
345 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
346 device
->rad_info
.family
== CHIP_VEGA12
||
347 device
->rad_info
.family
== CHIP_RAVEN
||
348 device
->rad_info
.family
== CHIP_RAVEN2
;
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
354 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
356 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
360 device
->rad_info
.family
== CHIP_RAVEN
;
362 /* Out-of-order primitive rasterization. */
363 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
364 device
->rad_info
.max_se
>= 2;
365 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
366 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
368 device
->dcc_msaa_allowed
=
369 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
372 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
373 (device
->rad_info
.chip_class
>= GFX8
&&
374 device
->rad_info
.me_fw_feature
>= 41);
376 radv_physical_device_init_mem_types(device
);
377 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
379 device
->bus_info
= *drm_device
->businfo
.pci
;
381 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
382 ac_print_gpu_info(&device
->rad_info
);
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
388 result
= radv_init_wsi(device
);
389 if (result
!= VK_SUCCESS
) {
390 device
->ws
->destroy(device
->ws
);
391 vk_error(instance
, result
);
405 radv_physical_device_finish(struct radv_physical_device
*device
)
407 radv_finish_wsi(device
);
408 device
->ws
->destroy(device
->ws
);
409 disk_cache_destroy(device
->disk_cache
);
410 close(device
->local_fd
);
411 if (device
->master_fd
!= -1)
412 close(device
->master_fd
);
416 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
417 VkSystemAllocationScope allocationScope
)
423 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
424 size_t align
, VkSystemAllocationScope allocationScope
)
426 return realloc(pOriginal
, size
);
430 default_free_func(void *pUserData
, void *pMemory
)
435 static const VkAllocationCallbacks default_alloc
= {
437 .pfnAllocation
= default_alloc_func
,
438 .pfnReallocation
= default_realloc_func
,
439 .pfnFree
= default_free_func
,
442 static const struct debug_control radv_debug_options
[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
444 {"nodcc", RADV_DEBUG_NO_DCC
},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
446 {"nocache", RADV_DEBUG_NO_CACHE
},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
448 {"nohiz", RADV_DEBUG_NO_HIZ
},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
451 {"allbos", RADV_DEBUG_ALL_BOS
},
452 {"noibs", RADV_DEBUG_NO_IBS
},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
457 {"nosisched", RADV_DEBUG_NO_SISCHED
},
458 {"preoptir", RADV_DEBUG_PREOPTIR
},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
461 {"info", RADV_DEBUG_INFO
},
462 {"errors", RADV_DEBUG_ERRORS
},
463 {"startup", RADV_DEBUG_STARTUP
},
464 {"checkir", RADV_DEBUG_CHECKIR
},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
466 {"nobinning", RADV_DEBUG_NOBINNING
},
471 radv_get_debug_option_name(int id
)
473 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
474 return radv_debug_options
[id
].string
;
477 static const struct debug_control radv_perftest_options
[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
479 {"sisched", RADV_PERFTEST_SISCHED
},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
482 {"bolist", RADV_PERFTEST_BO_LIST
},
487 radv_get_perftest_option_name(int id
)
489 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
490 return radv_perftest_options
[id
].string
;
494 radv_handle_per_app_options(struct radv_instance
*instance
,
495 const VkApplicationInfo
*info
)
497 const char *name
= info
? info
->pApplicationName
: NULL
;
502 if (!strcmp(name
, "Talos - Linux - 32bit") ||
503 !strcmp(name
, "Talos - Linux - 64bit")) {
504 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
508 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
510 } else if (!strcmp(name
, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
516 static int radv_get_instance_extension_index(const char *name
)
518 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
519 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
525 static const char radv_dri_options_xml
[] =
527 DRI_CONF_SECTION_QUALITY
528 DRI_CONF_ADAPTIVE_SYNC("true")
532 static void radv_init_dri_options(struct radv_instance
*instance
)
534 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
535 driParseConfigFiles(&instance
->dri_options
,
536 &instance
->available_dri_options
,
540 VkResult
radv_CreateInstance(
541 const VkInstanceCreateInfo
* pCreateInfo
,
542 const VkAllocationCallbacks
* pAllocator
,
543 VkInstance
* pInstance
)
545 struct radv_instance
*instance
;
548 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
550 uint32_t client_version
;
551 if (pCreateInfo
->pApplicationInfo
&&
552 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
553 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
555 client_version
= VK_API_VERSION_1_0
;
558 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
559 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
561 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
563 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
566 instance
->alloc
= *pAllocator
;
568 instance
->alloc
= default_alloc
;
570 instance
->apiVersion
= client_version
;
571 instance
->physicalDeviceCount
= -1;
573 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
576 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
577 radv_perftest_options
);
580 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
581 radv_logi("Created an instance");
583 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
584 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
585 int index
= radv_get_instance_extension_index(ext_name
);
587 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
588 vk_free2(&default_alloc
, pAllocator
, instance
);
589 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
592 instance
->enabled_extensions
.extensions
[index
] = true;
595 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
596 if (result
!= VK_SUCCESS
) {
597 vk_free2(&default_alloc
, pAllocator
, instance
);
598 return vk_error(instance
, result
);
602 glsl_type_singleton_init_or_ref();
604 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
606 radv_init_dri_options(instance
);
607 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
609 *pInstance
= radv_instance_to_handle(instance
);
614 void radv_DestroyInstance(
615 VkInstance _instance
,
616 const VkAllocationCallbacks
* pAllocator
)
618 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
623 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
624 radv_physical_device_finish(instance
->physicalDevices
+ i
);
627 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
629 glsl_type_singleton_decref();
632 driDestroyOptionCache(&instance
->dri_options
);
633 driDestroyOptionInfo(&instance
->available_dri_options
);
635 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
637 vk_free(&instance
->alloc
, instance
);
641 radv_enumerate_devices(struct radv_instance
*instance
)
643 /* TODO: Check for more devices ? */
644 drmDevicePtr devices
[8];
645 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
648 instance
->physicalDeviceCount
= 0;
650 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
652 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
653 radv_logi("Found %d drm nodes", max_devices
);
656 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
658 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
659 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
660 devices
[i
]->bustype
== DRM_BUS_PCI
&&
661 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
663 result
= radv_physical_device_init(instance
->physicalDevices
+
664 instance
->physicalDeviceCount
,
667 if (result
== VK_SUCCESS
)
668 ++instance
->physicalDeviceCount
;
669 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
673 drmFreeDevices(devices
, max_devices
);
678 VkResult
radv_EnumeratePhysicalDevices(
679 VkInstance _instance
,
680 uint32_t* pPhysicalDeviceCount
,
681 VkPhysicalDevice
* pPhysicalDevices
)
683 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
686 if (instance
->physicalDeviceCount
< 0) {
687 result
= radv_enumerate_devices(instance
);
688 if (result
!= VK_SUCCESS
&&
689 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
693 if (!pPhysicalDevices
) {
694 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
696 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
697 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
698 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
701 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
705 VkResult
radv_EnumeratePhysicalDeviceGroups(
706 VkInstance _instance
,
707 uint32_t* pPhysicalDeviceGroupCount
,
708 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
710 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
713 if (instance
->physicalDeviceCount
< 0) {
714 result
= radv_enumerate_devices(instance
);
715 if (result
!= VK_SUCCESS
&&
716 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
720 if (!pPhysicalDeviceGroupProperties
) {
721 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
723 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
724 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
725 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
726 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
727 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
730 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
734 void radv_GetPhysicalDeviceFeatures(
735 VkPhysicalDevice physicalDevice
,
736 VkPhysicalDeviceFeatures
* pFeatures
)
738 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
739 memset(pFeatures
, 0, sizeof(*pFeatures
));
741 *pFeatures
= (VkPhysicalDeviceFeatures
) {
742 .robustBufferAccess
= true,
743 .fullDrawIndexUint32
= true,
744 .imageCubeArray
= true,
745 .independentBlend
= true,
746 .geometryShader
= true,
747 .tessellationShader
= true,
748 .sampleRateShading
= true,
749 .dualSrcBlend
= true,
751 .multiDrawIndirect
= true,
752 .drawIndirectFirstInstance
= true,
754 .depthBiasClamp
= true,
755 .fillModeNonSolid
= true,
760 .multiViewport
= true,
761 .samplerAnisotropy
= true,
762 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
763 .textureCompressionASTC_LDR
= false,
764 .textureCompressionBC
= true,
765 .occlusionQueryPrecise
= true,
766 .pipelineStatisticsQuery
= true,
767 .vertexPipelineStoresAndAtomics
= true,
768 .fragmentStoresAndAtomics
= true,
769 .shaderTessellationAndGeometryPointSize
= true,
770 .shaderImageGatherExtended
= true,
771 .shaderStorageImageExtendedFormats
= true,
772 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
773 .shaderUniformBufferArrayDynamicIndexing
= true,
774 .shaderSampledImageArrayDynamicIndexing
= true,
775 .shaderStorageBufferArrayDynamicIndexing
= true,
776 .shaderStorageImageArrayDynamicIndexing
= true,
777 .shaderStorageImageReadWithoutFormat
= true,
778 .shaderStorageImageWriteWithoutFormat
= true,
779 .shaderClipDistance
= true,
780 .shaderCullDistance
= true,
781 .shaderFloat64
= true,
783 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
784 .sparseBinding
= true,
785 .variableMultisampleRate
= true,
786 .inheritedQueries
= true,
790 void radv_GetPhysicalDeviceFeatures2(
791 VkPhysicalDevice physicalDevice
,
792 VkPhysicalDeviceFeatures2
*pFeatures
)
794 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
795 vk_foreach_struct(ext
, pFeatures
->pNext
) {
796 switch (ext
->sType
) {
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
798 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
799 features
->variablePointersStorageBuffer
= true;
800 features
->variablePointers
= true;
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
804 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
805 features
->multiview
= true;
806 features
->multiviewGeometryShader
= true;
807 features
->multiviewTessellationShader
= true;
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
811 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
812 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
813 features
->shaderDrawParameters
= true;
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
817 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
818 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
819 features
->protectedMemory
= false;
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
823 VkPhysicalDevice16BitStorageFeatures
*features
=
824 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
825 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
826 features
->storageBuffer16BitAccess
= enabled
;
827 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
828 features
->storagePushConstant16
= enabled
;
829 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
833 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
834 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
835 features
->samplerYcbcrConversion
= true;
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
839 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
840 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
841 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
842 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
843 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
844 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
845 features
->shaderSampledImageArrayNonUniformIndexing
= true;
846 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
847 features
->shaderStorageImageArrayNonUniformIndexing
= true;
848 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
849 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
850 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
851 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
852 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
853 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
854 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
855 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
856 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
857 features
->descriptorBindingUpdateUnusedWhilePending
= true;
858 features
->descriptorBindingPartiallyBound
= true;
859 features
->descriptorBindingVariableDescriptorCount
= true;
860 features
->runtimeDescriptorArray
= true;
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
864 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
865 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
866 features
->conditionalRendering
= true;
867 features
->inheritedConditionalRendering
= false;
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
871 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
872 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
873 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
874 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
878 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
879 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
880 features
->transformFeedback
= true;
881 features
->geometryStreams
= true;
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
885 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
886 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
887 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
891 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
892 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
893 features
->memoryPriority
= VK_TRUE
;
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
897 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
898 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
899 features
->bufferDeviceAddress
= true;
900 features
->bufferDeviceAddressCaptureReplay
= false;
901 features
->bufferDeviceAddressMultiDevice
= false;
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
905 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
906 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
907 features
->depthClipEnable
= true;
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
911 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
912 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
913 features
->hostQueryReset
= true;
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
917 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
918 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
919 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
920 features
->storageBuffer8BitAccess
= enabled
;
921 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
922 features
->storagePushConstant8
= enabled
;
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
926 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
927 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
928 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
929 features
->shaderInt8
= true;
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
933 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
934 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
935 /* TODO: Enable this once the driver supports 64-bit
936 * compare&swap atomic operations.
938 features
->shaderBufferInt64Atomics
= false;
939 features
->shaderSharedInt64Atomics
= false;
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
943 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
944 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
946 features
->inlineUniformBlock
= true;
947 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
951 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
952 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
953 features
->computeDerivativeGroupQuads
= false;
954 features
->computeDerivativeGroupLinear
= true;
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
958 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
959 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
960 features
->ycbcrImageArrays
= true;
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
964 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
965 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
966 features
->uniformBufferStandardLayout
= true;
973 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
976 void radv_GetPhysicalDeviceProperties(
977 VkPhysicalDevice physicalDevice
,
978 VkPhysicalDeviceProperties
* pProperties
)
980 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
981 VkSampleCountFlags sample_counts
= 0xf;
983 /* make sure that the entire descriptor set is addressable with a signed
984 * 32-bit int. So the sum of all limits scaled by descriptor size has to
985 * be at most 2 GiB. the combined image & samples object count as one of
986 * both. This limit is for the pipeline layout, not for the set layout, but
987 * there is no set limit, so we just set a pipeline limit. I don't think
988 * any app is going to hit this soon. */
989 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
990 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
991 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
992 32 /* sampler, largest when combined with image */ +
993 64 /* sampled image */ +
994 64 /* storage image */);
996 VkPhysicalDeviceLimits limits
= {
997 .maxImageDimension1D
= (1 << 14),
998 .maxImageDimension2D
= (1 << 14),
999 .maxImageDimension3D
= (1 << 11),
1000 .maxImageDimensionCube
= (1 << 14),
1001 .maxImageArrayLayers
= (1 << 11),
1002 .maxTexelBufferElements
= 128 * 1024 * 1024,
1003 .maxUniformBufferRange
= UINT32_MAX
,
1004 .maxStorageBufferRange
= UINT32_MAX
,
1005 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1006 .maxMemoryAllocationCount
= UINT32_MAX
,
1007 .maxSamplerAllocationCount
= 64 * 1024,
1008 .bufferImageGranularity
= 64, /* A cache line */
1009 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1010 .maxBoundDescriptorSets
= MAX_SETS
,
1011 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1012 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1013 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1014 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1015 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1016 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1017 .maxPerStageResources
= max_descriptor_set_size
,
1018 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1019 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1020 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1021 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1022 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1023 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1024 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1025 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1026 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1027 .maxVertexInputBindings
= MAX_VBS
,
1028 .maxVertexInputAttributeOffset
= 2047,
1029 .maxVertexInputBindingStride
= 2048,
1030 .maxVertexOutputComponents
= 128,
1031 .maxTessellationGenerationLevel
= 64,
1032 .maxTessellationPatchSize
= 32,
1033 .maxTessellationControlPerVertexInputComponents
= 128,
1034 .maxTessellationControlPerVertexOutputComponents
= 128,
1035 .maxTessellationControlPerPatchOutputComponents
= 120,
1036 .maxTessellationControlTotalOutputComponents
= 4096,
1037 .maxTessellationEvaluationInputComponents
= 128,
1038 .maxTessellationEvaluationOutputComponents
= 128,
1039 .maxGeometryShaderInvocations
= 127,
1040 .maxGeometryInputComponents
= 64,
1041 .maxGeometryOutputComponents
= 128,
1042 .maxGeometryOutputVertices
= 256,
1043 .maxGeometryTotalOutputComponents
= 1024,
1044 .maxFragmentInputComponents
= 128,
1045 .maxFragmentOutputAttachments
= 8,
1046 .maxFragmentDualSrcAttachments
= 1,
1047 .maxFragmentCombinedOutputResources
= 8,
1048 .maxComputeSharedMemorySize
= 32768,
1049 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1050 .maxComputeWorkGroupInvocations
= 2048,
1051 .maxComputeWorkGroupSize
= {
1056 .subPixelPrecisionBits
= 8,
1057 .subTexelPrecisionBits
= 8,
1058 .mipmapPrecisionBits
= 8,
1059 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1060 .maxDrawIndirectCount
= UINT32_MAX
,
1061 .maxSamplerLodBias
= 16,
1062 .maxSamplerAnisotropy
= 16,
1063 .maxViewports
= MAX_VIEWPORTS
,
1064 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1065 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1066 .viewportSubPixelBits
= 8,
1067 .minMemoryMapAlignment
= 4096, /* A page */
1068 .minTexelBufferOffsetAlignment
= 1,
1069 .minUniformBufferOffsetAlignment
= 4,
1070 .minStorageBufferOffsetAlignment
= 4,
1071 .minTexelOffset
= -32,
1072 .maxTexelOffset
= 31,
1073 .minTexelGatherOffset
= -32,
1074 .maxTexelGatherOffset
= 31,
1075 .minInterpolationOffset
= -2,
1076 .maxInterpolationOffset
= 2,
1077 .subPixelInterpolationOffsetBits
= 8,
1078 .maxFramebufferWidth
= (1 << 14),
1079 .maxFramebufferHeight
= (1 << 14),
1080 .maxFramebufferLayers
= (1 << 10),
1081 .framebufferColorSampleCounts
= sample_counts
,
1082 .framebufferDepthSampleCounts
= sample_counts
,
1083 .framebufferStencilSampleCounts
= sample_counts
,
1084 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1085 .maxColorAttachments
= MAX_RTS
,
1086 .sampledImageColorSampleCounts
= sample_counts
,
1087 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1088 .sampledImageDepthSampleCounts
= sample_counts
,
1089 .sampledImageStencilSampleCounts
= sample_counts
,
1090 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1091 .maxSampleMaskWords
= 1,
1092 .timestampComputeAndGraphics
= true,
1093 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1094 .maxClipDistances
= 8,
1095 .maxCullDistances
= 8,
1096 .maxCombinedClipAndCullDistances
= 8,
1097 .discreteQueuePriorities
= 2,
1098 .pointSizeRange
= { 0.0, 8192.0 },
1099 .lineWidthRange
= { 0.0, 7.9921875 },
1100 .pointSizeGranularity
= (1.0 / 8.0),
1101 .lineWidthGranularity
= (1.0 / 128.0),
1102 .strictLines
= false, /* FINISHME */
1103 .standardSampleLocations
= true,
1104 .optimalBufferCopyOffsetAlignment
= 128,
1105 .optimalBufferCopyRowPitchAlignment
= 128,
1106 .nonCoherentAtomSize
= 64,
1109 *pProperties
= (VkPhysicalDeviceProperties
) {
1110 .apiVersion
= radv_physical_device_api_version(pdevice
),
1111 .driverVersion
= vk_get_driver_version(),
1112 .vendorID
= ATI_VENDOR_ID
,
1113 .deviceID
= pdevice
->rad_info
.pci_id
,
1114 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1116 .sparseProperties
= {0},
1119 strcpy(pProperties
->deviceName
, pdevice
->name
);
1120 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1123 void radv_GetPhysicalDeviceProperties2(
1124 VkPhysicalDevice physicalDevice
,
1125 VkPhysicalDeviceProperties2
*pProperties
)
1127 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1128 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1130 vk_foreach_struct(ext
, pProperties
->pNext
) {
1131 switch (ext
->sType
) {
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1133 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1134 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1135 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1139 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1140 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1141 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1142 properties
->deviceLUIDValid
= false;
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1146 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1147 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1148 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1152 VkPhysicalDevicePointClippingProperties
*properties
=
1153 (VkPhysicalDevicePointClippingProperties
*)ext
;
1154 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1158 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1159 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1160 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1164 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1165 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1166 properties
->minImportedHostPointerAlignment
= 4096;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1170 VkPhysicalDeviceSubgroupProperties
*properties
=
1171 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1172 properties
->subgroupSize
= 64;
1173 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1174 properties
->supportedOperations
=
1175 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1176 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1177 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1178 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1179 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1180 properties
->supportedOperations
|=
1181 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1182 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1183 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1185 properties
->quadOperationsInAllStages
= true;
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1189 VkPhysicalDeviceMaintenance3Properties
*properties
=
1190 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1191 /* Make sure everything is addressable by a signed 32-bit int, and
1192 * our largest descriptors are 96 bytes. */
1193 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1194 /* Our buffer size fields allow only this much */
1195 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1199 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1200 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1201 /* GFX6-8 only support single channel min/max filter. */
1202 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1203 properties
->filterMinmaxSingleComponentFormats
= true;
1206 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1207 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1208 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1210 /* Shader engines. */
1211 properties
->shaderEngineCount
=
1212 pdevice
->rad_info
.max_se
;
1213 properties
->shaderArraysPerEngineCount
=
1214 pdevice
->rad_info
.max_sh_per_se
;
1215 properties
->computeUnitsPerShaderArray
=
1216 pdevice
->rad_info
.num_good_cu_per_sh
;
1217 properties
->simdPerComputeUnit
= 4;
1218 properties
->wavefrontsPerSimd
=
1219 pdevice
->rad_info
.family
== CHIP_TONGA
||
1220 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1221 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1222 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1223 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1224 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1225 properties
->wavefrontSize
= 64;
1228 properties
->sgprsPerSimd
=
1229 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1230 properties
->minSgprAllocation
=
1231 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1232 properties
->maxSgprAllocation
=
1233 pdevice
->rad_info
.family
== CHIP_TONGA
||
1234 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1235 properties
->sgprAllocationGranularity
=
1236 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1239 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1240 properties
->minVgprAllocation
= 4;
1241 properties
->maxVgprAllocation
= 256;
1242 properties
->vgprAllocationGranularity
= 4;
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1246 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1247 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1248 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1252 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1253 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1254 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1255 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1256 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1257 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1258 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1259 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1260 properties
->robustBufferAccessUpdateAfterBind
= false;
1261 properties
->quadDivergentImplicitLod
= false;
1263 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1264 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1265 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1266 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1267 32 /* sampler, largest when combined with image */ +
1268 64 /* sampled image */ +
1269 64 /* storage image */);
1270 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1271 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1272 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1273 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1274 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1275 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1276 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1277 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1278 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1279 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1280 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1281 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1282 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1283 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1284 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1288 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1289 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1290 properties
->protectedNoFault
= false;
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1294 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1295 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1296 properties
->primitiveOverestimationSize
= 0;
1297 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1298 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1299 properties
->primitiveUnderestimation
= VK_FALSE
;
1300 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1301 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1302 properties
->degenerateLinesRasterized
= VK_FALSE
;
1303 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1304 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1308 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1309 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1310 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1311 properties
->pciBus
= pdevice
->bus_info
.bus
;
1312 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1313 properties
->pciFunction
= pdevice
->bus_info
.func
;
1316 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1317 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1318 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1320 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1321 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1322 strcpy(driver_props
->driverName
, "radv");
1324 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1325 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1326 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1327 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1329 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1338 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1339 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1340 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1341 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1342 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1343 properties
->maxTransformFeedbackStreamDataSize
= 512;
1344 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1345 properties
->maxTransformFeedbackBufferDataStride
= 512;
1346 properties
->transformFeedbackQueries
= true;
1347 properties
->transformFeedbackStreamsLinesTriangles
= false;
1348 properties
->transformFeedbackRasterizationStreamSelect
= false;
1349 properties
->transformFeedbackDraw
= true;
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1353 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1354 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1356 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1357 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1358 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1359 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1360 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1369 static void radv_get_physical_device_queue_family_properties(
1370 struct radv_physical_device
* pdevice
,
1372 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1374 int num_queue_families
= 1;
1376 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1377 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1378 num_queue_families
++;
1380 if (pQueueFamilyProperties
== NULL
) {
1381 *pCount
= num_queue_families
;
1390 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1391 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1392 VK_QUEUE_COMPUTE_BIT
|
1393 VK_QUEUE_TRANSFER_BIT
|
1394 VK_QUEUE_SPARSE_BINDING_BIT
,
1396 .timestampValidBits
= 64,
1397 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1402 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1403 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1404 if (*pCount
> idx
) {
1405 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1406 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1407 VK_QUEUE_TRANSFER_BIT
|
1408 VK_QUEUE_SPARSE_BINDING_BIT
,
1409 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1410 .timestampValidBits
= 64,
1411 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1419 void radv_GetPhysicalDeviceQueueFamilyProperties(
1420 VkPhysicalDevice physicalDevice
,
1422 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1424 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1425 if (!pQueueFamilyProperties
) {
1426 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1429 VkQueueFamilyProperties
*properties
[] = {
1430 pQueueFamilyProperties
+ 0,
1431 pQueueFamilyProperties
+ 1,
1432 pQueueFamilyProperties
+ 2,
1434 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1435 assert(*pCount
<= 3);
1438 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1439 VkPhysicalDevice physicalDevice
,
1441 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1443 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1444 if (!pQueueFamilyProperties
) {
1445 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1448 VkQueueFamilyProperties
*properties
[] = {
1449 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1450 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1451 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1453 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1454 assert(*pCount
<= 3);
1457 void radv_GetPhysicalDeviceMemoryProperties(
1458 VkPhysicalDevice physicalDevice
,
1459 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1461 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1463 *pMemoryProperties
= physical_device
->memory_properties
;
1467 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1468 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1470 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1471 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1472 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1473 uint64_t vram_size
= radv_get_vram_size(device
);
1474 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1475 uint64_t heap_budget
, heap_usage
;
1477 /* For all memory heaps, the computation of budget is as follow:
1478 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1480 * The Vulkan spec 1.1.97 says that the budget should include any
1481 * currently allocated device memory.
1483 * Note that the application heap usages are not really accurate (eg.
1484 * in presence of shared buffers).
1487 heap_usage
= device
->ws
->query_value(device
->ws
,
1488 RADEON_ALLOCATED_VRAM
);
1490 heap_budget
= vram_size
-
1491 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1494 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM
] = heap_budget
;
1495 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM
] = heap_usage
;
1498 if (visible_vram_size
) {
1499 heap_usage
= device
->ws
->query_value(device
->ws
,
1500 RADEON_ALLOCATED_VRAM_VIS
);
1502 heap_budget
= visible_vram_size
-
1503 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1506 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_budget
;
1507 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_usage
;
1511 heap_usage
= device
->ws
->query_value(device
->ws
,
1512 RADEON_ALLOCATED_GTT
);
1514 heap_budget
= gtt_size
-
1515 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1518 memoryBudget
->heapBudget
[RADV_MEM_HEAP_GTT
] = heap_budget
;
1519 memoryBudget
->heapUsage
[RADV_MEM_HEAP_GTT
] = heap_usage
;
1522 /* The heapBudget and heapUsage values must be zero for array elements
1523 * greater than or equal to
1524 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1526 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1527 memoryBudget
->heapBudget
[i
] = 0;
1528 memoryBudget
->heapUsage
[i
] = 0;
1532 void radv_GetPhysicalDeviceMemoryProperties2(
1533 VkPhysicalDevice physicalDevice
,
1534 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1536 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1537 &pMemoryProperties
->memoryProperties
);
1539 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1540 vk_find_struct(pMemoryProperties
->pNext
,
1541 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1543 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1546 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1548 VkExternalMemoryHandleTypeFlagBits handleType
,
1549 const void *pHostPointer
,
1550 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1552 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1556 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1557 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1558 uint32_t memoryTypeBits
= 0;
1559 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1560 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1561 memoryTypeBits
= (1 << i
);
1565 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1569 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1573 static enum radeon_ctx_priority
1574 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1576 /* Default to MEDIUM when a specific global priority isn't requested */
1578 return RADEON_CTX_PRIORITY_MEDIUM
;
1580 switch(pObj
->globalPriority
) {
1581 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1582 return RADEON_CTX_PRIORITY_REALTIME
;
1583 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1584 return RADEON_CTX_PRIORITY_HIGH
;
1585 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1586 return RADEON_CTX_PRIORITY_MEDIUM
;
1587 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1588 return RADEON_CTX_PRIORITY_LOW
;
1590 unreachable("Illegal global priority value");
1591 return RADEON_CTX_PRIORITY_INVALID
;
1596 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1597 uint32_t queue_family_index
, int idx
,
1598 VkDeviceQueueCreateFlags flags
,
1599 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1601 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1602 queue
->device
= device
;
1603 queue
->queue_family_index
= queue_family_index
;
1604 queue
->queue_idx
= idx
;
1605 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1606 queue
->flags
= flags
;
1608 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1610 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1616 radv_queue_finish(struct radv_queue
*queue
)
1619 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1621 if (queue
->initial_full_flush_preamble_cs
)
1622 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1623 if (queue
->initial_preamble_cs
)
1624 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1625 if (queue
->continue_preamble_cs
)
1626 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1627 if (queue
->descriptor_bo
)
1628 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1629 if (queue
->scratch_bo
)
1630 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1631 if (queue
->esgs_ring_bo
)
1632 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1633 if (queue
->gsvs_ring_bo
)
1634 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1635 if (queue
->tess_rings_bo
)
1636 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1637 if (queue
->compute_scratch_bo
)
1638 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1642 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1644 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1645 bo_list
->list
.count
= bo_list
->capacity
= 0;
1646 bo_list
->list
.bos
= NULL
;
1650 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1652 free(bo_list
->list
.bos
);
1653 pthread_mutex_destroy(&bo_list
->mutex
);
1656 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1657 struct radeon_winsys_bo
*bo
)
1659 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1664 if (unlikely(!device
->use_global_bo_list
))
1667 pthread_mutex_lock(&bo_list
->mutex
);
1668 if (bo_list
->list
.count
== bo_list
->capacity
) {
1669 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1670 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1673 pthread_mutex_unlock(&bo_list
->mutex
);
1674 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1677 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1678 bo_list
->capacity
= capacity
;
1681 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1682 pthread_mutex_unlock(&bo_list
->mutex
);
1686 static void radv_bo_list_remove(struct radv_device
*device
,
1687 struct radeon_winsys_bo
*bo
)
1689 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1694 if (unlikely(!device
->use_global_bo_list
))
1697 pthread_mutex_lock(&bo_list
->mutex
);
1698 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1699 if (bo_list
->list
.bos
[i
] == bo
) {
1700 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1701 --bo_list
->list
.count
;
1705 pthread_mutex_unlock(&bo_list
->mutex
);
1709 radv_device_init_gs_info(struct radv_device
*device
)
1711 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1712 device
->physical_device
->rad_info
.family
);
1715 static int radv_get_device_extension_index(const char *name
)
1717 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1718 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1725 radv_get_int_debug_option(const char *name
, int default_value
)
1732 result
= default_value
;
1736 result
= strtol(str
, &endptr
, 0);
1737 if (str
== endptr
) {
1738 /* No digits founs. */
1739 result
= default_value
;
1746 VkResult
radv_CreateDevice(
1747 VkPhysicalDevice physicalDevice
,
1748 const VkDeviceCreateInfo
* pCreateInfo
,
1749 const VkAllocationCallbacks
* pAllocator
,
1752 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1754 struct radv_device
*device
;
1756 bool keep_shader_info
= false;
1758 /* Check enabled features */
1759 if (pCreateInfo
->pEnabledFeatures
) {
1760 VkPhysicalDeviceFeatures supported_features
;
1761 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1762 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1763 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1764 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1765 for (uint32_t i
= 0; i
< num_features
; i
++) {
1766 if (enabled_feature
[i
] && !supported_feature
[i
])
1767 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1771 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1773 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1775 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1777 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1778 device
->instance
= physical_device
->instance
;
1779 device
->physical_device
= physical_device
;
1781 device
->ws
= physical_device
->ws
;
1783 device
->alloc
= *pAllocator
;
1785 device
->alloc
= physical_device
->instance
->alloc
;
1787 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1788 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1789 int index
= radv_get_device_extension_index(ext_name
);
1790 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1791 vk_free(&device
->alloc
, device
);
1792 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1795 device
->enabled_extensions
.extensions
[index
] = true;
1798 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1800 /* With update after bind we can't attach bo's to the command buffer
1801 * from the descriptor set anymore, so we have to use a global BO list.
1803 device
->use_global_bo_list
=
1804 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1805 device
->enabled_extensions
.EXT_descriptor_indexing
||
1806 device
->enabled_extensions
.EXT_buffer_device_address
;
1808 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1809 list_inithead(&device
->shader_slabs
);
1811 radv_bo_list_init(&device
->bo_list
);
1813 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1814 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1815 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1816 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1817 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1819 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1821 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1822 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1823 if (!device
->queues
[qfi
]) {
1824 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1828 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1830 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1832 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1833 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1834 qfi
, q
, queue_create
->flags
,
1836 if (result
!= VK_SUCCESS
)
1841 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1842 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1844 /* Disabled and not implemented for now. */
1845 device
->dfsm_allowed
= device
->pbb_allowed
&&
1846 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1847 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1850 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1853 /* The maximum number of scratch waves. Scratch space isn't divided
1854 * evenly between CUs. The number is only a function of the number of CUs.
1855 * We can decrease the constant to decrease the scratch buffer size.
1857 * sctx->scratch_waves must be >= the maximum possible size of
1858 * 1 threadgroup, so that the hw doesn't hang from being unable
1861 * The recommended value is 4 per CU at most. Higher numbers don't
1862 * bring much benefit, but they still occupy chip resources (think
1863 * async compute). I've seen ~2% performance difference between 4 and 32.
1865 uint32_t max_threads_per_block
= 2048;
1866 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1867 max_threads_per_block
/ 64);
1869 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1871 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1872 /* If the KMD allows it (there is a KMD hw register for it),
1873 * allow launching waves out-of-order.
1875 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1878 radv_device_init_gs_info(device
);
1880 device
->tess_offchip_block_dw_size
=
1881 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1882 device
->has_distributed_tess
=
1883 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1884 device
->physical_device
->rad_info
.max_se
>= 2;
1886 if (getenv("RADV_TRACE_FILE")) {
1887 const char *filename
= getenv("RADV_TRACE_FILE");
1889 keep_shader_info
= true;
1891 if (!radv_init_trace(device
))
1894 fprintf(stderr
, "*****************************************************************************\n");
1895 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1896 fprintf(stderr
, "*****************************************************************************\n");
1898 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1899 radv_dump_enabled_options(device
, stderr
);
1902 device
->keep_shader_info
= keep_shader_info
;
1904 result
= radv_device_init_meta(device
);
1905 if (result
!= VK_SUCCESS
)
1908 radv_device_init_msaa(device
);
1910 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1911 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1913 case RADV_QUEUE_GENERAL
:
1914 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1915 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1916 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1918 case RADV_QUEUE_COMPUTE
:
1919 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1920 radeon_emit(device
->empty_cs
[family
], 0);
1923 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1926 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
1927 cik_create_gfx_config(device
);
1929 VkPipelineCacheCreateInfo ci
;
1930 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1933 ci
.pInitialData
= NULL
;
1934 ci
.initialDataSize
= 0;
1936 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1938 if (result
!= VK_SUCCESS
)
1941 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1943 device
->force_aniso
=
1944 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1945 if (device
->force_aniso
>= 0) {
1946 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1947 1 << util_logbase2(device
->force_aniso
));
1950 *pDevice
= radv_device_to_handle(device
);
1954 radv_device_finish_meta(device
);
1956 radv_bo_list_finish(&device
->bo_list
);
1958 if (device
->trace_bo
)
1959 device
->ws
->buffer_destroy(device
->trace_bo
);
1961 if (device
->gfx_init
)
1962 device
->ws
->buffer_destroy(device
->gfx_init
);
1964 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1965 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1966 radv_queue_finish(&device
->queues
[i
][q
]);
1967 if (device
->queue_count
[i
])
1968 vk_free(&device
->alloc
, device
->queues
[i
]);
1971 vk_free(&device
->alloc
, device
);
1975 void radv_DestroyDevice(
1977 const VkAllocationCallbacks
* pAllocator
)
1979 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1984 if (device
->trace_bo
)
1985 device
->ws
->buffer_destroy(device
->trace_bo
);
1987 if (device
->gfx_init
)
1988 device
->ws
->buffer_destroy(device
->gfx_init
);
1990 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1991 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1992 radv_queue_finish(&device
->queues
[i
][q
]);
1993 if (device
->queue_count
[i
])
1994 vk_free(&device
->alloc
, device
->queues
[i
]);
1995 if (device
->empty_cs
[i
])
1996 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1998 radv_device_finish_meta(device
);
2000 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2001 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2003 radv_destroy_shader_slabs(device
);
2005 radv_bo_list_finish(&device
->bo_list
);
2006 vk_free(&device
->alloc
, device
);
2009 VkResult
radv_EnumerateInstanceLayerProperties(
2010 uint32_t* pPropertyCount
,
2011 VkLayerProperties
* pProperties
)
2013 if (pProperties
== NULL
) {
2014 *pPropertyCount
= 0;
2018 /* None supported at this time */
2019 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2022 VkResult
radv_EnumerateDeviceLayerProperties(
2023 VkPhysicalDevice physicalDevice
,
2024 uint32_t* pPropertyCount
,
2025 VkLayerProperties
* pProperties
)
2027 if (pProperties
== NULL
) {
2028 *pPropertyCount
= 0;
2032 /* None supported at this time */
2033 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2036 void radv_GetDeviceQueue2(
2038 const VkDeviceQueueInfo2
* pQueueInfo
,
2041 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2042 struct radv_queue
*queue
;
2044 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2045 if (pQueueInfo
->flags
!= queue
->flags
) {
2046 /* From the Vulkan 1.1.70 spec:
2048 * "The queue returned by vkGetDeviceQueue2 must have the same
2049 * flags value from this structure as that used at device
2050 * creation time in a VkDeviceQueueCreateInfo instance. If no
2051 * matching flags were specified at device creation time then
2052 * pQueue will return VK_NULL_HANDLE."
2054 *pQueue
= VK_NULL_HANDLE
;
2058 *pQueue
= radv_queue_to_handle(queue
);
2061 void radv_GetDeviceQueue(
2063 uint32_t queueFamilyIndex
,
2064 uint32_t queueIndex
,
2067 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2068 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2069 .queueFamilyIndex
= queueFamilyIndex
,
2070 .queueIndex
= queueIndex
2073 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2077 fill_geom_tess_rings(struct radv_queue
*queue
,
2079 bool add_sample_positions
,
2080 uint32_t esgs_ring_size
,
2081 struct radeon_winsys_bo
*esgs_ring_bo
,
2082 uint32_t gsvs_ring_size
,
2083 struct radeon_winsys_bo
*gsvs_ring_bo
,
2084 uint32_t tess_factor_ring_size
,
2085 uint32_t tess_offchip_ring_offset
,
2086 uint32_t tess_offchip_ring_size
,
2087 struct radeon_winsys_bo
*tess_rings_bo
)
2089 uint32_t *desc
= &map
[4];
2092 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2094 /* stride 0, num records - size, add tid, swizzle, elsize4,
2097 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2098 S_008F04_STRIDE(0) |
2099 S_008F04_SWIZZLE_ENABLE(true);
2100 desc
[2] = esgs_ring_size
;
2101 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2102 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2103 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2104 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2105 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2107 S_008F0C_ELEMENT_SIZE(1) |
2108 S_008F0C_INDEX_STRIDE(3) |
2109 S_008F0C_ADD_TID_ENABLE(true);
2111 /* GS entry for ES->GS ring */
2112 /* stride 0, num records - size, elsize0,
2115 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2116 S_008F04_STRIDE(0) |
2117 S_008F04_SWIZZLE_ENABLE(false);
2118 desc
[6] = esgs_ring_size
;
2119 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2120 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2121 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2122 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2123 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2124 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2125 S_008F0C_ELEMENT_SIZE(0) |
2126 S_008F0C_INDEX_STRIDE(0) |
2127 S_008F0C_ADD_TID_ENABLE(false);
2133 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2135 /* VS entry for GS->VS ring */
2136 /* stride 0, num records - size, elsize0,
2139 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2140 S_008F04_STRIDE(0) |
2141 S_008F04_SWIZZLE_ENABLE(false);
2142 desc
[2] = gsvs_ring_size
;
2143 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2144 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2145 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2146 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2147 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2148 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2149 S_008F0C_ELEMENT_SIZE(0) |
2150 S_008F0C_INDEX_STRIDE(0) |
2151 S_008F0C_ADD_TID_ENABLE(false);
2153 /* stride gsvs_itemsize, num records 64
2154 elsize 4, index stride 16 */
2155 /* shader will patch stride and desc[2] */
2157 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2158 S_008F04_STRIDE(0) |
2159 S_008F04_SWIZZLE_ENABLE(true);
2161 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2165 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2167 S_008F0C_ELEMENT_SIZE(1) |
2168 S_008F0C_INDEX_STRIDE(1) |
2169 S_008F0C_ADD_TID_ENABLE(true);
2174 if (tess_rings_bo
) {
2175 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2176 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2179 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2180 S_008F04_STRIDE(0) |
2181 S_008F04_SWIZZLE_ENABLE(false);
2182 desc
[2] = tess_factor_ring_size
;
2183 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2187 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2188 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2189 S_008F0C_ELEMENT_SIZE(0) |
2190 S_008F0C_INDEX_STRIDE(0) |
2191 S_008F0C_ADD_TID_ENABLE(false);
2193 desc
[4] = tess_offchip_va
;
2194 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2195 S_008F04_STRIDE(0) |
2196 S_008F04_SWIZZLE_ENABLE(false);
2197 desc
[6] = tess_offchip_ring_size
;
2198 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2199 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2200 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2201 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2202 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2203 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2204 S_008F0C_ELEMENT_SIZE(0) |
2205 S_008F0C_INDEX_STRIDE(0) |
2206 S_008F0C_ADD_TID_ENABLE(false);
2211 if (add_sample_positions
) {
2212 /* add sample positions after all rings */
2213 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2215 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2217 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2219 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2224 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2226 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2227 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2228 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2229 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2230 unsigned max_offchip_buffers
;
2231 unsigned offchip_granularity
;
2232 unsigned hs_offchip_param
;
2236 * This must be one less than the maximum number due to a hw limitation.
2237 * Various hardware bugs need thGFX7
2240 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2241 * Gfx7 should limit max_offchip_buffers to 508
2242 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2244 * Follow AMDVLK here.
2246 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2247 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2248 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2249 --max_offchip_buffers_per_se
;
2251 max_offchip_buffers
= max_offchip_buffers_per_se
*
2252 device
->physical_device
->rad_info
.max_se
;
2254 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2255 * around by setting 4K granularity.
2257 if (device
->tess_offchip_block_dw_size
== 4096) {
2258 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2259 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2261 assert(device
->tess_offchip_block_dw_size
== 8192);
2262 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2265 switch (device
->physical_device
->rad_info
.chip_class
) {
2267 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2273 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2277 *max_offchip_buffers_p
= max_offchip_buffers
;
2278 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2279 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2280 --max_offchip_buffers
;
2282 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2283 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2286 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2288 return hs_offchip_param
;
2292 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2293 struct radeon_winsys_bo
*esgs_ring_bo
,
2294 uint32_t esgs_ring_size
,
2295 struct radeon_winsys_bo
*gsvs_ring_bo
,
2296 uint32_t gsvs_ring_size
)
2298 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2302 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2305 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2307 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2308 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2309 radeon_emit(cs
, esgs_ring_size
>> 8);
2310 radeon_emit(cs
, gsvs_ring_size
>> 8);
2312 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2313 radeon_emit(cs
, esgs_ring_size
>> 8);
2314 radeon_emit(cs
, gsvs_ring_size
>> 8);
2319 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2320 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2321 struct radeon_winsys_bo
*tess_rings_bo
)
2328 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2330 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2332 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2333 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2334 S_030938_SIZE(tf_ring_size
/ 4));
2335 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2337 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2338 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2339 S_030944_BASE_HI(tf_va
>> 40));
2341 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2344 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2345 S_008988_SIZE(tf_ring_size
/ 4));
2346 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2348 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2354 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2355 struct radeon_winsys_bo
*compute_scratch_bo
)
2357 uint64_t scratch_va
;
2359 if (!compute_scratch_bo
)
2362 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2364 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2366 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2367 radeon_emit(cs
, scratch_va
);
2368 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2369 S_008F04_SWIZZLE_ENABLE(1));
2373 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2374 struct radeon_cmdbuf
*cs
,
2375 struct radeon_winsys_bo
*descriptor_bo
)
2382 va
= radv_buffer_get_va(descriptor_bo
);
2384 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2386 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2387 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2388 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2389 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2390 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2392 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2393 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2397 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2398 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2399 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2400 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2401 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2402 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2404 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2405 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2412 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2414 struct radv_device
*device
= queue
->device
;
2416 if (device
->gfx_init
) {
2417 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2419 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2420 radeon_emit(cs
, va
);
2421 radeon_emit(cs
, va
>> 32);
2422 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2424 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2426 struct radv_physical_device
*physical_device
= device
->physical_device
;
2427 si_emit_graphics(physical_device
, cs
);
2432 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2434 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2435 si_emit_compute(physical_device
, cs
);
2439 radv_get_preamble_cs(struct radv_queue
*queue
,
2440 uint32_t scratch_size
,
2441 uint32_t compute_scratch_size
,
2442 uint32_t esgs_ring_size
,
2443 uint32_t gsvs_ring_size
,
2444 bool needs_tess_rings
,
2445 bool needs_sample_positions
,
2446 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2447 struct radeon_cmdbuf
**initial_preamble_cs
,
2448 struct radeon_cmdbuf
**continue_preamble_cs
)
2450 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2451 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2452 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2453 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2454 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2455 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2456 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2457 bool add_tess_rings
= false, add_sample_positions
= false;
2458 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2459 unsigned max_offchip_buffers
;
2460 unsigned hs_offchip_param
= 0;
2461 unsigned tess_offchip_ring_offset
;
2462 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2463 if (!queue
->has_tess_rings
) {
2464 if (needs_tess_rings
)
2465 add_tess_rings
= true;
2467 if (!queue
->has_sample_positions
) {
2468 if (needs_sample_positions
)
2469 add_sample_positions
= true;
2471 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2472 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2473 &max_offchip_buffers
);
2474 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2475 tess_offchip_ring_size
= max_offchip_buffers
*
2476 queue
->device
->tess_offchip_block_dw_size
* 4;
2478 if (scratch_size
<= queue
->scratch_size
&&
2479 compute_scratch_size
<= queue
->compute_scratch_size
&&
2480 esgs_ring_size
<= queue
->esgs_ring_size
&&
2481 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2482 !add_tess_rings
&& !add_sample_positions
&&
2483 queue
->initial_preamble_cs
) {
2484 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2485 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2486 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2487 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2488 *continue_preamble_cs
= NULL
;
2492 if (scratch_size
> queue
->scratch_size
) {
2493 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2498 RADV_BO_PRIORITY_SCRATCH
);
2502 scratch_bo
= queue
->scratch_bo
;
2504 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2505 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2506 compute_scratch_size
,
2510 RADV_BO_PRIORITY_SCRATCH
);
2511 if (!compute_scratch_bo
)
2515 compute_scratch_bo
= queue
->compute_scratch_bo
;
2517 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2518 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2523 RADV_BO_PRIORITY_SCRATCH
);
2527 esgs_ring_bo
= queue
->esgs_ring_bo
;
2528 esgs_ring_size
= queue
->esgs_ring_size
;
2531 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2532 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2537 RADV_BO_PRIORITY_SCRATCH
);
2541 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2542 gsvs_ring_size
= queue
->gsvs_ring_size
;
2545 if (add_tess_rings
) {
2546 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2547 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2551 RADV_BO_PRIORITY_SCRATCH
);
2555 tess_rings_bo
= queue
->tess_rings_bo
;
2558 if (scratch_bo
!= queue
->scratch_bo
||
2559 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2560 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2561 tess_rings_bo
!= queue
->tess_rings_bo
||
2562 add_sample_positions
) {
2564 if (gsvs_ring_bo
|| esgs_ring_bo
||
2565 tess_rings_bo
|| add_sample_positions
) {
2566 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2567 if (add_sample_positions
)
2568 size
+= 128; /* 64+32+16+8 = 120 bytes */
2570 else if (scratch_bo
)
2571 size
= 8; /* 2 dword */
2573 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2577 RADEON_FLAG_CPU_ACCESS
|
2578 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2579 RADEON_FLAG_READ_ONLY
,
2580 RADV_BO_PRIORITY_DESCRIPTOR
);
2584 descriptor_bo
= queue
->descriptor_bo
;
2586 if (descriptor_bo
!= queue
->descriptor_bo
) {
2587 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2590 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2591 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2592 S_008F04_SWIZZLE_ENABLE(1);
2593 map
[0] = scratch_va
;
2597 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2598 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2599 esgs_ring_size
, esgs_ring_bo
,
2600 gsvs_ring_size
, gsvs_ring_bo
,
2601 tess_factor_ring_size
,
2602 tess_offchip_ring_offset
,
2603 tess_offchip_ring_size
,
2606 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2609 for(int i
= 0; i
< 3; ++i
) {
2610 struct radeon_cmdbuf
*cs
= NULL
;
2611 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2612 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2619 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2621 /* Emit initial configuration. */
2622 switch (queue
->queue_family_index
) {
2623 case RADV_QUEUE_GENERAL
:
2624 radv_init_graphics_state(cs
, queue
);
2626 case RADV_QUEUE_COMPUTE
:
2627 radv_init_compute_state(cs
, queue
);
2629 case RADV_QUEUE_TRANSFER
:
2633 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2634 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2635 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2636 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2637 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2640 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2641 gsvs_ring_bo
, gsvs_ring_size
);
2642 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2643 tess_factor_ring_size
, tess_rings_bo
);
2644 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2645 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2648 si_cs_emit_cache_flush(cs
,
2649 queue
->device
->physical_device
->rad_info
.chip_class
,
2651 queue
->queue_family_index
== RING_COMPUTE
&&
2652 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2653 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2654 RADV_CMD_FLAG_INV_ICACHE
|
2655 RADV_CMD_FLAG_INV_SMEM_L1
|
2656 RADV_CMD_FLAG_INV_VMEM_L1
|
2657 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2658 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2659 } else if (i
== 1) {
2660 si_cs_emit_cache_flush(cs
,
2661 queue
->device
->physical_device
->rad_info
.chip_class
,
2663 queue
->queue_family_index
== RING_COMPUTE
&&
2664 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2665 RADV_CMD_FLAG_INV_ICACHE
|
2666 RADV_CMD_FLAG_INV_SMEM_L1
|
2667 RADV_CMD_FLAG_INV_VMEM_L1
|
2668 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2669 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2672 if (!queue
->device
->ws
->cs_finalize(cs
))
2676 if (queue
->initial_full_flush_preamble_cs
)
2677 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2679 if (queue
->initial_preamble_cs
)
2680 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2682 if (queue
->continue_preamble_cs
)
2683 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2685 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2686 queue
->initial_preamble_cs
= dest_cs
[1];
2687 queue
->continue_preamble_cs
= dest_cs
[2];
2689 if (scratch_bo
!= queue
->scratch_bo
) {
2690 if (queue
->scratch_bo
)
2691 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2692 queue
->scratch_bo
= scratch_bo
;
2693 queue
->scratch_size
= scratch_size
;
2696 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2697 if (queue
->compute_scratch_bo
)
2698 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2699 queue
->compute_scratch_bo
= compute_scratch_bo
;
2700 queue
->compute_scratch_size
= compute_scratch_size
;
2703 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2704 if (queue
->esgs_ring_bo
)
2705 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2706 queue
->esgs_ring_bo
= esgs_ring_bo
;
2707 queue
->esgs_ring_size
= esgs_ring_size
;
2710 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2711 if (queue
->gsvs_ring_bo
)
2712 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2713 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2714 queue
->gsvs_ring_size
= gsvs_ring_size
;
2717 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2718 queue
->tess_rings_bo
= tess_rings_bo
;
2719 queue
->has_tess_rings
= true;
2722 if (descriptor_bo
!= queue
->descriptor_bo
) {
2723 if (queue
->descriptor_bo
)
2724 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2726 queue
->descriptor_bo
= descriptor_bo
;
2729 if (add_sample_positions
)
2730 queue
->has_sample_positions
= true;
2732 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2733 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2734 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2735 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2736 *continue_preamble_cs
= NULL
;
2739 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2741 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2742 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2743 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2744 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2745 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2746 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2747 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2748 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2749 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2750 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2751 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2752 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2753 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2754 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2757 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2758 struct radv_winsys_sem_counts
*counts
,
2760 const VkSemaphore
*sems
,
2764 int syncobj_idx
= 0, sem_idx
= 0;
2766 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2769 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2770 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2772 if (sem
->temp_syncobj
|| sem
->syncobj
)
2773 counts
->syncobj_count
++;
2775 counts
->sem_count
++;
2778 if (_fence
!= VK_NULL_HANDLE
) {
2779 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2780 if (fence
->temp_syncobj
|| fence
->syncobj
)
2781 counts
->syncobj_count
++;
2784 if (counts
->syncobj_count
) {
2785 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2786 if (!counts
->syncobj
)
2787 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2790 if (counts
->sem_count
) {
2791 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2793 free(counts
->syncobj
);
2794 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2798 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2799 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2801 if (sem
->temp_syncobj
) {
2802 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2804 else if (sem
->syncobj
)
2805 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2808 counts
->sem
[sem_idx
++] = sem
->sem
;
2812 if (_fence
!= VK_NULL_HANDLE
) {
2813 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2814 if (fence
->temp_syncobj
)
2815 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2816 else if (fence
->syncobj
)
2817 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2824 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2826 free(sem_info
->wait
.syncobj
);
2827 free(sem_info
->wait
.sem
);
2828 free(sem_info
->signal
.syncobj
);
2829 free(sem_info
->signal
.sem
);
2833 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2835 const VkSemaphore
*sems
)
2837 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2838 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2840 if (sem
->temp_syncobj
) {
2841 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2842 sem
->temp_syncobj
= 0;
2848 radv_alloc_sem_info(struct radv_instance
*instance
,
2849 struct radv_winsys_sem_info
*sem_info
,
2851 const VkSemaphore
*wait_sems
,
2852 int num_signal_sems
,
2853 const VkSemaphore
*signal_sems
,
2857 memset(sem_info
, 0, sizeof(*sem_info
));
2859 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2862 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2864 radv_free_sem_info(sem_info
);
2866 /* caller can override these */
2867 sem_info
->cs_emit_wait
= true;
2868 sem_info
->cs_emit_signal
= true;
2872 /* Signals fence as soon as all the work currently put on queue is done. */
2873 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2874 struct radv_fence
*fence
)
2878 struct radv_winsys_sem_info sem_info
;
2880 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2881 radv_fence_to_handle(fence
));
2882 if (result
!= VK_SUCCESS
)
2885 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2886 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2887 1, NULL
, NULL
, &sem_info
, NULL
,
2888 false, fence
->fence
);
2889 radv_free_sem_info(&sem_info
);
2892 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2897 VkResult
radv_QueueSubmit(
2899 uint32_t submitCount
,
2900 const VkSubmitInfo
* pSubmits
,
2903 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2904 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2905 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2906 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2908 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
2909 uint32_t scratch_size
= 0;
2910 uint32_t compute_scratch_size
= 0;
2911 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2912 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2914 bool fence_emitted
= false;
2915 bool tess_rings_needed
= false;
2916 bool sample_positions_needed
= false;
2918 /* Do this first so failing to allocate scratch buffers can't result in
2919 * partially executed submissions. */
2920 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2921 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2922 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2923 pSubmits
[i
].pCommandBuffers
[j
]);
2925 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2926 compute_scratch_size
= MAX2(compute_scratch_size
,
2927 cmd_buffer
->compute_scratch_size_needed
);
2928 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2929 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2930 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2931 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2935 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2936 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2937 sample_positions_needed
, &initial_flush_preamble_cs
,
2938 &initial_preamble_cs
, &continue_preamble_cs
);
2939 if (result
!= VK_SUCCESS
)
2942 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2943 struct radeon_cmdbuf
**cs_array
;
2944 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2945 bool can_patch
= true;
2947 struct radv_winsys_sem_info sem_info
;
2949 result
= radv_alloc_sem_info(queue
->device
->instance
,
2951 pSubmits
[i
].waitSemaphoreCount
,
2952 pSubmits
[i
].pWaitSemaphores
,
2953 pSubmits
[i
].signalSemaphoreCount
,
2954 pSubmits
[i
].pSignalSemaphores
,
2956 if (result
!= VK_SUCCESS
)
2959 if (!pSubmits
[i
].commandBufferCount
) {
2960 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2961 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2962 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2967 radv_loge("failed to submit CS %d\n", i
);
2970 fence_emitted
= true;
2972 radv_free_sem_info(&sem_info
);
2976 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
2977 (pSubmits
[i
].commandBufferCount
));
2979 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2980 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2981 pSubmits
[i
].pCommandBuffers
[j
]);
2982 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2984 cs_array
[j
] = cmd_buffer
->cs
;
2985 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
2988 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
2991 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
2992 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
2993 const struct radv_winsys_bo_list
*bo_list
= NULL
;
2995 advance
= MIN2(max_cs_submission
,
2996 pSubmits
[i
].commandBufferCount
- j
);
2998 if (queue
->device
->trace_bo
)
2999 *queue
->device
->trace_id_ptr
= 0;
3001 sem_info
.cs_emit_wait
= j
== 0;
3002 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3004 if (unlikely(queue
->device
->use_global_bo_list
)) {
3005 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3006 bo_list
= &queue
->device
->bo_list
.list
;
3009 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3010 advance
, initial_preamble
, continue_preamble_cs
,
3012 can_patch
, base_fence
);
3014 if (unlikely(queue
->device
->use_global_bo_list
))
3015 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3018 radv_loge("failed to submit CS %d\n", i
);
3021 fence_emitted
= true;
3022 if (queue
->device
->trace_bo
) {
3023 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3027 radv_free_temp_syncobjs(queue
->device
,
3028 pSubmits
[i
].waitSemaphoreCount
,
3029 pSubmits
[i
].pWaitSemaphores
);
3030 radv_free_sem_info(&sem_info
);
3035 if (!fence_emitted
) {
3036 result
= radv_signal_fence(queue
, fence
);
3037 if (result
!= VK_SUCCESS
)
3045 VkResult
radv_QueueWaitIdle(
3048 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3050 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3051 radv_queue_family_to_ring(queue
->queue_family_index
),
3056 VkResult
radv_DeviceWaitIdle(
3059 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3061 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3062 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3063 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3069 VkResult
radv_EnumerateInstanceExtensionProperties(
3070 const char* pLayerName
,
3071 uint32_t* pPropertyCount
,
3072 VkExtensionProperties
* pProperties
)
3074 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3076 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3077 if (radv_supported_instance_extensions
.extensions
[i
]) {
3078 vk_outarray_append(&out
, prop
) {
3079 *prop
= radv_instance_extensions
[i
];
3084 return vk_outarray_status(&out
);
3087 VkResult
radv_EnumerateDeviceExtensionProperties(
3088 VkPhysicalDevice physicalDevice
,
3089 const char* pLayerName
,
3090 uint32_t* pPropertyCount
,
3091 VkExtensionProperties
* pProperties
)
3093 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3094 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3096 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3097 if (device
->supported_extensions
.extensions
[i
]) {
3098 vk_outarray_append(&out
, prop
) {
3099 *prop
= radv_device_extensions
[i
];
3104 return vk_outarray_status(&out
);
3107 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3108 VkInstance _instance
,
3111 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3113 return radv_lookup_entrypoint_checked(pName
,
3114 instance
? instance
->apiVersion
: 0,
3115 instance
? &instance
->enabled_extensions
: NULL
,
3119 /* The loader wants us to expose a second GetInstanceProcAddr function
3120 * to work around certain LD_PRELOAD issues seen in apps.
3123 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3124 VkInstance instance
,
3128 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3129 VkInstance instance
,
3132 return radv_GetInstanceProcAddr(instance
, pName
);
3136 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3137 VkInstance _instance
,
3141 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3142 VkInstance _instance
,
3145 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3147 return radv_lookup_physical_device_entrypoint_checked(pName
,
3148 instance
? instance
->apiVersion
: 0,
3149 instance
? &instance
->enabled_extensions
: NULL
);
3152 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3158 return radv_lookup_entrypoint_checked(pName
,
3159 device
->instance
->apiVersion
,
3160 &device
->instance
->enabled_extensions
,
3161 &device
->enabled_extensions
);
3164 bool radv_get_memory_fd(struct radv_device
*device
,
3165 struct radv_device_memory
*memory
,
3168 struct radeon_bo_metadata metadata
;
3170 if (memory
->image
) {
3171 radv_init_metadata(device
, memory
->image
, &metadata
);
3172 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3175 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3179 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3180 const VkMemoryAllocateInfo
* pAllocateInfo
,
3181 const VkAllocationCallbacks
* pAllocator
,
3182 VkDeviceMemory
* pMem
)
3184 struct radv_device_memory
*mem
;
3186 enum radeon_bo_domain domain
;
3188 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3190 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3192 if (pAllocateInfo
->allocationSize
== 0) {
3193 /* Apparently, this is allowed */
3194 *pMem
= VK_NULL_HANDLE
;
3198 const VkImportMemoryFdInfoKHR
*import_info
=
3199 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3200 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3201 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3202 const VkExportMemoryAllocateInfo
*export_info
=
3203 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3204 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3205 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3207 const struct wsi_memory_allocate_info
*wsi_info
=
3208 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3210 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3211 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3213 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3215 if (wsi_info
&& wsi_info
->implicit_sync
)
3216 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3218 if (dedicate_info
) {
3219 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3220 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3226 float priority_float
= 0.5;
3227 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3228 vk_find_struct_const(pAllocateInfo
->pNext
,
3229 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3231 priority_float
= priority_ext
->priority
;
3233 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3234 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3236 mem
->user_ptr
= NULL
;
3239 assert(import_info
->handleType
==
3240 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3241 import_info
->handleType
==
3242 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3243 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3244 priority
, NULL
, NULL
);
3246 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3249 close(import_info
->fd
);
3251 } else if (host_ptr_info
) {
3252 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3253 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3254 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3255 pAllocateInfo
->allocationSize
,
3258 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3261 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3264 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3265 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3266 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3267 domain
= RADEON_DOMAIN_GTT
;
3269 domain
= RADEON_DOMAIN_VRAM
;
3271 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3272 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3274 flags
|= RADEON_FLAG_CPU_ACCESS
;
3276 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3277 flags
|= RADEON_FLAG_GTT_WC
;
3279 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3280 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3281 if (device
->use_global_bo_list
) {
3282 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3286 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3287 domain
, flags
, priority
);
3290 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3293 mem
->type_index
= mem_type_index
;
3296 result
= radv_bo_list_add(device
, mem
->bo
);
3297 if (result
!= VK_SUCCESS
)
3300 *pMem
= radv_device_memory_to_handle(mem
);
3305 device
->ws
->buffer_destroy(mem
->bo
);
3307 vk_free2(&device
->alloc
, pAllocator
, mem
);
3312 VkResult
radv_AllocateMemory(
3314 const VkMemoryAllocateInfo
* pAllocateInfo
,
3315 const VkAllocationCallbacks
* pAllocator
,
3316 VkDeviceMemory
* pMem
)
3318 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3319 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3322 void radv_FreeMemory(
3324 VkDeviceMemory _mem
,
3325 const VkAllocationCallbacks
* pAllocator
)
3327 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3328 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3333 radv_bo_list_remove(device
, mem
->bo
);
3334 device
->ws
->buffer_destroy(mem
->bo
);
3337 vk_free2(&device
->alloc
, pAllocator
, mem
);
3340 VkResult
radv_MapMemory(
3342 VkDeviceMemory _memory
,
3343 VkDeviceSize offset
,
3345 VkMemoryMapFlags flags
,
3348 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3349 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3357 *ppData
= mem
->user_ptr
;
3359 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3366 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3369 void radv_UnmapMemory(
3371 VkDeviceMemory _memory
)
3373 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3374 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3379 if (mem
->user_ptr
== NULL
)
3380 device
->ws
->buffer_unmap(mem
->bo
);
3383 VkResult
radv_FlushMappedMemoryRanges(
3385 uint32_t memoryRangeCount
,
3386 const VkMappedMemoryRange
* pMemoryRanges
)
3391 VkResult
radv_InvalidateMappedMemoryRanges(
3393 uint32_t memoryRangeCount
,
3394 const VkMappedMemoryRange
* pMemoryRanges
)
3399 void radv_GetBufferMemoryRequirements(
3402 VkMemoryRequirements
* pMemoryRequirements
)
3404 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3405 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3407 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3409 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3410 pMemoryRequirements
->alignment
= 4096;
3412 pMemoryRequirements
->alignment
= 16;
3414 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3417 void radv_GetBufferMemoryRequirements2(
3419 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3420 VkMemoryRequirements2
*pMemoryRequirements
)
3422 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3423 &pMemoryRequirements
->memoryRequirements
);
3424 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3425 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3426 switch (ext
->sType
) {
3427 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3428 VkMemoryDedicatedRequirements
*req
=
3429 (VkMemoryDedicatedRequirements
*) ext
;
3430 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3431 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3440 void radv_GetImageMemoryRequirements(
3443 VkMemoryRequirements
* pMemoryRequirements
)
3445 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3446 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3448 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3450 pMemoryRequirements
->size
= image
->size
;
3451 pMemoryRequirements
->alignment
= image
->alignment
;
3454 void radv_GetImageMemoryRequirements2(
3456 const VkImageMemoryRequirementsInfo2
*pInfo
,
3457 VkMemoryRequirements2
*pMemoryRequirements
)
3459 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3460 &pMemoryRequirements
->memoryRequirements
);
3462 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3464 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3465 switch (ext
->sType
) {
3466 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3467 VkMemoryDedicatedRequirements
*req
=
3468 (VkMemoryDedicatedRequirements
*) ext
;
3469 req
->requiresDedicatedAllocation
= image
->shareable
;
3470 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3479 void radv_GetImageSparseMemoryRequirements(
3482 uint32_t* pSparseMemoryRequirementCount
,
3483 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3488 void radv_GetImageSparseMemoryRequirements2(
3490 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3491 uint32_t* pSparseMemoryRequirementCount
,
3492 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3497 void radv_GetDeviceMemoryCommitment(
3499 VkDeviceMemory memory
,
3500 VkDeviceSize
* pCommittedMemoryInBytes
)
3502 *pCommittedMemoryInBytes
= 0;
3505 VkResult
radv_BindBufferMemory2(VkDevice device
,
3506 uint32_t bindInfoCount
,
3507 const VkBindBufferMemoryInfo
*pBindInfos
)
3509 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3510 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3511 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3514 buffer
->bo
= mem
->bo
;
3515 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3523 VkResult
radv_BindBufferMemory(
3526 VkDeviceMemory memory
,
3527 VkDeviceSize memoryOffset
)
3529 const VkBindBufferMemoryInfo info
= {
3530 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3533 .memoryOffset
= memoryOffset
3536 return radv_BindBufferMemory2(device
, 1, &info
);
3539 VkResult
radv_BindImageMemory2(VkDevice device
,
3540 uint32_t bindInfoCount
,
3541 const VkBindImageMemoryInfo
*pBindInfos
)
3543 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3544 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3545 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3548 image
->bo
= mem
->bo
;
3549 image
->offset
= pBindInfos
[i
].memoryOffset
;
3559 VkResult
radv_BindImageMemory(
3562 VkDeviceMemory memory
,
3563 VkDeviceSize memoryOffset
)
3565 const VkBindImageMemoryInfo info
= {
3566 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3569 .memoryOffset
= memoryOffset
3572 return radv_BindImageMemory2(device
, 1, &info
);
3577 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3578 const VkSparseBufferMemoryBindInfo
*bind
)
3580 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3582 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3583 struct radv_device_memory
*mem
= NULL
;
3585 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3586 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3588 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3589 bind
->pBinds
[i
].resourceOffset
,
3590 bind
->pBinds
[i
].size
,
3591 mem
? mem
->bo
: NULL
,
3592 bind
->pBinds
[i
].memoryOffset
);
3597 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3598 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3600 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3602 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3603 struct radv_device_memory
*mem
= NULL
;
3605 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3606 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3608 device
->ws
->buffer_virtual_bind(image
->bo
,
3609 bind
->pBinds
[i
].resourceOffset
,
3610 bind
->pBinds
[i
].size
,
3611 mem
? mem
->bo
: NULL
,
3612 bind
->pBinds
[i
].memoryOffset
);
3616 VkResult
radv_QueueBindSparse(
3618 uint32_t bindInfoCount
,
3619 const VkBindSparseInfo
* pBindInfo
,
3622 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3623 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3624 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3625 bool fence_emitted
= false;
3629 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3630 struct radv_winsys_sem_info sem_info
;
3631 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3632 radv_sparse_buffer_bind_memory(queue
->device
,
3633 pBindInfo
[i
].pBufferBinds
+ j
);
3636 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3637 radv_sparse_image_opaque_bind_memory(queue
->device
,
3638 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3642 result
= radv_alloc_sem_info(queue
->device
->instance
,
3644 pBindInfo
[i
].waitSemaphoreCount
,
3645 pBindInfo
[i
].pWaitSemaphores
,
3646 pBindInfo
[i
].signalSemaphoreCount
,
3647 pBindInfo
[i
].pSignalSemaphores
,
3649 if (result
!= VK_SUCCESS
)
3652 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3653 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3654 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3659 radv_loge("failed to submit CS %d\n", i
);
3663 fence_emitted
= true;
3666 radv_free_sem_info(&sem_info
);
3671 if (!fence_emitted
) {
3672 result
= radv_signal_fence(queue
, fence
);
3673 if (result
!= VK_SUCCESS
)
3681 VkResult
radv_CreateFence(
3683 const VkFenceCreateInfo
* pCreateInfo
,
3684 const VkAllocationCallbacks
* pAllocator
,
3687 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3688 const VkExportFenceCreateInfo
*export
=
3689 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3690 VkExternalFenceHandleTypeFlags handleTypes
=
3691 export
? export
->handleTypes
: 0;
3693 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3695 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3698 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3700 fence
->fence_wsi
= NULL
;
3701 fence
->temp_syncobj
= 0;
3702 if (device
->always_use_syncobj
|| handleTypes
) {
3703 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3705 vk_free2(&device
->alloc
, pAllocator
, fence
);
3706 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3708 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3709 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3711 fence
->fence
= NULL
;
3713 fence
->fence
= device
->ws
->create_fence();
3714 if (!fence
->fence
) {
3715 vk_free2(&device
->alloc
, pAllocator
, fence
);
3716 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3719 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3720 device
->ws
->signal_fence(fence
->fence
);
3723 *pFence
= radv_fence_to_handle(fence
);
3728 void radv_DestroyFence(
3731 const VkAllocationCallbacks
* pAllocator
)
3733 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3734 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3739 if (fence
->temp_syncobj
)
3740 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3742 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3744 device
->ws
->destroy_fence(fence
->fence
);
3745 if (fence
->fence_wsi
)
3746 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3747 vk_free2(&device
->alloc
, pAllocator
, fence
);
3751 uint64_t radv_get_current_time(void)
3754 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3755 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3758 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3760 uint64_t current_time
= radv_get_current_time();
3762 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3764 return current_time
+ timeout
;
3768 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3769 uint32_t fenceCount
, const VkFence
*pFences
)
3771 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3772 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3773 if (fence
->fence
== NULL
|| fence
->syncobj
||
3774 fence
->temp_syncobj
|| fence
->fence_wsi
||
3775 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3781 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3783 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3784 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3785 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3791 VkResult
radv_WaitForFences(
3793 uint32_t fenceCount
,
3794 const VkFence
* pFences
,
3798 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3799 timeout
= radv_get_absolute_timeout(timeout
);
3801 if (device
->always_use_syncobj
&&
3802 radv_all_fences_syncobj(fenceCount
, pFences
))
3804 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3806 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3808 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3809 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3810 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3813 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3816 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3819 if (!waitAll
&& fenceCount
> 1) {
3820 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3821 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3822 uint32_t wait_count
= 0;
3823 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3825 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3827 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3828 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3830 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3835 fences
[wait_count
++] = fence
->fence
;
3838 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3839 waitAll
, timeout
- radv_get_current_time());
3842 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3845 while(radv_get_current_time() <= timeout
) {
3846 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3847 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3854 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3855 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3856 bool expired
= false;
3858 if (fence
->temp_syncobj
) {
3859 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3864 if (fence
->syncobj
) {
3865 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3871 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
3872 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
3873 radv_get_current_time() <= timeout
)
3877 expired
= device
->ws
->fence_wait(device
->ws
,
3884 if (fence
->fence_wsi
) {
3885 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3886 if (result
!= VK_SUCCESS
)
3894 VkResult
radv_ResetFences(VkDevice _device
,
3895 uint32_t fenceCount
,
3896 const VkFence
*pFences
)
3898 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3900 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3901 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3903 device
->ws
->reset_fence(fence
->fence
);
3905 /* Per spec, we first restore the permanent payload, and then reset, so
3906 * having a temp syncobj should not skip resetting the permanent syncobj. */
3907 if (fence
->temp_syncobj
) {
3908 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3909 fence
->temp_syncobj
= 0;
3912 if (fence
->syncobj
) {
3913 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3920 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3922 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3923 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3925 if (fence
->temp_syncobj
) {
3926 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3927 return success
? VK_SUCCESS
: VK_NOT_READY
;
3930 if (fence
->syncobj
) {
3931 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3932 return success
? VK_SUCCESS
: VK_NOT_READY
;
3936 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3937 return VK_NOT_READY
;
3939 if (fence
->fence_wsi
) {
3940 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3942 if (result
!= VK_SUCCESS
) {
3943 if (result
== VK_TIMEOUT
)
3944 return VK_NOT_READY
;
3952 // Queue semaphore functions
3954 VkResult
radv_CreateSemaphore(
3956 const VkSemaphoreCreateInfo
* pCreateInfo
,
3957 const VkAllocationCallbacks
* pAllocator
,
3958 VkSemaphore
* pSemaphore
)
3960 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3961 const VkExportSemaphoreCreateInfo
*export
=
3962 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
3963 VkExternalSemaphoreHandleTypeFlags handleTypes
=
3964 export
? export
->handleTypes
: 0;
3966 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
3968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3970 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3972 sem
->temp_syncobj
= 0;
3973 /* create a syncobject if we are going to export this semaphore */
3974 if (device
->always_use_syncobj
|| handleTypes
) {
3975 assert (device
->physical_device
->rad_info
.has_syncobj
);
3976 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
3978 vk_free2(&device
->alloc
, pAllocator
, sem
);
3979 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3983 sem
->sem
= device
->ws
->create_sem(device
->ws
);
3985 vk_free2(&device
->alloc
, pAllocator
, sem
);
3986 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3991 *pSemaphore
= radv_semaphore_to_handle(sem
);
3995 void radv_DestroySemaphore(
3997 VkSemaphore _semaphore
,
3998 const VkAllocationCallbacks
* pAllocator
)
4000 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4001 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4006 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4008 device
->ws
->destroy_sem(sem
->sem
);
4009 vk_free2(&device
->alloc
, pAllocator
, sem
);
4012 VkResult
radv_CreateEvent(
4014 const VkEventCreateInfo
* pCreateInfo
,
4015 const VkAllocationCallbacks
* pAllocator
,
4018 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4019 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4021 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4024 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4026 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4028 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4029 RADV_BO_PRIORITY_FENCE
);
4031 vk_free2(&device
->alloc
, pAllocator
, event
);
4032 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4035 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4037 *pEvent
= radv_event_to_handle(event
);
4042 void radv_DestroyEvent(
4045 const VkAllocationCallbacks
* pAllocator
)
4047 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4048 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4052 device
->ws
->buffer_destroy(event
->bo
);
4053 vk_free2(&device
->alloc
, pAllocator
, event
);
4056 VkResult
radv_GetEventStatus(
4060 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4062 if (*event
->map
== 1)
4063 return VK_EVENT_SET
;
4064 return VK_EVENT_RESET
;
4067 VkResult
radv_SetEvent(
4071 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4077 VkResult
radv_ResetEvent(
4081 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4087 VkResult
radv_CreateBuffer(
4089 const VkBufferCreateInfo
* pCreateInfo
,
4090 const VkAllocationCallbacks
* pAllocator
,
4093 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4094 struct radv_buffer
*buffer
;
4096 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4098 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4099 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4101 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4103 buffer
->size
= pCreateInfo
->size
;
4104 buffer
->usage
= pCreateInfo
->usage
;
4107 buffer
->flags
= pCreateInfo
->flags
;
4109 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4110 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4112 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4113 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4114 align64(buffer
->size
, 4096),
4115 4096, 0, RADEON_FLAG_VIRTUAL
,
4116 RADV_BO_PRIORITY_VIRTUAL
);
4118 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4119 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4123 *pBuffer
= radv_buffer_to_handle(buffer
);
4128 void radv_DestroyBuffer(
4131 const VkAllocationCallbacks
* pAllocator
)
4133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4134 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4139 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4140 device
->ws
->buffer_destroy(buffer
->bo
);
4142 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4145 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4147 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4149 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4150 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4154 static inline unsigned
4155 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4158 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4160 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4163 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4165 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4169 radv_init_dcc_control_reg(struct radv_device
*device
,
4170 struct radv_image_view
*iview
)
4172 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4173 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4174 unsigned max_compressed_block_size
;
4175 unsigned independent_64b_blocks
;
4177 if (!radv_image_has_dcc(iview
->image
))
4180 if (iview
->image
->info
.samples
> 1) {
4181 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4182 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4183 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4184 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4187 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4188 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4189 * dGPU and 64 for APU because all of our APUs to date use
4190 * DIMMs which have a request granularity size of 64B while all
4191 * other chips have a 32B request size.
4193 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4196 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4197 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4198 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4199 /* If this DCC image is potentially going to be used in texture
4200 * fetches, we need some special settings.
4202 independent_64b_blocks
= 1;
4203 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4205 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4206 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4207 * big as possible for better compression state.
4209 independent_64b_blocks
= 0;
4210 max_compressed_block_size
= max_uncompressed_block_size
;
4213 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4214 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4215 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4216 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
4220 radv_initialise_color_surface(struct radv_device
*device
,
4221 struct radv_color_buffer_info
*cb
,
4222 struct radv_image_view
*iview
)
4224 const struct vk_format_description
*desc
;
4225 unsigned ntype
, format
, swap
, endian
;
4226 unsigned blend_clamp
= 0, blend_bypass
= 0;
4228 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4229 const struct radeon_surf
*surf
= &plane
->surface
;
4231 desc
= vk_format_description(iview
->vk_format
);
4233 memset(cb
, 0, sizeof(*cb
));
4235 /* Intensity is implemented as Red, so treat it that way. */
4236 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4238 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4240 cb
->cb_color_base
= va
>> 8;
4242 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4243 struct gfx9_surf_meta_flags meta
;
4244 if (iview
->image
->dcc_offset
)
4245 meta
= surf
->u
.gfx9
.dcc
;
4247 meta
= surf
->u
.gfx9
.cmask
;
4249 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4250 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4251 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4252 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4254 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4255 cb
->cb_color_base
|= surf
->tile_swizzle
;
4257 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4259 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4260 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4262 cb
->cb_color_base
+= level_info
->offset
>> 8;
4263 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4264 cb
->cb_color_base
|= surf
->tile_swizzle
;
4266 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4267 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4268 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4270 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4271 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4272 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4274 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4276 if (radv_image_has_fmask(iview
->image
)) {
4277 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4278 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4279 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4280 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4282 /* This must be set for fast clear to work without FMASK. */
4283 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4284 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4285 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4286 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4290 /* CMASK variables */
4291 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4292 va
+= iview
->image
->cmask
.offset
;
4293 cb
->cb_color_cmask
= va
>> 8;
4295 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4296 va
+= iview
->image
->dcc_offset
;
4297 cb
->cb_dcc_base
= va
>> 8;
4298 cb
->cb_dcc_base
|= surf
->tile_swizzle
;
4300 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4301 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4302 S_028C6C_SLICE_MAX(max_slice
);
4304 if (iview
->image
->info
.samples
> 1) {
4305 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4307 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4308 S_028C74_NUM_FRAGMENTS(log_samples
);
4311 if (radv_image_has_fmask(iview
->image
)) {
4312 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4313 cb
->cb_color_fmask
= va
>> 8;
4314 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4316 cb
->cb_color_fmask
= cb
->cb_color_base
;
4319 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4321 vk_format_get_first_non_void_channel(iview
->vk_format
));
4322 format
= radv_translate_colorformat(iview
->vk_format
);
4323 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4324 radv_finishme("Illegal color\n");
4325 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4326 endian
= radv_colorformat_endian_swap(format
);
4328 /* blend clamp should be set for all NORM/SRGB types */
4329 if (ntype
== V_028C70_NUMBER_UNORM
||
4330 ntype
== V_028C70_NUMBER_SNORM
||
4331 ntype
== V_028C70_NUMBER_SRGB
)
4334 /* set blend bypass according to docs if SINT/UINT or
4335 8/24 COLOR variants */
4336 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4337 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4338 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4343 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4344 (format
== V_028C70_COLOR_8
||
4345 format
== V_028C70_COLOR_8_8
||
4346 format
== V_028C70_COLOR_8_8_8_8
))
4347 ->color_is_int8
= true;
4349 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4350 S_028C70_COMP_SWAP(swap
) |
4351 S_028C70_BLEND_CLAMP(blend_clamp
) |
4352 S_028C70_BLEND_BYPASS(blend_bypass
) |
4353 S_028C70_SIMPLE_FLOAT(1) |
4354 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4355 ntype
!= V_028C70_NUMBER_SNORM
&&
4356 ntype
!= V_028C70_NUMBER_SRGB
&&
4357 format
!= V_028C70_COLOR_8_24
&&
4358 format
!= V_028C70_COLOR_24_8
) |
4359 S_028C70_NUMBER_TYPE(ntype
) |
4360 S_028C70_ENDIAN(endian
);
4361 if (radv_image_has_fmask(iview
->image
)) {
4362 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4363 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4364 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4365 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4369 if (radv_image_has_cmask(iview
->image
) &&
4370 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4371 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4373 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4374 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4376 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4378 /* This must be set for fast clear to work without FMASK. */
4379 if (!radv_image_has_fmask(iview
->image
) &&
4380 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4381 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4382 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4385 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4386 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4388 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4389 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4390 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4391 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4393 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
4394 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4395 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4396 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4397 S_028C68_MIP0_HEIGHT(height
- 1) |
4398 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4403 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4404 struct radv_image_view
*iview
)
4406 unsigned max_zplanes
= 0;
4408 assert(radv_image_is_tc_compat_htile(iview
->image
));
4410 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4411 /* Default value for 32-bit depth surfaces. */
4414 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4415 iview
->image
->info
.samples
> 1)
4418 max_zplanes
= max_zplanes
+ 1;
4420 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4421 /* Do not enable Z plane compression for 16-bit depth
4422 * surfaces because isn't supported on GFX8. Only
4423 * 32-bit depth surfaces are supported by the hardware.
4424 * This allows to maintain shader compatibility and to
4425 * reduce the number of depth decompressions.
4429 if (iview
->image
->info
.samples
<= 1)
4431 else if (iview
->image
->info
.samples
<= 4)
4442 radv_initialise_ds_surface(struct radv_device
*device
,
4443 struct radv_ds_buffer_info
*ds
,
4444 struct radv_image_view
*iview
)
4446 unsigned level
= iview
->base_mip
;
4447 unsigned format
, stencil_format
;
4448 uint64_t va
, s_offs
, z_offs
;
4449 bool stencil_only
= false;
4450 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4451 const struct radeon_surf
*surf
= &plane
->surface
;
4453 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4455 memset(ds
, 0, sizeof(*ds
));
4456 switch (iview
->image
->vk_format
) {
4457 case VK_FORMAT_D24_UNORM_S8_UINT
:
4458 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4459 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4460 ds
->offset_scale
= 2.0f
;
4462 case VK_FORMAT_D16_UNORM
:
4463 case VK_FORMAT_D16_UNORM_S8_UINT
:
4464 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4465 ds
->offset_scale
= 4.0f
;
4467 case VK_FORMAT_D32_SFLOAT
:
4468 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4469 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4470 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4471 ds
->offset_scale
= 1.0f
;
4473 case VK_FORMAT_S8_UINT
:
4474 stencil_only
= true;
4480 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4481 stencil_format
= surf
->has_stencil
?
4482 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4484 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4485 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4486 S_028008_SLICE_MAX(max_slice
);
4488 ds
->db_htile_data_base
= 0;
4489 ds
->db_htile_surface
= 0;
4491 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4492 s_offs
= z_offs
= va
;
4494 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4495 assert(surf
->u
.gfx9
.surf_offset
== 0);
4496 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4498 ds
->db_z_info
= S_028038_FORMAT(format
) |
4499 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4500 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4501 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4502 S_028038_ZRANGE_PRECISION(1);
4503 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4504 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4506 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4507 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4508 ds
->db_depth_view
|= S_028008_MIPID(level
);
4510 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4511 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4513 if (radv_htile_enabled(iview
->image
, level
)) {
4514 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4516 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4517 unsigned max_zplanes
=
4518 radv_calc_decompress_on_z_planes(device
, iview
);
4520 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4521 S_028038_ITERATE_FLUSH(1);
4522 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4525 if (!surf
->has_stencil
)
4526 /* Use all of the htile_buffer for depth if there's no stencil. */
4527 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4528 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4529 iview
->image
->htile_offset
;
4530 ds
->db_htile_data_base
= va
>> 8;
4531 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4532 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
) |
4533 S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4536 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4539 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4541 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4542 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4544 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4545 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4546 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4548 if (iview
->image
->info
.samples
> 1)
4549 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4551 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4552 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4553 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4554 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4555 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4556 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4557 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4558 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4561 tile_mode
= stencil_tile_mode
;
4563 ds
->db_depth_info
|=
4564 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4565 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4566 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4567 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4568 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4569 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4570 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4571 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4573 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4574 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4575 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4576 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4578 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4581 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4582 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4583 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4585 if (radv_htile_enabled(iview
->image
, level
)) {
4586 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4588 if (!surf
->has_stencil
&&
4589 !radv_image_is_tc_compat_htile(iview
->image
))
4590 /* Use all of the htile_buffer for depth if there's no stencil. */
4591 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4593 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4594 iview
->image
->htile_offset
;
4595 ds
->db_htile_data_base
= va
>> 8;
4596 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4598 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4599 unsigned max_zplanes
=
4600 radv_calc_decompress_on_z_planes(device
, iview
);
4602 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4603 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4608 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4609 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4612 VkResult
radv_CreateFramebuffer(
4614 const VkFramebufferCreateInfo
* pCreateInfo
,
4615 const VkAllocationCallbacks
* pAllocator
,
4616 VkFramebuffer
* pFramebuffer
)
4618 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4619 struct radv_framebuffer
*framebuffer
;
4621 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4623 size_t size
= sizeof(*framebuffer
) +
4624 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4625 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4626 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4627 if (framebuffer
== NULL
)
4628 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4630 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4631 framebuffer
->width
= pCreateInfo
->width
;
4632 framebuffer
->height
= pCreateInfo
->height
;
4633 framebuffer
->layers
= pCreateInfo
->layers
;
4634 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4635 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4636 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4637 framebuffer
->attachments
[i
].attachment
= iview
;
4638 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4639 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4641 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4643 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4644 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4645 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4648 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4652 void radv_DestroyFramebuffer(
4655 const VkAllocationCallbacks
* pAllocator
)
4657 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4658 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4662 vk_free2(&device
->alloc
, pAllocator
, fb
);
4665 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4667 switch (address_mode
) {
4668 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4669 return V_008F30_SQ_TEX_WRAP
;
4670 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4671 return V_008F30_SQ_TEX_MIRROR
;
4672 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4673 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4674 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4675 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4676 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4677 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4679 unreachable("illegal tex wrap mode");
4685 radv_tex_compare(VkCompareOp op
)
4688 case VK_COMPARE_OP_NEVER
:
4689 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4690 case VK_COMPARE_OP_LESS
:
4691 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4692 case VK_COMPARE_OP_EQUAL
:
4693 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4694 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4695 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4696 case VK_COMPARE_OP_GREATER
:
4697 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4698 case VK_COMPARE_OP_NOT_EQUAL
:
4699 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4700 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4701 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4702 case VK_COMPARE_OP_ALWAYS
:
4703 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4705 unreachable("illegal compare mode");
4711 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4714 case VK_FILTER_NEAREST
:
4715 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4716 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4717 case VK_FILTER_LINEAR
:
4718 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4719 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4720 case VK_FILTER_CUBIC_IMG
:
4722 fprintf(stderr
, "illegal texture filter");
4728 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4731 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4732 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4733 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4734 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4736 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4741 radv_tex_bordercolor(VkBorderColor bcolor
)
4744 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4745 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4746 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4747 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4748 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4749 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4750 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4751 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4752 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4760 radv_tex_aniso_filter(unsigned filter
)
4774 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4777 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4778 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4779 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4780 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4781 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4782 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4790 radv_get_max_anisotropy(struct radv_device
*device
,
4791 const VkSamplerCreateInfo
*pCreateInfo
)
4793 if (device
->force_aniso
>= 0)
4794 return device
->force_aniso
;
4796 if (pCreateInfo
->anisotropyEnable
&&
4797 pCreateInfo
->maxAnisotropy
> 1.0f
)
4798 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4804 radv_init_sampler(struct radv_device
*device
,
4805 struct radv_sampler
*sampler
,
4806 const VkSamplerCreateInfo
*pCreateInfo
)
4808 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4809 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4810 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= GFX8
);
4811 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4813 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4814 vk_find_struct_const(pCreateInfo
->pNext
,
4815 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4816 if (sampler_reduction
)
4817 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4819 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4820 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4821 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4822 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4823 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4824 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4825 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4826 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4827 S_008F30_DISABLE_CUBE_WRAP(0) |
4828 S_008F30_COMPAT_MODE(is_vi
) |
4829 S_008F30_FILTER_MODE(filter_mode
));
4830 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4831 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4832 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4833 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4834 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4835 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4836 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4837 S_008F38_MIP_POINT_PRECLAMP(0) |
4838 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
4839 S_008F38_FILTER_PREC_FIX(1) |
4840 S_008F38_ANISO_OVERRIDE(is_vi
));
4841 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4842 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4845 VkResult
radv_CreateSampler(
4847 const VkSamplerCreateInfo
* pCreateInfo
,
4848 const VkAllocationCallbacks
* pAllocator
,
4849 VkSampler
* pSampler
)
4851 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4852 struct radv_sampler
*sampler
;
4854 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
4855 vk_find_struct_const(pCreateInfo
->pNext
,
4856 SAMPLER_YCBCR_CONVERSION_INFO
);
4858 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4860 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4861 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4863 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4865 radv_init_sampler(device
, sampler
, pCreateInfo
);
4867 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
4868 *pSampler
= radv_sampler_to_handle(sampler
);
4873 void radv_DestroySampler(
4876 const VkAllocationCallbacks
* pAllocator
)
4878 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4879 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4883 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4886 /* vk_icd.h does not declare this function, so we declare it here to
4887 * suppress Wmissing-prototypes.
4889 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4890 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4892 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4893 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4895 /* For the full details on loader interface versioning, see
4896 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4897 * What follows is a condensed summary, to help you navigate the large and
4898 * confusing official doc.
4900 * - Loader interface v0 is incompatible with later versions. We don't
4903 * - In loader interface v1:
4904 * - The first ICD entrypoint called by the loader is
4905 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4907 * - The ICD must statically expose no other Vulkan symbol unless it is
4908 * linked with -Bsymbolic.
4909 * - Each dispatchable Vulkan handle created by the ICD must be
4910 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4911 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4912 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4913 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4914 * such loader-managed surfaces.
4916 * - Loader interface v2 differs from v1 in:
4917 * - The first ICD entrypoint called by the loader is
4918 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4919 * statically expose this entrypoint.
4921 * - Loader interface v3 differs from v2 in:
4922 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4923 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4924 * because the loader no longer does so.
4926 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
4930 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
4931 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
4934 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4935 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
4937 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
4939 /* At the moment, we support only the below handle types. */
4940 assert(pGetFdInfo
->handleType
==
4941 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4942 pGetFdInfo
->handleType
==
4943 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4945 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
4947 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4951 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
4952 VkExternalMemoryHandleTypeFlagBits handleType
,
4954 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
4956 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4958 switch (handleType
) {
4959 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
4960 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
4964 /* The valid usage section for this function says:
4966 * "handleType must not be one of the handle types defined as
4969 * So opaque handle types fall into the default "unsupported" case.
4971 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4975 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
4979 uint32_t syncobj_handle
= 0;
4980 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
4982 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4985 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
4987 *syncobj
= syncobj_handle
;
4993 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
4997 /* If we create a syncobj we do it locally so that if we have an error, we don't
4998 * leave a syncobj in an undetermined state in the fence. */
4999 uint32_t syncobj_handle
= *syncobj
;
5000 if (!syncobj_handle
) {
5001 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5003 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5008 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5010 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5012 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5015 *syncobj
= syncobj_handle
;
5022 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5023 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5025 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5026 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5027 uint32_t *syncobj_dst
= NULL
;
5029 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5030 syncobj_dst
= &sem
->temp_syncobj
;
5032 syncobj_dst
= &sem
->syncobj
;
5035 switch(pImportSemaphoreFdInfo
->handleType
) {
5036 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5037 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5038 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5039 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5041 unreachable("Unhandled semaphore handle type");
5045 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5046 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5049 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5050 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5052 uint32_t syncobj_handle
;
5054 if (sem
->temp_syncobj
)
5055 syncobj_handle
= sem
->temp_syncobj
;
5057 syncobj_handle
= sem
->syncobj
;
5059 switch(pGetFdInfo
->handleType
) {
5060 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5061 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5063 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5064 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5066 if (sem
->temp_syncobj
) {
5067 close (sem
->temp_syncobj
);
5068 sem
->temp_syncobj
= 0;
5070 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5075 unreachable("Unhandled semaphore handle type");
5079 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5083 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5084 VkPhysicalDevice physicalDevice
,
5085 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5086 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5088 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5090 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5091 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5092 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5093 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5094 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5095 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5096 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5097 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5098 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5099 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5100 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5101 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5102 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5104 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5105 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5106 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5110 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5111 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5114 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5115 uint32_t *syncobj_dst
= NULL
;
5118 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5119 syncobj_dst
= &fence
->temp_syncobj
;
5121 syncobj_dst
= &fence
->syncobj
;
5124 switch(pImportFenceFdInfo
->handleType
) {
5125 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5126 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5127 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5128 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5130 unreachable("Unhandled fence handle type");
5134 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5135 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5138 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5139 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5141 uint32_t syncobj_handle
;
5143 if (fence
->temp_syncobj
)
5144 syncobj_handle
= fence
->temp_syncobj
;
5146 syncobj_handle
= fence
->syncobj
;
5148 switch(pGetFdInfo
->handleType
) {
5149 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5150 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5152 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5153 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5155 if (fence
->temp_syncobj
) {
5156 close (fence
->temp_syncobj
);
5157 fence
->temp_syncobj
= 0;
5159 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5164 unreachable("Unhandled fence handle type");
5168 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5172 void radv_GetPhysicalDeviceExternalFenceProperties(
5173 VkPhysicalDevice physicalDevice
,
5174 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5175 VkExternalFenceProperties
*pExternalFenceProperties
)
5177 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5179 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5180 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5181 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5182 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5183 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5184 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5185 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5187 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5188 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5189 pExternalFenceProperties
->externalFenceFeatures
= 0;
5194 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5195 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5196 const VkAllocationCallbacks
* pAllocator
,
5197 VkDebugReportCallbackEXT
* pCallback
)
5199 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5200 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5201 pCreateInfo
, pAllocator
, &instance
->alloc
,
5206 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5207 VkDebugReportCallbackEXT _callback
,
5208 const VkAllocationCallbacks
* pAllocator
)
5210 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5211 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5212 _callback
, pAllocator
, &instance
->alloc
);
5216 radv_DebugReportMessageEXT(VkInstance _instance
,
5217 VkDebugReportFlagsEXT flags
,
5218 VkDebugReportObjectTypeEXT objectType
,
5221 int32_t messageCode
,
5222 const char* pLayerPrefix
,
5223 const char* pMessage
)
5225 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5226 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5227 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5231 radv_GetDeviceGroupPeerMemoryFeatures(
5234 uint32_t localDeviceIndex
,
5235 uint32_t remoteDeviceIndex
,
5236 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5238 assert(localDeviceIndex
== remoteDeviceIndex
);
5240 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5241 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5242 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5243 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5246 static const VkTimeDomainEXT radv_time_domains
[] = {
5247 VK_TIME_DOMAIN_DEVICE_EXT
,
5248 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5249 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5252 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5253 VkPhysicalDevice physicalDevice
,
5254 uint32_t *pTimeDomainCount
,
5255 VkTimeDomainEXT
*pTimeDomains
)
5258 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5260 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5261 vk_outarray_append(&out
, i
) {
5262 *i
= radv_time_domains
[d
];
5266 return vk_outarray_status(&out
);
5270 radv_clock_gettime(clockid_t clock_id
)
5272 struct timespec current
;
5275 ret
= clock_gettime(clock_id
, ¤t
);
5276 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5277 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5281 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5284 VkResult
radv_GetCalibratedTimestampsEXT(
5286 uint32_t timestampCount
,
5287 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5288 uint64_t *pTimestamps
,
5289 uint64_t *pMaxDeviation
)
5291 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5292 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5294 uint64_t begin
, end
;
5295 uint64_t max_clock_period
= 0;
5297 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5299 for (d
= 0; d
< timestampCount
; d
++) {
5300 switch (pTimestampInfos
[d
].timeDomain
) {
5301 case VK_TIME_DOMAIN_DEVICE_EXT
:
5302 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5304 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5305 max_clock_period
= MAX2(max_clock_period
, device_period
);
5307 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5308 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5309 max_clock_period
= MAX2(max_clock_period
, 1);
5312 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5313 pTimestamps
[d
] = begin
;
5321 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5324 * The maximum deviation is the sum of the interval over which we
5325 * perform the sampling and the maximum period of any sampled
5326 * clock. That's because the maximum skew between any two sampled
5327 * clock edges is when the sampled clock with the largest period is
5328 * sampled at the end of that period but right at the beginning of the
5329 * sampling interval and some other clock is sampled right at the
5330 * begining of its sampling period and right at the end of the
5331 * sampling interval. Let's assume the GPU has the longest clock
5332 * period and that the application is sampling GPU and monotonic:
5335 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5336 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5340 * GPU -----_____-----_____-----_____-----_____
5343 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5344 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5346 * Interval <----------------->
5347 * Deviation <-------------------------->
5351 * m = read(monotonic) 2
5354 * We round the sample interval up by one tick to cover sampling error
5355 * in the interval clock
5358 uint64_t sample_interval
= end
- begin
+ 1;
5360 *pMaxDeviation
= sample_interval
+ max_clock_period
;