2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_is_mem_type_vram(enum radv_mem_type type
)
135 return type
== RADV_MEM_TYPE_VRAM
||
136 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
140 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
142 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
143 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
148 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
149 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
155 return type
== RADV_MEM_TYPE_GTT_CACHED
||
156 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
160 radv_is_mem_type_uncached(enum radv_mem_type type
)
162 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
163 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
164 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
169 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
172 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
173 uint64_t vram_size
= radv_get_vram_size(device
);
174 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
175 device
->memory_properties
.memoryHeapCount
= 0;
177 vram_index
= device
->memory_properties
.memoryHeapCount
++;
178 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
180 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 if (visible_vram_size
) {
184 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
185 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
186 .size
= visible_vram_size
,
187 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
190 if (device
->rad_info
.gart_size
> 0) {
191 gart_index
= device
->memory_properties
.memoryHeapCount
++;
192 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
193 .size
= device
->rad_info
.gart_size
,
194 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
199 unsigned type_count
= 0;
200 if (vram_index
>= 0) {
201 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
202 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
203 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
204 .heapIndex
= vram_index
,
207 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
212 .heapIndex
= gart_index
,
215 if (visible_vram_index
>= 0) {
216 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
221 .heapIndex
= visible_vram_index
,
224 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
230 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
231 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
234 .heapIndex
= gart_index
,
237 if (gart_index
>= 0) {
238 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
239 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
240 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
243 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
244 .heapIndex
= gart_index
,
247 device
->memory_properties
.memoryTypeCount
= type_count
;
249 if (device
->rad_info
.has_l2_uncached
) {
250 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
251 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
253 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
255 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
256 enum radv_mem_type mem_type_id
;
258 switch (device
->mem_type_indices
[i
]) {
259 case RADV_MEM_TYPE_VRAM
:
260 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
263 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
266 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
268 case RADV_MEM_TYPE_GTT_CACHED
:
269 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
272 unreachable("invalid memory type");
275 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
279 device
->mem_type_indices
[type_count
] = mem_type_id
;
280 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
281 .propertyFlags
= property_flags
,
282 .heapIndex
= mem_type
.heapIndex
,
286 device
->memory_properties
.memoryTypeCount
= type_count
;
291 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
293 const char *family
= getenv("RADV_FORCE_FAMILY");
299 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
300 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
301 /* Override family and chip_class. */
302 device
->rad_info
.family
= i
;
303 device
->rad_info
.name
= "OVERRIDDEN";
305 if (i
>= CHIP_NAVI10
)
306 device
->rad_info
.chip_class
= GFX10
;
307 else if (i
>= CHIP_VEGA10
)
308 device
->rad_info
.chip_class
= GFX9
;
309 else if (i
>= CHIP_TONGA
)
310 device
->rad_info
.chip_class
= GFX8
;
311 else if (i
>= CHIP_BONAIRE
)
312 device
->rad_info
.chip_class
= GFX7
;
314 device
->rad_info
.chip_class
= GFX6
;
316 /* Don't submit any IBs. */
317 device
->instance
->debug_flags
|= RADV_DEBUG_NOOP
;
322 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
327 radv_physical_device_init(struct radv_physical_device
*device
,
328 struct radv_instance
*instance
,
329 drmDevicePtr drm_device
)
331 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
333 drmVersionPtr version
;
337 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
339 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
340 radv_logi("Could not open device '%s'", path
);
342 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
345 version
= drmGetVersion(fd
);
349 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
350 radv_logi("Could not get the kernel driver version for device '%s'", path
);
352 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
353 "failed to get version %s: %m", path
);
356 if (strcmp(version
->name
, "amdgpu")) {
357 drmFreeVersion(version
);
360 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
361 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
363 return VK_ERROR_INCOMPATIBLE_DRIVER
;
365 drmFreeVersion(version
);
367 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
368 radv_logi("Found compatible device '%s'.", path
);
370 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
371 device
->instance
= instance
;
373 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
374 instance
->perftest_flags
);
376 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
380 if (instance
->enabled_extensions
.KHR_display
) {
381 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
382 if (master_fd
>= 0) {
383 uint32_t accel_working
= 0;
384 struct drm_amdgpu_info request
= {
385 .return_pointer
= (uintptr_t)&accel_working
,
386 .return_size
= sizeof(accel_working
),
387 .query
= AMDGPU_INFO_ACCEL_WORKING
390 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
397 device
->master_fd
= master_fd
;
398 device
->local_fd
= fd
;
399 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
401 radv_handle_env_var_force_family(device
);
403 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
405 snprintf(device
->name
, sizeof(device
->name
),
406 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
407 device
->rad_info
.name
);
409 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
410 device
->ws
->destroy(device
->ws
);
411 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
412 "cannot generate UUID");
416 /* These flags affect shader compilation. */
417 uint64_t shader_env_flags
=
418 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
419 (device
->use_aco
? 0x2 : 0);
421 /* The gpu id is already embedded in the uuid so we just pass "radv"
422 * when creating the cache.
424 char buf
[VK_UUID_SIZE
* 2 + 1];
425 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
426 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
428 if (device
->rad_info
.chip_class
< GFX8
)
429 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
431 radv_get_driver_uuid(&device
->driver_uuid
);
432 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
434 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
435 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
437 device
->dcc_msaa_allowed
=
438 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
440 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
441 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
443 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
444 device
->rad_info
.family
!= CHIP_NAVI14
&&
445 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
446 if (device
->use_aco
&& device
->use_ngg
) {
447 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
448 device
->use_ngg
= false;
451 device
->use_ngg_streamout
= false;
453 /* Determine the number of threads per wave for all stages. */
454 device
->cs_wave_size
= 64;
455 device
->ps_wave_size
= 64;
456 device
->ge_wave_size
= 64;
458 if (device
->rad_info
.chip_class
>= GFX10
) {
459 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
460 device
->cs_wave_size
= 32;
462 /* For pixel shaders, wave64 is recommanded. */
463 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
464 device
->ps_wave_size
= 32;
466 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
467 device
->ge_wave_size
= 32;
470 radv_physical_device_init_mem_types(device
);
471 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
473 device
->bus_info
= *drm_device
->businfo
.pci
;
475 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
476 ac_print_gpu_info(&device
->rad_info
);
478 /* The WSI is structured as a layer on top of the driver, so this has
479 * to be the last part of initialization (at least until we get other
482 result
= radv_init_wsi(device
);
483 if (result
!= VK_SUCCESS
) {
484 device
->ws
->destroy(device
->ws
);
485 vk_error(instance
, result
);
499 radv_physical_device_finish(struct radv_physical_device
*device
)
501 radv_finish_wsi(device
);
502 device
->ws
->destroy(device
->ws
);
503 disk_cache_destroy(device
->disk_cache
);
504 close(device
->local_fd
);
505 if (device
->master_fd
!= -1)
506 close(device
->master_fd
);
510 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
511 VkSystemAllocationScope allocationScope
)
517 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
518 size_t align
, VkSystemAllocationScope allocationScope
)
520 return realloc(pOriginal
, size
);
524 default_free_func(void *pUserData
, void *pMemory
)
529 static const VkAllocationCallbacks default_alloc
= {
531 .pfnAllocation
= default_alloc_func
,
532 .pfnReallocation
= default_realloc_func
,
533 .pfnFree
= default_free_func
,
536 static const struct debug_control radv_debug_options
[] = {
537 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
538 {"nodcc", RADV_DEBUG_NO_DCC
},
539 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
540 {"nocache", RADV_DEBUG_NO_CACHE
},
541 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
542 {"nohiz", RADV_DEBUG_NO_HIZ
},
543 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
544 {"allbos", RADV_DEBUG_ALL_BOS
},
545 {"noibs", RADV_DEBUG_NO_IBS
},
546 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
547 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
548 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
549 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
550 {"nosisched", RADV_DEBUG_NO_SISCHED
},
551 {"preoptir", RADV_DEBUG_PREOPTIR
},
552 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
553 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
554 {"info", RADV_DEBUG_INFO
},
555 {"errors", RADV_DEBUG_ERRORS
},
556 {"startup", RADV_DEBUG_STARTUP
},
557 {"checkir", RADV_DEBUG_CHECKIR
},
558 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
559 {"nobinning", RADV_DEBUG_NOBINNING
},
560 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
561 {"nongg", RADV_DEBUG_NO_NGG
},
562 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
563 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
564 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
565 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
566 {"noop", RADV_DEBUG_NOOP
},
571 radv_get_debug_option_name(int id
)
573 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
574 return radv_debug_options
[id
].string
;
577 static const struct debug_control radv_perftest_options
[] = {
578 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
579 {"sisched", RADV_PERFTEST_SISCHED
},
580 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
581 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
582 {"bolist", RADV_PERFTEST_BO_LIST
},
583 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
584 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
585 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
586 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
587 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
588 {"dfsm", RADV_PERFTEST_DFSM
},
589 {"aco", RADV_PERFTEST_ACO
},
594 radv_get_perftest_option_name(int id
)
596 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
597 return radv_perftest_options
[id
].string
;
601 radv_handle_per_app_options(struct radv_instance
*instance
,
602 const VkApplicationInfo
*info
)
604 const char *name
= info
? info
->pApplicationName
: NULL
;
609 if (!strcmp(name
, "Talos - Linux - 32bit") ||
610 !strcmp(name
, "Talos - Linux - 64bit")) {
611 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
612 /* Force enable LLVM sisched for Talos because it looks
613 * safe and it gives few more FPS.
615 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
617 } else if (!strcmp(name
, "DOOM_VFR")) {
618 /* Work around a Doom VFR game bug */
619 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
620 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
621 /* Workaround for a WaW hazard when LLVM moves/merges
622 * load/store memory operations.
623 * See https://reviews.llvm.org/D61313
625 if (LLVM_VERSION_MAJOR
< 9)
626 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
627 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
628 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
629 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
630 /* Force enable VK_AMD_shader_ballot because it looks
631 * safe and it gives a nice boost (+20% on Vega 56 at
632 * this time). It also prevents corruption on LLVM.
634 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
636 } else if (!strcmp(name
, "Fledge")) {
638 * Zero VRAM for "The Surge 2"
640 * This avoid a hang when when rendering any level. Likely
641 * uninitialized data in an indirect draw.
643 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
647 static int radv_get_instance_extension_index(const char *name
)
649 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
650 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
656 static const char radv_dri_options_xml
[] =
658 DRI_CONF_SECTION_PERFORMANCE
659 DRI_CONF_ADAPTIVE_SYNC("true")
660 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
661 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
664 DRI_CONF_SECTION_DEBUG
665 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
669 static void radv_init_dri_options(struct radv_instance
*instance
)
671 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
672 driParseConfigFiles(&instance
->dri_options
,
673 &instance
->available_dri_options
,
675 instance
->engineName
,
676 instance
->engineVersion
);
679 VkResult
radv_CreateInstance(
680 const VkInstanceCreateInfo
* pCreateInfo
,
681 const VkAllocationCallbacks
* pAllocator
,
682 VkInstance
* pInstance
)
684 struct radv_instance
*instance
;
687 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
689 uint32_t client_version
;
690 if (pCreateInfo
->pApplicationInfo
&&
691 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
692 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
694 client_version
= VK_API_VERSION_1_0
;
697 const char *engine_name
= NULL
;
698 uint32_t engine_version
= 0;
699 if (pCreateInfo
->pApplicationInfo
) {
700 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
701 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
704 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
705 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
707 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
709 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
712 instance
->alloc
= *pAllocator
;
714 instance
->alloc
= default_alloc
;
716 instance
->apiVersion
= client_version
;
717 instance
->physicalDeviceCount
= -1;
719 /* Get secure compile thread count. NOTE: We cap this at 32 */
720 #define MAX_SC_PROCS 32
721 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
723 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
725 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
728 /* Disable memory cache when secure compile is set */
729 if (radv_device_use_secure_compile(instance
))
730 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
732 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
733 radv_perftest_options
);
735 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
736 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
738 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
739 radv_logi("Created an instance");
741 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
742 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
743 int index
= radv_get_instance_extension_index(ext_name
);
745 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
746 vk_free2(&default_alloc
, pAllocator
, instance
);
747 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
750 instance
->enabled_extensions
.extensions
[index
] = true;
753 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
754 if (result
!= VK_SUCCESS
) {
755 vk_free2(&default_alloc
, pAllocator
, instance
);
756 return vk_error(instance
, result
);
759 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
760 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
761 instance
->engineVersion
= engine_version
;
763 glsl_type_singleton_init_or_ref();
765 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
767 radv_init_dri_options(instance
);
768 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
770 *pInstance
= radv_instance_to_handle(instance
);
775 void radv_DestroyInstance(
776 VkInstance _instance
,
777 const VkAllocationCallbacks
* pAllocator
)
779 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
784 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
785 radv_physical_device_finish(instance
->physicalDevices
+ i
);
788 vk_free(&instance
->alloc
, instance
->engineName
);
790 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
792 glsl_type_singleton_decref();
794 driDestroyOptionCache(&instance
->dri_options
);
795 driDestroyOptionInfo(&instance
->available_dri_options
);
797 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
799 vk_free(&instance
->alloc
, instance
);
803 radv_enumerate_devices(struct radv_instance
*instance
)
805 /* TODO: Check for more devices ? */
806 drmDevicePtr devices
[8];
807 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
810 instance
->physicalDeviceCount
= 0;
812 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
814 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
815 radv_logi("Found %d drm nodes", max_devices
);
818 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
820 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
821 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
822 devices
[i
]->bustype
== DRM_BUS_PCI
&&
823 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
825 result
= radv_physical_device_init(instance
->physicalDevices
+
826 instance
->physicalDeviceCount
,
829 if (result
== VK_SUCCESS
)
830 ++instance
->physicalDeviceCount
;
831 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
835 drmFreeDevices(devices
, max_devices
);
840 VkResult
radv_EnumeratePhysicalDevices(
841 VkInstance _instance
,
842 uint32_t* pPhysicalDeviceCount
,
843 VkPhysicalDevice
* pPhysicalDevices
)
845 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
848 if (instance
->physicalDeviceCount
< 0) {
849 result
= radv_enumerate_devices(instance
);
850 if (result
!= VK_SUCCESS
&&
851 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
855 if (!pPhysicalDevices
) {
856 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
858 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
859 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
860 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
863 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
867 VkResult
radv_EnumeratePhysicalDeviceGroups(
868 VkInstance _instance
,
869 uint32_t* pPhysicalDeviceGroupCount
,
870 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
872 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
875 if (instance
->physicalDeviceCount
< 0) {
876 result
= radv_enumerate_devices(instance
);
877 if (result
!= VK_SUCCESS
&&
878 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
882 if (!pPhysicalDeviceGroupProperties
) {
883 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
885 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
886 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
887 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
888 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
889 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
892 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
896 void radv_GetPhysicalDeviceFeatures(
897 VkPhysicalDevice physicalDevice
,
898 VkPhysicalDeviceFeatures
* pFeatures
)
900 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
901 memset(pFeatures
, 0, sizeof(*pFeatures
));
903 *pFeatures
= (VkPhysicalDeviceFeatures
) {
904 .robustBufferAccess
= true,
905 .fullDrawIndexUint32
= true,
906 .imageCubeArray
= true,
907 .independentBlend
= true,
908 .geometryShader
= true,
909 .tessellationShader
= true,
910 .sampleRateShading
= true,
911 .dualSrcBlend
= true,
913 .multiDrawIndirect
= true,
914 .drawIndirectFirstInstance
= true,
916 .depthBiasClamp
= true,
917 .fillModeNonSolid
= true,
922 .multiViewport
= true,
923 .samplerAnisotropy
= true,
924 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
925 .textureCompressionASTC_LDR
= false,
926 .textureCompressionBC
= true,
927 .occlusionQueryPrecise
= true,
928 .pipelineStatisticsQuery
= true,
929 .vertexPipelineStoresAndAtomics
= true,
930 .fragmentStoresAndAtomics
= true,
931 .shaderTessellationAndGeometryPointSize
= true,
932 .shaderImageGatherExtended
= true,
933 .shaderStorageImageExtendedFormats
= true,
934 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
935 .shaderUniformBufferArrayDynamicIndexing
= true,
936 .shaderSampledImageArrayDynamicIndexing
= true,
937 .shaderStorageBufferArrayDynamicIndexing
= true,
938 .shaderStorageImageArrayDynamicIndexing
= true,
939 .shaderStorageImageReadWithoutFormat
= true,
940 .shaderStorageImageWriteWithoutFormat
= true,
941 .shaderClipDistance
= true,
942 .shaderCullDistance
= true,
943 .shaderFloat64
= true,
945 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
946 .sparseBinding
= true,
947 .variableMultisampleRate
= true,
948 .inheritedQueries
= true,
952 void radv_GetPhysicalDeviceFeatures2(
953 VkPhysicalDevice physicalDevice
,
954 VkPhysicalDeviceFeatures2
*pFeatures
)
956 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
957 vk_foreach_struct(ext
, pFeatures
->pNext
) {
958 switch (ext
->sType
) {
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
960 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
961 features
->variablePointersStorageBuffer
= true;
962 features
->variablePointers
= true;
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
966 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
967 features
->multiview
= true;
968 features
->multiviewGeometryShader
= true;
969 features
->multiviewTessellationShader
= true;
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
973 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
974 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
975 features
->shaderDrawParameters
= true;
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
979 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
980 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
981 features
->protectedMemory
= false;
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
985 VkPhysicalDevice16BitStorageFeatures
*features
=
986 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
987 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
988 features
->storageBuffer16BitAccess
= enabled
;
989 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
990 features
->storagePushConstant16
= enabled
;
991 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
995 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
996 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
997 features
->samplerYcbcrConversion
= true;
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1001 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1002 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1003 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1004 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1005 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1006 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1007 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1008 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1009 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1010 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1011 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1012 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1013 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1014 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1015 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1016 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1017 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1018 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1019 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1020 features
->descriptorBindingPartiallyBound
= true;
1021 features
->descriptorBindingVariableDescriptorCount
= true;
1022 features
->runtimeDescriptorArray
= true;
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1026 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1027 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1028 features
->conditionalRendering
= true;
1029 features
->inheritedConditionalRendering
= false;
1032 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1033 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1034 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1035 features
->vertexAttributeInstanceRateDivisor
= true;
1036 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1040 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1041 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1042 features
->transformFeedback
= true;
1043 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1047 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1048 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1049 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1053 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1054 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1055 features
->memoryPriority
= true;
1058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1059 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1060 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1061 features
->bufferDeviceAddress
= true;
1062 features
->bufferDeviceAddressCaptureReplay
= false;
1063 features
->bufferDeviceAddressMultiDevice
= false;
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1067 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1068 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1069 features
->bufferDeviceAddress
= true;
1070 features
->bufferDeviceAddressCaptureReplay
= false;
1071 features
->bufferDeviceAddressMultiDevice
= false;
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1075 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1076 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1077 features
->depthClipEnable
= true;
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1081 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1082 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1083 features
->hostQueryReset
= true;
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1087 VkPhysicalDevice8BitStorageFeatures
*features
=
1088 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1089 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1090 features
->storageBuffer8BitAccess
= enabled
;
1091 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1092 features
->storagePushConstant8
= enabled
;
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1096 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1097 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1098 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1099 features
->shaderInt8
= !pdevice
->use_aco
;
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1103 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1104 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1105 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1106 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1110 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1111 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1112 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1116 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1117 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1119 features
->inlineUniformBlock
= true;
1120 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1123 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1124 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1125 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1126 features
->computeDerivativeGroupQuads
= false;
1127 features
->computeDerivativeGroupLinear
= true;
1130 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1131 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1132 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1133 features
->ycbcrImageArrays
= true;
1136 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1137 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1138 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1139 features
->uniformBufferStandardLayout
= true;
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1143 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1144 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1145 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1149 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1150 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1151 features
->imagelessFramebuffer
= true;
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1155 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1156 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1157 features
->pipelineExecutableInfo
= true;
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1161 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1162 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1163 features
->shaderSubgroupClock
= true;
1164 features
->shaderDeviceClock
= false;
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1168 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1169 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1170 features
->texelBufferAlignment
= true;
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1174 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1175 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1176 features
->timelineSemaphore
= true;
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1180 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1181 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1182 features
->subgroupSizeControl
= true;
1183 features
->computeFullSubgroups
= true;
1186 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1187 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1188 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1189 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1193 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1194 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1195 features
->shaderSubgroupExtendedTypes
= true;
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1199 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1200 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1201 features
->separateDepthStencilLayouts
= true;
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1205 VkPhysicalDeviceVulkan11Features
*features
=
1206 (VkPhysicalDeviceVulkan11Features
*)ext
;
1207 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1208 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1209 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1210 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1211 features
->multiview
= true;
1212 features
->multiviewGeometryShader
= true;
1213 features
->multiviewTessellationShader
= true;
1214 features
->variablePointersStorageBuffer
= true;
1215 features
->variablePointers
= true;
1216 features
->protectedMemory
= false;
1217 features
->samplerYcbcrConversion
= true;
1218 features
->shaderDrawParameters
= true;
1221 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1222 VkPhysicalDeviceVulkan12Features
*features
=
1223 (VkPhysicalDeviceVulkan12Features
*)ext
;
1224 features
->samplerMirrorClampToEdge
= true;
1225 features
->drawIndirectCount
= true;
1226 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1227 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1228 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1229 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1230 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1231 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1232 features
->shaderInt8
= !pdevice
->use_aco
;
1233 features
->descriptorIndexing
= true;
1234 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1235 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1236 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1237 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1238 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1239 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1240 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1241 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1242 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1243 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1244 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1245 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1246 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1247 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1248 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1249 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1250 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1251 features
->descriptorBindingPartiallyBound
= true;
1252 features
->descriptorBindingVariableDescriptorCount
= true;
1253 features
->runtimeDescriptorArray
= true;
1254 features
->samplerFilterMinmax
= pdevice
->rad_info
.chip_class
>= GFX7
;
1255 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1256 features
->imagelessFramebuffer
= true;
1257 features
->uniformBufferStandardLayout
= true;
1258 features
->shaderSubgroupExtendedTypes
= true;
1259 features
->separateDepthStencilLayouts
= true;
1260 features
->hostQueryReset
= true;
1261 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1262 features
->bufferDeviceAddress
= true;
1263 features
->bufferDeviceAddressCaptureReplay
= false;
1264 features
->bufferDeviceAddressMultiDevice
= false;
1265 features
->vulkanMemoryModel
= false;
1266 features
->vulkanMemoryModelDeviceScope
= false;
1267 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1268 features
->shaderOutputViewportIndex
= true;
1269 features
->shaderOutputLayer
= true;
1270 features
->subgroupBroadcastDynamicId
= true;
1277 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1281 radv_max_descriptor_set_size()
1283 /* make sure that the entire descriptor set is addressable with a signed
1284 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1285 * be at most 2 GiB. the combined image & samples object count as one of
1286 * both. This limit is for the pipeline layout, not for the set layout, but
1287 * there is no set limit, so we just set a pipeline limit. I don't think
1288 * any app is going to hit this soon. */
1289 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1290 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1291 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1292 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1293 32 /* sampler, largest when combined with image */ +
1294 64 /* sampled image */ +
1295 64 /* storage image */);
1298 void radv_GetPhysicalDeviceProperties(
1299 VkPhysicalDevice physicalDevice
,
1300 VkPhysicalDeviceProperties
* pProperties
)
1302 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1303 VkSampleCountFlags sample_counts
= 0xf;
1305 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1307 VkPhysicalDeviceLimits limits
= {
1308 .maxImageDimension1D
= (1 << 14),
1309 .maxImageDimension2D
= (1 << 14),
1310 .maxImageDimension3D
= (1 << 11),
1311 .maxImageDimensionCube
= (1 << 14),
1312 .maxImageArrayLayers
= (1 << 11),
1313 .maxTexelBufferElements
= 128 * 1024 * 1024,
1314 .maxUniformBufferRange
= UINT32_MAX
,
1315 .maxStorageBufferRange
= UINT32_MAX
,
1316 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1317 .maxMemoryAllocationCount
= UINT32_MAX
,
1318 .maxSamplerAllocationCount
= 64 * 1024,
1319 .bufferImageGranularity
= 64, /* A cache line */
1320 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1321 .maxBoundDescriptorSets
= MAX_SETS
,
1322 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1323 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1324 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1325 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1326 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1327 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1328 .maxPerStageResources
= max_descriptor_set_size
,
1329 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1330 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1331 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1332 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1333 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1334 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1335 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1336 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1337 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1338 .maxVertexInputBindings
= MAX_VBS
,
1339 .maxVertexInputAttributeOffset
= 2047,
1340 .maxVertexInputBindingStride
= 2048,
1341 .maxVertexOutputComponents
= 128,
1342 .maxTessellationGenerationLevel
= 64,
1343 .maxTessellationPatchSize
= 32,
1344 .maxTessellationControlPerVertexInputComponents
= 128,
1345 .maxTessellationControlPerVertexOutputComponents
= 128,
1346 .maxTessellationControlPerPatchOutputComponents
= 120,
1347 .maxTessellationControlTotalOutputComponents
= 4096,
1348 .maxTessellationEvaluationInputComponents
= 128,
1349 .maxTessellationEvaluationOutputComponents
= 128,
1350 .maxGeometryShaderInvocations
= 127,
1351 .maxGeometryInputComponents
= 64,
1352 .maxGeometryOutputComponents
= 128,
1353 .maxGeometryOutputVertices
= 256,
1354 .maxGeometryTotalOutputComponents
= 1024,
1355 .maxFragmentInputComponents
= 128,
1356 .maxFragmentOutputAttachments
= 8,
1357 .maxFragmentDualSrcAttachments
= 1,
1358 .maxFragmentCombinedOutputResources
= 8,
1359 .maxComputeSharedMemorySize
= 32768,
1360 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1361 .maxComputeWorkGroupInvocations
= 1024,
1362 .maxComputeWorkGroupSize
= {
1367 .subPixelPrecisionBits
= 8,
1368 .subTexelPrecisionBits
= 8,
1369 .mipmapPrecisionBits
= 8,
1370 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1371 .maxDrawIndirectCount
= UINT32_MAX
,
1372 .maxSamplerLodBias
= 16,
1373 .maxSamplerAnisotropy
= 16,
1374 .maxViewports
= MAX_VIEWPORTS
,
1375 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1376 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1377 .viewportSubPixelBits
= 8,
1378 .minMemoryMapAlignment
= 4096, /* A page */
1379 .minTexelBufferOffsetAlignment
= 4,
1380 .minUniformBufferOffsetAlignment
= 4,
1381 .minStorageBufferOffsetAlignment
= 4,
1382 .minTexelOffset
= -32,
1383 .maxTexelOffset
= 31,
1384 .minTexelGatherOffset
= -32,
1385 .maxTexelGatherOffset
= 31,
1386 .minInterpolationOffset
= -2,
1387 .maxInterpolationOffset
= 2,
1388 .subPixelInterpolationOffsetBits
= 8,
1389 .maxFramebufferWidth
= (1 << 14),
1390 .maxFramebufferHeight
= (1 << 14),
1391 .maxFramebufferLayers
= (1 << 10),
1392 .framebufferColorSampleCounts
= sample_counts
,
1393 .framebufferDepthSampleCounts
= sample_counts
,
1394 .framebufferStencilSampleCounts
= sample_counts
,
1395 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1396 .maxColorAttachments
= MAX_RTS
,
1397 .sampledImageColorSampleCounts
= sample_counts
,
1398 .sampledImageIntegerSampleCounts
= sample_counts
,
1399 .sampledImageDepthSampleCounts
= sample_counts
,
1400 .sampledImageStencilSampleCounts
= sample_counts
,
1401 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1402 .maxSampleMaskWords
= 1,
1403 .timestampComputeAndGraphics
= true,
1404 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1405 .maxClipDistances
= 8,
1406 .maxCullDistances
= 8,
1407 .maxCombinedClipAndCullDistances
= 8,
1408 .discreteQueuePriorities
= 2,
1409 .pointSizeRange
= { 0.0, 8192.0 },
1410 .lineWidthRange
= { 0.0, 7.9921875 },
1411 .pointSizeGranularity
= (1.0 / 8.0),
1412 .lineWidthGranularity
= (1.0 / 128.0),
1413 .strictLines
= false, /* FINISHME */
1414 .standardSampleLocations
= true,
1415 .optimalBufferCopyOffsetAlignment
= 128,
1416 .optimalBufferCopyRowPitchAlignment
= 128,
1417 .nonCoherentAtomSize
= 64,
1420 *pProperties
= (VkPhysicalDeviceProperties
) {
1421 .apiVersion
= radv_physical_device_api_version(pdevice
),
1422 .driverVersion
= vk_get_driver_version(),
1423 .vendorID
= ATI_VENDOR_ID
,
1424 .deviceID
= pdevice
->rad_info
.pci_id
,
1425 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1427 .sparseProperties
= {0},
1430 strcpy(pProperties
->deviceName
, pdevice
->name
);
1431 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1435 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1436 VkPhysicalDeviceVulkan11Properties
*p
)
1438 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1440 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1441 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1442 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1443 /* The LUID is for Windows. */
1444 p
->deviceLUIDValid
= false;
1445 p
->deviceNodeMask
= 0;
1447 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1448 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1449 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1450 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1451 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1452 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1453 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1454 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1456 if (pdevice
->rad_info
.chip_class
== GFX8
||
1457 pdevice
->rad_info
.chip_class
== GFX9
) {
1458 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1459 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1461 p
->subgroupQuadOperationsInAllStages
= true;
1463 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1464 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1465 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1466 p
->protectedNoFault
= false;
1467 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1468 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1472 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1473 VkPhysicalDeviceVulkan12Properties
*p
)
1475 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1477 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1478 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1479 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1480 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1481 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1482 p
->conformanceVersion
= (VkConformanceVersion
) {
1489 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1490 * controlled by the same config register.
1492 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1493 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1495 /* Do not allow both preserving and flushing denorms because different
1496 * shaders in the same pipeline can have different settings and this
1497 * won't work for merged shaders. To make it work, this requires LLVM
1498 * support for changing the register. The same logic applies for the
1499 * rounding modes because they are configured with the same config
1500 * register. TODO: we can enable a lot of these for ACO when it
1501 * supports all stages.
1503 p
->shaderDenormFlushToZeroFloat32
= true;
1504 p
->shaderDenormPreserveFloat32
= false;
1505 p
->shaderRoundingModeRTEFloat32
= true;
1506 p
->shaderRoundingModeRTZFloat32
= false;
1507 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1509 p
->shaderDenormFlushToZeroFloat16
= false;
1510 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1511 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1512 p
->shaderRoundingModeRTZFloat16
= false;
1513 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1515 p
->shaderDenormFlushToZeroFloat64
= false;
1516 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1517 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1518 p
->shaderRoundingModeRTZFloat64
= false;
1519 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1521 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1522 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1523 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1524 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1525 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1526 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1527 p
->robustBufferAccessUpdateAfterBind
= false;
1528 p
->quadDivergentImplicitLod
= false;
1530 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1531 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1532 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1533 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1534 32 /* sampler, largest when combined with image */ +
1535 64 /* sampled image */ +
1536 64 /* storage image */);
1537 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1538 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1539 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1540 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1541 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1542 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1543 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1544 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1545 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1546 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1547 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1548 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1549 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1550 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1551 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1553 /* We support all of the depth resolve modes */
1554 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1555 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1556 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1557 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1559 /* Average doesn't make sense for stencil so we don't support that */
1560 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1561 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1562 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1564 p
->independentResolveNone
= true;
1565 p
->independentResolve
= true;
1567 /* GFX6-8 only support single channel min/max filter. */
1568 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1569 p
->filterMinmaxSingleComponentFormats
= true;
1571 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1573 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1576 void radv_GetPhysicalDeviceProperties2(
1577 VkPhysicalDevice physicalDevice
,
1578 VkPhysicalDeviceProperties2
*pProperties
)
1580 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1581 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1583 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1584 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1586 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1588 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1589 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1591 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1593 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1594 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1595 sizeof(core_##major##_##minor.core_property))
1597 #define CORE_PROPERTY(major, minor, property) \
1598 CORE_RENAMED_PROPERTY(major, minor, property, property)
1600 vk_foreach_struct(ext
, pProperties
->pNext
) {
1601 switch (ext
->sType
) {
1602 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1603 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1604 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1605 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1608 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1609 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1610 CORE_PROPERTY(1, 1, deviceUUID
);
1611 CORE_PROPERTY(1, 1, driverUUID
);
1612 CORE_PROPERTY(1, 1, deviceLUID
);
1613 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1616 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1617 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1618 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1619 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1622 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1623 VkPhysicalDevicePointClippingProperties
*properties
=
1624 (VkPhysicalDevicePointClippingProperties
*)ext
;
1625 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1628 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1629 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1630 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1631 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1634 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1635 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1636 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1637 properties
->minImportedHostPointerAlignment
= 4096;
1640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1641 VkPhysicalDeviceSubgroupProperties
*properties
=
1642 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1643 CORE_PROPERTY(1, 1, subgroupSize
);
1644 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1645 subgroupSupportedStages
);
1646 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1647 subgroupSupportedOperations
);
1648 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1649 subgroupQuadOperationsInAllStages
);
1652 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1653 VkPhysicalDeviceMaintenance3Properties
*properties
=
1654 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1655 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1656 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1659 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1660 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1661 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1662 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1663 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1666 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1667 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1668 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1670 /* Shader engines. */
1671 properties
->shaderEngineCount
=
1672 pdevice
->rad_info
.max_se
;
1673 properties
->shaderArraysPerEngineCount
=
1674 pdevice
->rad_info
.max_sh_per_se
;
1675 properties
->computeUnitsPerShaderArray
=
1676 pdevice
->rad_info
.num_good_cu_per_sh
;
1677 properties
->simdPerComputeUnit
= 4;
1678 properties
->wavefrontsPerSimd
=
1679 pdevice
->rad_info
.family
== CHIP_TONGA
||
1680 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1681 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1682 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1683 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1684 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1685 properties
->wavefrontSize
= 64;
1688 properties
->sgprsPerSimd
=
1689 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1690 properties
->minSgprAllocation
=
1691 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1692 properties
->maxSgprAllocation
=
1693 pdevice
->rad_info
.family
== CHIP_TONGA
||
1694 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1695 properties
->sgprAllocationGranularity
=
1696 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1699 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1700 properties
->minVgprAllocation
= 4;
1701 properties
->maxVgprAllocation
= 256;
1702 properties
->vgprAllocationGranularity
= 4;
1705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1706 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1707 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1709 properties
->shaderCoreFeatures
= 0;
1710 properties
->activeComputeUnitCount
=
1711 pdevice
->rad_info
.num_good_compute_units
;
1714 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1715 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1716 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1717 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1720 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1721 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1722 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1723 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1724 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1725 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1726 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1727 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1728 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1729 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1730 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1731 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1732 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1733 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1734 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1735 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1736 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1737 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1738 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1739 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1740 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1741 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1742 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1743 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1744 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1745 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1749 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1750 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1751 CORE_PROPERTY(1, 1, protectedNoFault
);
1754 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1755 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1756 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1757 properties
->primitiveOverestimationSize
= 0;
1758 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1759 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1760 properties
->primitiveUnderestimation
= false;
1761 properties
->conservativePointAndLineRasterization
= false;
1762 properties
->degenerateTrianglesRasterized
= false;
1763 properties
->degenerateLinesRasterized
= false;
1764 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1765 properties
->conservativeRasterizationPostDepthCoverage
= false;
1768 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1769 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1770 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1771 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1772 properties
->pciBus
= pdevice
->bus_info
.bus
;
1773 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1774 properties
->pciFunction
= pdevice
->bus_info
.func
;
1777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1778 VkPhysicalDeviceDriverProperties
*properties
=
1779 (VkPhysicalDeviceDriverProperties
*) ext
;
1780 CORE_PROPERTY(1, 2, driverID
);
1781 CORE_PROPERTY(1, 2, driverName
);
1782 CORE_PROPERTY(1, 2, driverInfo
);
1783 CORE_PROPERTY(1, 2, conformanceVersion
);
1786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1787 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1788 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1789 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1790 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1791 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1792 properties
->maxTransformFeedbackStreamDataSize
= 512;
1793 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1794 properties
->maxTransformFeedbackBufferDataStride
= 512;
1795 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1796 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1797 properties
->transformFeedbackRasterizationStreamSelect
= false;
1798 properties
->transformFeedbackDraw
= true;
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1802 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1803 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1805 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1806 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1807 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1808 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1809 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1813 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1814 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1815 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1816 VK_SAMPLE_COUNT_4_BIT
|
1817 VK_SAMPLE_COUNT_8_BIT
;
1818 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1819 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1820 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1821 properties
->sampleLocationSubPixelBits
= 4;
1822 properties
->variableSampleLocations
= false;
1825 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1826 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1827 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1828 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1829 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1830 CORE_PROPERTY(1, 2, independentResolveNone
);
1831 CORE_PROPERTY(1, 2, independentResolve
);
1834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1835 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1836 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1837 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1838 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1839 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1840 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1844 VkPhysicalDeviceFloatControlsProperties
*properties
=
1845 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1846 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1847 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1848 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1849 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1850 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1851 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1852 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1853 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1854 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1855 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1856 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1857 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1858 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1859 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1860 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1861 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1862 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1866 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1867 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1868 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1872 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1873 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1874 props
->minSubgroupSize
= 64;
1875 props
->maxSubgroupSize
= 64;
1876 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1877 props
->requiredSubgroupSizeStages
= 0;
1879 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1880 /* Only GFX10+ supports wave32. */
1881 props
->minSubgroupSize
= 32;
1882 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1887 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1890 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1898 static void radv_get_physical_device_queue_family_properties(
1899 struct radv_physical_device
* pdevice
,
1901 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1903 int num_queue_families
= 1;
1905 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1906 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1907 num_queue_families
++;
1909 if (pQueueFamilyProperties
== NULL
) {
1910 *pCount
= num_queue_families
;
1919 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1920 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1921 VK_QUEUE_COMPUTE_BIT
|
1922 VK_QUEUE_TRANSFER_BIT
|
1923 VK_QUEUE_SPARSE_BINDING_BIT
,
1925 .timestampValidBits
= 64,
1926 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1931 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1932 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1933 if (*pCount
> idx
) {
1934 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1935 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1936 VK_QUEUE_TRANSFER_BIT
|
1937 VK_QUEUE_SPARSE_BINDING_BIT
,
1938 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1939 .timestampValidBits
= 64,
1940 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1948 void radv_GetPhysicalDeviceQueueFamilyProperties(
1949 VkPhysicalDevice physicalDevice
,
1951 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1953 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1954 if (!pQueueFamilyProperties
) {
1955 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1958 VkQueueFamilyProperties
*properties
[] = {
1959 pQueueFamilyProperties
+ 0,
1960 pQueueFamilyProperties
+ 1,
1961 pQueueFamilyProperties
+ 2,
1963 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1964 assert(*pCount
<= 3);
1967 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1968 VkPhysicalDevice physicalDevice
,
1970 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1972 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1973 if (!pQueueFamilyProperties
) {
1974 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1977 VkQueueFamilyProperties
*properties
[] = {
1978 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1979 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1980 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1982 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1983 assert(*pCount
<= 3);
1986 void radv_GetPhysicalDeviceMemoryProperties(
1987 VkPhysicalDevice physicalDevice
,
1988 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1990 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1992 *pMemoryProperties
= physical_device
->memory_properties
;
1996 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1997 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1999 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2000 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2001 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2002 uint64_t vram_size
= radv_get_vram_size(device
);
2003 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2004 uint64_t heap_budget
, heap_usage
;
2006 /* For all memory heaps, the computation of budget is as follow:
2007 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2009 * The Vulkan spec 1.1.97 says that the budget should include any
2010 * currently allocated device memory.
2012 * Note that the application heap usages are not really accurate (eg.
2013 * in presence of shared buffers).
2015 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2016 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2018 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2019 heap_usage
= device
->ws
->query_value(device
->ws
,
2020 RADEON_ALLOCATED_VRAM
);
2022 heap_budget
= vram_size
-
2023 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2026 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2027 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2028 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2029 heap_usage
= device
->ws
->query_value(device
->ws
,
2030 RADEON_ALLOCATED_VRAM_VIS
);
2032 heap_budget
= visible_vram_size
-
2033 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2036 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2037 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2038 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2039 heap_usage
= device
->ws
->query_value(device
->ws
,
2040 RADEON_ALLOCATED_GTT
);
2042 heap_budget
= gtt_size
-
2043 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2046 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2047 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2051 /* The heapBudget and heapUsage values must be zero for array elements
2052 * greater than or equal to
2053 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2055 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2056 memoryBudget
->heapBudget
[i
] = 0;
2057 memoryBudget
->heapUsage
[i
] = 0;
2061 void radv_GetPhysicalDeviceMemoryProperties2(
2062 VkPhysicalDevice physicalDevice
,
2063 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2065 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2066 &pMemoryProperties
->memoryProperties
);
2068 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2069 vk_find_struct(pMemoryProperties
->pNext
,
2070 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2072 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2075 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2077 VkExternalMemoryHandleTypeFlagBits handleType
,
2078 const void *pHostPointer
,
2079 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2081 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2085 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2086 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2087 uint32_t memoryTypeBits
= 0;
2088 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2089 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2090 memoryTypeBits
= (1 << i
);
2094 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2098 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2102 static enum radeon_ctx_priority
2103 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2105 /* Default to MEDIUM when a specific global priority isn't requested */
2107 return RADEON_CTX_PRIORITY_MEDIUM
;
2109 switch(pObj
->globalPriority
) {
2110 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2111 return RADEON_CTX_PRIORITY_REALTIME
;
2112 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2113 return RADEON_CTX_PRIORITY_HIGH
;
2114 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2115 return RADEON_CTX_PRIORITY_MEDIUM
;
2116 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2117 return RADEON_CTX_PRIORITY_LOW
;
2119 unreachable("Illegal global priority value");
2120 return RADEON_CTX_PRIORITY_INVALID
;
2125 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2126 uint32_t queue_family_index
, int idx
,
2127 VkDeviceQueueCreateFlags flags
,
2128 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2130 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2131 queue
->device
= device
;
2132 queue
->queue_family_index
= queue_family_index
;
2133 queue
->queue_idx
= idx
;
2134 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2135 queue
->flags
= flags
;
2137 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2139 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2141 list_inithead(&queue
->pending_submissions
);
2142 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2148 radv_queue_finish(struct radv_queue
*queue
)
2150 pthread_mutex_destroy(&queue
->pending_mutex
);
2153 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2155 if (queue
->initial_full_flush_preamble_cs
)
2156 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2157 if (queue
->initial_preamble_cs
)
2158 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2159 if (queue
->continue_preamble_cs
)
2160 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2161 if (queue
->descriptor_bo
)
2162 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2163 if (queue
->scratch_bo
)
2164 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2165 if (queue
->esgs_ring_bo
)
2166 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2167 if (queue
->gsvs_ring_bo
)
2168 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2169 if (queue
->tess_rings_bo
)
2170 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2172 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2173 if (queue
->gds_oa_bo
)
2174 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2175 if (queue
->compute_scratch_bo
)
2176 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2180 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2182 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2183 bo_list
->list
.count
= bo_list
->capacity
= 0;
2184 bo_list
->list
.bos
= NULL
;
2188 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2190 free(bo_list
->list
.bos
);
2191 pthread_mutex_destroy(&bo_list
->mutex
);
2194 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2195 struct radeon_winsys_bo
*bo
)
2197 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2202 if (unlikely(!device
->use_global_bo_list
))
2205 pthread_mutex_lock(&bo_list
->mutex
);
2206 if (bo_list
->list
.count
== bo_list
->capacity
) {
2207 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2208 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2211 pthread_mutex_unlock(&bo_list
->mutex
);
2212 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2215 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2216 bo_list
->capacity
= capacity
;
2219 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2220 pthread_mutex_unlock(&bo_list
->mutex
);
2224 static void radv_bo_list_remove(struct radv_device
*device
,
2225 struct radeon_winsys_bo
*bo
)
2227 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2232 if (unlikely(!device
->use_global_bo_list
))
2235 pthread_mutex_lock(&bo_list
->mutex
);
2236 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2237 if (bo_list
->list
.bos
[i
] == bo
) {
2238 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2239 --bo_list
->list
.count
;
2243 pthread_mutex_unlock(&bo_list
->mutex
);
2247 radv_device_init_gs_info(struct radv_device
*device
)
2249 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2250 device
->physical_device
->rad_info
.family
);
2253 static int radv_get_device_extension_index(const char *name
)
2255 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2256 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2263 radv_get_int_debug_option(const char *name
, int default_value
)
2270 result
= default_value
;
2274 result
= strtol(str
, &endptr
, 0);
2275 if (str
== endptr
) {
2276 /* No digits founs. */
2277 result
= default_value
;
2284 static int install_seccomp_filter() {
2286 struct sock_filter filter
[] = {
2287 /* Check arch is 64bit x86 */
2288 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2289 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2291 /* Futex is required for mutex locks */
2292 #if defined __NR__newselect
2293 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2294 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2295 #elif defined __NR_select
2296 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2297 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2299 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2300 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2303 /* Allow system exit calls for the forked process */
2304 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2305 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2307 /* Allow system read calls */
2308 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2309 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2311 /* Allow system write calls */
2312 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2313 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2315 /* Allow system brk calls (we need this for malloc) */
2316 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2317 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2319 /* Futex is required for mutex locks */
2320 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2321 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2323 /* Return error if we hit a system call not on the whitelist */
2324 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2326 /* Allow whitelisted system calls */
2327 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2330 struct sock_fprog prog
= {
2331 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2335 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2338 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2344 /* Helper function with timeout support for reading from the pipe between
2345 * processes used for secure compile.
2347 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2356 /* We can't rely on the value of tv after calling select() so
2357 * we must reset it on each iteration of the loop.
2362 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2368 ssize_t bytes_read
= read(fd
, buf
, size
);
2377 /* select timeout */
2383 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2387 d
= opendir("/proc/self/fd");
2390 int dir_fd
= dirfd(d
);
2392 while ((dir
= readdir(d
)) != NULL
) {
2393 if (dir
->d_name
[0] == '.')
2396 int fd
= atoi(dir
->d_name
);
2401 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2402 if (keep_fds
[i
] == fd
)
2414 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2415 int *fd_server
, int *fd_client
,
2416 unsigned process
, bool make_fifo
)
2418 bool result
= false;
2419 char *fifo_server_path
= NULL
;
2420 char *fifo_client_path
= NULL
;
2422 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2423 goto open_fifo_exit
;
2425 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2426 goto open_fifo_exit
;
2429 int file1
= mkfifo(fifo_server_path
, 0666);
2431 goto open_fifo_exit
;
2433 int file2
= mkfifo(fifo_client_path
, 0666);
2435 goto open_fifo_exit
;
2438 *fd_server
= open(fifo_server_path
, O_RDWR
);
2440 goto open_fifo_exit
;
2442 *fd_client
= open(fifo_client_path
, O_RDWR
);
2443 if(*fd_client
< 1) {
2445 goto open_fifo_exit
;
2451 free(fifo_server_path
);
2452 free(fifo_client_path
);
2457 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2458 int fd_idle_device_output
)
2460 int fd_secure_input
;
2461 int fd_secure_output
;
2462 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2467 enum radv_secure_compile_type sc_type
;
2469 const int needed_fds
[] = {
2472 fd_idle_device_output
,
2475 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2476 install_seccomp_filter() == -1) {
2477 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2479 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2480 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2481 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2484 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2486 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2487 goto secure_compile_exit
;
2490 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2492 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2493 struct radv_pipeline
*pipeline
;
2494 bool sc_read
= true;
2496 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2497 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2499 pipeline
->device
= device
;
2501 /* Read pipeline layout */
2502 struct radv_pipeline_layout layout
;
2503 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2504 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2506 goto secure_compile_exit
;
2508 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2509 uint32_t layout_size
;
2510 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2512 goto secure_compile_exit
;
2514 layout
.set
[set
].layout
= malloc(layout_size
);
2515 layout
.set
[set
].layout
->layout_size
= layout_size
;
2516 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2517 layout
.set
[set
].layout
->layout_size
, true);
2520 pipeline
->layout
= &layout
;
2522 /* Read pipeline key */
2523 struct radv_pipeline_key key
;
2524 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2526 /* Read pipeline create flags */
2527 VkPipelineCreateFlags flags
;
2528 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2530 /* Read stage and shader information */
2531 uint32_t num_stages
;
2532 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2533 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2535 goto secure_compile_exit
;
2537 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2540 gl_shader_stage stage
;
2541 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2543 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2545 /* Read entry point name */
2547 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2549 goto secure_compile_exit
;
2551 char *ep_name
= malloc(name_size
);
2552 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2553 pStage
->pName
= ep_name
;
2555 /* Read shader module */
2557 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2559 goto secure_compile_exit
;
2561 struct radv_shader_module
*module
= malloc(module_size
);
2562 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2563 pStage
->module
= radv_shader_module_to_handle(module
);
2565 /* Read specialization info */
2567 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2569 goto secure_compile_exit
;
2571 if (has_spec_info
) {
2572 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2573 pStage
->pSpecializationInfo
= specInfo
;
2575 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2577 goto secure_compile_exit
;
2579 void *si_data
= malloc(specInfo
->dataSize
);
2580 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2581 specInfo
->pData
= si_data
;
2583 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2585 goto secure_compile_exit
;
2587 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2588 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2589 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2591 goto secure_compile_exit
;
2594 specInfo
->pMapEntries
= mapEntries
;
2597 pStages
[stage
] = pStage
;
2600 /* Compile the shaders */
2601 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2602 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2604 /* free memory allocated above */
2605 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2606 free(layout
.set
[set
].layout
);
2608 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2612 free((void *) pStages
[i
]->pName
);
2613 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2614 if (pStages
[i
]->pSpecializationInfo
) {
2615 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2616 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2617 free((void *) pStages
[i
]->pSpecializationInfo
);
2619 free((void *) pStages
[i
]);
2622 vk_free(&device
->alloc
, pipeline
);
2624 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2625 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2627 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2628 goto secure_compile_exit
;
2632 secure_compile_exit
:
2633 close(fd_secure_input
);
2634 close(fd_secure_output
);
2635 close(fd_idle_device_output
);
2639 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2641 int fd_secure_input
[2];
2642 int fd_secure_output
[2];
2644 /* create pipe descriptors (used to communicate between processes) */
2645 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2646 return RADV_SC_TYPE_INIT_FAILURE
;
2650 if ((sc_pid
= fork()) == 0) {
2651 device
->sc_state
->secure_compile_thread_counter
= process
;
2652 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2655 return RADV_SC_TYPE_INIT_FAILURE
;
2657 /* Read the init result returned from the secure process */
2658 enum radv_secure_compile_type sc_type
;
2659 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2661 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2662 close(fd_secure_input
[0]);
2663 close(fd_secure_input
[1]);
2664 close(fd_secure_output
[1]);
2665 close(fd_secure_output
[0]);
2667 waitpid(sc_pid
, &status
, 0);
2669 return RADV_SC_TYPE_INIT_FAILURE
;
2671 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2672 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2674 close(fd_secure_input
[0]);
2675 close(fd_secure_input
[1]);
2676 close(fd_secure_output
[1]);
2677 close(fd_secure_output
[0]);
2680 waitpid(sc_pid
, &status
, 0);
2684 return RADV_SC_TYPE_INIT_SUCCESS
;
2687 /* Run a bare bones fork of a device that was forked right after its creation.
2688 * This device will have low overhead when it is forked again before each
2689 * pipeline compilation. This device sits idle and its only job is to fork
2692 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2693 int fd_secure_input
, int fd_secure_output
)
2695 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2696 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2697 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2699 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2702 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2704 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2705 sc_type
= fork_secure_compile_device(device
, process
);
2707 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2708 goto secure_compile_exit
;
2710 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2711 goto secure_compile_exit
;
2715 secure_compile_exit
:
2716 close(fd_secure_input
);
2717 close(fd_secure_output
);
2721 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2723 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2725 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2726 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2728 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2729 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2732 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2735 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2737 device
->sc_state
= vk_zalloc(&device
->alloc
,
2738 sizeof(struct radv_secure_compile_state
),
2739 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2741 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2743 pid_t upid
= getpid();
2744 time_t seconds
= time(NULL
);
2747 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2748 return VK_ERROR_INITIALIZATION_FAILED
;
2750 device
->sc_state
->uid
= uid
;
2752 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2753 int fd_secure_input
[MAX_SC_PROCS
][2];
2754 int fd_secure_output
[MAX_SC_PROCS
][2];
2756 /* create pipe descriptors (used to communicate between processes) */
2757 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2758 if (pipe(fd_secure_input
[i
]) == -1 ||
2759 pipe(fd_secure_output
[i
]) == -1) {
2760 return VK_ERROR_INITIALIZATION_FAILED
;
2764 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2765 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2766 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2768 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2769 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2770 device
->sc_state
->secure_compile_thread_counter
= process
;
2771 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2773 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2774 return VK_ERROR_INITIALIZATION_FAILED
;
2776 /* Read the init result returned from the secure process */
2777 enum radv_secure_compile_type sc_type
;
2778 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2781 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2782 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2783 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2784 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2787 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2788 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2791 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2792 close(fd_secure_input
[process
][0]);
2793 close(fd_secure_input
[process
][1]);
2794 close(fd_secure_output
[process
][1]);
2795 close(fd_secure_output
[process
][0]);
2797 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2799 /* Destroy any forks that were created sucessfully */
2800 for (unsigned i
= 0; i
< process
; i
++) {
2801 destroy_secure_compile_device(device
, i
);
2804 return VK_ERROR_INITIALIZATION_FAILED
;
2812 radv_create_pthread_cond(pthread_cond_t
*cond
)
2814 pthread_condattr_t condattr
;
2815 if (pthread_condattr_init(&condattr
)) {
2816 return VK_ERROR_INITIALIZATION_FAILED
;
2819 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2820 pthread_condattr_destroy(&condattr
);
2821 return VK_ERROR_INITIALIZATION_FAILED
;
2823 if (pthread_cond_init(cond
, &condattr
)) {
2824 pthread_condattr_destroy(&condattr
);
2825 return VK_ERROR_INITIALIZATION_FAILED
;
2827 pthread_condattr_destroy(&condattr
);
2831 VkResult
radv_CreateDevice(
2832 VkPhysicalDevice physicalDevice
,
2833 const VkDeviceCreateInfo
* pCreateInfo
,
2834 const VkAllocationCallbacks
* pAllocator
,
2837 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2839 struct radv_device
*device
;
2841 bool keep_shader_info
= false;
2843 /* Check enabled features */
2844 if (pCreateInfo
->pEnabledFeatures
) {
2845 VkPhysicalDeviceFeatures supported_features
;
2846 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2847 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2848 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2849 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2850 for (uint32_t i
= 0; i
< num_features
; i
++) {
2851 if (enabled_feature
[i
] && !supported_feature
[i
])
2852 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2856 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2858 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2860 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2862 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2863 device
->instance
= physical_device
->instance
;
2864 device
->physical_device
= physical_device
;
2866 device
->ws
= physical_device
->ws
;
2868 device
->alloc
= *pAllocator
;
2870 device
->alloc
= physical_device
->instance
->alloc
;
2872 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2873 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2874 int index
= radv_get_device_extension_index(ext_name
);
2875 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2876 vk_free(&device
->alloc
, device
);
2877 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2880 device
->enabled_extensions
.extensions
[index
] = true;
2883 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2885 /* With update after bind we can't attach bo's to the command buffer
2886 * from the descriptor set anymore, so we have to use a global BO list.
2888 device
->use_global_bo_list
=
2889 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2890 device
->enabled_extensions
.EXT_descriptor_indexing
||
2891 device
->enabled_extensions
.EXT_buffer_device_address
||
2892 device
->enabled_extensions
.KHR_buffer_device_address
;
2894 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2895 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2897 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2898 list_inithead(&device
->shader_slabs
);
2900 radv_bo_list_init(&device
->bo_list
);
2902 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2903 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2904 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2905 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2906 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2908 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2910 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2911 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2912 if (!device
->queues
[qfi
]) {
2913 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2917 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2919 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2921 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2922 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2923 qfi
, q
, queue_create
->flags
,
2925 if (result
!= VK_SUCCESS
)
2930 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2931 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2933 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2934 device
->dfsm_allowed
= device
->pbb_allowed
&&
2935 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2937 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2939 /* The maximum number of scratch waves. Scratch space isn't divided
2940 * evenly between CUs. The number is only a function of the number of CUs.
2941 * We can decrease the constant to decrease the scratch buffer size.
2943 * sctx->scratch_waves must be >= the maximum possible size of
2944 * 1 threadgroup, so that the hw doesn't hang from being unable
2947 * The recommended value is 4 per CU at most. Higher numbers don't
2948 * bring much benefit, but they still occupy chip resources (think
2949 * async compute). I've seen ~2% performance difference between 4 and 32.
2951 uint32_t max_threads_per_block
= 2048;
2952 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2953 max_threads_per_block
/ 64);
2955 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2957 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2958 /* If the KMD allows it (there is a KMD hw register for it),
2959 * allow launching waves out-of-order.
2961 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2964 radv_device_init_gs_info(device
);
2966 device
->tess_offchip_block_dw_size
=
2967 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2969 if (getenv("RADV_TRACE_FILE")) {
2970 const char *filename
= getenv("RADV_TRACE_FILE");
2972 keep_shader_info
= true;
2974 if (!radv_init_trace(device
))
2977 fprintf(stderr
, "*****************************************************************************\n");
2978 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2979 fprintf(stderr
, "*****************************************************************************\n");
2981 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2982 radv_dump_enabled_options(device
, stderr
);
2985 /* Temporarily disable secure compile while we create meta shaders, etc */
2986 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2988 device
->instance
->num_sc_threads
= 0;
2990 device
->keep_shader_info
= keep_shader_info
;
2991 result
= radv_device_init_meta(device
);
2992 if (result
!= VK_SUCCESS
)
2995 radv_device_init_msaa(device
);
2997 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2998 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3000 case RADV_QUEUE_GENERAL
:
3001 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3002 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3003 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3005 case RADV_QUEUE_COMPUTE
:
3006 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3007 radeon_emit(device
->empty_cs
[family
], 0);
3010 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3013 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3014 cik_create_gfx_config(device
);
3016 VkPipelineCacheCreateInfo ci
;
3017 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3020 ci
.pInitialData
= NULL
;
3021 ci
.initialDataSize
= 0;
3023 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3025 if (result
!= VK_SUCCESS
)
3028 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3030 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3031 if (result
!= VK_SUCCESS
)
3032 goto fail_mem_cache
;
3034 device
->force_aniso
=
3035 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3036 if (device
->force_aniso
>= 0) {
3037 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3038 1 << util_logbase2(device
->force_aniso
));
3041 /* Fork device for secure compile as required */
3042 device
->instance
->num_sc_threads
= sc_threads
;
3043 if (radv_device_use_secure_compile(device
->instance
)) {
3045 result
= fork_secure_compile_idle_device(device
);
3046 if (result
!= VK_SUCCESS
)
3050 *pDevice
= radv_device_to_handle(device
);
3054 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3056 radv_device_finish_meta(device
);
3058 radv_bo_list_finish(&device
->bo_list
);
3060 if (device
->trace_bo
)
3061 device
->ws
->buffer_destroy(device
->trace_bo
);
3063 if (device
->gfx_init
)
3064 device
->ws
->buffer_destroy(device
->gfx_init
);
3066 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3067 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3068 radv_queue_finish(&device
->queues
[i
][q
]);
3069 if (device
->queue_count
[i
])
3070 vk_free(&device
->alloc
, device
->queues
[i
]);
3073 vk_free(&device
->alloc
, device
);
3077 void radv_DestroyDevice(
3079 const VkAllocationCallbacks
* pAllocator
)
3081 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3086 if (device
->trace_bo
)
3087 device
->ws
->buffer_destroy(device
->trace_bo
);
3089 if (device
->gfx_init
)
3090 device
->ws
->buffer_destroy(device
->gfx_init
);
3092 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3093 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3094 radv_queue_finish(&device
->queues
[i
][q
]);
3095 if (device
->queue_count
[i
])
3096 vk_free(&device
->alloc
, device
->queues
[i
]);
3097 if (device
->empty_cs
[i
])
3098 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3100 radv_device_finish_meta(device
);
3102 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3103 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3105 radv_destroy_shader_slabs(device
);
3107 pthread_cond_destroy(&device
->timeline_cond
);
3108 radv_bo_list_finish(&device
->bo_list
);
3109 if (radv_device_use_secure_compile(device
->instance
)) {
3110 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3111 destroy_secure_compile_device(device
, i
);
3115 if (device
->sc_state
) {
3116 free(device
->sc_state
->uid
);
3117 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3119 vk_free(&device
->alloc
, device
->sc_state
);
3120 vk_free(&device
->alloc
, device
);
3123 VkResult
radv_EnumerateInstanceLayerProperties(
3124 uint32_t* pPropertyCount
,
3125 VkLayerProperties
* pProperties
)
3127 if (pProperties
== NULL
) {
3128 *pPropertyCount
= 0;
3132 /* None supported at this time */
3133 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3136 VkResult
radv_EnumerateDeviceLayerProperties(
3137 VkPhysicalDevice physicalDevice
,
3138 uint32_t* pPropertyCount
,
3139 VkLayerProperties
* pProperties
)
3141 if (pProperties
== NULL
) {
3142 *pPropertyCount
= 0;
3146 /* None supported at this time */
3147 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3150 void radv_GetDeviceQueue2(
3152 const VkDeviceQueueInfo2
* pQueueInfo
,
3155 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3156 struct radv_queue
*queue
;
3158 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3159 if (pQueueInfo
->flags
!= queue
->flags
) {
3160 /* From the Vulkan 1.1.70 spec:
3162 * "The queue returned by vkGetDeviceQueue2 must have the same
3163 * flags value from this structure as that used at device
3164 * creation time in a VkDeviceQueueCreateInfo instance. If no
3165 * matching flags were specified at device creation time then
3166 * pQueue will return VK_NULL_HANDLE."
3168 *pQueue
= VK_NULL_HANDLE
;
3172 *pQueue
= radv_queue_to_handle(queue
);
3175 void radv_GetDeviceQueue(
3177 uint32_t queueFamilyIndex
,
3178 uint32_t queueIndex
,
3181 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3182 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3183 .queueFamilyIndex
= queueFamilyIndex
,
3184 .queueIndex
= queueIndex
3187 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3191 fill_geom_tess_rings(struct radv_queue
*queue
,
3193 bool add_sample_positions
,
3194 uint32_t esgs_ring_size
,
3195 struct radeon_winsys_bo
*esgs_ring_bo
,
3196 uint32_t gsvs_ring_size
,
3197 struct radeon_winsys_bo
*gsvs_ring_bo
,
3198 uint32_t tess_factor_ring_size
,
3199 uint32_t tess_offchip_ring_offset
,
3200 uint32_t tess_offchip_ring_size
,
3201 struct radeon_winsys_bo
*tess_rings_bo
)
3203 uint32_t *desc
= &map
[4];
3206 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3208 /* stride 0, num records - size, add tid, swizzle, elsize4,
3211 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3212 S_008F04_SWIZZLE_ENABLE(true);
3213 desc
[2] = esgs_ring_size
;
3214 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3215 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3216 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3217 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3218 S_008F0C_INDEX_STRIDE(3) |
3219 S_008F0C_ADD_TID_ENABLE(1);
3221 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3222 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3223 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3224 S_008F0C_RESOURCE_LEVEL(1);
3226 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3227 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3228 S_008F0C_ELEMENT_SIZE(1);
3231 /* GS entry for ES->GS ring */
3232 /* stride 0, num records - size, elsize0,
3235 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3236 desc
[6] = esgs_ring_size
;
3237 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3238 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3239 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3240 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3242 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3243 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3244 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3245 S_008F0C_RESOURCE_LEVEL(1);
3247 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3248 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3255 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3257 /* VS entry for GS->VS ring */
3258 /* stride 0, num records - size, elsize0,
3261 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3262 desc
[2] = gsvs_ring_size
;
3263 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3264 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3265 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3266 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3268 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3269 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3270 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3271 S_008F0C_RESOURCE_LEVEL(1);
3273 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3274 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3277 /* stride gsvs_itemsize, num records 64
3278 elsize 4, index stride 16 */
3279 /* shader will patch stride and desc[2] */
3281 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3282 S_008F04_SWIZZLE_ENABLE(1);
3284 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3288 S_008F0C_INDEX_STRIDE(1) |
3289 S_008F0C_ADD_TID_ENABLE(true);
3291 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3292 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3293 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3294 S_008F0C_RESOURCE_LEVEL(1);
3296 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3297 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3298 S_008F0C_ELEMENT_SIZE(1);
3305 if (tess_rings_bo
) {
3306 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3307 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3310 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3311 desc
[2] = tess_factor_ring_size
;
3312 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3313 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3314 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3315 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3317 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3318 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3319 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3320 S_008F0C_RESOURCE_LEVEL(1);
3322 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3326 desc
[4] = tess_offchip_va
;
3327 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3328 desc
[6] = tess_offchip_ring_size
;
3329 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3330 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3331 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3332 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3334 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3335 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3336 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3337 S_008F0C_RESOURCE_LEVEL(1);
3339 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3340 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3346 if (add_sample_positions
) {
3347 /* add sample positions after all rings */
3348 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3350 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3352 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3354 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3359 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3361 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3362 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3363 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3364 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3365 unsigned max_offchip_buffers
;
3366 unsigned offchip_granularity
;
3367 unsigned hs_offchip_param
;
3371 * This must be one less than the maximum number due to a hw limitation.
3372 * Various hardware bugs need thGFX7
3375 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3376 * Gfx7 should limit max_offchip_buffers to 508
3377 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3379 * Follow AMDVLK here.
3381 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3382 max_offchip_buffers_per_se
= 256;
3383 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3384 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3385 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3386 --max_offchip_buffers_per_se
;
3388 max_offchip_buffers
= max_offchip_buffers_per_se
*
3389 device
->physical_device
->rad_info
.max_se
;
3391 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3392 * around by setting 4K granularity.
3394 if (device
->tess_offchip_block_dw_size
== 4096) {
3395 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3396 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3398 assert(device
->tess_offchip_block_dw_size
== 8192);
3399 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3402 switch (device
->physical_device
->rad_info
.chip_class
) {
3404 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3409 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3417 *max_offchip_buffers_p
= max_offchip_buffers
;
3418 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3419 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3420 --max_offchip_buffers
;
3422 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3423 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3426 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3428 return hs_offchip_param
;
3432 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3433 struct radeon_winsys_bo
*esgs_ring_bo
,
3434 uint32_t esgs_ring_size
,
3435 struct radeon_winsys_bo
*gsvs_ring_bo
,
3436 uint32_t gsvs_ring_size
)
3438 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3442 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3445 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3447 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3448 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3449 radeon_emit(cs
, esgs_ring_size
>> 8);
3450 radeon_emit(cs
, gsvs_ring_size
>> 8);
3452 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3453 radeon_emit(cs
, esgs_ring_size
>> 8);
3454 radeon_emit(cs
, gsvs_ring_size
>> 8);
3459 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3460 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3461 struct radeon_winsys_bo
*tess_rings_bo
)
3468 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3470 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3472 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3473 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3474 S_030938_SIZE(tf_ring_size
/ 4));
3475 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3478 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3479 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3480 S_030984_BASE_HI(tf_va
>> 40));
3481 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3482 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3483 S_030944_BASE_HI(tf_va
>> 40));
3485 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3488 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3489 S_008988_SIZE(tf_ring_size
/ 4));
3490 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3492 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3498 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3499 uint32_t size_per_wave
, uint32_t waves
,
3500 struct radeon_winsys_bo
*scratch_bo
)
3502 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3508 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3510 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3511 S_0286E8_WAVES(waves
) |
3512 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3516 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3517 uint32_t size_per_wave
, uint32_t waves
,
3518 struct radeon_winsys_bo
*compute_scratch_bo
)
3520 uint64_t scratch_va
;
3522 if (!compute_scratch_bo
)
3525 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3527 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3529 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3530 radeon_emit(cs
, scratch_va
);
3531 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3532 S_008F04_SWIZZLE_ENABLE(1));
3534 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3535 S_00B860_WAVES(waves
) |
3536 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3540 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3541 struct radeon_cmdbuf
*cs
,
3542 struct radeon_winsys_bo
*descriptor_bo
)
3549 va
= radv_buffer_get_va(descriptor_bo
);
3551 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3553 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3554 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3555 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3556 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3557 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3559 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3560 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3563 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3564 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3565 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3566 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3567 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3569 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3570 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3574 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3575 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3576 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3577 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3578 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3579 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3581 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3582 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3589 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3591 struct radv_device
*device
= queue
->device
;
3593 if (device
->gfx_init
) {
3594 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3596 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3597 radeon_emit(cs
, va
);
3598 radeon_emit(cs
, va
>> 32);
3599 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3601 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3603 struct radv_physical_device
*physical_device
= device
->physical_device
;
3604 si_emit_graphics(physical_device
, cs
);
3609 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3611 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3612 si_emit_compute(physical_device
, cs
);
3616 radv_get_preamble_cs(struct radv_queue
*queue
,
3617 uint32_t scratch_size_per_wave
,
3618 uint32_t scratch_waves
,
3619 uint32_t compute_scratch_size_per_wave
,
3620 uint32_t compute_scratch_waves
,
3621 uint32_t esgs_ring_size
,
3622 uint32_t gsvs_ring_size
,
3623 bool needs_tess_rings
,
3626 bool needs_sample_positions
,
3627 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3628 struct radeon_cmdbuf
**initial_preamble_cs
,
3629 struct radeon_cmdbuf
**continue_preamble_cs
)
3631 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3632 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3633 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3634 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3635 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3636 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3637 struct radeon_winsys_bo
*gds_bo
= NULL
;
3638 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3639 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3640 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3641 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3642 unsigned max_offchip_buffers
;
3643 unsigned hs_offchip_param
= 0;
3644 unsigned tess_offchip_ring_offset
;
3645 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3646 if (!queue
->has_tess_rings
) {
3647 if (needs_tess_rings
)
3648 add_tess_rings
= true;
3650 if (!queue
->has_gds
) {
3654 if (!queue
->has_gds_oa
) {
3658 if (!queue
->has_sample_positions
) {
3659 if (needs_sample_positions
)
3660 add_sample_positions
= true;
3662 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3663 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3664 &max_offchip_buffers
);
3665 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3666 tess_offchip_ring_size
= max_offchip_buffers
*
3667 queue
->device
->tess_offchip_block_dw_size
* 4;
3669 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3670 if (scratch_size_per_wave
)
3671 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3675 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3676 if (compute_scratch_size_per_wave
)
3677 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3679 compute_scratch_waves
= 0;
3681 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3682 scratch_waves
<= queue
->scratch_waves
&&
3683 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3684 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3685 esgs_ring_size
<= queue
->esgs_ring_size
&&
3686 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3687 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3688 queue
->initial_preamble_cs
) {
3689 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3690 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3691 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3692 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3693 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3694 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3695 *continue_preamble_cs
= NULL
;
3699 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3700 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3701 if (scratch_size
> queue_scratch_size
) {
3702 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3707 RADV_BO_PRIORITY_SCRATCH
);
3711 scratch_bo
= queue
->scratch_bo
;
3713 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3714 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3715 if (compute_scratch_size
> compute_queue_scratch_size
) {
3716 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3717 compute_scratch_size
,
3721 RADV_BO_PRIORITY_SCRATCH
);
3722 if (!compute_scratch_bo
)
3726 compute_scratch_bo
= queue
->compute_scratch_bo
;
3728 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3729 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3734 RADV_BO_PRIORITY_SCRATCH
);
3738 esgs_ring_bo
= queue
->esgs_ring_bo
;
3739 esgs_ring_size
= queue
->esgs_ring_size
;
3742 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3743 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3748 RADV_BO_PRIORITY_SCRATCH
);
3752 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3753 gsvs_ring_size
= queue
->gsvs_ring_size
;
3756 if (add_tess_rings
) {
3757 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3758 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3762 RADV_BO_PRIORITY_SCRATCH
);
3766 tess_rings_bo
= queue
->tess_rings_bo
;
3770 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3772 /* 4 streamout GDS counters.
3773 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3775 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3779 RADV_BO_PRIORITY_SCRATCH
);
3783 gds_bo
= queue
->gds_bo
;
3787 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3789 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3793 RADV_BO_PRIORITY_SCRATCH
);
3797 gds_oa_bo
= queue
->gds_oa_bo
;
3800 if (scratch_bo
!= queue
->scratch_bo
||
3801 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3802 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3803 tess_rings_bo
!= queue
->tess_rings_bo
||
3804 add_sample_positions
) {
3806 if (gsvs_ring_bo
|| esgs_ring_bo
||
3807 tess_rings_bo
|| add_sample_positions
) {
3808 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3809 if (add_sample_positions
)
3810 size
+= 128; /* 64+32+16+8 = 120 bytes */
3812 else if (scratch_bo
)
3813 size
= 8; /* 2 dword */
3815 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3819 RADEON_FLAG_CPU_ACCESS
|
3820 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3821 RADEON_FLAG_READ_ONLY
,
3822 RADV_BO_PRIORITY_DESCRIPTOR
);
3826 descriptor_bo
= queue
->descriptor_bo
;
3828 if (descriptor_bo
!= queue
->descriptor_bo
) {
3829 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3832 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3833 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3834 S_008F04_SWIZZLE_ENABLE(1);
3835 map
[0] = scratch_va
;
3839 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3840 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3841 esgs_ring_size
, esgs_ring_bo
,
3842 gsvs_ring_size
, gsvs_ring_bo
,
3843 tess_factor_ring_size
,
3844 tess_offchip_ring_offset
,
3845 tess_offchip_ring_size
,
3848 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3851 for(int i
= 0; i
< 3; ++i
) {
3852 struct radeon_cmdbuf
*cs
= NULL
;
3853 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3854 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3861 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3863 /* Emit initial configuration. */
3864 switch (queue
->queue_family_index
) {
3865 case RADV_QUEUE_GENERAL
:
3866 radv_init_graphics_state(cs
, queue
);
3868 case RADV_QUEUE_COMPUTE
:
3869 radv_init_compute_state(cs
, queue
);
3871 case RADV_QUEUE_TRANSFER
:
3875 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3876 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3877 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3879 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3880 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3883 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3884 gsvs_ring_bo
, gsvs_ring_size
);
3885 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3886 tess_factor_ring_size
, tess_rings_bo
);
3887 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3888 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3889 compute_scratch_waves
, compute_scratch_bo
);
3890 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3891 scratch_waves
, scratch_bo
);
3894 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3896 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3899 si_cs_emit_cache_flush(cs
,
3900 queue
->device
->physical_device
->rad_info
.chip_class
,
3902 queue
->queue_family_index
== RING_COMPUTE
&&
3903 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3904 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3905 RADV_CMD_FLAG_INV_ICACHE
|
3906 RADV_CMD_FLAG_INV_SCACHE
|
3907 RADV_CMD_FLAG_INV_VCACHE
|
3908 RADV_CMD_FLAG_INV_L2
|
3909 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3910 } else if (i
== 1) {
3911 si_cs_emit_cache_flush(cs
,
3912 queue
->device
->physical_device
->rad_info
.chip_class
,
3914 queue
->queue_family_index
== RING_COMPUTE
&&
3915 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3916 RADV_CMD_FLAG_INV_ICACHE
|
3917 RADV_CMD_FLAG_INV_SCACHE
|
3918 RADV_CMD_FLAG_INV_VCACHE
|
3919 RADV_CMD_FLAG_INV_L2
|
3920 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3923 if (!queue
->device
->ws
->cs_finalize(cs
))
3927 if (queue
->initial_full_flush_preamble_cs
)
3928 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3930 if (queue
->initial_preamble_cs
)
3931 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3933 if (queue
->continue_preamble_cs
)
3934 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3936 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3937 queue
->initial_preamble_cs
= dest_cs
[1];
3938 queue
->continue_preamble_cs
= dest_cs
[2];
3940 if (scratch_bo
!= queue
->scratch_bo
) {
3941 if (queue
->scratch_bo
)
3942 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3943 queue
->scratch_bo
= scratch_bo
;
3945 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3946 queue
->scratch_waves
= scratch_waves
;
3948 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3949 if (queue
->compute_scratch_bo
)
3950 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3951 queue
->compute_scratch_bo
= compute_scratch_bo
;
3953 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3954 queue
->compute_scratch_waves
= compute_scratch_waves
;
3956 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3957 if (queue
->esgs_ring_bo
)
3958 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3959 queue
->esgs_ring_bo
= esgs_ring_bo
;
3960 queue
->esgs_ring_size
= esgs_ring_size
;
3963 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3964 if (queue
->gsvs_ring_bo
)
3965 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3966 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3967 queue
->gsvs_ring_size
= gsvs_ring_size
;
3970 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3971 queue
->tess_rings_bo
= tess_rings_bo
;
3972 queue
->has_tess_rings
= true;
3975 if (gds_bo
!= queue
->gds_bo
) {
3976 queue
->gds_bo
= gds_bo
;
3977 queue
->has_gds
= true;
3980 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3981 queue
->gds_oa_bo
= gds_oa_bo
;
3982 queue
->has_gds_oa
= true;
3985 if (descriptor_bo
!= queue
->descriptor_bo
) {
3986 if (queue
->descriptor_bo
)
3987 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3989 queue
->descriptor_bo
= descriptor_bo
;
3992 if (add_sample_positions
)
3993 queue
->has_sample_positions
= true;
3995 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3996 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3997 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3998 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3999 *continue_preamble_cs
= NULL
;
4002 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4004 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4005 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4006 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4007 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4008 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4009 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4010 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4011 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4012 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4013 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4014 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4015 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4016 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4017 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4018 queue
->device
->ws
->buffer_destroy(gds_bo
);
4019 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4020 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4022 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4025 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4026 struct radv_winsys_sem_counts
*counts
,
4028 struct radv_semaphore_part
**sems
,
4029 const uint64_t *timeline_values
,
4033 int syncobj_idx
= 0, sem_idx
= 0;
4035 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4038 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4039 switch(sems
[i
]->kind
) {
4040 case RADV_SEMAPHORE_SYNCOBJ
:
4041 counts
->syncobj_count
++;
4043 case RADV_SEMAPHORE_WINSYS
:
4044 counts
->sem_count
++;
4046 case RADV_SEMAPHORE_NONE
:
4048 case RADV_SEMAPHORE_TIMELINE
:
4049 counts
->syncobj_count
++;
4054 if (_fence
!= VK_NULL_HANDLE
) {
4055 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4056 if (fence
->temp_syncobj
|| fence
->syncobj
)
4057 counts
->syncobj_count
++;
4060 if (counts
->syncobj_count
) {
4061 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4062 if (!counts
->syncobj
)
4063 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4066 if (counts
->sem_count
) {
4067 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4069 free(counts
->syncobj
);
4070 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4074 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4075 switch(sems
[i
]->kind
) {
4076 case RADV_SEMAPHORE_NONE
:
4077 unreachable("Empty semaphore");
4079 case RADV_SEMAPHORE_SYNCOBJ
:
4080 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4082 case RADV_SEMAPHORE_WINSYS
:
4083 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4085 case RADV_SEMAPHORE_TIMELINE
: {
4086 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4087 struct radv_timeline_point
*point
= NULL
;
4089 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4091 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4094 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4097 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4099 /* Explicitly remove the semaphore so we might not find
4100 * a point later post-submit. */
4108 if (_fence
!= VK_NULL_HANDLE
) {
4109 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4110 if (fence
->temp_syncobj
)
4111 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4112 else if (fence
->syncobj
)
4113 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4116 assert(syncobj_idx
<= counts
->syncobj_count
);
4117 counts
->syncobj_count
= syncobj_idx
;
4123 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4125 free(sem_info
->wait
.syncobj
);
4126 free(sem_info
->wait
.sem
);
4127 free(sem_info
->signal
.syncobj
);
4128 free(sem_info
->signal
.sem
);
4132 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4134 struct radv_semaphore_part
*sems
)
4136 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4137 radv_destroy_semaphore_part(device
, sems
+ i
);
4142 radv_alloc_sem_info(struct radv_device
*device
,
4143 struct radv_winsys_sem_info
*sem_info
,
4145 struct radv_semaphore_part
**wait_sems
,
4146 const uint64_t *wait_values
,
4147 int num_signal_sems
,
4148 struct radv_semaphore_part
**signal_sems
,
4149 const uint64_t *signal_values
,
4153 memset(sem_info
, 0, sizeof(*sem_info
));
4155 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4158 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4160 radv_free_sem_info(sem_info
);
4162 /* caller can override these */
4163 sem_info
->cs_emit_wait
= true;
4164 sem_info
->cs_emit_signal
= true;
4169 radv_finalize_timelines(struct radv_device
*device
,
4170 uint32_t num_wait_sems
,
4171 struct radv_semaphore_part
**wait_sems
,
4172 const uint64_t *wait_values
,
4173 uint32_t num_signal_sems
,
4174 struct radv_semaphore_part
**signal_sems
,
4175 const uint64_t *signal_values
,
4176 struct list_head
*processing_list
)
4178 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4179 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4180 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4181 struct radv_timeline_point
*point
=
4182 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4183 point
->wait_count
-= 2;
4184 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4187 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4188 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4189 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4190 struct radv_timeline_point
*point
=
4191 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4192 signal_sems
[i
]->timeline
.highest_submitted
=
4193 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4194 point
->wait_count
-= 2;
4195 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4196 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4202 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4203 const VkSparseBufferMemoryBindInfo
*bind
)
4205 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4207 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4208 struct radv_device_memory
*mem
= NULL
;
4210 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4211 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4213 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4214 bind
->pBinds
[i
].resourceOffset
,
4215 bind
->pBinds
[i
].size
,
4216 mem
? mem
->bo
: NULL
,
4217 bind
->pBinds
[i
].memoryOffset
);
4222 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4223 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4225 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4227 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4228 struct radv_device_memory
*mem
= NULL
;
4230 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4231 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4233 device
->ws
->buffer_virtual_bind(image
->bo
,
4234 bind
->pBinds
[i
].resourceOffset
,
4235 bind
->pBinds
[i
].size
,
4236 mem
? mem
->bo
: NULL
,
4237 bind
->pBinds
[i
].memoryOffset
);
4242 radv_get_preambles(struct radv_queue
*queue
,
4243 const VkCommandBuffer
*cmd_buffers
,
4244 uint32_t cmd_buffer_count
,
4245 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4246 struct radeon_cmdbuf
**initial_preamble_cs
,
4247 struct radeon_cmdbuf
**continue_preamble_cs
)
4249 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4250 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4251 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4252 bool tess_rings_needed
= false;
4253 bool gds_needed
= false;
4254 bool gds_oa_needed
= false;
4255 bool sample_positions_needed
= false;
4257 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4258 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4261 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4262 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4263 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4264 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4265 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4266 cmd_buffer
->compute_scratch_waves_wanted
);
4267 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4268 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4269 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4270 gds_needed
|= cmd_buffer
->gds_needed
;
4271 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4272 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4275 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4276 compute_scratch_size_per_wave
, compute_waves_wanted
,
4277 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4278 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4279 initial_full_flush_preamble_cs
,
4280 initial_preamble_cs
, continue_preamble_cs
);
4283 struct radv_deferred_queue_submission
{
4284 struct radv_queue
*queue
;
4285 VkCommandBuffer
*cmd_buffers
;
4286 uint32_t cmd_buffer_count
;
4288 /* Sparse bindings that happen on a queue. */
4289 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4290 uint32_t buffer_bind_count
;
4291 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4292 uint32_t image_opaque_bind_count
;
4295 VkShaderStageFlags wait_dst_stage_mask
;
4296 struct radv_semaphore_part
**wait_semaphores
;
4297 uint32_t wait_semaphore_count
;
4298 struct radv_semaphore_part
**signal_semaphores
;
4299 uint32_t signal_semaphore_count
;
4302 uint64_t *wait_values
;
4303 uint64_t *signal_values
;
4305 struct radv_semaphore_part
*temporary_semaphore_parts
;
4306 uint32_t temporary_semaphore_part_count
;
4308 struct list_head queue_pending_list
;
4309 uint32_t submission_wait_count
;
4310 struct radv_timeline_waiter
*wait_nodes
;
4312 struct list_head processing_list
;
4315 struct radv_queue_submission
{
4316 const VkCommandBuffer
*cmd_buffers
;
4317 uint32_t cmd_buffer_count
;
4319 /* Sparse bindings that happen on a queue. */
4320 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4321 uint32_t buffer_bind_count
;
4322 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4323 uint32_t image_opaque_bind_count
;
4326 VkPipelineStageFlags wait_dst_stage_mask
;
4327 const VkSemaphore
*wait_semaphores
;
4328 uint32_t wait_semaphore_count
;
4329 const VkSemaphore
*signal_semaphores
;
4330 uint32_t signal_semaphore_count
;
4333 const uint64_t *wait_values
;
4334 uint32_t wait_value_count
;
4335 const uint64_t *signal_values
;
4336 uint32_t signal_value_count
;
4340 radv_create_deferred_submission(struct radv_queue
*queue
,
4341 const struct radv_queue_submission
*submission
,
4342 struct radv_deferred_queue_submission
**out
)
4344 struct radv_deferred_queue_submission
*deferred
= NULL
;
4345 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4347 uint32_t temporary_count
= 0;
4348 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4349 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4350 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4354 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4355 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4356 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4357 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4358 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4359 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4360 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4361 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4362 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4364 deferred
= calloc(1, size
);
4366 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4368 deferred
->queue
= queue
;
4370 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4371 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4372 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4373 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4375 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4376 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4377 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4378 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4380 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4381 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4382 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4383 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4385 deferred
->flush_caches
= submission
->flush_caches
;
4386 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4388 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4389 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4391 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4392 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4394 deferred
->fence
= submission
->fence
;
4396 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4397 deferred
->temporary_semaphore_part_count
= temporary_count
;
4399 uint32_t temporary_idx
= 0;
4400 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4401 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4402 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4403 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4404 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4405 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4408 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4411 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4412 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4413 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4414 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4416 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4420 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4421 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4422 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4423 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4425 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4426 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4427 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4428 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4435 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4436 struct list_head
*processing_list
)
4438 uint32_t wait_cnt
= 0;
4439 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4440 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4441 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4442 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4443 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4445 waiter
->value
= submission
->wait_values
[i
];
4446 waiter
->submission
= submission
;
4447 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4450 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4454 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4456 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4457 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4459 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4461 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4462 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4464 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4465 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4466 list_addtail(&submission
->processing_list
, processing_list
);
4471 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4472 struct list_head
*processing_list
)
4474 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4475 list_del(&submission
->queue_pending_list
);
4477 /* trigger the next submission in the queue. */
4478 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4479 struct radv_deferred_queue_submission
*next_submission
=
4480 list_first_entry(&submission
->queue
->pending_submissions
,
4481 struct radv_deferred_queue_submission
,
4482 queue_pending_list
);
4483 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4484 list_addtail(&next_submission
->processing_list
, processing_list
);
4487 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4489 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4493 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4494 struct list_head
*processing_list
)
4496 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4497 struct radv_queue
*queue
= submission
->queue
;
4498 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4499 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4500 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4501 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4502 bool can_patch
= true;
4504 struct radv_winsys_sem_info sem_info
;
4507 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4508 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4509 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4511 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4512 submission
->cmd_buffer_count
,
4513 &initial_preamble_cs
,
4514 &initial_flush_preamble_cs
,
4515 &continue_preamble_cs
);
4516 if (result
!= VK_SUCCESS
)
4519 result
= radv_alloc_sem_info(queue
->device
,
4521 submission
->wait_semaphore_count
,
4522 submission
->wait_semaphores
,
4523 submission
->wait_values
,
4524 submission
->signal_semaphore_count
,
4525 submission
->signal_semaphores
,
4526 submission
->signal_values
,
4528 if (result
!= VK_SUCCESS
)
4531 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4532 radv_sparse_buffer_bind_memory(queue
->device
,
4533 submission
->buffer_binds
+ i
);
4536 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4537 radv_sparse_image_opaque_bind_memory(queue
->device
,
4538 submission
->image_opaque_binds
+ i
);
4541 if (!submission
->cmd_buffer_count
) {
4542 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4543 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4548 radv_loge("failed to submit CS\n");
4554 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4555 (submission
->cmd_buffer_count
));
4557 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4558 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4559 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4561 cs_array
[j
] = cmd_buffer
->cs
;
4562 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4565 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4568 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4569 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4570 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4572 advance
= MIN2(max_cs_submission
,
4573 submission
->cmd_buffer_count
- j
);
4575 if (queue
->device
->trace_bo
)
4576 *queue
->device
->trace_id_ptr
= 0;
4578 sem_info
.cs_emit_wait
= j
== 0;
4579 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4581 if (unlikely(queue
->device
->use_global_bo_list
)) {
4582 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4583 bo_list
= &queue
->device
->bo_list
.list
;
4586 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4587 advance
, initial_preamble
, continue_preamble_cs
,
4589 can_patch
, base_fence
);
4591 if (unlikely(queue
->device
->use_global_bo_list
))
4592 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4595 radv_loge("failed to submit CS\n");
4598 if (queue
->device
->trace_bo
) {
4599 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4607 radv_free_temp_syncobjs(queue
->device
,
4608 submission
->temporary_semaphore_part_count
,
4609 submission
->temporary_semaphore_parts
);
4610 radv_finalize_timelines(queue
->device
,
4611 submission
->wait_semaphore_count
,
4612 submission
->wait_semaphores
,
4613 submission
->wait_values
,
4614 submission
->signal_semaphore_count
,
4615 submission
->signal_semaphores
,
4616 submission
->signal_values
,
4618 /* Has to happen after timeline finalization to make sure the
4619 * condition variable is only triggered when timelines and queue have
4621 radv_queue_submission_update_queue(submission
, processing_list
);
4622 radv_free_sem_info(&sem_info
);
4627 radv_free_temp_syncobjs(queue
->device
,
4628 submission
->temporary_semaphore_part_count
,
4629 submission
->temporary_semaphore_parts
);
4631 return VK_ERROR_DEVICE_LOST
;
4635 radv_process_submissions(struct list_head
*processing_list
)
4637 while(!list_is_empty(processing_list
)) {
4638 struct radv_deferred_queue_submission
*submission
=
4639 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4640 list_del(&submission
->processing_list
);
4642 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4643 if (result
!= VK_SUCCESS
)
4649 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4650 const struct radv_queue_submission
*submission
)
4652 struct radv_deferred_queue_submission
*deferred
= NULL
;
4654 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4655 if (result
!= VK_SUCCESS
)
4658 struct list_head processing_list
;
4659 list_inithead(&processing_list
);
4661 radv_queue_enqueue_submission(deferred
, &processing_list
);
4662 return radv_process_submissions(&processing_list
);
4665 /* Signals fence as soon as all the work currently put on queue is done. */
4666 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4669 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4674 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4676 return info
->commandBufferCount
||
4677 info
->waitSemaphoreCount
||
4678 info
->signalSemaphoreCount
;
4681 VkResult
radv_QueueSubmit(
4683 uint32_t submitCount
,
4684 const VkSubmitInfo
* pSubmits
,
4687 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4689 uint32_t fence_idx
= 0;
4690 bool flushed_caches
= false;
4692 if (fence
!= VK_NULL_HANDLE
) {
4693 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4694 if (radv_submit_has_effects(pSubmits
+ i
))
4697 fence_idx
= UINT32_MAX
;
4699 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4700 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4703 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4704 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4705 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4708 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4709 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4711 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4712 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4713 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4714 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4715 .flush_caches
= !flushed_caches
,
4716 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4717 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4718 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4719 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4720 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4721 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4722 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4723 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4724 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4726 if (result
!= VK_SUCCESS
)
4729 flushed_caches
= true;
4732 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4733 result
= radv_signal_fence(queue
, fence
);
4734 if (result
!= VK_SUCCESS
)
4741 VkResult
radv_QueueWaitIdle(
4744 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4746 pthread_mutex_lock(&queue
->pending_mutex
);
4747 while (!list_is_empty(&queue
->pending_submissions
)) {
4748 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4750 pthread_mutex_unlock(&queue
->pending_mutex
);
4752 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4753 radv_queue_family_to_ring(queue
->queue_family_index
),
4758 VkResult
radv_DeviceWaitIdle(
4761 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4763 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4764 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4765 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4771 VkResult
radv_EnumerateInstanceExtensionProperties(
4772 const char* pLayerName
,
4773 uint32_t* pPropertyCount
,
4774 VkExtensionProperties
* pProperties
)
4776 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4778 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4779 if (radv_supported_instance_extensions
.extensions
[i
]) {
4780 vk_outarray_append(&out
, prop
) {
4781 *prop
= radv_instance_extensions
[i
];
4786 return vk_outarray_status(&out
);
4789 VkResult
radv_EnumerateDeviceExtensionProperties(
4790 VkPhysicalDevice physicalDevice
,
4791 const char* pLayerName
,
4792 uint32_t* pPropertyCount
,
4793 VkExtensionProperties
* pProperties
)
4795 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4796 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4798 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4799 if (device
->supported_extensions
.extensions
[i
]) {
4800 vk_outarray_append(&out
, prop
) {
4801 *prop
= radv_device_extensions
[i
];
4806 return vk_outarray_status(&out
);
4809 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4810 VkInstance _instance
,
4813 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4814 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4817 return radv_lookup_entrypoint_unchecked(pName
);
4819 return radv_lookup_entrypoint_checked(pName
,
4820 instance
? instance
->apiVersion
: 0,
4821 instance
? &instance
->enabled_extensions
: NULL
,
4826 /* The loader wants us to expose a second GetInstanceProcAddr function
4827 * to work around certain LD_PRELOAD issues seen in apps.
4830 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4831 VkInstance instance
,
4835 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4836 VkInstance instance
,
4839 return radv_GetInstanceProcAddr(instance
, pName
);
4843 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4844 VkInstance _instance
,
4848 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4849 VkInstance _instance
,
4852 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4854 return radv_lookup_physical_device_entrypoint_checked(pName
,
4855 instance
? instance
->apiVersion
: 0,
4856 instance
? &instance
->enabled_extensions
: NULL
);
4859 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4863 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4864 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4867 return radv_lookup_entrypoint_unchecked(pName
);
4869 return radv_lookup_entrypoint_checked(pName
,
4870 device
->instance
->apiVersion
,
4871 &device
->instance
->enabled_extensions
,
4872 &device
->enabled_extensions
);
4876 bool radv_get_memory_fd(struct radv_device
*device
,
4877 struct radv_device_memory
*memory
,
4880 struct radeon_bo_metadata metadata
;
4882 if (memory
->image
) {
4883 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4884 radv_init_metadata(device
, memory
->image
, &metadata
);
4885 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4888 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4893 static void radv_free_memory(struct radv_device
*device
,
4894 const VkAllocationCallbacks
* pAllocator
,
4895 struct radv_device_memory
*mem
)
4900 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4901 if (mem
->android_hardware_buffer
)
4902 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4906 radv_bo_list_remove(device
, mem
->bo
);
4907 device
->ws
->buffer_destroy(mem
->bo
);
4911 vk_free2(&device
->alloc
, pAllocator
, mem
);
4914 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4915 const VkMemoryAllocateInfo
* pAllocateInfo
,
4916 const VkAllocationCallbacks
* pAllocator
,
4917 VkDeviceMemory
* pMem
)
4919 struct radv_device_memory
*mem
;
4921 enum radeon_bo_domain domain
;
4923 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
4925 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4927 const VkImportMemoryFdInfoKHR
*import_info
=
4928 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4929 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4930 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4931 const VkExportMemoryAllocateInfo
*export_info
=
4932 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4933 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4934 vk_find_struct_const(pAllocateInfo
->pNext
,
4935 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4936 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4937 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4939 const struct wsi_memory_allocate_info
*wsi_info
=
4940 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4942 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4943 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4944 /* Apparently, this is allowed */
4945 *pMem
= VK_NULL_HANDLE
;
4949 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4950 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4952 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4954 if (wsi_info
&& wsi_info
->implicit_sync
)
4955 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4957 if (dedicate_info
) {
4958 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4959 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4965 float priority_float
= 0.5;
4966 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4967 vk_find_struct_const(pAllocateInfo
->pNext
,
4968 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4970 priority_float
= priority_ext
->priority
;
4972 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4973 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4975 mem
->user_ptr
= NULL
;
4978 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4979 mem
->android_hardware_buffer
= NULL
;
4982 if (ahb_import_info
) {
4983 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4984 if (result
!= VK_SUCCESS
)
4986 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4987 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4988 if (result
!= VK_SUCCESS
)
4990 } else if (import_info
) {
4991 assert(import_info
->handleType
==
4992 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4993 import_info
->handleType
==
4994 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4995 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
4998 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5001 close(import_info
->fd
);
5003 } else if (host_ptr_info
) {
5004 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5005 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5006 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5007 pAllocateInfo
->allocationSize
,
5010 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5013 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5016 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5017 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5018 radv_is_mem_type_gtt_cached(mem_type_index
))
5019 domain
= RADEON_DOMAIN_GTT
;
5021 domain
= RADEON_DOMAIN_VRAM
;
5023 if (radv_is_mem_type_vram(mem_type_index
))
5024 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5026 flags
|= RADEON_FLAG_CPU_ACCESS
;
5028 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5029 flags
|= RADEON_FLAG_GTT_WC
;
5031 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5032 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5033 if (device
->use_global_bo_list
) {
5034 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5038 if (radv_is_mem_type_uncached(mem_type_index
)) {
5039 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5040 flags
|= RADEON_FLAG_VA_UNCACHED
;
5043 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5044 domain
, flags
, priority
);
5047 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5050 mem
->type_index
= mem_type_index
;
5053 result
= radv_bo_list_add(device
, mem
->bo
);
5054 if (result
!= VK_SUCCESS
)
5057 *pMem
= radv_device_memory_to_handle(mem
);
5062 radv_free_memory(device
, pAllocator
,mem
);
5067 VkResult
radv_AllocateMemory(
5069 const VkMemoryAllocateInfo
* pAllocateInfo
,
5070 const VkAllocationCallbacks
* pAllocator
,
5071 VkDeviceMemory
* pMem
)
5073 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5074 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5077 void radv_FreeMemory(
5079 VkDeviceMemory _mem
,
5080 const VkAllocationCallbacks
* pAllocator
)
5082 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5083 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5085 radv_free_memory(device
, pAllocator
, mem
);
5088 VkResult
radv_MapMemory(
5090 VkDeviceMemory _memory
,
5091 VkDeviceSize offset
,
5093 VkMemoryMapFlags flags
,
5096 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5097 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5105 *ppData
= mem
->user_ptr
;
5107 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5114 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5117 void radv_UnmapMemory(
5119 VkDeviceMemory _memory
)
5121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5122 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5127 if (mem
->user_ptr
== NULL
)
5128 device
->ws
->buffer_unmap(mem
->bo
);
5131 VkResult
radv_FlushMappedMemoryRanges(
5133 uint32_t memoryRangeCount
,
5134 const VkMappedMemoryRange
* pMemoryRanges
)
5139 VkResult
radv_InvalidateMappedMemoryRanges(
5141 uint32_t memoryRangeCount
,
5142 const VkMappedMemoryRange
* pMemoryRanges
)
5147 void radv_GetBufferMemoryRequirements(
5150 VkMemoryRequirements
* pMemoryRequirements
)
5152 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5153 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5155 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5157 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5158 pMemoryRequirements
->alignment
= 4096;
5160 pMemoryRequirements
->alignment
= 16;
5162 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5165 void radv_GetBufferMemoryRequirements2(
5167 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5168 VkMemoryRequirements2
*pMemoryRequirements
)
5170 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5171 &pMemoryRequirements
->memoryRequirements
);
5172 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5173 switch (ext
->sType
) {
5174 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5175 VkMemoryDedicatedRequirements
*req
=
5176 (VkMemoryDedicatedRequirements
*) ext
;
5177 req
->requiresDedicatedAllocation
= false;
5178 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5187 void radv_GetImageMemoryRequirements(
5190 VkMemoryRequirements
* pMemoryRequirements
)
5192 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5193 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5195 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5197 pMemoryRequirements
->size
= image
->size
;
5198 pMemoryRequirements
->alignment
= image
->alignment
;
5201 void radv_GetImageMemoryRequirements2(
5203 const VkImageMemoryRequirementsInfo2
*pInfo
,
5204 VkMemoryRequirements2
*pMemoryRequirements
)
5206 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5207 &pMemoryRequirements
->memoryRequirements
);
5209 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5211 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5212 switch (ext
->sType
) {
5213 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5214 VkMemoryDedicatedRequirements
*req
=
5215 (VkMemoryDedicatedRequirements
*) ext
;
5216 req
->requiresDedicatedAllocation
= image
->shareable
&&
5217 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5218 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5227 void radv_GetImageSparseMemoryRequirements(
5230 uint32_t* pSparseMemoryRequirementCount
,
5231 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5236 void radv_GetImageSparseMemoryRequirements2(
5238 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5239 uint32_t* pSparseMemoryRequirementCount
,
5240 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5245 void radv_GetDeviceMemoryCommitment(
5247 VkDeviceMemory memory
,
5248 VkDeviceSize
* pCommittedMemoryInBytes
)
5250 *pCommittedMemoryInBytes
= 0;
5253 VkResult
radv_BindBufferMemory2(VkDevice device
,
5254 uint32_t bindInfoCount
,
5255 const VkBindBufferMemoryInfo
*pBindInfos
)
5257 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5258 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5259 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5262 buffer
->bo
= mem
->bo
;
5263 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5271 VkResult
radv_BindBufferMemory(
5274 VkDeviceMemory memory
,
5275 VkDeviceSize memoryOffset
)
5277 const VkBindBufferMemoryInfo info
= {
5278 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5281 .memoryOffset
= memoryOffset
5284 return radv_BindBufferMemory2(device
, 1, &info
);
5287 VkResult
radv_BindImageMemory2(VkDevice device
,
5288 uint32_t bindInfoCount
,
5289 const VkBindImageMemoryInfo
*pBindInfos
)
5291 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5292 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5293 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5296 image
->bo
= mem
->bo
;
5297 image
->offset
= pBindInfos
[i
].memoryOffset
;
5307 VkResult
radv_BindImageMemory(
5310 VkDeviceMemory memory
,
5311 VkDeviceSize memoryOffset
)
5313 const VkBindImageMemoryInfo info
= {
5314 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5317 .memoryOffset
= memoryOffset
5320 return radv_BindImageMemory2(device
, 1, &info
);
5323 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5325 return info
->bufferBindCount
||
5326 info
->imageOpaqueBindCount
||
5327 info
->imageBindCount
||
5328 info
->waitSemaphoreCount
||
5329 info
->signalSemaphoreCount
;
5332 VkResult
radv_QueueBindSparse(
5334 uint32_t bindInfoCount
,
5335 const VkBindSparseInfo
* pBindInfo
,
5338 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5340 uint32_t fence_idx
= 0;
5342 if (fence
!= VK_NULL_HANDLE
) {
5343 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5344 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5347 fence_idx
= UINT32_MAX
;
5349 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5350 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5353 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5354 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5356 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5357 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5358 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5359 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5360 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5361 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5362 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5363 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5364 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5365 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5366 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5367 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5368 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5369 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5372 if (result
!= VK_SUCCESS
)
5376 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5377 result
= radv_signal_fence(queue
, fence
);
5378 if (result
!= VK_SUCCESS
)
5385 VkResult
radv_CreateFence(
5387 const VkFenceCreateInfo
* pCreateInfo
,
5388 const VkAllocationCallbacks
* pAllocator
,
5391 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5392 const VkExportFenceCreateInfo
*export
=
5393 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5394 VkExternalFenceHandleTypeFlags handleTypes
=
5395 export
? export
->handleTypes
: 0;
5397 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5399 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5402 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5404 fence
->fence_wsi
= NULL
;
5405 fence
->temp_syncobj
= 0;
5406 if (device
->always_use_syncobj
|| handleTypes
) {
5407 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5409 vk_free2(&device
->alloc
, pAllocator
, fence
);
5410 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5412 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5413 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5415 fence
->fence
= NULL
;
5417 fence
->fence
= device
->ws
->create_fence();
5418 if (!fence
->fence
) {
5419 vk_free2(&device
->alloc
, pAllocator
, fence
);
5420 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5423 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5424 device
->ws
->signal_fence(fence
->fence
);
5427 *pFence
= radv_fence_to_handle(fence
);
5432 void radv_DestroyFence(
5435 const VkAllocationCallbacks
* pAllocator
)
5437 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5438 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5443 if (fence
->temp_syncobj
)
5444 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5446 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5448 device
->ws
->destroy_fence(fence
->fence
);
5449 if (fence
->fence_wsi
)
5450 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5451 vk_free2(&device
->alloc
, pAllocator
, fence
);
5455 uint64_t radv_get_current_time(void)
5458 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5459 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5462 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5464 uint64_t current_time
= radv_get_current_time();
5466 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5468 return current_time
+ timeout
;
5472 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5473 uint32_t fenceCount
, const VkFence
*pFences
)
5475 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5476 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5477 if (fence
->fence
== NULL
|| fence
->syncobj
||
5478 fence
->temp_syncobj
|| fence
->fence_wsi
||
5479 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5485 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5487 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5488 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5489 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5495 VkResult
radv_WaitForFences(
5497 uint32_t fenceCount
,
5498 const VkFence
* pFences
,
5502 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5503 timeout
= radv_get_absolute_timeout(timeout
);
5505 if (device
->always_use_syncobj
&&
5506 radv_all_fences_syncobj(fenceCount
, pFences
))
5508 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5510 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5512 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5513 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5514 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5517 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5520 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5523 if (!waitAll
&& fenceCount
> 1) {
5524 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5525 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5526 uint32_t wait_count
= 0;
5527 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5529 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5531 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5532 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5534 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5539 fences
[wait_count
++] = fence
->fence
;
5542 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5543 waitAll
, timeout
- radv_get_current_time());
5546 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5549 while(radv_get_current_time() <= timeout
) {
5550 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5551 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5558 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5559 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5560 bool expired
= false;
5562 if (fence
->temp_syncobj
) {
5563 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5568 if (fence
->syncobj
) {
5569 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5575 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5576 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5577 radv_get_current_time() <= timeout
)
5581 expired
= device
->ws
->fence_wait(device
->ws
,
5588 if (fence
->fence_wsi
) {
5589 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5590 if (result
!= VK_SUCCESS
)
5598 VkResult
radv_ResetFences(VkDevice _device
,
5599 uint32_t fenceCount
,
5600 const VkFence
*pFences
)
5602 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5604 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5605 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5607 device
->ws
->reset_fence(fence
->fence
);
5609 /* Per spec, we first restore the permanent payload, and then reset, so
5610 * having a temp syncobj should not skip resetting the permanent syncobj. */
5611 if (fence
->temp_syncobj
) {
5612 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5613 fence
->temp_syncobj
= 0;
5616 if (fence
->syncobj
) {
5617 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5624 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5626 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5627 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5629 if (fence
->temp_syncobj
) {
5630 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5631 return success
? VK_SUCCESS
: VK_NOT_READY
;
5634 if (fence
->syncobj
) {
5635 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5636 return success
? VK_SUCCESS
: VK_NOT_READY
;
5640 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5641 return VK_NOT_READY
;
5643 if (fence
->fence_wsi
) {
5644 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5646 if (result
!= VK_SUCCESS
) {
5647 if (result
== VK_TIMEOUT
)
5648 return VK_NOT_READY
;
5656 // Queue semaphore functions
5659 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5661 timeline
->highest_signaled
= value
;
5662 timeline
->highest_submitted
= value
;
5663 list_inithead(&timeline
->points
);
5664 list_inithead(&timeline
->free_points
);
5665 list_inithead(&timeline
->waiters
);
5666 pthread_mutex_init(&timeline
->mutex
, NULL
);
5670 radv_destroy_timeline(struct radv_device
*device
,
5671 struct radv_timeline
*timeline
)
5673 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5674 &timeline
->free_points
, list
) {
5675 list_del(&point
->list
);
5676 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5679 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5680 &timeline
->points
, list
) {
5681 list_del(&point
->list
);
5682 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5685 pthread_mutex_destroy(&timeline
->mutex
);
5689 radv_timeline_gc_locked(struct radv_device
*device
,
5690 struct radv_timeline
*timeline
)
5692 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5693 &timeline
->points
, list
) {
5694 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5697 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5698 timeline
->highest_signaled
= point
->value
;
5699 list_del(&point
->list
);
5700 list_add(&point
->list
, &timeline
->free_points
);
5705 static struct radv_timeline_point
*
5706 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5707 struct radv_timeline
*timeline
,
5710 radv_timeline_gc_locked(device
, timeline
);
5712 if (p
<= timeline
->highest_signaled
)
5715 list_for_each_entry(struct radv_timeline_point
, point
,
5716 &timeline
->points
, list
) {
5717 if (point
->value
>= p
) {
5718 ++point
->wait_count
;
5725 static struct radv_timeline_point
*
5726 radv_timeline_add_point_locked(struct radv_device
*device
,
5727 struct radv_timeline
*timeline
,
5730 radv_timeline_gc_locked(device
, timeline
);
5732 struct radv_timeline_point
*ret
= NULL
;
5733 struct radv_timeline_point
*prev
= NULL
;
5735 if (p
<= timeline
->highest_signaled
)
5738 list_for_each_entry(struct radv_timeline_point
, point
,
5739 &timeline
->points
, list
) {
5740 if (point
->value
== p
) {
5744 if (point
->value
< p
)
5748 if (list_is_empty(&timeline
->free_points
)) {
5749 ret
= malloc(sizeof(struct radv_timeline_point
));
5750 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5752 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5753 list_del(&ret
->list
);
5755 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5759 ret
->wait_count
= 1;
5762 list_add(&ret
->list
, &prev
->list
);
5764 list_addtail(&ret
->list
, &timeline
->points
);
5771 radv_timeline_wait_locked(struct radv_device
*device
,
5772 struct radv_timeline
*timeline
,
5774 uint64_t abs_timeout
)
5776 while(timeline
->highest_submitted
< value
) {
5777 struct timespec abstime
;
5778 timespec_from_nsec(&abstime
, abs_timeout
);
5780 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5782 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5786 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5790 pthread_mutex_unlock(&timeline
->mutex
);
5792 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5794 pthread_mutex_lock(&timeline
->mutex
);
5795 point
->wait_count
--;
5796 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5800 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5801 struct list_head
*processing_list
)
5803 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5804 &timeline
->waiters
, list
) {
5805 if (waiter
->value
> timeline
->highest_submitted
)
5808 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5809 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5811 list_del(&waiter
->list
);
5816 void radv_destroy_semaphore_part(struct radv_device
*device
,
5817 struct radv_semaphore_part
*part
)
5819 switch(part
->kind
) {
5820 case RADV_SEMAPHORE_NONE
:
5822 case RADV_SEMAPHORE_WINSYS
:
5823 device
->ws
->destroy_sem(part
->ws_sem
);
5825 case RADV_SEMAPHORE_TIMELINE
:
5826 radv_destroy_timeline(device
, &part
->timeline
);
5828 case RADV_SEMAPHORE_SYNCOBJ
:
5829 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5832 part
->kind
= RADV_SEMAPHORE_NONE
;
5835 static VkSemaphoreTypeKHR
5836 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5838 const VkSemaphoreTypeCreateInfo
*type_info
=
5839 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5842 return VK_SEMAPHORE_TYPE_BINARY
;
5845 *initial_value
= type_info
->initialValue
;
5846 return type_info
->semaphoreType
;
5849 VkResult
radv_CreateSemaphore(
5851 const VkSemaphoreCreateInfo
* pCreateInfo
,
5852 const VkAllocationCallbacks
* pAllocator
,
5853 VkSemaphore
* pSemaphore
)
5855 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5856 const VkExportSemaphoreCreateInfo
*export
=
5857 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5858 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5859 export
? export
->handleTypes
: 0;
5860 uint64_t initial_value
= 0;
5861 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5863 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5865 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5867 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5869 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5870 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5872 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5873 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5874 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5875 } else if (device
->always_use_syncobj
|| handleTypes
) {
5876 assert (device
->physical_device
->rad_info
.has_syncobj
);
5877 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
5879 vk_free2(&device
->alloc
, pAllocator
, sem
);
5880 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5882 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5884 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5885 if (!sem
->permanent
.ws_sem
) {
5886 vk_free2(&device
->alloc
, pAllocator
, sem
);
5887 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5889 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5892 *pSemaphore
= radv_semaphore_to_handle(sem
);
5896 void radv_DestroySemaphore(
5898 VkSemaphore _semaphore
,
5899 const VkAllocationCallbacks
* pAllocator
)
5901 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5902 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5906 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5907 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5908 vk_free2(&device
->alloc
, pAllocator
, sem
);
5912 radv_GetSemaphoreCounterValue(VkDevice _device
,
5913 VkSemaphore _semaphore
,
5916 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5917 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5919 struct radv_semaphore_part
*part
=
5920 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5922 switch (part
->kind
) {
5923 case RADV_SEMAPHORE_TIMELINE
: {
5924 pthread_mutex_lock(&part
->timeline
.mutex
);
5925 radv_timeline_gc_locked(device
, &part
->timeline
);
5926 *pValue
= part
->timeline
.highest_signaled
;
5927 pthread_mutex_unlock(&part
->timeline
.mutex
);
5930 case RADV_SEMAPHORE_NONE
:
5931 case RADV_SEMAPHORE_SYNCOBJ
:
5932 case RADV_SEMAPHORE_WINSYS
:
5933 unreachable("Invalid semaphore type");
5935 unreachable("Unhandled semaphore type");
5940 radv_wait_timelines(struct radv_device
*device
,
5941 const VkSemaphoreWaitInfo
* pWaitInfo
,
5942 uint64_t abs_timeout
)
5944 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5946 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5947 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5948 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5949 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5950 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5952 if (result
== VK_SUCCESS
)
5955 if (radv_get_current_time() > abs_timeout
)
5960 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5961 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5962 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5963 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5964 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5966 if (result
!= VK_SUCCESS
)
5972 radv_WaitSemaphores(VkDevice _device
,
5973 const VkSemaphoreWaitInfo
* pWaitInfo
,
5976 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5977 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5978 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5982 radv_SignalSemaphore(VkDevice _device
,
5983 const VkSemaphoreSignalInfo
* pSignalInfo
)
5985 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5986 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
5988 struct radv_semaphore_part
*part
=
5989 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5991 switch(part
->kind
) {
5992 case RADV_SEMAPHORE_TIMELINE
: {
5993 pthread_mutex_lock(&part
->timeline
.mutex
);
5994 radv_timeline_gc_locked(device
, &part
->timeline
);
5995 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
5996 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
5998 struct list_head processing_list
;
5999 list_inithead(&processing_list
);
6000 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6001 pthread_mutex_unlock(&part
->timeline
.mutex
);
6003 return radv_process_submissions(&processing_list
);
6005 case RADV_SEMAPHORE_NONE
:
6006 case RADV_SEMAPHORE_SYNCOBJ
:
6007 case RADV_SEMAPHORE_WINSYS
:
6008 unreachable("Invalid semaphore type");
6015 VkResult
radv_CreateEvent(
6017 const VkEventCreateInfo
* pCreateInfo
,
6018 const VkAllocationCallbacks
* pAllocator
,
6021 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6022 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6024 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6027 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6029 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6031 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6032 RADV_BO_PRIORITY_FENCE
);
6034 vk_free2(&device
->alloc
, pAllocator
, event
);
6035 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6038 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6040 *pEvent
= radv_event_to_handle(event
);
6045 void radv_DestroyEvent(
6048 const VkAllocationCallbacks
* pAllocator
)
6050 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6051 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6055 device
->ws
->buffer_destroy(event
->bo
);
6056 vk_free2(&device
->alloc
, pAllocator
, event
);
6059 VkResult
radv_GetEventStatus(
6063 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6065 if (*event
->map
== 1)
6066 return VK_EVENT_SET
;
6067 return VK_EVENT_RESET
;
6070 VkResult
radv_SetEvent(
6074 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6080 VkResult
radv_ResetEvent(
6084 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6090 VkResult
radv_CreateBuffer(
6092 const VkBufferCreateInfo
* pCreateInfo
,
6093 const VkAllocationCallbacks
* pAllocator
,
6096 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6097 struct radv_buffer
*buffer
;
6099 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6101 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6102 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6104 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6106 buffer
->size
= pCreateInfo
->size
;
6107 buffer
->usage
= pCreateInfo
->usage
;
6110 buffer
->flags
= pCreateInfo
->flags
;
6112 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6113 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6115 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6116 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6117 align64(buffer
->size
, 4096),
6118 4096, 0, RADEON_FLAG_VIRTUAL
,
6119 RADV_BO_PRIORITY_VIRTUAL
);
6121 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6122 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6126 *pBuffer
= radv_buffer_to_handle(buffer
);
6131 void radv_DestroyBuffer(
6134 const VkAllocationCallbacks
* pAllocator
)
6136 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6137 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6142 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6143 device
->ws
->buffer_destroy(buffer
->bo
);
6145 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6148 VkDeviceAddress
radv_GetBufferDeviceAddress(
6150 const VkBufferDeviceAddressInfo
* pInfo
)
6152 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6153 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6157 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6158 const VkBufferDeviceAddressInfo
* pInfo
)
6163 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6164 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6169 static inline unsigned
6170 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6173 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6175 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6178 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6180 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6184 radv_init_dcc_control_reg(struct radv_device
*device
,
6185 struct radv_image_view
*iview
)
6187 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6188 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6189 unsigned max_compressed_block_size
;
6190 unsigned independent_128b_blocks
;
6191 unsigned independent_64b_blocks
;
6193 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6196 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6197 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6198 * dGPU and 64 for APU because all of our APUs to date use
6199 * DIMMs which have a request granularity size of 64B while all
6200 * other chips have a 32B request size.
6202 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6205 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6206 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6207 independent_64b_blocks
= 0;
6208 independent_128b_blocks
= 1;
6210 independent_128b_blocks
= 0;
6212 if (iview
->image
->info
.samples
> 1) {
6213 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6214 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6215 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6216 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6219 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6220 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6221 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6222 /* If this DCC image is potentially going to be used in texture
6223 * fetches, we need some special settings.
6225 independent_64b_blocks
= 1;
6226 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6228 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6229 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6230 * big as possible for better compression state.
6232 independent_64b_blocks
= 0;
6233 max_compressed_block_size
= max_uncompressed_block_size
;
6237 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6238 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6239 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6240 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6241 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6245 radv_initialise_color_surface(struct radv_device
*device
,
6246 struct radv_color_buffer_info
*cb
,
6247 struct radv_image_view
*iview
)
6249 const struct vk_format_description
*desc
;
6250 unsigned ntype
, format
, swap
, endian
;
6251 unsigned blend_clamp
= 0, blend_bypass
= 0;
6253 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6254 const struct radeon_surf
*surf
= &plane
->surface
;
6256 desc
= vk_format_description(iview
->vk_format
);
6258 memset(cb
, 0, sizeof(*cb
));
6260 /* Intensity is implemented as Red, so treat it that way. */
6261 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6263 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6265 cb
->cb_color_base
= va
>> 8;
6267 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6268 struct gfx9_surf_meta_flags meta
;
6269 if (iview
->image
->dcc_offset
)
6270 meta
= surf
->u
.gfx9
.dcc
;
6272 meta
= surf
->u
.gfx9
.cmask
;
6274 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6275 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6276 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6277 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6278 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6280 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6281 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6282 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6283 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6284 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6287 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6288 cb
->cb_color_base
|= surf
->tile_swizzle
;
6290 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6291 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6293 cb
->cb_color_base
+= level_info
->offset
>> 8;
6294 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6295 cb
->cb_color_base
|= surf
->tile_swizzle
;
6297 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6298 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6299 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6301 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6302 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6303 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6305 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6307 if (radv_image_has_fmask(iview
->image
)) {
6308 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6309 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6310 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6311 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6313 /* This must be set for fast clear to work without FMASK. */
6314 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6315 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6316 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6317 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6321 /* CMASK variables */
6322 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6323 va
+= iview
->image
->cmask_offset
;
6324 cb
->cb_color_cmask
= va
>> 8;
6326 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6327 va
+= iview
->image
->dcc_offset
;
6329 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6330 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6331 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6333 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6334 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6336 cb
->cb_dcc_base
= va
>> 8;
6337 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6339 /* GFX10 field has the same base shift as the GFX6 field. */
6340 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6341 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6342 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6344 if (iview
->image
->info
.samples
> 1) {
6345 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6347 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6348 S_028C74_NUM_FRAGMENTS(log_samples
);
6351 if (radv_image_has_fmask(iview
->image
)) {
6352 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6353 cb
->cb_color_fmask
= va
>> 8;
6354 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6356 cb
->cb_color_fmask
= cb
->cb_color_base
;
6359 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6361 vk_format_get_first_non_void_channel(iview
->vk_format
));
6362 format
= radv_translate_colorformat(iview
->vk_format
);
6363 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6364 radv_finishme("Illegal color\n");
6365 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6366 endian
= radv_colorformat_endian_swap(format
);
6368 /* blend clamp should be set for all NORM/SRGB types */
6369 if (ntype
== V_028C70_NUMBER_UNORM
||
6370 ntype
== V_028C70_NUMBER_SNORM
||
6371 ntype
== V_028C70_NUMBER_SRGB
)
6374 /* set blend bypass according to docs if SINT/UINT or
6375 8/24 COLOR variants */
6376 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6377 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6378 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6383 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6384 (format
== V_028C70_COLOR_8
||
6385 format
== V_028C70_COLOR_8_8
||
6386 format
== V_028C70_COLOR_8_8_8_8
))
6387 ->color_is_int8
= true;
6389 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6390 S_028C70_COMP_SWAP(swap
) |
6391 S_028C70_BLEND_CLAMP(blend_clamp
) |
6392 S_028C70_BLEND_BYPASS(blend_bypass
) |
6393 S_028C70_SIMPLE_FLOAT(1) |
6394 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6395 ntype
!= V_028C70_NUMBER_SNORM
&&
6396 ntype
!= V_028C70_NUMBER_SRGB
&&
6397 format
!= V_028C70_COLOR_8_24
&&
6398 format
!= V_028C70_COLOR_24_8
) |
6399 S_028C70_NUMBER_TYPE(ntype
) |
6400 S_028C70_ENDIAN(endian
);
6401 if (radv_image_has_fmask(iview
->image
)) {
6402 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6403 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6404 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6405 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6408 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6409 /* Allow the texture block to read FMASK directly
6410 * without decompressing it. This bit must be cleared
6411 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6412 * otherwise the operation doesn't happen.
6414 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6416 /* Set CMASK into a tiling format that allows the
6417 * texture block to read it.
6419 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6423 if (radv_image_has_cmask(iview
->image
) &&
6424 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6425 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6427 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6428 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6430 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6432 /* This must be set for fast clear to work without FMASK. */
6433 if (!radv_image_has_fmask(iview
->image
) &&
6434 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6435 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6436 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6439 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6440 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6442 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6443 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6444 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6445 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6447 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6448 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6450 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6451 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6452 S_028EE0_RESOURCE_LEVEL(1);
6454 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6455 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6456 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6459 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6460 S_028C68_MIP0_HEIGHT(height
- 1) |
6461 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6466 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6467 struct radv_image_view
*iview
)
6469 unsigned max_zplanes
= 0;
6471 assert(radv_image_is_tc_compat_htile(iview
->image
));
6473 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6474 /* Default value for 32-bit depth surfaces. */
6477 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6478 iview
->image
->info
.samples
> 1)
6481 max_zplanes
= max_zplanes
+ 1;
6483 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6484 /* Do not enable Z plane compression for 16-bit depth
6485 * surfaces because isn't supported on GFX8. Only
6486 * 32-bit depth surfaces are supported by the hardware.
6487 * This allows to maintain shader compatibility and to
6488 * reduce the number of depth decompressions.
6492 if (iview
->image
->info
.samples
<= 1)
6494 else if (iview
->image
->info
.samples
<= 4)
6505 radv_initialise_ds_surface(struct radv_device
*device
,
6506 struct radv_ds_buffer_info
*ds
,
6507 struct radv_image_view
*iview
)
6509 unsigned level
= iview
->base_mip
;
6510 unsigned format
, stencil_format
;
6511 uint64_t va
, s_offs
, z_offs
;
6512 bool stencil_only
= false;
6513 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6514 const struct radeon_surf
*surf
= &plane
->surface
;
6516 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6518 memset(ds
, 0, sizeof(*ds
));
6519 switch (iview
->image
->vk_format
) {
6520 case VK_FORMAT_D24_UNORM_S8_UINT
:
6521 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6522 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6523 ds
->offset_scale
= 2.0f
;
6525 case VK_FORMAT_D16_UNORM
:
6526 case VK_FORMAT_D16_UNORM_S8_UINT
:
6527 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6528 ds
->offset_scale
= 4.0f
;
6530 case VK_FORMAT_D32_SFLOAT
:
6531 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6532 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6533 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6534 ds
->offset_scale
= 1.0f
;
6536 case VK_FORMAT_S8_UINT
:
6537 stencil_only
= true;
6543 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6544 stencil_format
= surf
->has_stencil
?
6545 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6547 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6548 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6549 S_028008_SLICE_MAX(max_slice
);
6550 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6551 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6552 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6555 ds
->db_htile_data_base
= 0;
6556 ds
->db_htile_surface
= 0;
6558 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6559 s_offs
= z_offs
= va
;
6561 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6562 assert(surf
->u
.gfx9
.surf_offset
== 0);
6563 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6565 ds
->db_z_info
= S_028038_FORMAT(format
) |
6566 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6567 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6568 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6569 S_028038_ZRANGE_PRECISION(1);
6570 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6571 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6573 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6574 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6575 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6578 ds
->db_depth_view
|= S_028008_MIPID(level
);
6579 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6580 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6582 if (radv_htile_enabled(iview
->image
, level
)) {
6583 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6585 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6586 unsigned max_zplanes
=
6587 radv_calc_decompress_on_z_planes(device
, iview
);
6589 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6591 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6592 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6593 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6595 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6596 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6600 if (!surf
->has_stencil
)
6601 /* Use all of the htile_buffer for depth if there's no stencil. */
6602 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6603 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6604 iview
->image
->htile_offset
;
6605 ds
->db_htile_data_base
= va
>> 8;
6606 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6607 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6609 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6610 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6614 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6617 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6619 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6620 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6622 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6623 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6624 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6626 if (iview
->image
->info
.samples
> 1)
6627 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6629 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6630 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6631 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6632 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6633 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6634 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6635 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6636 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6639 tile_mode
= stencil_tile_mode
;
6641 ds
->db_depth_info
|=
6642 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6643 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6644 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6645 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6646 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6647 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6648 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6649 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6651 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6652 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6653 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6654 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6656 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6659 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6660 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6661 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6663 if (radv_htile_enabled(iview
->image
, level
)) {
6664 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6666 if (!surf
->has_stencil
&&
6667 !radv_image_is_tc_compat_htile(iview
->image
))
6668 /* Use all of the htile_buffer for depth if there's no stencil. */
6669 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6671 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6672 iview
->image
->htile_offset
;
6673 ds
->db_htile_data_base
= va
>> 8;
6674 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6676 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6677 unsigned max_zplanes
=
6678 radv_calc_decompress_on_z_planes(device
, iview
);
6680 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6681 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6686 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6687 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6690 VkResult
radv_CreateFramebuffer(
6692 const VkFramebufferCreateInfo
* pCreateInfo
,
6693 const VkAllocationCallbacks
* pAllocator
,
6694 VkFramebuffer
* pFramebuffer
)
6696 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6697 struct radv_framebuffer
*framebuffer
;
6698 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6699 vk_find_struct_const(pCreateInfo
->pNext
,
6700 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6702 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6704 size_t size
= sizeof(*framebuffer
);
6705 if (!imageless_create_info
)
6706 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6707 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6708 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6709 if (framebuffer
== NULL
)
6710 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6712 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6713 framebuffer
->width
= pCreateInfo
->width
;
6714 framebuffer
->height
= pCreateInfo
->height
;
6715 framebuffer
->layers
= pCreateInfo
->layers
;
6716 if (imageless_create_info
) {
6717 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6718 const VkFramebufferAttachmentImageInfo
*attachment
=
6719 imageless_create_info
->pAttachmentImageInfos
+ i
;
6720 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6721 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6722 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6725 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6726 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6727 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6728 framebuffer
->attachments
[i
] = iview
;
6729 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6730 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6731 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6735 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6739 void radv_DestroyFramebuffer(
6742 const VkAllocationCallbacks
* pAllocator
)
6744 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6745 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6749 vk_free2(&device
->alloc
, pAllocator
, fb
);
6752 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6754 switch (address_mode
) {
6755 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6756 return V_008F30_SQ_TEX_WRAP
;
6757 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6758 return V_008F30_SQ_TEX_MIRROR
;
6759 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6760 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6761 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6762 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6763 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6764 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6766 unreachable("illegal tex wrap mode");
6772 radv_tex_compare(VkCompareOp op
)
6775 case VK_COMPARE_OP_NEVER
:
6776 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6777 case VK_COMPARE_OP_LESS
:
6778 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6779 case VK_COMPARE_OP_EQUAL
:
6780 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6781 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6782 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6783 case VK_COMPARE_OP_GREATER
:
6784 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6785 case VK_COMPARE_OP_NOT_EQUAL
:
6786 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6787 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6788 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6789 case VK_COMPARE_OP_ALWAYS
:
6790 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6792 unreachable("illegal compare mode");
6798 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6801 case VK_FILTER_NEAREST
:
6802 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6803 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6804 case VK_FILTER_LINEAR
:
6805 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6806 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6807 case VK_FILTER_CUBIC_IMG
:
6809 fprintf(stderr
, "illegal texture filter");
6815 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6818 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6819 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6820 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6821 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6823 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6828 radv_tex_bordercolor(VkBorderColor bcolor
)
6831 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6832 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6833 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6834 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6835 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6836 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6837 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6838 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6839 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6847 radv_tex_aniso_filter(unsigned filter
)
6861 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6864 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6865 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6866 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6867 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6868 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6869 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6877 radv_get_max_anisotropy(struct radv_device
*device
,
6878 const VkSamplerCreateInfo
*pCreateInfo
)
6880 if (device
->force_aniso
>= 0)
6881 return device
->force_aniso
;
6883 if (pCreateInfo
->anisotropyEnable
&&
6884 pCreateInfo
->maxAnisotropy
> 1.0f
)
6885 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6891 radv_init_sampler(struct radv_device
*device
,
6892 struct radv_sampler
*sampler
,
6893 const VkSamplerCreateInfo
*pCreateInfo
)
6895 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6896 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6897 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6898 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6899 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6900 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6902 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6903 vk_find_struct_const(pCreateInfo
->pNext
,
6904 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6905 if (sampler_reduction
)
6906 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6908 if (pCreateInfo
->compareEnable
)
6909 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6911 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6912 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6913 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6914 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6915 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6916 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6917 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6918 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6919 S_008F30_DISABLE_CUBE_WRAP(0) |
6920 S_008F30_COMPAT_MODE(compat_mode
) |
6921 S_008F30_FILTER_MODE(filter_mode
));
6922 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6923 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6924 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6925 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6926 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6927 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6928 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6929 S_008F38_MIP_POINT_PRECLAMP(0));
6930 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6931 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
6933 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6934 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6936 sampler
->state
[2] |=
6937 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6938 S_008F38_FILTER_PREC_FIX(1) |
6939 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6943 VkResult
radv_CreateSampler(
6945 const VkSamplerCreateInfo
* pCreateInfo
,
6946 const VkAllocationCallbacks
* pAllocator
,
6947 VkSampler
* pSampler
)
6949 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6950 struct radv_sampler
*sampler
;
6952 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
6953 vk_find_struct_const(pCreateInfo
->pNext
,
6954 SAMPLER_YCBCR_CONVERSION_INFO
);
6956 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
6958 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
6959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6961 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6963 radv_init_sampler(device
, sampler
, pCreateInfo
);
6965 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
6966 *pSampler
= radv_sampler_to_handle(sampler
);
6971 void radv_DestroySampler(
6974 const VkAllocationCallbacks
* pAllocator
)
6976 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6977 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
6981 vk_free2(&device
->alloc
, pAllocator
, sampler
);
6984 /* vk_icd.h does not declare this function, so we declare it here to
6985 * suppress Wmissing-prototypes.
6987 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6988 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
6990 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6991 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
6993 /* For the full details on loader interface versioning, see
6994 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
6995 * What follows is a condensed summary, to help you navigate the large and
6996 * confusing official doc.
6998 * - Loader interface v0 is incompatible with later versions. We don't
7001 * - In loader interface v1:
7002 * - The first ICD entrypoint called by the loader is
7003 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7005 * - The ICD must statically expose no other Vulkan symbol unless it is
7006 * linked with -Bsymbolic.
7007 * - Each dispatchable Vulkan handle created by the ICD must be
7008 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7009 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7010 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7011 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7012 * such loader-managed surfaces.
7014 * - Loader interface v2 differs from v1 in:
7015 * - The first ICD entrypoint called by the loader is
7016 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7017 * statically expose this entrypoint.
7019 * - Loader interface v3 differs from v2 in:
7020 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7021 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7022 * because the loader no longer does so.
7024 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7028 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7029 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7032 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7033 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7035 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7037 /* At the moment, we support only the below handle types. */
7038 assert(pGetFdInfo
->handleType
==
7039 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7040 pGetFdInfo
->handleType
==
7041 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7043 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7045 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7049 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7050 VkExternalMemoryHandleTypeFlagBits handleType
,
7052 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7054 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7056 switch (handleType
) {
7057 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7058 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7062 /* The valid usage section for this function says:
7064 * "handleType must not be one of the handle types defined as
7067 * So opaque handle types fall into the default "unsupported" case.
7069 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7073 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7077 uint32_t syncobj_handle
= 0;
7078 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7080 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7083 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7085 *syncobj
= syncobj_handle
;
7091 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7095 /* If we create a syncobj we do it locally so that if we have an error, we don't
7096 * leave a syncobj in an undetermined state in the fence. */
7097 uint32_t syncobj_handle
= *syncobj
;
7098 if (!syncobj_handle
) {
7099 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7101 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7106 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7108 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7110 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7113 *syncobj
= syncobj_handle
;
7120 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7121 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7123 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7124 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7126 struct radv_semaphore_part
*dst
= NULL
;
7128 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7129 dst
= &sem
->temporary
;
7131 dst
= &sem
->permanent
;
7134 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7136 switch(pImportSemaphoreFdInfo
->handleType
) {
7137 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7138 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7140 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7141 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7144 unreachable("Unhandled semaphore handle type");
7147 if (result
== VK_SUCCESS
) {
7148 dst
->syncobj
= syncobj
;
7149 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7155 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7156 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7159 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7160 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7162 uint32_t syncobj_handle
;
7164 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7165 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7166 syncobj_handle
= sem
->temporary
.syncobj
;
7168 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7169 syncobj_handle
= sem
->permanent
.syncobj
;
7172 switch(pGetFdInfo
->handleType
) {
7173 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7174 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7176 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7177 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7179 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7180 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7182 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7187 unreachable("Unhandled semaphore handle type");
7191 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7195 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7196 VkPhysicalDevice physicalDevice
,
7197 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7198 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7200 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7201 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7203 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7204 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7205 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7206 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7208 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7209 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7210 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7211 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7212 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7213 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7214 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7215 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7216 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7217 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7218 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7219 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7220 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7222 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7223 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7224 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7228 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7229 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7231 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7232 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7233 uint32_t *syncobj_dst
= NULL
;
7236 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7237 syncobj_dst
= &fence
->temp_syncobj
;
7239 syncobj_dst
= &fence
->syncobj
;
7242 switch(pImportFenceFdInfo
->handleType
) {
7243 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7244 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7245 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7246 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7248 unreachable("Unhandled fence handle type");
7252 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7253 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7256 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7257 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7259 uint32_t syncobj_handle
;
7261 if (fence
->temp_syncobj
)
7262 syncobj_handle
= fence
->temp_syncobj
;
7264 syncobj_handle
= fence
->syncobj
;
7266 switch(pGetFdInfo
->handleType
) {
7267 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7268 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7270 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7271 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7273 if (fence
->temp_syncobj
) {
7274 close (fence
->temp_syncobj
);
7275 fence
->temp_syncobj
= 0;
7277 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7282 unreachable("Unhandled fence handle type");
7286 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7290 void radv_GetPhysicalDeviceExternalFenceProperties(
7291 VkPhysicalDevice physicalDevice
,
7292 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7293 VkExternalFenceProperties
*pExternalFenceProperties
)
7295 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7297 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7298 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7299 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7300 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7301 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7302 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7303 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7305 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7306 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7307 pExternalFenceProperties
->externalFenceFeatures
= 0;
7312 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7313 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7314 const VkAllocationCallbacks
* pAllocator
,
7315 VkDebugReportCallbackEXT
* pCallback
)
7317 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7318 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7319 pCreateInfo
, pAllocator
, &instance
->alloc
,
7324 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7325 VkDebugReportCallbackEXT _callback
,
7326 const VkAllocationCallbacks
* pAllocator
)
7328 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7329 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7330 _callback
, pAllocator
, &instance
->alloc
);
7334 radv_DebugReportMessageEXT(VkInstance _instance
,
7335 VkDebugReportFlagsEXT flags
,
7336 VkDebugReportObjectTypeEXT objectType
,
7339 int32_t messageCode
,
7340 const char* pLayerPrefix
,
7341 const char* pMessage
)
7343 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7344 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7345 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7349 radv_GetDeviceGroupPeerMemoryFeatures(
7352 uint32_t localDeviceIndex
,
7353 uint32_t remoteDeviceIndex
,
7354 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7356 assert(localDeviceIndex
== remoteDeviceIndex
);
7358 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7359 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7360 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7361 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7364 static const VkTimeDomainEXT radv_time_domains
[] = {
7365 VK_TIME_DOMAIN_DEVICE_EXT
,
7366 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7367 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7370 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7371 VkPhysicalDevice physicalDevice
,
7372 uint32_t *pTimeDomainCount
,
7373 VkTimeDomainEXT
*pTimeDomains
)
7376 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7378 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7379 vk_outarray_append(&out
, i
) {
7380 *i
= radv_time_domains
[d
];
7384 return vk_outarray_status(&out
);
7388 radv_clock_gettime(clockid_t clock_id
)
7390 struct timespec current
;
7393 ret
= clock_gettime(clock_id
, ¤t
);
7394 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7395 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7399 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7402 VkResult
radv_GetCalibratedTimestampsEXT(
7404 uint32_t timestampCount
,
7405 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7406 uint64_t *pTimestamps
,
7407 uint64_t *pMaxDeviation
)
7409 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7410 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7412 uint64_t begin
, end
;
7413 uint64_t max_clock_period
= 0;
7415 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7417 for (d
= 0; d
< timestampCount
; d
++) {
7418 switch (pTimestampInfos
[d
].timeDomain
) {
7419 case VK_TIME_DOMAIN_DEVICE_EXT
:
7420 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7422 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7423 max_clock_period
= MAX2(max_clock_period
, device_period
);
7425 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7426 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7427 max_clock_period
= MAX2(max_clock_period
, 1);
7430 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7431 pTimestamps
[d
] = begin
;
7439 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7442 * The maximum deviation is the sum of the interval over which we
7443 * perform the sampling and the maximum period of any sampled
7444 * clock. That's because the maximum skew between any two sampled
7445 * clock edges is when the sampled clock with the largest period is
7446 * sampled at the end of that period but right at the beginning of the
7447 * sampling interval and some other clock is sampled right at the
7448 * begining of its sampling period and right at the end of the
7449 * sampling interval. Let's assume the GPU has the longest clock
7450 * period and that the application is sampling GPU and monotonic:
7453 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7454 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7458 * GPU -----_____-----_____-----_____-----_____
7461 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7462 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7464 * Interval <----------------->
7465 * Deviation <-------------------------->
7469 * m = read(monotonic) 2
7472 * We round the sample interval up by one tick to cover sampling error
7473 * in the interval clock
7476 uint64_t sample_interval
= end
- begin
+ 1;
7478 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7483 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7484 VkPhysicalDevice physicalDevice
,
7485 VkSampleCountFlagBits samples
,
7486 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7488 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7489 VK_SAMPLE_COUNT_4_BIT
|
7490 VK_SAMPLE_COUNT_8_BIT
)) {
7491 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7493 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };