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radv/amdgpu: Support a preamble CS.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static const VkExtensionProperties instance_extensions[] = {
81 {
82 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
83 .specVersion = 25,
84 },
85 #ifdef VK_USE_PLATFORM_XCB_KHR
86 {
87 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_XLIB_KHR
92 {
93 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
98 {
99 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
100 .specVersion = 5,
101 },
102 #endif
103 };
104
105 static const VkExtensionProperties common_device_extensions[] = {
106 {
107 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
112 .specVersion = 68,
113 },
114 {
115 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
116 .specVersion = 1,
117 },
118 {
119 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 };
123
124 static VkResult
125 radv_extensions_register(struct radv_instance *instance,
126 struct radv_extensions *extensions,
127 const VkExtensionProperties *new_ext,
128 uint32_t num_ext)
129 {
130 size_t new_size;
131 VkExtensionProperties *new_ptr;
132
133 assert(new_ext && num_ext > 0);
134
135 if (!new_ext)
136 return VK_ERROR_INITIALIZATION_FAILED;
137
138 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
139 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
140 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
141
142 /* Old array continues to be valid, update nothing */
143 if (!new_ptr)
144 return VK_ERROR_OUT_OF_HOST_MEMORY;
145
146 memcpy(&new_ptr[extensions->num_ext], new_ext,
147 num_ext * sizeof(VkExtensionProperties));
148 extensions->ext_array = new_ptr;
149 extensions->num_ext += num_ext;
150
151 return VK_SUCCESS;
152 }
153
154 static void
155 radv_extensions_finish(struct radv_instance *instance,
156 struct radv_extensions *extensions)
157 {
158 assert(extensions);
159
160 if (!extensions)
161 radv_loge("Attemted to free invalid extension struct\n");
162
163 if (extensions->ext_array)
164 vk_free(&instance->alloc, extensions->ext_array);
165 }
166
167 static bool
168 is_extension_enabled(const VkExtensionProperties *extensions,
169 size_t num_ext,
170 const char *name)
171 {
172 assert(extensions && name);
173
174 for (uint32_t i = 0; i < num_ext; i++) {
175 if (strcmp(name, extensions[i].extensionName) == 0)
176 return true;
177 }
178
179 return false;
180 }
181
182 static VkResult
183 radv_physical_device_init(struct radv_physical_device *device,
184 struct radv_instance *instance,
185 const char *path)
186 {
187 VkResult result;
188 drmVersionPtr version;
189 int fd;
190
191 fd = open(path, O_RDWR | O_CLOEXEC);
192 if (fd < 0)
193 return VK_ERROR_INCOMPATIBLE_DRIVER;
194
195 version = drmGetVersion(fd);
196 if (!version) {
197 close(fd);
198 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
199 "failed to get version %s: %m", path);
200 }
201
202 if (strcmp(version->name, "amdgpu")) {
203 drmFreeVersion(version);
204 close(fd);
205 return VK_ERROR_INCOMPATIBLE_DRIVER;
206 }
207 drmFreeVersion(version);
208
209 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
210 device->instance = instance;
211 assert(strlen(path) < ARRAY_SIZE(device->path));
212 strncpy(device->path, path, ARRAY_SIZE(device->path));
213
214 device->ws = radv_amdgpu_winsys_create(fd);
215 if (!device->ws) {
216 result = VK_ERROR_INCOMPATIBLE_DRIVER;
217 goto fail;
218 }
219 device->ws->query_info(device->ws, &device->rad_info);
220 result = radv_init_wsi(device);
221 if (result != VK_SUCCESS) {
222 device->ws->destroy(device->ws);
223 goto fail;
224 }
225
226 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
227 radv_finish_wsi(device);
228 device->ws->destroy(device->ws);
229 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
230 "cannot generate UUID");
231 goto fail;
232 }
233
234 result = radv_extensions_register(instance,
235 &device->extensions,
236 common_device_extensions,
237 ARRAY_SIZE(common_device_extensions));
238 if (result != VK_SUCCESS)
239 goto fail;
240
241 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
242 device->name = device->rad_info.name;
243 close(fd);
244 return VK_SUCCESS;
245
246 fail:
247 close(fd);
248 return result;
249 }
250
251 static void
252 radv_physical_device_finish(struct radv_physical_device *device)
253 {
254 radv_extensions_finish(device->instance, &device->extensions);
255 radv_finish_wsi(device);
256 device->ws->destroy(device->ws);
257 }
258
259
260 static void *
261 default_alloc_func(void *pUserData, size_t size, size_t align,
262 VkSystemAllocationScope allocationScope)
263 {
264 return malloc(size);
265 }
266
267 static void *
268 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
269 size_t align, VkSystemAllocationScope allocationScope)
270 {
271 return realloc(pOriginal, size);
272 }
273
274 static void
275 default_free_func(void *pUserData, void *pMemory)
276 {
277 free(pMemory);
278 }
279
280 static const VkAllocationCallbacks default_alloc = {
281 .pUserData = NULL,
282 .pfnAllocation = default_alloc_func,
283 .pfnReallocation = default_realloc_func,
284 .pfnFree = default_free_func,
285 };
286
287 static const struct debug_control radv_debug_options[] = {
288 {"fastclears", RADV_DEBUG_FAST_CLEARS},
289 {"nodcc", RADV_DEBUG_NO_DCC},
290 {"shaders", RADV_DEBUG_DUMP_SHADERS},
291 {"nocache", RADV_DEBUG_NO_CACHE},
292 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
293 {"nohiz", RADV_DEBUG_NO_HIZ},
294 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
295 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
296 {NULL, 0}
297 };
298
299 VkResult radv_CreateInstance(
300 const VkInstanceCreateInfo* pCreateInfo,
301 const VkAllocationCallbacks* pAllocator,
302 VkInstance* pInstance)
303 {
304 struct radv_instance *instance;
305
306 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
307
308 uint32_t client_version;
309 if (pCreateInfo->pApplicationInfo &&
310 pCreateInfo->pApplicationInfo->apiVersion != 0) {
311 client_version = pCreateInfo->pApplicationInfo->apiVersion;
312 } else {
313 client_version = VK_MAKE_VERSION(1, 0, 0);
314 }
315
316 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
317 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
318 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
319 "Client requested version %d.%d.%d",
320 VK_VERSION_MAJOR(client_version),
321 VK_VERSION_MINOR(client_version),
322 VK_VERSION_PATCH(client_version));
323 }
324
325 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
326 if (!is_extension_enabled(instance_extensions,
327 ARRAY_SIZE(instance_extensions),
328 pCreateInfo->ppEnabledExtensionNames[i]))
329 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
330 }
331
332 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
333 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
334 if (!instance)
335 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
336
337 memset(instance, 0, sizeof(*instance));
338
339 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
340
341 if (pAllocator)
342 instance->alloc = *pAllocator;
343 else
344 instance->alloc = default_alloc;
345
346 instance->apiVersion = client_version;
347 instance->physicalDeviceCount = -1;
348
349 _mesa_locale_init();
350
351 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
352
353 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
354 radv_debug_options);
355
356 *pInstance = radv_instance_to_handle(instance);
357
358 return VK_SUCCESS;
359 }
360
361 void radv_DestroyInstance(
362 VkInstance _instance,
363 const VkAllocationCallbacks* pAllocator)
364 {
365 RADV_FROM_HANDLE(radv_instance, instance, _instance);
366
367 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
368 radv_physical_device_finish(instance->physicalDevices + i);
369 }
370
371 VG(VALGRIND_DESTROY_MEMPOOL(instance));
372
373 _mesa_locale_fini();
374
375 vk_free(&instance->alloc, instance);
376 }
377
378 VkResult radv_EnumeratePhysicalDevices(
379 VkInstance _instance,
380 uint32_t* pPhysicalDeviceCount,
381 VkPhysicalDevice* pPhysicalDevices)
382 {
383 RADV_FROM_HANDLE(radv_instance, instance, _instance);
384 VkResult result;
385
386 if (instance->physicalDeviceCount < 0) {
387 char path[20];
388 instance->physicalDeviceCount = 0;
389 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
390 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
391 result = radv_physical_device_init(instance->physicalDevices +
392 instance->physicalDeviceCount,
393 instance, path);
394 if (result == VK_SUCCESS)
395 ++instance->physicalDeviceCount;
396 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
397 return result;
398 }
399 }
400
401 if (!pPhysicalDevices) {
402 *pPhysicalDeviceCount = instance->physicalDeviceCount;
403 } else {
404 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
405 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
406 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
407 }
408
409 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
410 : VK_SUCCESS;
411 }
412
413 void radv_GetPhysicalDeviceFeatures(
414 VkPhysicalDevice physicalDevice,
415 VkPhysicalDeviceFeatures* pFeatures)
416 {
417 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
418
419 memset(pFeatures, 0, sizeof(*pFeatures));
420
421 *pFeatures = (VkPhysicalDeviceFeatures) {
422 .robustBufferAccess = true,
423 .fullDrawIndexUint32 = true,
424 .imageCubeArray = true,
425 .independentBlend = true,
426 .geometryShader = false,
427 .tessellationShader = false,
428 .sampleRateShading = false,
429 .dualSrcBlend = true,
430 .logicOp = true,
431 .multiDrawIndirect = true,
432 .drawIndirectFirstInstance = true,
433 .depthClamp = true,
434 .depthBiasClamp = true,
435 .fillModeNonSolid = true,
436 .depthBounds = true,
437 .wideLines = true,
438 .largePoints = true,
439 .alphaToOne = true,
440 .multiViewport = false,
441 .samplerAnisotropy = true,
442 .textureCompressionETC2 = false,
443 .textureCompressionASTC_LDR = false,
444 .textureCompressionBC = true,
445 .occlusionQueryPrecise = true,
446 .pipelineStatisticsQuery = false,
447 .vertexPipelineStoresAndAtomics = true,
448 .fragmentStoresAndAtomics = true,
449 .shaderTessellationAndGeometryPointSize = true,
450 .shaderImageGatherExtended = true,
451 .shaderStorageImageExtendedFormats = true,
452 .shaderStorageImageMultisample = false,
453 .shaderUniformBufferArrayDynamicIndexing = true,
454 .shaderSampledImageArrayDynamicIndexing = true,
455 .shaderStorageBufferArrayDynamicIndexing = true,
456 .shaderStorageImageArrayDynamicIndexing = true,
457 .shaderStorageImageReadWithoutFormat = false,
458 .shaderStorageImageWriteWithoutFormat = false,
459 .shaderClipDistance = true,
460 .shaderCullDistance = true,
461 .shaderFloat64 = false,
462 .shaderInt64 = false,
463 .shaderInt16 = false,
464 .alphaToOne = true,
465 .variableMultisampleRate = false,
466 .inheritedQueries = false,
467 };
468 }
469
470 void radv_GetPhysicalDeviceFeatures2KHR(
471 VkPhysicalDevice physicalDevice,
472 VkPhysicalDeviceFeatures2KHR *pFeatures)
473 {
474 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
475 }
476
477 void radv_GetPhysicalDeviceProperties(
478 VkPhysicalDevice physicalDevice,
479 VkPhysicalDeviceProperties* pProperties)
480 {
481 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
482 VkSampleCountFlags sample_counts = 0xf;
483 VkPhysicalDeviceLimits limits = {
484 .maxImageDimension1D = (1 << 14),
485 .maxImageDimension2D = (1 << 14),
486 .maxImageDimension3D = (1 << 11),
487 .maxImageDimensionCube = (1 << 14),
488 .maxImageArrayLayers = (1 << 11),
489 .maxTexelBufferElements = 128 * 1024 * 1024,
490 .maxUniformBufferRange = UINT32_MAX,
491 .maxStorageBufferRange = UINT32_MAX,
492 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
493 .maxMemoryAllocationCount = UINT32_MAX,
494 .maxSamplerAllocationCount = 64 * 1024,
495 .bufferImageGranularity = 64, /* A cache line */
496 .sparseAddressSpaceSize = 0,
497 .maxBoundDescriptorSets = MAX_SETS,
498 .maxPerStageDescriptorSamplers = 64,
499 .maxPerStageDescriptorUniformBuffers = 64,
500 .maxPerStageDescriptorStorageBuffers = 64,
501 .maxPerStageDescriptorSampledImages = 64,
502 .maxPerStageDescriptorStorageImages = 64,
503 .maxPerStageDescriptorInputAttachments = 64,
504 .maxPerStageResources = 128,
505 .maxDescriptorSetSamplers = 256,
506 .maxDescriptorSetUniformBuffers = 256,
507 .maxDescriptorSetUniformBuffersDynamic = 256,
508 .maxDescriptorSetStorageBuffers = 256,
509 .maxDescriptorSetStorageBuffersDynamic = 256,
510 .maxDescriptorSetSampledImages = 256,
511 .maxDescriptorSetStorageImages = 256,
512 .maxDescriptorSetInputAttachments = 256,
513 .maxVertexInputAttributes = 32,
514 .maxVertexInputBindings = 32,
515 .maxVertexInputAttributeOffset = 2047,
516 .maxVertexInputBindingStride = 2048,
517 .maxVertexOutputComponents = 128,
518 .maxTessellationGenerationLevel = 0,
519 .maxTessellationPatchSize = 0,
520 .maxTessellationControlPerVertexInputComponents = 0,
521 .maxTessellationControlPerVertexOutputComponents = 0,
522 .maxTessellationControlPerPatchOutputComponents = 0,
523 .maxTessellationControlTotalOutputComponents = 0,
524 .maxTessellationEvaluationInputComponents = 0,
525 .maxTessellationEvaluationOutputComponents = 0,
526 .maxGeometryShaderInvocations = 32,
527 .maxGeometryInputComponents = 64,
528 .maxGeometryOutputComponents = 128,
529 .maxGeometryOutputVertices = 256,
530 .maxGeometryTotalOutputComponents = 1024,
531 .maxFragmentInputComponents = 128,
532 .maxFragmentOutputAttachments = 8,
533 .maxFragmentDualSrcAttachments = 1,
534 .maxFragmentCombinedOutputResources = 8,
535 .maxComputeSharedMemorySize = 32768,
536 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
537 .maxComputeWorkGroupInvocations = 2048,
538 .maxComputeWorkGroupSize = {
539 2048,
540 2048,
541 2048
542 },
543 .subPixelPrecisionBits = 4 /* FIXME */,
544 .subTexelPrecisionBits = 4 /* FIXME */,
545 .mipmapPrecisionBits = 4 /* FIXME */,
546 .maxDrawIndexedIndexValue = UINT32_MAX,
547 .maxDrawIndirectCount = UINT32_MAX,
548 .maxSamplerLodBias = 16,
549 .maxSamplerAnisotropy = 16,
550 .maxViewports = MAX_VIEWPORTS,
551 .maxViewportDimensions = { (1 << 14), (1 << 14) },
552 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
553 .viewportSubPixelBits = 13, /* We take a float? */
554 .minMemoryMapAlignment = 4096, /* A page */
555 .minTexelBufferOffsetAlignment = 1,
556 .minUniformBufferOffsetAlignment = 4,
557 .minStorageBufferOffsetAlignment = 4,
558 .minTexelOffset = -32,
559 .maxTexelOffset = 31,
560 .minTexelGatherOffset = -32,
561 .maxTexelGatherOffset = 31,
562 .minInterpolationOffset = -2,
563 .maxInterpolationOffset = 2,
564 .subPixelInterpolationOffsetBits = 8,
565 .maxFramebufferWidth = (1 << 14),
566 .maxFramebufferHeight = (1 << 14),
567 .maxFramebufferLayers = (1 << 10),
568 .framebufferColorSampleCounts = sample_counts,
569 .framebufferDepthSampleCounts = sample_counts,
570 .framebufferStencilSampleCounts = sample_counts,
571 .framebufferNoAttachmentsSampleCounts = sample_counts,
572 .maxColorAttachments = MAX_RTS,
573 .sampledImageColorSampleCounts = sample_counts,
574 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
575 .sampledImageDepthSampleCounts = sample_counts,
576 .sampledImageStencilSampleCounts = sample_counts,
577 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
578 .maxSampleMaskWords = 1,
579 .timestampComputeAndGraphics = false,
580 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
581 .maxClipDistances = 8,
582 .maxCullDistances = 8,
583 .maxCombinedClipAndCullDistances = 8,
584 .discreteQueuePriorities = 1,
585 .pointSizeRange = { 0.125, 255.875 },
586 .lineWidthRange = { 0.0, 7.9921875 },
587 .pointSizeGranularity = (1.0 / 8.0),
588 .lineWidthGranularity = (1.0 / 128.0),
589 .strictLines = false, /* FINISHME */
590 .standardSampleLocations = true,
591 .optimalBufferCopyOffsetAlignment = 128,
592 .optimalBufferCopyRowPitchAlignment = 128,
593 .nonCoherentAtomSize = 64,
594 };
595
596 *pProperties = (VkPhysicalDeviceProperties) {
597 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
598 .driverVersion = 1,
599 .vendorID = 0x1002,
600 .deviceID = pdevice->rad_info.pci_id,
601 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
602 .limits = limits,
603 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
604 };
605
606 strcpy(pProperties->deviceName, pdevice->name);
607 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
608 }
609
610 void radv_GetPhysicalDeviceProperties2KHR(
611 VkPhysicalDevice physicalDevice,
612 VkPhysicalDeviceProperties2KHR *pProperties)
613 {
614 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
615 }
616
617 void radv_GetPhysicalDeviceQueueFamilyProperties(
618 VkPhysicalDevice physicalDevice,
619 uint32_t* pCount,
620 VkQueueFamilyProperties* pQueueFamilyProperties)
621 {
622 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
623 int num_queue_families = 1;
624 int idx;
625 if (pdevice->rad_info.compute_rings > 0 &&
626 pdevice->rad_info.chip_class >= CIK &&
627 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
628 num_queue_families++;
629
630 if (pQueueFamilyProperties == NULL) {
631 *pCount = num_queue_families;
632 return;
633 }
634
635 if (!*pCount)
636 return;
637
638 idx = 0;
639 if (*pCount >= 1) {
640 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
641 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
642 VK_QUEUE_COMPUTE_BIT |
643 VK_QUEUE_TRANSFER_BIT,
644 .queueCount = 1,
645 .timestampValidBits = 64,
646 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
647 };
648 idx++;
649 }
650
651 if (pdevice->rad_info.compute_rings > 0 &&
652 pdevice->rad_info.chip_class >= CIK &&
653 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
654 if (*pCount > idx) {
655 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
656 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
657 .queueCount = pdevice->rad_info.compute_rings,
658 .timestampValidBits = 64,
659 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
660 };
661 idx++;
662 }
663 }
664 *pCount = idx;
665 }
666
667 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
668 VkPhysicalDevice physicalDevice,
669 uint32_t* pCount,
670 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
671 {
672 return radv_GetPhysicalDeviceQueueFamilyProperties(physicalDevice,
673 pCount,
674 &pQueueFamilyProperties->queueFamilyProperties);
675 }
676
677 void radv_GetPhysicalDeviceMemoryProperties(
678 VkPhysicalDevice physicalDevice,
679 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
680 {
681 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
682
683 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
684
685 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
686 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
687 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
688 .heapIndex = RADV_MEM_HEAP_VRAM,
689 };
690 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
691 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
692 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
693 .heapIndex = RADV_MEM_HEAP_GTT,
694 };
695 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
696 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
697 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
698 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
699 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
700 };
701 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
702 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
703 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
704 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
705 .heapIndex = RADV_MEM_HEAP_GTT,
706 };
707
708 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
709
710 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
711 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
712 .size = physical_device->rad_info.vram_size -
713 physical_device->rad_info.visible_vram_size,
714 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
715 };
716 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
717 .size = physical_device->rad_info.visible_vram_size,
718 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
719 };
720 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
721 .size = physical_device->rad_info.gart_size,
722 .flags = 0,
723 };
724 }
725
726 void radv_GetPhysicalDeviceMemoryProperties2KHR(
727 VkPhysicalDevice physicalDevice,
728 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
729 {
730 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
731 &pMemoryProperties->memoryProperties);
732 }
733
734 static int
735 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
736 int queue_family_index, int idx)
737 {
738 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
739 queue->device = device;
740 queue->queue_family_index = queue_family_index;
741 queue->queue_idx = idx;
742
743 queue->hw_ctx = device->ws->ctx_create(device->ws);
744 if (!queue->hw_ctx)
745 return VK_ERROR_OUT_OF_HOST_MEMORY;
746
747 return VK_SUCCESS;
748 }
749
750 static void
751 radv_queue_finish(struct radv_queue *queue)
752 {
753 if (queue->hw_ctx)
754 queue->device->ws->ctx_destroy(queue->hw_ctx);
755 }
756
757 VkResult radv_CreateDevice(
758 VkPhysicalDevice physicalDevice,
759 const VkDeviceCreateInfo* pCreateInfo,
760 const VkAllocationCallbacks* pAllocator,
761 VkDevice* pDevice)
762 {
763 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
764 VkResult result;
765 struct radv_device *device;
766
767 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
768 if (!is_extension_enabled(physical_device->extensions.ext_array,
769 physical_device->extensions.num_ext,
770 pCreateInfo->ppEnabledExtensionNames[i]))
771 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
772 }
773
774 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
775 sizeof(*device), 8,
776 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
777 if (!device)
778 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
779
780 memset(device, 0, sizeof(*device));
781
782 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
783 device->instance = physical_device->instance;
784 device->physical_device = physical_device;
785
786 device->debug_flags = device->instance->debug_flags;
787
788 device->ws = physical_device->ws;
789 if (pAllocator)
790 device->alloc = *pAllocator;
791 else
792 device->alloc = physical_device->instance->alloc;
793
794 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
795 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
796 uint32_t qfi = queue_create->queueFamilyIndex;
797
798 device->queues[qfi] = vk_alloc(&device->alloc,
799 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
800 if (!device->queues[qfi]) {
801 result = VK_ERROR_OUT_OF_HOST_MEMORY;
802 goto fail;
803 }
804
805 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
806
807 device->queue_count[qfi] = queue_create->queueCount;
808
809 for (unsigned q = 0; q < queue_create->queueCount; q++) {
810 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
811 if (result != VK_SUCCESS)
812 goto fail;
813 }
814 }
815
816 result = radv_device_init_meta(device);
817 if (result != VK_SUCCESS)
818 goto fail;
819
820 radv_device_init_msaa(device);
821
822 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
823 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
824 switch (family) {
825 case RADV_QUEUE_GENERAL:
826 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
827 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
828 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
829 break;
830 case RADV_QUEUE_COMPUTE:
831 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
832 radeon_emit(device->empty_cs[family], 0);
833 break;
834 }
835 device->ws->cs_finalize(device->empty_cs[family]);
836 }
837
838 if (getenv("RADV_TRACE_FILE")) {
839 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
840 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
841 if (!device->trace_bo)
842 goto fail;
843
844 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
845 if (!device->trace_id_ptr)
846 goto fail;
847 }
848
849 *pDevice = radv_device_to_handle(device);
850 return VK_SUCCESS;
851
852 fail:
853 if (device->trace_bo)
854 device->ws->buffer_destroy(device->trace_bo);
855
856 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
857 for (unsigned q = 0; q < device->queue_count[i]; q++)
858 radv_queue_finish(&device->queues[i][q]);
859 if (device->queue_count[i])
860 vk_free(&device->alloc, device->queues[i]);
861 }
862
863 vk_free(&device->alloc, device);
864 return result;
865 }
866
867 void radv_DestroyDevice(
868 VkDevice _device,
869 const VkAllocationCallbacks* pAllocator)
870 {
871 RADV_FROM_HANDLE(radv_device, device, _device);
872
873 if (device->trace_bo)
874 device->ws->buffer_destroy(device->trace_bo);
875
876 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
877 for (unsigned q = 0; q < device->queue_count[i]; q++)
878 radv_queue_finish(&device->queues[i][q]);
879 if (device->queue_count[i])
880 vk_free(&device->alloc, device->queues[i]);
881 }
882 radv_device_finish_meta(device);
883
884 vk_free(&device->alloc, device);
885 }
886
887 VkResult radv_EnumerateInstanceExtensionProperties(
888 const char* pLayerName,
889 uint32_t* pPropertyCount,
890 VkExtensionProperties* pProperties)
891 {
892 if (pProperties == NULL) {
893 *pPropertyCount = ARRAY_SIZE(instance_extensions);
894 return VK_SUCCESS;
895 }
896
897 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
898 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
899
900 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
901 return VK_INCOMPLETE;
902
903 return VK_SUCCESS;
904 }
905
906 VkResult radv_EnumerateDeviceExtensionProperties(
907 VkPhysicalDevice physicalDevice,
908 const char* pLayerName,
909 uint32_t* pPropertyCount,
910 VkExtensionProperties* pProperties)
911 {
912 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
913
914 if (pProperties == NULL) {
915 *pPropertyCount = pdevice->extensions.num_ext;
916 return VK_SUCCESS;
917 }
918
919 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
920 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
921
922 if (*pPropertyCount < pdevice->extensions.num_ext)
923 return VK_INCOMPLETE;
924
925 return VK_SUCCESS;
926 }
927
928 VkResult radv_EnumerateInstanceLayerProperties(
929 uint32_t* pPropertyCount,
930 VkLayerProperties* pProperties)
931 {
932 if (pProperties == NULL) {
933 *pPropertyCount = 0;
934 return VK_SUCCESS;
935 }
936
937 /* None supported at this time */
938 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
939 }
940
941 VkResult radv_EnumerateDeviceLayerProperties(
942 VkPhysicalDevice physicalDevice,
943 uint32_t* pPropertyCount,
944 VkLayerProperties* pProperties)
945 {
946 if (pProperties == NULL) {
947 *pPropertyCount = 0;
948 return VK_SUCCESS;
949 }
950
951 /* None supported at this time */
952 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
953 }
954
955 void radv_GetDeviceQueue(
956 VkDevice _device,
957 uint32_t queueFamilyIndex,
958 uint32_t queueIndex,
959 VkQueue* pQueue)
960 {
961 RADV_FROM_HANDLE(radv_device, device, _device);
962
963 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
964 }
965
966 static void radv_dump_trace(struct radv_device *device,
967 struct radeon_winsys_cs *cs)
968 {
969 const char *filename = getenv("RADV_TRACE_FILE");
970 FILE *f = fopen(filename, "w");
971 if (!f) {
972 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
973 return;
974 }
975
976 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
977 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
978 fclose(f);
979 }
980
981 VkResult radv_QueueSubmit(
982 VkQueue _queue,
983 uint32_t submitCount,
984 const VkSubmitInfo* pSubmits,
985 VkFence _fence)
986 {
987 RADV_FROM_HANDLE(radv_queue, queue, _queue);
988 RADV_FROM_HANDLE(radv_fence, fence, _fence);
989 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
990 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
991 int ret;
992 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
993
994 for (uint32_t i = 0; i < submitCount; i++) {
995 struct radeon_winsys_cs **cs_array;
996 bool can_patch = true;
997 uint32_t advance;
998
999 if (!pSubmits[i].commandBufferCount)
1000 continue;
1001
1002 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1003 pSubmits[i].commandBufferCount);
1004
1005 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1007 pSubmits[i].pCommandBuffers[j]);
1008 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1009
1010 cs_array[j] = cmd_buffer->cs;
1011 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1012 can_patch = false;
1013 }
1014
1015 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1016 advance = MIN2(max_cs_submission,
1017 pSubmits[i].commandBufferCount - j);
1018 bool b = j == 0;
1019 bool e = j + advance == pSubmits[i].commandBufferCount;
1020
1021 if (queue->device->trace_bo)
1022 *queue->device->trace_id_ptr = 0;
1023
1024 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1025 advance, NULL,
1026 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1027 b ? pSubmits[i].waitSemaphoreCount : 0,
1028 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1029 e ? pSubmits[i].signalSemaphoreCount : 0,
1030 can_patch, base_fence);
1031
1032 if (ret) {
1033 radv_loge("failed to submit CS %d\n", i);
1034 abort();
1035 }
1036 if (queue->device->trace_bo) {
1037 bool success = queue->device->ws->ctx_wait_idle(
1038 queue->hw_ctx,
1039 radv_queue_family_to_ring(
1040 queue->queue_family_index),
1041 queue->queue_idx);
1042
1043 if (!success) { /* Hang */
1044 radv_dump_trace(queue->device, cs_array[j]);
1045 abort();
1046 }
1047 }
1048 }
1049 free(cs_array);
1050 }
1051
1052 if (fence) {
1053 if (!submitCount)
1054 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1055 &queue->device->empty_cs[queue->queue_family_index],
1056 1, NULL, NULL, 0, NULL, 0,
1057 false, base_fence);
1058
1059 fence->submitted = true;
1060 }
1061
1062 return VK_SUCCESS;
1063 }
1064
1065 VkResult radv_QueueWaitIdle(
1066 VkQueue _queue)
1067 {
1068 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1069
1070 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1071 radv_queue_family_to_ring(queue->queue_family_index),
1072 queue->queue_idx);
1073 return VK_SUCCESS;
1074 }
1075
1076 VkResult radv_DeviceWaitIdle(
1077 VkDevice _device)
1078 {
1079 RADV_FROM_HANDLE(radv_device, device, _device);
1080
1081 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1082 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1083 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1084 }
1085 }
1086 return VK_SUCCESS;
1087 }
1088
1089 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1090 VkInstance instance,
1091 const char* pName)
1092 {
1093 return radv_lookup_entrypoint(pName);
1094 }
1095
1096 /* The loader wants us to expose a second GetInstanceProcAddr function
1097 * to work around certain LD_PRELOAD issues seen in apps.
1098 */
1099 PUBLIC
1100 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1101 VkInstance instance,
1102 const char* pName);
1103
1104 PUBLIC
1105 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1106 VkInstance instance,
1107 const char* pName)
1108 {
1109 return radv_GetInstanceProcAddr(instance, pName);
1110 }
1111
1112 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1113 VkDevice device,
1114 const char* pName)
1115 {
1116 return radv_lookup_entrypoint(pName);
1117 }
1118
1119 VkResult radv_AllocateMemory(
1120 VkDevice _device,
1121 const VkMemoryAllocateInfo* pAllocateInfo,
1122 const VkAllocationCallbacks* pAllocator,
1123 VkDeviceMemory* pMem)
1124 {
1125 RADV_FROM_HANDLE(radv_device, device, _device);
1126 struct radv_device_memory *mem;
1127 VkResult result;
1128 enum radeon_bo_domain domain;
1129 uint32_t flags = 0;
1130 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1131
1132 if (pAllocateInfo->allocationSize == 0) {
1133 /* Apparently, this is allowed */
1134 *pMem = VK_NULL_HANDLE;
1135 return VK_SUCCESS;
1136 }
1137
1138 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1139 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1140 if (mem == NULL)
1141 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1142
1143 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1144 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1145 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1146 domain = RADEON_DOMAIN_GTT;
1147 else
1148 domain = RADEON_DOMAIN_VRAM;
1149
1150 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1151 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1152 else
1153 flags |= RADEON_FLAG_CPU_ACCESS;
1154
1155 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1156 flags |= RADEON_FLAG_GTT_WC;
1157
1158 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1159 domain, flags);
1160
1161 if (!mem->bo) {
1162 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1163 goto fail;
1164 }
1165 mem->type_index = pAllocateInfo->memoryTypeIndex;
1166
1167 *pMem = radv_device_memory_to_handle(mem);
1168
1169 return VK_SUCCESS;
1170
1171 fail:
1172 vk_free2(&device->alloc, pAllocator, mem);
1173
1174 return result;
1175 }
1176
1177 void radv_FreeMemory(
1178 VkDevice _device,
1179 VkDeviceMemory _mem,
1180 const VkAllocationCallbacks* pAllocator)
1181 {
1182 RADV_FROM_HANDLE(radv_device, device, _device);
1183 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1184
1185 if (mem == NULL)
1186 return;
1187
1188 device->ws->buffer_destroy(mem->bo);
1189 mem->bo = NULL;
1190
1191 vk_free2(&device->alloc, pAllocator, mem);
1192 }
1193
1194 VkResult radv_MapMemory(
1195 VkDevice _device,
1196 VkDeviceMemory _memory,
1197 VkDeviceSize offset,
1198 VkDeviceSize size,
1199 VkMemoryMapFlags flags,
1200 void** ppData)
1201 {
1202 RADV_FROM_HANDLE(radv_device, device, _device);
1203 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1204
1205 if (mem == NULL) {
1206 *ppData = NULL;
1207 return VK_SUCCESS;
1208 }
1209
1210 *ppData = device->ws->buffer_map(mem->bo);
1211 if (*ppData) {
1212 *ppData += offset;
1213 return VK_SUCCESS;
1214 }
1215
1216 return VK_ERROR_MEMORY_MAP_FAILED;
1217 }
1218
1219 void radv_UnmapMemory(
1220 VkDevice _device,
1221 VkDeviceMemory _memory)
1222 {
1223 RADV_FROM_HANDLE(radv_device, device, _device);
1224 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1225
1226 if (mem == NULL)
1227 return;
1228
1229 device->ws->buffer_unmap(mem->bo);
1230 }
1231
1232 VkResult radv_FlushMappedMemoryRanges(
1233 VkDevice _device,
1234 uint32_t memoryRangeCount,
1235 const VkMappedMemoryRange* pMemoryRanges)
1236 {
1237 return VK_SUCCESS;
1238 }
1239
1240 VkResult radv_InvalidateMappedMemoryRanges(
1241 VkDevice _device,
1242 uint32_t memoryRangeCount,
1243 const VkMappedMemoryRange* pMemoryRanges)
1244 {
1245 return VK_SUCCESS;
1246 }
1247
1248 void radv_GetBufferMemoryRequirements(
1249 VkDevice device,
1250 VkBuffer _buffer,
1251 VkMemoryRequirements* pMemoryRequirements)
1252 {
1253 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1254
1255 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1256
1257 pMemoryRequirements->size = buffer->size;
1258 pMemoryRequirements->alignment = 16;
1259 }
1260
1261 void radv_GetImageMemoryRequirements(
1262 VkDevice device,
1263 VkImage _image,
1264 VkMemoryRequirements* pMemoryRequirements)
1265 {
1266 RADV_FROM_HANDLE(radv_image, image, _image);
1267
1268 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1269
1270 pMemoryRequirements->size = image->size;
1271 pMemoryRequirements->alignment = image->alignment;
1272 }
1273
1274 void radv_GetImageSparseMemoryRequirements(
1275 VkDevice device,
1276 VkImage image,
1277 uint32_t* pSparseMemoryRequirementCount,
1278 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1279 {
1280 stub();
1281 }
1282
1283 void radv_GetDeviceMemoryCommitment(
1284 VkDevice device,
1285 VkDeviceMemory memory,
1286 VkDeviceSize* pCommittedMemoryInBytes)
1287 {
1288 *pCommittedMemoryInBytes = 0;
1289 }
1290
1291 VkResult radv_BindBufferMemory(
1292 VkDevice device,
1293 VkBuffer _buffer,
1294 VkDeviceMemory _memory,
1295 VkDeviceSize memoryOffset)
1296 {
1297 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1298 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1299
1300 if (mem) {
1301 buffer->bo = mem->bo;
1302 buffer->offset = memoryOffset;
1303 } else {
1304 buffer->bo = NULL;
1305 buffer->offset = 0;
1306 }
1307
1308 return VK_SUCCESS;
1309 }
1310
1311 VkResult radv_BindImageMemory(
1312 VkDevice device,
1313 VkImage _image,
1314 VkDeviceMemory _memory,
1315 VkDeviceSize memoryOffset)
1316 {
1317 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1318 RADV_FROM_HANDLE(radv_image, image, _image);
1319
1320 if (mem) {
1321 image->bo = mem->bo;
1322 image->offset = memoryOffset;
1323 } else {
1324 image->bo = NULL;
1325 image->offset = 0;
1326 }
1327
1328 return VK_SUCCESS;
1329 }
1330
1331 VkResult radv_QueueBindSparse(
1332 VkQueue queue,
1333 uint32_t bindInfoCount,
1334 const VkBindSparseInfo* pBindInfo,
1335 VkFence fence)
1336 {
1337 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1338 }
1339
1340 VkResult radv_CreateFence(
1341 VkDevice _device,
1342 const VkFenceCreateInfo* pCreateInfo,
1343 const VkAllocationCallbacks* pAllocator,
1344 VkFence* pFence)
1345 {
1346 RADV_FROM_HANDLE(radv_device, device, _device);
1347 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1348 sizeof(*fence), 8,
1349 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1350
1351 if (!fence)
1352 return VK_ERROR_OUT_OF_HOST_MEMORY;
1353
1354 memset(fence, 0, sizeof(*fence));
1355 fence->submitted = false;
1356 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1357 fence->fence = device->ws->create_fence();
1358 if (!fence->fence) {
1359 vk_free2(&device->alloc, pAllocator, fence);
1360 return VK_ERROR_OUT_OF_HOST_MEMORY;
1361 }
1362
1363 *pFence = radv_fence_to_handle(fence);
1364
1365 return VK_SUCCESS;
1366 }
1367
1368 void radv_DestroyFence(
1369 VkDevice _device,
1370 VkFence _fence,
1371 const VkAllocationCallbacks* pAllocator)
1372 {
1373 RADV_FROM_HANDLE(radv_device, device, _device);
1374 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1375
1376 if (!fence)
1377 return;
1378 device->ws->destroy_fence(fence->fence);
1379 vk_free2(&device->alloc, pAllocator, fence);
1380 }
1381
1382 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1383 {
1384 uint64_t current_time;
1385 struct timespec tv;
1386
1387 clock_gettime(CLOCK_MONOTONIC, &tv);
1388 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1389
1390 timeout = MIN2(UINT64_MAX - current_time, timeout);
1391
1392 return current_time + timeout;
1393 }
1394
1395 VkResult radv_WaitForFences(
1396 VkDevice _device,
1397 uint32_t fenceCount,
1398 const VkFence* pFences,
1399 VkBool32 waitAll,
1400 uint64_t timeout)
1401 {
1402 RADV_FROM_HANDLE(radv_device, device, _device);
1403 timeout = radv_get_absolute_timeout(timeout);
1404
1405 if (!waitAll && fenceCount > 1) {
1406 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1407 }
1408
1409 for (uint32_t i = 0; i < fenceCount; ++i) {
1410 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1411 bool expired = false;
1412
1413 if (fence->signalled)
1414 continue;
1415
1416 if (!fence->submitted)
1417 return VK_TIMEOUT;
1418
1419 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1420 if (!expired)
1421 return VK_TIMEOUT;
1422
1423 fence->signalled = true;
1424 }
1425
1426 return VK_SUCCESS;
1427 }
1428
1429 VkResult radv_ResetFences(VkDevice device,
1430 uint32_t fenceCount,
1431 const VkFence *pFences)
1432 {
1433 for (unsigned i = 0; i < fenceCount; ++i) {
1434 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1435 fence->submitted = fence->signalled = false;
1436 }
1437
1438 return VK_SUCCESS;
1439 }
1440
1441 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1442 {
1443 RADV_FROM_HANDLE(radv_device, device, _device);
1444 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1445
1446 if (fence->signalled)
1447 return VK_SUCCESS;
1448 if (!fence->submitted)
1449 return VK_NOT_READY;
1450
1451 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1452 return VK_NOT_READY;
1453
1454 return VK_SUCCESS;
1455 }
1456
1457
1458 // Queue semaphore functions
1459
1460 VkResult radv_CreateSemaphore(
1461 VkDevice _device,
1462 const VkSemaphoreCreateInfo* pCreateInfo,
1463 const VkAllocationCallbacks* pAllocator,
1464 VkSemaphore* pSemaphore)
1465 {
1466 RADV_FROM_HANDLE(radv_device, device, _device);
1467 struct radeon_winsys_sem *sem;
1468
1469 sem = device->ws->create_sem(device->ws);
1470 if (!sem)
1471 return VK_ERROR_OUT_OF_HOST_MEMORY;
1472
1473 *pSemaphore = (VkSemaphore)sem;
1474 return VK_SUCCESS;
1475 }
1476
1477 void radv_DestroySemaphore(
1478 VkDevice _device,
1479 VkSemaphore _semaphore,
1480 const VkAllocationCallbacks* pAllocator)
1481 {
1482 RADV_FROM_HANDLE(radv_device, device, _device);
1483 struct radeon_winsys_sem *sem;
1484 if (!_semaphore)
1485 return;
1486
1487 sem = (struct radeon_winsys_sem *)_semaphore;
1488 device->ws->destroy_sem(sem);
1489 }
1490
1491 VkResult radv_CreateEvent(
1492 VkDevice _device,
1493 const VkEventCreateInfo* pCreateInfo,
1494 const VkAllocationCallbacks* pAllocator,
1495 VkEvent* pEvent)
1496 {
1497 RADV_FROM_HANDLE(radv_device, device, _device);
1498 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1499 sizeof(*event), 8,
1500 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1501
1502 if (!event)
1503 return VK_ERROR_OUT_OF_HOST_MEMORY;
1504
1505 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1506 RADEON_DOMAIN_GTT,
1507 RADEON_FLAG_CPU_ACCESS);
1508 if (!event->bo) {
1509 vk_free2(&device->alloc, pAllocator, event);
1510 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1511 }
1512
1513 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1514
1515 *pEvent = radv_event_to_handle(event);
1516
1517 return VK_SUCCESS;
1518 }
1519
1520 void radv_DestroyEvent(
1521 VkDevice _device,
1522 VkEvent _event,
1523 const VkAllocationCallbacks* pAllocator)
1524 {
1525 RADV_FROM_HANDLE(radv_device, device, _device);
1526 RADV_FROM_HANDLE(radv_event, event, _event);
1527
1528 if (!event)
1529 return;
1530 device->ws->buffer_destroy(event->bo);
1531 vk_free2(&device->alloc, pAllocator, event);
1532 }
1533
1534 VkResult radv_GetEventStatus(
1535 VkDevice _device,
1536 VkEvent _event)
1537 {
1538 RADV_FROM_HANDLE(radv_event, event, _event);
1539
1540 if (*event->map == 1)
1541 return VK_EVENT_SET;
1542 return VK_EVENT_RESET;
1543 }
1544
1545 VkResult radv_SetEvent(
1546 VkDevice _device,
1547 VkEvent _event)
1548 {
1549 RADV_FROM_HANDLE(radv_event, event, _event);
1550 *event->map = 1;
1551
1552 return VK_SUCCESS;
1553 }
1554
1555 VkResult radv_ResetEvent(
1556 VkDevice _device,
1557 VkEvent _event)
1558 {
1559 RADV_FROM_HANDLE(radv_event, event, _event);
1560 *event->map = 0;
1561
1562 return VK_SUCCESS;
1563 }
1564
1565 VkResult radv_CreateBuffer(
1566 VkDevice _device,
1567 const VkBufferCreateInfo* pCreateInfo,
1568 const VkAllocationCallbacks* pAllocator,
1569 VkBuffer* pBuffer)
1570 {
1571 RADV_FROM_HANDLE(radv_device, device, _device);
1572 struct radv_buffer *buffer;
1573
1574 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1575
1576 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1577 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1578 if (buffer == NULL)
1579 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1580
1581 buffer->size = pCreateInfo->size;
1582 buffer->usage = pCreateInfo->usage;
1583 buffer->bo = NULL;
1584 buffer->offset = 0;
1585
1586 *pBuffer = radv_buffer_to_handle(buffer);
1587
1588 return VK_SUCCESS;
1589 }
1590
1591 void radv_DestroyBuffer(
1592 VkDevice _device,
1593 VkBuffer _buffer,
1594 const VkAllocationCallbacks* pAllocator)
1595 {
1596 RADV_FROM_HANDLE(radv_device, device, _device);
1597 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1598
1599 if (!buffer)
1600 return;
1601
1602 vk_free2(&device->alloc, pAllocator, buffer);
1603 }
1604
1605 static inline unsigned
1606 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1607 {
1608 if (stencil)
1609 return image->surface.stencil_tiling_index[level];
1610 else
1611 return image->surface.tiling_index[level];
1612 }
1613
1614 static void
1615 radv_initialise_color_surface(struct radv_device *device,
1616 struct radv_color_buffer_info *cb,
1617 struct radv_image_view *iview)
1618 {
1619 const struct vk_format_description *desc;
1620 unsigned ntype, format, swap, endian;
1621 unsigned blend_clamp = 0, blend_bypass = 0;
1622 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1623 uint64_t va;
1624 const struct radeon_surf *surf = &iview->image->surface;
1625 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1626
1627 desc = vk_format_description(iview->vk_format);
1628
1629 memset(cb, 0, sizeof(*cb));
1630
1631 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1632 va += level_info->offset;
1633 cb->cb_color_base = va >> 8;
1634
1635 /* CMASK variables */
1636 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1637 va += iview->image->cmask.offset;
1638 cb->cb_color_cmask = va >> 8;
1639 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1640
1641 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1642 va += iview->image->dcc_offset;
1643 cb->cb_dcc_base = va >> 8;
1644
1645 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
1646 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1647 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
1648
1649 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1650 pitch_tile_max = level_info->nblk_x / 8 - 1;
1651 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1652 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1653
1654 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1655 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1656
1657 /* Intensity is implemented as Red, so treat it that way. */
1658 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1659 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1660
1661 if (iview->image->samples > 1) {
1662 unsigned log_samples = util_logbase2(iview->image->samples);
1663
1664 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1665 S_028C74_NUM_FRAGMENTS(log_samples);
1666 }
1667
1668 if (iview->image->fmask.size) {
1669 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1670 if (device->physical_device->rad_info.chip_class >= CIK)
1671 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1672 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1673 cb->cb_color_fmask = va >> 8;
1674 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1675 } else {
1676 /* This must be set for fast clear to work without FMASK. */
1677 if (device->physical_device->rad_info.chip_class >= CIK)
1678 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1679 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1680 cb->cb_color_fmask = cb->cb_color_base;
1681 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1682 }
1683
1684 ntype = radv_translate_color_numformat(iview->vk_format,
1685 desc,
1686 vk_format_get_first_non_void_channel(iview->vk_format));
1687 format = radv_translate_colorformat(iview->vk_format);
1688 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1689 radv_finishme("Illegal color\n");
1690 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1691 endian = radv_colorformat_endian_swap(format);
1692
1693 /* blend clamp should be set for all NORM/SRGB types */
1694 if (ntype == V_028C70_NUMBER_UNORM ||
1695 ntype == V_028C70_NUMBER_SNORM ||
1696 ntype == V_028C70_NUMBER_SRGB)
1697 blend_clamp = 1;
1698
1699 /* set blend bypass according to docs if SINT/UINT or
1700 8/24 COLOR variants */
1701 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1702 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1703 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1704 blend_clamp = 0;
1705 blend_bypass = 1;
1706 }
1707 #if 0
1708 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1709 (format == V_028C70_COLOR_8 ||
1710 format == V_028C70_COLOR_8_8 ||
1711 format == V_028C70_COLOR_8_8_8_8))
1712 ->color_is_int8 = true;
1713 #endif
1714 cb->cb_color_info = S_028C70_FORMAT(format) |
1715 S_028C70_COMP_SWAP(swap) |
1716 S_028C70_BLEND_CLAMP(blend_clamp) |
1717 S_028C70_BLEND_BYPASS(blend_bypass) |
1718 S_028C70_SIMPLE_FLOAT(1) |
1719 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1720 ntype != V_028C70_NUMBER_SNORM &&
1721 ntype != V_028C70_NUMBER_SRGB &&
1722 format != V_028C70_COLOR_8_24 &&
1723 format != V_028C70_COLOR_24_8) |
1724 S_028C70_NUMBER_TYPE(ntype) |
1725 S_028C70_ENDIAN(endian);
1726 if (iview->image->samples > 1)
1727 if (iview->image->fmask.size)
1728 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1729
1730 if (iview->image->cmask.size &&
1731 (device->debug_flags & RADV_DEBUG_FAST_CLEARS))
1732 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1733
1734 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1735 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1736
1737 if (device->physical_device->rad_info.chip_class >= VI) {
1738 unsigned max_uncompressed_block_size = 2;
1739 if (iview->image->samples > 1) {
1740 if (iview->image->surface.bpe == 1)
1741 max_uncompressed_block_size = 0;
1742 else if (iview->image->surface.bpe == 2)
1743 max_uncompressed_block_size = 1;
1744 }
1745
1746 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1747 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1748 }
1749
1750 /* This must be set for fast clear to work without FMASK. */
1751 if (!iview->image->fmask.size &&
1752 device->physical_device->rad_info.chip_class == SI) {
1753 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1754 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1755 }
1756 }
1757
1758 static void
1759 radv_initialise_ds_surface(struct radv_device *device,
1760 struct radv_ds_buffer_info *ds,
1761 struct radv_image_view *iview)
1762 {
1763 unsigned level = iview->base_mip;
1764 unsigned format;
1765 uint64_t va, s_offs, z_offs;
1766 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1767 memset(ds, 0, sizeof(*ds));
1768 switch (iview->vk_format) {
1769 case VK_FORMAT_D24_UNORM_S8_UINT:
1770 case VK_FORMAT_X8_D24_UNORM_PACK32:
1771 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1772 ds->offset_scale = 2.0f;
1773 break;
1774 case VK_FORMAT_D16_UNORM:
1775 case VK_FORMAT_D16_UNORM_S8_UINT:
1776 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1777 ds->offset_scale = 4.0f;
1778 break;
1779 case VK_FORMAT_D32_SFLOAT:
1780 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1781 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1782 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1783 ds->offset_scale = 1.0f;
1784 break;
1785 default:
1786 break;
1787 }
1788
1789 format = radv_translate_dbformat(iview->vk_format);
1790 if (format == V_028040_Z_INVALID) {
1791 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1792 }
1793
1794 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1795 s_offs = z_offs = va;
1796 z_offs += iview->image->surface.level[level].offset;
1797 s_offs += iview->image->surface.stencil_level[level].offset;
1798
1799 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
1800 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1801 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
1802 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1803 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1804
1805 if (iview->image->samples > 1)
1806 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1807
1808 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1809 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1810 else
1811 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1812
1813 if (device->physical_device->rad_info.chip_class >= CIK) {
1814 struct radeon_info *info = &device->physical_device->rad_info;
1815 unsigned tiling_index = iview->image->surface.tiling_index[level];
1816 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1817 unsigned macro_index = iview->image->surface.macro_tile_index;
1818 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1819 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1820 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1821
1822 ds->db_depth_info |=
1823 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1824 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1825 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1826 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1827 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1828 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1829 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1830 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1831 } else {
1832 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1833 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1834 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1835 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1836 }
1837
1838 if (iview->image->htile.size && !level) {
1839 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1840 S_028040_ALLOW_EXPCLEAR(1);
1841
1842 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1843 /* Workaround: For a not yet understood reason, the
1844 * combination of MSAA, fast stencil clear and stencil
1845 * decompress messes with subsequent stencil buffer
1846 * uses. Problem was reproduced on Verde, Bonaire,
1847 * Tonga, and Carrizo.
1848 *
1849 * Disabling EXPCLEAR works around the problem.
1850 *
1851 * Check piglit's arb_texture_multisample-stencil-clear
1852 * test if you want to try changing this.
1853 */
1854 if (iview->image->samples <= 1)
1855 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1856 } else
1857 /* Use all of the htile_buffer for depth if there's no stencil. */
1858 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1859
1860 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1861 iview->image->htile.offset;
1862 ds->db_htile_data_base = va >> 8;
1863 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1864 } else {
1865 ds->db_htile_data_base = 0;
1866 ds->db_htile_surface = 0;
1867 }
1868
1869 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1870 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1871
1872 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1873 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1874 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1875 }
1876
1877 VkResult radv_CreateFramebuffer(
1878 VkDevice _device,
1879 const VkFramebufferCreateInfo* pCreateInfo,
1880 const VkAllocationCallbacks* pAllocator,
1881 VkFramebuffer* pFramebuffer)
1882 {
1883 RADV_FROM_HANDLE(radv_device, device, _device);
1884 struct radv_framebuffer *framebuffer;
1885
1886 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1887
1888 size_t size = sizeof(*framebuffer) +
1889 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1890 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1891 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1892 if (framebuffer == NULL)
1893 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1894
1895 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1896 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1897 VkImageView _iview = pCreateInfo->pAttachments[i];
1898 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1899 framebuffer->attachments[i].attachment = iview;
1900 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1901 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1902 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1903 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1904 }
1905 }
1906
1907 framebuffer->width = pCreateInfo->width;
1908 framebuffer->height = pCreateInfo->height;
1909 framebuffer->layers = pCreateInfo->layers;
1910
1911 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1912 return VK_SUCCESS;
1913 }
1914
1915 void radv_DestroyFramebuffer(
1916 VkDevice _device,
1917 VkFramebuffer _fb,
1918 const VkAllocationCallbacks* pAllocator)
1919 {
1920 RADV_FROM_HANDLE(radv_device, device, _device);
1921 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1922
1923 if (!fb)
1924 return;
1925 vk_free2(&device->alloc, pAllocator, fb);
1926 }
1927
1928 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1929 {
1930 switch (address_mode) {
1931 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1932 return V_008F30_SQ_TEX_WRAP;
1933 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1934 return V_008F30_SQ_TEX_MIRROR;
1935 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1936 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1937 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1938 return V_008F30_SQ_TEX_CLAMP_BORDER;
1939 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1940 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1941 default:
1942 unreachable("illegal tex wrap mode");
1943 break;
1944 }
1945 }
1946
1947 static unsigned
1948 radv_tex_compare(VkCompareOp op)
1949 {
1950 switch (op) {
1951 case VK_COMPARE_OP_NEVER:
1952 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1953 case VK_COMPARE_OP_LESS:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1955 case VK_COMPARE_OP_EQUAL:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1957 case VK_COMPARE_OP_LESS_OR_EQUAL:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1959 case VK_COMPARE_OP_GREATER:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1961 case VK_COMPARE_OP_NOT_EQUAL:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1963 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1965 case VK_COMPARE_OP_ALWAYS:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1967 default:
1968 unreachable("illegal compare mode");
1969 break;
1970 }
1971 }
1972
1973 static unsigned
1974 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1975 {
1976 switch (filter) {
1977 case VK_FILTER_NEAREST:
1978 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1979 V_008F38_SQ_TEX_XY_FILTER_POINT);
1980 case VK_FILTER_LINEAR:
1981 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1982 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1983 case VK_FILTER_CUBIC_IMG:
1984 default:
1985 fprintf(stderr, "illegal texture filter");
1986 return 0;
1987 }
1988 }
1989
1990 static unsigned
1991 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1992 {
1993 switch (mode) {
1994 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1995 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1996 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1997 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1998 default:
1999 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2000 }
2001 }
2002
2003 static unsigned
2004 radv_tex_bordercolor(VkBorderColor bcolor)
2005 {
2006 switch (bcolor) {
2007 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2008 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2009 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2010 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2011 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2012 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2013 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2014 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2015 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2016 default:
2017 break;
2018 }
2019 return 0;
2020 }
2021
2022 static unsigned
2023 radv_tex_aniso_filter(unsigned filter)
2024 {
2025 if (filter < 2)
2026 return 0;
2027 if (filter < 4)
2028 return 1;
2029 if (filter < 8)
2030 return 2;
2031 if (filter < 16)
2032 return 3;
2033 return 4;
2034 }
2035
2036 static void
2037 radv_init_sampler(struct radv_device *device,
2038 struct radv_sampler *sampler,
2039 const VkSamplerCreateInfo *pCreateInfo)
2040 {
2041 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2042 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2043 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2044 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2045
2046 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2047 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2048 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2049 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2050 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2051 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2052 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2053 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2054 S_008F30_DISABLE_CUBE_WRAP(0) |
2055 S_008F30_COMPAT_MODE(is_vi));
2056 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2057 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2058 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2059 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2060 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2061 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2062 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2063 S_008F38_MIP_POINT_PRECLAMP(1) |
2064 S_008F38_DISABLE_LSB_CEIL(1) |
2065 S_008F38_FILTER_PREC_FIX(1) |
2066 S_008F38_ANISO_OVERRIDE(is_vi));
2067 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2068 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2069 }
2070
2071 VkResult radv_CreateSampler(
2072 VkDevice _device,
2073 const VkSamplerCreateInfo* pCreateInfo,
2074 const VkAllocationCallbacks* pAllocator,
2075 VkSampler* pSampler)
2076 {
2077 RADV_FROM_HANDLE(radv_device, device, _device);
2078 struct radv_sampler *sampler;
2079
2080 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2081
2082 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2083 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2084 if (!sampler)
2085 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2086
2087 radv_init_sampler(device, sampler, pCreateInfo);
2088 *pSampler = radv_sampler_to_handle(sampler);
2089
2090 return VK_SUCCESS;
2091 }
2092
2093 void radv_DestroySampler(
2094 VkDevice _device,
2095 VkSampler _sampler,
2096 const VkAllocationCallbacks* pAllocator)
2097 {
2098 RADV_FROM_HANDLE(radv_device, device, _device);
2099 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2100
2101 if (!sampler)
2102 return;
2103 vk_free2(&device->alloc, pAllocator, sampler);
2104 }
2105
2106
2107 /* vk_icd.h does not declare this function, so we declare it here to
2108 * suppress Wmissing-prototypes.
2109 */
2110 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2111 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2112
2113 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2114 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2115 {
2116 /* For the full details on loader interface versioning, see
2117 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2118 * What follows is a condensed summary, to help you navigate the large and
2119 * confusing official doc.
2120 *
2121 * - Loader interface v0 is incompatible with later versions. We don't
2122 * support it.
2123 *
2124 * - In loader interface v1:
2125 * - The first ICD entrypoint called by the loader is
2126 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2127 * entrypoint.
2128 * - The ICD must statically expose no other Vulkan symbol unless it is
2129 * linked with -Bsymbolic.
2130 * - Each dispatchable Vulkan handle created by the ICD must be
2131 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2132 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2133 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2134 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2135 * such loader-managed surfaces.
2136 *
2137 * - Loader interface v2 differs from v1 in:
2138 * - The first ICD entrypoint called by the loader is
2139 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2140 * statically expose this entrypoint.
2141 *
2142 * - Loader interface v3 differs from v2 in:
2143 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2144 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2145 * because the loader no longer does so.
2146 */
2147 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2148 return VK_SUCCESS;
2149 }