2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/xmlpool.h"
69 static struct radv_timeline_point
*
70 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
71 struct radv_timeline
*timeline
,
74 static struct radv_timeline_point
*
75 radv_timeline_add_point_locked(struct radv_device
*device
,
76 struct radv_timeline
*timeline
,
80 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
81 struct list_head
*processing_list
);
84 void radv_destroy_semaphore_part(struct radv_device
*device
,
85 struct radv_semaphore_part
*part
);
88 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
91 unsigned char sha1
[20];
92 unsigned ptr_size
= sizeof(void*);
94 memset(uuid
, 0, VK_UUID_SIZE
);
95 _mesa_sha1_init(&ctx
);
97 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
98 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
101 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
102 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
103 _mesa_sha1_final(&ctx
, sha1
);
105 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
110 radv_get_driver_uuid(void *uuid
)
112 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
116 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
118 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
122 radv_get_visible_vram_size(struct radv_physical_device
*device
)
124 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
128 radv_get_vram_size(struct radv_physical_device
*device
)
130 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
134 radv_is_mem_type_vram(enum radv_mem_type type
)
136 return type
== RADV_MEM_TYPE_VRAM
||
137 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
141 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
143 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
144 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
147 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
149 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
150 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
154 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
156 return type
== RADV_MEM_TYPE_GTT_CACHED
||
157 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
161 radv_is_mem_type_uncached(enum radv_mem_type type
)
163 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
164 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
166 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
170 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
172 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
173 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
174 uint64_t vram_size
= radv_get_vram_size(device
);
175 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
176 device
->memory_properties
.memoryHeapCount
= 0;
178 vram_index
= device
->memory_properties
.memoryHeapCount
++;
179 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
181 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
184 if (visible_vram_size
) {
185 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
186 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
187 .size
= visible_vram_size
,
188 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
191 if (device
->rad_info
.gart_size
> 0) {
192 gart_index
= device
->memory_properties
.memoryHeapCount
++;
193 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
194 .size
= device
->rad_info
.gart_size
,
195 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
199 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
200 unsigned type_count
= 0;
201 if (vram_index
>= 0) {
202 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
203 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
204 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
205 .heapIndex
= vram_index
,
208 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
209 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
210 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
211 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
212 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
213 .heapIndex
= gart_index
,
216 if (visible_vram_index
>= 0) {
217 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
218 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
219 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
220 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
221 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
222 .heapIndex
= visible_vram_index
,
225 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
226 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
227 * as they have identical property flags, and according to the
228 * spec, for types with identical flags, the one with greater
229 * performance must be given a lower index. */
230 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
231 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
232 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
233 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
234 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
235 .heapIndex
= gart_index
,
238 if (gart_index
>= 0) {
239 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
240 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
241 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
242 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
243 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
244 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
245 .heapIndex
= gart_index
,
248 device
->memory_properties
.memoryTypeCount
= type_count
;
250 if (device
->rad_info
.has_l2_uncached
) {
251 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
252 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
254 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
255 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
256 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
257 enum radv_mem_type mem_type_id
;
259 switch (device
->mem_type_indices
[i
]) {
260 case RADV_MEM_TYPE_VRAM
:
261 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
263 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
264 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
266 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
267 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
269 case RADV_MEM_TYPE_GTT_CACHED
:
270 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
273 unreachable("invalid memory type");
276 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
277 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
278 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
280 device
->mem_type_indices
[type_count
] = mem_type_id
;
281 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
282 .propertyFlags
= property_flags
,
283 .heapIndex
= mem_type
.heapIndex
,
287 device
->memory_properties
.memoryTypeCount
= type_count
;
292 radv_physical_device_init(struct radv_physical_device
*device
,
293 struct radv_instance
*instance
,
294 drmDevicePtr drm_device
)
301 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
302 drmVersionPtr version
;
304 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
306 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
307 radv_logi("Could not open device '%s'", path
);
309 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
312 version
= drmGetVersion(fd
);
316 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
317 radv_logi("Could not get the kernel driver version for device '%s'", path
);
319 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
320 "failed to get version %s: %m", path
);
323 if (strcmp(version
->name
, "amdgpu")) {
324 drmFreeVersion(version
);
327 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
328 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
330 return VK_ERROR_INCOMPATIBLE_DRIVER
;
332 drmFreeVersion(version
);
334 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
335 radv_logi("Found compatible device '%s'.", path
);
338 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
339 device
->instance
= instance
;
342 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
343 instance
->perftest_flags
);
345 device
->ws
= radv_null_winsys_create();
349 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
353 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
354 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
355 if (master_fd
>= 0) {
356 uint32_t accel_working
= 0;
357 struct drm_amdgpu_info request
= {
358 .return_pointer
= (uintptr_t)&accel_working
,
359 .return_size
= sizeof(accel_working
),
360 .query
= AMDGPU_INFO_ACCEL_WORKING
363 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
370 device
->master_fd
= master_fd
;
371 device
->local_fd
= fd
;
372 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
374 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
376 snprintf(device
->name
, sizeof(device
->name
),
377 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
378 device
->rad_info
.name
);
380 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
381 device
->ws
->destroy(device
->ws
);
382 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
383 "cannot generate UUID");
387 /* These flags affect shader compilation. */
388 uint64_t shader_env_flags
= (device
->use_aco
? 0x2 : 0);
390 /* The gpu id is already embedded in the uuid so we just pass "radv"
391 * when creating the cache.
393 char buf
[VK_UUID_SIZE
* 2 + 1];
394 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
395 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
397 if (device
->rad_info
.chip_class
< GFX8
)
398 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
400 radv_get_driver_uuid(&device
->driver_uuid
);
401 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
403 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
404 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
406 device
->dcc_msaa_allowed
=
407 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
409 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
410 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
412 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
413 device
->rad_info
.family
!= CHIP_NAVI14
&&
414 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
415 if (device
->use_aco
&& device
->use_ngg
) {
416 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
417 device
->use_ngg
= false;
420 device
->use_ngg_streamout
= false;
422 /* Determine the number of threads per wave for all stages. */
423 device
->cs_wave_size
= 64;
424 device
->ps_wave_size
= 64;
425 device
->ge_wave_size
= 64;
427 if (device
->rad_info
.chip_class
>= GFX10
) {
428 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
429 device
->cs_wave_size
= 32;
431 /* For pixel shaders, wave64 is recommanded. */
432 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
433 device
->ps_wave_size
= 32;
435 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
436 device
->ge_wave_size
= 32;
439 radv_physical_device_init_mem_types(device
);
440 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
443 device
->bus_info
= *drm_device
->businfo
.pci
;
445 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
446 ac_print_gpu_info(&device
->rad_info
);
448 /* The WSI is structured as a layer on top of the driver, so this has
449 * to be the last part of initialization (at least until we get other
452 result
= radv_init_wsi(device
);
453 if (result
!= VK_SUCCESS
) {
454 device
->ws
->destroy(device
->ws
);
455 vk_error(instance
, result
);
469 radv_physical_device_finish(struct radv_physical_device
*device
)
471 radv_finish_wsi(device
);
472 device
->ws
->destroy(device
->ws
);
473 disk_cache_destroy(device
->disk_cache
);
474 close(device
->local_fd
);
475 if (device
->master_fd
!= -1)
476 close(device
->master_fd
);
480 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
481 VkSystemAllocationScope allocationScope
)
487 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
488 size_t align
, VkSystemAllocationScope allocationScope
)
490 return realloc(pOriginal
, size
);
494 default_free_func(void *pUserData
, void *pMemory
)
499 static const VkAllocationCallbacks default_alloc
= {
501 .pfnAllocation
= default_alloc_func
,
502 .pfnReallocation
= default_realloc_func
,
503 .pfnFree
= default_free_func
,
506 static const struct debug_control radv_debug_options
[] = {
507 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
508 {"nodcc", RADV_DEBUG_NO_DCC
},
509 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
510 {"nocache", RADV_DEBUG_NO_CACHE
},
511 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
512 {"nohiz", RADV_DEBUG_NO_HIZ
},
513 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
514 {"allbos", RADV_DEBUG_ALL_BOS
},
515 {"noibs", RADV_DEBUG_NO_IBS
},
516 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
517 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
518 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
519 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
520 {"preoptir", RADV_DEBUG_PREOPTIR
},
521 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
522 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
523 {"info", RADV_DEBUG_INFO
},
524 {"errors", RADV_DEBUG_ERRORS
},
525 {"startup", RADV_DEBUG_STARTUP
},
526 {"checkir", RADV_DEBUG_CHECKIR
},
527 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
528 {"nobinning", RADV_DEBUG_NOBINNING
},
529 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
530 {"nongg", RADV_DEBUG_NO_NGG
},
531 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
532 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
533 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
534 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
539 radv_get_debug_option_name(int id
)
541 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
542 return radv_debug_options
[id
].string
;
545 static const struct debug_control radv_perftest_options
[] = {
546 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
547 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
548 {"bolist", RADV_PERFTEST_BO_LIST
},
549 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
550 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
551 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
552 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
553 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
554 {"dfsm", RADV_PERFTEST_DFSM
},
555 {"aco", RADV_PERFTEST_ACO
},
560 radv_get_perftest_option_name(int id
)
562 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
563 return radv_perftest_options
[id
].string
;
567 radv_handle_per_app_options(struct radv_instance
*instance
,
568 const VkApplicationInfo
*info
)
570 const char *name
= info
? info
->pApplicationName
: NULL
;
575 if (!strcmp(name
, "DOOM_VFR")) {
576 /* Work around a Doom VFR game bug */
577 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
578 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
579 /* Workaround for a WaW hazard when LLVM moves/merges
580 * load/store memory operations.
581 * See https://reviews.llvm.org/D61313
583 if (LLVM_VERSION_MAJOR
< 9)
584 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
585 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
586 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
587 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
588 /* Force enable VK_AMD_shader_ballot because it looks
589 * safe and it gives a nice boost (+20% on Vega 56 at
590 * this time). It also prevents corruption on LLVM.
592 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
594 } else if (!strcmp(name
, "Fledge")) {
596 * Zero VRAM for "The Surge 2"
598 * This avoid a hang when when rendering any level. Likely
599 * uninitialized data in an indirect draw.
601 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
605 static int radv_get_instance_extension_index(const char *name
)
607 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
608 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
614 static const char radv_dri_options_xml
[] =
616 DRI_CONF_SECTION_PERFORMANCE
617 DRI_CONF_ADAPTIVE_SYNC("true")
618 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
619 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
622 DRI_CONF_SECTION_DEBUG
623 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
627 static void radv_init_dri_options(struct radv_instance
*instance
)
629 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
630 driParseConfigFiles(&instance
->dri_options
,
631 &instance
->available_dri_options
,
633 instance
->engineName
,
634 instance
->engineVersion
);
637 VkResult
radv_CreateInstance(
638 const VkInstanceCreateInfo
* pCreateInfo
,
639 const VkAllocationCallbacks
* pAllocator
,
640 VkInstance
* pInstance
)
642 struct radv_instance
*instance
;
645 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
647 uint32_t client_version
;
648 if (pCreateInfo
->pApplicationInfo
&&
649 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
650 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
652 client_version
= VK_API_VERSION_1_0
;
655 const char *engine_name
= NULL
;
656 uint32_t engine_version
= 0;
657 if (pCreateInfo
->pApplicationInfo
) {
658 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
659 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
662 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
665 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
667 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
670 instance
->alloc
= *pAllocator
;
672 instance
->alloc
= default_alloc
;
674 instance
->apiVersion
= client_version
;
675 instance
->physicalDeviceCount
= -1;
677 /* Get secure compile thread count. NOTE: We cap this at 32 */
678 #define MAX_SC_PROCS 32
679 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
681 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
683 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
686 /* Disable memory cache when secure compile is set */
687 if (radv_device_use_secure_compile(instance
))
688 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
690 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
691 radv_perftest_options
);
693 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
694 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
696 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
697 radv_logi("Created an instance");
699 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
700 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
701 int index
= radv_get_instance_extension_index(ext_name
);
703 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
704 vk_free2(&default_alloc
, pAllocator
, instance
);
705 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
708 instance
->enabled_extensions
.extensions
[index
] = true;
711 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
713 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
714 /* Vulkan requires that entrypoints for extensions which have
715 * not been enabled must not be advertised.
718 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
719 &instance
->enabled_extensions
)) {
720 instance
->dispatch
.entrypoints
[i
] = NULL
;
722 instance
->dispatch
.entrypoints
[i
] =
723 radv_instance_dispatch_table
.entrypoints
[i
];
727 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
728 /* Vulkan requires that entrypoints for extensions which have
729 * not been enabled must not be advertised.
732 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
733 &instance
->enabled_extensions
)) {
734 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
736 instance
->physical_device_dispatch
.entrypoints
[i
] =
737 radv_physical_device_dispatch_table
.entrypoints
[i
];
741 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
742 /* Vulkan requires that entrypoints for extensions which have
743 * not been enabled must not be advertised.
746 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
747 &instance
->enabled_extensions
, NULL
)) {
748 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
750 instance
->device_dispatch
.entrypoints
[i
] =
751 radv_device_dispatch_table
.entrypoints
[i
];
755 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
756 if (result
!= VK_SUCCESS
) {
757 vk_free2(&default_alloc
, pAllocator
, instance
);
758 return vk_error(instance
, result
);
761 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
762 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
763 instance
->engineVersion
= engine_version
;
765 glsl_type_singleton_init_or_ref();
767 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
769 radv_init_dri_options(instance
);
770 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
772 *pInstance
= radv_instance_to_handle(instance
);
777 void radv_DestroyInstance(
778 VkInstance _instance
,
779 const VkAllocationCallbacks
* pAllocator
)
781 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
786 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
787 radv_physical_device_finish(instance
->physicalDevices
+ i
);
790 vk_free(&instance
->alloc
, instance
->engineName
);
792 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
794 glsl_type_singleton_decref();
796 driDestroyOptionCache(&instance
->dri_options
);
797 driDestroyOptionInfo(&instance
->available_dri_options
);
799 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
801 vk_free(&instance
->alloc
, instance
);
805 radv_enumerate_devices(struct radv_instance
*instance
)
807 /* TODO: Check for more devices ? */
808 drmDevicePtr devices
[8];
809 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
812 instance
->physicalDeviceCount
= 0;
814 if (getenv("RADV_FORCE_FAMILY")) {
815 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
816 * device that allows to test the compiler without having an
819 result
= radv_physical_device_init(instance
->physicalDevices
+
820 instance
->physicalDeviceCount
,
823 ++instance
->physicalDeviceCount
;
827 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
829 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
830 radv_logi("Found %d drm nodes", max_devices
);
833 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
835 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
836 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
837 devices
[i
]->bustype
== DRM_BUS_PCI
&&
838 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
840 result
= radv_physical_device_init(instance
->physicalDevices
+
841 instance
->physicalDeviceCount
,
844 if (result
== VK_SUCCESS
)
845 ++instance
->physicalDeviceCount
;
846 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
850 drmFreeDevices(devices
, max_devices
);
855 VkResult
radv_EnumeratePhysicalDevices(
856 VkInstance _instance
,
857 uint32_t* pPhysicalDeviceCount
,
858 VkPhysicalDevice
* pPhysicalDevices
)
860 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
863 if (instance
->physicalDeviceCount
< 0) {
864 result
= radv_enumerate_devices(instance
);
865 if (result
!= VK_SUCCESS
&&
866 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
870 if (!pPhysicalDevices
) {
871 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
873 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
874 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
875 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
878 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
882 VkResult
radv_EnumeratePhysicalDeviceGroups(
883 VkInstance _instance
,
884 uint32_t* pPhysicalDeviceGroupCount
,
885 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
887 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
890 if (instance
->physicalDeviceCount
< 0) {
891 result
= radv_enumerate_devices(instance
);
892 if (result
!= VK_SUCCESS
&&
893 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
897 if (!pPhysicalDeviceGroupProperties
) {
898 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
900 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
901 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
902 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
903 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
904 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
907 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
911 void radv_GetPhysicalDeviceFeatures(
912 VkPhysicalDevice physicalDevice
,
913 VkPhysicalDeviceFeatures
* pFeatures
)
915 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
916 memset(pFeatures
, 0, sizeof(*pFeatures
));
918 *pFeatures
= (VkPhysicalDeviceFeatures
) {
919 .robustBufferAccess
= true,
920 .fullDrawIndexUint32
= true,
921 .imageCubeArray
= true,
922 .independentBlend
= true,
923 .geometryShader
= true,
924 .tessellationShader
= true,
925 .sampleRateShading
= true,
926 .dualSrcBlend
= true,
928 .multiDrawIndirect
= true,
929 .drawIndirectFirstInstance
= true,
931 .depthBiasClamp
= true,
932 .fillModeNonSolid
= true,
937 .multiViewport
= true,
938 .samplerAnisotropy
= true,
939 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
940 .textureCompressionASTC_LDR
= false,
941 .textureCompressionBC
= true,
942 .occlusionQueryPrecise
= true,
943 .pipelineStatisticsQuery
= true,
944 .vertexPipelineStoresAndAtomics
= true,
945 .fragmentStoresAndAtomics
= true,
946 .shaderTessellationAndGeometryPointSize
= true,
947 .shaderImageGatherExtended
= true,
948 .shaderStorageImageExtendedFormats
= true,
949 .shaderStorageImageMultisample
= true,
950 .shaderUniformBufferArrayDynamicIndexing
= true,
951 .shaderSampledImageArrayDynamicIndexing
= true,
952 .shaderStorageBufferArrayDynamicIndexing
= true,
953 .shaderStorageImageArrayDynamicIndexing
= true,
954 .shaderStorageImageReadWithoutFormat
= true,
955 .shaderStorageImageWriteWithoutFormat
= true,
956 .shaderClipDistance
= true,
957 .shaderCullDistance
= true,
958 .shaderFloat64
= true,
960 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
961 .sparseBinding
= true,
962 .variableMultisampleRate
= true,
963 .inheritedQueries
= true,
967 void radv_GetPhysicalDeviceFeatures2(
968 VkPhysicalDevice physicalDevice
,
969 VkPhysicalDeviceFeatures2
*pFeatures
)
971 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
972 vk_foreach_struct(ext
, pFeatures
->pNext
) {
973 switch (ext
->sType
) {
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
975 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
976 features
->variablePointersStorageBuffer
= true;
977 features
->variablePointers
= true;
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
981 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
982 features
->multiview
= true;
983 features
->multiviewGeometryShader
= true;
984 features
->multiviewTessellationShader
= true;
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
988 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
989 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
990 features
->shaderDrawParameters
= true;
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
994 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
995 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
996 features
->protectedMemory
= false;
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
1000 VkPhysicalDevice16BitStorageFeatures
*features
=
1001 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1002 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1003 features
->storageBuffer16BitAccess
= enabled
;
1004 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
1005 features
->storagePushConstant16
= enabled
;
1006 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
1009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1010 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1011 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1012 features
->samplerYcbcrConversion
= true;
1015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1016 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1017 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1018 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1019 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1020 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1021 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1022 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1023 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1024 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1025 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1026 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1027 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1028 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1029 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1030 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1031 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1032 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1033 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1034 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1035 features
->descriptorBindingPartiallyBound
= true;
1036 features
->descriptorBindingVariableDescriptorCount
= true;
1037 features
->runtimeDescriptorArray
= true;
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1041 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1042 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1043 features
->conditionalRendering
= true;
1044 features
->inheritedConditionalRendering
= false;
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1048 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1049 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1050 features
->vertexAttributeInstanceRateDivisor
= true;
1051 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1055 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1056 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1057 features
->transformFeedback
= true;
1058 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1062 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1063 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1064 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1068 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1069 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1070 features
->memoryPriority
= true;
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1074 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1075 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1076 features
->bufferDeviceAddress
= true;
1077 features
->bufferDeviceAddressCaptureReplay
= false;
1078 features
->bufferDeviceAddressMultiDevice
= false;
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1082 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1083 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1084 features
->bufferDeviceAddress
= true;
1085 features
->bufferDeviceAddressCaptureReplay
= false;
1086 features
->bufferDeviceAddressMultiDevice
= false;
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1090 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1091 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1092 features
->depthClipEnable
= true;
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1096 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1097 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1098 features
->hostQueryReset
= true;
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1102 VkPhysicalDevice8BitStorageFeatures
*features
=
1103 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1104 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1105 features
->storageBuffer8BitAccess
= enabled
;
1106 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1107 features
->storagePushConstant8
= enabled
;
1110 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1111 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1112 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1113 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1114 features
->shaderInt8
= !pdevice
->use_aco
;
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1118 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1119 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1120 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1121 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1125 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1126 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1127 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1130 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1131 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1132 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1134 features
->inlineUniformBlock
= true;
1135 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1139 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1140 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1141 features
->computeDerivativeGroupQuads
= false;
1142 features
->computeDerivativeGroupLinear
= true;
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1146 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1147 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1148 features
->ycbcrImageArrays
= true;
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1152 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1153 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1154 features
->uniformBufferStandardLayout
= true;
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1158 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1159 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1160 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1164 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1165 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1166 features
->imagelessFramebuffer
= true;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1170 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1171 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1172 features
->pipelineExecutableInfo
= true;
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1176 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1177 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1178 features
->shaderSubgroupClock
= true;
1179 features
->shaderDeviceClock
= false;
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1183 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1184 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1185 features
->texelBufferAlignment
= true;
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1189 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1190 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1191 features
->timelineSemaphore
= true;
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1195 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1196 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1197 features
->subgroupSizeControl
= true;
1198 features
->computeFullSubgroups
= true;
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1202 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1203 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1204 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1208 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1209 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1210 features
->shaderSubgroupExtendedTypes
= true;
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1214 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1215 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1216 features
->separateDepthStencilLayouts
= true;
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1220 VkPhysicalDeviceVulkan11Features
*features
=
1221 (VkPhysicalDeviceVulkan11Features
*)ext
;
1222 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1223 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1224 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1225 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1226 features
->multiview
= true;
1227 features
->multiviewGeometryShader
= true;
1228 features
->multiviewTessellationShader
= true;
1229 features
->variablePointersStorageBuffer
= true;
1230 features
->variablePointers
= true;
1231 features
->protectedMemory
= false;
1232 features
->samplerYcbcrConversion
= true;
1233 features
->shaderDrawParameters
= true;
1236 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1237 VkPhysicalDeviceVulkan12Features
*features
=
1238 (VkPhysicalDeviceVulkan12Features
*)ext
;
1239 features
->samplerMirrorClampToEdge
= true;
1240 features
->drawIndirectCount
= true;
1241 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1242 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1243 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1244 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1245 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1246 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1247 features
->shaderInt8
= !pdevice
->use_aco
;
1248 features
->descriptorIndexing
= true;
1249 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1250 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1251 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1252 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1253 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1254 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1255 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1256 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1257 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1258 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1259 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1260 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1261 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1262 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1263 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1264 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1265 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1266 features
->descriptorBindingPartiallyBound
= true;
1267 features
->descriptorBindingVariableDescriptorCount
= true;
1268 features
->runtimeDescriptorArray
= true;
1269 features
->samplerFilterMinmax
= true;
1270 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1271 features
->imagelessFramebuffer
= true;
1272 features
->uniformBufferStandardLayout
= true;
1273 features
->shaderSubgroupExtendedTypes
= true;
1274 features
->separateDepthStencilLayouts
= true;
1275 features
->hostQueryReset
= true;
1276 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1277 features
->bufferDeviceAddress
= true;
1278 features
->bufferDeviceAddressCaptureReplay
= false;
1279 features
->bufferDeviceAddressMultiDevice
= false;
1280 features
->vulkanMemoryModel
= false;
1281 features
->vulkanMemoryModelDeviceScope
= false;
1282 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1283 features
->shaderOutputViewportIndex
= true;
1284 features
->shaderOutputLayer
= true;
1285 features
->subgroupBroadcastDynamicId
= true;
1288 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1289 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1290 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1291 features
->rectangularLines
= false;
1292 features
->bresenhamLines
= true;
1293 features
->smoothLines
= false;
1294 features
->stippledRectangularLines
= false;
1295 features
->stippledBresenhamLines
= true;
1296 features
->stippledSmoothLines
= false;
1303 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1307 radv_max_descriptor_set_size()
1309 /* make sure that the entire descriptor set is addressable with a signed
1310 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1311 * be at most 2 GiB. the combined image & samples object count as one of
1312 * both. This limit is for the pipeline layout, not for the set layout, but
1313 * there is no set limit, so we just set a pipeline limit. I don't think
1314 * any app is going to hit this soon. */
1315 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1316 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1317 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1318 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1319 32 /* sampler, largest when combined with image */ +
1320 64 /* sampled image */ +
1321 64 /* storage image */);
1324 void radv_GetPhysicalDeviceProperties(
1325 VkPhysicalDevice physicalDevice
,
1326 VkPhysicalDeviceProperties
* pProperties
)
1328 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1329 VkSampleCountFlags sample_counts
= 0xf;
1331 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1333 VkPhysicalDeviceLimits limits
= {
1334 .maxImageDimension1D
= (1 << 14),
1335 .maxImageDimension2D
= (1 << 14),
1336 .maxImageDimension3D
= (1 << 11),
1337 .maxImageDimensionCube
= (1 << 14),
1338 .maxImageArrayLayers
= (1 << 11),
1339 .maxTexelBufferElements
= 128 * 1024 * 1024,
1340 .maxUniformBufferRange
= UINT32_MAX
,
1341 .maxStorageBufferRange
= UINT32_MAX
,
1342 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1343 .maxMemoryAllocationCount
= UINT32_MAX
,
1344 .maxSamplerAllocationCount
= 64 * 1024,
1345 .bufferImageGranularity
= 64, /* A cache line */
1346 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1347 .maxBoundDescriptorSets
= MAX_SETS
,
1348 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1349 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1350 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1351 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1352 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1353 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1354 .maxPerStageResources
= max_descriptor_set_size
,
1355 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1356 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1357 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1358 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1359 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1360 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1361 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1362 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1363 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1364 .maxVertexInputBindings
= MAX_VBS
,
1365 .maxVertexInputAttributeOffset
= 2047,
1366 .maxVertexInputBindingStride
= 2048,
1367 .maxVertexOutputComponents
= 128,
1368 .maxTessellationGenerationLevel
= 64,
1369 .maxTessellationPatchSize
= 32,
1370 .maxTessellationControlPerVertexInputComponents
= 128,
1371 .maxTessellationControlPerVertexOutputComponents
= 128,
1372 .maxTessellationControlPerPatchOutputComponents
= 120,
1373 .maxTessellationControlTotalOutputComponents
= 4096,
1374 .maxTessellationEvaluationInputComponents
= 128,
1375 .maxTessellationEvaluationOutputComponents
= 128,
1376 .maxGeometryShaderInvocations
= 127,
1377 .maxGeometryInputComponents
= 64,
1378 .maxGeometryOutputComponents
= 128,
1379 .maxGeometryOutputVertices
= 256,
1380 .maxGeometryTotalOutputComponents
= 1024,
1381 .maxFragmentInputComponents
= 128,
1382 .maxFragmentOutputAttachments
= 8,
1383 .maxFragmentDualSrcAttachments
= 1,
1384 .maxFragmentCombinedOutputResources
= 8,
1385 .maxComputeSharedMemorySize
= 32768,
1386 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1387 .maxComputeWorkGroupInvocations
= 1024,
1388 .maxComputeWorkGroupSize
= {
1393 .subPixelPrecisionBits
= 8,
1394 .subTexelPrecisionBits
= 8,
1395 .mipmapPrecisionBits
= 8,
1396 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1397 .maxDrawIndirectCount
= UINT32_MAX
,
1398 .maxSamplerLodBias
= 16,
1399 .maxSamplerAnisotropy
= 16,
1400 .maxViewports
= MAX_VIEWPORTS
,
1401 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1402 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1403 .viewportSubPixelBits
= 8,
1404 .minMemoryMapAlignment
= 4096, /* A page */
1405 .minTexelBufferOffsetAlignment
= 4,
1406 .minUniformBufferOffsetAlignment
= 4,
1407 .minStorageBufferOffsetAlignment
= 4,
1408 .minTexelOffset
= -32,
1409 .maxTexelOffset
= 31,
1410 .minTexelGatherOffset
= -32,
1411 .maxTexelGatherOffset
= 31,
1412 .minInterpolationOffset
= -2,
1413 .maxInterpolationOffset
= 2,
1414 .subPixelInterpolationOffsetBits
= 8,
1415 .maxFramebufferWidth
= (1 << 14),
1416 .maxFramebufferHeight
= (1 << 14),
1417 .maxFramebufferLayers
= (1 << 10),
1418 .framebufferColorSampleCounts
= sample_counts
,
1419 .framebufferDepthSampleCounts
= sample_counts
,
1420 .framebufferStencilSampleCounts
= sample_counts
,
1421 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1422 .maxColorAttachments
= MAX_RTS
,
1423 .sampledImageColorSampleCounts
= sample_counts
,
1424 .sampledImageIntegerSampleCounts
= sample_counts
,
1425 .sampledImageDepthSampleCounts
= sample_counts
,
1426 .sampledImageStencilSampleCounts
= sample_counts
,
1427 .storageImageSampleCounts
= sample_counts
,
1428 .maxSampleMaskWords
= 1,
1429 .timestampComputeAndGraphics
= true,
1430 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1431 .maxClipDistances
= 8,
1432 .maxCullDistances
= 8,
1433 .maxCombinedClipAndCullDistances
= 8,
1434 .discreteQueuePriorities
= 2,
1435 .pointSizeRange
= { 0.0, 8192.0 },
1436 .lineWidthRange
= { 0.0, 8192.0 },
1437 .pointSizeGranularity
= (1.0 / 8.0),
1438 .lineWidthGranularity
= (1.0 / 8.0),
1439 .strictLines
= false, /* FINISHME */
1440 .standardSampleLocations
= true,
1441 .optimalBufferCopyOffsetAlignment
= 128,
1442 .optimalBufferCopyRowPitchAlignment
= 128,
1443 .nonCoherentAtomSize
= 64,
1446 *pProperties
= (VkPhysicalDeviceProperties
) {
1447 .apiVersion
= radv_physical_device_api_version(pdevice
),
1448 .driverVersion
= vk_get_driver_version(),
1449 .vendorID
= ATI_VENDOR_ID
,
1450 .deviceID
= pdevice
->rad_info
.pci_id
,
1451 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1453 .sparseProperties
= {0},
1456 strcpy(pProperties
->deviceName
, pdevice
->name
);
1457 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1461 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1462 VkPhysicalDeviceVulkan11Properties
*p
)
1464 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1466 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1467 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1468 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1469 /* The LUID is for Windows. */
1470 p
->deviceLUIDValid
= false;
1471 p
->deviceNodeMask
= 0;
1473 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1474 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1475 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1476 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1477 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1478 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1479 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1480 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1482 if (pdevice
->rad_info
.chip_class
== GFX8
||
1483 pdevice
->rad_info
.chip_class
== GFX9
) {
1484 p
->subgroupSupportedOperations
|= VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1485 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1487 p
->subgroupQuadOperationsInAllStages
= true;
1489 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1490 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1491 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1492 p
->protectedNoFault
= false;
1493 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1494 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1498 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1499 VkPhysicalDeviceVulkan12Properties
*p
)
1501 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1503 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1504 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1505 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1506 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1507 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1508 p
->conformanceVersion
= (VkConformanceVersion
) {
1515 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1516 * controlled by the same config register.
1518 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1519 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1521 /* Do not allow both preserving and flushing denorms because different
1522 * shaders in the same pipeline can have different settings and this
1523 * won't work for merged shaders. To make it work, this requires LLVM
1524 * support for changing the register. The same logic applies for the
1525 * rounding modes because they are configured with the same config
1526 * register. TODO: we can enable a lot of these for ACO when it
1527 * supports all stages.
1529 p
->shaderDenormFlushToZeroFloat32
= true;
1530 p
->shaderDenormPreserveFloat32
= false;
1531 p
->shaderRoundingModeRTEFloat32
= true;
1532 p
->shaderRoundingModeRTZFloat32
= false;
1533 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1535 p
->shaderDenormFlushToZeroFloat16
= false;
1536 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1537 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1538 p
->shaderRoundingModeRTZFloat16
= false;
1539 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1541 p
->shaderDenormFlushToZeroFloat64
= false;
1542 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1543 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1544 p
->shaderRoundingModeRTZFloat64
= false;
1545 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1547 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1548 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1549 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1550 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1551 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1552 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1553 p
->robustBufferAccessUpdateAfterBind
= false;
1554 p
->quadDivergentImplicitLod
= false;
1556 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1557 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1558 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1559 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1560 32 /* sampler, largest when combined with image */ +
1561 64 /* sampled image */ +
1562 64 /* storage image */);
1563 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1564 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1565 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1566 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1567 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1568 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1569 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1570 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1571 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1572 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1573 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1574 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1575 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1576 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1577 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1579 /* We support all of the depth resolve modes */
1580 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1581 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1582 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1583 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1585 /* Average doesn't make sense for stencil so we don't support that */
1586 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1587 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1588 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1590 p
->independentResolveNone
= true;
1591 p
->independentResolve
= true;
1593 /* GFX6-8 only support single channel min/max filter. */
1594 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1595 p
->filterMinmaxSingleComponentFormats
= true;
1597 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1599 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1602 void radv_GetPhysicalDeviceProperties2(
1603 VkPhysicalDevice physicalDevice
,
1604 VkPhysicalDeviceProperties2
*pProperties
)
1606 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1607 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1609 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1610 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1612 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1614 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1615 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1617 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1619 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1620 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1621 sizeof(core_##major##_##minor.core_property))
1623 #define CORE_PROPERTY(major, minor, property) \
1624 CORE_RENAMED_PROPERTY(major, minor, property, property)
1626 vk_foreach_struct(ext
, pProperties
->pNext
) {
1627 switch (ext
->sType
) {
1628 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1629 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1630 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1631 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1634 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1635 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1636 CORE_PROPERTY(1, 1, deviceUUID
);
1637 CORE_PROPERTY(1, 1, driverUUID
);
1638 CORE_PROPERTY(1, 1, deviceLUID
);
1639 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1642 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1643 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1644 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1645 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1648 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1649 VkPhysicalDevicePointClippingProperties
*properties
=
1650 (VkPhysicalDevicePointClippingProperties
*)ext
;
1651 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1654 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1655 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1656 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1657 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1660 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1661 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1662 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1663 properties
->minImportedHostPointerAlignment
= 4096;
1666 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1667 VkPhysicalDeviceSubgroupProperties
*properties
=
1668 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1669 CORE_PROPERTY(1, 1, subgroupSize
);
1670 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1671 subgroupSupportedStages
);
1672 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1673 subgroupSupportedOperations
);
1674 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1675 subgroupQuadOperationsInAllStages
);
1678 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1679 VkPhysicalDeviceMaintenance3Properties
*properties
=
1680 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1681 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1682 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1685 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1686 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1687 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1688 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1689 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1692 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1693 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1694 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1696 /* Shader engines. */
1697 properties
->shaderEngineCount
=
1698 pdevice
->rad_info
.max_se
;
1699 properties
->shaderArraysPerEngineCount
=
1700 pdevice
->rad_info
.max_sh_per_se
;
1701 properties
->computeUnitsPerShaderArray
=
1702 pdevice
->rad_info
.num_good_cu_per_sh
;
1703 properties
->simdPerComputeUnit
=
1704 pdevice
->rad_info
.num_simd_per_compute_unit
;
1705 properties
->wavefrontsPerSimd
=
1706 pdevice
->rad_info
.max_wave64_per_simd
;
1707 properties
->wavefrontSize
= 64;
1710 properties
->sgprsPerSimd
=
1711 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1712 properties
->minSgprAllocation
=
1713 pdevice
->rad_info
.min_sgpr_alloc
;
1714 properties
->maxSgprAllocation
=
1715 pdevice
->rad_info
.max_sgpr_alloc
;
1716 properties
->sgprAllocationGranularity
=
1717 pdevice
->rad_info
.sgpr_alloc_granularity
;
1720 properties
->vgprsPerSimd
=
1721 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1722 properties
->minVgprAllocation
=
1723 pdevice
->rad_info
.min_vgpr_alloc
;
1724 properties
->maxVgprAllocation
=
1725 pdevice
->rad_info
.max_vgpr_alloc
;
1726 properties
->vgprAllocationGranularity
=
1727 pdevice
->rad_info
.vgpr_alloc_granularity
;
1730 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1731 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1732 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1734 properties
->shaderCoreFeatures
= 0;
1735 properties
->activeComputeUnitCount
=
1736 pdevice
->rad_info
.num_good_compute_units
;
1739 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1740 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1741 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1742 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1746 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1747 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1748 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1749 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1750 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1751 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1752 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1753 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1754 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1755 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1756 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1757 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1758 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1759 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1760 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1761 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1762 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1763 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1764 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1765 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1766 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1767 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1768 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1769 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1770 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1774 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1775 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1776 CORE_PROPERTY(1, 1, protectedNoFault
);
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1780 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1781 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1782 properties
->primitiveOverestimationSize
= 0;
1783 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1784 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1785 properties
->primitiveUnderestimation
= false;
1786 properties
->conservativePointAndLineRasterization
= false;
1787 properties
->degenerateTrianglesRasterized
= false;
1788 properties
->degenerateLinesRasterized
= false;
1789 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1790 properties
->conservativeRasterizationPostDepthCoverage
= false;
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1794 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1795 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1796 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1797 properties
->pciBus
= pdevice
->bus_info
.bus
;
1798 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1799 properties
->pciFunction
= pdevice
->bus_info
.func
;
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1803 VkPhysicalDeviceDriverProperties
*properties
=
1804 (VkPhysicalDeviceDriverProperties
*) ext
;
1805 CORE_PROPERTY(1, 2, driverID
);
1806 CORE_PROPERTY(1, 2, driverName
);
1807 CORE_PROPERTY(1, 2, driverInfo
);
1808 CORE_PROPERTY(1, 2, conformanceVersion
);
1811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1812 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1813 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1814 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1815 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1816 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1817 properties
->maxTransformFeedbackStreamDataSize
= 512;
1818 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1819 properties
->maxTransformFeedbackBufferDataStride
= 512;
1820 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1821 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1822 properties
->transformFeedbackRasterizationStreamSelect
= false;
1823 properties
->transformFeedbackDraw
= true;
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1827 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1828 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1830 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1831 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1832 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1833 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1834 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1838 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1839 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1840 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1841 VK_SAMPLE_COUNT_4_BIT
|
1842 VK_SAMPLE_COUNT_8_BIT
;
1843 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1844 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1845 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1846 properties
->sampleLocationSubPixelBits
= 4;
1847 properties
->variableSampleLocations
= false;
1850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1851 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1852 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1853 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1854 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1855 CORE_PROPERTY(1, 2, independentResolveNone
);
1856 CORE_PROPERTY(1, 2, independentResolve
);
1859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1860 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1861 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1862 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1863 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1864 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1865 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1868 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1869 VkPhysicalDeviceFloatControlsProperties
*properties
=
1870 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1871 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1872 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1873 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1874 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1875 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1876 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1877 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1878 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1879 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1880 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1881 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1882 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1883 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1884 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1885 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1886 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1887 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1891 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1892 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1893 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1897 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1898 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1899 props
->minSubgroupSize
= 64;
1900 props
->maxSubgroupSize
= 64;
1901 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1902 props
->requiredSubgroupSizeStages
= 0;
1904 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1905 /* Only GFX10+ supports wave32. */
1906 props
->minSubgroupSize
= 32;
1907 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1912 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1915 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
1917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
1918 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
1919 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
1920 props
->lineSubPixelPrecisionBits
= 4;
1929 static void radv_get_physical_device_queue_family_properties(
1930 struct radv_physical_device
* pdevice
,
1932 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1934 int num_queue_families
= 1;
1936 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1937 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1938 num_queue_families
++;
1940 if (pQueueFamilyProperties
== NULL
) {
1941 *pCount
= num_queue_families
;
1950 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1951 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1952 VK_QUEUE_COMPUTE_BIT
|
1953 VK_QUEUE_TRANSFER_BIT
|
1954 VK_QUEUE_SPARSE_BINDING_BIT
,
1956 .timestampValidBits
= 64,
1957 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1962 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1963 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1964 if (*pCount
> idx
) {
1965 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1966 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1967 VK_QUEUE_TRANSFER_BIT
|
1968 VK_QUEUE_SPARSE_BINDING_BIT
,
1969 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1970 .timestampValidBits
= 64,
1971 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1979 void radv_GetPhysicalDeviceQueueFamilyProperties(
1980 VkPhysicalDevice physicalDevice
,
1982 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1984 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1985 if (!pQueueFamilyProperties
) {
1986 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1989 VkQueueFamilyProperties
*properties
[] = {
1990 pQueueFamilyProperties
+ 0,
1991 pQueueFamilyProperties
+ 1,
1992 pQueueFamilyProperties
+ 2,
1994 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1995 assert(*pCount
<= 3);
1998 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1999 VkPhysicalDevice physicalDevice
,
2001 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2003 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2004 if (!pQueueFamilyProperties
) {
2005 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2008 VkQueueFamilyProperties
*properties
[] = {
2009 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2010 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2011 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2013 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2014 assert(*pCount
<= 3);
2017 void radv_GetPhysicalDeviceMemoryProperties(
2018 VkPhysicalDevice physicalDevice
,
2019 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2021 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2023 *pMemoryProperties
= physical_device
->memory_properties
;
2027 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2028 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2030 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2031 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2032 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2033 uint64_t vram_size
= radv_get_vram_size(device
);
2034 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2035 uint64_t heap_budget
, heap_usage
;
2037 /* For all memory heaps, the computation of budget is as follow:
2038 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2040 * The Vulkan spec 1.1.97 says that the budget should include any
2041 * currently allocated device memory.
2043 * Note that the application heap usages are not really accurate (eg.
2044 * in presence of shared buffers).
2046 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2047 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2049 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2050 heap_usage
= device
->ws
->query_value(device
->ws
,
2051 RADEON_ALLOCATED_VRAM
);
2053 heap_budget
= vram_size
-
2054 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2057 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2058 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2059 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2060 heap_usage
= device
->ws
->query_value(device
->ws
,
2061 RADEON_ALLOCATED_VRAM_VIS
);
2063 heap_budget
= visible_vram_size
-
2064 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2067 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2068 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2069 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2070 heap_usage
= device
->ws
->query_value(device
->ws
,
2071 RADEON_ALLOCATED_GTT
);
2073 heap_budget
= gtt_size
-
2074 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2077 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2078 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2082 /* The heapBudget and heapUsage values must be zero for array elements
2083 * greater than or equal to
2084 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2086 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2087 memoryBudget
->heapBudget
[i
] = 0;
2088 memoryBudget
->heapUsage
[i
] = 0;
2092 void radv_GetPhysicalDeviceMemoryProperties2(
2093 VkPhysicalDevice physicalDevice
,
2094 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2096 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2097 &pMemoryProperties
->memoryProperties
);
2099 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2100 vk_find_struct(pMemoryProperties
->pNext
,
2101 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2103 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2106 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2108 VkExternalMemoryHandleTypeFlagBits handleType
,
2109 const void *pHostPointer
,
2110 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2116 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2117 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2118 uint32_t memoryTypeBits
= 0;
2119 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2120 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2121 memoryTypeBits
= (1 << i
);
2125 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2129 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2133 static enum radeon_ctx_priority
2134 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2136 /* Default to MEDIUM when a specific global priority isn't requested */
2138 return RADEON_CTX_PRIORITY_MEDIUM
;
2140 switch(pObj
->globalPriority
) {
2141 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2142 return RADEON_CTX_PRIORITY_REALTIME
;
2143 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2144 return RADEON_CTX_PRIORITY_HIGH
;
2145 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2146 return RADEON_CTX_PRIORITY_MEDIUM
;
2147 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2148 return RADEON_CTX_PRIORITY_LOW
;
2150 unreachable("Illegal global priority value");
2151 return RADEON_CTX_PRIORITY_INVALID
;
2156 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2157 uint32_t queue_family_index
, int idx
,
2158 VkDeviceQueueCreateFlags flags
,
2159 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2161 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2162 queue
->device
= device
;
2163 queue
->queue_family_index
= queue_family_index
;
2164 queue
->queue_idx
= idx
;
2165 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2166 queue
->flags
= flags
;
2168 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2170 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2172 list_inithead(&queue
->pending_submissions
);
2173 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2179 radv_queue_finish(struct radv_queue
*queue
)
2181 pthread_mutex_destroy(&queue
->pending_mutex
);
2184 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2186 if (queue
->initial_full_flush_preamble_cs
)
2187 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2188 if (queue
->initial_preamble_cs
)
2189 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2190 if (queue
->continue_preamble_cs
)
2191 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2192 if (queue
->descriptor_bo
)
2193 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2194 if (queue
->scratch_bo
)
2195 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2196 if (queue
->esgs_ring_bo
)
2197 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2198 if (queue
->gsvs_ring_bo
)
2199 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2200 if (queue
->tess_rings_bo
)
2201 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2203 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2204 if (queue
->gds_oa_bo
)
2205 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2206 if (queue
->compute_scratch_bo
)
2207 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2211 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2213 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2214 bo_list
->list
.count
= bo_list
->capacity
= 0;
2215 bo_list
->list
.bos
= NULL
;
2219 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2221 free(bo_list
->list
.bos
);
2222 pthread_mutex_destroy(&bo_list
->mutex
);
2225 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2226 struct radeon_winsys_bo
*bo
)
2228 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2233 if (unlikely(!device
->use_global_bo_list
))
2236 pthread_mutex_lock(&bo_list
->mutex
);
2237 if (bo_list
->list
.count
== bo_list
->capacity
) {
2238 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2239 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2242 pthread_mutex_unlock(&bo_list
->mutex
);
2243 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2246 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2247 bo_list
->capacity
= capacity
;
2250 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2251 pthread_mutex_unlock(&bo_list
->mutex
);
2255 static void radv_bo_list_remove(struct radv_device
*device
,
2256 struct radeon_winsys_bo
*bo
)
2258 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2263 if (unlikely(!device
->use_global_bo_list
))
2266 pthread_mutex_lock(&bo_list
->mutex
);
2267 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2268 if (bo_list
->list
.bos
[i
] == bo
) {
2269 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2270 --bo_list
->list
.count
;
2274 pthread_mutex_unlock(&bo_list
->mutex
);
2278 radv_device_init_gs_info(struct radv_device
*device
)
2280 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2281 device
->physical_device
->rad_info
.family
);
2284 static int radv_get_device_extension_index(const char *name
)
2286 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2287 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2294 radv_get_int_debug_option(const char *name
, int default_value
)
2301 result
= default_value
;
2305 result
= strtol(str
, &endptr
, 0);
2306 if (str
== endptr
) {
2307 /* No digits founs. */
2308 result
= default_value
;
2315 static int install_seccomp_filter() {
2317 struct sock_filter filter
[] = {
2318 /* Check arch is 64bit x86 */
2319 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2320 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2322 /* Futex is required for mutex locks */
2323 #if defined __NR__newselect
2324 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2325 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2326 #elif defined __NR_select
2327 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2328 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2330 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2331 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2334 /* Allow system exit calls for the forked process */
2335 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2336 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2338 /* Allow system read calls */
2339 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2340 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2342 /* Allow system write calls */
2343 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2344 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2346 /* Allow system brk calls (we need this for malloc) */
2347 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2348 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2350 /* Futex is required for mutex locks */
2351 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2352 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2354 /* Return error if we hit a system call not on the whitelist */
2355 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2357 /* Allow whitelisted system calls */
2358 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2361 struct sock_fprog prog
= {
2362 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2366 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2369 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2375 /* Helper function with timeout support for reading from the pipe between
2376 * processes used for secure compile.
2378 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2387 /* We can't rely on the value of tv after calling select() so
2388 * we must reset it on each iteration of the loop.
2393 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2399 ssize_t bytes_read
= read(fd
, buf
, size
);
2408 /* select timeout */
2414 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2418 d
= opendir("/proc/self/fd");
2421 int dir_fd
= dirfd(d
);
2423 while ((dir
= readdir(d
)) != NULL
) {
2424 if (dir
->d_name
[0] == '.')
2427 int fd
= atoi(dir
->d_name
);
2432 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2433 if (keep_fds
[i
] == fd
)
2445 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2446 int *fd_server
, int *fd_client
,
2447 unsigned process
, bool make_fifo
)
2449 bool result
= false;
2450 char *fifo_server_path
= NULL
;
2451 char *fifo_client_path
= NULL
;
2453 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2454 goto open_fifo_exit
;
2456 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2457 goto open_fifo_exit
;
2460 int file1
= mkfifo(fifo_server_path
, 0666);
2462 goto open_fifo_exit
;
2464 int file2
= mkfifo(fifo_client_path
, 0666);
2466 goto open_fifo_exit
;
2469 *fd_server
= open(fifo_server_path
, O_RDWR
);
2471 goto open_fifo_exit
;
2473 *fd_client
= open(fifo_client_path
, O_RDWR
);
2474 if(*fd_client
< 1) {
2476 goto open_fifo_exit
;
2482 free(fifo_server_path
);
2483 free(fifo_client_path
);
2488 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2489 int fd_idle_device_output
)
2491 int fd_secure_input
;
2492 int fd_secure_output
;
2493 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2498 enum radv_secure_compile_type sc_type
;
2500 const int needed_fds
[] = {
2503 fd_idle_device_output
,
2506 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2507 install_seccomp_filter() == -1) {
2508 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2510 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2511 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2512 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2515 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2517 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2518 goto secure_compile_exit
;
2521 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2523 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2524 struct radv_pipeline
*pipeline
;
2525 bool sc_read
= true;
2527 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2528 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2530 pipeline
->device
= device
;
2532 /* Read pipeline layout */
2533 struct radv_pipeline_layout layout
;
2534 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2535 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2537 goto secure_compile_exit
;
2539 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2540 uint32_t layout_size
;
2541 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2543 goto secure_compile_exit
;
2545 layout
.set
[set
].layout
= malloc(layout_size
);
2546 layout
.set
[set
].layout
->layout_size
= layout_size
;
2547 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2548 layout
.set
[set
].layout
->layout_size
, true);
2551 pipeline
->layout
= &layout
;
2553 /* Read pipeline key */
2554 struct radv_pipeline_key key
;
2555 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2557 /* Read pipeline create flags */
2558 VkPipelineCreateFlags flags
;
2559 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2561 /* Read stage and shader information */
2562 uint32_t num_stages
;
2563 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2564 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2566 goto secure_compile_exit
;
2568 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2571 gl_shader_stage stage
;
2572 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2574 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2576 /* Read entry point name */
2578 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2580 goto secure_compile_exit
;
2582 char *ep_name
= malloc(name_size
);
2583 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2584 pStage
->pName
= ep_name
;
2586 /* Read shader module */
2588 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2590 goto secure_compile_exit
;
2592 struct radv_shader_module
*module
= malloc(module_size
);
2593 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2594 pStage
->module
= radv_shader_module_to_handle(module
);
2596 /* Read specialization info */
2598 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2600 goto secure_compile_exit
;
2602 if (has_spec_info
) {
2603 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2604 pStage
->pSpecializationInfo
= specInfo
;
2606 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2608 goto secure_compile_exit
;
2610 void *si_data
= malloc(specInfo
->dataSize
);
2611 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2612 specInfo
->pData
= si_data
;
2614 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2616 goto secure_compile_exit
;
2618 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2619 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2620 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2622 goto secure_compile_exit
;
2625 specInfo
->pMapEntries
= mapEntries
;
2628 pStages
[stage
] = pStage
;
2631 /* Compile the shaders */
2632 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2633 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2635 /* free memory allocated above */
2636 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2637 free(layout
.set
[set
].layout
);
2639 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2643 free((void *) pStages
[i
]->pName
);
2644 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2645 if (pStages
[i
]->pSpecializationInfo
) {
2646 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2647 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2648 free((void *) pStages
[i
]->pSpecializationInfo
);
2650 free((void *) pStages
[i
]);
2653 vk_free(&device
->alloc
, pipeline
);
2655 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2656 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2658 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2659 goto secure_compile_exit
;
2663 secure_compile_exit
:
2664 close(fd_secure_input
);
2665 close(fd_secure_output
);
2666 close(fd_idle_device_output
);
2670 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2672 int fd_secure_input
[2];
2673 int fd_secure_output
[2];
2675 /* create pipe descriptors (used to communicate between processes) */
2676 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2677 return RADV_SC_TYPE_INIT_FAILURE
;
2681 if ((sc_pid
= fork()) == 0) {
2682 device
->sc_state
->secure_compile_thread_counter
= process
;
2683 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2686 return RADV_SC_TYPE_INIT_FAILURE
;
2688 /* Read the init result returned from the secure process */
2689 enum radv_secure_compile_type sc_type
;
2690 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2692 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2693 close(fd_secure_input
[0]);
2694 close(fd_secure_input
[1]);
2695 close(fd_secure_output
[1]);
2696 close(fd_secure_output
[0]);
2698 waitpid(sc_pid
, &status
, 0);
2700 return RADV_SC_TYPE_INIT_FAILURE
;
2702 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2703 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2705 close(fd_secure_input
[0]);
2706 close(fd_secure_input
[1]);
2707 close(fd_secure_output
[1]);
2708 close(fd_secure_output
[0]);
2711 waitpid(sc_pid
, &status
, 0);
2715 return RADV_SC_TYPE_INIT_SUCCESS
;
2718 /* Run a bare bones fork of a device that was forked right after its creation.
2719 * This device will have low overhead when it is forked again before each
2720 * pipeline compilation. This device sits idle and its only job is to fork
2723 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2724 int fd_secure_input
, int fd_secure_output
)
2726 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2727 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2728 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2730 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2733 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2735 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2736 sc_type
= fork_secure_compile_device(device
, process
);
2738 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2739 goto secure_compile_exit
;
2741 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2742 goto secure_compile_exit
;
2746 secure_compile_exit
:
2747 close(fd_secure_input
);
2748 close(fd_secure_output
);
2752 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2754 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2756 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2757 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2759 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2760 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2763 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2766 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2768 device
->sc_state
= vk_zalloc(&device
->alloc
,
2769 sizeof(struct radv_secure_compile_state
),
2770 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2772 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2774 pid_t upid
= getpid();
2775 time_t seconds
= time(NULL
);
2778 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2779 return VK_ERROR_INITIALIZATION_FAILED
;
2781 device
->sc_state
->uid
= uid
;
2783 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2784 int fd_secure_input
[MAX_SC_PROCS
][2];
2785 int fd_secure_output
[MAX_SC_PROCS
][2];
2787 /* create pipe descriptors (used to communicate between processes) */
2788 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2789 if (pipe(fd_secure_input
[i
]) == -1 ||
2790 pipe(fd_secure_output
[i
]) == -1) {
2791 return VK_ERROR_INITIALIZATION_FAILED
;
2795 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2796 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2797 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2799 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2800 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2801 device
->sc_state
->secure_compile_thread_counter
= process
;
2802 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2804 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2805 return VK_ERROR_INITIALIZATION_FAILED
;
2807 /* Read the init result returned from the secure process */
2808 enum radv_secure_compile_type sc_type
;
2809 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2812 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2813 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2814 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2815 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2818 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2819 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2822 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2823 close(fd_secure_input
[process
][0]);
2824 close(fd_secure_input
[process
][1]);
2825 close(fd_secure_output
[process
][1]);
2826 close(fd_secure_output
[process
][0]);
2828 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2830 /* Destroy any forks that were created sucessfully */
2831 for (unsigned i
= 0; i
< process
; i
++) {
2832 destroy_secure_compile_device(device
, i
);
2835 return VK_ERROR_INITIALIZATION_FAILED
;
2843 radv_device_init_dispatch(struct radv_device
*device
)
2845 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2846 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2848 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2849 /* Vulkan requires that entrypoints for extensions which have not been
2850 * enabled must not be advertised.
2853 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2854 &instance
->enabled_extensions
,
2855 &device
->enabled_extensions
)) {
2856 device
->dispatch
.entrypoints
[i
] = NULL
;
2858 device
->dispatch
.entrypoints
[i
] =
2859 radv_device_dispatch_table
.entrypoints
[i
];
2865 radv_create_pthread_cond(pthread_cond_t
*cond
)
2867 pthread_condattr_t condattr
;
2868 if (pthread_condattr_init(&condattr
)) {
2869 return VK_ERROR_INITIALIZATION_FAILED
;
2872 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2873 pthread_condattr_destroy(&condattr
);
2874 return VK_ERROR_INITIALIZATION_FAILED
;
2876 if (pthread_cond_init(cond
, &condattr
)) {
2877 pthread_condattr_destroy(&condattr
);
2878 return VK_ERROR_INITIALIZATION_FAILED
;
2880 pthread_condattr_destroy(&condattr
);
2884 VkResult
radv_CreateDevice(
2885 VkPhysicalDevice physicalDevice
,
2886 const VkDeviceCreateInfo
* pCreateInfo
,
2887 const VkAllocationCallbacks
* pAllocator
,
2890 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2892 struct radv_device
*device
;
2894 bool keep_shader_info
= false;
2896 /* Check enabled features */
2897 if (pCreateInfo
->pEnabledFeatures
) {
2898 VkPhysicalDeviceFeatures supported_features
;
2899 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2900 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2901 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2902 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2903 for (uint32_t i
= 0; i
< num_features
; i
++) {
2904 if (enabled_feature
[i
] && !supported_feature
[i
])
2905 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2909 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2911 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2913 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2915 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2916 device
->instance
= physical_device
->instance
;
2917 device
->physical_device
= physical_device
;
2919 device
->ws
= physical_device
->ws
;
2921 device
->alloc
= *pAllocator
;
2923 device
->alloc
= physical_device
->instance
->alloc
;
2925 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2926 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2927 int index
= radv_get_device_extension_index(ext_name
);
2928 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2929 vk_free(&device
->alloc
, device
);
2930 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2933 device
->enabled_extensions
.extensions
[index
] = true;
2936 radv_device_init_dispatch(device
);
2938 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2940 /* With update after bind we can't attach bo's to the command buffer
2941 * from the descriptor set anymore, so we have to use a global BO list.
2943 device
->use_global_bo_list
=
2944 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2945 device
->enabled_extensions
.EXT_descriptor_indexing
||
2946 device
->enabled_extensions
.EXT_buffer_device_address
||
2947 device
->enabled_extensions
.KHR_buffer_device_address
;
2949 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2950 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2952 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2953 list_inithead(&device
->shader_slabs
);
2955 radv_bo_list_init(&device
->bo_list
);
2957 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2958 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2959 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2960 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2961 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2963 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2965 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2966 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2967 if (!device
->queues
[qfi
]) {
2968 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2972 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2974 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2976 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2977 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2978 qfi
, q
, queue_create
->flags
,
2980 if (result
!= VK_SUCCESS
)
2985 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2986 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2988 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2989 device
->dfsm_allowed
= device
->pbb_allowed
&&
2990 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2992 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2994 /* The maximum number of scratch waves. Scratch space isn't divided
2995 * evenly between CUs. The number is only a function of the number of CUs.
2996 * We can decrease the constant to decrease the scratch buffer size.
2998 * sctx->scratch_waves must be >= the maximum possible size of
2999 * 1 threadgroup, so that the hw doesn't hang from being unable
3002 * The recommended value is 4 per CU at most. Higher numbers don't
3003 * bring much benefit, but they still occupy chip resources (think
3004 * async compute). I've seen ~2% performance difference between 4 and 32.
3006 uint32_t max_threads_per_block
= 2048;
3007 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
3008 max_threads_per_block
/ 64);
3010 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
3012 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3013 /* If the KMD allows it (there is a KMD hw register for it),
3014 * allow launching waves out-of-order.
3016 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3019 radv_device_init_gs_info(device
);
3021 device
->tess_offchip_block_dw_size
=
3022 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
3024 if (getenv("RADV_TRACE_FILE")) {
3025 const char *filename
= getenv("RADV_TRACE_FILE");
3027 keep_shader_info
= true;
3029 if (!radv_init_trace(device
))
3032 fprintf(stderr
, "*****************************************************************************\n");
3033 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
3034 fprintf(stderr
, "*****************************************************************************\n");
3036 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
3037 radv_dump_enabled_options(device
, stderr
);
3040 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
3041 if (radv_thread_trace
>= 0) {
3042 fprintf(stderr
, "******************************************************************************\n");
3043 fprintf(stderr
, "* WARNING: Thread trace support is experimental and only supported on GFX9+! *\n");
3044 fprintf(stderr
, "******************************************************************************\n");
3046 /* TODO: add support for more ASICs. */
3047 assert(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3049 /* Default buffer size set to 1MB per SE. */
3050 device
->thread_trace_buffer_size
=
3051 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
3052 device
->thread_trace_start_frame
= radv_thread_trace
;
3054 if (!radv_thread_trace_init(device
))
3058 /* Temporarily disable secure compile while we create meta shaders, etc */
3059 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
3061 device
->instance
->num_sc_threads
= 0;
3063 device
->keep_shader_info
= keep_shader_info
;
3064 result
= radv_device_init_meta(device
);
3065 if (result
!= VK_SUCCESS
)
3068 radv_device_init_msaa(device
);
3070 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
3071 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3073 case RADV_QUEUE_GENERAL
:
3074 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3075 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3076 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3078 case RADV_QUEUE_COMPUTE
:
3079 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3080 radeon_emit(device
->empty_cs
[family
], 0);
3083 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3086 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3087 cik_create_gfx_config(device
);
3089 VkPipelineCacheCreateInfo ci
;
3090 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3093 ci
.pInitialData
= NULL
;
3094 ci
.initialDataSize
= 0;
3096 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3098 if (result
!= VK_SUCCESS
)
3101 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3103 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3104 if (result
!= VK_SUCCESS
)
3105 goto fail_mem_cache
;
3107 device
->force_aniso
=
3108 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3109 if (device
->force_aniso
>= 0) {
3110 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3111 1 << util_logbase2(device
->force_aniso
));
3114 /* Fork device for secure compile as required */
3115 device
->instance
->num_sc_threads
= sc_threads
;
3116 if (radv_device_use_secure_compile(device
->instance
)) {
3118 result
= fork_secure_compile_idle_device(device
);
3119 if (result
!= VK_SUCCESS
)
3123 *pDevice
= radv_device_to_handle(device
);
3127 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3129 radv_device_finish_meta(device
);
3131 radv_bo_list_finish(&device
->bo_list
);
3133 radv_thread_trace_finish(device
);
3135 if (device
->trace_bo
)
3136 device
->ws
->buffer_destroy(device
->trace_bo
);
3138 if (device
->gfx_init
)
3139 device
->ws
->buffer_destroy(device
->gfx_init
);
3141 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3142 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3143 radv_queue_finish(&device
->queues
[i
][q
]);
3144 if (device
->queue_count
[i
])
3145 vk_free(&device
->alloc
, device
->queues
[i
]);
3148 vk_free(&device
->alloc
, device
);
3152 void radv_DestroyDevice(
3154 const VkAllocationCallbacks
* pAllocator
)
3156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3161 if (device
->trace_bo
)
3162 device
->ws
->buffer_destroy(device
->trace_bo
);
3164 if (device
->gfx_init
)
3165 device
->ws
->buffer_destroy(device
->gfx_init
);
3167 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3168 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3169 radv_queue_finish(&device
->queues
[i
][q
]);
3170 if (device
->queue_count
[i
])
3171 vk_free(&device
->alloc
, device
->queues
[i
]);
3172 if (device
->empty_cs
[i
])
3173 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3175 radv_device_finish_meta(device
);
3177 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3178 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3180 radv_destroy_shader_slabs(device
);
3182 pthread_cond_destroy(&device
->timeline_cond
);
3183 radv_bo_list_finish(&device
->bo_list
);
3185 radv_thread_trace_finish(device
);
3187 if (radv_device_use_secure_compile(device
->instance
)) {
3188 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3189 destroy_secure_compile_device(device
, i
);
3193 if (device
->sc_state
) {
3194 free(device
->sc_state
->uid
);
3195 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3197 vk_free(&device
->alloc
, device
->sc_state
);
3198 vk_free(&device
->alloc
, device
);
3201 VkResult
radv_EnumerateInstanceLayerProperties(
3202 uint32_t* pPropertyCount
,
3203 VkLayerProperties
* pProperties
)
3205 if (pProperties
== NULL
) {
3206 *pPropertyCount
= 0;
3210 /* None supported at this time */
3211 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3214 VkResult
radv_EnumerateDeviceLayerProperties(
3215 VkPhysicalDevice physicalDevice
,
3216 uint32_t* pPropertyCount
,
3217 VkLayerProperties
* pProperties
)
3219 if (pProperties
== NULL
) {
3220 *pPropertyCount
= 0;
3224 /* None supported at this time */
3225 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3228 void radv_GetDeviceQueue2(
3230 const VkDeviceQueueInfo2
* pQueueInfo
,
3233 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3234 struct radv_queue
*queue
;
3236 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3237 if (pQueueInfo
->flags
!= queue
->flags
) {
3238 /* From the Vulkan 1.1.70 spec:
3240 * "The queue returned by vkGetDeviceQueue2 must have the same
3241 * flags value from this structure as that used at device
3242 * creation time in a VkDeviceQueueCreateInfo instance. If no
3243 * matching flags were specified at device creation time then
3244 * pQueue will return VK_NULL_HANDLE."
3246 *pQueue
= VK_NULL_HANDLE
;
3250 *pQueue
= radv_queue_to_handle(queue
);
3253 void radv_GetDeviceQueue(
3255 uint32_t queueFamilyIndex
,
3256 uint32_t queueIndex
,
3259 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3260 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3261 .queueFamilyIndex
= queueFamilyIndex
,
3262 .queueIndex
= queueIndex
3265 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3269 fill_geom_tess_rings(struct radv_queue
*queue
,
3271 bool add_sample_positions
,
3272 uint32_t esgs_ring_size
,
3273 struct radeon_winsys_bo
*esgs_ring_bo
,
3274 uint32_t gsvs_ring_size
,
3275 struct radeon_winsys_bo
*gsvs_ring_bo
,
3276 uint32_t tess_factor_ring_size
,
3277 uint32_t tess_offchip_ring_offset
,
3278 uint32_t tess_offchip_ring_size
,
3279 struct radeon_winsys_bo
*tess_rings_bo
)
3281 uint32_t *desc
= &map
[4];
3284 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3286 /* stride 0, num records - size, add tid, swizzle, elsize4,
3289 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3290 S_008F04_SWIZZLE_ENABLE(true);
3291 desc
[2] = esgs_ring_size
;
3292 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3293 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3294 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3295 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3296 S_008F0C_INDEX_STRIDE(3) |
3297 S_008F0C_ADD_TID_ENABLE(1);
3299 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3300 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3301 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3302 S_008F0C_RESOURCE_LEVEL(1);
3304 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3306 S_008F0C_ELEMENT_SIZE(1);
3309 /* GS entry for ES->GS ring */
3310 /* stride 0, num records - size, elsize0,
3313 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3314 desc
[6] = esgs_ring_size
;
3315 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3316 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3317 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3318 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3320 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3321 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3322 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3323 S_008F0C_RESOURCE_LEVEL(1);
3325 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3326 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3333 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3335 /* VS entry for GS->VS ring */
3336 /* stride 0, num records - size, elsize0,
3339 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3340 desc
[2] = gsvs_ring_size
;
3341 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3342 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3343 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3344 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3346 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3347 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3348 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3349 S_008F0C_RESOURCE_LEVEL(1);
3351 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3352 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3355 /* stride gsvs_itemsize, num records 64
3356 elsize 4, index stride 16 */
3357 /* shader will patch stride and desc[2] */
3359 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3360 S_008F04_SWIZZLE_ENABLE(1);
3362 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3363 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3364 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3365 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3366 S_008F0C_INDEX_STRIDE(1) |
3367 S_008F0C_ADD_TID_ENABLE(true);
3369 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3370 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3371 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3372 S_008F0C_RESOURCE_LEVEL(1);
3374 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3376 S_008F0C_ELEMENT_SIZE(1);
3383 if (tess_rings_bo
) {
3384 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3385 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3388 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3389 desc
[2] = tess_factor_ring_size
;
3390 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3391 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3392 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3393 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3395 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3396 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3397 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3398 S_008F0C_RESOURCE_LEVEL(1);
3400 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3401 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3404 desc
[4] = tess_offchip_va
;
3405 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3406 desc
[6] = tess_offchip_ring_size
;
3407 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3412 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3413 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3414 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3415 S_008F0C_RESOURCE_LEVEL(1);
3417 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3418 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3424 if (add_sample_positions
) {
3425 /* add sample positions after all rings */
3426 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3428 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3430 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3432 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3437 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3439 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3440 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3441 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3442 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3443 unsigned max_offchip_buffers
;
3444 unsigned offchip_granularity
;
3445 unsigned hs_offchip_param
;
3449 * This must be one less than the maximum number due to a hw limitation.
3450 * Various hardware bugs need thGFX7
3453 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3454 * Gfx7 should limit max_offchip_buffers to 508
3455 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3457 * Follow AMDVLK here.
3459 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3460 max_offchip_buffers_per_se
= 256;
3461 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3462 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3463 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3464 --max_offchip_buffers_per_se
;
3466 max_offchip_buffers
= max_offchip_buffers_per_se
*
3467 device
->physical_device
->rad_info
.max_se
;
3469 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3470 * around by setting 4K granularity.
3472 if (device
->tess_offchip_block_dw_size
== 4096) {
3473 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3474 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3476 assert(device
->tess_offchip_block_dw_size
== 8192);
3477 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3480 switch (device
->physical_device
->rad_info
.chip_class
) {
3482 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3487 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3495 *max_offchip_buffers_p
= max_offchip_buffers
;
3496 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3497 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3498 --max_offchip_buffers
;
3500 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3501 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3504 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3506 return hs_offchip_param
;
3510 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3511 struct radeon_winsys_bo
*esgs_ring_bo
,
3512 uint32_t esgs_ring_size
,
3513 struct radeon_winsys_bo
*gsvs_ring_bo
,
3514 uint32_t gsvs_ring_size
)
3516 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3520 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3523 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3525 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3526 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3527 radeon_emit(cs
, esgs_ring_size
>> 8);
3528 radeon_emit(cs
, gsvs_ring_size
>> 8);
3530 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3531 radeon_emit(cs
, esgs_ring_size
>> 8);
3532 radeon_emit(cs
, gsvs_ring_size
>> 8);
3537 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3538 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3539 struct radeon_winsys_bo
*tess_rings_bo
)
3546 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3548 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3550 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3551 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3552 S_030938_SIZE(tf_ring_size
/ 4));
3553 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3556 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3557 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3558 S_030984_BASE_HI(tf_va
>> 40));
3559 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3560 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3561 S_030944_BASE_HI(tf_va
>> 40));
3563 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3566 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3567 S_008988_SIZE(tf_ring_size
/ 4));
3568 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3570 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3576 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3577 uint32_t size_per_wave
, uint32_t waves
,
3578 struct radeon_winsys_bo
*scratch_bo
)
3580 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3586 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3588 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3589 S_0286E8_WAVES(waves
) |
3590 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3594 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3595 uint32_t size_per_wave
, uint32_t waves
,
3596 struct radeon_winsys_bo
*compute_scratch_bo
)
3598 uint64_t scratch_va
;
3600 if (!compute_scratch_bo
)
3603 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3605 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3607 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3608 radeon_emit(cs
, scratch_va
);
3609 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3610 S_008F04_SWIZZLE_ENABLE(1));
3612 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3613 S_00B860_WAVES(waves
) |
3614 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3618 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3619 struct radeon_cmdbuf
*cs
,
3620 struct radeon_winsys_bo
*descriptor_bo
)
3627 va
= radv_buffer_get_va(descriptor_bo
);
3629 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3631 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3632 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3633 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3634 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3635 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3637 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3638 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3641 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3642 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3643 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3644 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3645 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3647 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3648 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3652 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3653 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3654 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3655 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3656 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3657 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3659 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3660 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3667 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3669 struct radv_device
*device
= queue
->device
;
3671 if (device
->gfx_init
) {
3672 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3674 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3675 radeon_emit(cs
, va
);
3676 radeon_emit(cs
, va
>> 32);
3677 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3679 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3681 struct radv_physical_device
*physical_device
= device
->physical_device
;
3682 si_emit_graphics(physical_device
, cs
);
3687 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3689 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3690 si_emit_compute(physical_device
, cs
);
3694 radv_get_preamble_cs(struct radv_queue
*queue
,
3695 uint32_t scratch_size_per_wave
,
3696 uint32_t scratch_waves
,
3697 uint32_t compute_scratch_size_per_wave
,
3698 uint32_t compute_scratch_waves
,
3699 uint32_t esgs_ring_size
,
3700 uint32_t gsvs_ring_size
,
3701 bool needs_tess_rings
,
3704 bool needs_sample_positions
,
3705 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3706 struct radeon_cmdbuf
**initial_preamble_cs
,
3707 struct radeon_cmdbuf
**continue_preamble_cs
)
3709 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3710 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3711 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3712 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3713 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3714 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3715 struct radeon_winsys_bo
*gds_bo
= NULL
;
3716 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3717 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3718 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3719 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3720 unsigned max_offchip_buffers
;
3721 unsigned hs_offchip_param
= 0;
3722 unsigned tess_offchip_ring_offset
;
3723 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3724 if (!queue
->has_tess_rings
) {
3725 if (needs_tess_rings
)
3726 add_tess_rings
= true;
3728 if (!queue
->has_gds
) {
3732 if (!queue
->has_gds_oa
) {
3736 if (!queue
->has_sample_positions
) {
3737 if (needs_sample_positions
)
3738 add_sample_positions
= true;
3740 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3741 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3742 &max_offchip_buffers
);
3743 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3744 tess_offchip_ring_size
= max_offchip_buffers
*
3745 queue
->device
->tess_offchip_block_dw_size
* 4;
3747 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3748 if (scratch_size_per_wave
)
3749 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3753 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3754 if (compute_scratch_size_per_wave
)
3755 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3757 compute_scratch_waves
= 0;
3759 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3760 scratch_waves
<= queue
->scratch_waves
&&
3761 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3762 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3763 esgs_ring_size
<= queue
->esgs_ring_size
&&
3764 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3765 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3766 queue
->initial_preamble_cs
) {
3767 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3768 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3769 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3770 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3771 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3772 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3773 *continue_preamble_cs
= NULL
;
3777 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3778 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3779 if (scratch_size
> queue_scratch_size
) {
3780 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3785 RADV_BO_PRIORITY_SCRATCH
);
3789 scratch_bo
= queue
->scratch_bo
;
3791 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3792 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3793 if (compute_scratch_size
> compute_queue_scratch_size
) {
3794 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3795 compute_scratch_size
,
3799 RADV_BO_PRIORITY_SCRATCH
);
3800 if (!compute_scratch_bo
)
3804 compute_scratch_bo
= queue
->compute_scratch_bo
;
3806 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3807 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3812 RADV_BO_PRIORITY_SCRATCH
);
3816 esgs_ring_bo
= queue
->esgs_ring_bo
;
3817 esgs_ring_size
= queue
->esgs_ring_size
;
3820 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3821 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3826 RADV_BO_PRIORITY_SCRATCH
);
3830 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3831 gsvs_ring_size
= queue
->gsvs_ring_size
;
3834 if (add_tess_rings
) {
3835 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3836 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3840 RADV_BO_PRIORITY_SCRATCH
);
3844 tess_rings_bo
= queue
->tess_rings_bo
;
3848 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3850 /* 4 streamout GDS counters.
3851 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3853 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3857 RADV_BO_PRIORITY_SCRATCH
);
3861 gds_bo
= queue
->gds_bo
;
3865 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3867 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3871 RADV_BO_PRIORITY_SCRATCH
);
3875 gds_oa_bo
= queue
->gds_oa_bo
;
3878 if (scratch_bo
!= queue
->scratch_bo
||
3879 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3880 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3881 tess_rings_bo
!= queue
->tess_rings_bo
||
3882 add_sample_positions
) {
3884 if (gsvs_ring_bo
|| esgs_ring_bo
||
3885 tess_rings_bo
|| add_sample_positions
) {
3886 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3887 if (add_sample_positions
)
3888 size
+= 128; /* 64+32+16+8 = 120 bytes */
3890 else if (scratch_bo
)
3891 size
= 8; /* 2 dword */
3893 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3897 RADEON_FLAG_CPU_ACCESS
|
3898 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3899 RADEON_FLAG_READ_ONLY
,
3900 RADV_BO_PRIORITY_DESCRIPTOR
);
3904 descriptor_bo
= queue
->descriptor_bo
;
3906 if (descriptor_bo
!= queue
->descriptor_bo
) {
3907 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3910 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3911 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3912 S_008F04_SWIZZLE_ENABLE(1);
3913 map
[0] = scratch_va
;
3917 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3918 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3919 esgs_ring_size
, esgs_ring_bo
,
3920 gsvs_ring_size
, gsvs_ring_bo
,
3921 tess_factor_ring_size
,
3922 tess_offchip_ring_offset
,
3923 tess_offchip_ring_size
,
3926 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3929 for(int i
= 0; i
< 3; ++i
) {
3930 struct radeon_cmdbuf
*cs
= NULL
;
3931 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3932 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3939 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3941 /* Emit initial configuration. */
3942 switch (queue
->queue_family_index
) {
3943 case RADV_QUEUE_GENERAL
:
3944 radv_init_graphics_state(cs
, queue
);
3946 case RADV_QUEUE_COMPUTE
:
3947 radv_init_compute_state(cs
, queue
);
3949 case RADV_QUEUE_TRANSFER
:
3953 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3954 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3955 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3957 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3958 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3961 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3962 gsvs_ring_bo
, gsvs_ring_size
);
3963 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3964 tess_factor_ring_size
, tess_rings_bo
);
3965 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3966 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3967 compute_scratch_waves
, compute_scratch_bo
);
3968 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3969 scratch_waves
, scratch_bo
);
3972 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3974 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3976 if (queue
->device
->trace_bo
)
3977 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3980 si_cs_emit_cache_flush(cs
,
3981 queue
->device
->physical_device
->rad_info
.chip_class
,
3983 queue
->queue_family_index
== RING_COMPUTE
&&
3984 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3985 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3986 RADV_CMD_FLAG_INV_ICACHE
|
3987 RADV_CMD_FLAG_INV_SCACHE
|
3988 RADV_CMD_FLAG_INV_VCACHE
|
3989 RADV_CMD_FLAG_INV_L2
|
3990 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3991 } else if (i
== 1) {
3992 si_cs_emit_cache_flush(cs
,
3993 queue
->device
->physical_device
->rad_info
.chip_class
,
3995 queue
->queue_family_index
== RING_COMPUTE
&&
3996 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3997 RADV_CMD_FLAG_INV_ICACHE
|
3998 RADV_CMD_FLAG_INV_SCACHE
|
3999 RADV_CMD_FLAG_INV_VCACHE
|
4000 RADV_CMD_FLAG_INV_L2
|
4001 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
4004 if (!queue
->device
->ws
->cs_finalize(cs
))
4008 if (queue
->initial_full_flush_preamble_cs
)
4009 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
4011 if (queue
->initial_preamble_cs
)
4012 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
4014 if (queue
->continue_preamble_cs
)
4015 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
4017 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
4018 queue
->initial_preamble_cs
= dest_cs
[1];
4019 queue
->continue_preamble_cs
= dest_cs
[2];
4021 if (scratch_bo
!= queue
->scratch_bo
) {
4022 if (queue
->scratch_bo
)
4023 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
4024 queue
->scratch_bo
= scratch_bo
;
4026 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
4027 queue
->scratch_waves
= scratch_waves
;
4029 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
4030 if (queue
->compute_scratch_bo
)
4031 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
4032 queue
->compute_scratch_bo
= compute_scratch_bo
;
4034 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
4035 queue
->compute_scratch_waves
= compute_scratch_waves
;
4037 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
4038 if (queue
->esgs_ring_bo
)
4039 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
4040 queue
->esgs_ring_bo
= esgs_ring_bo
;
4041 queue
->esgs_ring_size
= esgs_ring_size
;
4044 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
4045 if (queue
->gsvs_ring_bo
)
4046 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
4047 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
4048 queue
->gsvs_ring_size
= gsvs_ring_size
;
4051 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
4052 queue
->tess_rings_bo
= tess_rings_bo
;
4053 queue
->has_tess_rings
= true;
4056 if (gds_bo
!= queue
->gds_bo
) {
4057 queue
->gds_bo
= gds_bo
;
4058 queue
->has_gds
= true;
4061 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
4062 queue
->gds_oa_bo
= gds_oa_bo
;
4063 queue
->has_gds_oa
= true;
4066 if (descriptor_bo
!= queue
->descriptor_bo
) {
4067 if (queue
->descriptor_bo
)
4068 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
4070 queue
->descriptor_bo
= descriptor_bo
;
4073 if (add_sample_positions
)
4074 queue
->has_sample_positions
= true;
4076 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
4077 *initial_preamble_cs
= queue
->initial_preamble_cs
;
4078 *continue_preamble_cs
= queue
->continue_preamble_cs
;
4079 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
4080 *continue_preamble_cs
= NULL
;
4083 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4085 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4086 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4087 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4088 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4089 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4090 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4091 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4092 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4093 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4094 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4095 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4096 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4097 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4098 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4099 queue
->device
->ws
->buffer_destroy(gds_bo
);
4100 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4101 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4103 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4106 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4107 struct radv_winsys_sem_counts
*counts
,
4109 struct radv_semaphore_part
**sems
,
4110 const uint64_t *timeline_values
,
4114 int syncobj_idx
= 0, sem_idx
= 0;
4116 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4119 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4120 switch(sems
[i
]->kind
) {
4121 case RADV_SEMAPHORE_SYNCOBJ
:
4122 counts
->syncobj_count
++;
4124 case RADV_SEMAPHORE_WINSYS
:
4125 counts
->sem_count
++;
4127 case RADV_SEMAPHORE_NONE
:
4129 case RADV_SEMAPHORE_TIMELINE
:
4130 counts
->syncobj_count
++;
4135 if (_fence
!= VK_NULL_HANDLE
) {
4136 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4137 if (fence
->temp_syncobj
|| fence
->syncobj
)
4138 counts
->syncobj_count
++;
4141 if (counts
->syncobj_count
) {
4142 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4143 if (!counts
->syncobj
)
4144 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4147 if (counts
->sem_count
) {
4148 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4150 free(counts
->syncobj
);
4151 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4155 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4156 switch(sems
[i
]->kind
) {
4157 case RADV_SEMAPHORE_NONE
:
4158 unreachable("Empty semaphore");
4160 case RADV_SEMAPHORE_SYNCOBJ
:
4161 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4163 case RADV_SEMAPHORE_WINSYS
:
4164 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4166 case RADV_SEMAPHORE_TIMELINE
: {
4167 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4168 struct radv_timeline_point
*point
= NULL
;
4170 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4172 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4175 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4178 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4180 /* Explicitly remove the semaphore so we might not find
4181 * a point later post-submit. */
4189 if (_fence
!= VK_NULL_HANDLE
) {
4190 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4191 if (fence
->temp_syncobj
)
4192 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4193 else if (fence
->syncobj
)
4194 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4197 assert(syncobj_idx
<= counts
->syncobj_count
);
4198 counts
->syncobj_count
= syncobj_idx
;
4204 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4206 free(sem_info
->wait
.syncobj
);
4207 free(sem_info
->wait
.sem
);
4208 free(sem_info
->signal
.syncobj
);
4209 free(sem_info
->signal
.sem
);
4213 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4215 struct radv_semaphore_part
*sems
)
4217 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4218 radv_destroy_semaphore_part(device
, sems
+ i
);
4223 radv_alloc_sem_info(struct radv_device
*device
,
4224 struct radv_winsys_sem_info
*sem_info
,
4226 struct radv_semaphore_part
**wait_sems
,
4227 const uint64_t *wait_values
,
4228 int num_signal_sems
,
4229 struct radv_semaphore_part
**signal_sems
,
4230 const uint64_t *signal_values
,
4234 memset(sem_info
, 0, sizeof(*sem_info
));
4236 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4239 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4241 radv_free_sem_info(sem_info
);
4243 /* caller can override these */
4244 sem_info
->cs_emit_wait
= true;
4245 sem_info
->cs_emit_signal
= true;
4250 radv_finalize_timelines(struct radv_device
*device
,
4251 uint32_t num_wait_sems
,
4252 struct radv_semaphore_part
**wait_sems
,
4253 const uint64_t *wait_values
,
4254 uint32_t num_signal_sems
,
4255 struct radv_semaphore_part
**signal_sems
,
4256 const uint64_t *signal_values
,
4257 struct list_head
*processing_list
)
4259 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4260 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4261 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4262 struct radv_timeline_point
*point
=
4263 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4264 point
->wait_count
-= 2;
4265 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4268 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4269 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4270 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4271 struct radv_timeline_point
*point
=
4272 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4273 signal_sems
[i
]->timeline
.highest_submitted
=
4274 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4275 point
->wait_count
-= 2;
4276 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4277 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4283 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4284 const VkSparseBufferMemoryBindInfo
*bind
)
4286 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4288 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4289 struct radv_device_memory
*mem
= NULL
;
4291 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4292 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4294 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4295 bind
->pBinds
[i
].resourceOffset
,
4296 bind
->pBinds
[i
].size
,
4297 mem
? mem
->bo
: NULL
,
4298 bind
->pBinds
[i
].memoryOffset
);
4303 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4304 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4306 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4308 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4309 struct radv_device_memory
*mem
= NULL
;
4311 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4312 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4314 device
->ws
->buffer_virtual_bind(image
->bo
,
4315 bind
->pBinds
[i
].resourceOffset
,
4316 bind
->pBinds
[i
].size
,
4317 mem
? mem
->bo
: NULL
,
4318 bind
->pBinds
[i
].memoryOffset
);
4323 radv_get_preambles(struct radv_queue
*queue
,
4324 const VkCommandBuffer
*cmd_buffers
,
4325 uint32_t cmd_buffer_count
,
4326 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4327 struct radeon_cmdbuf
**initial_preamble_cs
,
4328 struct radeon_cmdbuf
**continue_preamble_cs
)
4330 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4331 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4332 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4333 bool tess_rings_needed
= false;
4334 bool gds_needed
= false;
4335 bool gds_oa_needed
= false;
4336 bool sample_positions_needed
= false;
4338 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4339 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4342 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4343 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4344 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4345 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4346 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4347 cmd_buffer
->compute_scratch_waves_wanted
);
4348 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4349 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4350 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4351 gds_needed
|= cmd_buffer
->gds_needed
;
4352 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4353 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4356 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4357 compute_scratch_size_per_wave
, compute_waves_wanted
,
4358 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4359 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4360 initial_full_flush_preamble_cs
,
4361 initial_preamble_cs
, continue_preamble_cs
);
4364 struct radv_deferred_queue_submission
{
4365 struct radv_queue
*queue
;
4366 VkCommandBuffer
*cmd_buffers
;
4367 uint32_t cmd_buffer_count
;
4369 /* Sparse bindings that happen on a queue. */
4370 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4371 uint32_t buffer_bind_count
;
4372 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4373 uint32_t image_opaque_bind_count
;
4376 VkShaderStageFlags wait_dst_stage_mask
;
4377 struct radv_semaphore_part
**wait_semaphores
;
4378 uint32_t wait_semaphore_count
;
4379 struct radv_semaphore_part
**signal_semaphores
;
4380 uint32_t signal_semaphore_count
;
4383 uint64_t *wait_values
;
4384 uint64_t *signal_values
;
4386 struct radv_semaphore_part
*temporary_semaphore_parts
;
4387 uint32_t temporary_semaphore_part_count
;
4389 struct list_head queue_pending_list
;
4390 uint32_t submission_wait_count
;
4391 struct radv_timeline_waiter
*wait_nodes
;
4393 struct list_head processing_list
;
4396 struct radv_queue_submission
{
4397 const VkCommandBuffer
*cmd_buffers
;
4398 uint32_t cmd_buffer_count
;
4400 /* Sparse bindings that happen on a queue. */
4401 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4402 uint32_t buffer_bind_count
;
4403 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4404 uint32_t image_opaque_bind_count
;
4407 VkPipelineStageFlags wait_dst_stage_mask
;
4408 const VkSemaphore
*wait_semaphores
;
4409 uint32_t wait_semaphore_count
;
4410 const VkSemaphore
*signal_semaphores
;
4411 uint32_t signal_semaphore_count
;
4414 const uint64_t *wait_values
;
4415 uint32_t wait_value_count
;
4416 const uint64_t *signal_values
;
4417 uint32_t signal_value_count
;
4421 radv_create_deferred_submission(struct radv_queue
*queue
,
4422 const struct radv_queue_submission
*submission
,
4423 struct radv_deferred_queue_submission
**out
)
4425 struct radv_deferred_queue_submission
*deferred
= NULL
;
4426 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4428 uint32_t temporary_count
= 0;
4429 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4430 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4431 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4435 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4436 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4437 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4438 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4439 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4440 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4441 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4442 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4443 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4445 deferred
= calloc(1, size
);
4447 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4449 deferred
->queue
= queue
;
4451 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4452 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4453 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4454 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4456 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4457 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4458 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4459 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4461 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4462 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4463 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4464 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4466 deferred
->flush_caches
= submission
->flush_caches
;
4467 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4469 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4470 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4472 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4473 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4475 deferred
->fence
= submission
->fence
;
4477 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4478 deferred
->temporary_semaphore_part_count
= temporary_count
;
4480 uint32_t temporary_idx
= 0;
4481 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4482 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4483 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4484 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4485 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4486 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4489 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4492 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4493 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4494 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4495 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4497 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4501 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4502 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4503 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4504 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4506 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4507 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4508 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4509 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4516 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4517 struct list_head
*processing_list
)
4519 uint32_t wait_cnt
= 0;
4520 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4521 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4522 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4523 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4524 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4526 waiter
->value
= submission
->wait_values
[i
];
4527 waiter
->submission
= submission
;
4528 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4531 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4535 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4537 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4538 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4540 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4542 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4543 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4545 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4546 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4547 list_addtail(&submission
->processing_list
, processing_list
);
4552 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4553 struct list_head
*processing_list
)
4555 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4556 list_del(&submission
->queue_pending_list
);
4558 /* trigger the next submission in the queue. */
4559 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4560 struct radv_deferred_queue_submission
*next_submission
=
4561 list_first_entry(&submission
->queue
->pending_submissions
,
4562 struct radv_deferred_queue_submission
,
4563 queue_pending_list
);
4564 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4565 list_addtail(&next_submission
->processing_list
, processing_list
);
4568 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4570 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4574 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4575 struct list_head
*processing_list
)
4577 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4578 struct radv_queue
*queue
= submission
->queue
;
4579 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4580 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4581 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4582 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4583 bool can_patch
= true;
4585 struct radv_winsys_sem_info sem_info
;
4588 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4589 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4590 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4592 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4593 submission
->cmd_buffer_count
,
4594 &initial_preamble_cs
,
4595 &initial_flush_preamble_cs
,
4596 &continue_preamble_cs
);
4597 if (result
!= VK_SUCCESS
)
4600 result
= radv_alloc_sem_info(queue
->device
,
4602 submission
->wait_semaphore_count
,
4603 submission
->wait_semaphores
,
4604 submission
->wait_values
,
4605 submission
->signal_semaphore_count
,
4606 submission
->signal_semaphores
,
4607 submission
->signal_values
,
4609 if (result
!= VK_SUCCESS
)
4612 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4613 radv_sparse_buffer_bind_memory(queue
->device
,
4614 submission
->buffer_binds
+ i
);
4617 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4618 radv_sparse_image_opaque_bind_memory(queue
->device
,
4619 submission
->image_opaque_binds
+ i
);
4622 if (!submission
->cmd_buffer_count
) {
4623 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4624 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4629 radv_loge("failed to submit CS\n");
4635 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4636 (submission
->cmd_buffer_count
));
4638 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4639 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4640 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4642 cs_array
[j
] = cmd_buffer
->cs
;
4643 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4646 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4649 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4650 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4651 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4653 advance
= MIN2(max_cs_submission
,
4654 submission
->cmd_buffer_count
- j
);
4656 if (queue
->device
->trace_bo
)
4657 *queue
->device
->trace_id_ptr
= 0;
4659 sem_info
.cs_emit_wait
= j
== 0;
4660 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4662 if (unlikely(queue
->device
->use_global_bo_list
)) {
4663 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4664 bo_list
= &queue
->device
->bo_list
.list
;
4667 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4668 advance
, initial_preamble
, continue_preamble_cs
,
4670 can_patch
, base_fence
);
4672 if (unlikely(queue
->device
->use_global_bo_list
))
4673 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4676 radv_loge("failed to submit CS\n");
4679 if (queue
->device
->trace_bo
) {
4680 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4688 radv_free_temp_syncobjs(queue
->device
,
4689 submission
->temporary_semaphore_part_count
,
4690 submission
->temporary_semaphore_parts
);
4691 radv_finalize_timelines(queue
->device
,
4692 submission
->wait_semaphore_count
,
4693 submission
->wait_semaphores
,
4694 submission
->wait_values
,
4695 submission
->signal_semaphore_count
,
4696 submission
->signal_semaphores
,
4697 submission
->signal_values
,
4699 /* Has to happen after timeline finalization to make sure the
4700 * condition variable is only triggered when timelines and queue have
4702 radv_queue_submission_update_queue(submission
, processing_list
);
4703 radv_free_sem_info(&sem_info
);
4708 radv_free_temp_syncobjs(queue
->device
,
4709 submission
->temporary_semaphore_part_count
,
4710 submission
->temporary_semaphore_parts
);
4712 return VK_ERROR_DEVICE_LOST
;
4716 radv_process_submissions(struct list_head
*processing_list
)
4718 while(!list_is_empty(processing_list
)) {
4719 struct radv_deferred_queue_submission
*submission
=
4720 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4721 list_del(&submission
->processing_list
);
4723 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4724 if (result
!= VK_SUCCESS
)
4730 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4731 const struct radv_queue_submission
*submission
)
4733 struct radv_deferred_queue_submission
*deferred
= NULL
;
4735 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4736 if (result
!= VK_SUCCESS
)
4739 struct list_head processing_list
;
4740 list_inithead(&processing_list
);
4742 radv_queue_enqueue_submission(deferred
, &processing_list
);
4743 return radv_process_submissions(&processing_list
);
4747 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4749 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4750 struct radv_winsys_sem_info sem_info
;
4754 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4755 0, NULL
, VK_NULL_HANDLE
);
4756 if (result
!= VK_SUCCESS
)
4759 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1, NULL
,
4760 NULL
, &sem_info
, NULL
, false, NULL
);
4761 radv_free_sem_info(&sem_info
);
4765 /* Signals fence as soon as all the work currently put on queue is done. */
4766 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4769 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4774 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4776 return info
->commandBufferCount
||
4777 info
->waitSemaphoreCount
||
4778 info
->signalSemaphoreCount
;
4781 VkResult
radv_QueueSubmit(
4783 uint32_t submitCount
,
4784 const VkSubmitInfo
* pSubmits
,
4787 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4789 uint32_t fence_idx
= 0;
4790 bool flushed_caches
= false;
4792 if (fence
!= VK_NULL_HANDLE
) {
4793 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4794 if (radv_submit_has_effects(pSubmits
+ i
))
4797 fence_idx
= UINT32_MAX
;
4799 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4800 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4803 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4804 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4805 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4808 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4809 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4811 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4812 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4813 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4814 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4815 .flush_caches
= !flushed_caches
,
4816 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4817 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4818 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4819 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4820 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4821 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4822 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4823 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4824 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4826 if (result
!= VK_SUCCESS
)
4829 flushed_caches
= true;
4832 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4833 result
= radv_signal_fence(queue
, fence
);
4834 if (result
!= VK_SUCCESS
)
4841 VkResult
radv_QueueWaitIdle(
4844 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4846 pthread_mutex_lock(&queue
->pending_mutex
);
4847 while (!list_is_empty(&queue
->pending_submissions
)) {
4848 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4850 pthread_mutex_unlock(&queue
->pending_mutex
);
4852 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4853 radv_queue_family_to_ring(queue
->queue_family_index
),
4858 VkResult
radv_DeviceWaitIdle(
4861 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4863 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4864 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4865 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4871 VkResult
radv_EnumerateInstanceExtensionProperties(
4872 const char* pLayerName
,
4873 uint32_t* pPropertyCount
,
4874 VkExtensionProperties
* pProperties
)
4876 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4878 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4879 if (radv_supported_instance_extensions
.extensions
[i
]) {
4880 vk_outarray_append(&out
, prop
) {
4881 *prop
= radv_instance_extensions
[i
];
4886 return vk_outarray_status(&out
);
4889 VkResult
radv_EnumerateDeviceExtensionProperties(
4890 VkPhysicalDevice physicalDevice
,
4891 const char* pLayerName
,
4892 uint32_t* pPropertyCount
,
4893 VkExtensionProperties
* pProperties
)
4895 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4896 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4898 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4899 if (device
->supported_extensions
.extensions
[i
]) {
4900 vk_outarray_append(&out
, prop
) {
4901 *prop
= radv_device_extensions
[i
];
4906 return vk_outarray_status(&out
);
4909 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4910 VkInstance _instance
,
4913 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4915 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4916 * when we have to return valid function pointers, NULL, or it's left
4917 * undefined. See the table for exact details.
4922 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4923 if (strcmp(pName, "vk" #entrypoint) == 0) \
4924 return (PFN_vkVoidFunction)radv_##entrypoint
4926 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4927 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4928 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4929 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4931 #undef LOOKUP_RADV_ENTRYPOINT
4933 if (instance
== NULL
)
4936 int idx
= radv_get_instance_entrypoint_index(pName
);
4938 return instance
->dispatch
.entrypoints
[idx
];
4940 idx
= radv_get_physical_device_entrypoint_index(pName
);
4942 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4944 idx
= radv_get_device_entrypoint_index(pName
);
4946 return instance
->device_dispatch
.entrypoints
[idx
];
4951 /* The loader wants us to expose a second GetInstanceProcAddr function
4952 * to work around certain LD_PRELOAD issues seen in apps.
4955 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4956 VkInstance instance
,
4960 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4961 VkInstance instance
,
4964 return radv_GetInstanceProcAddr(instance
, pName
);
4968 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4969 VkInstance _instance
,
4973 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4974 VkInstance _instance
,
4977 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4979 if (!pName
|| !instance
)
4982 int idx
= radv_get_physical_device_entrypoint_index(pName
);
4986 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4989 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4993 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4995 if (!device
|| !pName
)
4998 int idx
= radv_get_device_entrypoint_index(pName
);
5002 return device
->dispatch
.entrypoints
[idx
];
5005 bool radv_get_memory_fd(struct radv_device
*device
,
5006 struct radv_device_memory
*memory
,
5009 struct radeon_bo_metadata metadata
;
5011 if (memory
->image
) {
5012 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
5013 radv_init_metadata(device
, memory
->image
, &metadata
);
5014 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
5017 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
5022 static void radv_free_memory(struct radv_device
*device
,
5023 const VkAllocationCallbacks
* pAllocator
,
5024 struct radv_device_memory
*mem
)
5029 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5030 if (mem
->android_hardware_buffer
)
5031 AHardwareBuffer_release(mem
->android_hardware_buffer
);
5035 radv_bo_list_remove(device
, mem
->bo
);
5036 device
->ws
->buffer_destroy(mem
->bo
);
5040 vk_free2(&device
->alloc
, pAllocator
, mem
);
5043 static VkResult
radv_alloc_memory(struct radv_device
*device
,
5044 const VkMemoryAllocateInfo
* pAllocateInfo
,
5045 const VkAllocationCallbacks
* pAllocator
,
5046 VkDeviceMemory
* pMem
)
5048 struct radv_device_memory
*mem
;
5050 enum radeon_bo_domain domain
;
5052 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
5054 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
5056 const VkImportMemoryFdInfoKHR
*import_info
=
5057 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
5058 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
5059 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
5060 const VkExportMemoryAllocateInfo
*export_info
=
5061 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
5062 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
5063 vk_find_struct_const(pAllocateInfo
->pNext
,
5064 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
5065 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
5066 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
5068 const struct wsi_memory_allocate_info
*wsi_info
=
5069 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
5071 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
5072 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
5073 /* Apparently, this is allowed */
5074 *pMem
= VK_NULL_HANDLE
;
5078 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
5079 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5081 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5083 if (wsi_info
&& wsi_info
->implicit_sync
)
5084 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
5086 if (dedicate_info
) {
5087 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
5088 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
5094 float priority_float
= 0.5;
5095 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
5096 vk_find_struct_const(pAllocateInfo
->pNext
,
5097 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
5099 priority_float
= priority_ext
->priority
;
5101 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
5102 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
5104 mem
->user_ptr
= NULL
;
5107 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5108 mem
->android_hardware_buffer
= NULL
;
5111 if (ahb_import_info
) {
5112 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
5113 if (result
!= VK_SUCCESS
)
5115 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
5116 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5117 if (result
!= VK_SUCCESS
)
5119 } else if (import_info
) {
5120 assert(import_info
->handleType
==
5121 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5122 import_info
->handleType
==
5123 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5124 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5127 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5130 close(import_info
->fd
);
5132 } else if (host_ptr_info
) {
5133 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5134 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5135 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5136 pAllocateInfo
->allocationSize
,
5139 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5142 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5145 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5146 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5147 radv_is_mem_type_gtt_cached(mem_type_index
))
5148 domain
= RADEON_DOMAIN_GTT
;
5150 domain
= RADEON_DOMAIN_VRAM
;
5152 if (radv_is_mem_type_vram(mem_type_index
))
5153 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5155 flags
|= RADEON_FLAG_CPU_ACCESS
;
5157 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5158 flags
|= RADEON_FLAG_GTT_WC
;
5160 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5161 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5162 if (device
->use_global_bo_list
) {
5163 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5167 if (radv_is_mem_type_uncached(mem_type_index
)) {
5168 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5169 flags
|= RADEON_FLAG_VA_UNCACHED
;
5172 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5173 domain
, flags
, priority
);
5176 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5179 mem
->type_index
= mem_type_index
;
5182 result
= radv_bo_list_add(device
, mem
->bo
);
5183 if (result
!= VK_SUCCESS
)
5186 *pMem
= radv_device_memory_to_handle(mem
);
5191 radv_free_memory(device
, pAllocator
,mem
);
5196 VkResult
radv_AllocateMemory(
5198 const VkMemoryAllocateInfo
* pAllocateInfo
,
5199 const VkAllocationCallbacks
* pAllocator
,
5200 VkDeviceMemory
* pMem
)
5202 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5203 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5206 void radv_FreeMemory(
5208 VkDeviceMemory _mem
,
5209 const VkAllocationCallbacks
* pAllocator
)
5211 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5212 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5214 radv_free_memory(device
, pAllocator
, mem
);
5217 VkResult
radv_MapMemory(
5219 VkDeviceMemory _memory
,
5220 VkDeviceSize offset
,
5222 VkMemoryMapFlags flags
,
5225 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5226 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5234 *ppData
= mem
->user_ptr
;
5236 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5243 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5246 void radv_UnmapMemory(
5248 VkDeviceMemory _memory
)
5250 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5251 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5256 if (mem
->user_ptr
== NULL
)
5257 device
->ws
->buffer_unmap(mem
->bo
);
5260 VkResult
radv_FlushMappedMemoryRanges(
5262 uint32_t memoryRangeCount
,
5263 const VkMappedMemoryRange
* pMemoryRanges
)
5268 VkResult
radv_InvalidateMappedMemoryRanges(
5270 uint32_t memoryRangeCount
,
5271 const VkMappedMemoryRange
* pMemoryRanges
)
5276 void radv_GetBufferMemoryRequirements(
5279 VkMemoryRequirements
* pMemoryRequirements
)
5281 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5282 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5284 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5286 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5287 pMemoryRequirements
->alignment
= 4096;
5289 pMemoryRequirements
->alignment
= 16;
5291 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5294 void radv_GetBufferMemoryRequirements2(
5296 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5297 VkMemoryRequirements2
*pMemoryRequirements
)
5299 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5300 &pMemoryRequirements
->memoryRequirements
);
5301 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5302 switch (ext
->sType
) {
5303 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5304 VkMemoryDedicatedRequirements
*req
=
5305 (VkMemoryDedicatedRequirements
*) ext
;
5306 req
->requiresDedicatedAllocation
= false;
5307 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5316 void radv_GetImageMemoryRequirements(
5319 VkMemoryRequirements
* pMemoryRequirements
)
5321 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5322 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5324 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5326 pMemoryRequirements
->size
= image
->size
;
5327 pMemoryRequirements
->alignment
= image
->alignment
;
5330 void radv_GetImageMemoryRequirements2(
5332 const VkImageMemoryRequirementsInfo2
*pInfo
,
5333 VkMemoryRequirements2
*pMemoryRequirements
)
5335 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5336 &pMemoryRequirements
->memoryRequirements
);
5338 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5340 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5341 switch (ext
->sType
) {
5342 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5343 VkMemoryDedicatedRequirements
*req
=
5344 (VkMemoryDedicatedRequirements
*) ext
;
5345 req
->requiresDedicatedAllocation
= image
->shareable
&&
5346 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5347 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5356 void radv_GetImageSparseMemoryRequirements(
5359 uint32_t* pSparseMemoryRequirementCount
,
5360 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5365 void radv_GetImageSparseMemoryRequirements2(
5367 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5368 uint32_t* pSparseMemoryRequirementCount
,
5369 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5374 void radv_GetDeviceMemoryCommitment(
5376 VkDeviceMemory memory
,
5377 VkDeviceSize
* pCommittedMemoryInBytes
)
5379 *pCommittedMemoryInBytes
= 0;
5382 VkResult
radv_BindBufferMemory2(VkDevice device
,
5383 uint32_t bindInfoCount
,
5384 const VkBindBufferMemoryInfo
*pBindInfos
)
5386 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5387 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5388 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5391 buffer
->bo
= mem
->bo
;
5392 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5400 VkResult
radv_BindBufferMemory(
5403 VkDeviceMemory memory
,
5404 VkDeviceSize memoryOffset
)
5406 const VkBindBufferMemoryInfo info
= {
5407 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5410 .memoryOffset
= memoryOffset
5413 return radv_BindBufferMemory2(device
, 1, &info
);
5416 VkResult
radv_BindImageMemory2(VkDevice device
,
5417 uint32_t bindInfoCount
,
5418 const VkBindImageMemoryInfo
*pBindInfos
)
5420 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5421 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5422 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5425 image
->bo
= mem
->bo
;
5426 image
->offset
= pBindInfos
[i
].memoryOffset
;
5436 VkResult
radv_BindImageMemory(
5439 VkDeviceMemory memory
,
5440 VkDeviceSize memoryOffset
)
5442 const VkBindImageMemoryInfo info
= {
5443 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5446 .memoryOffset
= memoryOffset
5449 return radv_BindImageMemory2(device
, 1, &info
);
5452 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5454 return info
->bufferBindCount
||
5455 info
->imageOpaqueBindCount
||
5456 info
->imageBindCount
||
5457 info
->waitSemaphoreCount
||
5458 info
->signalSemaphoreCount
;
5461 VkResult
radv_QueueBindSparse(
5463 uint32_t bindInfoCount
,
5464 const VkBindSparseInfo
* pBindInfo
,
5467 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5469 uint32_t fence_idx
= 0;
5471 if (fence
!= VK_NULL_HANDLE
) {
5472 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5473 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5476 fence_idx
= UINT32_MAX
;
5478 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5479 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5482 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5483 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5485 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5486 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5487 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5488 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5489 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5490 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5491 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5492 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5493 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5494 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5495 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5496 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5497 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5498 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5501 if (result
!= VK_SUCCESS
)
5505 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5506 result
= radv_signal_fence(queue
, fence
);
5507 if (result
!= VK_SUCCESS
)
5514 VkResult
radv_CreateFence(
5516 const VkFenceCreateInfo
* pCreateInfo
,
5517 const VkAllocationCallbacks
* pAllocator
,
5520 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5521 const VkExportFenceCreateInfo
*export
=
5522 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5523 VkExternalFenceHandleTypeFlags handleTypes
=
5524 export
? export
->handleTypes
: 0;
5526 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5528 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5531 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5533 fence
->fence_wsi
= NULL
;
5534 fence
->temp_syncobj
= 0;
5535 if (device
->always_use_syncobj
|| handleTypes
) {
5536 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5538 vk_free2(&device
->alloc
, pAllocator
, fence
);
5539 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5541 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5542 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5544 fence
->fence
= NULL
;
5546 fence
->fence
= device
->ws
->create_fence();
5547 if (!fence
->fence
) {
5548 vk_free2(&device
->alloc
, pAllocator
, fence
);
5549 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5552 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5553 device
->ws
->signal_fence(fence
->fence
);
5556 *pFence
= radv_fence_to_handle(fence
);
5561 void radv_DestroyFence(
5564 const VkAllocationCallbacks
* pAllocator
)
5566 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5567 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5572 if (fence
->temp_syncobj
)
5573 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5575 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5577 device
->ws
->destroy_fence(fence
->fence
);
5578 if (fence
->fence_wsi
)
5579 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5580 vk_free2(&device
->alloc
, pAllocator
, fence
);
5584 uint64_t radv_get_current_time(void)
5587 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5588 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5591 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5593 uint64_t current_time
= radv_get_current_time();
5595 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5597 return current_time
+ timeout
;
5601 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5602 uint32_t fenceCount
, const VkFence
*pFences
)
5604 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5605 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5606 if (fence
->fence
== NULL
|| fence
->syncobj
||
5607 fence
->temp_syncobj
|| fence
->fence_wsi
||
5608 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5614 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5616 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5617 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5618 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5624 VkResult
radv_WaitForFences(
5626 uint32_t fenceCount
,
5627 const VkFence
* pFences
,
5631 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5632 timeout
= radv_get_absolute_timeout(timeout
);
5634 if (device
->always_use_syncobj
&&
5635 radv_all_fences_syncobj(fenceCount
, pFences
))
5637 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5639 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5641 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5642 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5643 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5646 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5649 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5652 if (!waitAll
&& fenceCount
> 1) {
5653 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5654 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5655 uint32_t wait_count
= 0;
5656 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5658 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5660 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5661 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5663 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5668 fences
[wait_count
++] = fence
->fence
;
5671 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5672 waitAll
, timeout
- radv_get_current_time());
5675 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5678 while(radv_get_current_time() <= timeout
) {
5679 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5680 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5687 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5688 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5689 bool expired
= false;
5691 if (fence
->temp_syncobj
) {
5692 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5697 if (fence
->syncobj
) {
5698 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5704 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5705 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5706 radv_get_current_time() <= timeout
)
5710 expired
= device
->ws
->fence_wait(device
->ws
,
5717 if (fence
->fence_wsi
) {
5718 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5719 if (result
!= VK_SUCCESS
)
5727 VkResult
radv_ResetFences(VkDevice _device
,
5728 uint32_t fenceCount
,
5729 const VkFence
*pFences
)
5731 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5733 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5734 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5736 device
->ws
->reset_fence(fence
->fence
);
5738 /* Per spec, we first restore the permanent payload, and then reset, so
5739 * having a temp syncobj should not skip resetting the permanent syncobj. */
5740 if (fence
->temp_syncobj
) {
5741 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5742 fence
->temp_syncobj
= 0;
5745 if (fence
->syncobj
) {
5746 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5753 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5755 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5756 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5758 if (fence
->temp_syncobj
) {
5759 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5760 return success
? VK_SUCCESS
: VK_NOT_READY
;
5763 if (fence
->syncobj
) {
5764 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5765 return success
? VK_SUCCESS
: VK_NOT_READY
;
5769 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5770 return VK_NOT_READY
;
5772 if (fence
->fence_wsi
) {
5773 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5775 if (result
!= VK_SUCCESS
) {
5776 if (result
== VK_TIMEOUT
)
5777 return VK_NOT_READY
;
5785 // Queue semaphore functions
5788 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5790 timeline
->highest_signaled
= value
;
5791 timeline
->highest_submitted
= value
;
5792 list_inithead(&timeline
->points
);
5793 list_inithead(&timeline
->free_points
);
5794 list_inithead(&timeline
->waiters
);
5795 pthread_mutex_init(&timeline
->mutex
, NULL
);
5799 radv_destroy_timeline(struct radv_device
*device
,
5800 struct radv_timeline
*timeline
)
5802 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5803 &timeline
->free_points
, list
) {
5804 list_del(&point
->list
);
5805 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5808 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5809 &timeline
->points
, list
) {
5810 list_del(&point
->list
);
5811 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5814 pthread_mutex_destroy(&timeline
->mutex
);
5818 radv_timeline_gc_locked(struct radv_device
*device
,
5819 struct radv_timeline
*timeline
)
5821 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5822 &timeline
->points
, list
) {
5823 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5826 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5827 timeline
->highest_signaled
= point
->value
;
5828 list_del(&point
->list
);
5829 list_add(&point
->list
, &timeline
->free_points
);
5834 static struct radv_timeline_point
*
5835 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5836 struct radv_timeline
*timeline
,
5839 radv_timeline_gc_locked(device
, timeline
);
5841 if (p
<= timeline
->highest_signaled
)
5844 list_for_each_entry(struct radv_timeline_point
, point
,
5845 &timeline
->points
, list
) {
5846 if (point
->value
>= p
) {
5847 ++point
->wait_count
;
5854 static struct radv_timeline_point
*
5855 radv_timeline_add_point_locked(struct radv_device
*device
,
5856 struct radv_timeline
*timeline
,
5859 radv_timeline_gc_locked(device
, timeline
);
5861 struct radv_timeline_point
*ret
= NULL
;
5862 struct radv_timeline_point
*prev
= NULL
;
5864 if (p
<= timeline
->highest_signaled
)
5867 list_for_each_entry(struct radv_timeline_point
, point
,
5868 &timeline
->points
, list
) {
5869 if (point
->value
== p
) {
5873 if (point
->value
< p
)
5877 if (list_is_empty(&timeline
->free_points
)) {
5878 ret
= malloc(sizeof(struct radv_timeline_point
));
5879 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5881 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5882 list_del(&ret
->list
);
5884 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5888 ret
->wait_count
= 1;
5891 list_add(&ret
->list
, &prev
->list
);
5893 list_addtail(&ret
->list
, &timeline
->points
);
5900 radv_timeline_wait_locked(struct radv_device
*device
,
5901 struct radv_timeline
*timeline
,
5903 uint64_t abs_timeout
)
5905 while(timeline
->highest_submitted
< value
) {
5906 struct timespec abstime
;
5907 timespec_from_nsec(&abstime
, abs_timeout
);
5909 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5911 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5915 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5919 pthread_mutex_unlock(&timeline
->mutex
);
5921 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5923 pthread_mutex_lock(&timeline
->mutex
);
5924 point
->wait_count
--;
5925 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5929 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5930 struct list_head
*processing_list
)
5932 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5933 &timeline
->waiters
, list
) {
5934 if (waiter
->value
> timeline
->highest_submitted
)
5937 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5938 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5940 list_del(&waiter
->list
);
5945 void radv_destroy_semaphore_part(struct radv_device
*device
,
5946 struct radv_semaphore_part
*part
)
5948 switch(part
->kind
) {
5949 case RADV_SEMAPHORE_NONE
:
5951 case RADV_SEMAPHORE_WINSYS
:
5952 device
->ws
->destroy_sem(part
->ws_sem
);
5954 case RADV_SEMAPHORE_TIMELINE
:
5955 radv_destroy_timeline(device
, &part
->timeline
);
5957 case RADV_SEMAPHORE_SYNCOBJ
:
5958 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5961 part
->kind
= RADV_SEMAPHORE_NONE
;
5964 static VkSemaphoreTypeKHR
5965 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5967 const VkSemaphoreTypeCreateInfo
*type_info
=
5968 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5971 return VK_SEMAPHORE_TYPE_BINARY
;
5974 *initial_value
= type_info
->initialValue
;
5975 return type_info
->semaphoreType
;
5978 VkResult
radv_CreateSemaphore(
5980 const VkSemaphoreCreateInfo
* pCreateInfo
,
5981 const VkAllocationCallbacks
* pAllocator
,
5982 VkSemaphore
* pSemaphore
)
5984 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5985 const VkExportSemaphoreCreateInfo
*export
=
5986 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5987 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5988 export
? export
->handleTypes
: 0;
5989 uint64_t initial_value
= 0;
5990 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5992 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5994 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5996 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5998 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5999 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
6001 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
6002 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
6003 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
6004 } else if (device
->always_use_syncobj
|| handleTypes
) {
6005 assert (device
->physical_device
->rad_info
.has_syncobj
);
6006 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
6008 vk_free2(&device
->alloc
, pAllocator
, sem
);
6009 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6011 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
6013 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
6014 if (!sem
->permanent
.ws_sem
) {
6015 vk_free2(&device
->alloc
, pAllocator
, sem
);
6016 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6018 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
6021 *pSemaphore
= radv_semaphore_to_handle(sem
);
6025 void radv_DestroySemaphore(
6027 VkSemaphore _semaphore
,
6028 const VkAllocationCallbacks
* pAllocator
)
6030 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6031 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
6035 radv_destroy_semaphore_part(device
, &sem
->temporary
);
6036 radv_destroy_semaphore_part(device
, &sem
->permanent
);
6037 vk_free2(&device
->alloc
, pAllocator
, sem
);
6041 radv_GetSemaphoreCounterValue(VkDevice _device
,
6042 VkSemaphore _semaphore
,
6045 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6046 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
6048 struct radv_semaphore_part
*part
=
6049 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6051 switch (part
->kind
) {
6052 case RADV_SEMAPHORE_TIMELINE
: {
6053 pthread_mutex_lock(&part
->timeline
.mutex
);
6054 radv_timeline_gc_locked(device
, &part
->timeline
);
6055 *pValue
= part
->timeline
.highest_signaled
;
6056 pthread_mutex_unlock(&part
->timeline
.mutex
);
6059 case RADV_SEMAPHORE_NONE
:
6060 case RADV_SEMAPHORE_SYNCOBJ
:
6061 case RADV_SEMAPHORE_WINSYS
:
6062 unreachable("Invalid semaphore type");
6064 unreachable("Unhandled semaphore type");
6069 radv_wait_timelines(struct radv_device
*device
,
6070 const VkSemaphoreWaitInfo
* pWaitInfo
,
6071 uint64_t abs_timeout
)
6073 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
6075 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6076 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6077 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6078 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
6079 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6081 if (result
== VK_SUCCESS
)
6084 if (radv_get_current_time() > abs_timeout
)
6089 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6090 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6091 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6092 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
6093 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6095 if (result
!= VK_SUCCESS
)
6101 radv_WaitSemaphores(VkDevice _device
,
6102 const VkSemaphoreWaitInfo
* pWaitInfo
,
6105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6106 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
6107 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
6111 radv_SignalSemaphore(VkDevice _device
,
6112 const VkSemaphoreSignalInfo
* pSignalInfo
)
6114 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6115 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6117 struct radv_semaphore_part
*part
=
6118 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6120 switch(part
->kind
) {
6121 case RADV_SEMAPHORE_TIMELINE
: {
6122 pthread_mutex_lock(&part
->timeline
.mutex
);
6123 radv_timeline_gc_locked(device
, &part
->timeline
);
6124 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6125 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6127 struct list_head processing_list
;
6128 list_inithead(&processing_list
);
6129 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6130 pthread_mutex_unlock(&part
->timeline
.mutex
);
6132 return radv_process_submissions(&processing_list
);
6134 case RADV_SEMAPHORE_NONE
:
6135 case RADV_SEMAPHORE_SYNCOBJ
:
6136 case RADV_SEMAPHORE_WINSYS
:
6137 unreachable("Invalid semaphore type");
6144 VkResult
radv_CreateEvent(
6146 const VkEventCreateInfo
* pCreateInfo
,
6147 const VkAllocationCallbacks
* pAllocator
,
6150 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6151 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6153 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6156 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6158 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6160 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6161 RADV_BO_PRIORITY_FENCE
);
6163 vk_free2(&device
->alloc
, pAllocator
, event
);
6164 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6167 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6169 *pEvent
= radv_event_to_handle(event
);
6174 void radv_DestroyEvent(
6177 const VkAllocationCallbacks
* pAllocator
)
6179 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6180 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6184 device
->ws
->buffer_destroy(event
->bo
);
6185 vk_free2(&device
->alloc
, pAllocator
, event
);
6188 VkResult
radv_GetEventStatus(
6192 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6194 if (*event
->map
== 1)
6195 return VK_EVENT_SET
;
6196 return VK_EVENT_RESET
;
6199 VkResult
radv_SetEvent(
6203 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6209 VkResult
radv_ResetEvent(
6213 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6219 VkResult
radv_CreateBuffer(
6221 const VkBufferCreateInfo
* pCreateInfo
,
6222 const VkAllocationCallbacks
* pAllocator
,
6225 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6226 struct radv_buffer
*buffer
;
6228 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6230 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6231 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6233 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6235 buffer
->size
= pCreateInfo
->size
;
6236 buffer
->usage
= pCreateInfo
->usage
;
6239 buffer
->flags
= pCreateInfo
->flags
;
6241 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6242 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6244 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6245 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6246 align64(buffer
->size
, 4096),
6247 4096, 0, RADEON_FLAG_VIRTUAL
,
6248 RADV_BO_PRIORITY_VIRTUAL
);
6250 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6251 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6255 *pBuffer
= radv_buffer_to_handle(buffer
);
6260 void radv_DestroyBuffer(
6263 const VkAllocationCallbacks
* pAllocator
)
6265 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6266 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6271 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6272 device
->ws
->buffer_destroy(buffer
->bo
);
6274 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6277 VkDeviceAddress
radv_GetBufferDeviceAddress(
6279 const VkBufferDeviceAddressInfo
* pInfo
)
6281 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6282 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6286 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6287 const VkBufferDeviceAddressInfo
* pInfo
)
6292 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6293 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6298 static inline unsigned
6299 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6302 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6304 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6307 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6309 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6313 radv_init_dcc_control_reg(struct radv_device
*device
,
6314 struct radv_image_view
*iview
)
6316 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6317 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6318 unsigned max_compressed_block_size
;
6319 unsigned independent_128b_blocks
;
6320 unsigned independent_64b_blocks
;
6322 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6325 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6326 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6327 * dGPU and 64 for APU because all of our APUs to date use
6328 * DIMMs which have a request granularity size of 64B while all
6329 * other chips have a 32B request size.
6331 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6334 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6335 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6336 independent_64b_blocks
= 0;
6337 independent_128b_blocks
= 1;
6339 independent_128b_blocks
= 0;
6341 if (iview
->image
->info
.samples
> 1) {
6342 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6343 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6344 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6345 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6348 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6349 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6350 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6351 /* If this DCC image is potentially going to be used in texture
6352 * fetches, we need some special settings.
6354 independent_64b_blocks
= 1;
6355 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6357 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6358 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6359 * big as possible for better compression state.
6361 independent_64b_blocks
= 0;
6362 max_compressed_block_size
= max_uncompressed_block_size
;
6366 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6367 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6368 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6369 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6370 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6374 radv_initialise_color_surface(struct radv_device
*device
,
6375 struct radv_color_buffer_info
*cb
,
6376 struct radv_image_view
*iview
)
6378 const struct vk_format_description
*desc
;
6379 unsigned ntype
, format
, swap
, endian
;
6380 unsigned blend_clamp
= 0, blend_bypass
= 0;
6382 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6383 const struct radeon_surf
*surf
= &plane
->surface
;
6385 desc
= vk_format_description(iview
->vk_format
);
6387 memset(cb
, 0, sizeof(*cb
));
6389 /* Intensity is implemented as Red, so treat it that way. */
6390 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6392 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6394 cb
->cb_color_base
= va
>> 8;
6396 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6397 struct gfx9_surf_meta_flags meta
;
6398 if (iview
->image
->dcc_offset
)
6399 meta
= surf
->u
.gfx9
.dcc
;
6401 meta
= surf
->u
.gfx9
.cmask
;
6403 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6404 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6405 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6406 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6407 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6409 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6410 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6411 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6412 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6413 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6416 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6417 cb
->cb_color_base
|= surf
->tile_swizzle
;
6419 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6420 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6422 cb
->cb_color_base
+= level_info
->offset
>> 8;
6423 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6424 cb
->cb_color_base
|= surf
->tile_swizzle
;
6426 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6427 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6428 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6430 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6431 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6432 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6434 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6436 if (radv_image_has_fmask(iview
->image
)) {
6437 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6438 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6439 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6440 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6442 /* This must be set for fast clear to work without FMASK. */
6443 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6444 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6445 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6446 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6450 /* CMASK variables */
6451 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6452 va
+= iview
->image
->cmask_offset
;
6453 cb
->cb_color_cmask
= va
>> 8;
6455 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6456 va
+= iview
->image
->dcc_offset
;
6458 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6459 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6460 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6462 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6463 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6465 cb
->cb_dcc_base
= va
>> 8;
6466 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6468 /* GFX10 field has the same base shift as the GFX6 field. */
6469 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6470 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6471 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6473 if (iview
->image
->info
.samples
> 1) {
6474 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6476 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6477 S_028C74_NUM_FRAGMENTS(log_samples
);
6480 if (radv_image_has_fmask(iview
->image
)) {
6481 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6482 cb
->cb_color_fmask
= va
>> 8;
6483 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6485 cb
->cb_color_fmask
= cb
->cb_color_base
;
6488 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6490 vk_format_get_first_non_void_channel(iview
->vk_format
));
6491 format
= radv_translate_colorformat(iview
->vk_format
);
6492 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6493 radv_finishme("Illegal color\n");
6494 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6495 endian
= radv_colorformat_endian_swap(format
);
6497 /* blend clamp should be set for all NORM/SRGB types */
6498 if (ntype
== V_028C70_NUMBER_UNORM
||
6499 ntype
== V_028C70_NUMBER_SNORM
||
6500 ntype
== V_028C70_NUMBER_SRGB
)
6503 /* set blend bypass according to docs if SINT/UINT or
6504 8/24 COLOR variants */
6505 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6506 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6507 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6512 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6513 (format
== V_028C70_COLOR_8
||
6514 format
== V_028C70_COLOR_8_8
||
6515 format
== V_028C70_COLOR_8_8_8_8
))
6516 ->color_is_int8
= true;
6518 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6519 S_028C70_COMP_SWAP(swap
) |
6520 S_028C70_BLEND_CLAMP(blend_clamp
) |
6521 S_028C70_BLEND_BYPASS(blend_bypass
) |
6522 S_028C70_SIMPLE_FLOAT(1) |
6523 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6524 ntype
!= V_028C70_NUMBER_SNORM
&&
6525 ntype
!= V_028C70_NUMBER_SRGB
&&
6526 format
!= V_028C70_COLOR_8_24
&&
6527 format
!= V_028C70_COLOR_24_8
) |
6528 S_028C70_NUMBER_TYPE(ntype
) |
6529 S_028C70_ENDIAN(endian
);
6530 if (radv_image_has_fmask(iview
->image
)) {
6531 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6532 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6533 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6534 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6537 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6538 /* Allow the texture block to read FMASK directly
6539 * without decompressing it. This bit must be cleared
6540 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6541 * otherwise the operation doesn't happen.
6543 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6545 /* Set CMASK into a tiling format that allows the
6546 * texture block to read it.
6548 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6552 if (radv_image_has_cmask(iview
->image
) &&
6553 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6554 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6556 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6557 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6559 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6561 /* This must be set for fast clear to work without FMASK. */
6562 if (!radv_image_has_fmask(iview
->image
) &&
6563 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6564 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6565 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6568 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6569 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6571 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6572 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6573 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6574 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6576 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6577 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6579 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6580 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6581 S_028EE0_RESOURCE_LEVEL(1);
6583 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6584 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6585 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6588 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6589 S_028C68_MIP0_HEIGHT(height
- 1) |
6590 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6595 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6596 struct radv_image_view
*iview
)
6598 unsigned max_zplanes
= 0;
6600 assert(radv_image_is_tc_compat_htile(iview
->image
));
6602 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6603 /* Default value for 32-bit depth surfaces. */
6606 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6607 iview
->image
->info
.samples
> 1)
6610 max_zplanes
= max_zplanes
+ 1;
6612 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6613 /* Do not enable Z plane compression for 16-bit depth
6614 * surfaces because isn't supported on GFX8. Only
6615 * 32-bit depth surfaces are supported by the hardware.
6616 * This allows to maintain shader compatibility and to
6617 * reduce the number of depth decompressions.
6621 if (iview
->image
->info
.samples
<= 1)
6623 else if (iview
->image
->info
.samples
<= 4)
6634 radv_initialise_ds_surface(struct radv_device
*device
,
6635 struct radv_ds_buffer_info
*ds
,
6636 struct radv_image_view
*iview
)
6638 unsigned level
= iview
->base_mip
;
6639 unsigned format
, stencil_format
;
6640 uint64_t va
, s_offs
, z_offs
;
6641 bool stencil_only
= false;
6642 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6643 const struct radeon_surf
*surf
= &plane
->surface
;
6645 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6647 memset(ds
, 0, sizeof(*ds
));
6648 switch (iview
->image
->vk_format
) {
6649 case VK_FORMAT_D24_UNORM_S8_UINT
:
6650 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6651 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6652 ds
->offset_scale
= 2.0f
;
6654 case VK_FORMAT_D16_UNORM
:
6655 case VK_FORMAT_D16_UNORM_S8_UINT
:
6656 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6657 ds
->offset_scale
= 4.0f
;
6659 case VK_FORMAT_D32_SFLOAT
:
6660 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6661 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6662 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6663 ds
->offset_scale
= 1.0f
;
6665 case VK_FORMAT_S8_UINT
:
6666 stencil_only
= true;
6672 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6673 stencil_format
= surf
->has_stencil
?
6674 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6676 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6677 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6678 S_028008_SLICE_MAX(max_slice
);
6679 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6680 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6681 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6684 ds
->db_htile_data_base
= 0;
6685 ds
->db_htile_surface
= 0;
6687 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6688 s_offs
= z_offs
= va
;
6690 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6691 assert(surf
->u
.gfx9
.surf_offset
== 0);
6692 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6694 ds
->db_z_info
= S_028038_FORMAT(format
) |
6695 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6696 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6697 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6698 S_028038_ZRANGE_PRECISION(1);
6699 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6700 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6702 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6703 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6704 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6707 ds
->db_depth_view
|= S_028008_MIPID(level
);
6708 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6709 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6711 if (radv_htile_enabled(iview
->image
, level
)) {
6712 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6714 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6715 unsigned max_zplanes
=
6716 radv_calc_decompress_on_z_planes(device
, iview
);
6718 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6720 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6721 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6722 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6724 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6725 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6729 if (!surf
->has_stencil
)
6730 /* Use all of the htile_buffer for depth if there's no stencil. */
6731 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6732 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6733 iview
->image
->htile_offset
;
6734 ds
->db_htile_data_base
= va
>> 8;
6735 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6736 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6738 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6739 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6743 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6746 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6748 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6749 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6751 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6752 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6753 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6755 if (iview
->image
->info
.samples
> 1)
6756 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6758 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6759 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6760 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6761 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6762 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6763 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6764 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6765 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6768 tile_mode
= stencil_tile_mode
;
6770 ds
->db_depth_info
|=
6771 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6772 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6773 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6774 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6775 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6776 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6777 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6778 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6780 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6781 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6782 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6783 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6785 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6788 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6789 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6790 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6792 if (radv_htile_enabled(iview
->image
, level
)) {
6793 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6795 if (!surf
->has_stencil
&&
6796 !radv_image_is_tc_compat_htile(iview
->image
))
6797 /* Use all of the htile_buffer for depth if there's no stencil. */
6798 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6800 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6801 iview
->image
->htile_offset
;
6802 ds
->db_htile_data_base
= va
>> 8;
6803 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6805 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6806 unsigned max_zplanes
=
6807 radv_calc_decompress_on_z_planes(device
, iview
);
6809 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6810 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6815 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6816 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6819 VkResult
radv_CreateFramebuffer(
6821 const VkFramebufferCreateInfo
* pCreateInfo
,
6822 const VkAllocationCallbacks
* pAllocator
,
6823 VkFramebuffer
* pFramebuffer
)
6825 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6826 struct radv_framebuffer
*framebuffer
;
6827 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6828 vk_find_struct_const(pCreateInfo
->pNext
,
6829 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6831 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6833 size_t size
= sizeof(*framebuffer
);
6834 if (!imageless_create_info
)
6835 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6836 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6837 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6838 if (framebuffer
== NULL
)
6839 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6841 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6842 framebuffer
->width
= pCreateInfo
->width
;
6843 framebuffer
->height
= pCreateInfo
->height
;
6844 framebuffer
->layers
= pCreateInfo
->layers
;
6845 if (imageless_create_info
) {
6846 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6847 const VkFramebufferAttachmentImageInfo
*attachment
=
6848 imageless_create_info
->pAttachmentImageInfos
+ i
;
6849 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6850 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6851 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6854 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6855 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6856 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6857 framebuffer
->attachments
[i
] = iview
;
6858 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6859 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6860 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6864 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6868 void radv_DestroyFramebuffer(
6871 const VkAllocationCallbacks
* pAllocator
)
6873 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6874 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6878 vk_free2(&device
->alloc
, pAllocator
, fb
);
6881 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6883 switch (address_mode
) {
6884 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6885 return V_008F30_SQ_TEX_WRAP
;
6886 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6887 return V_008F30_SQ_TEX_MIRROR
;
6888 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6889 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6890 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6891 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6892 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6893 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6895 unreachable("illegal tex wrap mode");
6901 radv_tex_compare(VkCompareOp op
)
6904 case VK_COMPARE_OP_NEVER
:
6905 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6906 case VK_COMPARE_OP_LESS
:
6907 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6908 case VK_COMPARE_OP_EQUAL
:
6909 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6910 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6911 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6912 case VK_COMPARE_OP_GREATER
:
6913 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6914 case VK_COMPARE_OP_NOT_EQUAL
:
6915 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6916 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6917 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6918 case VK_COMPARE_OP_ALWAYS
:
6919 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6921 unreachable("illegal compare mode");
6927 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6930 case VK_FILTER_NEAREST
:
6931 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6932 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6933 case VK_FILTER_LINEAR
:
6934 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6935 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6936 case VK_FILTER_CUBIC_IMG
:
6938 fprintf(stderr
, "illegal texture filter");
6944 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6947 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6948 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6949 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6950 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6952 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6957 radv_tex_bordercolor(VkBorderColor bcolor
)
6960 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6961 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6962 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6963 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6964 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6965 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6966 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6967 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6968 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6976 radv_tex_aniso_filter(unsigned filter
)
6990 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6993 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6994 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6995 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6996 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6997 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6998 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
7006 radv_get_max_anisotropy(struct radv_device
*device
,
7007 const VkSamplerCreateInfo
*pCreateInfo
)
7009 if (device
->force_aniso
>= 0)
7010 return device
->force_aniso
;
7012 if (pCreateInfo
->anisotropyEnable
&&
7013 pCreateInfo
->maxAnisotropy
> 1.0f
)
7014 return (uint32_t)pCreateInfo
->maxAnisotropy
;
7020 radv_init_sampler(struct radv_device
*device
,
7021 struct radv_sampler
*sampler
,
7022 const VkSamplerCreateInfo
*pCreateInfo
)
7024 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
7025 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
7026 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
7027 device
->physical_device
->rad_info
.chip_class
== GFX9
;
7028 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7029 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7031 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
7032 vk_find_struct_const(pCreateInfo
->pNext
,
7033 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
7034 if (sampler_reduction
)
7035 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
7037 if (pCreateInfo
->compareEnable
)
7038 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
7040 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
7041 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
7042 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
7043 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
7044 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
7045 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
7046 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
7047 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
7048 S_008F30_DISABLE_CUBE_WRAP(0) |
7049 S_008F30_COMPAT_MODE(compat_mode
) |
7050 S_008F30_FILTER_MODE(filter_mode
));
7051 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
7052 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
7053 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
7054 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
7055 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
7056 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
7057 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
7058 S_008F38_MIP_POINT_PRECLAMP(0));
7059 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
7060 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
7062 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
7063 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7065 sampler
->state
[2] |=
7066 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
7067 S_008F38_FILTER_PREC_FIX(1) |
7068 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
7072 VkResult
radv_CreateSampler(
7074 const VkSamplerCreateInfo
* pCreateInfo
,
7075 const VkAllocationCallbacks
* pAllocator
,
7076 VkSampler
* pSampler
)
7078 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7079 struct radv_sampler
*sampler
;
7081 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7082 vk_find_struct_const(pCreateInfo
->pNext
,
7083 SAMPLER_YCBCR_CONVERSION_INFO
);
7085 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7087 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
7088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7090 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7092 radv_init_sampler(device
, sampler
, pCreateInfo
);
7094 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7095 *pSampler
= radv_sampler_to_handle(sampler
);
7100 void radv_DestroySampler(
7103 const VkAllocationCallbacks
* pAllocator
)
7105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7106 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7110 vk_free2(&device
->alloc
, pAllocator
, sampler
);
7113 /* vk_icd.h does not declare this function, so we declare it here to
7114 * suppress Wmissing-prototypes.
7116 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7117 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7119 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7120 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7122 /* For the full details on loader interface versioning, see
7123 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7124 * What follows is a condensed summary, to help you navigate the large and
7125 * confusing official doc.
7127 * - Loader interface v0 is incompatible with later versions. We don't
7130 * - In loader interface v1:
7131 * - The first ICD entrypoint called by the loader is
7132 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7134 * - The ICD must statically expose no other Vulkan symbol unless it is
7135 * linked with -Bsymbolic.
7136 * - Each dispatchable Vulkan handle created by the ICD must be
7137 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7138 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7139 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7140 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7141 * such loader-managed surfaces.
7143 * - Loader interface v2 differs from v1 in:
7144 * - The first ICD entrypoint called by the loader is
7145 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7146 * statically expose this entrypoint.
7148 * - Loader interface v3 differs from v2 in:
7149 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7150 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7151 * because the loader no longer does so.
7153 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7157 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7158 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7162 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7164 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7166 /* At the moment, we support only the below handle types. */
7167 assert(pGetFdInfo
->handleType
==
7168 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7169 pGetFdInfo
->handleType
==
7170 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7172 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7174 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7178 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7179 VkExternalMemoryHandleTypeFlagBits handleType
,
7181 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7183 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7185 switch (handleType
) {
7186 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7187 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7191 /* The valid usage section for this function says:
7193 * "handleType must not be one of the handle types defined as
7196 * So opaque handle types fall into the default "unsupported" case.
7198 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7202 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7206 uint32_t syncobj_handle
= 0;
7207 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7209 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7212 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7214 *syncobj
= syncobj_handle
;
7220 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7224 /* If we create a syncobj we do it locally so that if we have an error, we don't
7225 * leave a syncobj in an undetermined state in the fence. */
7226 uint32_t syncobj_handle
= *syncobj
;
7227 if (!syncobj_handle
) {
7228 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7230 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7235 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7237 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7239 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7242 *syncobj
= syncobj_handle
;
7249 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7250 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7252 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7253 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7255 struct radv_semaphore_part
*dst
= NULL
;
7257 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7258 dst
= &sem
->temporary
;
7260 dst
= &sem
->permanent
;
7263 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7265 switch(pImportSemaphoreFdInfo
->handleType
) {
7266 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7267 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7269 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7270 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7273 unreachable("Unhandled semaphore handle type");
7276 if (result
== VK_SUCCESS
) {
7277 dst
->syncobj
= syncobj
;
7278 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7284 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7285 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7288 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7289 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7291 uint32_t syncobj_handle
;
7293 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7294 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7295 syncobj_handle
= sem
->temporary
.syncobj
;
7297 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7298 syncobj_handle
= sem
->permanent
.syncobj
;
7301 switch(pGetFdInfo
->handleType
) {
7302 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7303 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7305 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7306 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7308 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7309 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7311 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7316 unreachable("Unhandled semaphore handle type");
7320 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7324 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7325 VkPhysicalDevice physicalDevice
,
7326 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7327 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7329 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7330 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7332 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7333 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7334 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7335 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7337 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7338 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7339 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7340 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7341 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7342 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7343 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7344 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7345 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7346 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7347 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7348 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7349 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7351 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7352 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7353 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7357 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7358 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7360 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7361 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7362 uint32_t *syncobj_dst
= NULL
;
7365 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7366 syncobj_dst
= &fence
->temp_syncobj
;
7368 syncobj_dst
= &fence
->syncobj
;
7371 switch(pImportFenceFdInfo
->handleType
) {
7372 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7373 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7374 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7375 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7377 unreachable("Unhandled fence handle type");
7381 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7382 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7385 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7386 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7388 uint32_t syncobj_handle
;
7390 if (fence
->temp_syncobj
)
7391 syncobj_handle
= fence
->temp_syncobj
;
7393 syncobj_handle
= fence
->syncobj
;
7395 switch(pGetFdInfo
->handleType
) {
7396 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7397 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7399 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7400 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7402 if (fence
->temp_syncobj
) {
7403 close (fence
->temp_syncobj
);
7404 fence
->temp_syncobj
= 0;
7406 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7411 unreachable("Unhandled fence handle type");
7415 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7419 void radv_GetPhysicalDeviceExternalFenceProperties(
7420 VkPhysicalDevice physicalDevice
,
7421 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7422 VkExternalFenceProperties
*pExternalFenceProperties
)
7424 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7426 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7427 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7428 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7429 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7430 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7431 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7432 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7434 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7435 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7436 pExternalFenceProperties
->externalFenceFeatures
= 0;
7441 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7442 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7443 const VkAllocationCallbacks
* pAllocator
,
7444 VkDebugReportCallbackEXT
* pCallback
)
7446 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7447 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7448 pCreateInfo
, pAllocator
, &instance
->alloc
,
7453 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7454 VkDebugReportCallbackEXT _callback
,
7455 const VkAllocationCallbacks
* pAllocator
)
7457 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7458 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7459 _callback
, pAllocator
, &instance
->alloc
);
7463 radv_DebugReportMessageEXT(VkInstance _instance
,
7464 VkDebugReportFlagsEXT flags
,
7465 VkDebugReportObjectTypeEXT objectType
,
7468 int32_t messageCode
,
7469 const char* pLayerPrefix
,
7470 const char* pMessage
)
7472 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7473 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7474 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7478 radv_GetDeviceGroupPeerMemoryFeatures(
7481 uint32_t localDeviceIndex
,
7482 uint32_t remoteDeviceIndex
,
7483 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7485 assert(localDeviceIndex
== remoteDeviceIndex
);
7487 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7488 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7489 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7490 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7493 static const VkTimeDomainEXT radv_time_domains
[] = {
7494 VK_TIME_DOMAIN_DEVICE_EXT
,
7495 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7496 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7499 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7500 VkPhysicalDevice physicalDevice
,
7501 uint32_t *pTimeDomainCount
,
7502 VkTimeDomainEXT
*pTimeDomains
)
7505 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7507 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7508 vk_outarray_append(&out
, i
) {
7509 *i
= radv_time_domains
[d
];
7513 return vk_outarray_status(&out
);
7517 radv_clock_gettime(clockid_t clock_id
)
7519 struct timespec current
;
7522 ret
= clock_gettime(clock_id
, ¤t
);
7523 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7524 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7528 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7531 VkResult
radv_GetCalibratedTimestampsEXT(
7533 uint32_t timestampCount
,
7534 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7535 uint64_t *pTimestamps
,
7536 uint64_t *pMaxDeviation
)
7538 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7539 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7541 uint64_t begin
, end
;
7542 uint64_t max_clock_period
= 0;
7544 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7546 for (d
= 0; d
< timestampCount
; d
++) {
7547 switch (pTimestampInfos
[d
].timeDomain
) {
7548 case VK_TIME_DOMAIN_DEVICE_EXT
:
7549 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7551 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7552 max_clock_period
= MAX2(max_clock_period
, device_period
);
7554 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7555 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7556 max_clock_period
= MAX2(max_clock_period
, 1);
7559 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7560 pTimestamps
[d
] = begin
;
7568 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7571 * The maximum deviation is the sum of the interval over which we
7572 * perform the sampling and the maximum period of any sampled
7573 * clock. That's because the maximum skew between any two sampled
7574 * clock edges is when the sampled clock with the largest period is
7575 * sampled at the end of that period but right at the beginning of the
7576 * sampling interval and some other clock is sampled right at the
7577 * begining of its sampling period and right at the end of the
7578 * sampling interval. Let's assume the GPU has the longest clock
7579 * period and that the application is sampling GPU and monotonic:
7582 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7583 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7587 * GPU -----_____-----_____-----_____-----_____
7590 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7591 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7593 * Interval <----------------->
7594 * Deviation <-------------------------->
7598 * m = read(monotonic) 2
7601 * We round the sample interval up by one tick to cover sampling error
7602 * in the interval clock
7605 uint64_t sample_interval
= end
- begin
+ 1;
7607 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7612 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7613 VkPhysicalDevice physicalDevice
,
7614 VkSampleCountFlagBits samples
,
7615 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7617 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7618 VK_SAMPLE_COUNT_4_BIT
|
7619 VK_SAMPLE_COUNT_8_BIT
)) {
7620 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7622 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };