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radv: Enable VK_KHR_incremental_present.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 {
88 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
89 .specVersion = 1,
90 },
91 };
92
93 static const VkExtensionProperties common_device_extensions[] = {
94 {
95 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
100 .specVersion = 1,
101 },
102 {
103 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
108 .specVersion = 68,
109 },
110 {
111 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
116 .specVersion = 1,
117 },
118 {
119 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
120 .specVersion = 1,
121 },
122 };
123
124 static VkResult
125 radv_extensions_register(struct radv_instance *instance,
126 struct radv_extensions *extensions,
127 const VkExtensionProperties *new_ext,
128 uint32_t num_ext)
129 {
130 size_t new_size;
131 VkExtensionProperties *new_ptr;
132
133 assert(new_ext && num_ext > 0);
134
135 if (!new_ext)
136 return VK_ERROR_INITIALIZATION_FAILED;
137
138 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
139 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
140 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
141
142 /* Old array continues to be valid, update nothing */
143 if (!new_ptr)
144 return VK_ERROR_OUT_OF_HOST_MEMORY;
145
146 memcpy(&new_ptr[extensions->num_ext], new_ext,
147 num_ext * sizeof(VkExtensionProperties));
148 extensions->ext_array = new_ptr;
149 extensions->num_ext += num_ext;
150
151 return VK_SUCCESS;
152 }
153
154 static void
155 radv_extensions_finish(struct radv_instance *instance,
156 struct radv_extensions *extensions)
157 {
158 assert(extensions);
159
160 if (!extensions)
161 radv_loge("Attemted to free invalid extension struct\n");
162
163 if (extensions->ext_array)
164 vk_free(&instance->alloc, extensions->ext_array);
165 }
166
167 static bool
168 is_extension_enabled(const VkExtensionProperties *extensions,
169 size_t num_ext,
170 const char *name)
171 {
172 assert(extensions && name);
173
174 for (uint32_t i = 0; i < num_ext; i++) {
175 if (strcmp(name, extensions[i].extensionName) == 0)
176 return true;
177 }
178
179 return false;
180 }
181
182 static VkResult
183 radv_physical_device_init(struct radv_physical_device *device,
184 struct radv_instance *instance,
185 const char *path)
186 {
187 VkResult result;
188 drmVersionPtr version;
189 int fd;
190
191 fd = open(path, O_RDWR | O_CLOEXEC);
192 if (fd < 0)
193 return VK_ERROR_INCOMPATIBLE_DRIVER;
194
195 version = drmGetVersion(fd);
196 if (!version) {
197 close(fd);
198 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
199 "failed to get version %s: %m", path);
200 }
201
202 if (strcmp(version->name, "amdgpu")) {
203 drmFreeVersion(version);
204 close(fd);
205 return VK_ERROR_INCOMPATIBLE_DRIVER;
206 }
207 drmFreeVersion(version);
208
209 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
210 device->instance = instance;
211 assert(strlen(path) < ARRAY_SIZE(device->path));
212 strncpy(device->path, path, ARRAY_SIZE(device->path));
213
214 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
215 if (!device->ws) {
216 result = VK_ERROR_INCOMPATIBLE_DRIVER;
217 goto fail;
218 }
219
220 device->local_fd = fd;
221 device->ws->query_info(device->ws, &device->rad_info);
222 result = radv_init_wsi(device);
223 if (result != VK_SUCCESS) {
224 device->ws->destroy(device->ws);
225 goto fail;
226 }
227
228 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
229 radv_finish_wsi(device);
230 device->ws->destroy(device->ws);
231 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
232 "cannot generate UUID");
233 goto fail;
234 }
235
236 result = radv_extensions_register(instance,
237 &device->extensions,
238 common_device_extensions,
239 ARRAY_SIZE(common_device_extensions));
240 if (result != VK_SUCCESS)
241 goto fail;
242
243 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
244 device->name = device->rad_info.name;
245
246 return VK_SUCCESS;
247
248 fail:
249 close(fd);
250 return result;
251 }
252
253 static void
254 radv_physical_device_finish(struct radv_physical_device *device)
255 {
256 radv_extensions_finish(device->instance, &device->extensions);
257 radv_finish_wsi(device);
258 device->ws->destroy(device->ws);
259 close(device->local_fd);
260 }
261
262
263 static void *
264 default_alloc_func(void *pUserData, size_t size, size_t align,
265 VkSystemAllocationScope allocationScope)
266 {
267 return malloc(size);
268 }
269
270 static void *
271 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
272 size_t align, VkSystemAllocationScope allocationScope)
273 {
274 return realloc(pOriginal, size);
275 }
276
277 static void
278 default_free_func(void *pUserData, void *pMemory)
279 {
280 free(pMemory);
281 }
282
283 static const VkAllocationCallbacks default_alloc = {
284 .pUserData = NULL,
285 .pfnAllocation = default_alloc_func,
286 .pfnReallocation = default_realloc_func,
287 .pfnFree = default_free_func,
288 };
289
290 static const struct debug_control radv_debug_options[] = {
291 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
292 {"nodcc", RADV_DEBUG_NO_DCC},
293 {"shaders", RADV_DEBUG_DUMP_SHADERS},
294 {"nocache", RADV_DEBUG_NO_CACHE},
295 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
296 {"nohiz", RADV_DEBUG_NO_HIZ},
297 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
298 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
299 {"allbos", RADV_DEBUG_ALL_BOS},
300 {"noibs", RADV_DEBUG_NO_IBS},
301 {NULL, 0}
302 };
303
304 VkResult radv_CreateInstance(
305 const VkInstanceCreateInfo* pCreateInfo,
306 const VkAllocationCallbacks* pAllocator,
307 VkInstance* pInstance)
308 {
309 struct radv_instance *instance;
310
311 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
312
313 uint32_t client_version;
314 if (pCreateInfo->pApplicationInfo &&
315 pCreateInfo->pApplicationInfo->apiVersion != 0) {
316 client_version = pCreateInfo->pApplicationInfo->apiVersion;
317 } else {
318 client_version = VK_MAKE_VERSION(1, 0, 0);
319 }
320
321 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
322 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
323 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
324 "Client requested version %d.%d.%d",
325 VK_VERSION_MAJOR(client_version),
326 VK_VERSION_MINOR(client_version),
327 VK_VERSION_PATCH(client_version));
328 }
329
330 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
331 if (!is_extension_enabled(instance_extensions,
332 ARRAY_SIZE(instance_extensions),
333 pCreateInfo->ppEnabledExtensionNames[i]))
334 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
335 }
336
337 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
338 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
339 if (!instance)
340 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
341
342 memset(instance, 0, sizeof(*instance));
343
344 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
345
346 if (pAllocator)
347 instance->alloc = *pAllocator;
348 else
349 instance->alloc = default_alloc;
350
351 instance->apiVersion = client_version;
352 instance->physicalDeviceCount = -1;
353
354 _mesa_locale_init();
355
356 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
357
358 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
359 radv_debug_options);
360
361 *pInstance = radv_instance_to_handle(instance);
362
363 return VK_SUCCESS;
364 }
365
366 void radv_DestroyInstance(
367 VkInstance _instance,
368 const VkAllocationCallbacks* pAllocator)
369 {
370 RADV_FROM_HANDLE(radv_instance, instance, _instance);
371
372 if (!instance)
373 return;
374
375 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
376 radv_physical_device_finish(instance->physicalDevices + i);
377 }
378
379 VG(VALGRIND_DESTROY_MEMPOOL(instance));
380
381 _mesa_locale_fini();
382
383 vk_free(&instance->alloc, instance);
384 }
385
386 static VkResult
387 radv_enumerate_devices(struct radv_instance *instance)
388 {
389 /* TODO: Check for more devices ? */
390 drmDevicePtr devices[8];
391 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
392 int max_devices;
393
394 instance->physicalDeviceCount = 0;
395
396 max_devices = drmGetDevices2(0, devices, sizeof(devices));
397 if (max_devices < 1)
398 return VK_ERROR_INCOMPATIBLE_DRIVER;
399
400 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
401 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
402 devices[i]->bustype == DRM_BUS_PCI &&
403 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
404
405 result = radv_physical_device_init(instance->physicalDevices +
406 instance->physicalDeviceCount,
407 instance,
408 devices[i]->nodes[DRM_NODE_RENDER]);
409 if (result == VK_SUCCESS)
410 ++instance->physicalDeviceCount;
411 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
412 return result;
413 }
414 }
415 return result;
416 }
417
418 VkResult radv_EnumeratePhysicalDevices(
419 VkInstance _instance,
420 uint32_t* pPhysicalDeviceCount,
421 VkPhysicalDevice* pPhysicalDevices)
422 {
423 RADV_FROM_HANDLE(radv_instance, instance, _instance);
424 VkResult result;
425
426 if (instance->physicalDeviceCount < 0) {
427 result = radv_enumerate_devices(instance);
428 if (result != VK_SUCCESS &&
429 result != VK_ERROR_INCOMPATIBLE_DRIVER)
430 return result;
431 }
432
433 if (!pPhysicalDevices) {
434 *pPhysicalDeviceCount = instance->physicalDeviceCount;
435 } else {
436 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
437 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
438 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
439 }
440
441 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
442 : VK_SUCCESS;
443 }
444
445 void radv_GetPhysicalDeviceFeatures(
446 VkPhysicalDevice physicalDevice,
447 VkPhysicalDeviceFeatures* pFeatures)
448 {
449 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
450
451 memset(pFeatures, 0, sizeof(*pFeatures));
452
453 *pFeatures = (VkPhysicalDeviceFeatures) {
454 .robustBufferAccess = true,
455 .fullDrawIndexUint32 = true,
456 .imageCubeArray = true,
457 .independentBlend = true,
458 .geometryShader = true,
459 .tessellationShader = true,
460 .sampleRateShading = false,
461 .dualSrcBlend = true,
462 .logicOp = true,
463 .multiDrawIndirect = true,
464 .drawIndirectFirstInstance = true,
465 .depthClamp = true,
466 .depthBiasClamp = true,
467 .fillModeNonSolid = true,
468 .depthBounds = true,
469 .wideLines = true,
470 .largePoints = true,
471 .alphaToOne = true,
472 .multiViewport = true,
473 .samplerAnisotropy = true,
474 .textureCompressionETC2 = false,
475 .textureCompressionASTC_LDR = false,
476 .textureCompressionBC = true,
477 .occlusionQueryPrecise = true,
478 .pipelineStatisticsQuery = false,
479 .vertexPipelineStoresAndAtomics = true,
480 .fragmentStoresAndAtomics = true,
481 .shaderTessellationAndGeometryPointSize = true,
482 .shaderImageGatherExtended = true,
483 .shaderStorageImageExtendedFormats = true,
484 .shaderStorageImageMultisample = false,
485 .shaderUniformBufferArrayDynamicIndexing = true,
486 .shaderSampledImageArrayDynamicIndexing = true,
487 .shaderStorageBufferArrayDynamicIndexing = true,
488 .shaderStorageImageArrayDynamicIndexing = true,
489 .shaderStorageImageReadWithoutFormat = true,
490 .shaderStorageImageWriteWithoutFormat = true,
491 .shaderClipDistance = true,
492 .shaderCullDistance = true,
493 .shaderFloat64 = true,
494 .shaderInt64 = false,
495 .shaderInt16 = false,
496 .sparseBinding = true,
497 .variableMultisampleRate = false,
498 .inheritedQueries = false,
499 };
500 }
501
502 void radv_GetPhysicalDeviceFeatures2KHR(
503 VkPhysicalDevice physicalDevice,
504 VkPhysicalDeviceFeatures2KHR *pFeatures)
505 {
506 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
507 }
508
509 static uint32_t radv_get_driver_version()
510 {
511 const char *minor_string = strchr(VERSION, '.');
512 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
513 int major = atoi(VERSION);
514 int minor = minor_string ? atoi(minor_string + 1) : 0;
515 int patch = patch_string ? atoi(patch_string + 1) : 0;
516 if (strstr(VERSION, "devel")) {
517 if (patch == 0) {
518 patch = 99;
519 if (minor == 0) {
520 minor = 99;
521 --major;
522 } else
523 --minor;
524 } else
525 --patch;
526 }
527 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
528 return version;
529 }
530
531 void radv_GetPhysicalDeviceProperties(
532 VkPhysicalDevice physicalDevice,
533 VkPhysicalDeviceProperties* pProperties)
534 {
535 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
536 VkSampleCountFlags sample_counts = 0xf;
537 VkPhysicalDeviceLimits limits = {
538 .maxImageDimension1D = (1 << 14),
539 .maxImageDimension2D = (1 << 14),
540 .maxImageDimension3D = (1 << 11),
541 .maxImageDimensionCube = (1 << 14),
542 .maxImageArrayLayers = (1 << 11),
543 .maxTexelBufferElements = 128 * 1024 * 1024,
544 .maxUniformBufferRange = UINT32_MAX,
545 .maxStorageBufferRange = UINT32_MAX,
546 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
547 .maxMemoryAllocationCount = UINT32_MAX,
548 .maxSamplerAllocationCount = 64 * 1024,
549 .bufferImageGranularity = 64, /* A cache line */
550 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
551 .maxBoundDescriptorSets = MAX_SETS,
552 .maxPerStageDescriptorSamplers = 64,
553 .maxPerStageDescriptorUniformBuffers = 64,
554 .maxPerStageDescriptorStorageBuffers = 64,
555 .maxPerStageDescriptorSampledImages = 64,
556 .maxPerStageDescriptorStorageImages = 64,
557 .maxPerStageDescriptorInputAttachments = 64,
558 .maxPerStageResources = 128,
559 .maxDescriptorSetSamplers = 256,
560 .maxDescriptorSetUniformBuffers = 256,
561 .maxDescriptorSetUniformBuffersDynamic = 256,
562 .maxDescriptorSetStorageBuffers = 256,
563 .maxDescriptorSetStorageBuffersDynamic = 256,
564 .maxDescriptorSetSampledImages = 256,
565 .maxDescriptorSetStorageImages = 256,
566 .maxDescriptorSetInputAttachments = 256,
567 .maxVertexInputAttributes = 32,
568 .maxVertexInputBindings = 32,
569 .maxVertexInputAttributeOffset = 2047,
570 .maxVertexInputBindingStride = 2048,
571 .maxVertexOutputComponents = 128,
572 .maxTessellationGenerationLevel = 64,
573 .maxTessellationPatchSize = 32,
574 .maxTessellationControlPerVertexInputComponents = 128,
575 .maxTessellationControlPerVertexOutputComponents = 128,
576 .maxTessellationControlPerPatchOutputComponents = 120,
577 .maxTessellationControlTotalOutputComponents = 4096,
578 .maxTessellationEvaluationInputComponents = 128,
579 .maxTessellationEvaluationOutputComponents = 128,
580 .maxGeometryShaderInvocations = 32,
581 .maxGeometryInputComponents = 64,
582 .maxGeometryOutputComponents = 128,
583 .maxGeometryOutputVertices = 256,
584 .maxGeometryTotalOutputComponents = 1024,
585 .maxFragmentInputComponents = 128,
586 .maxFragmentOutputAttachments = 8,
587 .maxFragmentDualSrcAttachments = 1,
588 .maxFragmentCombinedOutputResources = 8,
589 .maxComputeSharedMemorySize = 32768,
590 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
591 .maxComputeWorkGroupInvocations = 2048,
592 .maxComputeWorkGroupSize = {
593 2048,
594 2048,
595 2048
596 },
597 .subPixelPrecisionBits = 4 /* FIXME */,
598 .subTexelPrecisionBits = 4 /* FIXME */,
599 .mipmapPrecisionBits = 4 /* FIXME */,
600 .maxDrawIndexedIndexValue = UINT32_MAX,
601 .maxDrawIndirectCount = UINT32_MAX,
602 .maxSamplerLodBias = 16,
603 .maxSamplerAnisotropy = 16,
604 .maxViewports = MAX_VIEWPORTS,
605 .maxViewportDimensions = { (1 << 14), (1 << 14) },
606 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
607 .viewportSubPixelBits = 13, /* We take a float? */
608 .minMemoryMapAlignment = 4096, /* A page */
609 .minTexelBufferOffsetAlignment = 1,
610 .minUniformBufferOffsetAlignment = 4,
611 .minStorageBufferOffsetAlignment = 4,
612 .minTexelOffset = -32,
613 .maxTexelOffset = 31,
614 .minTexelGatherOffset = -32,
615 .maxTexelGatherOffset = 31,
616 .minInterpolationOffset = -2,
617 .maxInterpolationOffset = 2,
618 .subPixelInterpolationOffsetBits = 8,
619 .maxFramebufferWidth = (1 << 14),
620 .maxFramebufferHeight = (1 << 14),
621 .maxFramebufferLayers = (1 << 10),
622 .framebufferColorSampleCounts = sample_counts,
623 .framebufferDepthSampleCounts = sample_counts,
624 .framebufferStencilSampleCounts = sample_counts,
625 .framebufferNoAttachmentsSampleCounts = sample_counts,
626 .maxColorAttachments = MAX_RTS,
627 .sampledImageColorSampleCounts = sample_counts,
628 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
629 .sampledImageDepthSampleCounts = sample_counts,
630 .sampledImageStencilSampleCounts = sample_counts,
631 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
632 .maxSampleMaskWords = 1,
633 .timestampComputeAndGraphics = false,
634 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
635 .maxClipDistances = 8,
636 .maxCullDistances = 8,
637 .maxCombinedClipAndCullDistances = 8,
638 .discreteQueuePriorities = 1,
639 .pointSizeRange = { 0.125, 255.875 },
640 .lineWidthRange = { 0.0, 7.9921875 },
641 .pointSizeGranularity = (1.0 / 8.0),
642 .lineWidthGranularity = (1.0 / 128.0),
643 .strictLines = false, /* FINISHME */
644 .standardSampleLocations = true,
645 .optimalBufferCopyOffsetAlignment = 128,
646 .optimalBufferCopyRowPitchAlignment = 128,
647 .nonCoherentAtomSize = 64,
648 };
649
650 *pProperties = (VkPhysicalDeviceProperties) {
651 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
652 .driverVersion = radv_get_driver_version(),
653 .vendorID = 0x1002,
654 .deviceID = pdevice->rad_info.pci_id,
655 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
656 .limits = limits,
657 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
658 };
659
660 strcpy(pProperties->deviceName, pdevice->name);
661 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
662 }
663
664 void radv_GetPhysicalDeviceProperties2KHR(
665 VkPhysicalDevice physicalDevice,
666 VkPhysicalDeviceProperties2KHR *pProperties)
667 {
668 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
669 }
670
671 static void radv_get_physical_device_queue_family_properties(
672 struct radv_physical_device* pdevice,
673 uint32_t* pCount,
674 VkQueueFamilyProperties** pQueueFamilyProperties)
675 {
676 int num_queue_families = 1;
677 int idx;
678 if (pdevice->rad_info.compute_rings > 0 &&
679 pdevice->rad_info.chip_class >= CIK &&
680 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
681 num_queue_families++;
682
683 if (pQueueFamilyProperties == NULL) {
684 *pCount = num_queue_families;
685 return;
686 }
687
688 if (!*pCount)
689 return;
690
691 idx = 0;
692 if (*pCount >= 1) {
693 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
694 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
695 VK_QUEUE_COMPUTE_BIT |
696 VK_QUEUE_TRANSFER_BIT |
697 VK_QUEUE_SPARSE_BINDING_BIT,
698 .queueCount = 1,
699 .timestampValidBits = 64,
700 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
701 };
702 idx++;
703 }
704
705 if (pdevice->rad_info.compute_rings > 0 &&
706 pdevice->rad_info.chip_class >= CIK &&
707 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
708 if (*pCount > idx) {
709 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
710 .queueFlags = VK_QUEUE_COMPUTE_BIT |
711 VK_QUEUE_TRANSFER_BIT |
712 VK_QUEUE_SPARSE_BINDING_BIT,
713 .queueCount = pdevice->rad_info.compute_rings,
714 .timestampValidBits = 64,
715 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
716 };
717 idx++;
718 }
719 }
720 *pCount = idx;
721 }
722
723 void radv_GetPhysicalDeviceQueueFamilyProperties(
724 VkPhysicalDevice physicalDevice,
725 uint32_t* pCount,
726 VkQueueFamilyProperties* pQueueFamilyProperties)
727 {
728 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
729 if (!pQueueFamilyProperties) {
730 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
731 return;
732 }
733 VkQueueFamilyProperties *properties[] = {
734 pQueueFamilyProperties + 0,
735 pQueueFamilyProperties + 1,
736 pQueueFamilyProperties + 2,
737 };
738 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
739 assert(*pCount <= 3);
740 }
741
742 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
743 VkPhysicalDevice physicalDevice,
744 uint32_t* pCount,
745 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
746 {
747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
748 if (!pQueueFamilyProperties) {
749 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
750 return;
751 }
752 VkQueueFamilyProperties *properties[] = {
753 &pQueueFamilyProperties[0].queueFamilyProperties,
754 &pQueueFamilyProperties[1].queueFamilyProperties,
755 &pQueueFamilyProperties[2].queueFamilyProperties,
756 };
757 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
758 assert(*pCount <= 3);
759 }
760
761 void radv_GetPhysicalDeviceMemoryProperties(
762 VkPhysicalDevice physicalDevice,
763 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
764 {
765 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
766
767 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
768
769 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
770 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
771 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
772 .heapIndex = RADV_MEM_HEAP_VRAM,
773 };
774 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
775 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
776 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
777 .heapIndex = RADV_MEM_HEAP_GTT,
778 };
779 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
780 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
781 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
782 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
783 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
784 };
785 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
786 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
787 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
788 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
789 .heapIndex = RADV_MEM_HEAP_GTT,
790 };
791
792 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
793
794 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
795 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
796 .size = physical_device->rad_info.vram_size -
797 physical_device->rad_info.visible_vram_size,
798 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
799 };
800 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
801 .size = physical_device->rad_info.visible_vram_size,
802 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
803 };
804 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
805 .size = physical_device->rad_info.gart_size,
806 .flags = 0,
807 };
808 }
809
810 void radv_GetPhysicalDeviceMemoryProperties2KHR(
811 VkPhysicalDevice physicalDevice,
812 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
813 {
814 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
815 &pMemoryProperties->memoryProperties);
816 }
817
818 static int
819 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
820 int queue_family_index, int idx)
821 {
822 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
823 queue->device = device;
824 queue->queue_family_index = queue_family_index;
825 queue->queue_idx = idx;
826
827 queue->hw_ctx = device->ws->ctx_create(device->ws);
828 if (!queue->hw_ctx)
829 return VK_ERROR_OUT_OF_HOST_MEMORY;
830
831 return VK_SUCCESS;
832 }
833
834 static void
835 radv_queue_finish(struct radv_queue *queue)
836 {
837 if (queue->hw_ctx)
838 queue->device->ws->ctx_destroy(queue->hw_ctx);
839
840 if (queue->initial_preamble_cs)
841 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
842 if (queue->continue_preamble_cs)
843 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
844 if (queue->descriptor_bo)
845 queue->device->ws->buffer_destroy(queue->descriptor_bo);
846 if (queue->scratch_bo)
847 queue->device->ws->buffer_destroy(queue->scratch_bo);
848 if (queue->esgs_ring_bo)
849 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
850 if (queue->gsvs_ring_bo)
851 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
852 if (queue->tess_factor_ring_bo)
853 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
854 if (queue->tess_offchip_ring_bo)
855 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
856 if (queue->compute_scratch_bo)
857 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
858 }
859
860 static void
861 radv_device_init_gs_info(struct radv_device *device)
862 {
863 switch (device->physical_device->rad_info.family) {
864 case CHIP_OLAND:
865 case CHIP_HAINAN:
866 case CHIP_KAVERI:
867 case CHIP_KABINI:
868 case CHIP_MULLINS:
869 case CHIP_ICELAND:
870 case CHIP_CARRIZO:
871 case CHIP_STONEY:
872 device->gs_table_depth = 16;
873 return;
874 case CHIP_TAHITI:
875 case CHIP_PITCAIRN:
876 case CHIP_VERDE:
877 case CHIP_BONAIRE:
878 case CHIP_HAWAII:
879 case CHIP_TONGA:
880 case CHIP_FIJI:
881 case CHIP_POLARIS10:
882 case CHIP_POLARIS11:
883 device->gs_table_depth = 32;
884 return;
885 default:
886 unreachable("unknown GPU");
887 }
888 }
889
890 VkResult radv_CreateDevice(
891 VkPhysicalDevice physicalDevice,
892 const VkDeviceCreateInfo* pCreateInfo,
893 const VkAllocationCallbacks* pAllocator,
894 VkDevice* pDevice)
895 {
896 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
897 VkResult result;
898 struct radv_device *device;
899
900 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
901 if (!is_extension_enabled(physical_device->extensions.ext_array,
902 physical_device->extensions.num_ext,
903 pCreateInfo->ppEnabledExtensionNames[i]))
904 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
905 }
906
907 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
908 sizeof(*device), 8,
909 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
910 if (!device)
911 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
912
913 memset(device, 0, sizeof(*device));
914
915 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
916 device->instance = physical_device->instance;
917 device->physical_device = physical_device;
918
919 device->debug_flags = device->instance->debug_flags;
920
921 device->ws = physical_device->ws;
922 if (pAllocator)
923 device->alloc = *pAllocator;
924 else
925 device->alloc = physical_device->instance->alloc;
926
927 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
928 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
929 uint32_t qfi = queue_create->queueFamilyIndex;
930
931 device->queues[qfi] = vk_alloc(&device->alloc,
932 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
933 if (!device->queues[qfi]) {
934 result = VK_ERROR_OUT_OF_HOST_MEMORY;
935 goto fail;
936 }
937
938 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
939
940 device->queue_count[qfi] = queue_create->queueCount;
941
942 for (unsigned q = 0; q < queue_create->queueCount; q++) {
943 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
944 if (result != VK_SUCCESS)
945 goto fail;
946 }
947 }
948
949 #if HAVE_LLVM < 0x0400
950 device->llvm_supports_spill = false;
951 #else
952 device->llvm_supports_spill = true;
953 #endif
954
955 /* The maximum number of scratch waves. Scratch space isn't divided
956 * evenly between CUs. The number is only a function of the number of CUs.
957 * We can decrease the constant to decrease the scratch buffer size.
958 *
959 * sctx->scratch_waves must be >= the maximum posible size of
960 * 1 threadgroup, so that the hw doesn't hang from being unable
961 * to start any.
962 *
963 * The recommended value is 4 per CU at most. Higher numbers don't
964 * bring much benefit, but they still occupy chip resources (think
965 * async compute). I've seen ~2% performance difference between 4 and 32.
966 */
967 uint32_t max_threads_per_block = 2048;
968 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
969 max_threads_per_block / 64);
970
971 radv_device_init_gs_info(device);
972
973 device->tess_offchip_block_dw_size =
974 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
975 device->has_distributed_tess =
976 device->physical_device->rad_info.chip_class >= VI &&
977 device->physical_device->rad_info.max_se >= 2;
978
979 result = radv_device_init_meta(device);
980 if (result != VK_SUCCESS)
981 goto fail;
982
983 radv_device_init_msaa(device);
984
985 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
986 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
987 switch (family) {
988 case RADV_QUEUE_GENERAL:
989 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
990 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
991 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
992 break;
993 case RADV_QUEUE_COMPUTE:
994 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
995 radeon_emit(device->empty_cs[family], 0);
996 break;
997 }
998 device->ws->cs_finalize(device->empty_cs[family]);
999
1000 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1001 switch (family) {
1002 case RADV_QUEUE_GENERAL:
1003 case RADV_QUEUE_COMPUTE:
1004 si_cs_emit_cache_flush(device->flush_cs[family],
1005 device->physical_device->rad_info.chip_class,
1006 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1007 RADV_CMD_FLAG_INV_ICACHE |
1008 RADV_CMD_FLAG_INV_SMEM_L1 |
1009 RADV_CMD_FLAG_INV_VMEM_L1 |
1010 RADV_CMD_FLAG_INV_GLOBAL_L2);
1011 break;
1012 }
1013 device->ws->cs_finalize(device->flush_cs[family]);
1014 }
1015
1016 if (getenv("RADV_TRACE_FILE")) {
1017 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1018 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1019 if (!device->trace_bo)
1020 goto fail;
1021
1022 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1023 if (!device->trace_id_ptr)
1024 goto fail;
1025 }
1026
1027 if (device->physical_device->rad_info.chip_class >= CIK)
1028 cik_create_gfx_config(device);
1029
1030 VkPipelineCacheCreateInfo ci;
1031 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1032 ci.pNext = NULL;
1033 ci.flags = 0;
1034 ci.pInitialData = NULL;
1035 ci.initialDataSize = 0;
1036 VkPipelineCache pc;
1037 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1038 &ci, NULL, &pc);
1039 if (result != VK_SUCCESS)
1040 goto fail;
1041
1042 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1043
1044 *pDevice = radv_device_to_handle(device);
1045 return VK_SUCCESS;
1046
1047 fail:
1048 if (device->trace_bo)
1049 device->ws->buffer_destroy(device->trace_bo);
1050
1051 if (device->gfx_init)
1052 device->ws->buffer_destroy(device->gfx_init);
1053
1054 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1055 for (unsigned q = 0; q < device->queue_count[i]; q++)
1056 radv_queue_finish(&device->queues[i][q]);
1057 if (device->queue_count[i])
1058 vk_free(&device->alloc, device->queues[i]);
1059 }
1060
1061 vk_free(&device->alloc, device);
1062 return result;
1063 }
1064
1065 void radv_DestroyDevice(
1066 VkDevice _device,
1067 const VkAllocationCallbacks* pAllocator)
1068 {
1069 RADV_FROM_HANDLE(radv_device, device, _device);
1070
1071 if (!device)
1072 return;
1073
1074 if (device->trace_bo)
1075 device->ws->buffer_destroy(device->trace_bo);
1076
1077 if (device->gfx_init)
1078 device->ws->buffer_destroy(device->gfx_init);
1079
1080 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1081 for (unsigned q = 0; q < device->queue_count[i]; q++)
1082 radv_queue_finish(&device->queues[i][q]);
1083 if (device->queue_count[i])
1084 vk_free(&device->alloc, device->queues[i]);
1085 if (device->empty_cs[i])
1086 device->ws->cs_destroy(device->empty_cs[i]);
1087 if (device->flush_cs[i])
1088 device->ws->cs_destroy(device->flush_cs[i]);
1089 }
1090 radv_device_finish_meta(device);
1091
1092 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1093 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1094
1095 vk_free(&device->alloc, device);
1096 }
1097
1098 VkResult radv_EnumerateInstanceExtensionProperties(
1099 const char* pLayerName,
1100 uint32_t* pPropertyCount,
1101 VkExtensionProperties* pProperties)
1102 {
1103 if (pProperties == NULL) {
1104 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1105 return VK_SUCCESS;
1106 }
1107
1108 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1109 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1110
1111 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1112 return VK_INCOMPLETE;
1113
1114 return VK_SUCCESS;
1115 }
1116
1117 VkResult radv_EnumerateDeviceExtensionProperties(
1118 VkPhysicalDevice physicalDevice,
1119 const char* pLayerName,
1120 uint32_t* pPropertyCount,
1121 VkExtensionProperties* pProperties)
1122 {
1123 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1124
1125 if (pProperties == NULL) {
1126 *pPropertyCount = pdevice->extensions.num_ext;
1127 return VK_SUCCESS;
1128 }
1129
1130 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1131 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1132
1133 if (*pPropertyCount < pdevice->extensions.num_ext)
1134 return VK_INCOMPLETE;
1135
1136 return VK_SUCCESS;
1137 }
1138
1139 VkResult radv_EnumerateInstanceLayerProperties(
1140 uint32_t* pPropertyCount,
1141 VkLayerProperties* pProperties)
1142 {
1143 if (pProperties == NULL) {
1144 *pPropertyCount = 0;
1145 return VK_SUCCESS;
1146 }
1147
1148 /* None supported at this time */
1149 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1150 }
1151
1152 VkResult radv_EnumerateDeviceLayerProperties(
1153 VkPhysicalDevice physicalDevice,
1154 uint32_t* pPropertyCount,
1155 VkLayerProperties* pProperties)
1156 {
1157 if (pProperties == NULL) {
1158 *pPropertyCount = 0;
1159 return VK_SUCCESS;
1160 }
1161
1162 /* None supported at this time */
1163 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1164 }
1165
1166 void radv_GetDeviceQueue(
1167 VkDevice _device,
1168 uint32_t queueFamilyIndex,
1169 uint32_t queueIndex,
1170 VkQueue* pQueue)
1171 {
1172 RADV_FROM_HANDLE(radv_device, device, _device);
1173
1174 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1175 }
1176
1177 static void radv_dump_trace(struct radv_device *device,
1178 struct radeon_winsys_cs *cs)
1179 {
1180 const char *filename = getenv("RADV_TRACE_FILE");
1181 FILE *f = fopen(filename, "w");
1182 if (!f) {
1183 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1184 return;
1185 }
1186
1187 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1188 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1189 fclose(f);
1190 }
1191
1192 static void
1193 fill_geom_tess_rings(struct radv_queue *queue,
1194 uint32_t *map,
1195 bool add_sample_positions,
1196 uint32_t esgs_ring_size,
1197 struct radeon_winsys_bo *esgs_ring_bo,
1198 uint32_t gsvs_ring_size,
1199 struct radeon_winsys_bo *gsvs_ring_bo,
1200 uint32_t tess_factor_ring_size,
1201 struct radeon_winsys_bo *tess_factor_ring_bo,
1202 uint32_t tess_offchip_ring_size,
1203 struct radeon_winsys_bo *tess_offchip_ring_bo)
1204 {
1205 uint64_t esgs_va = 0, gsvs_va = 0;
1206 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1207 uint32_t *desc = &map[4];
1208
1209 if (esgs_ring_bo)
1210 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1211 if (gsvs_ring_bo)
1212 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1213 if (tess_factor_ring_bo)
1214 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1215 if (tess_offchip_ring_bo)
1216 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1217
1218 /* stride 0, num records - size, add tid, swizzle, elsize4,
1219 index stride 64 */
1220 desc[0] = esgs_va;
1221 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1222 S_008F04_STRIDE(0) |
1223 S_008F04_SWIZZLE_ENABLE(true);
1224 desc[2] = esgs_ring_size;
1225 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1226 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1227 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1228 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1229 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1230 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1231 S_008F0C_ELEMENT_SIZE(1) |
1232 S_008F0C_INDEX_STRIDE(3) |
1233 S_008F0C_ADD_TID_ENABLE(true);
1234
1235 desc += 4;
1236 /* GS entry for ES->GS ring */
1237 /* stride 0, num records - size, elsize0,
1238 index stride 0 */
1239 desc[0] = esgs_va;
1240 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1241 S_008F04_STRIDE(0) |
1242 S_008F04_SWIZZLE_ENABLE(false);
1243 desc[2] = esgs_ring_size;
1244 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1245 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1246 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1247 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1248 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1249 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1250 S_008F0C_ELEMENT_SIZE(0) |
1251 S_008F0C_INDEX_STRIDE(0) |
1252 S_008F0C_ADD_TID_ENABLE(false);
1253
1254 desc += 4;
1255 /* VS entry for GS->VS ring */
1256 /* stride 0, num records - size, elsize0,
1257 index stride 0 */
1258 desc[0] = gsvs_va;
1259 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1260 S_008F04_STRIDE(0) |
1261 S_008F04_SWIZZLE_ENABLE(false);
1262 desc[2] = gsvs_ring_size;
1263 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1264 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1265 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1266 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1267 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1268 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1269 S_008F0C_ELEMENT_SIZE(0) |
1270 S_008F0C_INDEX_STRIDE(0) |
1271 S_008F0C_ADD_TID_ENABLE(false);
1272 desc += 4;
1273
1274 /* stride gsvs_itemsize, num records 64
1275 elsize 4, index stride 16 */
1276 /* shader will patch stride and desc[2] */
1277 desc[0] = gsvs_va;
1278 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1279 S_008F04_STRIDE(0) |
1280 S_008F04_SWIZZLE_ENABLE(true);
1281 desc[2] = 0;
1282 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1283 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1284 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1285 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1286 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1287 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1288 S_008F0C_ELEMENT_SIZE(1) |
1289 S_008F0C_INDEX_STRIDE(1) |
1290 S_008F0C_ADD_TID_ENABLE(true);
1291 desc += 4;
1292
1293 desc[0] = tess_factor_va;
1294 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1295 S_008F04_STRIDE(0) |
1296 S_008F04_SWIZZLE_ENABLE(false);
1297 desc[2] = tess_factor_ring_size;
1298 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1299 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1300 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1301 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1302 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1303 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1304 S_008F0C_ELEMENT_SIZE(0) |
1305 S_008F0C_INDEX_STRIDE(0) |
1306 S_008F0C_ADD_TID_ENABLE(false);
1307 desc += 4;
1308
1309 desc[0] = tess_offchip_va;
1310 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1311 S_008F04_STRIDE(0) |
1312 S_008F04_SWIZZLE_ENABLE(false);
1313 desc[2] = tess_offchip_ring_size;
1314 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1315 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1316 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1317 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1318 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1319 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1320 S_008F0C_ELEMENT_SIZE(0) |
1321 S_008F0C_INDEX_STRIDE(0) |
1322 S_008F0C_ADD_TID_ENABLE(false);
1323 desc += 4;
1324
1325 /* add sample positions after all rings */
1326 memcpy(desc, queue->device->sample_locations_1x, 8);
1327 desc += 2;
1328 memcpy(desc, queue->device->sample_locations_2x, 16);
1329 desc += 4;
1330 memcpy(desc, queue->device->sample_locations_4x, 32);
1331 desc += 8;
1332 memcpy(desc, queue->device->sample_locations_8x, 64);
1333 desc += 16;
1334 memcpy(desc, queue->device->sample_locations_16x, 128);
1335 }
1336
1337 static unsigned
1338 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1339 {
1340 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1341 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1342 device->physical_device->rad_info.family != CHIP_STONEY;
1343 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1344 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1345 device->physical_device->rad_info.max_se;
1346 unsigned offchip_granularity;
1347 unsigned hs_offchip_param;
1348 switch (device->tess_offchip_block_dw_size) {
1349 default:
1350 assert(0);
1351 /* fall through */
1352 case 8192:
1353 offchip_granularity = V_03093C_X_8K_DWORDS;
1354 break;
1355 case 4096:
1356 offchip_granularity = V_03093C_X_4K_DWORDS;
1357 break;
1358 }
1359
1360 switch (device->physical_device->rad_info.chip_class) {
1361 case SI:
1362 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1363 break;
1364 case CIK:
1365 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1366 break;
1367 case VI:
1368 default:
1369 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
1370 break;
1371 }
1372
1373 *max_offchip_buffers_p = max_offchip_buffers;
1374 if (device->physical_device->rad_info.chip_class >= CIK) {
1375 if (device->physical_device->rad_info.chip_class >= VI)
1376 --max_offchip_buffers;
1377 hs_offchip_param =
1378 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1379 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1380 } else {
1381 hs_offchip_param =
1382 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1383 }
1384 return hs_offchip_param;
1385 }
1386
1387 static VkResult
1388 radv_get_preamble_cs(struct radv_queue *queue,
1389 uint32_t scratch_size,
1390 uint32_t compute_scratch_size,
1391 uint32_t esgs_ring_size,
1392 uint32_t gsvs_ring_size,
1393 bool needs_tess_rings,
1394 bool needs_sample_positions,
1395 struct radeon_winsys_cs **initial_preamble_cs,
1396 struct radeon_winsys_cs **continue_preamble_cs)
1397 {
1398 struct radeon_winsys_bo *scratch_bo = NULL;
1399 struct radeon_winsys_bo *descriptor_bo = NULL;
1400 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1401 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1402 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1403 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1404 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1405 struct radeon_winsys_cs *dest_cs[2] = {0};
1406 bool add_tess_rings = false, add_sample_positions = false;
1407 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1408 unsigned max_offchip_buffers;
1409 unsigned hs_offchip_param = 0;
1410 if (!queue->has_tess_rings) {
1411 if (needs_tess_rings)
1412 add_tess_rings = true;
1413 }
1414 if (!queue->has_sample_positions) {
1415 if (needs_sample_positions)
1416 add_sample_positions = true;
1417 }
1418 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1419 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1420 &max_offchip_buffers);
1421 tess_offchip_ring_size = max_offchip_buffers *
1422 queue->device->tess_offchip_block_dw_size * 4;
1423
1424 if (scratch_size <= queue->scratch_size &&
1425 compute_scratch_size <= queue->compute_scratch_size &&
1426 esgs_ring_size <= queue->esgs_ring_size &&
1427 gsvs_ring_size <= queue->gsvs_ring_size &&
1428 !add_tess_rings && !add_sample_positions &&
1429 queue->initial_preamble_cs) {
1430 *initial_preamble_cs = queue->initial_preamble_cs;
1431 *continue_preamble_cs = queue->continue_preamble_cs;
1432 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1433 *continue_preamble_cs = NULL;
1434 return VK_SUCCESS;
1435 }
1436
1437 if (scratch_size > queue->scratch_size) {
1438 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1439 scratch_size,
1440 4096,
1441 RADEON_DOMAIN_VRAM,
1442 RADEON_FLAG_NO_CPU_ACCESS);
1443 if (!scratch_bo)
1444 goto fail;
1445 } else
1446 scratch_bo = queue->scratch_bo;
1447
1448 if (compute_scratch_size > queue->compute_scratch_size) {
1449 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1450 compute_scratch_size,
1451 4096,
1452 RADEON_DOMAIN_VRAM,
1453 RADEON_FLAG_NO_CPU_ACCESS);
1454 if (!compute_scratch_bo)
1455 goto fail;
1456
1457 } else
1458 compute_scratch_bo = queue->compute_scratch_bo;
1459
1460 if (esgs_ring_size > queue->esgs_ring_size) {
1461 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1462 esgs_ring_size,
1463 4096,
1464 RADEON_DOMAIN_VRAM,
1465 RADEON_FLAG_NO_CPU_ACCESS);
1466 if (!esgs_ring_bo)
1467 goto fail;
1468 } else {
1469 esgs_ring_bo = queue->esgs_ring_bo;
1470 esgs_ring_size = queue->esgs_ring_size;
1471 }
1472
1473 if (gsvs_ring_size > queue->gsvs_ring_size) {
1474 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1475 gsvs_ring_size,
1476 4096,
1477 RADEON_DOMAIN_VRAM,
1478 RADEON_FLAG_NO_CPU_ACCESS);
1479 if (!gsvs_ring_bo)
1480 goto fail;
1481 } else {
1482 gsvs_ring_bo = queue->gsvs_ring_bo;
1483 gsvs_ring_size = queue->gsvs_ring_size;
1484 }
1485
1486 if (add_tess_rings) {
1487 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1488 tess_factor_ring_size,
1489 256,
1490 RADEON_DOMAIN_VRAM,
1491 RADEON_FLAG_NO_CPU_ACCESS);
1492 if (!tess_factor_ring_bo)
1493 goto fail;
1494 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1495 tess_offchip_ring_size,
1496 256,
1497 RADEON_DOMAIN_VRAM,
1498 RADEON_FLAG_NO_CPU_ACCESS);
1499 if (!tess_offchip_ring_bo)
1500 goto fail;
1501 } else {
1502 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1503 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1504 }
1505
1506 if (scratch_bo != queue->scratch_bo ||
1507 esgs_ring_bo != queue->esgs_ring_bo ||
1508 gsvs_ring_bo != queue->gsvs_ring_bo ||
1509 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1510 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1511 uint32_t size = 0;
1512 if (gsvs_ring_bo || esgs_ring_bo ||
1513 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1514 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1515 if (add_sample_positions)
1516 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1517 }
1518 else if (scratch_bo)
1519 size = 8; /* 2 dword */
1520
1521 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1522 size,
1523 4096,
1524 RADEON_DOMAIN_VRAM,
1525 RADEON_FLAG_CPU_ACCESS);
1526 if (!descriptor_bo)
1527 goto fail;
1528 } else
1529 descriptor_bo = queue->descriptor_bo;
1530
1531 for(int i = 0; i < 2; ++i) {
1532 struct radeon_winsys_cs *cs = NULL;
1533 cs = queue->device->ws->cs_create(queue->device->ws,
1534 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1535 if (!cs)
1536 goto fail;
1537
1538 dest_cs[i] = cs;
1539
1540 if (scratch_bo)
1541 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1542
1543 if (esgs_ring_bo)
1544 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1545
1546 if (gsvs_ring_bo)
1547 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1548
1549 if (tess_factor_ring_bo)
1550 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1551
1552 if (tess_offchip_ring_bo)
1553 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1554
1555 if (descriptor_bo)
1556 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1557
1558 if (descriptor_bo != queue->descriptor_bo) {
1559 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1560
1561 if (scratch_bo) {
1562 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1563 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1564 S_008F04_SWIZZLE_ENABLE(1);
1565 map[0] = scratch_va;
1566 map[1] = rsrc1;
1567 }
1568
1569 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1570 add_sample_positions)
1571 fill_geom_tess_rings(queue, map, add_sample_positions,
1572 esgs_ring_size, esgs_ring_bo,
1573 gsvs_ring_size, gsvs_ring_bo,
1574 tess_factor_ring_size, tess_factor_ring_bo,
1575 tess_offchip_ring_size, tess_offchip_ring_bo);
1576
1577 queue->device->ws->buffer_unmap(descriptor_bo);
1578 }
1579
1580 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1581 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1582 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1583 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1584 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1585 }
1586
1587 if (esgs_ring_bo || gsvs_ring_bo) {
1588 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1589 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1590 radeon_emit(cs, esgs_ring_size >> 8);
1591 radeon_emit(cs, gsvs_ring_size >> 8);
1592 } else {
1593 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1594 radeon_emit(cs, esgs_ring_size >> 8);
1595 radeon_emit(cs, gsvs_ring_size >> 8);
1596 }
1597 }
1598
1599 if (tess_factor_ring_bo) {
1600 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1601 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1602 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1603 S_030938_SIZE(tess_factor_ring_size / 4));
1604 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1605 tf_va >> 8);
1606 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1607 } else {
1608 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1609 S_008988_SIZE(tess_factor_ring_size / 4));
1610 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1611 tf_va >> 8);
1612 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1613 hs_offchip_param);
1614 }
1615 }
1616
1617 if (descriptor_bo) {
1618 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1619 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1620 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1621 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1622 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1623 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1624
1625 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1626
1627 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1628 radeon_set_sh_reg_seq(cs, regs[i], 2);
1629 radeon_emit(cs, va);
1630 radeon_emit(cs, va >> 32);
1631 }
1632 }
1633
1634 if (compute_scratch_bo) {
1635 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1636 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1637 S_008F04_SWIZZLE_ENABLE(1);
1638
1639 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1640
1641 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1642 radeon_emit(cs, scratch_va);
1643 radeon_emit(cs, rsrc1);
1644 }
1645
1646 if (!i) {
1647 si_cs_emit_cache_flush(cs,
1648 queue->device->physical_device->rad_info.chip_class,
1649 queue->queue_family_index == RING_COMPUTE &&
1650 queue->device->physical_device->rad_info.chip_class >= CIK,
1651 RADV_CMD_FLAG_INV_ICACHE |
1652 RADV_CMD_FLAG_INV_SMEM_L1 |
1653 RADV_CMD_FLAG_INV_VMEM_L1 |
1654 RADV_CMD_FLAG_INV_GLOBAL_L2);
1655 }
1656
1657 if (!queue->device->ws->cs_finalize(cs))
1658 goto fail;
1659 }
1660
1661 if (queue->initial_preamble_cs)
1662 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1663
1664 if (queue->continue_preamble_cs)
1665 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1666
1667 queue->initial_preamble_cs = dest_cs[0];
1668 queue->continue_preamble_cs = dest_cs[1];
1669
1670 if (scratch_bo != queue->scratch_bo) {
1671 if (queue->scratch_bo)
1672 queue->device->ws->buffer_destroy(queue->scratch_bo);
1673 queue->scratch_bo = scratch_bo;
1674 queue->scratch_size = scratch_size;
1675 }
1676
1677 if (compute_scratch_bo != queue->compute_scratch_bo) {
1678 if (queue->compute_scratch_bo)
1679 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1680 queue->compute_scratch_bo = compute_scratch_bo;
1681 queue->compute_scratch_size = compute_scratch_size;
1682 }
1683
1684 if (esgs_ring_bo != queue->esgs_ring_bo) {
1685 if (queue->esgs_ring_bo)
1686 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1687 queue->esgs_ring_bo = esgs_ring_bo;
1688 queue->esgs_ring_size = esgs_ring_size;
1689 }
1690
1691 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1692 if (queue->gsvs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1694 queue->gsvs_ring_bo = gsvs_ring_bo;
1695 queue->gsvs_ring_size = gsvs_ring_size;
1696 }
1697
1698 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1699 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1700 }
1701
1702 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1703 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1704 queue->has_tess_rings = true;
1705 }
1706
1707 if (descriptor_bo != queue->descriptor_bo) {
1708 if (queue->descriptor_bo)
1709 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1710
1711 queue->descriptor_bo = descriptor_bo;
1712 }
1713
1714 if (add_sample_positions)
1715 queue->has_sample_positions = true;
1716
1717 *initial_preamble_cs = queue->initial_preamble_cs;
1718 *continue_preamble_cs = queue->continue_preamble_cs;
1719 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1720 *continue_preamble_cs = NULL;
1721 return VK_SUCCESS;
1722 fail:
1723 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1724 if (dest_cs[i])
1725 queue->device->ws->cs_destroy(dest_cs[i]);
1726 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1727 queue->device->ws->buffer_destroy(descriptor_bo);
1728 if (scratch_bo && scratch_bo != queue->scratch_bo)
1729 queue->device->ws->buffer_destroy(scratch_bo);
1730 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1731 queue->device->ws->buffer_destroy(compute_scratch_bo);
1732 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1733 queue->device->ws->buffer_destroy(esgs_ring_bo);
1734 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1735 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1736 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1737 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1738 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1739 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1740 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1741 }
1742
1743 VkResult radv_QueueSubmit(
1744 VkQueue _queue,
1745 uint32_t submitCount,
1746 const VkSubmitInfo* pSubmits,
1747 VkFence _fence)
1748 {
1749 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1750 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1751 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1752 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1753 int ret;
1754 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1755 uint32_t scratch_size = 0;
1756 uint32_t compute_scratch_size = 0;
1757 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1758 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1759 VkResult result;
1760 bool fence_emitted = false;
1761 bool tess_rings_needed = false;
1762 bool sample_positions_needed = false;
1763
1764 /* Do this first so failing to allocate scratch buffers can't result in
1765 * partially executed submissions. */
1766 for (uint32_t i = 0; i < submitCount; i++) {
1767 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1769 pSubmits[i].pCommandBuffers[j]);
1770
1771 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1772 compute_scratch_size = MAX2(compute_scratch_size,
1773 cmd_buffer->compute_scratch_size_needed);
1774 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1775 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1776 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1777 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1778 }
1779 }
1780
1781 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1782 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1783 sample_positions_needed,
1784 &initial_preamble_cs, &continue_preamble_cs);
1785 if (result != VK_SUCCESS)
1786 return result;
1787
1788 for (uint32_t i = 0; i < submitCount; i++) {
1789 struct radeon_winsys_cs **cs_array;
1790 bool do_flush = !i;
1791 bool can_patch = !do_flush;
1792 uint32_t advance;
1793
1794 if (!pSubmits[i].commandBufferCount) {
1795 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1796 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1797 &queue->device->empty_cs[queue->queue_family_index],
1798 1, NULL, NULL,
1799 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1800 pSubmits[i].waitSemaphoreCount,
1801 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1802 pSubmits[i].signalSemaphoreCount,
1803 false, base_fence);
1804 if (ret) {
1805 radv_loge("failed to submit CS %d\n", i);
1806 abort();
1807 }
1808 fence_emitted = true;
1809 }
1810 continue;
1811 }
1812
1813 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1814 (pSubmits[i].commandBufferCount + do_flush));
1815
1816 if(do_flush)
1817 cs_array[0] = queue->device->flush_cs[queue->queue_family_index];
1818
1819 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1821 pSubmits[i].pCommandBuffers[j]);
1822 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1823
1824 cs_array[j + do_flush] = cmd_buffer->cs;
1825 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1826 can_patch = false;
1827 }
1828
1829 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1830 advance = MIN2(max_cs_submission,
1831 pSubmits[i].commandBufferCount + do_flush - j);
1832 bool b = j == 0;
1833 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1834
1835 if (queue->device->trace_bo)
1836 *queue->device->trace_id_ptr = 0;
1837
1838 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1839 advance, initial_preamble_cs, continue_preamble_cs,
1840 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1841 b ? pSubmits[i].waitSemaphoreCount : 0,
1842 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1843 e ? pSubmits[i].signalSemaphoreCount : 0,
1844 can_patch, base_fence);
1845
1846 if (ret) {
1847 radv_loge("failed to submit CS %d\n", i);
1848 abort();
1849 }
1850 fence_emitted = true;
1851 if (queue->device->trace_bo) {
1852 bool success = queue->device->ws->ctx_wait_idle(
1853 queue->hw_ctx,
1854 radv_queue_family_to_ring(
1855 queue->queue_family_index),
1856 queue->queue_idx);
1857
1858 if (!success) { /* Hang */
1859 radv_dump_trace(queue->device, cs_array[j]);
1860 abort();
1861 }
1862 }
1863 }
1864 free(cs_array);
1865 }
1866
1867 if (fence) {
1868 if (!fence_emitted)
1869 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1870 &queue->device->empty_cs[queue->queue_family_index],
1871 1, NULL, NULL, NULL, 0, NULL, 0,
1872 false, base_fence);
1873
1874 fence->submitted = true;
1875 }
1876
1877 return VK_SUCCESS;
1878 }
1879
1880 VkResult radv_QueueWaitIdle(
1881 VkQueue _queue)
1882 {
1883 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1884
1885 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1886 radv_queue_family_to_ring(queue->queue_family_index),
1887 queue->queue_idx);
1888 return VK_SUCCESS;
1889 }
1890
1891 VkResult radv_DeviceWaitIdle(
1892 VkDevice _device)
1893 {
1894 RADV_FROM_HANDLE(radv_device, device, _device);
1895
1896 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1897 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1898 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1899 }
1900 }
1901 return VK_SUCCESS;
1902 }
1903
1904 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1905 VkInstance instance,
1906 const char* pName)
1907 {
1908 return radv_lookup_entrypoint(pName);
1909 }
1910
1911 /* The loader wants us to expose a second GetInstanceProcAddr function
1912 * to work around certain LD_PRELOAD issues seen in apps.
1913 */
1914 PUBLIC
1915 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1916 VkInstance instance,
1917 const char* pName);
1918
1919 PUBLIC
1920 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1921 VkInstance instance,
1922 const char* pName)
1923 {
1924 return radv_GetInstanceProcAddr(instance, pName);
1925 }
1926
1927 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1928 VkDevice device,
1929 const char* pName)
1930 {
1931 return radv_lookup_entrypoint(pName);
1932 }
1933
1934 bool radv_get_memory_fd(struct radv_device *device,
1935 struct radv_device_memory *memory,
1936 int *pFD)
1937 {
1938 struct radeon_bo_metadata metadata;
1939
1940 if (memory->image) {
1941 radv_init_metadata(device, memory->image, &metadata);
1942 device->ws->buffer_set_metadata(memory->bo, &metadata);
1943 }
1944
1945 return device->ws->buffer_get_fd(device->ws, memory->bo,
1946 pFD);
1947 }
1948
1949 VkResult radv_AllocateMemory(
1950 VkDevice _device,
1951 const VkMemoryAllocateInfo* pAllocateInfo,
1952 const VkAllocationCallbacks* pAllocator,
1953 VkDeviceMemory* pMem)
1954 {
1955 RADV_FROM_HANDLE(radv_device, device, _device);
1956 struct radv_device_memory *mem;
1957 VkResult result;
1958 enum radeon_bo_domain domain;
1959 uint32_t flags = 0;
1960 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
1961 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1962
1963 if (pAllocateInfo->allocationSize == 0) {
1964 /* Apparently, this is allowed */
1965 *pMem = VK_NULL_HANDLE;
1966 return VK_SUCCESS;
1967 }
1968
1969 vk_foreach_struct(ext, pAllocateInfo->pNext) {
1970 switch (ext->sType) {
1971 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
1972 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
1973 break;
1974 default:
1975 break;
1976 }
1977 }
1978
1979 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1980 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1981 if (mem == NULL)
1982 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1983
1984 if (dedicate_info) {
1985 mem->image = radv_image_from_handle(dedicate_info->image);
1986 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
1987 } else {
1988 mem->image = NULL;
1989 mem->buffer = NULL;
1990 }
1991
1992 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1993 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1994 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1995 domain = RADEON_DOMAIN_GTT;
1996 else
1997 domain = RADEON_DOMAIN_VRAM;
1998
1999 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2000 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2001 else
2002 flags |= RADEON_FLAG_CPU_ACCESS;
2003
2004 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2005 flags |= RADEON_FLAG_GTT_WC;
2006
2007 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2008 domain, flags);
2009
2010 if (!mem->bo) {
2011 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2012 goto fail;
2013 }
2014 mem->type_index = pAllocateInfo->memoryTypeIndex;
2015
2016 *pMem = radv_device_memory_to_handle(mem);
2017
2018 return VK_SUCCESS;
2019
2020 fail:
2021 vk_free2(&device->alloc, pAllocator, mem);
2022
2023 return result;
2024 }
2025
2026 void radv_FreeMemory(
2027 VkDevice _device,
2028 VkDeviceMemory _mem,
2029 const VkAllocationCallbacks* pAllocator)
2030 {
2031 RADV_FROM_HANDLE(radv_device, device, _device);
2032 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2033
2034 if (mem == NULL)
2035 return;
2036
2037 device->ws->buffer_destroy(mem->bo);
2038 mem->bo = NULL;
2039
2040 vk_free2(&device->alloc, pAllocator, mem);
2041 }
2042
2043 VkResult radv_MapMemory(
2044 VkDevice _device,
2045 VkDeviceMemory _memory,
2046 VkDeviceSize offset,
2047 VkDeviceSize size,
2048 VkMemoryMapFlags flags,
2049 void** ppData)
2050 {
2051 RADV_FROM_HANDLE(radv_device, device, _device);
2052 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2053
2054 if (mem == NULL) {
2055 *ppData = NULL;
2056 return VK_SUCCESS;
2057 }
2058
2059 *ppData = device->ws->buffer_map(mem->bo);
2060 if (*ppData) {
2061 *ppData += offset;
2062 return VK_SUCCESS;
2063 }
2064
2065 return VK_ERROR_MEMORY_MAP_FAILED;
2066 }
2067
2068 void radv_UnmapMemory(
2069 VkDevice _device,
2070 VkDeviceMemory _memory)
2071 {
2072 RADV_FROM_HANDLE(radv_device, device, _device);
2073 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2074
2075 if (mem == NULL)
2076 return;
2077
2078 device->ws->buffer_unmap(mem->bo);
2079 }
2080
2081 VkResult radv_FlushMappedMemoryRanges(
2082 VkDevice _device,
2083 uint32_t memoryRangeCount,
2084 const VkMappedMemoryRange* pMemoryRanges)
2085 {
2086 return VK_SUCCESS;
2087 }
2088
2089 VkResult radv_InvalidateMappedMemoryRanges(
2090 VkDevice _device,
2091 uint32_t memoryRangeCount,
2092 const VkMappedMemoryRange* pMemoryRanges)
2093 {
2094 return VK_SUCCESS;
2095 }
2096
2097 void radv_GetBufferMemoryRequirements(
2098 VkDevice device,
2099 VkBuffer _buffer,
2100 VkMemoryRequirements* pMemoryRequirements)
2101 {
2102 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2103
2104 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2105
2106 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2107 pMemoryRequirements->alignment = 4096;
2108 else
2109 pMemoryRequirements->alignment = 16;
2110
2111 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2112 }
2113
2114 void radv_GetImageMemoryRequirements(
2115 VkDevice device,
2116 VkImage _image,
2117 VkMemoryRequirements* pMemoryRequirements)
2118 {
2119 RADV_FROM_HANDLE(radv_image, image, _image);
2120
2121 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2122
2123 pMemoryRequirements->size = image->size;
2124 pMemoryRequirements->alignment = image->alignment;
2125 }
2126
2127 void radv_GetImageSparseMemoryRequirements(
2128 VkDevice device,
2129 VkImage image,
2130 uint32_t* pSparseMemoryRequirementCount,
2131 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2132 {
2133 stub();
2134 }
2135
2136 void radv_GetDeviceMemoryCommitment(
2137 VkDevice device,
2138 VkDeviceMemory memory,
2139 VkDeviceSize* pCommittedMemoryInBytes)
2140 {
2141 *pCommittedMemoryInBytes = 0;
2142 }
2143
2144 VkResult radv_BindBufferMemory(
2145 VkDevice device,
2146 VkBuffer _buffer,
2147 VkDeviceMemory _memory,
2148 VkDeviceSize memoryOffset)
2149 {
2150 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2151 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2152
2153 if (mem) {
2154 buffer->bo = mem->bo;
2155 buffer->offset = memoryOffset;
2156 } else {
2157 buffer->bo = NULL;
2158 buffer->offset = 0;
2159 }
2160
2161 return VK_SUCCESS;
2162 }
2163
2164 VkResult radv_BindImageMemory(
2165 VkDevice device,
2166 VkImage _image,
2167 VkDeviceMemory _memory,
2168 VkDeviceSize memoryOffset)
2169 {
2170 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2171 RADV_FROM_HANDLE(radv_image, image, _image);
2172
2173 if (mem) {
2174 image->bo = mem->bo;
2175 image->offset = memoryOffset;
2176 } else {
2177 image->bo = NULL;
2178 image->offset = 0;
2179 }
2180
2181 return VK_SUCCESS;
2182 }
2183
2184
2185 static void
2186 radv_sparse_buffer_bind_memory(struct radv_device *device,
2187 const VkSparseBufferMemoryBindInfo *bind)
2188 {
2189 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2190
2191 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2192 struct radv_device_memory *mem = NULL;
2193
2194 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2195 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2196
2197 device->ws->buffer_virtual_bind(buffer->bo,
2198 bind->pBinds[i].resourceOffset,
2199 bind->pBinds[i].size,
2200 mem ? mem->bo : NULL,
2201 bind->pBinds[i].memoryOffset);
2202 }
2203 }
2204
2205 static void
2206 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2207 const VkSparseImageOpaqueMemoryBindInfo *bind)
2208 {
2209 RADV_FROM_HANDLE(radv_image, image, bind->image);
2210
2211 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2212 struct radv_device_memory *mem = NULL;
2213
2214 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2215 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2216
2217 device->ws->buffer_virtual_bind(image->bo,
2218 bind->pBinds[i].resourceOffset,
2219 bind->pBinds[i].size,
2220 mem ? mem->bo : NULL,
2221 bind->pBinds[i].memoryOffset);
2222 }
2223 }
2224
2225 VkResult radv_QueueBindSparse(
2226 VkQueue _queue,
2227 uint32_t bindInfoCount,
2228 const VkBindSparseInfo* pBindInfo,
2229 VkFence _fence)
2230 {
2231 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2232 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2233 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2234 bool fence_emitted = false;
2235
2236 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2237 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2238 radv_sparse_buffer_bind_memory(queue->device,
2239 pBindInfo[i].pBufferBinds + j);
2240 }
2241
2242 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2243 radv_sparse_image_opaque_bind_memory(queue->device,
2244 pBindInfo[i].pImageOpaqueBinds + j);
2245 }
2246
2247 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2248 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2249 &queue->device->empty_cs[queue->queue_family_index],
2250 1, NULL, NULL,
2251 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2252 pBindInfo[i].waitSemaphoreCount,
2253 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2254 pBindInfo[i].signalSemaphoreCount,
2255 false, base_fence);
2256 fence_emitted = true;
2257 if (fence)
2258 fence->submitted = true;
2259 }
2260 }
2261
2262 if (fence && !fence_emitted) {
2263 fence->signalled = true;
2264 }
2265
2266 return VK_SUCCESS;
2267 }
2268
2269 VkResult radv_CreateFence(
2270 VkDevice _device,
2271 const VkFenceCreateInfo* pCreateInfo,
2272 const VkAllocationCallbacks* pAllocator,
2273 VkFence* pFence)
2274 {
2275 RADV_FROM_HANDLE(radv_device, device, _device);
2276 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2277 sizeof(*fence), 8,
2278 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2279
2280 if (!fence)
2281 return VK_ERROR_OUT_OF_HOST_MEMORY;
2282
2283 memset(fence, 0, sizeof(*fence));
2284 fence->submitted = false;
2285 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2286 fence->fence = device->ws->create_fence();
2287 if (!fence->fence) {
2288 vk_free2(&device->alloc, pAllocator, fence);
2289 return VK_ERROR_OUT_OF_HOST_MEMORY;
2290 }
2291
2292 *pFence = radv_fence_to_handle(fence);
2293
2294 return VK_SUCCESS;
2295 }
2296
2297 void radv_DestroyFence(
2298 VkDevice _device,
2299 VkFence _fence,
2300 const VkAllocationCallbacks* pAllocator)
2301 {
2302 RADV_FROM_HANDLE(radv_device, device, _device);
2303 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2304
2305 if (!fence)
2306 return;
2307 device->ws->destroy_fence(fence->fence);
2308 vk_free2(&device->alloc, pAllocator, fence);
2309 }
2310
2311 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2312 {
2313 uint64_t current_time;
2314 struct timespec tv;
2315
2316 clock_gettime(CLOCK_MONOTONIC, &tv);
2317 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2318
2319 timeout = MIN2(UINT64_MAX - current_time, timeout);
2320
2321 return current_time + timeout;
2322 }
2323
2324 VkResult radv_WaitForFences(
2325 VkDevice _device,
2326 uint32_t fenceCount,
2327 const VkFence* pFences,
2328 VkBool32 waitAll,
2329 uint64_t timeout)
2330 {
2331 RADV_FROM_HANDLE(radv_device, device, _device);
2332 timeout = radv_get_absolute_timeout(timeout);
2333
2334 if (!waitAll && fenceCount > 1) {
2335 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2336 }
2337
2338 for (uint32_t i = 0; i < fenceCount; ++i) {
2339 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2340 bool expired = false;
2341
2342 if (fence->signalled)
2343 continue;
2344
2345 if (!fence->submitted)
2346 return VK_TIMEOUT;
2347
2348 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2349 if (!expired)
2350 return VK_TIMEOUT;
2351
2352 fence->signalled = true;
2353 }
2354
2355 return VK_SUCCESS;
2356 }
2357
2358 VkResult radv_ResetFences(VkDevice device,
2359 uint32_t fenceCount,
2360 const VkFence *pFences)
2361 {
2362 for (unsigned i = 0; i < fenceCount; ++i) {
2363 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2364 fence->submitted = fence->signalled = false;
2365 }
2366
2367 return VK_SUCCESS;
2368 }
2369
2370 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2371 {
2372 RADV_FROM_HANDLE(radv_device, device, _device);
2373 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2374
2375 if (fence->signalled)
2376 return VK_SUCCESS;
2377 if (!fence->submitted)
2378 return VK_NOT_READY;
2379
2380 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2381 return VK_NOT_READY;
2382
2383 return VK_SUCCESS;
2384 }
2385
2386
2387 // Queue semaphore functions
2388
2389 VkResult radv_CreateSemaphore(
2390 VkDevice _device,
2391 const VkSemaphoreCreateInfo* pCreateInfo,
2392 const VkAllocationCallbacks* pAllocator,
2393 VkSemaphore* pSemaphore)
2394 {
2395 RADV_FROM_HANDLE(radv_device, device, _device);
2396 struct radeon_winsys_sem *sem;
2397
2398 sem = device->ws->create_sem(device->ws);
2399 if (!sem)
2400 return VK_ERROR_OUT_OF_HOST_MEMORY;
2401
2402 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2403 return VK_SUCCESS;
2404 }
2405
2406 void radv_DestroySemaphore(
2407 VkDevice _device,
2408 VkSemaphore _semaphore,
2409 const VkAllocationCallbacks* pAllocator)
2410 {
2411 RADV_FROM_HANDLE(radv_device, device, _device);
2412 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2413 if (!_semaphore)
2414 return;
2415
2416 device->ws->destroy_sem(sem);
2417 }
2418
2419 VkResult radv_CreateEvent(
2420 VkDevice _device,
2421 const VkEventCreateInfo* pCreateInfo,
2422 const VkAllocationCallbacks* pAllocator,
2423 VkEvent* pEvent)
2424 {
2425 RADV_FROM_HANDLE(radv_device, device, _device);
2426 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2427 sizeof(*event), 8,
2428 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2429
2430 if (!event)
2431 return VK_ERROR_OUT_OF_HOST_MEMORY;
2432
2433 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2434 RADEON_DOMAIN_GTT,
2435 RADEON_FLAG_CPU_ACCESS);
2436 if (!event->bo) {
2437 vk_free2(&device->alloc, pAllocator, event);
2438 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2439 }
2440
2441 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2442
2443 *pEvent = radv_event_to_handle(event);
2444
2445 return VK_SUCCESS;
2446 }
2447
2448 void radv_DestroyEvent(
2449 VkDevice _device,
2450 VkEvent _event,
2451 const VkAllocationCallbacks* pAllocator)
2452 {
2453 RADV_FROM_HANDLE(radv_device, device, _device);
2454 RADV_FROM_HANDLE(radv_event, event, _event);
2455
2456 if (!event)
2457 return;
2458 device->ws->buffer_destroy(event->bo);
2459 vk_free2(&device->alloc, pAllocator, event);
2460 }
2461
2462 VkResult radv_GetEventStatus(
2463 VkDevice _device,
2464 VkEvent _event)
2465 {
2466 RADV_FROM_HANDLE(radv_event, event, _event);
2467
2468 if (*event->map == 1)
2469 return VK_EVENT_SET;
2470 return VK_EVENT_RESET;
2471 }
2472
2473 VkResult radv_SetEvent(
2474 VkDevice _device,
2475 VkEvent _event)
2476 {
2477 RADV_FROM_HANDLE(radv_event, event, _event);
2478 *event->map = 1;
2479
2480 return VK_SUCCESS;
2481 }
2482
2483 VkResult radv_ResetEvent(
2484 VkDevice _device,
2485 VkEvent _event)
2486 {
2487 RADV_FROM_HANDLE(radv_event, event, _event);
2488 *event->map = 0;
2489
2490 return VK_SUCCESS;
2491 }
2492
2493 VkResult radv_CreateBuffer(
2494 VkDevice _device,
2495 const VkBufferCreateInfo* pCreateInfo,
2496 const VkAllocationCallbacks* pAllocator,
2497 VkBuffer* pBuffer)
2498 {
2499 RADV_FROM_HANDLE(radv_device, device, _device);
2500 struct radv_buffer *buffer;
2501
2502 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2503
2504 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2505 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2506 if (buffer == NULL)
2507 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2508
2509 buffer->size = pCreateInfo->size;
2510 buffer->usage = pCreateInfo->usage;
2511 buffer->bo = NULL;
2512 buffer->offset = 0;
2513 buffer->flags = pCreateInfo->flags;
2514
2515 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2516 buffer->bo = device->ws->buffer_create(device->ws,
2517 align64(buffer->size, 4096),
2518 4096, 0, RADEON_FLAG_VIRTUAL);
2519 if (!buffer->bo) {
2520 vk_free2(&device->alloc, pAllocator, buffer);
2521 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2522 }
2523 }
2524
2525 *pBuffer = radv_buffer_to_handle(buffer);
2526
2527 return VK_SUCCESS;
2528 }
2529
2530 void radv_DestroyBuffer(
2531 VkDevice _device,
2532 VkBuffer _buffer,
2533 const VkAllocationCallbacks* pAllocator)
2534 {
2535 RADV_FROM_HANDLE(radv_device, device, _device);
2536 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2537
2538 if (!buffer)
2539 return;
2540
2541 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2542 device->ws->buffer_destroy(buffer->bo);
2543
2544 vk_free2(&device->alloc, pAllocator, buffer);
2545 }
2546
2547 static inline unsigned
2548 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2549 {
2550 if (stencil)
2551 return image->surface.stencil_tiling_index[level];
2552 else
2553 return image->surface.tiling_index[level];
2554 }
2555
2556 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2557 {
2558 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2559 }
2560
2561 static void
2562 radv_initialise_color_surface(struct radv_device *device,
2563 struct radv_color_buffer_info *cb,
2564 struct radv_image_view *iview)
2565 {
2566 const struct vk_format_description *desc;
2567 unsigned ntype, format, swap, endian;
2568 unsigned blend_clamp = 0, blend_bypass = 0;
2569 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2570 uint64_t va;
2571 const struct radeon_surf *surf = &iview->image->surface;
2572 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2573
2574 desc = vk_format_description(iview->vk_format);
2575
2576 memset(cb, 0, sizeof(*cb));
2577
2578 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2579 va += level_info->offset;
2580 cb->cb_color_base = va >> 8;
2581
2582 /* CMASK variables */
2583 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2584 va += iview->image->cmask.offset;
2585 cb->cb_color_cmask = va >> 8;
2586 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2587
2588 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2589 va += iview->image->dcc_offset;
2590 cb->cb_dcc_base = va >> 8;
2591
2592 uint32_t max_slice = radv_surface_layer_count(iview);
2593 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2594 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2595
2596 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2597 pitch_tile_max = level_info->nblk_x / 8 - 1;
2598 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2599 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2600
2601 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2602 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2603
2604 /* Intensity is implemented as Red, so treat it that way. */
2605 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2606 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2607
2608 if (iview->image->samples > 1) {
2609 unsigned log_samples = util_logbase2(iview->image->samples);
2610
2611 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2612 S_028C74_NUM_FRAGMENTS(log_samples);
2613 }
2614
2615 if (iview->image->fmask.size) {
2616 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2617 if (device->physical_device->rad_info.chip_class >= CIK)
2618 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2619 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2620 cb->cb_color_fmask = va >> 8;
2621 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2622 } else {
2623 /* This must be set for fast clear to work without FMASK. */
2624 if (device->physical_device->rad_info.chip_class >= CIK)
2625 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2626 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2627 cb->cb_color_fmask = cb->cb_color_base;
2628 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2629 }
2630
2631 ntype = radv_translate_color_numformat(iview->vk_format,
2632 desc,
2633 vk_format_get_first_non_void_channel(iview->vk_format));
2634 format = radv_translate_colorformat(iview->vk_format);
2635 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2636 radv_finishme("Illegal color\n");
2637 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2638 endian = radv_colorformat_endian_swap(format);
2639
2640 /* blend clamp should be set for all NORM/SRGB types */
2641 if (ntype == V_028C70_NUMBER_UNORM ||
2642 ntype == V_028C70_NUMBER_SNORM ||
2643 ntype == V_028C70_NUMBER_SRGB)
2644 blend_clamp = 1;
2645
2646 /* set blend bypass according to docs if SINT/UINT or
2647 8/24 COLOR variants */
2648 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2649 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2650 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2651 blend_clamp = 0;
2652 blend_bypass = 1;
2653 }
2654 #if 0
2655 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2656 (format == V_028C70_COLOR_8 ||
2657 format == V_028C70_COLOR_8_8 ||
2658 format == V_028C70_COLOR_8_8_8_8))
2659 ->color_is_int8 = true;
2660 #endif
2661 cb->cb_color_info = S_028C70_FORMAT(format) |
2662 S_028C70_COMP_SWAP(swap) |
2663 S_028C70_BLEND_CLAMP(blend_clamp) |
2664 S_028C70_BLEND_BYPASS(blend_bypass) |
2665 S_028C70_SIMPLE_FLOAT(1) |
2666 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2667 ntype != V_028C70_NUMBER_SNORM &&
2668 ntype != V_028C70_NUMBER_SRGB &&
2669 format != V_028C70_COLOR_8_24 &&
2670 format != V_028C70_COLOR_24_8) |
2671 S_028C70_NUMBER_TYPE(ntype) |
2672 S_028C70_ENDIAN(endian);
2673 if (iview->image->samples > 1)
2674 if (iview->image->fmask.size)
2675 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2676
2677 if (iview->image->cmask.size &&
2678 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2679 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2680
2681 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2682 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2683
2684 if (device->physical_device->rad_info.chip_class >= VI) {
2685 unsigned max_uncompressed_block_size = 2;
2686 if (iview->image->samples > 1) {
2687 if (iview->image->surface.bpe == 1)
2688 max_uncompressed_block_size = 0;
2689 else if (iview->image->surface.bpe == 2)
2690 max_uncompressed_block_size = 1;
2691 }
2692
2693 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2694 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2695 }
2696
2697 /* This must be set for fast clear to work without FMASK. */
2698 if (!iview->image->fmask.size &&
2699 device->physical_device->rad_info.chip_class == SI) {
2700 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2701 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2702 }
2703 }
2704
2705 static void
2706 radv_initialise_ds_surface(struct radv_device *device,
2707 struct radv_ds_buffer_info *ds,
2708 struct radv_image_view *iview)
2709 {
2710 unsigned level = iview->base_mip;
2711 unsigned format;
2712 uint64_t va, s_offs, z_offs;
2713 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2714 memset(ds, 0, sizeof(*ds));
2715 switch (iview->vk_format) {
2716 case VK_FORMAT_D24_UNORM_S8_UINT:
2717 case VK_FORMAT_X8_D24_UNORM_PACK32:
2718 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2719 ds->offset_scale = 2.0f;
2720 break;
2721 case VK_FORMAT_D16_UNORM:
2722 case VK_FORMAT_D16_UNORM_S8_UINT:
2723 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2724 ds->offset_scale = 4.0f;
2725 break;
2726 case VK_FORMAT_D32_SFLOAT:
2727 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2728 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2729 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2730 ds->offset_scale = 1.0f;
2731 break;
2732 default:
2733 break;
2734 }
2735
2736 format = radv_translate_dbformat(iview->vk_format);
2737
2738 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2739 s_offs = z_offs = va;
2740 z_offs += iview->image->surface.level[level].offset;
2741 s_offs += iview->image->surface.stencil_level[level].offset;
2742
2743 uint32_t max_slice = radv_surface_layer_count(iview);
2744 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2745 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2746 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2747 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2748
2749 if (iview->image->samples > 1)
2750 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2751
2752 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2753 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2754 else
2755 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2756
2757 if (device->physical_device->rad_info.chip_class >= CIK) {
2758 struct radeon_info *info = &device->physical_device->rad_info;
2759 unsigned tiling_index = iview->image->surface.tiling_index[level];
2760 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2761 unsigned macro_index = iview->image->surface.macro_tile_index;
2762 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2763 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2764 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2765
2766 ds->db_depth_info |=
2767 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2768 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2769 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2770 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2771 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2772 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2773 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2774 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2775 } else {
2776 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2777 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2778 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2779 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2780 }
2781
2782 if (iview->image->surface.htile_size && !level) {
2783 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2784 S_028040_ALLOW_EXPCLEAR(1);
2785
2786 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2787 /* Workaround: For a not yet understood reason, the
2788 * combination of MSAA, fast stencil clear and stencil
2789 * decompress messes with subsequent stencil buffer
2790 * uses. Problem was reproduced on Verde, Bonaire,
2791 * Tonga, and Carrizo.
2792 *
2793 * Disabling EXPCLEAR works around the problem.
2794 *
2795 * Check piglit's arb_texture_multisample-stencil-clear
2796 * test if you want to try changing this.
2797 */
2798 if (iview->image->samples <= 1)
2799 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2800 } else
2801 /* Use all of the htile_buffer for depth if there's no stencil. */
2802 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2803
2804 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2805 iview->image->htile_offset;
2806 ds->db_htile_data_base = va >> 8;
2807 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2808 } else {
2809 ds->db_htile_data_base = 0;
2810 ds->db_htile_surface = 0;
2811 }
2812
2813 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2814 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2815
2816 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2817 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2818 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2819 }
2820
2821 VkResult radv_CreateFramebuffer(
2822 VkDevice _device,
2823 const VkFramebufferCreateInfo* pCreateInfo,
2824 const VkAllocationCallbacks* pAllocator,
2825 VkFramebuffer* pFramebuffer)
2826 {
2827 RADV_FROM_HANDLE(radv_device, device, _device);
2828 struct radv_framebuffer *framebuffer;
2829
2830 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2831
2832 size_t size = sizeof(*framebuffer) +
2833 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2834 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2835 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2836 if (framebuffer == NULL)
2837 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2838
2839 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2840 framebuffer->width = pCreateInfo->width;
2841 framebuffer->height = pCreateInfo->height;
2842 framebuffer->layers = pCreateInfo->layers;
2843 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2844 VkImageView _iview = pCreateInfo->pAttachments[i];
2845 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2846 framebuffer->attachments[i].attachment = iview;
2847 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2848 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2849 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2850 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2851 }
2852 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2853 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2854 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2855 }
2856
2857 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2858 return VK_SUCCESS;
2859 }
2860
2861 void radv_DestroyFramebuffer(
2862 VkDevice _device,
2863 VkFramebuffer _fb,
2864 const VkAllocationCallbacks* pAllocator)
2865 {
2866 RADV_FROM_HANDLE(radv_device, device, _device);
2867 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2868
2869 if (!fb)
2870 return;
2871 vk_free2(&device->alloc, pAllocator, fb);
2872 }
2873
2874 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2875 {
2876 switch (address_mode) {
2877 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2878 return V_008F30_SQ_TEX_WRAP;
2879 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2880 return V_008F30_SQ_TEX_MIRROR;
2881 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2882 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2883 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2884 return V_008F30_SQ_TEX_CLAMP_BORDER;
2885 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2886 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2887 default:
2888 unreachable("illegal tex wrap mode");
2889 break;
2890 }
2891 }
2892
2893 static unsigned
2894 radv_tex_compare(VkCompareOp op)
2895 {
2896 switch (op) {
2897 case VK_COMPARE_OP_NEVER:
2898 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2899 case VK_COMPARE_OP_LESS:
2900 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2901 case VK_COMPARE_OP_EQUAL:
2902 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2903 case VK_COMPARE_OP_LESS_OR_EQUAL:
2904 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2905 case VK_COMPARE_OP_GREATER:
2906 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2907 case VK_COMPARE_OP_NOT_EQUAL:
2908 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2909 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2910 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2911 case VK_COMPARE_OP_ALWAYS:
2912 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2913 default:
2914 unreachable("illegal compare mode");
2915 break;
2916 }
2917 }
2918
2919 static unsigned
2920 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2921 {
2922 switch (filter) {
2923 case VK_FILTER_NEAREST:
2924 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2925 V_008F38_SQ_TEX_XY_FILTER_POINT);
2926 case VK_FILTER_LINEAR:
2927 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2928 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2929 case VK_FILTER_CUBIC_IMG:
2930 default:
2931 fprintf(stderr, "illegal texture filter");
2932 return 0;
2933 }
2934 }
2935
2936 static unsigned
2937 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2938 {
2939 switch (mode) {
2940 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2941 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2942 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2943 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2944 default:
2945 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2946 }
2947 }
2948
2949 static unsigned
2950 radv_tex_bordercolor(VkBorderColor bcolor)
2951 {
2952 switch (bcolor) {
2953 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2954 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2955 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2956 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2957 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2958 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2959 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2960 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2961 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2962 default:
2963 break;
2964 }
2965 return 0;
2966 }
2967
2968 static unsigned
2969 radv_tex_aniso_filter(unsigned filter)
2970 {
2971 if (filter < 2)
2972 return 0;
2973 if (filter < 4)
2974 return 1;
2975 if (filter < 8)
2976 return 2;
2977 if (filter < 16)
2978 return 3;
2979 return 4;
2980 }
2981
2982 static void
2983 radv_init_sampler(struct radv_device *device,
2984 struct radv_sampler *sampler,
2985 const VkSamplerCreateInfo *pCreateInfo)
2986 {
2987 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2988 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2989 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2990 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2991
2992 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2993 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2994 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2995 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2996 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2997 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2998 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2999 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3000 S_008F30_DISABLE_CUBE_WRAP(0) |
3001 S_008F30_COMPAT_MODE(is_vi));
3002 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3003 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3004 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3005 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3006 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3007 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3008 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3009 S_008F38_MIP_POINT_PRECLAMP(0) |
3010 S_008F38_DISABLE_LSB_CEIL(1) |
3011 S_008F38_FILTER_PREC_FIX(1) |
3012 S_008F38_ANISO_OVERRIDE(is_vi));
3013 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3014 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3015 }
3016
3017 VkResult radv_CreateSampler(
3018 VkDevice _device,
3019 const VkSamplerCreateInfo* pCreateInfo,
3020 const VkAllocationCallbacks* pAllocator,
3021 VkSampler* pSampler)
3022 {
3023 RADV_FROM_HANDLE(radv_device, device, _device);
3024 struct radv_sampler *sampler;
3025
3026 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3027
3028 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3029 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3030 if (!sampler)
3031 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3032
3033 radv_init_sampler(device, sampler, pCreateInfo);
3034 *pSampler = radv_sampler_to_handle(sampler);
3035
3036 return VK_SUCCESS;
3037 }
3038
3039 void radv_DestroySampler(
3040 VkDevice _device,
3041 VkSampler _sampler,
3042 const VkAllocationCallbacks* pAllocator)
3043 {
3044 RADV_FROM_HANDLE(radv_device, device, _device);
3045 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3046
3047 if (!sampler)
3048 return;
3049 vk_free2(&device->alloc, pAllocator, sampler);
3050 }
3051
3052
3053 /* vk_icd.h does not declare this function, so we declare it here to
3054 * suppress Wmissing-prototypes.
3055 */
3056 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3057 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3058
3059 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3060 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3061 {
3062 /* For the full details on loader interface versioning, see
3063 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3064 * What follows is a condensed summary, to help you navigate the large and
3065 * confusing official doc.
3066 *
3067 * - Loader interface v0 is incompatible with later versions. We don't
3068 * support it.
3069 *
3070 * - In loader interface v1:
3071 * - The first ICD entrypoint called by the loader is
3072 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3073 * entrypoint.
3074 * - The ICD must statically expose no other Vulkan symbol unless it is
3075 * linked with -Bsymbolic.
3076 * - Each dispatchable Vulkan handle created by the ICD must be
3077 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3078 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3079 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3080 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3081 * such loader-managed surfaces.
3082 *
3083 * - Loader interface v2 differs from v1 in:
3084 * - The first ICD entrypoint called by the loader is
3085 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3086 * statically expose this entrypoint.
3087 *
3088 * - Loader interface v3 differs from v2 in:
3089 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3090 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3091 * because the loader no longer does so.
3092 */
3093 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3094 return VK_SUCCESS;
3095 }