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radv: Add support for icd loader interface v4.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
116 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
117 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
118 default: chip_string = "AMD RADV unknown"; break;
119 }
120
121 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
122 }
123
124 static uint64_t
125 radv_get_visible_vram_size(struct radv_physical_device *device)
126 {
127 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
128 }
129
130 static uint64_t
131 radv_get_vram_size(struct radv_physical_device *device)
132 {
133 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
134 }
135
136 static void
137 radv_physical_device_init_mem_types(struct radv_physical_device *device)
138 {
139 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
140 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
141 uint64_t vram_size = radv_get_vram_size(device);
142 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
143 device->memory_properties.memoryHeapCount = 0;
144 if (vram_size > 0) {
145 vram_index = device->memory_properties.memoryHeapCount++;
146 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
147 .size = vram_size,
148 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
149 };
150 }
151 if (visible_vram_size) {
152 visible_vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
154 .size = visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (device->rad_info.gart_size > 0) {
159 gart_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
161 .size = device->rad_info.gart_size,
162 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165
166 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
167 unsigned type_count = 0;
168 if (vram_index >= 0) {
169 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
170 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
171 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
172 .heapIndex = vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
197 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
198 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
199 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
200 .heapIndex = gart_index,
201 };
202 }
203 device->memory_properties.memoryTypeCount = type_count;
204 }
205
206 static void
207 radv_handle_env_var_force_family(struct radv_physical_device *device)
208 {
209 const char *family = getenv("RADV_FORCE_FAMILY");
210 unsigned i;
211
212 if (!family)
213 return;
214
215 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
216 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
217 /* Override family and chip_class. */
218 device->rad_info.family = i;
219
220 if (i >= CHIP_VEGA10)
221 device->rad_info.chip_class = GFX9;
222 else if (i >= CHIP_TONGA)
223 device->rad_info.chip_class = VI;
224 else if (i >= CHIP_BONAIRE)
225 device->rad_info.chip_class = CIK;
226 else
227 device->rad_info.chip_class = SI;
228
229 return;
230 }
231 }
232
233 fprintf(stderr, "radv: Unknown family: %s\n", family);
234 exit(1);
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246 int master_fd = -1;
247
248 fd = open(path, O_RDWR | O_CLOEXEC);
249 if (fd < 0) {
250 if (instance->debug_flags & RADV_DEBUG_STARTUP)
251 radv_logi("Could not open device '%s'", path);
252
253 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
254 }
255
256 version = drmGetVersion(fd);
257 if (!version) {
258 close(fd);
259
260 if (instance->debug_flags & RADV_DEBUG_STARTUP)
261 radv_logi("Could not get the kernel driver version for device '%s'", path);
262
263 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
264 "failed to get version %s: %m", path);
265 }
266
267 if (strcmp(version->name, "amdgpu")) {
268 drmFreeVersion(version);
269 close(fd);
270
271 if (instance->debug_flags & RADV_DEBUG_STARTUP)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
273
274 return VK_ERROR_INCOMPATIBLE_DRIVER;
275 }
276 drmFreeVersion(version);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Found compatible device '%s'.", path);
280
281 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
282 device->instance = instance;
283
284 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
285 instance->perftest_flags);
286 if (!device->ws) {
287 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 goto fail;
289 }
290
291 if (instance->enabled_extensions.KHR_display) {
292 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
293 if (master_fd >= 0) {
294 uint32_t accel_working = 0;
295 struct drm_amdgpu_info request = {
296 .return_pointer = (uintptr_t)&accel_working,
297 .return_size = sizeof(accel_working),
298 .query = AMDGPU_INFO_ACCEL_WORKING
299 };
300
301 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
302 close(master_fd);
303 master_fd = -1;
304 }
305 }
306 }
307
308 device->master_fd = master_fd;
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311
312 radv_handle_env_var_force_family(device);
313
314 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
315
316 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
317 device->ws->destroy(device->ws);
318 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
319 "cannot generate UUID");
320 goto fail;
321 }
322
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags =
325 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
326 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
327
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
330 */
331 char buf[VK_UUID_SIZE * 2 + 1];
332 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
333 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
334
335 if (device->rad_info.chip_class < VI ||
336 device->rad_info.chip_class > GFX9)
337 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338
339 radv_get_driver_uuid(&device->driver_uuid);
340 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
341
342 if (device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.chip_class >= GFX9) {
344 device->has_rbplus = true;
345 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.family == CHIP_VEGA12 ||
347 device->rad_info.family == CHIP_RAVEN ||
348 device->rad_info.family == CHIP_RAVEN2;
349 }
350
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 * on SI.
353 */
354 device->has_clear_state = device->rad_info.chip_class >= CIK;
355
356 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
357
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
360 device->rad_info.family == CHIP_RAVEN;
361
362 /* Out-of-order primitive rasterization. */
363 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
364 device->rad_info.max_se >= 2;
365 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
366 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
367
368 device->dcc_msaa_allowed =
369 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
370
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
372 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
373 (device->rad_info.chip_class >= VI &&
374 device->rad_info.me_fw_feature >= 41);
375
376 radv_physical_device_init_mem_types(device);
377 radv_fill_device_extension_table(device, &device->supported_extensions);
378
379 device->bus_info = *drm_device->businfo.pci;
380
381 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
382 ac_print_gpu_info(&device->rad_info);
383
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
386 * semi-layers).
387 */
388 result = radv_init_wsi(device);
389 if (result != VK_SUCCESS) {
390 device->ws->destroy(device->ws);
391 vk_error(instance, result);
392 goto fail;
393 }
394
395 return VK_SUCCESS;
396
397 fail:
398 close(fd);
399 if (master_fd != -1)
400 close(master_fd);
401 return result;
402 }
403
404 static void
405 radv_physical_device_finish(struct radv_physical_device *device)
406 {
407 radv_finish_wsi(device);
408 device->ws->destroy(device->ws);
409 disk_cache_destroy(device->disk_cache);
410 close(device->local_fd);
411 if (device->master_fd != -1)
412 close(device->master_fd);
413 }
414
415 static void *
416 default_alloc_func(void *pUserData, size_t size, size_t align,
417 VkSystemAllocationScope allocationScope)
418 {
419 return malloc(size);
420 }
421
422 static void *
423 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
424 size_t align, VkSystemAllocationScope allocationScope)
425 {
426 return realloc(pOriginal, size);
427 }
428
429 static void
430 default_free_func(void *pUserData, void *pMemory)
431 {
432 free(pMemory);
433 }
434
435 static const VkAllocationCallbacks default_alloc = {
436 .pUserData = NULL,
437 .pfnAllocation = default_alloc_func,
438 .pfnReallocation = default_realloc_func,
439 .pfnFree = default_free_func,
440 };
441
442 static const struct debug_control radv_debug_options[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
444 {"nodcc", RADV_DEBUG_NO_DCC},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS},
446 {"nocache", RADV_DEBUG_NO_CACHE},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
448 {"nohiz", RADV_DEBUG_NO_HIZ},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
451 {"allbos", RADV_DEBUG_ALL_BOS},
452 {"noibs", RADV_DEBUG_NO_IBS},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
457 {"nosisched", RADV_DEBUG_NO_SISCHED},
458 {"preoptir", RADV_DEBUG_PREOPTIR},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
461 {"info", RADV_DEBUG_INFO},
462 {"errors", RADV_DEBUG_ERRORS},
463 {"startup", RADV_DEBUG_STARTUP},
464 {"checkir", RADV_DEBUG_CHECKIR},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
466 {"nobinning", RADV_DEBUG_NOBINNING},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
482 {"bolist", RADV_PERFTEST_BO_LIST},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525 static const char radv_dri_options_xml[] =
526 DRI_CONF_BEGIN
527 DRI_CONF_SECTION_QUALITY
528 DRI_CONF_ADAPTIVE_SYNC("true")
529 DRI_CONF_SECTION_END
530 DRI_CONF_END;
531
532 static void radv_init_dri_options(struct radv_instance *instance)
533 {
534 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
535 driParseConfigFiles(&instance->dri_options,
536 &instance->available_dri_options,
537 0, "radv", NULL);
538 }
539
540 VkResult radv_CreateInstance(
541 const VkInstanceCreateInfo* pCreateInfo,
542 const VkAllocationCallbacks* pAllocator,
543 VkInstance* pInstance)
544 {
545 struct radv_instance *instance;
546 VkResult result;
547
548 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
549
550 uint32_t client_version;
551 if (pCreateInfo->pApplicationInfo &&
552 pCreateInfo->pApplicationInfo->apiVersion != 0) {
553 client_version = pCreateInfo->pApplicationInfo->apiVersion;
554 } else {
555 client_version = VK_API_VERSION_1_0;
556 }
557
558 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
559 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
560 if (!instance)
561 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
562
563 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
564
565 if (pAllocator)
566 instance->alloc = *pAllocator;
567 else
568 instance->alloc = default_alloc;
569
570 instance->apiVersion = client_version;
571 instance->physicalDeviceCount = -1;
572
573 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
574 radv_debug_options);
575
576 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
577 radv_perftest_options);
578
579
580 if (instance->debug_flags & RADV_DEBUG_STARTUP)
581 radv_logi("Created an instance");
582
583 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
584 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
585 int index = radv_get_instance_extension_index(ext_name);
586
587 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
588 vk_free2(&default_alloc, pAllocator, instance);
589 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
590 }
591
592 instance->enabled_extensions.extensions[index] = true;
593 }
594
595 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
596 if (result != VK_SUCCESS) {
597 vk_free2(&default_alloc, pAllocator, instance);
598 return vk_error(instance, result);
599 }
600
601 _mesa_locale_init();
602 glsl_type_singleton_init_or_ref();
603
604 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
605
606 radv_init_dri_options(instance);
607 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
608
609 *pInstance = radv_instance_to_handle(instance);
610
611 return VK_SUCCESS;
612 }
613
614 void radv_DestroyInstance(
615 VkInstance _instance,
616 const VkAllocationCallbacks* pAllocator)
617 {
618 RADV_FROM_HANDLE(radv_instance, instance, _instance);
619
620 if (!instance)
621 return;
622
623 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
624 radv_physical_device_finish(instance->physicalDevices + i);
625 }
626
627 VG(VALGRIND_DESTROY_MEMPOOL(instance));
628
629 glsl_type_singleton_decref();
630 _mesa_locale_fini();
631
632 driDestroyOptionCache(&instance->dri_options);
633 driDestroyOptionInfo(&instance->available_dri_options);
634
635 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
636
637 vk_free(&instance->alloc, instance);
638 }
639
640 static VkResult
641 radv_enumerate_devices(struct radv_instance *instance)
642 {
643 /* TODO: Check for more devices ? */
644 drmDevicePtr devices[8];
645 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
646 int max_devices;
647
648 instance->physicalDeviceCount = 0;
649
650 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
651
652 if (instance->debug_flags & RADV_DEBUG_STARTUP)
653 radv_logi("Found %d drm nodes", max_devices);
654
655 if (max_devices < 1)
656 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
657
658 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
659 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
660 devices[i]->bustype == DRM_BUS_PCI &&
661 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
662
663 result = radv_physical_device_init(instance->physicalDevices +
664 instance->physicalDeviceCount,
665 instance,
666 devices[i]);
667 if (result == VK_SUCCESS)
668 ++instance->physicalDeviceCount;
669 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 break;
671 }
672 }
673 drmFreeDevices(devices, max_devices);
674
675 return result;
676 }
677
678 VkResult radv_EnumeratePhysicalDevices(
679 VkInstance _instance,
680 uint32_t* pPhysicalDeviceCount,
681 VkPhysicalDevice* pPhysicalDevices)
682 {
683 RADV_FROM_HANDLE(radv_instance, instance, _instance);
684 VkResult result;
685
686 if (instance->physicalDeviceCount < 0) {
687 result = radv_enumerate_devices(instance);
688 if (result != VK_SUCCESS &&
689 result != VK_ERROR_INCOMPATIBLE_DRIVER)
690 return result;
691 }
692
693 if (!pPhysicalDevices) {
694 *pPhysicalDeviceCount = instance->physicalDeviceCount;
695 } else {
696 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
697 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
698 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
699 }
700
701 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
702 : VK_SUCCESS;
703 }
704
705 VkResult radv_EnumeratePhysicalDeviceGroups(
706 VkInstance _instance,
707 uint32_t* pPhysicalDeviceGroupCount,
708 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
709 {
710 RADV_FROM_HANDLE(radv_instance, instance, _instance);
711 VkResult result;
712
713 if (instance->physicalDeviceCount < 0) {
714 result = radv_enumerate_devices(instance);
715 if (result != VK_SUCCESS &&
716 result != VK_ERROR_INCOMPATIBLE_DRIVER)
717 return result;
718 }
719
720 if (!pPhysicalDeviceGroupProperties) {
721 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
722 } else {
723 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
724 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
725 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
726 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
727 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
728 }
729 }
730 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
731 : VK_SUCCESS;
732 }
733
734 void radv_GetPhysicalDeviceFeatures(
735 VkPhysicalDevice physicalDevice,
736 VkPhysicalDeviceFeatures* pFeatures)
737 {
738 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
739 memset(pFeatures, 0, sizeof(*pFeatures));
740
741 *pFeatures = (VkPhysicalDeviceFeatures) {
742 .robustBufferAccess = true,
743 .fullDrawIndexUint32 = true,
744 .imageCubeArray = true,
745 .independentBlend = true,
746 .geometryShader = true,
747 .tessellationShader = true,
748 .sampleRateShading = true,
749 .dualSrcBlend = true,
750 .logicOp = true,
751 .multiDrawIndirect = true,
752 .drawIndirectFirstInstance = true,
753 .depthClamp = true,
754 .depthBiasClamp = true,
755 .fillModeNonSolid = true,
756 .depthBounds = true,
757 .wideLines = true,
758 .largePoints = true,
759 .alphaToOne = true,
760 .multiViewport = true,
761 .samplerAnisotropy = true,
762 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
763 .textureCompressionASTC_LDR = false,
764 .textureCompressionBC = true,
765 .occlusionQueryPrecise = true,
766 .pipelineStatisticsQuery = true,
767 .vertexPipelineStoresAndAtomics = true,
768 .fragmentStoresAndAtomics = true,
769 .shaderTessellationAndGeometryPointSize = true,
770 .shaderImageGatherExtended = true,
771 .shaderStorageImageExtendedFormats = true,
772 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
773 .shaderUniformBufferArrayDynamicIndexing = true,
774 .shaderSampledImageArrayDynamicIndexing = true,
775 .shaderStorageBufferArrayDynamicIndexing = true,
776 .shaderStorageImageArrayDynamicIndexing = true,
777 .shaderStorageImageReadWithoutFormat = true,
778 .shaderStorageImageWriteWithoutFormat = true,
779 .shaderClipDistance = true,
780 .shaderCullDistance = true,
781 .shaderFloat64 = true,
782 .shaderInt64 = true,
783 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
784 .sparseBinding = true,
785 .variableMultisampleRate = true,
786 .inheritedQueries = true,
787 };
788 }
789
790 void radv_GetPhysicalDeviceFeatures2(
791 VkPhysicalDevice physicalDevice,
792 VkPhysicalDeviceFeatures2 *pFeatures)
793 {
794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
795 vk_foreach_struct(ext, pFeatures->pNext) {
796 switch (ext->sType) {
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
798 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
799 features->variablePointersStorageBuffer = true;
800 features->variablePointers = true;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
804 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
805 features->multiview = true;
806 features->multiviewGeometryShader = true;
807 features->multiviewTessellationShader = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
811 VkPhysicalDeviceShaderDrawParametersFeatures *features =
812 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
813 features->shaderDrawParameters = true;
814 break;
815 }
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
817 VkPhysicalDeviceProtectedMemoryFeatures *features =
818 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
819 features->protectedMemory = false;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
823 VkPhysicalDevice16BitStorageFeatures *features =
824 (VkPhysicalDevice16BitStorageFeatures*)ext;
825 bool enabled = pdevice->rad_info.chip_class >= VI;
826 features->storageBuffer16BitAccess = enabled;
827 features->uniformAndStorageBuffer16BitAccess = enabled;
828 features->storagePushConstant16 = enabled;
829 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
833 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
834 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
835 features->samplerYcbcrConversion = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
839 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
840 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
841 features->shaderInputAttachmentArrayDynamicIndexing = true;
842 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
843 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
844 features->shaderUniformBufferArrayNonUniformIndexing = true;
845 features->shaderSampledImageArrayNonUniformIndexing = true;
846 features->shaderStorageBufferArrayNonUniformIndexing = true;
847 features->shaderStorageImageArrayNonUniformIndexing = true;
848 features->shaderInputAttachmentArrayNonUniformIndexing = true;
849 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
850 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
851 features->descriptorBindingUniformBufferUpdateAfterBind = true;
852 features->descriptorBindingSampledImageUpdateAfterBind = true;
853 features->descriptorBindingStorageImageUpdateAfterBind = true;
854 features->descriptorBindingStorageBufferUpdateAfterBind = true;
855 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
856 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
857 features->descriptorBindingUpdateUnusedWhilePending = true;
858 features->descriptorBindingPartiallyBound = true;
859 features->descriptorBindingVariableDescriptorCount = true;
860 features->runtimeDescriptorArray = true;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
864 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
865 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
866 features->conditionalRendering = true;
867 features->inheritedConditionalRendering = false;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
871 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
872 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
873 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
874 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
878 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
879 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
880 features->transformFeedback = true;
881 features->geometryStreams = true;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
885 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
886 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
887 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
891 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
892 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
893 features->memoryPriority = VK_TRUE;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
897 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
898 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
899 features->bufferDeviceAddress = true;
900 features->bufferDeviceAddressCaptureReplay = false;
901 features->bufferDeviceAddressMultiDevice = false;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
905 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
906 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
907 features->depthClipEnable = true;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
911 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
912 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
913 features->hostQueryReset = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
917 VkPhysicalDevice8BitStorageFeaturesKHR *features =
918 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
919 bool enabled = pdevice->rad_info.chip_class >= VI;
920 features->storageBuffer8BitAccess = enabled;
921 features->uniformAndStorageBuffer8BitAccess = enabled;
922 features->storagePushConstant8 = enabled;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
926 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
927 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
928 features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800;
929 features->shaderInt8 = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
933 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
934 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
935 /* TODO: Enable this once the driver supports 64-bit
936 * compare&swap atomic operations.
937 */
938 features->shaderBufferInt64Atomics = false;
939 features->shaderSharedInt64Atomics = false;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
943 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
944 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
945
946 features->inlineUniformBlock = true;
947 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
948 break;
949 }
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
951 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
952 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
953 features->computeDerivativeGroupQuads = false;
954 features->computeDerivativeGroupLinear = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
958 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
959 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
960 features->ycbcrImageArrays = true;
961 break;
962 }
963 default:
964 break;
965 }
966 }
967 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
968 }
969
970 void radv_GetPhysicalDeviceProperties(
971 VkPhysicalDevice physicalDevice,
972 VkPhysicalDeviceProperties* pProperties)
973 {
974 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
975 VkSampleCountFlags sample_counts = 0xf;
976
977 /* make sure that the entire descriptor set is addressable with a signed
978 * 32-bit int. So the sum of all limits scaled by descriptor size has to
979 * be at most 2 GiB. the combined image & samples object count as one of
980 * both. This limit is for the pipeline layout, not for the set layout, but
981 * there is no set limit, so we just set a pipeline limit. I don't think
982 * any app is going to hit this soon. */
983 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
984 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
985 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
986 32 /* sampler, largest when combined with image */ +
987 64 /* sampled image */ +
988 64 /* storage image */);
989
990 VkPhysicalDeviceLimits limits = {
991 .maxImageDimension1D = (1 << 14),
992 .maxImageDimension2D = (1 << 14),
993 .maxImageDimension3D = (1 << 11),
994 .maxImageDimensionCube = (1 << 14),
995 .maxImageArrayLayers = (1 << 11),
996 .maxTexelBufferElements = 128 * 1024 * 1024,
997 .maxUniformBufferRange = UINT32_MAX,
998 .maxStorageBufferRange = UINT32_MAX,
999 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1000 .maxMemoryAllocationCount = UINT32_MAX,
1001 .maxSamplerAllocationCount = 64 * 1024,
1002 .bufferImageGranularity = 64, /* A cache line */
1003 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1004 .maxBoundDescriptorSets = MAX_SETS,
1005 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1006 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1007 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1008 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1009 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1010 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1011 .maxPerStageResources = max_descriptor_set_size,
1012 .maxDescriptorSetSamplers = max_descriptor_set_size,
1013 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1014 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1015 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1016 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1017 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1018 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1019 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1020 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1021 .maxVertexInputBindings = MAX_VBS,
1022 .maxVertexInputAttributeOffset = 2047,
1023 .maxVertexInputBindingStride = 2048,
1024 .maxVertexOutputComponents = 128,
1025 .maxTessellationGenerationLevel = 64,
1026 .maxTessellationPatchSize = 32,
1027 .maxTessellationControlPerVertexInputComponents = 128,
1028 .maxTessellationControlPerVertexOutputComponents = 128,
1029 .maxTessellationControlPerPatchOutputComponents = 120,
1030 .maxTessellationControlTotalOutputComponents = 4096,
1031 .maxTessellationEvaluationInputComponents = 128,
1032 .maxTessellationEvaluationOutputComponents = 128,
1033 .maxGeometryShaderInvocations = 127,
1034 .maxGeometryInputComponents = 64,
1035 .maxGeometryOutputComponents = 128,
1036 .maxGeometryOutputVertices = 256,
1037 .maxGeometryTotalOutputComponents = 1024,
1038 .maxFragmentInputComponents = 128,
1039 .maxFragmentOutputAttachments = 8,
1040 .maxFragmentDualSrcAttachments = 1,
1041 .maxFragmentCombinedOutputResources = 8,
1042 .maxComputeSharedMemorySize = 32768,
1043 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1044 .maxComputeWorkGroupInvocations = 2048,
1045 .maxComputeWorkGroupSize = {
1046 2048,
1047 2048,
1048 2048
1049 },
1050 .subPixelPrecisionBits = 8,
1051 .subTexelPrecisionBits = 8,
1052 .mipmapPrecisionBits = 8,
1053 .maxDrawIndexedIndexValue = UINT32_MAX,
1054 .maxDrawIndirectCount = UINT32_MAX,
1055 .maxSamplerLodBias = 16,
1056 .maxSamplerAnisotropy = 16,
1057 .maxViewports = MAX_VIEWPORTS,
1058 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1059 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1060 .viewportSubPixelBits = 8,
1061 .minMemoryMapAlignment = 4096, /* A page */
1062 .minTexelBufferOffsetAlignment = 1,
1063 .minUniformBufferOffsetAlignment = 4,
1064 .minStorageBufferOffsetAlignment = 4,
1065 .minTexelOffset = -32,
1066 .maxTexelOffset = 31,
1067 .minTexelGatherOffset = -32,
1068 .maxTexelGatherOffset = 31,
1069 .minInterpolationOffset = -2,
1070 .maxInterpolationOffset = 2,
1071 .subPixelInterpolationOffsetBits = 8,
1072 .maxFramebufferWidth = (1 << 14),
1073 .maxFramebufferHeight = (1 << 14),
1074 .maxFramebufferLayers = (1 << 10),
1075 .framebufferColorSampleCounts = sample_counts,
1076 .framebufferDepthSampleCounts = sample_counts,
1077 .framebufferStencilSampleCounts = sample_counts,
1078 .framebufferNoAttachmentsSampleCounts = sample_counts,
1079 .maxColorAttachments = MAX_RTS,
1080 .sampledImageColorSampleCounts = sample_counts,
1081 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1082 .sampledImageDepthSampleCounts = sample_counts,
1083 .sampledImageStencilSampleCounts = sample_counts,
1084 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1085 .maxSampleMaskWords = 1,
1086 .timestampComputeAndGraphics = true,
1087 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1088 .maxClipDistances = 8,
1089 .maxCullDistances = 8,
1090 .maxCombinedClipAndCullDistances = 8,
1091 .discreteQueuePriorities = 2,
1092 .pointSizeRange = { 0.0, 8192.0 },
1093 .lineWidthRange = { 0.0, 7.9921875 },
1094 .pointSizeGranularity = (1.0 / 8.0),
1095 .lineWidthGranularity = (1.0 / 128.0),
1096 .strictLines = false, /* FINISHME */
1097 .standardSampleLocations = true,
1098 .optimalBufferCopyOffsetAlignment = 128,
1099 .optimalBufferCopyRowPitchAlignment = 128,
1100 .nonCoherentAtomSize = 64,
1101 };
1102
1103 *pProperties = (VkPhysicalDeviceProperties) {
1104 .apiVersion = radv_physical_device_api_version(pdevice),
1105 .driverVersion = vk_get_driver_version(),
1106 .vendorID = ATI_VENDOR_ID,
1107 .deviceID = pdevice->rad_info.pci_id,
1108 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1109 .limits = limits,
1110 .sparseProperties = {0},
1111 };
1112
1113 strcpy(pProperties->deviceName, pdevice->name);
1114 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1115 }
1116
1117 void radv_GetPhysicalDeviceProperties2(
1118 VkPhysicalDevice physicalDevice,
1119 VkPhysicalDeviceProperties2 *pProperties)
1120 {
1121 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1122 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1123
1124 vk_foreach_struct(ext, pProperties->pNext) {
1125 switch (ext->sType) {
1126 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1127 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1128 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1129 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1133 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1134 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1135 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1136 properties->deviceLUIDValid = false;
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1140 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1141 properties->maxMultiviewViewCount = MAX_VIEWS;
1142 properties->maxMultiviewInstanceIndex = INT_MAX;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1146 VkPhysicalDevicePointClippingProperties *properties =
1147 (VkPhysicalDevicePointClippingProperties*)ext;
1148 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1152 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1153 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1154 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1158 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1159 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1160 properties->minImportedHostPointerAlignment = 4096;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1164 VkPhysicalDeviceSubgroupProperties *properties =
1165 (VkPhysicalDeviceSubgroupProperties*)ext;
1166 properties->subgroupSize = 64;
1167 properties->supportedStages = VK_SHADER_STAGE_ALL;
1168 properties->supportedOperations =
1169 VK_SUBGROUP_FEATURE_BASIC_BIT |
1170 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1171 VK_SUBGROUP_FEATURE_QUAD_BIT |
1172 VK_SUBGROUP_FEATURE_VOTE_BIT;
1173 if (pdevice->rad_info.chip_class >= VI) {
1174 properties->supportedOperations |=
1175 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1176 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1177 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1178 }
1179 properties->quadOperationsInAllStages = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1183 VkPhysicalDeviceMaintenance3Properties *properties =
1184 (VkPhysicalDeviceMaintenance3Properties*)ext;
1185 /* Make sure everything is addressable by a signed 32-bit int, and
1186 * our largest descriptors are 96 bytes. */
1187 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1188 /* Our buffer size fields allow only this much */
1189 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1190 break;
1191 }
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1193 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1194 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1195 /* GFX6-8 only support single channel min/max filter. */
1196 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1197 properties->filterMinmaxSingleComponentFormats = true;
1198 break;
1199 }
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1201 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1202 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1203
1204 /* Shader engines. */
1205 properties->shaderEngineCount =
1206 pdevice->rad_info.max_se;
1207 properties->shaderArraysPerEngineCount =
1208 pdevice->rad_info.max_sh_per_se;
1209 properties->computeUnitsPerShaderArray =
1210 pdevice->rad_info.num_good_cu_per_sh;
1211 properties->simdPerComputeUnit = 4;
1212 properties->wavefrontsPerSimd =
1213 pdevice->rad_info.family == CHIP_TONGA ||
1214 pdevice->rad_info.family == CHIP_ICELAND ||
1215 pdevice->rad_info.family == CHIP_POLARIS10 ||
1216 pdevice->rad_info.family == CHIP_POLARIS11 ||
1217 pdevice->rad_info.family == CHIP_POLARIS12 ||
1218 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1219 properties->wavefrontSize = 64;
1220
1221 /* SGPR. */
1222 properties->sgprsPerSimd =
1223 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1224 properties->minSgprAllocation =
1225 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1226 properties->maxSgprAllocation =
1227 pdevice->rad_info.family == CHIP_TONGA ||
1228 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1229 properties->sgprAllocationGranularity =
1230 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1231
1232 /* VGPR. */
1233 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1234 properties->minVgprAllocation = 4;
1235 properties->maxVgprAllocation = 256;
1236 properties->vgprAllocationGranularity = 4;
1237 break;
1238 }
1239 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1240 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1241 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1242 properties->maxVertexAttribDivisor = UINT32_MAX;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1246 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1247 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1248 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1249 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1250 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1251 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1252 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1253 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1254 properties->robustBufferAccessUpdateAfterBind = false;
1255 properties->quadDivergentImplicitLod = false;
1256
1257 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1258 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1259 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1260 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1261 32 /* sampler, largest when combined with image */ +
1262 64 /* sampled image */ +
1263 64 /* storage image */);
1264 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1265 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1266 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1267 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1268 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1269 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1270 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1271 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1272 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1273 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1274 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1275 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1276 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1277 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1278 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1279 break;
1280 }
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1282 VkPhysicalDeviceProtectedMemoryProperties *properties =
1283 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1284 properties->protectedNoFault = false;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1288 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1289 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1290 properties->primitiveOverestimationSize = 0;
1291 properties->maxExtraPrimitiveOverestimationSize = 0;
1292 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1293 properties->primitiveUnderestimation = VK_FALSE;
1294 properties->conservativePointAndLineRasterization = VK_FALSE;
1295 properties->degenerateTrianglesRasterized = VK_FALSE;
1296 properties->degenerateLinesRasterized = VK_FALSE;
1297 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1298 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1302 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1303 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1304 properties->pciDomain = pdevice->bus_info.domain;
1305 properties->pciBus = pdevice->bus_info.bus;
1306 properties->pciDevice = pdevice->bus_info.dev;
1307 properties->pciFunction = pdevice->bus_info.func;
1308 break;
1309 }
1310 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1311 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1312 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1313
1314 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1315 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1316 strcpy(driver_props->driverName, "radv");
1317
1318 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1319 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1320 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1321 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1322
1323 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1324 .major = 1,
1325 .minor = 1,
1326 .subminor = 2,
1327 .patch = 0,
1328 };
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1332 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1333 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1334 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1335 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1336 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1337 properties->maxTransformFeedbackStreamDataSize = 512;
1338 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1339 properties->maxTransformFeedbackBufferDataStride = 512;
1340 properties->transformFeedbackQueries = true;
1341 properties->transformFeedbackStreamsLinesTriangles = false;
1342 properties->transformFeedbackRasterizationStreamSelect = false;
1343 properties->transformFeedbackDraw = true;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1347 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1348 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1349
1350 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1351 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1352 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1353 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1354 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1355 break;
1356 }
1357 default:
1358 break;
1359 }
1360 }
1361 }
1362
1363 static void radv_get_physical_device_queue_family_properties(
1364 struct radv_physical_device* pdevice,
1365 uint32_t* pCount,
1366 VkQueueFamilyProperties** pQueueFamilyProperties)
1367 {
1368 int num_queue_families = 1;
1369 int idx;
1370 if (pdevice->rad_info.num_compute_rings > 0 &&
1371 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1372 num_queue_families++;
1373
1374 if (pQueueFamilyProperties == NULL) {
1375 *pCount = num_queue_families;
1376 return;
1377 }
1378
1379 if (!*pCount)
1380 return;
1381
1382 idx = 0;
1383 if (*pCount >= 1) {
1384 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1385 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1386 VK_QUEUE_COMPUTE_BIT |
1387 VK_QUEUE_TRANSFER_BIT |
1388 VK_QUEUE_SPARSE_BINDING_BIT,
1389 .queueCount = 1,
1390 .timestampValidBits = 64,
1391 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1392 };
1393 idx++;
1394 }
1395
1396 if (pdevice->rad_info.num_compute_rings > 0 &&
1397 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1398 if (*pCount > idx) {
1399 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1400 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1401 VK_QUEUE_TRANSFER_BIT |
1402 VK_QUEUE_SPARSE_BINDING_BIT,
1403 .queueCount = pdevice->rad_info.num_compute_rings,
1404 .timestampValidBits = 64,
1405 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1406 };
1407 idx++;
1408 }
1409 }
1410 *pCount = idx;
1411 }
1412
1413 void radv_GetPhysicalDeviceQueueFamilyProperties(
1414 VkPhysicalDevice physicalDevice,
1415 uint32_t* pCount,
1416 VkQueueFamilyProperties* pQueueFamilyProperties)
1417 {
1418 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1419 if (!pQueueFamilyProperties) {
1420 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1421 return;
1422 }
1423 VkQueueFamilyProperties *properties[] = {
1424 pQueueFamilyProperties + 0,
1425 pQueueFamilyProperties + 1,
1426 pQueueFamilyProperties + 2,
1427 };
1428 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1429 assert(*pCount <= 3);
1430 }
1431
1432 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1433 VkPhysicalDevice physicalDevice,
1434 uint32_t* pCount,
1435 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1436 {
1437 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1438 if (!pQueueFamilyProperties) {
1439 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1440 return;
1441 }
1442 VkQueueFamilyProperties *properties[] = {
1443 &pQueueFamilyProperties[0].queueFamilyProperties,
1444 &pQueueFamilyProperties[1].queueFamilyProperties,
1445 &pQueueFamilyProperties[2].queueFamilyProperties,
1446 };
1447 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1448 assert(*pCount <= 3);
1449 }
1450
1451 void radv_GetPhysicalDeviceMemoryProperties(
1452 VkPhysicalDevice physicalDevice,
1453 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1454 {
1455 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1456
1457 *pMemoryProperties = physical_device->memory_properties;
1458 }
1459
1460 static void
1461 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1462 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1463 {
1464 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1465 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1466 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1467 uint64_t vram_size = radv_get_vram_size(device);
1468 uint64_t gtt_size = device->rad_info.gart_size;
1469 uint64_t heap_budget, heap_usage;
1470
1471 /* For all memory heaps, the computation of budget is as follow:
1472 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1473 *
1474 * The Vulkan spec 1.1.97 says that the budget should include any
1475 * currently allocated device memory.
1476 *
1477 * Note that the application heap usages are not really accurate (eg.
1478 * in presence of shared buffers).
1479 */
1480 if (vram_size) {
1481 heap_usage = device->ws->query_value(device->ws,
1482 RADEON_ALLOCATED_VRAM);
1483
1484 heap_budget = vram_size -
1485 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1486 heap_usage;
1487
1488 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1489 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1490 }
1491
1492 if (visible_vram_size) {
1493 heap_usage = device->ws->query_value(device->ws,
1494 RADEON_ALLOCATED_VRAM_VIS);
1495
1496 heap_budget = visible_vram_size -
1497 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1498 heap_usage;
1499
1500 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1501 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1502 }
1503
1504 if (gtt_size) {
1505 heap_usage = device->ws->query_value(device->ws,
1506 RADEON_ALLOCATED_GTT);
1507
1508 heap_budget = gtt_size -
1509 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1510 heap_usage;
1511
1512 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1513 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1514 }
1515
1516 /* The heapBudget and heapUsage values must be zero for array elements
1517 * greater than or equal to
1518 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1519 */
1520 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1521 memoryBudget->heapBudget[i] = 0;
1522 memoryBudget->heapUsage[i] = 0;
1523 }
1524 }
1525
1526 void radv_GetPhysicalDeviceMemoryProperties2(
1527 VkPhysicalDevice physicalDevice,
1528 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1529 {
1530 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1531 &pMemoryProperties->memoryProperties);
1532
1533 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1534 vk_find_struct(pMemoryProperties->pNext,
1535 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1536 if (memory_budget)
1537 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1538 }
1539
1540 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1541 VkDevice _device,
1542 VkExternalMemoryHandleTypeFlagBits handleType,
1543 const void *pHostPointer,
1544 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1545 {
1546 RADV_FROM_HANDLE(radv_device, device, _device);
1547
1548 switch (handleType)
1549 {
1550 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1551 const struct radv_physical_device *physical_device = device->physical_device;
1552 uint32_t memoryTypeBits = 0;
1553 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1554 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1555 memoryTypeBits = (1 << i);
1556 break;
1557 }
1558 }
1559 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1560 return VK_SUCCESS;
1561 }
1562 default:
1563 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1564 }
1565 }
1566
1567 static enum radeon_ctx_priority
1568 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1569 {
1570 /* Default to MEDIUM when a specific global priority isn't requested */
1571 if (!pObj)
1572 return RADEON_CTX_PRIORITY_MEDIUM;
1573
1574 switch(pObj->globalPriority) {
1575 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1576 return RADEON_CTX_PRIORITY_REALTIME;
1577 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1578 return RADEON_CTX_PRIORITY_HIGH;
1579 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1580 return RADEON_CTX_PRIORITY_MEDIUM;
1581 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1582 return RADEON_CTX_PRIORITY_LOW;
1583 default:
1584 unreachable("Illegal global priority value");
1585 return RADEON_CTX_PRIORITY_INVALID;
1586 }
1587 }
1588
1589 static int
1590 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1591 uint32_t queue_family_index, int idx,
1592 VkDeviceQueueCreateFlags flags,
1593 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1594 {
1595 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1596 queue->device = device;
1597 queue->queue_family_index = queue_family_index;
1598 queue->queue_idx = idx;
1599 queue->priority = radv_get_queue_global_priority(global_priority);
1600 queue->flags = flags;
1601
1602 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1603 if (!queue->hw_ctx)
1604 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1605
1606 return VK_SUCCESS;
1607 }
1608
1609 static void
1610 radv_queue_finish(struct radv_queue *queue)
1611 {
1612 if (queue->hw_ctx)
1613 queue->device->ws->ctx_destroy(queue->hw_ctx);
1614
1615 if (queue->initial_full_flush_preamble_cs)
1616 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1617 if (queue->initial_preamble_cs)
1618 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1619 if (queue->continue_preamble_cs)
1620 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1621 if (queue->descriptor_bo)
1622 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1623 if (queue->scratch_bo)
1624 queue->device->ws->buffer_destroy(queue->scratch_bo);
1625 if (queue->esgs_ring_bo)
1626 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1627 if (queue->gsvs_ring_bo)
1628 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1629 if (queue->tess_rings_bo)
1630 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1631 if (queue->compute_scratch_bo)
1632 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1633 }
1634
1635 static void
1636 radv_bo_list_init(struct radv_bo_list *bo_list)
1637 {
1638 pthread_mutex_init(&bo_list->mutex, NULL);
1639 bo_list->list.count = bo_list->capacity = 0;
1640 bo_list->list.bos = NULL;
1641 }
1642
1643 static void
1644 radv_bo_list_finish(struct radv_bo_list *bo_list)
1645 {
1646 free(bo_list->list.bos);
1647 pthread_mutex_destroy(&bo_list->mutex);
1648 }
1649
1650 static VkResult radv_bo_list_add(struct radv_device *device,
1651 struct radeon_winsys_bo *bo)
1652 {
1653 struct radv_bo_list *bo_list = &device->bo_list;
1654
1655 if (bo->is_local)
1656 return VK_SUCCESS;
1657
1658 if (unlikely(!device->use_global_bo_list))
1659 return VK_SUCCESS;
1660
1661 pthread_mutex_lock(&bo_list->mutex);
1662 if (bo_list->list.count == bo_list->capacity) {
1663 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1664 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1665
1666 if (!data) {
1667 pthread_mutex_unlock(&bo_list->mutex);
1668 return VK_ERROR_OUT_OF_HOST_MEMORY;
1669 }
1670
1671 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1672 bo_list->capacity = capacity;
1673 }
1674
1675 bo_list->list.bos[bo_list->list.count++] = bo;
1676 pthread_mutex_unlock(&bo_list->mutex);
1677 return VK_SUCCESS;
1678 }
1679
1680 static void radv_bo_list_remove(struct radv_device *device,
1681 struct radeon_winsys_bo *bo)
1682 {
1683 struct radv_bo_list *bo_list = &device->bo_list;
1684
1685 if (bo->is_local)
1686 return;
1687
1688 if (unlikely(!device->use_global_bo_list))
1689 return;
1690
1691 pthread_mutex_lock(&bo_list->mutex);
1692 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1693 if (bo_list->list.bos[i] == bo) {
1694 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1695 --bo_list->list.count;
1696 break;
1697 }
1698 }
1699 pthread_mutex_unlock(&bo_list->mutex);
1700 }
1701
1702 static void
1703 radv_device_init_gs_info(struct radv_device *device)
1704 {
1705 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1706 device->physical_device->rad_info.family);
1707 }
1708
1709 static int radv_get_device_extension_index(const char *name)
1710 {
1711 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1712 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1713 return i;
1714 }
1715 return -1;
1716 }
1717
1718 static int
1719 radv_get_int_debug_option(const char *name, int default_value)
1720 {
1721 const char *str;
1722 int result;
1723
1724 str = getenv(name);
1725 if (!str) {
1726 result = default_value;
1727 } else {
1728 char *endptr;
1729
1730 result = strtol(str, &endptr, 0);
1731 if (str == endptr) {
1732 /* No digits founs. */
1733 result = default_value;
1734 }
1735 }
1736
1737 return result;
1738 }
1739
1740 VkResult radv_CreateDevice(
1741 VkPhysicalDevice physicalDevice,
1742 const VkDeviceCreateInfo* pCreateInfo,
1743 const VkAllocationCallbacks* pAllocator,
1744 VkDevice* pDevice)
1745 {
1746 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1747 VkResult result;
1748 struct radv_device *device;
1749
1750 bool keep_shader_info = false;
1751
1752 /* Check enabled features */
1753 if (pCreateInfo->pEnabledFeatures) {
1754 VkPhysicalDeviceFeatures supported_features;
1755 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1756 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1757 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1758 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1759 for (uint32_t i = 0; i < num_features; i++) {
1760 if (enabled_feature[i] && !supported_feature[i])
1761 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1762 }
1763 }
1764
1765 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1766 sizeof(*device), 8,
1767 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1768 if (!device)
1769 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1770
1771 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1772 device->instance = physical_device->instance;
1773 device->physical_device = physical_device;
1774
1775 device->ws = physical_device->ws;
1776 if (pAllocator)
1777 device->alloc = *pAllocator;
1778 else
1779 device->alloc = physical_device->instance->alloc;
1780
1781 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1782 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1783 int index = radv_get_device_extension_index(ext_name);
1784 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1785 vk_free(&device->alloc, device);
1786 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1787 }
1788
1789 device->enabled_extensions.extensions[index] = true;
1790 }
1791
1792 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1793
1794 /* With update after bind we can't attach bo's to the command buffer
1795 * from the descriptor set anymore, so we have to use a global BO list.
1796 */
1797 device->use_global_bo_list =
1798 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1799 device->enabled_extensions.EXT_descriptor_indexing ||
1800 device->enabled_extensions.EXT_buffer_device_address;
1801
1802 mtx_init(&device->shader_slab_mutex, mtx_plain);
1803 list_inithead(&device->shader_slabs);
1804
1805 radv_bo_list_init(&device->bo_list);
1806
1807 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1808 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1809 uint32_t qfi = queue_create->queueFamilyIndex;
1810 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1811 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1812
1813 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1814
1815 device->queues[qfi] = vk_alloc(&device->alloc,
1816 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1817 if (!device->queues[qfi]) {
1818 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1819 goto fail;
1820 }
1821
1822 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1823
1824 device->queue_count[qfi] = queue_create->queueCount;
1825
1826 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1827 result = radv_queue_init(device, &device->queues[qfi][q],
1828 qfi, q, queue_create->flags,
1829 global_priority);
1830 if (result != VK_SUCCESS)
1831 goto fail;
1832 }
1833 }
1834
1835 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1836 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1837
1838 /* Disabled and not implemented for now. */
1839 device->dfsm_allowed = device->pbb_allowed &&
1840 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1841 device->physical_device->rad_info.family == CHIP_RAVEN2);
1842
1843 #ifdef ANDROID
1844 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1845 #endif
1846
1847 /* The maximum number of scratch waves. Scratch space isn't divided
1848 * evenly between CUs. The number is only a function of the number of CUs.
1849 * We can decrease the constant to decrease the scratch buffer size.
1850 *
1851 * sctx->scratch_waves must be >= the maximum possible size of
1852 * 1 threadgroup, so that the hw doesn't hang from being unable
1853 * to start any.
1854 *
1855 * The recommended value is 4 per CU at most. Higher numbers don't
1856 * bring much benefit, but they still occupy chip resources (think
1857 * async compute). I've seen ~2% performance difference between 4 and 32.
1858 */
1859 uint32_t max_threads_per_block = 2048;
1860 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1861 max_threads_per_block / 64);
1862
1863 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1864
1865 if (device->physical_device->rad_info.chip_class >= CIK) {
1866 /* If the KMD allows it (there is a KMD hw register for it),
1867 * allow launching waves out-of-order.
1868 */
1869 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1870 }
1871
1872 radv_device_init_gs_info(device);
1873
1874 device->tess_offchip_block_dw_size =
1875 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1876 device->has_distributed_tess =
1877 device->physical_device->rad_info.chip_class >= VI &&
1878 device->physical_device->rad_info.max_se >= 2;
1879
1880 if (getenv("RADV_TRACE_FILE")) {
1881 const char *filename = getenv("RADV_TRACE_FILE");
1882
1883 keep_shader_info = true;
1884
1885 if (!radv_init_trace(device))
1886 goto fail;
1887
1888 fprintf(stderr, "*****************************************************************************\n");
1889 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1890 fprintf(stderr, "*****************************************************************************\n");
1891
1892 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1893 radv_dump_enabled_options(device, stderr);
1894 }
1895
1896 device->keep_shader_info = keep_shader_info;
1897
1898 result = radv_device_init_meta(device);
1899 if (result != VK_SUCCESS)
1900 goto fail;
1901
1902 radv_device_init_msaa(device);
1903
1904 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1905 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1906 switch (family) {
1907 case RADV_QUEUE_GENERAL:
1908 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1909 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1910 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1911 break;
1912 case RADV_QUEUE_COMPUTE:
1913 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1914 radeon_emit(device->empty_cs[family], 0);
1915 break;
1916 }
1917 device->ws->cs_finalize(device->empty_cs[family]);
1918 }
1919
1920 if (device->physical_device->rad_info.chip_class >= CIK)
1921 cik_create_gfx_config(device);
1922
1923 VkPipelineCacheCreateInfo ci;
1924 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1925 ci.pNext = NULL;
1926 ci.flags = 0;
1927 ci.pInitialData = NULL;
1928 ci.initialDataSize = 0;
1929 VkPipelineCache pc;
1930 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1931 &ci, NULL, &pc);
1932 if (result != VK_SUCCESS)
1933 goto fail_meta;
1934
1935 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1936
1937 device->force_aniso =
1938 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1939 if (device->force_aniso >= 0) {
1940 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1941 1 << util_logbase2(device->force_aniso));
1942 }
1943
1944 *pDevice = radv_device_to_handle(device);
1945 return VK_SUCCESS;
1946
1947 fail_meta:
1948 radv_device_finish_meta(device);
1949 fail:
1950 radv_bo_list_finish(&device->bo_list);
1951
1952 if (device->trace_bo)
1953 device->ws->buffer_destroy(device->trace_bo);
1954
1955 if (device->gfx_init)
1956 device->ws->buffer_destroy(device->gfx_init);
1957
1958 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1959 for (unsigned q = 0; q < device->queue_count[i]; q++)
1960 radv_queue_finish(&device->queues[i][q]);
1961 if (device->queue_count[i])
1962 vk_free(&device->alloc, device->queues[i]);
1963 }
1964
1965 vk_free(&device->alloc, device);
1966 return result;
1967 }
1968
1969 void radv_DestroyDevice(
1970 VkDevice _device,
1971 const VkAllocationCallbacks* pAllocator)
1972 {
1973 RADV_FROM_HANDLE(radv_device, device, _device);
1974
1975 if (!device)
1976 return;
1977
1978 if (device->trace_bo)
1979 device->ws->buffer_destroy(device->trace_bo);
1980
1981 if (device->gfx_init)
1982 device->ws->buffer_destroy(device->gfx_init);
1983
1984 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1985 for (unsigned q = 0; q < device->queue_count[i]; q++)
1986 radv_queue_finish(&device->queues[i][q]);
1987 if (device->queue_count[i])
1988 vk_free(&device->alloc, device->queues[i]);
1989 if (device->empty_cs[i])
1990 device->ws->cs_destroy(device->empty_cs[i]);
1991 }
1992 radv_device_finish_meta(device);
1993
1994 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1995 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1996
1997 radv_destroy_shader_slabs(device);
1998
1999 radv_bo_list_finish(&device->bo_list);
2000 vk_free(&device->alloc, device);
2001 }
2002
2003 VkResult radv_EnumerateInstanceLayerProperties(
2004 uint32_t* pPropertyCount,
2005 VkLayerProperties* pProperties)
2006 {
2007 if (pProperties == NULL) {
2008 *pPropertyCount = 0;
2009 return VK_SUCCESS;
2010 }
2011
2012 /* None supported at this time */
2013 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2014 }
2015
2016 VkResult radv_EnumerateDeviceLayerProperties(
2017 VkPhysicalDevice physicalDevice,
2018 uint32_t* pPropertyCount,
2019 VkLayerProperties* pProperties)
2020 {
2021 if (pProperties == NULL) {
2022 *pPropertyCount = 0;
2023 return VK_SUCCESS;
2024 }
2025
2026 /* None supported at this time */
2027 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2028 }
2029
2030 void radv_GetDeviceQueue2(
2031 VkDevice _device,
2032 const VkDeviceQueueInfo2* pQueueInfo,
2033 VkQueue* pQueue)
2034 {
2035 RADV_FROM_HANDLE(radv_device, device, _device);
2036 struct radv_queue *queue;
2037
2038 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2039 if (pQueueInfo->flags != queue->flags) {
2040 /* From the Vulkan 1.1.70 spec:
2041 *
2042 * "The queue returned by vkGetDeviceQueue2 must have the same
2043 * flags value from this structure as that used at device
2044 * creation time in a VkDeviceQueueCreateInfo instance. If no
2045 * matching flags were specified at device creation time then
2046 * pQueue will return VK_NULL_HANDLE."
2047 */
2048 *pQueue = VK_NULL_HANDLE;
2049 return;
2050 }
2051
2052 *pQueue = radv_queue_to_handle(queue);
2053 }
2054
2055 void radv_GetDeviceQueue(
2056 VkDevice _device,
2057 uint32_t queueFamilyIndex,
2058 uint32_t queueIndex,
2059 VkQueue* pQueue)
2060 {
2061 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2062 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2063 .queueFamilyIndex = queueFamilyIndex,
2064 .queueIndex = queueIndex
2065 };
2066
2067 radv_GetDeviceQueue2(_device, &info, pQueue);
2068 }
2069
2070 static void
2071 fill_geom_tess_rings(struct radv_queue *queue,
2072 uint32_t *map,
2073 bool add_sample_positions,
2074 uint32_t esgs_ring_size,
2075 struct radeon_winsys_bo *esgs_ring_bo,
2076 uint32_t gsvs_ring_size,
2077 struct radeon_winsys_bo *gsvs_ring_bo,
2078 uint32_t tess_factor_ring_size,
2079 uint32_t tess_offchip_ring_offset,
2080 uint32_t tess_offchip_ring_size,
2081 struct radeon_winsys_bo *tess_rings_bo)
2082 {
2083 uint32_t *desc = &map[4];
2084
2085 if (esgs_ring_bo) {
2086 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2087
2088 /* stride 0, num records - size, add tid, swizzle, elsize4,
2089 index stride 64 */
2090 desc[0] = esgs_va;
2091 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2092 S_008F04_STRIDE(0) |
2093 S_008F04_SWIZZLE_ENABLE(true);
2094 desc[2] = esgs_ring_size;
2095 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2096 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2097 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2098 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2099 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2100 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2101 S_008F0C_ELEMENT_SIZE(1) |
2102 S_008F0C_INDEX_STRIDE(3) |
2103 S_008F0C_ADD_TID_ENABLE(true);
2104
2105 /* GS entry for ES->GS ring */
2106 /* stride 0, num records - size, elsize0,
2107 index stride 0 */
2108 desc[4] = esgs_va;
2109 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2110 S_008F04_STRIDE(0) |
2111 S_008F04_SWIZZLE_ENABLE(false);
2112 desc[6] = esgs_ring_size;
2113 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2114 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2115 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2116 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2117 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2118 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2119 S_008F0C_ELEMENT_SIZE(0) |
2120 S_008F0C_INDEX_STRIDE(0) |
2121 S_008F0C_ADD_TID_ENABLE(false);
2122 }
2123
2124 desc += 8;
2125
2126 if (gsvs_ring_bo) {
2127 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2128
2129 /* VS entry for GS->VS ring */
2130 /* stride 0, num records - size, elsize0,
2131 index stride 0 */
2132 desc[0] = gsvs_va;
2133 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2134 S_008F04_STRIDE(0) |
2135 S_008F04_SWIZZLE_ENABLE(false);
2136 desc[2] = gsvs_ring_size;
2137 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2138 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2139 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2140 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2141 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2143 S_008F0C_ELEMENT_SIZE(0) |
2144 S_008F0C_INDEX_STRIDE(0) |
2145 S_008F0C_ADD_TID_ENABLE(false);
2146
2147 /* stride gsvs_itemsize, num records 64
2148 elsize 4, index stride 16 */
2149 /* shader will patch stride and desc[2] */
2150 desc[4] = gsvs_va;
2151 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2152 S_008F04_STRIDE(0) |
2153 S_008F04_SWIZZLE_ENABLE(true);
2154 desc[6] = 0;
2155 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2156 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2157 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2158 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2159 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2160 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2161 S_008F0C_ELEMENT_SIZE(1) |
2162 S_008F0C_INDEX_STRIDE(1) |
2163 S_008F0C_ADD_TID_ENABLE(true);
2164 }
2165
2166 desc += 8;
2167
2168 if (tess_rings_bo) {
2169 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2170 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2171
2172 desc[0] = tess_va;
2173 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2174 S_008F04_STRIDE(0) |
2175 S_008F04_SWIZZLE_ENABLE(false);
2176 desc[2] = tess_factor_ring_size;
2177 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2178 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2179 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2180 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2181 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2182 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2183 S_008F0C_ELEMENT_SIZE(0) |
2184 S_008F0C_INDEX_STRIDE(0) |
2185 S_008F0C_ADD_TID_ENABLE(false);
2186
2187 desc[4] = tess_offchip_va;
2188 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2189 S_008F04_STRIDE(0) |
2190 S_008F04_SWIZZLE_ENABLE(false);
2191 desc[6] = tess_offchip_ring_size;
2192 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2193 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2194 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2195 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2196 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2197 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2198 S_008F0C_ELEMENT_SIZE(0) |
2199 S_008F0C_INDEX_STRIDE(0) |
2200 S_008F0C_ADD_TID_ENABLE(false);
2201 }
2202
2203 desc += 8;
2204
2205 if (add_sample_positions) {
2206 /* add sample positions after all rings */
2207 memcpy(desc, queue->device->sample_locations_1x, 8);
2208 desc += 2;
2209 memcpy(desc, queue->device->sample_locations_2x, 16);
2210 desc += 4;
2211 memcpy(desc, queue->device->sample_locations_4x, 32);
2212 desc += 8;
2213 memcpy(desc, queue->device->sample_locations_8x, 64);
2214 }
2215 }
2216
2217 static unsigned
2218 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2219 {
2220 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2221 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2222 device->physical_device->rad_info.family != CHIP_STONEY;
2223 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2224 unsigned max_offchip_buffers;
2225 unsigned offchip_granularity;
2226 unsigned hs_offchip_param;
2227
2228 /*
2229 * Per RadeonSI:
2230 * This must be one less than the maximum number due to a hw limitation.
2231 * Various hardware bugs in SI, CIK, and GFX9 need this.
2232 *
2233 * Per AMDVLK:
2234 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2235 * Gfx7 should limit max_offchip_buffers to 508
2236 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2237 *
2238 * Follow AMDVLK here.
2239 */
2240 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2241 device->physical_device->rad_info.chip_class == CIK ||
2242 device->physical_device->rad_info.chip_class == SI)
2243 --max_offchip_buffers_per_se;
2244
2245 max_offchip_buffers = max_offchip_buffers_per_se *
2246 device->physical_device->rad_info.max_se;
2247
2248 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2249 * around by setting 4K granularity.
2250 */
2251 if (device->tess_offchip_block_dw_size == 4096) {
2252 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2253 offchip_granularity = V_03093C_X_4K_DWORDS;
2254 } else {
2255 assert(device->tess_offchip_block_dw_size == 8192);
2256 offchip_granularity = V_03093C_X_8K_DWORDS;
2257 }
2258
2259 switch (device->physical_device->rad_info.chip_class) {
2260 case SI:
2261 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2262 break;
2263 case CIK:
2264 case VI:
2265 case GFX9:
2266 default:
2267 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2268 break;
2269 }
2270
2271 *max_offchip_buffers_p = max_offchip_buffers;
2272 if (device->physical_device->rad_info.chip_class >= CIK) {
2273 if (device->physical_device->rad_info.chip_class >= VI)
2274 --max_offchip_buffers;
2275 hs_offchip_param =
2276 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2277 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2278 } else {
2279 hs_offchip_param =
2280 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2281 }
2282 return hs_offchip_param;
2283 }
2284
2285 static void
2286 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2287 struct radeon_winsys_bo *esgs_ring_bo,
2288 uint32_t esgs_ring_size,
2289 struct radeon_winsys_bo *gsvs_ring_bo,
2290 uint32_t gsvs_ring_size)
2291 {
2292 if (!esgs_ring_bo && !gsvs_ring_bo)
2293 return;
2294
2295 if (esgs_ring_bo)
2296 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2297
2298 if (gsvs_ring_bo)
2299 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2300
2301 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2302 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2303 radeon_emit(cs, esgs_ring_size >> 8);
2304 radeon_emit(cs, gsvs_ring_size >> 8);
2305 } else {
2306 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2307 radeon_emit(cs, esgs_ring_size >> 8);
2308 radeon_emit(cs, gsvs_ring_size >> 8);
2309 }
2310 }
2311
2312 static void
2313 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2314 unsigned hs_offchip_param, unsigned tf_ring_size,
2315 struct radeon_winsys_bo *tess_rings_bo)
2316 {
2317 uint64_t tf_va;
2318
2319 if (!tess_rings_bo)
2320 return;
2321
2322 tf_va = radv_buffer_get_va(tess_rings_bo);
2323
2324 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2325
2326 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2327 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2328 S_030938_SIZE(tf_ring_size / 4));
2329 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2330 tf_va >> 8);
2331 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2332 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2333 S_030944_BASE_HI(tf_va >> 40));
2334 }
2335 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2336 hs_offchip_param);
2337 } else {
2338 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2339 S_008988_SIZE(tf_ring_size / 4));
2340 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2341 tf_va >> 8);
2342 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2343 hs_offchip_param);
2344 }
2345 }
2346
2347 static void
2348 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2349 struct radeon_winsys_bo *compute_scratch_bo)
2350 {
2351 uint64_t scratch_va;
2352
2353 if (!compute_scratch_bo)
2354 return;
2355
2356 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2357
2358 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2359
2360 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2361 radeon_emit(cs, scratch_va);
2362 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2363 S_008F04_SWIZZLE_ENABLE(1));
2364 }
2365
2366 static void
2367 radv_emit_global_shader_pointers(struct radv_queue *queue,
2368 struct radeon_cmdbuf *cs,
2369 struct radeon_winsys_bo *descriptor_bo)
2370 {
2371 uint64_t va;
2372
2373 if (!descriptor_bo)
2374 return;
2375
2376 va = radv_buffer_get_va(descriptor_bo);
2377
2378 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2379
2380 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2381 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2382 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2383 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2384 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2385
2386 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2387 radv_emit_shader_pointer(queue->device, cs, regs[i],
2388 va, true);
2389 }
2390 } else {
2391 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2392 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2393 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2394 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2395 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2396 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2397
2398 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2399 radv_emit_shader_pointer(queue->device, cs, regs[i],
2400 va, true);
2401 }
2402 }
2403 }
2404
2405 static void
2406 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2407 {
2408 struct radv_device *device = queue->device;
2409
2410 if (device->gfx_init) {
2411 uint64_t va = radv_buffer_get_va(device->gfx_init);
2412
2413 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2414 radeon_emit(cs, va);
2415 radeon_emit(cs, va >> 32);
2416 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2417
2418 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2419 } else {
2420 struct radv_physical_device *physical_device = device->physical_device;
2421 si_emit_graphics(physical_device, cs);
2422 }
2423 }
2424
2425 static void
2426 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2427 {
2428 struct radv_physical_device *physical_device = queue->device->physical_device;
2429 si_emit_compute(physical_device, cs);
2430 }
2431
2432 static VkResult
2433 radv_get_preamble_cs(struct radv_queue *queue,
2434 uint32_t scratch_size,
2435 uint32_t compute_scratch_size,
2436 uint32_t esgs_ring_size,
2437 uint32_t gsvs_ring_size,
2438 bool needs_tess_rings,
2439 bool needs_sample_positions,
2440 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2441 struct radeon_cmdbuf **initial_preamble_cs,
2442 struct radeon_cmdbuf **continue_preamble_cs)
2443 {
2444 struct radeon_winsys_bo *scratch_bo = NULL;
2445 struct radeon_winsys_bo *descriptor_bo = NULL;
2446 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2447 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2448 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2449 struct radeon_winsys_bo *tess_rings_bo = NULL;
2450 struct radeon_cmdbuf *dest_cs[3] = {0};
2451 bool add_tess_rings = false, add_sample_positions = false;
2452 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2453 unsigned max_offchip_buffers;
2454 unsigned hs_offchip_param = 0;
2455 unsigned tess_offchip_ring_offset;
2456 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2457 if (!queue->has_tess_rings) {
2458 if (needs_tess_rings)
2459 add_tess_rings = true;
2460 }
2461 if (!queue->has_sample_positions) {
2462 if (needs_sample_positions)
2463 add_sample_positions = true;
2464 }
2465 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2466 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2467 &max_offchip_buffers);
2468 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2469 tess_offchip_ring_size = max_offchip_buffers *
2470 queue->device->tess_offchip_block_dw_size * 4;
2471
2472 if (scratch_size <= queue->scratch_size &&
2473 compute_scratch_size <= queue->compute_scratch_size &&
2474 esgs_ring_size <= queue->esgs_ring_size &&
2475 gsvs_ring_size <= queue->gsvs_ring_size &&
2476 !add_tess_rings && !add_sample_positions &&
2477 queue->initial_preamble_cs) {
2478 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2479 *initial_preamble_cs = queue->initial_preamble_cs;
2480 *continue_preamble_cs = queue->continue_preamble_cs;
2481 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2482 *continue_preamble_cs = NULL;
2483 return VK_SUCCESS;
2484 }
2485
2486 if (scratch_size > queue->scratch_size) {
2487 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2488 scratch_size,
2489 4096,
2490 RADEON_DOMAIN_VRAM,
2491 ring_bo_flags,
2492 RADV_BO_PRIORITY_SCRATCH);
2493 if (!scratch_bo)
2494 goto fail;
2495 } else
2496 scratch_bo = queue->scratch_bo;
2497
2498 if (compute_scratch_size > queue->compute_scratch_size) {
2499 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2500 compute_scratch_size,
2501 4096,
2502 RADEON_DOMAIN_VRAM,
2503 ring_bo_flags,
2504 RADV_BO_PRIORITY_SCRATCH);
2505 if (!compute_scratch_bo)
2506 goto fail;
2507
2508 } else
2509 compute_scratch_bo = queue->compute_scratch_bo;
2510
2511 if (esgs_ring_size > queue->esgs_ring_size) {
2512 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2513 esgs_ring_size,
2514 4096,
2515 RADEON_DOMAIN_VRAM,
2516 ring_bo_flags,
2517 RADV_BO_PRIORITY_SCRATCH);
2518 if (!esgs_ring_bo)
2519 goto fail;
2520 } else {
2521 esgs_ring_bo = queue->esgs_ring_bo;
2522 esgs_ring_size = queue->esgs_ring_size;
2523 }
2524
2525 if (gsvs_ring_size > queue->gsvs_ring_size) {
2526 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2527 gsvs_ring_size,
2528 4096,
2529 RADEON_DOMAIN_VRAM,
2530 ring_bo_flags,
2531 RADV_BO_PRIORITY_SCRATCH);
2532 if (!gsvs_ring_bo)
2533 goto fail;
2534 } else {
2535 gsvs_ring_bo = queue->gsvs_ring_bo;
2536 gsvs_ring_size = queue->gsvs_ring_size;
2537 }
2538
2539 if (add_tess_rings) {
2540 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2541 tess_offchip_ring_offset + tess_offchip_ring_size,
2542 256,
2543 RADEON_DOMAIN_VRAM,
2544 ring_bo_flags,
2545 RADV_BO_PRIORITY_SCRATCH);
2546 if (!tess_rings_bo)
2547 goto fail;
2548 } else {
2549 tess_rings_bo = queue->tess_rings_bo;
2550 }
2551
2552 if (scratch_bo != queue->scratch_bo ||
2553 esgs_ring_bo != queue->esgs_ring_bo ||
2554 gsvs_ring_bo != queue->gsvs_ring_bo ||
2555 tess_rings_bo != queue->tess_rings_bo ||
2556 add_sample_positions) {
2557 uint32_t size = 0;
2558 if (gsvs_ring_bo || esgs_ring_bo ||
2559 tess_rings_bo || add_sample_positions) {
2560 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2561 if (add_sample_positions)
2562 size += 128; /* 64+32+16+8 = 120 bytes */
2563 }
2564 else if (scratch_bo)
2565 size = 8; /* 2 dword */
2566
2567 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2568 size,
2569 4096,
2570 RADEON_DOMAIN_VRAM,
2571 RADEON_FLAG_CPU_ACCESS |
2572 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2573 RADEON_FLAG_READ_ONLY,
2574 RADV_BO_PRIORITY_DESCRIPTOR);
2575 if (!descriptor_bo)
2576 goto fail;
2577 } else
2578 descriptor_bo = queue->descriptor_bo;
2579
2580 if (descriptor_bo != queue->descriptor_bo) {
2581 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2582
2583 if (scratch_bo) {
2584 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2585 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2586 S_008F04_SWIZZLE_ENABLE(1);
2587 map[0] = scratch_va;
2588 map[1] = rsrc1;
2589 }
2590
2591 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2592 fill_geom_tess_rings(queue, map, add_sample_positions,
2593 esgs_ring_size, esgs_ring_bo,
2594 gsvs_ring_size, gsvs_ring_bo,
2595 tess_factor_ring_size,
2596 tess_offchip_ring_offset,
2597 tess_offchip_ring_size,
2598 tess_rings_bo);
2599
2600 queue->device->ws->buffer_unmap(descriptor_bo);
2601 }
2602
2603 for(int i = 0; i < 3; ++i) {
2604 struct radeon_cmdbuf *cs = NULL;
2605 cs = queue->device->ws->cs_create(queue->device->ws,
2606 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2607 if (!cs)
2608 goto fail;
2609
2610 dest_cs[i] = cs;
2611
2612 if (scratch_bo)
2613 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2614
2615 /* Emit initial configuration. */
2616 switch (queue->queue_family_index) {
2617 case RADV_QUEUE_GENERAL:
2618 radv_init_graphics_state(cs, queue);
2619 break;
2620 case RADV_QUEUE_COMPUTE:
2621 radv_init_compute_state(cs, queue);
2622 break;
2623 case RADV_QUEUE_TRANSFER:
2624 break;
2625 }
2626
2627 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2628 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2629 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2630 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2631 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2632 }
2633
2634 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2635 gsvs_ring_bo, gsvs_ring_size);
2636 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2637 tess_factor_ring_size, tess_rings_bo);
2638 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2639 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2640
2641 if (i == 0) {
2642 si_cs_emit_cache_flush(cs,
2643 queue->device->physical_device->rad_info.chip_class,
2644 NULL, 0,
2645 queue->queue_family_index == RING_COMPUTE &&
2646 queue->device->physical_device->rad_info.chip_class >= CIK,
2647 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2648 RADV_CMD_FLAG_INV_ICACHE |
2649 RADV_CMD_FLAG_INV_SMEM_L1 |
2650 RADV_CMD_FLAG_INV_VMEM_L1 |
2651 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2652 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2653 } else if (i == 1) {
2654 si_cs_emit_cache_flush(cs,
2655 queue->device->physical_device->rad_info.chip_class,
2656 NULL, 0,
2657 queue->queue_family_index == RING_COMPUTE &&
2658 queue->device->physical_device->rad_info.chip_class >= CIK,
2659 RADV_CMD_FLAG_INV_ICACHE |
2660 RADV_CMD_FLAG_INV_SMEM_L1 |
2661 RADV_CMD_FLAG_INV_VMEM_L1 |
2662 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2663 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2664 }
2665
2666 if (!queue->device->ws->cs_finalize(cs))
2667 goto fail;
2668 }
2669
2670 if (queue->initial_full_flush_preamble_cs)
2671 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2672
2673 if (queue->initial_preamble_cs)
2674 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2675
2676 if (queue->continue_preamble_cs)
2677 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2678
2679 queue->initial_full_flush_preamble_cs = dest_cs[0];
2680 queue->initial_preamble_cs = dest_cs[1];
2681 queue->continue_preamble_cs = dest_cs[2];
2682
2683 if (scratch_bo != queue->scratch_bo) {
2684 if (queue->scratch_bo)
2685 queue->device->ws->buffer_destroy(queue->scratch_bo);
2686 queue->scratch_bo = scratch_bo;
2687 queue->scratch_size = scratch_size;
2688 }
2689
2690 if (compute_scratch_bo != queue->compute_scratch_bo) {
2691 if (queue->compute_scratch_bo)
2692 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2693 queue->compute_scratch_bo = compute_scratch_bo;
2694 queue->compute_scratch_size = compute_scratch_size;
2695 }
2696
2697 if (esgs_ring_bo != queue->esgs_ring_bo) {
2698 if (queue->esgs_ring_bo)
2699 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2700 queue->esgs_ring_bo = esgs_ring_bo;
2701 queue->esgs_ring_size = esgs_ring_size;
2702 }
2703
2704 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2705 if (queue->gsvs_ring_bo)
2706 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2707 queue->gsvs_ring_bo = gsvs_ring_bo;
2708 queue->gsvs_ring_size = gsvs_ring_size;
2709 }
2710
2711 if (tess_rings_bo != queue->tess_rings_bo) {
2712 queue->tess_rings_bo = tess_rings_bo;
2713 queue->has_tess_rings = true;
2714 }
2715
2716 if (descriptor_bo != queue->descriptor_bo) {
2717 if (queue->descriptor_bo)
2718 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2719
2720 queue->descriptor_bo = descriptor_bo;
2721 }
2722
2723 if (add_sample_positions)
2724 queue->has_sample_positions = true;
2725
2726 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2727 *initial_preamble_cs = queue->initial_preamble_cs;
2728 *continue_preamble_cs = queue->continue_preamble_cs;
2729 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2730 *continue_preamble_cs = NULL;
2731 return VK_SUCCESS;
2732 fail:
2733 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2734 if (dest_cs[i])
2735 queue->device->ws->cs_destroy(dest_cs[i]);
2736 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2737 queue->device->ws->buffer_destroy(descriptor_bo);
2738 if (scratch_bo && scratch_bo != queue->scratch_bo)
2739 queue->device->ws->buffer_destroy(scratch_bo);
2740 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2741 queue->device->ws->buffer_destroy(compute_scratch_bo);
2742 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2743 queue->device->ws->buffer_destroy(esgs_ring_bo);
2744 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2745 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2746 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2747 queue->device->ws->buffer_destroy(tess_rings_bo);
2748 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2749 }
2750
2751 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2752 struct radv_winsys_sem_counts *counts,
2753 int num_sems,
2754 const VkSemaphore *sems,
2755 VkFence _fence,
2756 bool reset_temp)
2757 {
2758 int syncobj_idx = 0, sem_idx = 0;
2759
2760 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2761 return VK_SUCCESS;
2762
2763 for (uint32_t i = 0; i < num_sems; i++) {
2764 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2765
2766 if (sem->temp_syncobj || sem->syncobj)
2767 counts->syncobj_count++;
2768 else
2769 counts->sem_count++;
2770 }
2771
2772 if (_fence != VK_NULL_HANDLE) {
2773 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2774 if (fence->temp_syncobj || fence->syncobj)
2775 counts->syncobj_count++;
2776 }
2777
2778 if (counts->syncobj_count) {
2779 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2780 if (!counts->syncobj)
2781 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2782 }
2783
2784 if (counts->sem_count) {
2785 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2786 if (!counts->sem) {
2787 free(counts->syncobj);
2788 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2789 }
2790 }
2791
2792 for (uint32_t i = 0; i < num_sems; i++) {
2793 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2794
2795 if (sem->temp_syncobj) {
2796 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2797 }
2798 else if (sem->syncobj)
2799 counts->syncobj[syncobj_idx++] = sem->syncobj;
2800 else {
2801 assert(sem->sem);
2802 counts->sem[sem_idx++] = sem->sem;
2803 }
2804 }
2805
2806 if (_fence != VK_NULL_HANDLE) {
2807 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2808 if (fence->temp_syncobj)
2809 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2810 else if (fence->syncobj)
2811 counts->syncobj[syncobj_idx++] = fence->syncobj;
2812 }
2813
2814 return VK_SUCCESS;
2815 }
2816
2817 static void
2818 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2819 {
2820 free(sem_info->wait.syncobj);
2821 free(sem_info->wait.sem);
2822 free(sem_info->signal.syncobj);
2823 free(sem_info->signal.sem);
2824 }
2825
2826
2827 static void radv_free_temp_syncobjs(struct radv_device *device,
2828 int num_sems,
2829 const VkSemaphore *sems)
2830 {
2831 for (uint32_t i = 0; i < num_sems; i++) {
2832 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2833
2834 if (sem->temp_syncobj) {
2835 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2836 sem->temp_syncobj = 0;
2837 }
2838 }
2839 }
2840
2841 static VkResult
2842 radv_alloc_sem_info(struct radv_instance *instance,
2843 struct radv_winsys_sem_info *sem_info,
2844 int num_wait_sems,
2845 const VkSemaphore *wait_sems,
2846 int num_signal_sems,
2847 const VkSemaphore *signal_sems,
2848 VkFence fence)
2849 {
2850 VkResult ret;
2851 memset(sem_info, 0, sizeof(*sem_info));
2852
2853 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2854 if (ret)
2855 return ret;
2856 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2857 if (ret)
2858 radv_free_sem_info(sem_info);
2859
2860 /* caller can override these */
2861 sem_info->cs_emit_wait = true;
2862 sem_info->cs_emit_signal = true;
2863 return ret;
2864 }
2865
2866 /* Signals fence as soon as all the work currently put on queue is done. */
2867 static VkResult radv_signal_fence(struct radv_queue *queue,
2868 struct radv_fence *fence)
2869 {
2870 int ret;
2871 VkResult result;
2872 struct radv_winsys_sem_info sem_info;
2873
2874 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2875 radv_fence_to_handle(fence));
2876 if (result != VK_SUCCESS)
2877 return result;
2878
2879 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2880 &queue->device->empty_cs[queue->queue_family_index],
2881 1, NULL, NULL, &sem_info, NULL,
2882 false, fence->fence);
2883 radv_free_sem_info(&sem_info);
2884
2885 if (ret)
2886 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2887
2888 return VK_SUCCESS;
2889 }
2890
2891 VkResult radv_QueueSubmit(
2892 VkQueue _queue,
2893 uint32_t submitCount,
2894 const VkSubmitInfo* pSubmits,
2895 VkFence _fence)
2896 {
2897 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2898 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2899 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2900 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2901 int ret;
2902 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2903 uint32_t scratch_size = 0;
2904 uint32_t compute_scratch_size = 0;
2905 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2906 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2907 VkResult result;
2908 bool fence_emitted = false;
2909 bool tess_rings_needed = false;
2910 bool sample_positions_needed = false;
2911
2912 /* Do this first so failing to allocate scratch buffers can't result in
2913 * partially executed submissions. */
2914 for (uint32_t i = 0; i < submitCount; i++) {
2915 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2917 pSubmits[i].pCommandBuffers[j]);
2918
2919 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2920 compute_scratch_size = MAX2(compute_scratch_size,
2921 cmd_buffer->compute_scratch_size_needed);
2922 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2923 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2924 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2925 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2926 }
2927 }
2928
2929 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2930 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2931 sample_positions_needed, &initial_flush_preamble_cs,
2932 &initial_preamble_cs, &continue_preamble_cs);
2933 if (result != VK_SUCCESS)
2934 return result;
2935
2936 for (uint32_t i = 0; i < submitCount; i++) {
2937 struct radeon_cmdbuf **cs_array;
2938 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2939 bool can_patch = true;
2940 uint32_t advance;
2941 struct radv_winsys_sem_info sem_info;
2942
2943 result = radv_alloc_sem_info(queue->device->instance,
2944 &sem_info,
2945 pSubmits[i].waitSemaphoreCount,
2946 pSubmits[i].pWaitSemaphores,
2947 pSubmits[i].signalSemaphoreCount,
2948 pSubmits[i].pSignalSemaphores,
2949 _fence);
2950 if (result != VK_SUCCESS)
2951 return result;
2952
2953 if (!pSubmits[i].commandBufferCount) {
2954 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2955 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2956 &queue->device->empty_cs[queue->queue_family_index],
2957 1, NULL, NULL,
2958 &sem_info, NULL,
2959 false, base_fence);
2960 if (ret) {
2961 radv_loge("failed to submit CS %d\n", i);
2962 abort();
2963 }
2964 fence_emitted = true;
2965 }
2966 radv_free_sem_info(&sem_info);
2967 continue;
2968 }
2969
2970 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2971 (pSubmits[i].commandBufferCount));
2972
2973 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2974 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2975 pSubmits[i].pCommandBuffers[j]);
2976 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2977
2978 cs_array[j] = cmd_buffer->cs;
2979 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2980 can_patch = false;
2981
2982 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2983 }
2984
2985 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2986 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2987 const struct radv_winsys_bo_list *bo_list = NULL;
2988
2989 advance = MIN2(max_cs_submission,
2990 pSubmits[i].commandBufferCount - j);
2991
2992 if (queue->device->trace_bo)
2993 *queue->device->trace_id_ptr = 0;
2994
2995 sem_info.cs_emit_wait = j == 0;
2996 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2997
2998 if (unlikely(queue->device->use_global_bo_list)) {
2999 pthread_mutex_lock(&queue->device->bo_list.mutex);
3000 bo_list = &queue->device->bo_list.list;
3001 }
3002
3003 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3004 advance, initial_preamble, continue_preamble_cs,
3005 &sem_info, bo_list,
3006 can_patch, base_fence);
3007
3008 if (unlikely(queue->device->use_global_bo_list))
3009 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3010
3011 if (ret) {
3012 radv_loge("failed to submit CS %d\n", i);
3013 abort();
3014 }
3015 fence_emitted = true;
3016 if (queue->device->trace_bo) {
3017 radv_check_gpu_hangs(queue, cs_array[j]);
3018 }
3019 }
3020
3021 radv_free_temp_syncobjs(queue->device,
3022 pSubmits[i].waitSemaphoreCount,
3023 pSubmits[i].pWaitSemaphores);
3024 radv_free_sem_info(&sem_info);
3025 free(cs_array);
3026 }
3027
3028 if (fence) {
3029 if (!fence_emitted) {
3030 result = radv_signal_fence(queue, fence);
3031 if (result != VK_SUCCESS)
3032 return result;
3033 }
3034 fence->submitted = true;
3035 }
3036
3037 return VK_SUCCESS;
3038 }
3039
3040 VkResult radv_QueueWaitIdle(
3041 VkQueue _queue)
3042 {
3043 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3044
3045 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3046 radv_queue_family_to_ring(queue->queue_family_index),
3047 queue->queue_idx);
3048 return VK_SUCCESS;
3049 }
3050
3051 VkResult radv_DeviceWaitIdle(
3052 VkDevice _device)
3053 {
3054 RADV_FROM_HANDLE(radv_device, device, _device);
3055
3056 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3057 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3058 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3059 }
3060 }
3061 return VK_SUCCESS;
3062 }
3063
3064 VkResult radv_EnumerateInstanceExtensionProperties(
3065 const char* pLayerName,
3066 uint32_t* pPropertyCount,
3067 VkExtensionProperties* pProperties)
3068 {
3069 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3070
3071 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3072 if (radv_supported_instance_extensions.extensions[i]) {
3073 vk_outarray_append(&out, prop) {
3074 *prop = radv_instance_extensions[i];
3075 }
3076 }
3077 }
3078
3079 return vk_outarray_status(&out);
3080 }
3081
3082 VkResult radv_EnumerateDeviceExtensionProperties(
3083 VkPhysicalDevice physicalDevice,
3084 const char* pLayerName,
3085 uint32_t* pPropertyCount,
3086 VkExtensionProperties* pProperties)
3087 {
3088 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3089 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3090
3091 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3092 if (device->supported_extensions.extensions[i]) {
3093 vk_outarray_append(&out, prop) {
3094 *prop = radv_device_extensions[i];
3095 }
3096 }
3097 }
3098
3099 return vk_outarray_status(&out);
3100 }
3101
3102 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3103 VkInstance _instance,
3104 const char* pName)
3105 {
3106 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3107
3108 return radv_lookup_entrypoint_checked(pName,
3109 instance ? instance->apiVersion : 0,
3110 instance ? &instance->enabled_extensions : NULL,
3111 NULL);
3112 }
3113
3114 /* The loader wants us to expose a second GetInstanceProcAddr function
3115 * to work around certain LD_PRELOAD issues seen in apps.
3116 */
3117 PUBLIC
3118 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3119 VkInstance instance,
3120 const char* pName);
3121
3122 PUBLIC
3123 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3124 VkInstance instance,
3125 const char* pName)
3126 {
3127 return radv_GetInstanceProcAddr(instance, pName);
3128 }
3129
3130 PUBLIC
3131 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3132 VkInstance _instance,
3133 const char* pName);
3134
3135 PUBLIC
3136 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3137 VkInstance _instance,
3138 const char* pName)
3139 {
3140 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3141
3142 return radv_lookup_physical_device_entrypoint_checked(pName,
3143 instance ? instance->apiVersion : 0,
3144 instance ? &instance->enabled_extensions : NULL);
3145 }
3146
3147 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3148 VkDevice _device,
3149 const char* pName)
3150 {
3151 RADV_FROM_HANDLE(radv_device, device, _device);
3152
3153 return radv_lookup_entrypoint_checked(pName,
3154 device->instance->apiVersion,
3155 &device->instance->enabled_extensions,
3156 &device->enabled_extensions);
3157 }
3158
3159 bool radv_get_memory_fd(struct radv_device *device,
3160 struct radv_device_memory *memory,
3161 int *pFD)
3162 {
3163 struct radeon_bo_metadata metadata;
3164
3165 if (memory->image) {
3166 radv_init_metadata(device, memory->image, &metadata);
3167 device->ws->buffer_set_metadata(memory->bo, &metadata);
3168 }
3169
3170 return device->ws->buffer_get_fd(device->ws, memory->bo,
3171 pFD);
3172 }
3173
3174 static VkResult radv_alloc_memory(struct radv_device *device,
3175 const VkMemoryAllocateInfo* pAllocateInfo,
3176 const VkAllocationCallbacks* pAllocator,
3177 VkDeviceMemory* pMem)
3178 {
3179 struct radv_device_memory *mem;
3180 VkResult result;
3181 enum radeon_bo_domain domain;
3182 uint32_t flags = 0;
3183 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3184
3185 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3186
3187 if (pAllocateInfo->allocationSize == 0) {
3188 /* Apparently, this is allowed */
3189 *pMem = VK_NULL_HANDLE;
3190 return VK_SUCCESS;
3191 }
3192
3193 const VkImportMemoryFdInfoKHR *import_info =
3194 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3195 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3196 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3197 const VkExportMemoryAllocateInfo *export_info =
3198 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3199 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3200 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3201
3202 const struct wsi_memory_allocate_info *wsi_info =
3203 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3204
3205 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3206 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3207 if (mem == NULL)
3208 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3209
3210 if (wsi_info && wsi_info->implicit_sync)
3211 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3212
3213 if (dedicate_info) {
3214 mem->image = radv_image_from_handle(dedicate_info->image);
3215 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3216 } else {
3217 mem->image = NULL;
3218 mem->buffer = NULL;
3219 }
3220
3221 float priority_float = 0.5;
3222 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3223 vk_find_struct_const(pAllocateInfo->pNext,
3224 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3225 if (priority_ext)
3226 priority_float = priority_ext->priority;
3227
3228 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3229 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3230
3231 mem->user_ptr = NULL;
3232
3233 if (import_info) {
3234 assert(import_info->handleType ==
3235 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3236 import_info->handleType ==
3237 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3238 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3239 priority, NULL, NULL);
3240 if (!mem->bo) {
3241 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3242 goto fail;
3243 } else {
3244 close(import_info->fd);
3245 }
3246 } else if (host_ptr_info) {
3247 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3248 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3249 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3250 pAllocateInfo->allocationSize,
3251 priority);
3252 if (!mem->bo) {
3253 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3254 goto fail;
3255 } else {
3256 mem->user_ptr = host_ptr_info->pHostPointer;
3257 }
3258 } else {
3259 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3260 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3261 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3262 domain = RADEON_DOMAIN_GTT;
3263 else
3264 domain = RADEON_DOMAIN_VRAM;
3265
3266 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3267 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3268 else
3269 flags |= RADEON_FLAG_CPU_ACCESS;
3270
3271 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3272 flags |= RADEON_FLAG_GTT_WC;
3273
3274 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3275 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3276 if (device->use_global_bo_list) {
3277 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3278 }
3279 }
3280
3281 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3282 domain, flags, priority);
3283
3284 if (!mem->bo) {
3285 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3286 goto fail;
3287 }
3288 mem->type_index = mem_type_index;
3289 }
3290
3291 result = radv_bo_list_add(device, mem->bo);
3292 if (result != VK_SUCCESS)
3293 goto fail_bo;
3294
3295 *pMem = radv_device_memory_to_handle(mem);
3296
3297 return VK_SUCCESS;
3298
3299 fail_bo:
3300 device->ws->buffer_destroy(mem->bo);
3301 fail:
3302 vk_free2(&device->alloc, pAllocator, mem);
3303
3304 return result;
3305 }
3306
3307 VkResult radv_AllocateMemory(
3308 VkDevice _device,
3309 const VkMemoryAllocateInfo* pAllocateInfo,
3310 const VkAllocationCallbacks* pAllocator,
3311 VkDeviceMemory* pMem)
3312 {
3313 RADV_FROM_HANDLE(radv_device, device, _device);
3314 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3315 }
3316
3317 void radv_FreeMemory(
3318 VkDevice _device,
3319 VkDeviceMemory _mem,
3320 const VkAllocationCallbacks* pAllocator)
3321 {
3322 RADV_FROM_HANDLE(radv_device, device, _device);
3323 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3324
3325 if (mem == NULL)
3326 return;
3327
3328 radv_bo_list_remove(device, mem->bo);
3329 device->ws->buffer_destroy(mem->bo);
3330 mem->bo = NULL;
3331
3332 vk_free2(&device->alloc, pAllocator, mem);
3333 }
3334
3335 VkResult radv_MapMemory(
3336 VkDevice _device,
3337 VkDeviceMemory _memory,
3338 VkDeviceSize offset,
3339 VkDeviceSize size,
3340 VkMemoryMapFlags flags,
3341 void** ppData)
3342 {
3343 RADV_FROM_HANDLE(radv_device, device, _device);
3344 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3345
3346 if (mem == NULL) {
3347 *ppData = NULL;
3348 return VK_SUCCESS;
3349 }
3350
3351 if (mem->user_ptr)
3352 *ppData = mem->user_ptr;
3353 else
3354 *ppData = device->ws->buffer_map(mem->bo);
3355
3356 if (*ppData) {
3357 *ppData += offset;
3358 return VK_SUCCESS;
3359 }
3360
3361 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3362 }
3363
3364 void radv_UnmapMemory(
3365 VkDevice _device,
3366 VkDeviceMemory _memory)
3367 {
3368 RADV_FROM_HANDLE(radv_device, device, _device);
3369 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3370
3371 if (mem == NULL)
3372 return;
3373
3374 if (mem->user_ptr == NULL)
3375 device->ws->buffer_unmap(mem->bo);
3376 }
3377
3378 VkResult radv_FlushMappedMemoryRanges(
3379 VkDevice _device,
3380 uint32_t memoryRangeCount,
3381 const VkMappedMemoryRange* pMemoryRanges)
3382 {
3383 return VK_SUCCESS;
3384 }
3385
3386 VkResult radv_InvalidateMappedMemoryRanges(
3387 VkDevice _device,
3388 uint32_t memoryRangeCount,
3389 const VkMappedMemoryRange* pMemoryRanges)
3390 {
3391 return VK_SUCCESS;
3392 }
3393
3394 void radv_GetBufferMemoryRequirements(
3395 VkDevice _device,
3396 VkBuffer _buffer,
3397 VkMemoryRequirements* pMemoryRequirements)
3398 {
3399 RADV_FROM_HANDLE(radv_device, device, _device);
3400 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3401
3402 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3403
3404 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3405 pMemoryRequirements->alignment = 4096;
3406 else
3407 pMemoryRequirements->alignment = 16;
3408
3409 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3410 }
3411
3412 void radv_GetBufferMemoryRequirements2(
3413 VkDevice device,
3414 const VkBufferMemoryRequirementsInfo2 *pInfo,
3415 VkMemoryRequirements2 *pMemoryRequirements)
3416 {
3417 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3418 &pMemoryRequirements->memoryRequirements);
3419 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3420 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3421 switch (ext->sType) {
3422 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3423 VkMemoryDedicatedRequirements *req =
3424 (VkMemoryDedicatedRequirements *) ext;
3425 req->requiresDedicatedAllocation = buffer->shareable;
3426 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3427 break;
3428 }
3429 default:
3430 break;
3431 }
3432 }
3433 }
3434
3435 void radv_GetImageMemoryRequirements(
3436 VkDevice _device,
3437 VkImage _image,
3438 VkMemoryRequirements* pMemoryRequirements)
3439 {
3440 RADV_FROM_HANDLE(radv_device, device, _device);
3441 RADV_FROM_HANDLE(radv_image, image, _image);
3442
3443 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3444
3445 pMemoryRequirements->size = image->size;
3446 pMemoryRequirements->alignment = image->alignment;
3447 }
3448
3449 void radv_GetImageMemoryRequirements2(
3450 VkDevice device,
3451 const VkImageMemoryRequirementsInfo2 *pInfo,
3452 VkMemoryRequirements2 *pMemoryRequirements)
3453 {
3454 radv_GetImageMemoryRequirements(device, pInfo->image,
3455 &pMemoryRequirements->memoryRequirements);
3456
3457 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3458
3459 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3460 switch (ext->sType) {
3461 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3462 VkMemoryDedicatedRequirements *req =
3463 (VkMemoryDedicatedRequirements *) ext;
3464 req->requiresDedicatedAllocation = image->shareable;
3465 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3466 break;
3467 }
3468 default:
3469 break;
3470 }
3471 }
3472 }
3473
3474 void radv_GetImageSparseMemoryRequirements(
3475 VkDevice device,
3476 VkImage image,
3477 uint32_t* pSparseMemoryRequirementCount,
3478 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3479 {
3480 stub();
3481 }
3482
3483 void radv_GetImageSparseMemoryRequirements2(
3484 VkDevice device,
3485 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3486 uint32_t* pSparseMemoryRequirementCount,
3487 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3488 {
3489 stub();
3490 }
3491
3492 void radv_GetDeviceMemoryCommitment(
3493 VkDevice device,
3494 VkDeviceMemory memory,
3495 VkDeviceSize* pCommittedMemoryInBytes)
3496 {
3497 *pCommittedMemoryInBytes = 0;
3498 }
3499
3500 VkResult radv_BindBufferMemory2(VkDevice device,
3501 uint32_t bindInfoCount,
3502 const VkBindBufferMemoryInfo *pBindInfos)
3503 {
3504 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3505 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3506 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3507
3508 if (mem) {
3509 buffer->bo = mem->bo;
3510 buffer->offset = pBindInfos[i].memoryOffset;
3511 } else {
3512 buffer->bo = NULL;
3513 }
3514 }
3515 return VK_SUCCESS;
3516 }
3517
3518 VkResult radv_BindBufferMemory(
3519 VkDevice device,
3520 VkBuffer buffer,
3521 VkDeviceMemory memory,
3522 VkDeviceSize memoryOffset)
3523 {
3524 const VkBindBufferMemoryInfo info = {
3525 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3526 .buffer = buffer,
3527 .memory = memory,
3528 .memoryOffset = memoryOffset
3529 };
3530
3531 return radv_BindBufferMemory2(device, 1, &info);
3532 }
3533
3534 VkResult radv_BindImageMemory2(VkDevice device,
3535 uint32_t bindInfoCount,
3536 const VkBindImageMemoryInfo *pBindInfos)
3537 {
3538 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3539 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3540 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3541
3542 if (mem) {
3543 image->bo = mem->bo;
3544 image->offset = pBindInfos[i].memoryOffset;
3545 } else {
3546 image->bo = NULL;
3547 image->offset = 0;
3548 }
3549 }
3550 return VK_SUCCESS;
3551 }
3552
3553
3554 VkResult radv_BindImageMemory(
3555 VkDevice device,
3556 VkImage image,
3557 VkDeviceMemory memory,
3558 VkDeviceSize memoryOffset)
3559 {
3560 const VkBindImageMemoryInfo info = {
3561 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3562 .image = image,
3563 .memory = memory,
3564 .memoryOffset = memoryOffset
3565 };
3566
3567 return radv_BindImageMemory2(device, 1, &info);
3568 }
3569
3570
3571 static void
3572 radv_sparse_buffer_bind_memory(struct radv_device *device,
3573 const VkSparseBufferMemoryBindInfo *bind)
3574 {
3575 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3576
3577 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3578 struct radv_device_memory *mem = NULL;
3579
3580 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3581 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3582
3583 device->ws->buffer_virtual_bind(buffer->bo,
3584 bind->pBinds[i].resourceOffset,
3585 bind->pBinds[i].size,
3586 mem ? mem->bo : NULL,
3587 bind->pBinds[i].memoryOffset);
3588 }
3589 }
3590
3591 static void
3592 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3593 const VkSparseImageOpaqueMemoryBindInfo *bind)
3594 {
3595 RADV_FROM_HANDLE(radv_image, image, bind->image);
3596
3597 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3598 struct radv_device_memory *mem = NULL;
3599
3600 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3601 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3602
3603 device->ws->buffer_virtual_bind(image->bo,
3604 bind->pBinds[i].resourceOffset,
3605 bind->pBinds[i].size,
3606 mem ? mem->bo : NULL,
3607 bind->pBinds[i].memoryOffset);
3608 }
3609 }
3610
3611 VkResult radv_QueueBindSparse(
3612 VkQueue _queue,
3613 uint32_t bindInfoCount,
3614 const VkBindSparseInfo* pBindInfo,
3615 VkFence _fence)
3616 {
3617 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3618 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3619 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3620 bool fence_emitted = false;
3621 VkResult result;
3622 int ret;
3623
3624 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3625 struct radv_winsys_sem_info sem_info;
3626 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3627 radv_sparse_buffer_bind_memory(queue->device,
3628 pBindInfo[i].pBufferBinds + j);
3629 }
3630
3631 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3632 radv_sparse_image_opaque_bind_memory(queue->device,
3633 pBindInfo[i].pImageOpaqueBinds + j);
3634 }
3635
3636 VkResult result;
3637 result = radv_alloc_sem_info(queue->device->instance,
3638 &sem_info,
3639 pBindInfo[i].waitSemaphoreCount,
3640 pBindInfo[i].pWaitSemaphores,
3641 pBindInfo[i].signalSemaphoreCount,
3642 pBindInfo[i].pSignalSemaphores,
3643 _fence);
3644 if (result != VK_SUCCESS)
3645 return result;
3646
3647 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3648 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3649 &queue->device->empty_cs[queue->queue_family_index],
3650 1, NULL, NULL,
3651 &sem_info, NULL,
3652 false, base_fence);
3653 if (ret) {
3654 radv_loge("failed to submit CS %d\n", i);
3655 abort();
3656 }
3657
3658 fence_emitted = true;
3659 if (fence)
3660 fence->submitted = true;
3661 }
3662
3663 radv_free_sem_info(&sem_info);
3664
3665 }
3666
3667 if (fence) {
3668 if (!fence_emitted) {
3669 result = radv_signal_fence(queue, fence);
3670 if (result != VK_SUCCESS)
3671 return result;
3672 }
3673 fence->submitted = true;
3674 }
3675
3676 return VK_SUCCESS;
3677 }
3678
3679 VkResult radv_CreateFence(
3680 VkDevice _device,
3681 const VkFenceCreateInfo* pCreateInfo,
3682 const VkAllocationCallbacks* pAllocator,
3683 VkFence* pFence)
3684 {
3685 RADV_FROM_HANDLE(radv_device, device, _device);
3686 const VkExportFenceCreateInfo *export =
3687 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3688 VkExternalFenceHandleTypeFlags handleTypes =
3689 export ? export->handleTypes : 0;
3690
3691 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3692 sizeof(*fence), 8,
3693 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3694
3695 if (!fence)
3696 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3697
3698 fence->fence_wsi = NULL;
3699 fence->submitted = false;
3700 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3701 fence->temp_syncobj = 0;
3702 if (device->always_use_syncobj || handleTypes) {
3703 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3704 if (ret) {
3705 vk_free2(&device->alloc, pAllocator, fence);
3706 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3707 }
3708 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3709 device->ws->signal_syncobj(device->ws, fence->syncobj);
3710 }
3711 fence->fence = NULL;
3712 } else {
3713 fence->fence = device->ws->create_fence();
3714 if (!fence->fence) {
3715 vk_free2(&device->alloc, pAllocator, fence);
3716 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3717 }
3718 fence->syncobj = 0;
3719 }
3720
3721 *pFence = radv_fence_to_handle(fence);
3722
3723 return VK_SUCCESS;
3724 }
3725
3726 void radv_DestroyFence(
3727 VkDevice _device,
3728 VkFence _fence,
3729 const VkAllocationCallbacks* pAllocator)
3730 {
3731 RADV_FROM_HANDLE(radv_device, device, _device);
3732 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3733
3734 if (!fence)
3735 return;
3736
3737 if (fence->temp_syncobj)
3738 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3739 if (fence->syncobj)
3740 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3741 if (fence->fence)
3742 device->ws->destroy_fence(fence->fence);
3743 if (fence->fence_wsi)
3744 fence->fence_wsi->destroy(fence->fence_wsi);
3745 vk_free2(&device->alloc, pAllocator, fence);
3746 }
3747
3748
3749 uint64_t radv_get_current_time(void)
3750 {
3751 struct timespec tv;
3752 clock_gettime(CLOCK_MONOTONIC, &tv);
3753 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3754 }
3755
3756 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3757 {
3758 uint64_t current_time = radv_get_current_time();
3759
3760 timeout = MIN2(UINT64_MAX - current_time, timeout);
3761
3762 return current_time + timeout;
3763 }
3764
3765
3766 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3767 {
3768 for (uint32_t i = 0; i < fenceCount; ++i) {
3769 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3770 if (fence->fence == NULL || fence->syncobj ||
3771 fence->temp_syncobj ||
3772 (!fence->signalled && !fence->submitted))
3773 return false;
3774 }
3775 return true;
3776 }
3777
3778 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3779 {
3780 for (uint32_t i = 0; i < fenceCount; ++i) {
3781 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3782 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3783 return false;
3784 }
3785 return true;
3786 }
3787
3788 VkResult radv_WaitForFences(
3789 VkDevice _device,
3790 uint32_t fenceCount,
3791 const VkFence* pFences,
3792 VkBool32 waitAll,
3793 uint64_t timeout)
3794 {
3795 RADV_FROM_HANDLE(radv_device, device, _device);
3796 timeout = radv_get_absolute_timeout(timeout);
3797
3798 if (device->always_use_syncobj &&
3799 radv_all_fences_syncobj(fenceCount, pFences))
3800 {
3801 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3802 if (!handles)
3803 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3804
3805 for (uint32_t i = 0; i < fenceCount; ++i) {
3806 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3807 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3808 }
3809
3810 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3811
3812 free(handles);
3813 return success ? VK_SUCCESS : VK_TIMEOUT;
3814 }
3815
3816 if (!waitAll && fenceCount > 1) {
3817 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3818 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3819 uint32_t wait_count = 0;
3820 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3821 if (!fences)
3822 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3823
3824 for (uint32_t i = 0; i < fenceCount; ++i) {
3825 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3826
3827 if (fence->signalled) {
3828 free(fences);
3829 return VK_SUCCESS;
3830 }
3831
3832 fences[wait_count++] = fence->fence;
3833 }
3834
3835 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3836 waitAll, timeout - radv_get_current_time());
3837
3838 free(fences);
3839 return success ? VK_SUCCESS : VK_TIMEOUT;
3840 }
3841
3842 while(radv_get_current_time() <= timeout) {
3843 for (uint32_t i = 0; i < fenceCount; ++i) {
3844 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3845 return VK_SUCCESS;
3846 }
3847 }
3848 return VK_TIMEOUT;
3849 }
3850
3851 for (uint32_t i = 0; i < fenceCount; ++i) {
3852 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3853 bool expired = false;
3854
3855 if (fence->temp_syncobj) {
3856 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3857 return VK_TIMEOUT;
3858 continue;
3859 }
3860
3861 if (fence->syncobj) {
3862 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3863 return VK_TIMEOUT;
3864 continue;
3865 }
3866
3867 if (fence->signalled)
3868 continue;
3869
3870 if (fence->fence) {
3871 if (!fence->submitted) {
3872 while(radv_get_current_time() <= timeout &&
3873 !fence->submitted)
3874 /* Do nothing */;
3875
3876 if (!fence->submitted)
3877 return VK_TIMEOUT;
3878
3879 /* Recheck as it may have been set by
3880 * submitting operations. */
3881
3882 if (fence->signalled)
3883 continue;
3884 }
3885
3886 expired = device->ws->fence_wait(device->ws,
3887 fence->fence,
3888 true, timeout);
3889 if (!expired)
3890 return VK_TIMEOUT;
3891 }
3892
3893 if (fence->fence_wsi) {
3894 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3895 if (result != VK_SUCCESS)
3896 return result;
3897 }
3898
3899 fence->signalled = true;
3900 }
3901
3902 return VK_SUCCESS;
3903 }
3904
3905 VkResult radv_ResetFences(VkDevice _device,
3906 uint32_t fenceCount,
3907 const VkFence *pFences)
3908 {
3909 RADV_FROM_HANDLE(radv_device, device, _device);
3910
3911 for (unsigned i = 0; i < fenceCount; ++i) {
3912 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3913 fence->submitted = fence->signalled = false;
3914
3915 /* Per spec, we first restore the permanent payload, and then reset, so
3916 * having a temp syncobj should not skip resetting the permanent syncobj. */
3917 if (fence->temp_syncobj) {
3918 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3919 fence->temp_syncobj = 0;
3920 }
3921
3922 if (fence->syncobj) {
3923 device->ws->reset_syncobj(device->ws, fence->syncobj);
3924 }
3925 }
3926
3927 return VK_SUCCESS;
3928 }
3929
3930 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3931 {
3932 RADV_FROM_HANDLE(radv_device, device, _device);
3933 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3934
3935 if (fence->temp_syncobj) {
3936 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3937 return success ? VK_SUCCESS : VK_NOT_READY;
3938 }
3939
3940 if (fence->syncobj) {
3941 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3942 return success ? VK_SUCCESS : VK_NOT_READY;
3943 }
3944
3945 if (fence->signalled)
3946 return VK_SUCCESS;
3947 if (!fence->submitted)
3948 return VK_NOT_READY;
3949 if (fence->fence) {
3950 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3951 return VK_NOT_READY;
3952 }
3953 if (fence->fence_wsi) {
3954 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3955
3956 if (result != VK_SUCCESS) {
3957 if (result == VK_TIMEOUT)
3958 return VK_NOT_READY;
3959 return result;
3960 }
3961 }
3962 return VK_SUCCESS;
3963 }
3964
3965
3966 // Queue semaphore functions
3967
3968 VkResult radv_CreateSemaphore(
3969 VkDevice _device,
3970 const VkSemaphoreCreateInfo* pCreateInfo,
3971 const VkAllocationCallbacks* pAllocator,
3972 VkSemaphore* pSemaphore)
3973 {
3974 RADV_FROM_HANDLE(radv_device, device, _device);
3975 const VkExportSemaphoreCreateInfo *export =
3976 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3977 VkExternalSemaphoreHandleTypeFlags handleTypes =
3978 export ? export->handleTypes : 0;
3979
3980 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3981 sizeof(*sem), 8,
3982 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3983 if (!sem)
3984 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3985
3986 sem->temp_syncobj = 0;
3987 /* create a syncobject if we are going to export this semaphore */
3988 if (device->always_use_syncobj || handleTypes) {
3989 assert (device->physical_device->rad_info.has_syncobj);
3990 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3991 if (ret) {
3992 vk_free2(&device->alloc, pAllocator, sem);
3993 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3994 }
3995 sem->sem = NULL;
3996 } else {
3997 sem->sem = device->ws->create_sem(device->ws);
3998 if (!sem->sem) {
3999 vk_free2(&device->alloc, pAllocator, sem);
4000 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4001 }
4002 sem->syncobj = 0;
4003 }
4004
4005 *pSemaphore = radv_semaphore_to_handle(sem);
4006 return VK_SUCCESS;
4007 }
4008
4009 void radv_DestroySemaphore(
4010 VkDevice _device,
4011 VkSemaphore _semaphore,
4012 const VkAllocationCallbacks* pAllocator)
4013 {
4014 RADV_FROM_HANDLE(radv_device, device, _device);
4015 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4016 if (!_semaphore)
4017 return;
4018
4019 if (sem->syncobj)
4020 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4021 else
4022 device->ws->destroy_sem(sem->sem);
4023 vk_free2(&device->alloc, pAllocator, sem);
4024 }
4025
4026 VkResult radv_CreateEvent(
4027 VkDevice _device,
4028 const VkEventCreateInfo* pCreateInfo,
4029 const VkAllocationCallbacks* pAllocator,
4030 VkEvent* pEvent)
4031 {
4032 RADV_FROM_HANDLE(radv_device, device, _device);
4033 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4034 sizeof(*event), 8,
4035 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4036
4037 if (!event)
4038 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4039
4040 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4041 RADEON_DOMAIN_GTT,
4042 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4043 RADV_BO_PRIORITY_FENCE);
4044 if (!event->bo) {
4045 vk_free2(&device->alloc, pAllocator, event);
4046 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4047 }
4048
4049 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4050
4051 *pEvent = radv_event_to_handle(event);
4052
4053 return VK_SUCCESS;
4054 }
4055
4056 void radv_DestroyEvent(
4057 VkDevice _device,
4058 VkEvent _event,
4059 const VkAllocationCallbacks* pAllocator)
4060 {
4061 RADV_FROM_HANDLE(radv_device, device, _device);
4062 RADV_FROM_HANDLE(radv_event, event, _event);
4063
4064 if (!event)
4065 return;
4066 device->ws->buffer_destroy(event->bo);
4067 vk_free2(&device->alloc, pAllocator, event);
4068 }
4069
4070 VkResult radv_GetEventStatus(
4071 VkDevice _device,
4072 VkEvent _event)
4073 {
4074 RADV_FROM_HANDLE(radv_event, event, _event);
4075
4076 if (*event->map == 1)
4077 return VK_EVENT_SET;
4078 return VK_EVENT_RESET;
4079 }
4080
4081 VkResult radv_SetEvent(
4082 VkDevice _device,
4083 VkEvent _event)
4084 {
4085 RADV_FROM_HANDLE(radv_event, event, _event);
4086 *event->map = 1;
4087
4088 return VK_SUCCESS;
4089 }
4090
4091 VkResult radv_ResetEvent(
4092 VkDevice _device,
4093 VkEvent _event)
4094 {
4095 RADV_FROM_HANDLE(radv_event, event, _event);
4096 *event->map = 0;
4097
4098 return VK_SUCCESS;
4099 }
4100
4101 VkResult radv_CreateBuffer(
4102 VkDevice _device,
4103 const VkBufferCreateInfo* pCreateInfo,
4104 const VkAllocationCallbacks* pAllocator,
4105 VkBuffer* pBuffer)
4106 {
4107 RADV_FROM_HANDLE(radv_device, device, _device);
4108 struct radv_buffer *buffer;
4109
4110 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4111
4112 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4113 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4114 if (buffer == NULL)
4115 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4116
4117 buffer->size = pCreateInfo->size;
4118 buffer->usage = pCreateInfo->usage;
4119 buffer->bo = NULL;
4120 buffer->offset = 0;
4121 buffer->flags = pCreateInfo->flags;
4122
4123 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4124 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4125
4126 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4127 buffer->bo = device->ws->buffer_create(device->ws,
4128 align64(buffer->size, 4096),
4129 4096, 0, RADEON_FLAG_VIRTUAL,
4130 RADV_BO_PRIORITY_VIRTUAL);
4131 if (!buffer->bo) {
4132 vk_free2(&device->alloc, pAllocator, buffer);
4133 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4134 }
4135 }
4136
4137 *pBuffer = radv_buffer_to_handle(buffer);
4138
4139 return VK_SUCCESS;
4140 }
4141
4142 void radv_DestroyBuffer(
4143 VkDevice _device,
4144 VkBuffer _buffer,
4145 const VkAllocationCallbacks* pAllocator)
4146 {
4147 RADV_FROM_HANDLE(radv_device, device, _device);
4148 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4149
4150 if (!buffer)
4151 return;
4152
4153 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4154 device->ws->buffer_destroy(buffer->bo);
4155
4156 vk_free2(&device->alloc, pAllocator, buffer);
4157 }
4158
4159 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4160 VkDevice device,
4161 const VkBufferDeviceAddressInfoEXT* pInfo)
4162 {
4163 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4164 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4165 }
4166
4167
4168 static inline unsigned
4169 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4170 {
4171 if (stencil)
4172 return plane->surface.u.legacy.stencil_tiling_index[level];
4173 else
4174 return plane->surface.u.legacy.tiling_index[level];
4175 }
4176
4177 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4178 {
4179 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4180 }
4181
4182 static uint32_t
4183 radv_init_dcc_control_reg(struct radv_device *device,
4184 struct radv_image_view *iview)
4185 {
4186 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4187 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4188 unsigned max_compressed_block_size;
4189 unsigned independent_64b_blocks;
4190
4191 if (!radv_image_has_dcc(iview->image))
4192 return 0;
4193
4194 if (iview->image->info.samples > 1) {
4195 if (iview->image->planes[0].surface.bpe == 1)
4196 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4197 else if (iview->image->planes[0].surface.bpe == 2)
4198 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4199 }
4200
4201 if (!device->physical_device->rad_info.has_dedicated_vram) {
4202 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4203 * dGPU and 64 for APU because all of our APUs to date use
4204 * DIMMs which have a request granularity size of 64B while all
4205 * other chips have a 32B request size.
4206 */
4207 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4208 }
4209
4210 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4211 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4212 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4213 /* If this DCC image is potentially going to be used in texture
4214 * fetches, we need some special settings.
4215 */
4216 independent_64b_blocks = 1;
4217 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4218 } else {
4219 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4220 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4221 * big as possible for better compression state.
4222 */
4223 independent_64b_blocks = 0;
4224 max_compressed_block_size = max_uncompressed_block_size;
4225 }
4226
4227 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4228 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4229 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4230 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4231 }
4232
4233 static void
4234 radv_initialise_color_surface(struct radv_device *device,
4235 struct radv_color_buffer_info *cb,
4236 struct radv_image_view *iview)
4237 {
4238 const struct vk_format_description *desc;
4239 unsigned ntype, format, swap, endian;
4240 unsigned blend_clamp = 0, blend_bypass = 0;
4241 uint64_t va;
4242 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4243 const struct radeon_surf *surf = &plane->surface;
4244
4245 desc = vk_format_description(iview->vk_format);
4246
4247 memset(cb, 0, sizeof(*cb));
4248
4249 /* Intensity is implemented as Red, so treat it that way. */
4250 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4251
4252 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4253
4254 cb->cb_color_base = va >> 8;
4255
4256 if (device->physical_device->rad_info.chip_class >= GFX9) {
4257 struct gfx9_surf_meta_flags meta;
4258 if (iview->image->dcc_offset)
4259 meta = surf->u.gfx9.dcc;
4260 else
4261 meta = surf->u.gfx9.cmask;
4262
4263 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4264 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4265 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4266 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4267
4268 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4269 cb->cb_color_base |= surf->tile_swizzle;
4270
4271 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4272 } else {
4273 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4274 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4275
4276 cb->cb_color_base += level_info->offset >> 8;
4277 if (level_info->mode == RADEON_SURF_MODE_2D)
4278 cb->cb_color_base |= surf->tile_swizzle;
4279
4280 pitch_tile_max = level_info->nblk_x / 8 - 1;
4281 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4282 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4283
4284 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4285 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4286 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4287
4288 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4289
4290 if (radv_image_has_fmask(iview->image)) {
4291 if (device->physical_device->rad_info.chip_class >= CIK)
4292 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4293 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4294 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4295 } else {
4296 /* This must be set for fast clear to work without FMASK. */
4297 if (device->physical_device->rad_info.chip_class >= CIK)
4298 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4299 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4300 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4301 }
4302 }
4303
4304 /* CMASK variables */
4305 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4306 va += iview->image->cmask.offset;
4307 cb->cb_color_cmask = va >> 8;
4308
4309 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4310 va += iview->image->dcc_offset;
4311 cb->cb_dcc_base = va >> 8;
4312 cb->cb_dcc_base |= surf->tile_swizzle;
4313
4314 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4315 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4316 S_028C6C_SLICE_MAX(max_slice);
4317
4318 if (iview->image->info.samples > 1) {
4319 unsigned log_samples = util_logbase2(iview->image->info.samples);
4320
4321 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4322 S_028C74_NUM_FRAGMENTS(log_samples);
4323 }
4324
4325 if (radv_image_has_fmask(iview->image)) {
4326 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4327 cb->cb_color_fmask = va >> 8;
4328 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4329 } else {
4330 cb->cb_color_fmask = cb->cb_color_base;
4331 }
4332
4333 ntype = radv_translate_color_numformat(iview->vk_format,
4334 desc,
4335 vk_format_get_first_non_void_channel(iview->vk_format));
4336 format = radv_translate_colorformat(iview->vk_format);
4337 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4338 radv_finishme("Illegal color\n");
4339 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4340 endian = radv_colorformat_endian_swap(format);
4341
4342 /* blend clamp should be set for all NORM/SRGB types */
4343 if (ntype == V_028C70_NUMBER_UNORM ||
4344 ntype == V_028C70_NUMBER_SNORM ||
4345 ntype == V_028C70_NUMBER_SRGB)
4346 blend_clamp = 1;
4347
4348 /* set blend bypass according to docs if SINT/UINT or
4349 8/24 COLOR variants */
4350 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4351 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4352 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4353 blend_clamp = 0;
4354 blend_bypass = 1;
4355 }
4356 #if 0
4357 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4358 (format == V_028C70_COLOR_8 ||
4359 format == V_028C70_COLOR_8_8 ||
4360 format == V_028C70_COLOR_8_8_8_8))
4361 ->color_is_int8 = true;
4362 #endif
4363 cb->cb_color_info = S_028C70_FORMAT(format) |
4364 S_028C70_COMP_SWAP(swap) |
4365 S_028C70_BLEND_CLAMP(blend_clamp) |
4366 S_028C70_BLEND_BYPASS(blend_bypass) |
4367 S_028C70_SIMPLE_FLOAT(1) |
4368 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4369 ntype != V_028C70_NUMBER_SNORM &&
4370 ntype != V_028C70_NUMBER_SRGB &&
4371 format != V_028C70_COLOR_8_24 &&
4372 format != V_028C70_COLOR_24_8) |
4373 S_028C70_NUMBER_TYPE(ntype) |
4374 S_028C70_ENDIAN(endian);
4375 if (radv_image_has_fmask(iview->image)) {
4376 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4377 if (device->physical_device->rad_info.chip_class == SI) {
4378 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4379 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4380 }
4381 }
4382
4383 if (radv_image_has_cmask(iview->image) &&
4384 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4385 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4386
4387 if (radv_dcc_enabled(iview->image, iview->base_mip))
4388 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4389
4390 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4391
4392 /* This must be set for fast clear to work without FMASK. */
4393 if (!radv_image_has_fmask(iview->image) &&
4394 device->physical_device->rad_info.chip_class == SI) {
4395 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4396 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4397 }
4398
4399 if (device->physical_device->rad_info.chip_class >= GFX9) {
4400 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4401
4402 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4403 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4404 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4405 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4406
4407 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4408 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4409 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4410 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4411 S_028C68_MIP0_HEIGHT(height - 1) |
4412 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4413 }
4414 }
4415
4416 static unsigned
4417 radv_calc_decompress_on_z_planes(struct radv_device *device,
4418 struct radv_image_view *iview)
4419 {
4420 unsigned max_zplanes = 0;
4421
4422 assert(radv_image_is_tc_compat_htile(iview->image));
4423
4424 if (device->physical_device->rad_info.chip_class >= GFX9) {
4425 /* Default value for 32-bit depth surfaces. */
4426 max_zplanes = 4;
4427
4428 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4429 iview->image->info.samples > 1)
4430 max_zplanes = 2;
4431
4432 max_zplanes = max_zplanes + 1;
4433 } else {
4434 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4435 /* Do not enable Z plane compression for 16-bit depth
4436 * surfaces because isn't supported on GFX8. Only
4437 * 32-bit depth surfaces are supported by the hardware.
4438 * This allows to maintain shader compatibility and to
4439 * reduce the number of depth decompressions.
4440 */
4441 max_zplanes = 1;
4442 } else {
4443 if (iview->image->info.samples <= 1)
4444 max_zplanes = 5;
4445 else if (iview->image->info.samples <= 4)
4446 max_zplanes = 3;
4447 else
4448 max_zplanes = 2;
4449 }
4450 }
4451
4452 return max_zplanes;
4453 }
4454
4455 static void
4456 radv_initialise_ds_surface(struct radv_device *device,
4457 struct radv_ds_buffer_info *ds,
4458 struct radv_image_view *iview)
4459 {
4460 unsigned level = iview->base_mip;
4461 unsigned format, stencil_format;
4462 uint64_t va, s_offs, z_offs;
4463 bool stencil_only = false;
4464 const struct radv_image_plane *plane = &iview->image->planes[0];
4465 const struct radeon_surf *surf = &plane->surface;
4466
4467 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4468
4469 memset(ds, 0, sizeof(*ds));
4470 switch (iview->image->vk_format) {
4471 case VK_FORMAT_D24_UNORM_S8_UINT:
4472 case VK_FORMAT_X8_D24_UNORM_PACK32:
4473 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4474 ds->offset_scale = 2.0f;
4475 break;
4476 case VK_FORMAT_D16_UNORM:
4477 case VK_FORMAT_D16_UNORM_S8_UINT:
4478 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4479 ds->offset_scale = 4.0f;
4480 break;
4481 case VK_FORMAT_D32_SFLOAT:
4482 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4483 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4484 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4485 ds->offset_scale = 1.0f;
4486 break;
4487 case VK_FORMAT_S8_UINT:
4488 stencil_only = true;
4489 break;
4490 default:
4491 break;
4492 }
4493
4494 format = radv_translate_dbformat(iview->image->vk_format);
4495 stencil_format = surf->has_stencil ?
4496 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4497
4498 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4499 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4500 S_028008_SLICE_MAX(max_slice);
4501
4502 ds->db_htile_data_base = 0;
4503 ds->db_htile_surface = 0;
4504
4505 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4506 s_offs = z_offs = va;
4507
4508 if (device->physical_device->rad_info.chip_class >= GFX9) {
4509 assert(surf->u.gfx9.surf_offset == 0);
4510 s_offs += surf->u.gfx9.stencil_offset;
4511
4512 ds->db_z_info = S_028038_FORMAT(format) |
4513 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4514 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4515 S_028038_MAXMIP(iview->image->info.levels - 1) |
4516 S_028038_ZRANGE_PRECISION(1);
4517 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4518 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4519
4520 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4521 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4522 ds->db_depth_view |= S_028008_MIPID(level);
4523
4524 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4525 S_02801C_Y_MAX(iview->image->info.height - 1);
4526
4527 if (radv_htile_enabled(iview->image, level)) {
4528 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4529
4530 if (radv_image_is_tc_compat_htile(iview->image)) {
4531 unsigned max_zplanes =
4532 radv_calc_decompress_on_z_planes(device, iview);
4533
4534 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4535 S_028038_ITERATE_FLUSH(1);
4536 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4537 }
4538
4539 if (!surf->has_stencil)
4540 /* Use all of the htile_buffer for depth if there's no stencil. */
4541 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4542 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4543 iview->image->htile_offset;
4544 ds->db_htile_data_base = va >> 8;
4545 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4546 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4547 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4548 }
4549 } else {
4550 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4551
4552 if (stencil_only)
4553 level_info = &surf->u.legacy.stencil_level[level];
4554
4555 z_offs += surf->u.legacy.level[level].offset;
4556 s_offs += surf->u.legacy.stencil_level[level].offset;
4557
4558 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4559 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4560 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4561
4562 if (iview->image->info.samples > 1)
4563 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4564
4565 if (device->physical_device->rad_info.chip_class >= CIK) {
4566 struct radeon_info *info = &device->physical_device->rad_info;
4567 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4568 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4569 unsigned macro_index = surf->u.legacy.macro_tile_index;
4570 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4571 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4572 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4573
4574 if (stencil_only)
4575 tile_mode = stencil_tile_mode;
4576
4577 ds->db_depth_info |=
4578 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4579 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4580 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4581 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4582 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4583 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4584 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4585 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4586 } else {
4587 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4588 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4589 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4590 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4591 if (stencil_only)
4592 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4593 }
4594
4595 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4596 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4597 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4598
4599 if (radv_htile_enabled(iview->image, level)) {
4600 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4601
4602 if (!surf->has_stencil &&
4603 !radv_image_is_tc_compat_htile(iview->image))
4604 /* Use all of the htile_buffer for depth if there's no stencil. */
4605 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4606
4607 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4608 iview->image->htile_offset;
4609 ds->db_htile_data_base = va >> 8;
4610 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4611
4612 if (radv_image_is_tc_compat_htile(iview->image)) {
4613 unsigned max_zplanes =
4614 radv_calc_decompress_on_z_planes(device, iview);
4615
4616 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4617 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4618 }
4619 }
4620 }
4621
4622 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4623 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4624 }
4625
4626 VkResult radv_CreateFramebuffer(
4627 VkDevice _device,
4628 const VkFramebufferCreateInfo* pCreateInfo,
4629 const VkAllocationCallbacks* pAllocator,
4630 VkFramebuffer* pFramebuffer)
4631 {
4632 RADV_FROM_HANDLE(radv_device, device, _device);
4633 struct radv_framebuffer *framebuffer;
4634
4635 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4636
4637 size_t size = sizeof(*framebuffer) +
4638 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4639 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4640 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4641 if (framebuffer == NULL)
4642 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4643
4644 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4645 framebuffer->width = pCreateInfo->width;
4646 framebuffer->height = pCreateInfo->height;
4647 framebuffer->layers = pCreateInfo->layers;
4648 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4649 VkImageView _iview = pCreateInfo->pAttachments[i];
4650 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4651 framebuffer->attachments[i].attachment = iview;
4652 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4653 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4654 } else {
4655 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4656 }
4657 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4658 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4659 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4660 }
4661
4662 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4663 return VK_SUCCESS;
4664 }
4665
4666 void radv_DestroyFramebuffer(
4667 VkDevice _device,
4668 VkFramebuffer _fb,
4669 const VkAllocationCallbacks* pAllocator)
4670 {
4671 RADV_FROM_HANDLE(radv_device, device, _device);
4672 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4673
4674 if (!fb)
4675 return;
4676 vk_free2(&device->alloc, pAllocator, fb);
4677 }
4678
4679 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4680 {
4681 switch (address_mode) {
4682 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4683 return V_008F30_SQ_TEX_WRAP;
4684 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4685 return V_008F30_SQ_TEX_MIRROR;
4686 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4687 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4688 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4689 return V_008F30_SQ_TEX_CLAMP_BORDER;
4690 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4691 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4692 default:
4693 unreachable("illegal tex wrap mode");
4694 break;
4695 }
4696 }
4697
4698 static unsigned
4699 radv_tex_compare(VkCompareOp op)
4700 {
4701 switch (op) {
4702 case VK_COMPARE_OP_NEVER:
4703 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4704 case VK_COMPARE_OP_LESS:
4705 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4706 case VK_COMPARE_OP_EQUAL:
4707 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4708 case VK_COMPARE_OP_LESS_OR_EQUAL:
4709 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4710 case VK_COMPARE_OP_GREATER:
4711 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4712 case VK_COMPARE_OP_NOT_EQUAL:
4713 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4714 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4715 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4716 case VK_COMPARE_OP_ALWAYS:
4717 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4718 default:
4719 unreachable("illegal compare mode");
4720 break;
4721 }
4722 }
4723
4724 static unsigned
4725 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4726 {
4727 switch (filter) {
4728 case VK_FILTER_NEAREST:
4729 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4730 V_008F38_SQ_TEX_XY_FILTER_POINT);
4731 case VK_FILTER_LINEAR:
4732 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4733 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4734 case VK_FILTER_CUBIC_IMG:
4735 default:
4736 fprintf(stderr, "illegal texture filter");
4737 return 0;
4738 }
4739 }
4740
4741 static unsigned
4742 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4743 {
4744 switch (mode) {
4745 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4746 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4747 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4748 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4749 default:
4750 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4751 }
4752 }
4753
4754 static unsigned
4755 radv_tex_bordercolor(VkBorderColor bcolor)
4756 {
4757 switch (bcolor) {
4758 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4759 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4760 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4761 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4762 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4763 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4764 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4765 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4766 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4767 default:
4768 break;
4769 }
4770 return 0;
4771 }
4772
4773 static unsigned
4774 radv_tex_aniso_filter(unsigned filter)
4775 {
4776 if (filter < 2)
4777 return 0;
4778 if (filter < 4)
4779 return 1;
4780 if (filter < 8)
4781 return 2;
4782 if (filter < 16)
4783 return 3;
4784 return 4;
4785 }
4786
4787 static unsigned
4788 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4789 {
4790 switch (mode) {
4791 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4792 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4793 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4794 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4795 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4796 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4797 default:
4798 break;
4799 }
4800 return 0;
4801 }
4802
4803 static uint32_t
4804 radv_get_max_anisotropy(struct radv_device *device,
4805 const VkSamplerCreateInfo *pCreateInfo)
4806 {
4807 if (device->force_aniso >= 0)
4808 return device->force_aniso;
4809
4810 if (pCreateInfo->anisotropyEnable &&
4811 pCreateInfo->maxAnisotropy > 1.0f)
4812 return (uint32_t)pCreateInfo->maxAnisotropy;
4813
4814 return 0;
4815 }
4816
4817 static void
4818 radv_init_sampler(struct radv_device *device,
4819 struct radv_sampler *sampler,
4820 const VkSamplerCreateInfo *pCreateInfo)
4821 {
4822 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4823 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4824 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4825 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4826
4827 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4828 vk_find_struct_const(pCreateInfo->pNext,
4829 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4830 if (sampler_reduction)
4831 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4832
4833 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4834 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4835 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4836 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4837 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4838 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4839 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4840 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4841 S_008F30_DISABLE_CUBE_WRAP(0) |
4842 S_008F30_COMPAT_MODE(is_vi) |
4843 S_008F30_FILTER_MODE(filter_mode));
4844 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4845 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4846 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4847 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4848 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4849 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4850 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4851 S_008F38_MIP_POINT_PRECLAMP(0) |
4852 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4853 S_008F38_FILTER_PREC_FIX(1) |
4854 S_008F38_ANISO_OVERRIDE(is_vi));
4855 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4856 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4857 }
4858
4859 VkResult radv_CreateSampler(
4860 VkDevice _device,
4861 const VkSamplerCreateInfo* pCreateInfo,
4862 const VkAllocationCallbacks* pAllocator,
4863 VkSampler* pSampler)
4864 {
4865 RADV_FROM_HANDLE(radv_device, device, _device);
4866 struct radv_sampler *sampler;
4867
4868 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4869 vk_find_struct_const(pCreateInfo->pNext,
4870 SAMPLER_YCBCR_CONVERSION_INFO);
4871
4872 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4873
4874 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4875 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4876 if (!sampler)
4877 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4878
4879 radv_init_sampler(device, sampler, pCreateInfo);
4880
4881 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4882 *pSampler = radv_sampler_to_handle(sampler);
4883
4884 return VK_SUCCESS;
4885 }
4886
4887 void radv_DestroySampler(
4888 VkDevice _device,
4889 VkSampler _sampler,
4890 const VkAllocationCallbacks* pAllocator)
4891 {
4892 RADV_FROM_HANDLE(radv_device, device, _device);
4893 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4894
4895 if (!sampler)
4896 return;
4897 vk_free2(&device->alloc, pAllocator, sampler);
4898 }
4899
4900 /* vk_icd.h does not declare this function, so we declare it here to
4901 * suppress Wmissing-prototypes.
4902 */
4903 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4904 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4905
4906 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4907 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4908 {
4909 /* For the full details on loader interface versioning, see
4910 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4911 * What follows is a condensed summary, to help you navigate the large and
4912 * confusing official doc.
4913 *
4914 * - Loader interface v0 is incompatible with later versions. We don't
4915 * support it.
4916 *
4917 * - In loader interface v1:
4918 * - The first ICD entrypoint called by the loader is
4919 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4920 * entrypoint.
4921 * - The ICD must statically expose no other Vulkan symbol unless it is
4922 * linked with -Bsymbolic.
4923 * - Each dispatchable Vulkan handle created by the ICD must be
4924 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4925 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4926 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4927 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4928 * such loader-managed surfaces.
4929 *
4930 * - Loader interface v2 differs from v1 in:
4931 * - The first ICD entrypoint called by the loader is
4932 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4933 * statically expose this entrypoint.
4934 *
4935 * - Loader interface v3 differs from v2 in:
4936 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4937 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4938 * because the loader no longer does so.
4939 */
4940 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4941 return VK_SUCCESS;
4942 }
4943
4944 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4945 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4946 int *pFD)
4947 {
4948 RADV_FROM_HANDLE(radv_device, device, _device);
4949 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4950
4951 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4952
4953 /* At the moment, we support only the below handle types. */
4954 assert(pGetFdInfo->handleType ==
4955 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4956 pGetFdInfo->handleType ==
4957 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4958
4959 bool ret = radv_get_memory_fd(device, memory, pFD);
4960 if (ret == false)
4961 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4962 return VK_SUCCESS;
4963 }
4964
4965 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4966 VkExternalMemoryHandleTypeFlagBits handleType,
4967 int fd,
4968 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4969 {
4970 RADV_FROM_HANDLE(radv_device, device, _device);
4971
4972 switch (handleType) {
4973 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4974 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4975 return VK_SUCCESS;
4976
4977 default:
4978 /* The valid usage section for this function says:
4979 *
4980 * "handleType must not be one of the handle types defined as
4981 * opaque."
4982 *
4983 * So opaque handle types fall into the default "unsupported" case.
4984 */
4985 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4986 }
4987 }
4988
4989 static VkResult radv_import_opaque_fd(struct radv_device *device,
4990 int fd,
4991 uint32_t *syncobj)
4992 {
4993 uint32_t syncobj_handle = 0;
4994 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4995 if (ret != 0)
4996 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4997
4998 if (*syncobj)
4999 device->ws->destroy_syncobj(device->ws, *syncobj);
5000
5001 *syncobj = syncobj_handle;
5002 close(fd);
5003
5004 return VK_SUCCESS;
5005 }
5006
5007 static VkResult radv_import_sync_fd(struct radv_device *device,
5008 int fd,
5009 uint32_t *syncobj)
5010 {
5011 /* If we create a syncobj we do it locally so that if we have an error, we don't
5012 * leave a syncobj in an undetermined state in the fence. */
5013 uint32_t syncobj_handle = *syncobj;
5014 if (!syncobj_handle) {
5015 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5016 if (ret) {
5017 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5018 }
5019 }
5020
5021 if (fd == -1) {
5022 device->ws->signal_syncobj(device->ws, syncobj_handle);
5023 } else {
5024 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5025 if (ret != 0)
5026 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5027 }
5028
5029 *syncobj = syncobj_handle;
5030 if (fd != -1)
5031 close(fd);
5032
5033 return VK_SUCCESS;
5034 }
5035
5036 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5037 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5038 {
5039 RADV_FROM_HANDLE(radv_device, device, _device);
5040 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5041 uint32_t *syncobj_dst = NULL;
5042
5043 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5044 syncobj_dst = &sem->temp_syncobj;
5045 } else {
5046 syncobj_dst = &sem->syncobj;
5047 }
5048
5049 switch(pImportSemaphoreFdInfo->handleType) {
5050 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5051 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5052 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5053 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5054 default:
5055 unreachable("Unhandled semaphore handle type");
5056 }
5057 }
5058
5059 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5060 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5061 int *pFd)
5062 {
5063 RADV_FROM_HANDLE(radv_device, device, _device);
5064 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5065 int ret;
5066 uint32_t syncobj_handle;
5067
5068 if (sem->temp_syncobj)
5069 syncobj_handle = sem->temp_syncobj;
5070 else
5071 syncobj_handle = sem->syncobj;
5072
5073 switch(pGetFdInfo->handleType) {
5074 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5075 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5076 break;
5077 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5078 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5079 if (!ret) {
5080 if (sem->temp_syncobj) {
5081 close (sem->temp_syncobj);
5082 sem->temp_syncobj = 0;
5083 } else {
5084 device->ws->reset_syncobj(device->ws, syncobj_handle);
5085 }
5086 }
5087 break;
5088 default:
5089 unreachable("Unhandled semaphore handle type");
5090 }
5091
5092 if (ret)
5093 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5094 return VK_SUCCESS;
5095 }
5096
5097 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5098 VkPhysicalDevice physicalDevice,
5099 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5100 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5101 {
5102 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5103
5104 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5105 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5106 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5107 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5108 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5109 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5110 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5111 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5112 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5113 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5114 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5115 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5116 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5117 } else {
5118 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5119 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5120 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5121 }
5122 }
5123
5124 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5125 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5126 {
5127 RADV_FROM_HANDLE(radv_device, device, _device);
5128 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5129 uint32_t *syncobj_dst = NULL;
5130
5131
5132 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5133 syncobj_dst = &fence->temp_syncobj;
5134 } else {
5135 syncobj_dst = &fence->syncobj;
5136 }
5137
5138 switch(pImportFenceFdInfo->handleType) {
5139 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5140 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5141 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5142 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5143 default:
5144 unreachable("Unhandled fence handle type");
5145 }
5146 }
5147
5148 VkResult radv_GetFenceFdKHR(VkDevice _device,
5149 const VkFenceGetFdInfoKHR *pGetFdInfo,
5150 int *pFd)
5151 {
5152 RADV_FROM_HANDLE(radv_device, device, _device);
5153 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5154 int ret;
5155 uint32_t syncobj_handle;
5156
5157 if (fence->temp_syncobj)
5158 syncobj_handle = fence->temp_syncobj;
5159 else
5160 syncobj_handle = fence->syncobj;
5161
5162 switch(pGetFdInfo->handleType) {
5163 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5164 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5165 break;
5166 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5167 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5168 if (!ret) {
5169 if (fence->temp_syncobj) {
5170 close (fence->temp_syncobj);
5171 fence->temp_syncobj = 0;
5172 } else {
5173 device->ws->reset_syncobj(device->ws, syncobj_handle);
5174 }
5175 }
5176 break;
5177 default:
5178 unreachable("Unhandled fence handle type");
5179 }
5180
5181 if (ret)
5182 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5183 return VK_SUCCESS;
5184 }
5185
5186 void radv_GetPhysicalDeviceExternalFenceProperties(
5187 VkPhysicalDevice physicalDevice,
5188 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5189 VkExternalFenceProperties *pExternalFenceProperties)
5190 {
5191 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5192
5193 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5194 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5195 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5196 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5197 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5198 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5199 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5200 } else {
5201 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5202 pExternalFenceProperties->compatibleHandleTypes = 0;
5203 pExternalFenceProperties->externalFenceFeatures = 0;
5204 }
5205 }
5206
5207 VkResult
5208 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5209 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5210 const VkAllocationCallbacks* pAllocator,
5211 VkDebugReportCallbackEXT* pCallback)
5212 {
5213 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5214 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5215 pCreateInfo, pAllocator, &instance->alloc,
5216 pCallback);
5217 }
5218
5219 void
5220 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5221 VkDebugReportCallbackEXT _callback,
5222 const VkAllocationCallbacks* pAllocator)
5223 {
5224 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5225 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5226 _callback, pAllocator, &instance->alloc);
5227 }
5228
5229 void
5230 radv_DebugReportMessageEXT(VkInstance _instance,
5231 VkDebugReportFlagsEXT flags,
5232 VkDebugReportObjectTypeEXT objectType,
5233 uint64_t object,
5234 size_t location,
5235 int32_t messageCode,
5236 const char* pLayerPrefix,
5237 const char* pMessage)
5238 {
5239 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5240 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5241 object, location, messageCode, pLayerPrefix, pMessage);
5242 }
5243
5244 void
5245 radv_GetDeviceGroupPeerMemoryFeatures(
5246 VkDevice device,
5247 uint32_t heapIndex,
5248 uint32_t localDeviceIndex,
5249 uint32_t remoteDeviceIndex,
5250 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5251 {
5252 assert(localDeviceIndex == remoteDeviceIndex);
5253
5254 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5255 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5256 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5257 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5258 }
5259
5260 static const VkTimeDomainEXT radv_time_domains[] = {
5261 VK_TIME_DOMAIN_DEVICE_EXT,
5262 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5263 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5264 };
5265
5266 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5267 VkPhysicalDevice physicalDevice,
5268 uint32_t *pTimeDomainCount,
5269 VkTimeDomainEXT *pTimeDomains)
5270 {
5271 int d;
5272 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5273
5274 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5275 vk_outarray_append(&out, i) {
5276 *i = radv_time_domains[d];
5277 }
5278 }
5279
5280 return vk_outarray_status(&out);
5281 }
5282
5283 static uint64_t
5284 radv_clock_gettime(clockid_t clock_id)
5285 {
5286 struct timespec current;
5287 int ret;
5288
5289 ret = clock_gettime(clock_id, &current);
5290 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5291 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5292 if (ret < 0)
5293 return 0;
5294
5295 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5296 }
5297
5298 VkResult radv_GetCalibratedTimestampsEXT(
5299 VkDevice _device,
5300 uint32_t timestampCount,
5301 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5302 uint64_t *pTimestamps,
5303 uint64_t *pMaxDeviation)
5304 {
5305 RADV_FROM_HANDLE(radv_device, device, _device);
5306 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5307 int d;
5308 uint64_t begin, end;
5309 uint64_t max_clock_period = 0;
5310
5311 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5312
5313 for (d = 0; d < timestampCount; d++) {
5314 switch (pTimestampInfos[d].timeDomain) {
5315 case VK_TIME_DOMAIN_DEVICE_EXT:
5316 pTimestamps[d] = device->ws->query_value(device->ws,
5317 RADEON_TIMESTAMP);
5318 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5319 max_clock_period = MAX2(max_clock_period, device_period);
5320 break;
5321 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5322 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5323 max_clock_period = MAX2(max_clock_period, 1);
5324 break;
5325
5326 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5327 pTimestamps[d] = begin;
5328 break;
5329 default:
5330 pTimestamps[d] = 0;
5331 break;
5332 }
5333 }
5334
5335 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5336
5337 /*
5338 * The maximum deviation is the sum of the interval over which we
5339 * perform the sampling and the maximum period of any sampled
5340 * clock. That's because the maximum skew between any two sampled
5341 * clock edges is when the sampled clock with the largest period is
5342 * sampled at the end of that period but right at the beginning of the
5343 * sampling interval and some other clock is sampled right at the
5344 * begining of its sampling period and right at the end of the
5345 * sampling interval. Let's assume the GPU has the longest clock
5346 * period and that the application is sampling GPU and monotonic:
5347 *
5348 * s e
5349 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5350 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5351 *
5352 * g
5353 * 0 1 2 3
5354 * GPU -----_____-----_____-----_____-----_____
5355 *
5356 * m
5357 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5358 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5359 *
5360 * Interval <----------------->
5361 * Deviation <-------------------------->
5362 *
5363 * s = read(raw) 2
5364 * g = read(GPU) 1
5365 * m = read(monotonic) 2
5366 * e = read(raw) b
5367 *
5368 * We round the sample interval up by one tick to cover sampling error
5369 * in the interval clock
5370 */
5371
5372 uint64_t sample_interval = end - begin + 1;
5373
5374 *pMaxDeviation = sample_interval + max_clock_period;
5375
5376 return VK_SUCCESS;
5377 }