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radv: implement VK_EXT_sample_locations and disable it
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
121 }
122
123 static uint64_t
124 radv_get_visible_vram_size(struct radv_physical_device *device)
125 {
126 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
127 }
128
129 static uint64_t
130 radv_get_vram_size(struct radv_physical_device *device)
131 {
132 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
133 }
134
135 static void
136 radv_physical_device_init_mem_types(struct radv_physical_device *device)
137 {
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
139 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
140 uint64_t vram_size = radv_get_vram_size(device);
141 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
142 device->memory_properties.memoryHeapCount = 0;
143 if (vram_size > 0) {
144 vram_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
146 .size = vram_size,
147 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150 if (visible_vram_size) {
151 visible_vram_index = device->memory_properties.memoryHeapCount++;
152 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
153 .size = visible_vram_size,
154 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
155 };
156 }
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
162 };
163 }
164
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
166 unsigned type_count = 0;
167 if (vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
185 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
186 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
189 .heapIndex = visible_vram_index,
190 };
191 }
192 if (gart_index >= 0) {
193 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
194 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
195 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
198 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 .heapIndex = gart_index,
200 };
201 }
202 device->memory_properties.memoryTypeCount = type_count;
203 }
204
205 static void
206 radv_handle_env_var_force_family(struct radv_physical_device *device)
207 {
208 const char *family = getenv("RADV_FORCE_FAMILY");
209 unsigned i;
210
211 if (!family)
212 return;
213
214 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
215 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
216 /* Override family and chip_class. */
217 device->rad_info.family = i;
218
219 if (i >= CHIP_VEGA10)
220 device->rad_info.chip_class = GFX9;
221 else if (i >= CHIP_TONGA)
222 device->rad_info.chip_class = GFX8;
223 else if (i >= CHIP_BONAIRE)
224 device->rad_info.chip_class = GFX7;
225 else
226 device->rad_info.chip_class = GFX6;
227
228 return;
229 }
230 }
231
232 fprintf(stderr, "radv: Unknown family: %s\n", family);
233 exit(1);
234 }
235
236 static VkResult
237 radv_physical_device_init(struct radv_physical_device *device,
238 struct radv_instance *instance,
239 drmDevicePtr drm_device)
240 {
241 const char *path = drm_device->nodes[DRM_NODE_RENDER];
242 VkResult result;
243 drmVersionPtr version;
244 int fd;
245 int master_fd = -1;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0) {
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Could not open device '%s'", path);
251
252 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
253 }
254
255 version = drmGetVersion(fd);
256 if (!version) {
257 close(fd);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not get the kernel driver version for device '%s'", path);
261
262 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
263 "failed to get version %s: %m", path);
264 }
265
266 if (strcmp(version->name, "amdgpu")) {
267 drmFreeVersion(version);
268 close(fd);
269
270 if (instance->debug_flags & RADV_DEBUG_STARTUP)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
272
273 return VK_ERROR_INCOMPATIBLE_DRIVER;
274 }
275 drmFreeVersion(version);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Found compatible device '%s'.", path);
279
280 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 device->instance = instance;
282
283 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
284 instance->perftest_flags);
285 if (!device->ws) {
286 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
287 goto fail;
288 }
289
290 if (instance->enabled_extensions.KHR_display) {
291 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
292 if (master_fd >= 0) {
293 uint32_t accel_working = 0;
294 struct drm_amdgpu_info request = {
295 .return_pointer = (uintptr_t)&accel_working,
296 .return_size = sizeof(accel_working),
297 .query = AMDGPU_INFO_ACCEL_WORKING
298 };
299
300 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
301 close(master_fd);
302 master_fd = -1;
303 }
304 }
305 }
306
307 device->master_fd = master_fd;
308 device->local_fd = fd;
309 device->ws->query_info(device->ws, &device->rad_info);
310
311 radv_handle_env_var_force_family(device);
312
313 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
314
315 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
316 device->ws->destroy(device->ws);
317 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags =
324 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
325 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
326
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
329 */
330 char buf[VK_UUID_SIZE * 2 + 1];
331 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
332 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
333
334 if (device->rad_info.chip_class < GFX8 ||
335 device->rad_info.chip_class > GFX9)
336 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337
338 radv_get_driver_uuid(&device->driver_uuid);
339 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
340
341 if (device->rad_info.family == CHIP_STONEY ||
342 device->rad_info.chip_class >= GFX9) {
343 device->has_rbplus = true;
344 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
345 device->rad_info.family == CHIP_VEGA12 ||
346 device->rad_info.family == CHIP_RAVEN ||
347 device->rad_info.family == CHIP_RAVEN2;
348 }
349
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
351 * on GFX6.
352 */
353 device->has_clear_state = device->rad_info.chip_class >= GFX7;
354
355 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
356
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
359 device->rad_info.family == CHIP_RAVEN;
360
361 /* Out-of-order primitive rasterization. */
362 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
363 device->rad_info.max_se >= 2;
364 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
365 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
366
367 device->dcc_msaa_allowed =
368 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
369
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
371 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
372 (device->rad_info.chip_class >= GFX8 &&
373 device->rad_info.me_fw_feature >= 41);
374
375 radv_physical_device_init_mem_types(device);
376 radv_fill_device_extension_table(device, &device->supported_extensions);
377
378 device->bus_info = *drm_device->businfo.pci;
379
380 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
381 ac_print_gpu_info(&device->rad_info);
382
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
385 * semi-layers).
386 */
387 result = radv_init_wsi(device);
388 if (result != VK_SUCCESS) {
389 device->ws->destroy(device->ws);
390 vk_error(instance, result);
391 goto fail;
392 }
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {"nobinning", RADV_DEBUG_NOBINNING},
466 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
482 {"bolist", RADV_PERFTEST_BO_LIST},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
514 /* Workaround for a WaW hazard when LLVM moves/merges
515 * load/store memory operations.
516 * See https://reviews.llvm.org/D61313
517 */
518 if (HAVE_LLVM < 0x900)
519 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
520 }
521 }
522
523 static int radv_get_instance_extension_index(const char *name)
524 {
525 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
526 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
527 return i;
528 }
529 return -1;
530 }
531
532 static const char radv_dri_options_xml[] =
533 DRI_CONF_BEGIN
534 DRI_CONF_SECTION_QUALITY
535 DRI_CONF_ADAPTIVE_SYNC("true")
536 DRI_CONF_SECTION_END
537 DRI_CONF_END;
538
539 static void radv_init_dri_options(struct radv_instance *instance)
540 {
541 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
542 driParseConfigFiles(&instance->dri_options,
543 &instance->available_dri_options,
544 0, "radv", NULL);
545 }
546
547 VkResult radv_CreateInstance(
548 const VkInstanceCreateInfo* pCreateInfo,
549 const VkAllocationCallbacks* pAllocator,
550 VkInstance* pInstance)
551 {
552 struct radv_instance *instance;
553 VkResult result;
554
555 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
556
557 uint32_t client_version;
558 if (pCreateInfo->pApplicationInfo &&
559 pCreateInfo->pApplicationInfo->apiVersion != 0) {
560 client_version = pCreateInfo->pApplicationInfo->apiVersion;
561 } else {
562 client_version = VK_API_VERSION_1_0;
563 }
564
565 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
566 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
567 if (!instance)
568 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
569
570 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
571
572 if (pAllocator)
573 instance->alloc = *pAllocator;
574 else
575 instance->alloc = default_alloc;
576
577 instance->apiVersion = client_version;
578 instance->physicalDeviceCount = -1;
579
580 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
581 radv_debug_options);
582
583 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
584 radv_perftest_options);
585
586
587 if (instance->debug_flags & RADV_DEBUG_STARTUP)
588 radv_logi("Created an instance");
589
590 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
591 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
592 int index = radv_get_instance_extension_index(ext_name);
593
594 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
595 vk_free2(&default_alloc, pAllocator, instance);
596 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
597 }
598
599 instance->enabled_extensions.extensions[index] = true;
600 }
601
602 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
603 if (result != VK_SUCCESS) {
604 vk_free2(&default_alloc, pAllocator, instance);
605 return vk_error(instance, result);
606 }
607
608 _mesa_locale_init();
609 glsl_type_singleton_init_or_ref();
610
611 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
612
613 radv_init_dri_options(instance);
614 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
615
616 *pInstance = radv_instance_to_handle(instance);
617
618 return VK_SUCCESS;
619 }
620
621 void radv_DestroyInstance(
622 VkInstance _instance,
623 const VkAllocationCallbacks* pAllocator)
624 {
625 RADV_FROM_HANDLE(radv_instance, instance, _instance);
626
627 if (!instance)
628 return;
629
630 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
631 radv_physical_device_finish(instance->physicalDevices + i);
632 }
633
634 VG(VALGRIND_DESTROY_MEMPOOL(instance));
635
636 glsl_type_singleton_decref();
637 _mesa_locale_fini();
638
639 driDestroyOptionCache(&instance->dri_options);
640 driDestroyOptionInfo(&instance->available_dri_options);
641
642 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
643
644 vk_free(&instance->alloc, instance);
645 }
646
647 static VkResult
648 radv_enumerate_devices(struct radv_instance *instance)
649 {
650 /* TODO: Check for more devices ? */
651 drmDevicePtr devices[8];
652 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
653 int max_devices;
654
655 instance->physicalDeviceCount = 0;
656
657 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
658
659 if (instance->debug_flags & RADV_DEBUG_STARTUP)
660 radv_logi("Found %d drm nodes", max_devices);
661
662 if (max_devices < 1)
663 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
664
665 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
666 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
667 devices[i]->bustype == DRM_BUS_PCI &&
668 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
669
670 result = radv_physical_device_init(instance->physicalDevices +
671 instance->physicalDeviceCount,
672 instance,
673 devices[i]);
674 if (result == VK_SUCCESS)
675 ++instance->physicalDeviceCount;
676 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
677 break;
678 }
679 }
680 drmFreeDevices(devices, max_devices);
681
682 return result;
683 }
684
685 VkResult radv_EnumeratePhysicalDevices(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceCount,
688 VkPhysicalDevice* pPhysicalDevices)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDevices) {
701 *pPhysicalDeviceCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
705 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
706 }
707
708 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
709 : VK_SUCCESS;
710 }
711
712 VkResult radv_EnumeratePhysicalDeviceGroups(
713 VkInstance _instance,
714 uint32_t* pPhysicalDeviceGroupCount,
715 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
716 {
717 RADV_FROM_HANDLE(radv_instance, instance, _instance);
718 VkResult result;
719
720 if (instance->physicalDeviceCount < 0) {
721 result = radv_enumerate_devices(instance);
722 if (result != VK_SUCCESS &&
723 result != VK_ERROR_INCOMPATIBLE_DRIVER)
724 return result;
725 }
726
727 if (!pPhysicalDeviceGroupProperties) {
728 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
729 } else {
730 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
731 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
732 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
733 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
734 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
735 }
736 }
737 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
738 : VK_SUCCESS;
739 }
740
741 void radv_GetPhysicalDeviceFeatures(
742 VkPhysicalDevice physicalDevice,
743 VkPhysicalDeviceFeatures* pFeatures)
744 {
745 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
746 memset(pFeatures, 0, sizeof(*pFeatures));
747
748 *pFeatures = (VkPhysicalDeviceFeatures) {
749 .robustBufferAccess = true,
750 .fullDrawIndexUint32 = true,
751 .imageCubeArray = true,
752 .independentBlend = true,
753 .geometryShader = true,
754 .tessellationShader = true,
755 .sampleRateShading = true,
756 .dualSrcBlend = true,
757 .logicOp = true,
758 .multiDrawIndirect = true,
759 .drawIndirectFirstInstance = true,
760 .depthClamp = true,
761 .depthBiasClamp = true,
762 .fillModeNonSolid = true,
763 .depthBounds = true,
764 .wideLines = true,
765 .largePoints = true,
766 .alphaToOne = true,
767 .multiViewport = true,
768 .samplerAnisotropy = true,
769 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
770 .textureCompressionASTC_LDR = false,
771 .textureCompressionBC = true,
772 .occlusionQueryPrecise = true,
773 .pipelineStatisticsQuery = true,
774 .vertexPipelineStoresAndAtomics = true,
775 .fragmentStoresAndAtomics = true,
776 .shaderTessellationAndGeometryPointSize = true,
777 .shaderImageGatherExtended = true,
778 .shaderStorageImageExtendedFormats = true,
779 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
780 .shaderUniformBufferArrayDynamicIndexing = true,
781 .shaderSampledImageArrayDynamicIndexing = true,
782 .shaderStorageBufferArrayDynamicIndexing = true,
783 .shaderStorageImageArrayDynamicIndexing = true,
784 .shaderStorageImageReadWithoutFormat = true,
785 .shaderStorageImageWriteWithoutFormat = true,
786 .shaderClipDistance = true,
787 .shaderCullDistance = true,
788 .shaderFloat64 = true,
789 .shaderInt64 = true,
790 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
791 .sparseBinding = true,
792 .variableMultisampleRate = true,
793 .inheritedQueries = true,
794 };
795 }
796
797 void radv_GetPhysicalDeviceFeatures2(
798 VkPhysicalDevice physicalDevice,
799 VkPhysicalDeviceFeatures2 *pFeatures)
800 {
801 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
802 vk_foreach_struct(ext, pFeatures->pNext) {
803 switch (ext->sType) {
804 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
805 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
806 features->variablePointersStorageBuffer = true;
807 features->variablePointers = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
811 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
812 features->multiview = true;
813 features->multiviewGeometryShader = true;
814 features->multiviewTessellationShader = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
818 VkPhysicalDeviceShaderDrawParametersFeatures *features =
819 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
820 features->shaderDrawParameters = true;
821 break;
822 }
823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
824 VkPhysicalDeviceProtectedMemoryFeatures *features =
825 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
826 features->protectedMemory = false;
827 break;
828 }
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
830 VkPhysicalDevice16BitStorageFeatures *features =
831 (VkPhysicalDevice16BitStorageFeatures*)ext;
832 bool enabled = pdevice->rad_info.chip_class >= GFX8;
833 features->storageBuffer16BitAccess = enabled;
834 features->uniformAndStorageBuffer16BitAccess = enabled;
835 features->storagePushConstant16 = enabled;
836 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
840 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
841 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
842 features->samplerYcbcrConversion = true;
843 break;
844 }
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
846 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
847 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
848 features->shaderInputAttachmentArrayDynamicIndexing = true;
849 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
850 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
851 features->shaderUniformBufferArrayNonUniformIndexing = true;
852 features->shaderSampledImageArrayNonUniformIndexing = true;
853 features->shaderStorageBufferArrayNonUniformIndexing = true;
854 features->shaderStorageImageArrayNonUniformIndexing = true;
855 features->shaderInputAttachmentArrayNonUniformIndexing = true;
856 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
857 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
858 features->descriptorBindingUniformBufferUpdateAfterBind = true;
859 features->descriptorBindingSampledImageUpdateAfterBind = true;
860 features->descriptorBindingStorageImageUpdateAfterBind = true;
861 features->descriptorBindingStorageBufferUpdateAfterBind = true;
862 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
863 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
864 features->descriptorBindingUpdateUnusedWhilePending = true;
865 features->descriptorBindingPartiallyBound = true;
866 features->descriptorBindingVariableDescriptorCount = true;
867 features->runtimeDescriptorArray = true;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
871 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
872 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
873 features->conditionalRendering = true;
874 features->inheritedConditionalRendering = false;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
878 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
879 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
880 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
881 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
885 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
886 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
887 features->transformFeedback = true;
888 features->geometryStreams = true;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
892 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
893 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
894 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
895 break;
896 }
897 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
898 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
899 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
900 features->memoryPriority = VK_TRUE;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
904 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
905 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
906 features->bufferDeviceAddress = true;
907 features->bufferDeviceAddressCaptureReplay = false;
908 features->bufferDeviceAddressMultiDevice = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
912 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
913 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
914 features->depthClipEnable = true;
915 break;
916 }
917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
918 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
919 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
920 features->hostQueryReset = true;
921 break;
922 }
923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
924 VkPhysicalDevice8BitStorageFeaturesKHR *features =
925 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
926 bool enabled = pdevice->rad_info.chip_class >= GFX8;
927 features->storageBuffer8BitAccess = enabled;
928 features->uniformAndStorageBuffer8BitAccess = enabled;
929 features->storagePushConstant8 = enabled;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
933 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
934 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
935 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
936 features->shaderInt8 = true;
937 break;
938 }
939 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
940 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
941 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
942 /* TODO: Enable this once the driver supports 64-bit
943 * compare&swap atomic operations.
944 */
945 features->shaderBufferInt64Atomics = false;
946 features->shaderSharedInt64Atomics = false;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
950 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
951 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
952
953 features->inlineUniformBlock = true;
954 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
958 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
959 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
960 features->computeDerivativeGroupQuads = false;
961 features->computeDerivativeGroupLinear = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
965 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
966 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
967 features->ycbcrImageArrays = true;
968 break;
969 }
970 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
971 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
972 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
973 features->uniformBufferStandardLayout = true;
974 break;
975 }
976 default:
977 break;
978 }
979 }
980 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
981 }
982
983 void radv_GetPhysicalDeviceProperties(
984 VkPhysicalDevice physicalDevice,
985 VkPhysicalDeviceProperties* pProperties)
986 {
987 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
988 VkSampleCountFlags sample_counts = 0xf;
989
990 /* make sure that the entire descriptor set is addressable with a signed
991 * 32-bit int. So the sum of all limits scaled by descriptor size has to
992 * be at most 2 GiB. the combined image & samples object count as one of
993 * both. This limit is for the pipeline layout, not for the set layout, but
994 * there is no set limit, so we just set a pipeline limit. I don't think
995 * any app is going to hit this soon. */
996 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
997 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
998 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
999 32 /* sampler, largest when combined with image */ +
1000 64 /* sampled image */ +
1001 64 /* storage image */);
1002
1003 VkPhysicalDeviceLimits limits = {
1004 .maxImageDimension1D = (1 << 14),
1005 .maxImageDimension2D = (1 << 14),
1006 .maxImageDimension3D = (1 << 11),
1007 .maxImageDimensionCube = (1 << 14),
1008 .maxImageArrayLayers = (1 << 11),
1009 .maxTexelBufferElements = 128 * 1024 * 1024,
1010 .maxUniformBufferRange = UINT32_MAX,
1011 .maxStorageBufferRange = UINT32_MAX,
1012 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1013 .maxMemoryAllocationCount = UINT32_MAX,
1014 .maxSamplerAllocationCount = 64 * 1024,
1015 .bufferImageGranularity = 64, /* A cache line */
1016 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1017 .maxBoundDescriptorSets = MAX_SETS,
1018 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1019 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1020 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1021 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1022 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1023 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1024 .maxPerStageResources = max_descriptor_set_size,
1025 .maxDescriptorSetSamplers = max_descriptor_set_size,
1026 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1027 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1028 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1029 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1030 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1031 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1032 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1033 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1034 .maxVertexInputBindings = MAX_VBS,
1035 .maxVertexInputAttributeOffset = 2047,
1036 .maxVertexInputBindingStride = 2048,
1037 .maxVertexOutputComponents = 128,
1038 .maxTessellationGenerationLevel = 64,
1039 .maxTessellationPatchSize = 32,
1040 .maxTessellationControlPerVertexInputComponents = 128,
1041 .maxTessellationControlPerVertexOutputComponents = 128,
1042 .maxTessellationControlPerPatchOutputComponents = 120,
1043 .maxTessellationControlTotalOutputComponents = 4096,
1044 .maxTessellationEvaluationInputComponents = 128,
1045 .maxTessellationEvaluationOutputComponents = 128,
1046 .maxGeometryShaderInvocations = 127,
1047 .maxGeometryInputComponents = 64,
1048 .maxGeometryOutputComponents = 128,
1049 .maxGeometryOutputVertices = 256,
1050 .maxGeometryTotalOutputComponents = 1024,
1051 .maxFragmentInputComponents = 128,
1052 .maxFragmentOutputAttachments = 8,
1053 .maxFragmentDualSrcAttachments = 1,
1054 .maxFragmentCombinedOutputResources = 8,
1055 .maxComputeSharedMemorySize = 32768,
1056 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1057 .maxComputeWorkGroupInvocations = 2048,
1058 .maxComputeWorkGroupSize = {
1059 2048,
1060 2048,
1061 2048
1062 },
1063 .subPixelPrecisionBits = 8,
1064 .subTexelPrecisionBits = 8,
1065 .mipmapPrecisionBits = 8,
1066 .maxDrawIndexedIndexValue = UINT32_MAX,
1067 .maxDrawIndirectCount = UINT32_MAX,
1068 .maxSamplerLodBias = 16,
1069 .maxSamplerAnisotropy = 16,
1070 .maxViewports = MAX_VIEWPORTS,
1071 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1072 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1073 .viewportSubPixelBits = 8,
1074 .minMemoryMapAlignment = 4096, /* A page */
1075 .minTexelBufferOffsetAlignment = 1,
1076 .minUniformBufferOffsetAlignment = 4,
1077 .minStorageBufferOffsetAlignment = 4,
1078 .minTexelOffset = -32,
1079 .maxTexelOffset = 31,
1080 .minTexelGatherOffset = -32,
1081 .maxTexelGatherOffset = 31,
1082 .minInterpolationOffset = -2,
1083 .maxInterpolationOffset = 2,
1084 .subPixelInterpolationOffsetBits = 8,
1085 .maxFramebufferWidth = (1 << 14),
1086 .maxFramebufferHeight = (1 << 14),
1087 .maxFramebufferLayers = (1 << 10),
1088 .framebufferColorSampleCounts = sample_counts,
1089 .framebufferDepthSampleCounts = sample_counts,
1090 .framebufferStencilSampleCounts = sample_counts,
1091 .framebufferNoAttachmentsSampleCounts = sample_counts,
1092 .maxColorAttachments = MAX_RTS,
1093 .sampledImageColorSampleCounts = sample_counts,
1094 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1095 .sampledImageDepthSampleCounts = sample_counts,
1096 .sampledImageStencilSampleCounts = sample_counts,
1097 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1098 .maxSampleMaskWords = 1,
1099 .timestampComputeAndGraphics = true,
1100 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1101 .maxClipDistances = 8,
1102 .maxCullDistances = 8,
1103 .maxCombinedClipAndCullDistances = 8,
1104 .discreteQueuePriorities = 2,
1105 .pointSizeRange = { 0.0, 8192.0 },
1106 .lineWidthRange = { 0.0, 7.9921875 },
1107 .pointSizeGranularity = (1.0 / 8.0),
1108 .lineWidthGranularity = (1.0 / 128.0),
1109 .strictLines = false, /* FINISHME */
1110 .standardSampleLocations = true,
1111 .optimalBufferCopyOffsetAlignment = 128,
1112 .optimalBufferCopyRowPitchAlignment = 128,
1113 .nonCoherentAtomSize = 64,
1114 };
1115
1116 *pProperties = (VkPhysicalDeviceProperties) {
1117 .apiVersion = radv_physical_device_api_version(pdevice),
1118 .driverVersion = vk_get_driver_version(),
1119 .vendorID = ATI_VENDOR_ID,
1120 .deviceID = pdevice->rad_info.pci_id,
1121 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1122 .limits = limits,
1123 .sparseProperties = {0},
1124 };
1125
1126 strcpy(pProperties->deviceName, pdevice->name);
1127 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1128 }
1129
1130 void radv_GetPhysicalDeviceProperties2(
1131 VkPhysicalDevice physicalDevice,
1132 VkPhysicalDeviceProperties2 *pProperties)
1133 {
1134 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1135 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1136
1137 vk_foreach_struct(ext, pProperties->pNext) {
1138 switch (ext->sType) {
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1140 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1141 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1142 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1146 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1147 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1148 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1149 properties->deviceLUIDValid = false;
1150 break;
1151 }
1152 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1153 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1154 properties->maxMultiviewViewCount = MAX_VIEWS;
1155 properties->maxMultiviewInstanceIndex = INT_MAX;
1156 break;
1157 }
1158 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1159 VkPhysicalDevicePointClippingProperties *properties =
1160 (VkPhysicalDevicePointClippingProperties*)ext;
1161 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1162 break;
1163 }
1164 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1165 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1166 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1167 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1171 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1172 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1173 properties->minImportedHostPointerAlignment = 4096;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1177 VkPhysicalDeviceSubgroupProperties *properties =
1178 (VkPhysicalDeviceSubgroupProperties*)ext;
1179 properties->subgroupSize = 64;
1180 properties->supportedStages = VK_SHADER_STAGE_ALL;
1181 properties->supportedOperations =
1182 VK_SUBGROUP_FEATURE_BASIC_BIT |
1183 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1184 VK_SUBGROUP_FEATURE_QUAD_BIT |
1185 VK_SUBGROUP_FEATURE_VOTE_BIT;
1186 if (pdevice->rad_info.chip_class >= GFX8) {
1187 properties->supportedOperations |=
1188 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1189 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1190 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1191 }
1192 properties->quadOperationsInAllStages = true;
1193 break;
1194 }
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1196 VkPhysicalDeviceMaintenance3Properties *properties =
1197 (VkPhysicalDeviceMaintenance3Properties*)ext;
1198 /* Make sure everything is addressable by a signed 32-bit int, and
1199 * our largest descriptors are 96 bytes. */
1200 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1201 /* Our buffer size fields allow only this much */
1202 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1206 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1207 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1208 /* GFX6-8 only support single channel min/max filter. */
1209 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1210 properties->filterMinmaxSingleComponentFormats = true;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1214 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1215 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1216
1217 /* Shader engines. */
1218 properties->shaderEngineCount =
1219 pdevice->rad_info.max_se;
1220 properties->shaderArraysPerEngineCount =
1221 pdevice->rad_info.max_sh_per_se;
1222 properties->computeUnitsPerShaderArray =
1223 pdevice->rad_info.num_good_cu_per_sh;
1224 properties->simdPerComputeUnit = 4;
1225 properties->wavefrontsPerSimd =
1226 pdevice->rad_info.family == CHIP_TONGA ||
1227 pdevice->rad_info.family == CHIP_ICELAND ||
1228 pdevice->rad_info.family == CHIP_POLARIS10 ||
1229 pdevice->rad_info.family == CHIP_POLARIS11 ||
1230 pdevice->rad_info.family == CHIP_POLARIS12 ||
1231 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1232 properties->wavefrontSize = 64;
1233
1234 /* SGPR. */
1235 properties->sgprsPerSimd =
1236 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1237 properties->minSgprAllocation =
1238 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1239 properties->maxSgprAllocation =
1240 pdevice->rad_info.family == CHIP_TONGA ||
1241 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1242 properties->sgprAllocationGranularity =
1243 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1244
1245 /* VGPR. */
1246 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1247 properties->minVgprAllocation = 4;
1248 properties->maxVgprAllocation = 256;
1249 properties->vgprAllocationGranularity = 4;
1250 break;
1251 }
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1253 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1254 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1255 properties->maxVertexAttribDivisor = UINT32_MAX;
1256 break;
1257 }
1258 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1259 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1260 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1261 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1262 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1263 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1264 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1265 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1266 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1267 properties->robustBufferAccessUpdateAfterBind = false;
1268 properties->quadDivergentImplicitLod = false;
1269
1270 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1271 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1272 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1273 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1274 32 /* sampler, largest when combined with image */ +
1275 64 /* sampled image */ +
1276 64 /* storage image */);
1277 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1278 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1279 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1280 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1281 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1282 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1283 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1284 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1285 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1286 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1287 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1288 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1289 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1290 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1292 break;
1293 }
1294 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1295 VkPhysicalDeviceProtectedMemoryProperties *properties =
1296 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1297 properties->protectedNoFault = false;
1298 break;
1299 }
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1301 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1302 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1303 properties->primitiveOverestimationSize = 0;
1304 properties->maxExtraPrimitiveOverestimationSize = 0;
1305 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1306 properties->primitiveUnderestimation = VK_FALSE;
1307 properties->conservativePointAndLineRasterization = VK_FALSE;
1308 properties->degenerateTrianglesRasterized = VK_FALSE;
1309 properties->degenerateLinesRasterized = VK_FALSE;
1310 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1311 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1312 break;
1313 }
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1315 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1316 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1317 properties->pciDomain = pdevice->bus_info.domain;
1318 properties->pciBus = pdevice->bus_info.bus;
1319 properties->pciDevice = pdevice->bus_info.dev;
1320 properties->pciFunction = pdevice->bus_info.func;
1321 break;
1322 }
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1324 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1325 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1326
1327 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1328 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1329 strcpy(driver_props->driverName, "radv");
1330
1331 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1332 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1333 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1334 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1335
1336 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1337 .major = 1,
1338 .minor = 1,
1339 .subminor = 2,
1340 .patch = 0,
1341 };
1342 break;
1343 }
1344 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1345 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1346 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1347 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1348 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1349 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1350 properties->maxTransformFeedbackStreamDataSize = 512;
1351 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1352 properties->maxTransformFeedbackBufferDataStride = 512;
1353 properties->transformFeedbackQueries = true;
1354 properties->transformFeedbackStreamsLinesTriangles = false;
1355 properties->transformFeedbackRasterizationStreamSelect = false;
1356 properties->transformFeedbackDraw = true;
1357 break;
1358 }
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1360 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1361 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1362
1363 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1364 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1365 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1366 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1367 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1368 break;
1369 }
1370 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1371 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1372 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1373 /* TODO: The ext is currently disabled because the
1374 * driver needs to handle sample locations during
1375 * layout transitions for depth/stencil surfaces and
1376 * HTILE.
1377 */
1378 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1379 /*
1380 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1381 VK_SAMPLE_COUNT_4_BIT |
1382 VK_SAMPLE_COUNT_8_BIT;
1383 */
1384 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1385 properties->sampleLocationCoordinateRange[0] = 0.0f;
1386 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1387 properties->sampleLocationSubPixelBits = 4;
1388 properties->variableSampleLocations = VK_FALSE;
1389 break;
1390 }
1391 default:
1392 break;
1393 }
1394 }
1395 }
1396
1397 static void radv_get_physical_device_queue_family_properties(
1398 struct radv_physical_device* pdevice,
1399 uint32_t* pCount,
1400 VkQueueFamilyProperties** pQueueFamilyProperties)
1401 {
1402 int num_queue_families = 1;
1403 int idx;
1404 if (pdevice->rad_info.num_compute_rings > 0 &&
1405 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1406 num_queue_families++;
1407
1408 if (pQueueFamilyProperties == NULL) {
1409 *pCount = num_queue_families;
1410 return;
1411 }
1412
1413 if (!*pCount)
1414 return;
1415
1416 idx = 0;
1417 if (*pCount >= 1) {
1418 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1419 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1420 VK_QUEUE_COMPUTE_BIT |
1421 VK_QUEUE_TRANSFER_BIT |
1422 VK_QUEUE_SPARSE_BINDING_BIT,
1423 .queueCount = 1,
1424 .timestampValidBits = 64,
1425 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1426 };
1427 idx++;
1428 }
1429
1430 if (pdevice->rad_info.num_compute_rings > 0 &&
1431 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1432 if (*pCount > idx) {
1433 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1434 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1435 VK_QUEUE_TRANSFER_BIT |
1436 VK_QUEUE_SPARSE_BINDING_BIT,
1437 .queueCount = pdevice->rad_info.num_compute_rings,
1438 .timestampValidBits = 64,
1439 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1440 };
1441 idx++;
1442 }
1443 }
1444 *pCount = idx;
1445 }
1446
1447 void radv_GetPhysicalDeviceQueueFamilyProperties(
1448 VkPhysicalDevice physicalDevice,
1449 uint32_t* pCount,
1450 VkQueueFamilyProperties* pQueueFamilyProperties)
1451 {
1452 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1453 if (!pQueueFamilyProperties) {
1454 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1455 return;
1456 }
1457 VkQueueFamilyProperties *properties[] = {
1458 pQueueFamilyProperties + 0,
1459 pQueueFamilyProperties + 1,
1460 pQueueFamilyProperties + 2,
1461 };
1462 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1463 assert(*pCount <= 3);
1464 }
1465
1466 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1467 VkPhysicalDevice physicalDevice,
1468 uint32_t* pCount,
1469 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1470 {
1471 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1472 if (!pQueueFamilyProperties) {
1473 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1474 return;
1475 }
1476 VkQueueFamilyProperties *properties[] = {
1477 &pQueueFamilyProperties[0].queueFamilyProperties,
1478 &pQueueFamilyProperties[1].queueFamilyProperties,
1479 &pQueueFamilyProperties[2].queueFamilyProperties,
1480 };
1481 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1482 assert(*pCount <= 3);
1483 }
1484
1485 void radv_GetPhysicalDeviceMemoryProperties(
1486 VkPhysicalDevice physicalDevice,
1487 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1488 {
1489 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1490
1491 *pMemoryProperties = physical_device->memory_properties;
1492 }
1493
1494 static void
1495 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1496 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1497 {
1498 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1499 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1500 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1501 uint64_t vram_size = radv_get_vram_size(device);
1502 uint64_t gtt_size = device->rad_info.gart_size;
1503 uint64_t heap_budget, heap_usage;
1504
1505 /* For all memory heaps, the computation of budget is as follow:
1506 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1507 *
1508 * The Vulkan spec 1.1.97 says that the budget should include any
1509 * currently allocated device memory.
1510 *
1511 * Note that the application heap usages are not really accurate (eg.
1512 * in presence of shared buffers).
1513 */
1514 if (vram_size) {
1515 heap_usage = device->ws->query_value(device->ws,
1516 RADEON_ALLOCATED_VRAM);
1517
1518 heap_budget = vram_size -
1519 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1520 heap_usage;
1521
1522 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1523 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1524 }
1525
1526 if (visible_vram_size) {
1527 heap_usage = device->ws->query_value(device->ws,
1528 RADEON_ALLOCATED_VRAM_VIS);
1529
1530 heap_budget = visible_vram_size -
1531 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1532 heap_usage;
1533
1534 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1535 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1536 }
1537
1538 if (gtt_size) {
1539 heap_usage = device->ws->query_value(device->ws,
1540 RADEON_ALLOCATED_GTT);
1541
1542 heap_budget = gtt_size -
1543 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1544 heap_usage;
1545
1546 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1547 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1548 }
1549
1550 /* The heapBudget and heapUsage values must be zero for array elements
1551 * greater than or equal to
1552 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1553 */
1554 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1555 memoryBudget->heapBudget[i] = 0;
1556 memoryBudget->heapUsage[i] = 0;
1557 }
1558 }
1559
1560 void radv_GetPhysicalDeviceMemoryProperties2(
1561 VkPhysicalDevice physicalDevice,
1562 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1563 {
1564 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1565 &pMemoryProperties->memoryProperties);
1566
1567 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1568 vk_find_struct(pMemoryProperties->pNext,
1569 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1570 if (memory_budget)
1571 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1572 }
1573
1574 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1575 VkDevice _device,
1576 VkExternalMemoryHandleTypeFlagBits handleType,
1577 const void *pHostPointer,
1578 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1579 {
1580 RADV_FROM_HANDLE(radv_device, device, _device);
1581
1582 switch (handleType)
1583 {
1584 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1585 const struct radv_physical_device *physical_device = device->physical_device;
1586 uint32_t memoryTypeBits = 0;
1587 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1588 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1589 memoryTypeBits = (1 << i);
1590 break;
1591 }
1592 }
1593 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1594 return VK_SUCCESS;
1595 }
1596 default:
1597 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1598 }
1599 }
1600
1601 static enum radeon_ctx_priority
1602 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1603 {
1604 /* Default to MEDIUM when a specific global priority isn't requested */
1605 if (!pObj)
1606 return RADEON_CTX_PRIORITY_MEDIUM;
1607
1608 switch(pObj->globalPriority) {
1609 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1610 return RADEON_CTX_PRIORITY_REALTIME;
1611 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1612 return RADEON_CTX_PRIORITY_HIGH;
1613 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1614 return RADEON_CTX_PRIORITY_MEDIUM;
1615 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1616 return RADEON_CTX_PRIORITY_LOW;
1617 default:
1618 unreachable("Illegal global priority value");
1619 return RADEON_CTX_PRIORITY_INVALID;
1620 }
1621 }
1622
1623 static int
1624 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1625 uint32_t queue_family_index, int idx,
1626 VkDeviceQueueCreateFlags flags,
1627 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1628 {
1629 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1630 queue->device = device;
1631 queue->queue_family_index = queue_family_index;
1632 queue->queue_idx = idx;
1633 queue->priority = radv_get_queue_global_priority(global_priority);
1634 queue->flags = flags;
1635
1636 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1637 if (!queue->hw_ctx)
1638 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1639
1640 return VK_SUCCESS;
1641 }
1642
1643 static void
1644 radv_queue_finish(struct radv_queue *queue)
1645 {
1646 if (queue->hw_ctx)
1647 queue->device->ws->ctx_destroy(queue->hw_ctx);
1648
1649 if (queue->initial_full_flush_preamble_cs)
1650 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1651 if (queue->initial_preamble_cs)
1652 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1653 if (queue->continue_preamble_cs)
1654 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1655 if (queue->descriptor_bo)
1656 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1657 if (queue->scratch_bo)
1658 queue->device->ws->buffer_destroy(queue->scratch_bo);
1659 if (queue->esgs_ring_bo)
1660 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1661 if (queue->gsvs_ring_bo)
1662 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1663 if (queue->tess_rings_bo)
1664 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1665 if (queue->compute_scratch_bo)
1666 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1667 }
1668
1669 static void
1670 radv_bo_list_init(struct radv_bo_list *bo_list)
1671 {
1672 pthread_mutex_init(&bo_list->mutex, NULL);
1673 bo_list->list.count = bo_list->capacity = 0;
1674 bo_list->list.bos = NULL;
1675 }
1676
1677 static void
1678 radv_bo_list_finish(struct radv_bo_list *bo_list)
1679 {
1680 free(bo_list->list.bos);
1681 pthread_mutex_destroy(&bo_list->mutex);
1682 }
1683
1684 static VkResult radv_bo_list_add(struct radv_device *device,
1685 struct radeon_winsys_bo *bo)
1686 {
1687 struct radv_bo_list *bo_list = &device->bo_list;
1688
1689 if (bo->is_local)
1690 return VK_SUCCESS;
1691
1692 if (unlikely(!device->use_global_bo_list))
1693 return VK_SUCCESS;
1694
1695 pthread_mutex_lock(&bo_list->mutex);
1696 if (bo_list->list.count == bo_list->capacity) {
1697 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1698 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1699
1700 if (!data) {
1701 pthread_mutex_unlock(&bo_list->mutex);
1702 return VK_ERROR_OUT_OF_HOST_MEMORY;
1703 }
1704
1705 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1706 bo_list->capacity = capacity;
1707 }
1708
1709 bo_list->list.bos[bo_list->list.count++] = bo;
1710 pthread_mutex_unlock(&bo_list->mutex);
1711 return VK_SUCCESS;
1712 }
1713
1714 static void radv_bo_list_remove(struct radv_device *device,
1715 struct radeon_winsys_bo *bo)
1716 {
1717 struct radv_bo_list *bo_list = &device->bo_list;
1718
1719 if (bo->is_local)
1720 return;
1721
1722 if (unlikely(!device->use_global_bo_list))
1723 return;
1724
1725 pthread_mutex_lock(&bo_list->mutex);
1726 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1727 if (bo_list->list.bos[i] == bo) {
1728 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1729 --bo_list->list.count;
1730 break;
1731 }
1732 }
1733 pthread_mutex_unlock(&bo_list->mutex);
1734 }
1735
1736 static void
1737 radv_device_init_gs_info(struct radv_device *device)
1738 {
1739 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1740 device->physical_device->rad_info.family);
1741 }
1742
1743 static int radv_get_device_extension_index(const char *name)
1744 {
1745 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1746 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1747 return i;
1748 }
1749 return -1;
1750 }
1751
1752 static int
1753 radv_get_int_debug_option(const char *name, int default_value)
1754 {
1755 const char *str;
1756 int result;
1757
1758 str = getenv(name);
1759 if (!str) {
1760 result = default_value;
1761 } else {
1762 char *endptr;
1763
1764 result = strtol(str, &endptr, 0);
1765 if (str == endptr) {
1766 /* No digits founs. */
1767 result = default_value;
1768 }
1769 }
1770
1771 return result;
1772 }
1773
1774 VkResult radv_CreateDevice(
1775 VkPhysicalDevice physicalDevice,
1776 const VkDeviceCreateInfo* pCreateInfo,
1777 const VkAllocationCallbacks* pAllocator,
1778 VkDevice* pDevice)
1779 {
1780 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1781 VkResult result;
1782 struct radv_device *device;
1783
1784 bool keep_shader_info = false;
1785
1786 /* Check enabled features */
1787 if (pCreateInfo->pEnabledFeatures) {
1788 VkPhysicalDeviceFeatures supported_features;
1789 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1790 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1791 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1792 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1793 for (uint32_t i = 0; i < num_features; i++) {
1794 if (enabled_feature[i] && !supported_feature[i])
1795 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1796 }
1797 }
1798
1799 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1800 sizeof(*device), 8,
1801 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1802 if (!device)
1803 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1804
1805 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1806 device->instance = physical_device->instance;
1807 device->physical_device = physical_device;
1808
1809 device->ws = physical_device->ws;
1810 if (pAllocator)
1811 device->alloc = *pAllocator;
1812 else
1813 device->alloc = physical_device->instance->alloc;
1814
1815 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1816 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1817 int index = radv_get_device_extension_index(ext_name);
1818 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1819 vk_free(&device->alloc, device);
1820 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1821 }
1822
1823 device->enabled_extensions.extensions[index] = true;
1824 }
1825
1826 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1827
1828 /* With update after bind we can't attach bo's to the command buffer
1829 * from the descriptor set anymore, so we have to use a global BO list.
1830 */
1831 device->use_global_bo_list =
1832 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1833 device->enabled_extensions.EXT_descriptor_indexing ||
1834 device->enabled_extensions.EXT_buffer_device_address;
1835
1836 mtx_init(&device->shader_slab_mutex, mtx_plain);
1837 list_inithead(&device->shader_slabs);
1838
1839 radv_bo_list_init(&device->bo_list);
1840
1841 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1842 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1843 uint32_t qfi = queue_create->queueFamilyIndex;
1844 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1845 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1846
1847 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1848
1849 device->queues[qfi] = vk_alloc(&device->alloc,
1850 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1851 if (!device->queues[qfi]) {
1852 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1853 goto fail;
1854 }
1855
1856 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1857
1858 device->queue_count[qfi] = queue_create->queueCount;
1859
1860 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1861 result = radv_queue_init(device, &device->queues[qfi][q],
1862 qfi, q, queue_create->flags,
1863 global_priority);
1864 if (result != VK_SUCCESS)
1865 goto fail;
1866 }
1867 }
1868
1869 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1870 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1871
1872 /* Disabled and not implemented for now. */
1873 device->dfsm_allowed = device->pbb_allowed &&
1874 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1875 device->physical_device->rad_info.family == CHIP_RAVEN2);
1876
1877 #ifdef ANDROID
1878 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1879 #endif
1880
1881 /* The maximum number of scratch waves. Scratch space isn't divided
1882 * evenly between CUs. The number is only a function of the number of CUs.
1883 * We can decrease the constant to decrease the scratch buffer size.
1884 *
1885 * sctx->scratch_waves must be >= the maximum possible size of
1886 * 1 threadgroup, so that the hw doesn't hang from being unable
1887 * to start any.
1888 *
1889 * The recommended value is 4 per CU at most. Higher numbers don't
1890 * bring much benefit, but they still occupy chip resources (think
1891 * async compute). I've seen ~2% performance difference between 4 and 32.
1892 */
1893 uint32_t max_threads_per_block = 2048;
1894 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1895 max_threads_per_block / 64);
1896
1897 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1898
1899 if (device->physical_device->rad_info.chip_class >= GFX7) {
1900 /* If the KMD allows it (there is a KMD hw register for it),
1901 * allow launching waves out-of-order.
1902 */
1903 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1904 }
1905
1906 radv_device_init_gs_info(device);
1907
1908 device->tess_offchip_block_dw_size =
1909 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1910 device->has_distributed_tess =
1911 device->physical_device->rad_info.chip_class >= GFX8 &&
1912 device->physical_device->rad_info.max_se >= 2;
1913
1914 if (getenv("RADV_TRACE_FILE")) {
1915 const char *filename = getenv("RADV_TRACE_FILE");
1916
1917 keep_shader_info = true;
1918
1919 if (!radv_init_trace(device))
1920 goto fail;
1921
1922 fprintf(stderr, "*****************************************************************************\n");
1923 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1924 fprintf(stderr, "*****************************************************************************\n");
1925
1926 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1927 radv_dump_enabled_options(device, stderr);
1928 }
1929
1930 device->keep_shader_info = keep_shader_info;
1931
1932 result = radv_device_init_meta(device);
1933 if (result != VK_SUCCESS)
1934 goto fail;
1935
1936 radv_device_init_msaa(device);
1937
1938 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1939 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1940 switch (family) {
1941 case RADV_QUEUE_GENERAL:
1942 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1943 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1944 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1945 break;
1946 case RADV_QUEUE_COMPUTE:
1947 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1948 radeon_emit(device->empty_cs[family], 0);
1949 break;
1950 }
1951 device->ws->cs_finalize(device->empty_cs[family]);
1952 }
1953
1954 if (device->physical_device->rad_info.chip_class >= GFX7)
1955 cik_create_gfx_config(device);
1956
1957 VkPipelineCacheCreateInfo ci;
1958 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1959 ci.pNext = NULL;
1960 ci.flags = 0;
1961 ci.pInitialData = NULL;
1962 ci.initialDataSize = 0;
1963 VkPipelineCache pc;
1964 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1965 &ci, NULL, &pc);
1966 if (result != VK_SUCCESS)
1967 goto fail_meta;
1968
1969 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1970
1971 device->force_aniso =
1972 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1973 if (device->force_aniso >= 0) {
1974 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1975 1 << util_logbase2(device->force_aniso));
1976 }
1977
1978 *pDevice = radv_device_to_handle(device);
1979 return VK_SUCCESS;
1980
1981 fail_meta:
1982 radv_device_finish_meta(device);
1983 fail:
1984 radv_bo_list_finish(&device->bo_list);
1985
1986 if (device->trace_bo)
1987 device->ws->buffer_destroy(device->trace_bo);
1988
1989 if (device->gfx_init)
1990 device->ws->buffer_destroy(device->gfx_init);
1991
1992 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1993 for (unsigned q = 0; q < device->queue_count[i]; q++)
1994 radv_queue_finish(&device->queues[i][q]);
1995 if (device->queue_count[i])
1996 vk_free(&device->alloc, device->queues[i]);
1997 }
1998
1999 vk_free(&device->alloc, device);
2000 return result;
2001 }
2002
2003 void radv_DestroyDevice(
2004 VkDevice _device,
2005 const VkAllocationCallbacks* pAllocator)
2006 {
2007 RADV_FROM_HANDLE(radv_device, device, _device);
2008
2009 if (!device)
2010 return;
2011
2012 if (device->trace_bo)
2013 device->ws->buffer_destroy(device->trace_bo);
2014
2015 if (device->gfx_init)
2016 device->ws->buffer_destroy(device->gfx_init);
2017
2018 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2019 for (unsigned q = 0; q < device->queue_count[i]; q++)
2020 radv_queue_finish(&device->queues[i][q]);
2021 if (device->queue_count[i])
2022 vk_free(&device->alloc, device->queues[i]);
2023 if (device->empty_cs[i])
2024 device->ws->cs_destroy(device->empty_cs[i]);
2025 }
2026 radv_device_finish_meta(device);
2027
2028 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2029 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2030
2031 radv_destroy_shader_slabs(device);
2032
2033 radv_bo_list_finish(&device->bo_list);
2034 vk_free(&device->alloc, device);
2035 }
2036
2037 VkResult radv_EnumerateInstanceLayerProperties(
2038 uint32_t* pPropertyCount,
2039 VkLayerProperties* pProperties)
2040 {
2041 if (pProperties == NULL) {
2042 *pPropertyCount = 0;
2043 return VK_SUCCESS;
2044 }
2045
2046 /* None supported at this time */
2047 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2048 }
2049
2050 VkResult radv_EnumerateDeviceLayerProperties(
2051 VkPhysicalDevice physicalDevice,
2052 uint32_t* pPropertyCount,
2053 VkLayerProperties* pProperties)
2054 {
2055 if (pProperties == NULL) {
2056 *pPropertyCount = 0;
2057 return VK_SUCCESS;
2058 }
2059
2060 /* None supported at this time */
2061 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2062 }
2063
2064 void radv_GetDeviceQueue2(
2065 VkDevice _device,
2066 const VkDeviceQueueInfo2* pQueueInfo,
2067 VkQueue* pQueue)
2068 {
2069 RADV_FROM_HANDLE(radv_device, device, _device);
2070 struct radv_queue *queue;
2071
2072 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2073 if (pQueueInfo->flags != queue->flags) {
2074 /* From the Vulkan 1.1.70 spec:
2075 *
2076 * "The queue returned by vkGetDeviceQueue2 must have the same
2077 * flags value from this structure as that used at device
2078 * creation time in a VkDeviceQueueCreateInfo instance. If no
2079 * matching flags were specified at device creation time then
2080 * pQueue will return VK_NULL_HANDLE."
2081 */
2082 *pQueue = VK_NULL_HANDLE;
2083 return;
2084 }
2085
2086 *pQueue = radv_queue_to_handle(queue);
2087 }
2088
2089 void radv_GetDeviceQueue(
2090 VkDevice _device,
2091 uint32_t queueFamilyIndex,
2092 uint32_t queueIndex,
2093 VkQueue* pQueue)
2094 {
2095 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2096 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2097 .queueFamilyIndex = queueFamilyIndex,
2098 .queueIndex = queueIndex
2099 };
2100
2101 radv_GetDeviceQueue2(_device, &info, pQueue);
2102 }
2103
2104 static void
2105 fill_geom_tess_rings(struct radv_queue *queue,
2106 uint32_t *map,
2107 bool add_sample_positions,
2108 uint32_t esgs_ring_size,
2109 struct radeon_winsys_bo *esgs_ring_bo,
2110 uint32_t gsvs_ring_size,
2111 struct radeon_winsys_bo *gsvs_ring_bo,
2112 uint32_t tess_factor_ring_size,
2113 uint32_t tess_offchip_ring_offset,
2114 uint32_t tess_offchip_ring_size,
2115 struct radeon_winsys_bo *tess_rings_bo)
2116 {
2117 uint32_t *desc = &map[4];
2118
2119 if (esgs_ring_bo) {
2120 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2121
2122 /* stride 0, num records - size, add tid, swizzle, elsize4,
2123 index stride 64 */
2124 desc[0] = esgs_va;
2125 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2126 S_008F04_STRIDE(0) |
2127 S_008F04_SWIZZLE_ENABLE(true);
2128 desc[2] = esgs_ring_size;
2129 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2130 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2131 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2132 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2133 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2134 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2135 S_008F0C_ELEMENT_SIZE(1) |
2136 S_008F0C_INDEX_STRIDE(3) |
2137 S_008F0C_ADD_TID_ENABLE(true);
2138
2139 /* GS entry for ES->GS ring */
2140 /* stride 0, num records - size, elsize0,
2141 index stride 0 */
2142 desc[4] = esgs_va;
2143 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2144 S_008F04_STRIDE(0) |
2145 S_008F04_SWIZZLE_ENABLE(false);
2146 desc[6] = esgs_ring_size;
2147 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2148 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2149 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2150 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2151 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2152 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2153 S_008F0C_ELEMENT_SIZE(0) |
2154 S_008F0C_INDEX_STRIDE(0) |
2155 S_008F0C_ADD_TID_ENABLE(false);
2156 }
2157
2158 desc += 8;
2159
2160 if (gsvs_ring_bo) {
2161 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2162
2163 /* VS entry for GS->VS ring */
2164 /* stride 0, num records - size, elsize0,
2165 index stride 0 */
2166 desc[0] = gsvs_va;
2167 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2168 S_008F04_STRIDE(0) |
2169 S_008F04_SWIZZLE_ENABLE(false);
2170 desc[2] = gsvs_ring_size;
2171 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2175 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2176 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2177 S_008F0C_ELEMENT_SIZE(0) |
2178 S_008F0C_INDEX_STRIDE(0) |
2179 S_008F0C_ADD_TID_ENABLE(false);
2180
2181 /* stride gsvs_itemsize, num records 64
2182 elsize 4, index stride 16 */
2183 /* shader will patch stride and desc[2] */
2184 desc[4] = gsvs_va;
2185 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2186 S_008F04_STRIDE(0) |
2187 S_008F04_SWIZZLE_ENABLE(true);
2188 desc[6] = 0;
2189 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2190 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2191 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2192 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2193 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2194 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2195 S_008F0C_ELEMENT_SIZE(1) |
2196 S_008F0C_INDEX_STRIDE(1) |
2197 S_008F0C_ADD_TID_ENABLE(true);
2198 }
2199
2200 desc += 8;
2201
2202 if (tess_rings_bo) {
2203 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2204 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2205
2206 desc[0] = tess_va;
2207 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2208 S_008F04_STRIDE(0) |
2209 S_008F04_SWIZZLE_ENABLE(false);
2210 desc[2] = tess_factor_ring_size;
2211 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2212 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2213 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2214 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2215 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2216 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2217 S_008F0C_ELEMENT_SIZE(0) |
2218 S_008F0C_INDEX_STRIDE(0) |
2219 S_008F0C_ADD_TID_ENABLE(false);
2220
2221 desc[4] = tess_offchip_va;
2222 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2223 S_008F04_STRIDE(0) |
2224 S_008F04_SWIZZLE_ENABLE(false);
2225 desc[6] = tess_offchip_ring_size;
2226 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2227 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2228 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2229 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2230 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2232 S_008F0C_ELEMENT_SIZE(0) |
2233 S_008F0C_INDEX_STRIDE(0) |
2234 S_008F0C_ADD_TID_ENABLE(false);
2235 }
2236
2237 desc += 8;
2238
2239 if (add_sample_positions) {
2240 /* add sample positions after all rings */
2241 memcpy(desc, queue->device->sample_locations_1x, 8);
2242 desc += 2;
2243 memcpy(desc, queue->device->sample_locations_2x, 16);
2244 desc += 4;
2245 memcpy(desc, queue->device->sample_locations_4x, 32);
2246 desc += 8;
2247 memcpy(desc, queue->device->sample_locations_8x, 64);
2248 }
2249 }
2250
2251 static unsigned
2252 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2253 {
2254 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2255 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2256 device->physical_device->rad_info.family != CHIP_STONEY;
2257 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2258 unsigned max_offchip_buffers;
2259 unsigned offchip_granularity;
2260 unsigned hs_offchip_param;
2261
2262 /*
2263 * Per RadeonSI:
2264 * This must be one less than the maximum number due to a hw limitation.
2265 * Various hardware bugs need thGFX7
2266 *
2267 * Per AMDVLK:
2268 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2269 * Gfx7 should limit max_offchip_buffers to 508
2270 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2271 *
2272 * Follow AMDVLK here.
2273 */
2274 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2275 device->physical_device->rad_info.chip_class == GFX7 ||
2276 device->physical_device->rad_info.chip_class == GFX6)
2277 --max_offchip_buffers_per_se;
2278
2279 max_offchip_buffers = max_offchip_buffers_per_se *
2280 device->physical_device->rad_info.max_se;
2281
2282 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2283 * around by setting 4K granularity.
2284 */
2285 if (device->tess_offchip_block_dw_size == 4096) {
2286 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2287 offchip_granularity = V_03093C_X_4K_DWORDS;
2288 } else {
2289 assert(device->tess_offchip_block_dw_size == 8192);
2290 offchip_granularity = V_03093C_X_8K_DWORDS;
2291 }
2292
2293 switch (device->physical_device->rad_info.chip_class) {
2294 case GFX6:
2295 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2296 break;
2297 case GFX7:
2298 case GFX8:
2299 case GFX9:
2300 default:
2301 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2302 break;
2303 }
2304
2305 *max_offchip_buffers_p = max_offchip_buffers;
2306 if (device->physical_device->rad_info.chip_class >= GFX7) {
2307 if (device->physical_device->rad_info.chip_class >= GFX8)
2308 --max_offchip_buffers;
2309 hs_offchip_param =
2310 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2311 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2312 } else {
2313 hs_offchip_param =
2314 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2315 }
2316 return hs_offchip_param;
2317 }
2318
2319 static void
2320 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2321 struct radeon_winsys_bo *esgs_ring_bo,
2322 uint32_t esgs_ring_size,
2323 struct radeon_winsys_bo *gsvs_ring_bo,
2324 uint32_t gsvs_ring_size)
2325 {
2326 if (!esgs_ring_bo && !gsvs_ring_bo)
2327 return;
2328
2329 if (esgs_ring_bo)
2330 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2331
2332 if (gsvs_ring_bo)
2333 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2334
2335 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2336 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2337 radeon_emit(cs, esgs_ring_size >> 8);
2338 radeon_emit(cs, gsvs_ring_size >> 8);
2339 } else {
2340 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2341 radeon_emit(cs, esgs_ring_size >> 8);
2342 radeon_emit(cs, gsvs_ring_size >> 8);
2343 }
2344 }
2345
2346 static void
2347 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2348 unsigned hs_offchip_param, unsigned tf_ring_size,
2349 struct radeon_winsys_bo *tess_rings_bo)
2350 {
2351 uint64_t tf_va;
2352
2353 if (!tess_rings_bo)
2354 return;
2355
2356 tf_va = radv_buffer_get_va(tess_rings_bo);
2357
2358 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2359
2360 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2361 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2362 S_030938_SIZE(tf_ring_size / 4));
2363 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2364 tf_va >> 8);
2365 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2366 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2367 S_030944_BASE_HI(tf_va >> 40));
2368 }
2369 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2370 hs_offchip_param);
2371 } else {
2372 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2373 S_008988_SIZE(tf_ring_size / 4));
2374 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2375 tf_va >> 8);
2376 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2377 hs_offchip_param);
2378 }
2379 }
2380
2381 static void
2382 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2383 struct radeon_winsys_bo *compute_scratch_bo)
2384 {
2385 uint64_t scratch_va;
2386
2387 if (!compute_scratch_bo)
2388 return;
2389
2390 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2391
2392 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2393
2394 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2395 radeon_emit(cs, scratch_va);
2396 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2397 S_008F04_SWIZZLE_ENABLE(1));
2398 }
2399
2400 static void
2401 radv_emit_global_shader_pointers(struct radv_queue *queue,
2402 struct radeon_cmdbuf *cs,
2403 struct radeon_winsys_bo *descriptor_bo)
2404 {
2405 uint64_t va;
2406
2407 if (!descriptor_bo)
2408 return;
2409
2410 va = radv_buffer_get_va(descriptor_bo);
2411
2412 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2413
2414 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2415 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2416 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2417 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2418 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2419
2420 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2421 radv_emit_shader_pointer(queue->device, cs, regs[i],
2422 va, true);
2423 }
2424 } else {
2425 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2426 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2427 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2428 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2429 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2430 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2431
2432 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2433 radv_emit_shader_pointer(queue->device, cs, regs[i],
2434 va, true);
2435 }
2436 }
2437 }
2438
2439 static void
2440 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2441 {
2442 struct radv_device *device = queue->device;
2443
2444 if (device->gfx_init) {
2445 uint64_t va = radv_buffer_get_va(device->gfx_init);
2446
2447 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2448 radeon_emit(cs, va);
2449 radeon_emit(cs, va >> 32);
2450 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2451
2452 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2453 } else {
2454 struct radv_physical_device *physical_device = device->physical_device;
2455 si_emit_graphics(physical_device, cs);
2456 }
2457 }
2458
2459 static void
2460 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2461 {
2462 struct radv_physical_device *physical_device = queue->device->physical_device;
2463 si_emit_compute(physical_device, cs);
2464 }
2465
2466 static VkResult
2467 radv_get_preamble_cs(struct radv_queue *queue,
2468 uint32_t scratch_size,
2469 uint32_t compute_scratch_size,
2470 uint32_t esgs_ring_size,
2471 uint32_t gsvs_ring_size,
2472 bool needs_tess_rings,
2473 bool needs_sample_positions,
2474 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2475 struct radeon_cmdbuf **initial_preamble_cs,
2476 struct radeon_cmdbuf **continue_preamble_cs)
2477 {
2478 struct radeon_winsys_bo *scratch_bo = NULL;
2479 struct radeon_winsys_bo *descriptor_bo = NULL;
2480 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2481 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2482 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2483 struct radeon_winsys_bo *tess_rings_bo = NULL;
2484 struct radeon_cmdbuf *dest_cs[3] = {0};
2485 bool add_tess_rings = false, add_sample_positions = false;
2486 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2487 unsigned max_offchip_buffers;
2488 unsigned hs_offchip_param = 0;
2489 unsigned tess_offchip_ring_offset;
2490 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2491 if (!queue->has_tess_rings) {
2492 if (needs_tess_rings)
2493 add_tess_rings = true;
2494 }
2495 if (!queue->has_sample_positions) {
2496 if (needs_sample_positions)
2497 add_sample_positions = true;
2498 }
2499 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2500 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2501 &max_offchip_buffers);
2502 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2503 tess_offchip_ring_size = max_offchip_buffers *
2504 queue->device->tess_offchip_block_dw_size * 4;
2505
2506 if (scratch_size <= queue->scratch_size &&
2507 compute_scratch_size <= queue->compute_scratch_size &&
2508 esgs_ring_size <= queue->esgs_ring_size &&
2509 gsvs_ring_size <= queue->gsvs_ring_size &&
2510 !add_tess_rings && !add_sample_positions &&
2511 queue->initial_preamble_cs) {
2512 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2513 *initial_preamble_cs = queue->initial_preamble_cs;
2514 *continue_preamble_cs = queue->continue_preamble_cs;
2515 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2516 *continue_preamble_cs = NULL;
2517 return VK_SUCCESS;
2518 }
2519
2520 if (scratch_size > queue->scratch_size) {
2521 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2522 scratch_size,
2523 4096,
2524 RADEON_DOMAIN_VRAM,
2525 ring_bo_flags,
2526 RADV_BO_PRIORITY_SCRATCH);
2527 if (!scratch_bo)
2528 goto fail;
2529 } else
2530 scratch_bo = queue->scratch_bo;
2531
2532 if (compute_scratch_size > queue->compute_scratch_size) {
2533 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2534 compute_scratch_size,
2535 4096,
2536 RADEON_DOMAIN_VRAM,
2537 ring_bo_flags,
2538 RADV_BO_PRIORITY_SCRATCH);
2539 if (!compute_scratch_bo)
2540 goto fail;
2541
2542 } else
2543 compute_scratch_bo = queue->compute_scratch_bo;
2544
2545 if (esgs_ring_size > queue->esgs_ring_size) {
2546 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2547 esgs_ring_size,
2548 4096,
2549 RADEON_DOMAIN_VRAM,
2550 ring_bo_flags,
2551 RADV_BO_PRIORITY_SCRATCH);
2552 if (!esgs_ring_bo)
2553 goto fail;
2554 } else {
2555 esgs_ring_bo = queue->esgs_ring_bo;
2556 esgs_ring_size = queue->esgs_ring_size;
2557 }
2558
2559 if (gsvs_ring_size > queue->gsvs_ring_size) {
2560 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2561 gsvs_ring_size,
2562 4096,
2563 RADEON_DOMAIN_VRAM,
2564 ring_bo_flags,
2565 RADV_BO_PRIORITY_SCRATCH);
2566 if (!gsvs_ring_bo)
2567 goto fail;
2568 } else {
2569 gsvs_ring_bo = queue->gsvs_ring_bo;
2570 gsvs_ring_size = queue->gsvs_ring_size;
2571 }
2572
2573 if (add_tess_rings) {
2574 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2575 tess_offchip_ring_offset + tess_offchip_ring_size,
2576 256,
2577 RADEON_DOMAIN_VRAM,
2578 ring_bo_flags,
2579 RADV_BO_PRIORITY_SCRATCH);
2580 if (!tess_rings_bo)
2581 goto fail;
2582 } else {
2583 tess_rings_bo = queue->tess_rings_bo;
2584 }
2585
2586 if (scratch_bo != queue->scratch_bo ||
2587 esgs_ring_bo != queue->esgs_ring_bo ||
2588 gsvs_ring_bo != queue->gsvs_ring_bo ||
2589 tess_rings_bo != queue->tess_rings_bo ||
2590 add_sample_positions) {
2591 uint32_t size = 0;
2592 if (gsvs_ring_bo || esgs_ring_bo ||
2593 tess_rings_bo || add_sample_positions) {
2594 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2595 if (add_sample_positions)
2596 size += 128; /* 64+32+16+8 = 120 bytes */
2597 }
2598 else if (scratch_bo)
2599 size = 8; /* 2 dword */
2600
2601 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2602 size,
2603 4096,
2604 RADEON_DOMAIN_VRAM,
2605 RADEON_FLAG_CPU_ACCESS |
2606 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2607 RADEON_FLAG_READ_ONLY,
2608 RADV_BO_PRIORITY_DESCRIPTOR);
2609 if (!descriptor_bo)
2610 goto fail;
2611 } else
2612 descriptor_bo = queue->descriptor_bo;
2613
2614 if (descriptor_bo != queue->descriptor_bo) {
2615 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2616
2617 if (scratch_bo) {
2618 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2619 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2620 S_008F04_SWIZZLE_ENABLE(1);
2621 map[0] = scratch_va;
2622 map[1] = rsrc1;
2623 }
2624
2625 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2626 fill_geom_tess_rings(queue, map, add_sample_positions,
2627 esgs_ring_size, esgs_ring_bo,
2628 gsvs_ring_size, gsvs_ring_bo,
2629 tess_factor_ring_size,
2630 tess_offchip_ring_offset,
2631 tess_offchip_ring_size,
2632 tess_rings_bo);
2633
2634 queue->device->ws->buffer_unmap(descriptor_bo);
2635 }
2636
2637 for(int i = 0; i < 3; ++i) {
2638 struct radeon_cmdbuf *cs = NULL;
2639 cs = queue->device->ws->cs_create(queue->device->ws,
2640 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2641 if (!cs)
2642 goto fail;
2643
2644 dest_cs[i] = cs;
2645
2646 if (scratch_bo)
2647 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2648
2649 /* Emit initial configuration. */
2650 switch (queue->queue_family_index) {
2651 case RADV_QUEUE_GENERAL:
2652 radv_init_graphics_state(cs, queue);
2653 break;
2654 case RADV_QUEUE_COMPUTE:
2655 radv_init_compute_state(cs, queue);
2656 break;
2657 case RADV_QUEUE_TRANSFER:
2658 break;
2659 }
2660
2661 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2662 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2663 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2664 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2665 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2666 }
2667
2668 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2669 gsvs_ring_bo, gsvs_ring_size);
2670 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2671 tess_factor_ring_size, tess_rings_bo);
2672 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2673 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2674
2675 if (i == 0) {
2676 si_cs_emit_cache_flush(cs,
2677 queue->device->physical_device->rad_info.chip_class,
2678 NULL, 0,
2679 queue->queue_family_index == RING_COMPUTE &&
2680 queue->device->physical_device->rad_info.chip_class >= GFX7,
2681 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2682 RADV_CMD_FLAG_INV_ICACHE |
2683 RADV_CMD_FLAG_INV_SMEM_L1 |
2684 RADV_CMD_FLAG_INV_VMEM_L1 |
2685 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2686 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2687 } else if (i == 1) {
2688 si_cs_emit_cache_flush(cs,
2689 queue->device->physical_device->rad_info.chip_class,
2690 NULL, 0,
2691 queue->queue_family_index == RING_COMPUTE &&
2692 queue->device->physical_device->rad_info.chip_class >= GFX7,
2693 RADV_CMD_FLAG_INV_ICACHE |
2694 RADV_CMD_FLAG_INV_SMEM_L1 |
2695 RADV_CMD_FLAG_INV_VMEM_L1 |
2696 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2697 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2698 }
2699
2700 if (!queue->device->ws->cs_finalize(cs))
2701 goto fail;
2702 }
2703
2704 if (queue->initial_full_flush_preamble_cs)
2705 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2706
2707 if (queue->initial_preamble_cs)
2708 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2709
2710 if (queue->continue_preamble_cs)
2711 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2712
2713 queue->initial_full_flush_preamble_cs = dest_cs[0];
2714 queue->initial_preamble_cs = dest_cs[1];
2715 queue->continue_preamble_cs = dest_cs[2];
2716
2717 if (scratch_bo != queue->scratch_bo) {
2718 if (queue->scratch_bo)
2719 queue->device->ws->buffer_destroy(queue->scratch_bo);
2720 queue->scratch_bo = scratch_bo;
2721 queue->scratch_size = scratch_size;
2722 }
2723
2724 if (compute_scratch_bo != queue->compute_scratch_bo) {
2725 if (queue->compute_scratch_bo)
2726 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2727 queue->compute_scratch_bo = compute_scratch_bo;
2728 queue->compute_scratch_size = compute_scratch_size;
2729 }
2730
2731 if (esgs_ring_bo != queue->esgs_ring_bo) {
2732 if (queue->esgs_ring_bo)
2733 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2734 queue->esgs_ring_bo = esgs_ring_bo;
2735 queue->esgs_ring_size = esgs_ring_size;
2736 }
2737
2738 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2739 if (queue->gsvs_ring_bo)
2740 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2741 queue->gsvs_ring_bo = gsvs_ring_bo;
2742 queue->gsvs_ring_size = gsvs_ring_size;
2743 }
2744
2745 if (tess_rings_bo != queue->tess_rings_bo) {
2746 queue->tess_rings_bo = tess_rings_bo;
2747 queue->has_tess_rings = true;
2748 }
2749
2750 if (descriptor_bo != queue->descriptor_bo) {
2751 if (queue->descriptor_bo)
2752 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2753
2754 queue->descriptor_bo = descriptor_bo;
2755 }
2756
2757 if (add_sample_positions)
2758 queue->has_sample_positions = true;
2759
2760 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2761 *initial_preamble_cs = queue->initial_preamble_cs;
2762 *continue_preamble_cs = queue->continue_preamble_cs;
2763 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2764 *continue_preamble_cs = NULL;
2765 return VK_SUCCESS;
2766 fail:
2767 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2768 if (dest_cs[i])
2769 queue->device->ws->cs_destroy(dest_cs[i]);
2770 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2771 queue->device->ws->buffer_destroy(descriptor_bo);
2772 if (scratch_bo && scratch_bo != queue->scratch_bo)
2773 queue->device->ws->buffer_destroy(scratch_bo);
2774 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2775 queue->device->ws->buffer_destroy(compute_scratch_bo);
2776 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2777 queue->device->ws->buffer_destroy(esgs_ring_bo);
2778 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2779 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2780 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2781 queue->device->ws->buffer_destroy(tess_rings_bo);
2782 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2783 }
2784
2785 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2786 struct radv_winsys_sem_counts *counts,
2787 int num_sems,
2788 const VkSemaphore *sems,
2789 VkFence _fence,
2790 bool reset_temp)
2791 {
2792 int syncobj_idx = 0, sem_idx = 0;
2793
2794 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2795 return VK_SUCCESS;
2796
2797 for (uint32_t i = 0; i < num_sems; i++) {
2798 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2799
2800 if (sem->temp_syncobj || sem->syncobj)
2801 counts->syncobj_count++;
2802 else
2803 counts->sem_count++;
2804 }
2805
2806 if (_fence != VK_NULL_HANDLE) {
2807 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2808 if (fence->temp_syncobj || fence->syncobj)
2809 counts->syncobj_count++;
2810 }
2811
2812 if (counts->syncobj_count) {
2813 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2814 if (!counts->syncobj)
2815 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2816 }
2817
2818 if (counts->sem_count) {
2819 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2820 if (!counts->sem) {
2821 free(counts->syncobj);
2822 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2823 }
2824 }
2825
2826 for (uint32_t i = 0; i < num_sems; i++) {
2827 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2828
2829 if (sem->temp_syncobj) {
2830 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2831 }
2832 else if (sem->syncobj)
2833 counts->syncobj[syncobj_idx++] = sem->syncobj;
2834 else {
2835 assert(sem->sem);
2836 counts->sem[sem_idx++] = sem->sem;
2837 }
2838 }
2839
2840 if (_fence != VK_NULL_HANDLE) {
2841 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2842 if (fence->temp_syncobj)
2843 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2844 else if (fence->syncobj)
2845 counts->syncobj[syncobj_idx++] = fence->syncobj;
2846 }
2847
2848 return VK_SUCCESS;
2849 }
2850
2851 static void
2852 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2853 {
2854 free(sem_info->wait.syncobj);
2855 free(sem_info->wait.sem);
2856 free(sem_info->signal.syncobj);
2857 free(sem_info->signal.sem);
2858 }
2859
2860
2861 static void radv_free_temp_syncobjs(struct radv_device *device,
2862 int num_sems,
2863 const VkSemaphore *sems)
2864 {
2865 for (uint32_t i = 0; i < num_sems; i++) {
2866 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2867
2868 if (sem->temp_syncobj) {
2869 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2870 sem->temp_syncobj = 0;
2871 }
2872 }
2873 }
2874
2875 static VkResult
2876 radv_alloc_sem_info(struct radv_instance *instance,
2877 struct radv_winsys_sem_info *sem_info,
2878 int num_wait_sems,
2879 const VkSemaphore *wait_sems,
2880 int num_signal_sems,
2881 const VkSemaphore *signal_sems,
2882 VkFence fence)
2883 {
2884 VkResult ret;
2885 memset(sem_info, 0, sizeof(*sem_info));
2886
2887 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2888 if (ret)
2889 return ret;
2890 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2891 if (ret)
2892 radv_free_sem_info(sem_info);
2893
2894 /* caller can override these */
2895 sem_info->cs_emit_wait = true;
2896 sem_info->cs_emit_signal = true;
2897 return ret;
2898 }
2899
2900 /* Signals fence as soon as all the work currently put on queue is done. */
2901 static VkResult radv_signal_fence(struct radv_queue *queue,
2902 struct radv_fence *fence)
2903 {
2904 int ret;
2905 VkResult result;
2906 struct radv_winsys_sem_info sem_info;
2907
2908 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2909 radv_fence_to_handle(fence));
2910 if (result != VK_SUCCESS)
2911 return result;
2912
2913 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2914 &queue->device->empty_cs[queue->queue_family_index],
2915 1, NULL, NULL, &sem_info, NULL,
2916 false, fence->fence);
2917 radv_free_sem_info(&sem_info);
2918
2919 if (ret)
2920 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2921
2922 return VK_SUCCESS;
2923 }
2924
2925 VkResult radv_QueueSubmit(
2926 VkQueue _queue,
2927 uint32_t submitCount,
2928 const VkSubmitInfo* pSubmits,
2929 VkFence _fence)
2930 {
2931 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2932 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2933 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2934 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2935 int ret;
2936 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2937 uint32_t scratch_size = 0;
2938 uint32_t compute_scratch_size = 0;
2939 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2940 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2941 VkResult result;
2942 bool fence_emitted = false;
2943 bool tess_rings_needed = false;
2944 bool sample_positions_needed = false;
2945
2946 /* Do this first so failing to allocate scratch buffers can't result in
2947 * partially executed submissions. */
2948 for (uint32_t i = 0; i < submitCount; i++) {
2949 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2951 pSubmits[i].pCommandBuffers[j]);
2952
2953 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2954 compute_scratch_size = MAX2(compute_scratch_size,
2955 cmd_buffer->compute_scratch_size_needed);
2956 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2957 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2958 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2959 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2960 }
2961 }
2962
2963 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2964 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2965 sample_positions_needed, &initial_flush_preamble_cs,
2966 &initial_preamble_cs, &continue_preamble_cs);
2967 if (result != VK_SUCCESS)
2968 return result;
2969
2970 for (uint32_t i = 0; i < submitCount; i++) {
2971 struct radeon_cmdbuf **cs_array;
2972 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2973 bool can_patch = true;
2974 uint32_t advance;
2975 struct radv_winsys_sem_info sem_info;
2976
2977 result = radv_alloc_sem_info(queue->device->instance,
2978 &sem_info,
2979 pSubmits[i].waitSemaphoreCount,
2980 pSubmits[i].pWaitSemaphores,
2981 pSubmits[i].signalSemaphoreCount,
2982 pSubmits[i].pSignalSemaphores,
2983 _fence);
2984 if (result != VK_SUCCESS)
2985 return result;
2986
2987 if (!pSubmits[i].commandBufferCount) {
2988 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2989 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2990 &queue->device->empty_cs[queue->queue_family_index],
2991 1, NULL, NULL,
2992 &sem_info, NULL,
2993 false, base_fence);
2994 if (ret) {
2995 radv_loge("failed to submit CS %d\n", i);
2996 abort();
2997 }
2998 fence_emitted = true;
2999 }
3000 radv_free_sem_info(&sem_info);
3001 continue;
3002 }
3003
3004 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3005 (pSubmits[i].commandBufferCount));
3006
3007 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3009 pSubmits[i].pCommandBuffers[j]);
3010 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3011
3012 cs_array[j] = cmd_buffer->cs;
3013 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3014 can_patch = false;
3015
3016 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3017 }
3018
3019 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3020 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3021 const struct radv_winsys_bo_list *bo_list = NULL;
3022
3023 advance = MIN2(max_cs_submission,
3024 pSubmits[i].commandBufferCount - j);
3025
3026 if (queue->device->trace_bo)
3027 *queue->device->trace_id_ptr = 0;
3028
3029 sem_info.cs_emit_wait = j == 0;
3030 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3031
3032 if (unlikely(queue->device->use_global_bo_list)) {
3033 pthread_mutex_lock(&queue->device->bo_list.mutex);
3034 bo_list = &queue->device->bo_list.list;
3035 }
3036
3037 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3038 advance, initial_preamble, continue_preamble_cs,
3039 &sem_info, bo_list,
3040 can_patch, base_fence);
3041
3042 if (unlikely(queue->device->use_global_bo_list))
3043 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3044
3045 if (ret) {
3046 radv_loge("failed to submit CS %d\n", i);
3047 abort();
3048 }
3049 fence_emitted = true;
3050 if (queue->device->trace_bo) {
3051 radv_check_gpu_hangs(queue, cs_array[j]);
3052 }
3053 }
3054
3055 radv_free_temp_syncobjs(queue->device,
3056 pSubmits[i].waitSemaphoreCount,
3057 pSubmits[i].pWaitSemaphores);
3058 radv_free_sem_info(&sem_info);
3059 free(cs_array);
3060 }
3061
3062 if (fence) {
3063 if (!fence_emitted) {
3064 result = radv_signal_fence(queue, fence);
3065 if (result != VK_SUCCESS)
3066 return result;
3067 }
3068 }
3069
3070 return VK_SUCCESS;
3071 }
3072
3073 VkResult radv_QueueWaitIdle(
3074 VkQueue _queue)
3075 {
3076 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3077
3078 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3079 radv_queue_family_to_ring(queue->queue_family_index),
3080 queue->queue_idx);
3081 return VK_SUCCESS;
3082 }
3083
3084 VkResult radv_DeviceWaitIdle(
3085 VkDevice _device)
3086 {
3087 RADV_FROM_HANDLE(radv_device, device, _device);
3088
3089 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3090 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3091 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3092 }
3093 }
3094 return VK_SUCCESS;
3095 }
3096
3097 VkResult radv_EnumerateInstanceExtensionProperties(
3098 const char* pLayerName,
3099 uint32_t* pPropertyCount,
3100 VkExtensionProperties* pProperties)
3101 {
3102 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3103
3104 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3105 if (radv_supported_instance_extensions.extensions[i]) {
3106 vk_outarray_append(&out, prop) {
3107 *prop = radv_instance_extensions[i];
3108 }
3109 }
3110 }
3111
3112 return vk_outarray_status(&out);
3113 }
3114
3115 VkResult radv_EnumerateDeviceExtensionProperties(
3116 VkPhysicalDevice physicalDevice,
3117 const char* pLayerName,
3118 uint32_t* pPropertyCount,
3119 VkExtensionProperties* pProperties)
3120 {
3121 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3122 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3123
3124 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3125 if (device->supported_extensions.extensions[i]) {
3126 vk_outarray_append(&out, prop) {
3127 *prop = radv_device_extensions[i];
3128 }
3129 }
3130 }
3131
3132 return vk_outarray_status(&out);
3133 }
3134
3135 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3136 VkInstance _instance,
3137 const char* pName)
3138 {
3139 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3140
3141 return radv_lookup_entrypoint_checked(pName,
3142 instance ? instance->apiVersion : 0,
3143 instance ? &instance->enabled_extensions : NULL,
3144 NULL);
3145 }
3146
3147 /* The loader wants us to expose a second GetInstanceProcAddr function
3148 * to work around certain LD_PRELOAD issues seen in apps.
3149 */
3150 PUBLIC
3151 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3152 VkInstance instance,
3153 const char* pName);
3154
3155 PUBLIC
3156 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3157 VkInstance instance,
3158 const char* pName)
3159 {
3160 return radv_GetInstanceProcAddr(instance, pName);
3161 }
3162
3163 PUBLIC
3164 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3165 VkInstance _instance,
3166 const char* pName);
3167
3168 PUBLIC
3169 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3170 VkInstance _instance,
3171 const char* pName)
3172 {
3173 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3174
3175 return radv_lookup_physical_device_entrypoint_checked(pName,
3176 instance ? instance->apiVersion : 0,
3177 instance ? &instance->enabled_extensions : NULL);
3178 }
3179
3180 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3181 VkDevice _device,
3182 const char* pName)
3183 {
3184 RADV_FROM_HANDLE(radv_device, device, _device);
3185
3186 return radv_lookup_entrypoint_checked(pName,
3187 device->instance->apiVersion,
3188 &device->instance->enabled_extensions,
3189 &device->enabled_extensions);
3190 }
3191
3192 bool radv_get_memory_fd(struct radv_device *device,
3193 struct radv_device_memory *memory,
3194 int *pFD)
3195 {
3196 struct radeon_bo_metadata metadata;
3197
3198 if (memory->image) {
3199 radv_init_metadata(device, memory->image, &metadata);
3200 device->ws->buffer_set_metadata(memory->bo, &metadata);
3201 }
3202
3203 return device->ws->buffer_get_fd(device->ws, memory->bo,
3204 pFD);
3205 }
3206
3207 static VkResult radv_alloc_memory(struct radv_device *device,
3208 const VkMemoryAllocateInfo* pAllocateInfo,
3209 const VkAllocationCallbacks* pAllocator,
3210 VkDeviceMemory* pMem)
3211 {
3212 struct radv_device_memory *mem;
3213 VkResult result;
3214 enum radeon_bo_domain domain;
3215 uint32_t flags = 0;
3216 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3217
3218 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3219
3220 if (pAllocateInfo->allocationSize == 0) {
3221 /* Apparently, this is allowed */
3222 *pMem = VK_NULL_HANDLE;
3223 return VK_SUCCESS;
3224 }
3225
3226 const VkImportMemoryFdInfoKHR *import_info =
3227 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3228 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3229 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3230 const VkExportMemoryAllocateInfo *export_info =
3231 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3232 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3233 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3234
3235 const struct wsi_memory_allocate_info *wsi_info =
3236 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3237
3238 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3239 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3240 if (mem == NULL)
3241 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3242
3243 if (wsi_info && wsi_info->implicit_sync)
3244 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3245
3246 if (dedicate_info) {
3247 mem->image = radv_image_from_handle(dedicate_info->image);
3248 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3249 } else {
3250 mem->image = NULL;
3251 mem->buffer = NULL;
3252 }
3253
3254 float priority_float = 0.5;
3255 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3256 vk_find_struct_const(pAllocateInfo->pNext,
3257 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3258 if (priority_ext)
3259 priority_float = priority_ext->priority;
3260
3261 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3262 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3263
3264 mem->user_ptr = NULL;
3265
3266 if (import_info) {
3267 assert(import_info->handleType ==
3268 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3269 import_info->handleType ==
3270 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3271 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3272 priority, NULL, NULL);
3273 if (!mem->bo) {
3274 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3275 goto fail;
3276 } else {
3277 close(import_info->fd);
3278 }
3279 } else if (host_ptr_info) {
3280 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3281 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3282 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3283 pAllocateInfo->allocationSize,
3284 priority);
3285 if (!mem->bo) {
3286 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3287 goto fail;
3288 } else {
3289 mem->user_ptr = host_ptr_info->pHostPointer;
3290 }
3291 } else {
3292 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3293 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3294 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3295 domain = RADEON_DOMAIN_GTT;
3296 else
3297 domain = RADEON_DOMAIN_VRAM;
3298
3299 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3300 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3301 else
3302 flags |= RADEON_FLAG_CPU_ACCESS;
3303
3304 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3305 flags |= RADEON_FLAG_GTT_WC;
3306
3307 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3308 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3309 if (device->use_global_bo_list) {
3310 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3311 }
3312 }
3313
3314 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3315 domain, flags, priority);
3316
3317 if (!mem->bo) {
3318 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3319 goto fail;
3320 }
3321 mem->type_index = mem_type_index;
3322 }
3323
3324 result = radv_bo_list_add(device, mem->bo);
3325 if (result != VK_SUCCESS)
3326 goto fail_bo;
3327
3328 *pMem = radv_device_memory_to_handle(mem);
3329
3330 return VK_SUCCESS;
3331
3332 fail_bo:
3333 device->ws->buffer_destroy(mem->bo);
3334 fail:
3335 vk_free2(&device->alloc, pAllocator, mem);
3336
3337 return result;
3338 }
3339
3340 VkResult radv_AllocateMemory(
3341 VkDevice _device,
3342 const VkMemoryAllocateInfo* pAllocateInfo,
3343 const VkAllocationCallbacks* pAllocator,
3344 VkDeviceMemory* pMem)
3345 {
3346 RADV_FROM_HANDLE(radv_device, device, _device);
3347 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3348 }
3349
3350 void radv_FreeMemory(
3351 VkDevice _device,
3352 VkDeviceMemory _mem,
3353 const VkAllocationCallbacks* pAllocator)
3354 {
3355 RADV_FROM_HANDLE(radv_device, device, _device);
3356 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3357
3358 if (mem == NULL)
3359 return;
3360
3361 radv_bo_list_remove(device, mem->bo);
3362 device->ws->buffer_destroy(mem->bo);
3363 mem->bo = NULL;
3364
3365 vk_free2(&device->alloc, pAllocator, mem);
3366 }
3367
3368 VkResult radv_MapMemory(
3369 VkDevice _device,
3370 VkDeviceMemory _memory,
3371 VkDeviceSize offset,
3372 VkDeviceSize size,
3373 VkMemoryMapFlags flags,
3374 void** ppData)
3375 {
3376 RADV_FROM_HANDLE(radv_device, device, _device);
3377 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3378
3379 if (mem == NULL) {
3380 *ppData = NULL;
3381 return VK_SUCCESS;
3382 }
3383
3384 if (mem->user_ptr)
3385 *ppData = mem->user_ptr;
3386 else
3387 *ppData = device->ws->buffer_map(mem->bo);
3388
3389 if (*ppData) {
3390 *ppData += offset;
3391 return VK_SUCCESS;
3392 }
3393
3394 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3395 }
3396
3397 void radv_UnmapMemory(
3398 VkDevice _device,
3399 VkDeviceMemory _memory)
3400 {
3401 RADV_FROM_HANDLE(radv_device, device, _device);
3402 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3403
3404 if (mem == NULL)
3405 return;
3406
3407 if (mem->user_ptr == NULL)
3408 device->ws->buffer_unmap(mem->bo);
3409 }
3410
3411 VkResult radv_FlushMappedMemoryRanges(
3412 VkDevice _device,
3413 uint32_t memoryRangeCount,
3414 const VkMappedMemoryRange* pMemoryRanges)
3415 {
3416 return VK_SUCCESS;
3417 }
3418
3419 VkResult radv_InvalidateMappedMemoryRanges(
3420 VkDevice _device,
3421 uint32_t memoryRangeCount,
3422 const VkMappedMemoryRange* pMemoryRanges)
3423 {
3424 return VK_SUCCESS;
3425 }
3426
3427 void radv_GetBufferMemoryRequirements(
3428 VkDevice _device,
3429 VkBuffer _buffer,
3430 VkMemoryRequirements* pMemoryRequirements)
3431 {
3432 RADV_FROM_HANDLE(radv_device, device, _device);
3433 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3434
3435 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3436
3437 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3438 pMemoryRequirements->alignment = 4096;
3439 else
3440 pMemoryRequirements->alignment = 16;
3441
3442 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3443 }
3444
3445 void radv_GetBufferMemoryRequirements2(
3446 VkDevice device,
3447 const VkBufferMemoryRequirementsInfo2 *pInfo,
3448 VkMemoryRequirements2 *pMemoryRequirements)
3449 {
3450 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3451 &pMemoryRequirements->memoryRequirements);
3452 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3453 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3454 switch (ext->sType) {
3455 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3456 VkMemoryDedicatedRequirements *req =
3457 (VkMemoryDedicatedRequirements *) ext;
3458 req->requiresDedicatedAllocation = buffer->shareable;
3459 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3460 break;
3461 }
3462 default:
3463 break;
3464 }
3465 }
3466 }
3467
3468 void radv_GetImageMemoryRequirements(
3469 VkDevice _device,
3470 VkImage _image,
3471 VkMemoryRequirements* pMemoryRequirements)
3472 {
3473 RADV_FROM_HANDLE(radv_device, device, _device);
3474 RADV_FROM_HANDLE(radv_image, image, _image);
3475
3476 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3477
3478 pMemoryRequirements->size = image->size;
3479 pMemoryRequirements->alignment = image->alignment;
3480 }
3481
3482 void radv_GetImageMemoryRequirements2(
3483 VkDevice device,
3484 const VkImageMemoryRequirementsInfo2 *pInfo,
3485 VkMemoryRequirements2 *pMemoryRequirements)
3486 {
3487 radv_GetImageMemoryRequirements(device, pInfo->image,
3488 &pMemoryRequirements->memoryRequirements);
3489
3490 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3491
3492 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3493 switch (ext->sType) {
3494 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3495 VkMemoryDedicatedRequirements *req =
3496 (VkMemoryDedicatedRequirements *) ext;
3497 req->requiresDedicatedAllocation = image->shareable;
3498 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3499 break;
3500 }
3501 default:
3502 break;
3503 }
3504 }
3505 }
3506
3507 void radv_GetImageSparseMemoryRequirements(
3508 VkDevice device,
3509 VkImage image,
3510 uint32_t* pSparseMemoryRequirementCount,
3511 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3512 {
3513 stub();
3514 }
3515
3516 void radv_GetImageSparseMemoryRequirements2(
3517 VkDevice device,
3518 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3519 uint32_t* pSparseMemoryRequirementCount,
3520 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3521 {
3522 stub();
3523 }
3524
3525 void radv_GetDeviceMemoryCommitment(
3526 VkDevice device,
3527 VkDeviceMemory memory,
3528 VkDeviceSize* pCommittedMemoryInBytes)
3529 {
3530 *pCommittedMemoryInBytes = 0;
3531 }
3532
3533 VkResult radv_BindBufferMemory2(VkDevice device,
3534 uint32_t bindInfoCount,
3535 const VkBindBufferMemoryInfo *pBindInfos)
3536 {
3537 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3538 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3539 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3540
3541 if (mem) {
3542 buffer->bo = mem->bo;
3543 buffer->offset = pBindInfos[i].memoryOffset;
3544 } else {
3545 buffer->bo = NULL;
3546 }
3547 }
3548 return VK_SUCCESS;
3549 }
3550
3551 VkResult radv_BindBufferMemory(
3552 VkDevice device,
3553 VkBuffer buffer,
3554 VkDeviceMemory memory,
3555 VkDeviceSize memoryOffset)
3556 {
3557 const VkBindBufferMemoryInfo info = {
3558 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3559 .buffer = buffer,
3560 .memory = memory,
3561 .memoryOffset = memoryOffset
3562 };
3563
3564 return radv_BindBufferMemory2(device, 1, &info);
3565 }
3566
3567 VkResult radv_BindImageMemory2(VkDevice device,
3568 uint32_t bindInfoCount,
3569 const VkBindImageMemoryInfo *pBindInfos)
3570 {
3571 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3572 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3573 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3574
3575 if (mem) {
3576 image->bo = mem->bo;
3577 image->offset = pBindInfos[i].memoryOffset;
3578 } else {
3579 image->bo = NULL;
3580 image->offset = 0;
3581 }
3582 }
3583 return VK_SUCCESS;
3584 }
3585
3586
3587 VkResult radv_BindImageMemory(
3588 VkDevice device,
3589 VkImage image,
3590 VkDeviceMemory memory,
3591 VkDeviceSize memoryOffset)
3592 {
3593 const VkBindImageMemoryInfo info = {
3594 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3595 .image = image,
3596 .memory = memory,
3597 .memoryOffset = memoryOffset
3598 };
3599
3600 return radv_BindImageMemory2(device, 1, &info);
3601 }
3602
3603
3604 static void
3605 radv_sparse_buffer_bind_memory(struct radv_device *device,
3606 const VkSparseBufferMemoryBindInfo *bind)
3607 {
3608 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3609
3610 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3611 struct radv_device_memory *mem = NULL;
3612
3613 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3614 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3615
3616 device->ws->buffer_virtual_bind(buffer->bo,
3617 bind->pBinds[i].resourceOffset,
3618 bind->pBinds[i].size,
3619 mem ? mem->bo : NULL,
3620 bind->pBinds[i].memoryOffset);
3621 }
3622 }
3623
3624 static void
3625 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3626 const VkSparseImageOpaqueMemoryBindInfo *bind)
3627 {
3628 RADV_FROM_HANDLE(radv_image, image, bind->image);
3629
3630 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3631 struct radv_device_memory *mem = NULL;
3632
3633 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3634 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3635
3636 device->ws->buffer_virtual_bind(image->bo,
3637 bind->pBinds[i].resourceOffset,
3638 bind->pBinds[i].size,
3639 mem ? mem->bo : NULL,
3640 bind->pBinds[i].memoryOffset);
3641 }
3642 }
3643
3644 VkResult radv_QueueBindSparse(
3645 VkQueue _queue,
3646 uint32_t bindInfoCount,
3647 const VkBindSparseInfo* pBindInfo,
3648 VkFence _fence)
3649 {
3650 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3651 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3652 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3653 bool fence_emitted = false;
3654 VkResult result;
3655 int ret;
3656
3657 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3658 struct radv_winsys_sem_info sem_info;
3659 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3660 radv_sparse_buffer_bind_memory(queue->device,
3661 pBindInfo[i].pBufferBinds + j);
3662 }
3663
3664 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3665 radv_sparse_image_opaque_bind_memory(queue->device,
3666 pBindInfo[i].pImageOpaqueBinds + j);
3667 }
3668
3669 VkResult result;
3670 result = radv_alloc_sem_info(queue->device->instance,
3671 &sem_info,
3672 pBindInfo[i].waitSemaphoreCount,
3673 pBindInfo[i].pWaitSemaphores,
3674 pBindInfo[i].signalSemaphoreCount,
3675 pBindInfo[i].pSignalSemaphores,
3676 _fence);
3677 if (result != VK_SUCCESS)
3678 return result;
3679
3680 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3681 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3682 &queue->device->empty_cs[queue->queue_family_index],
3683 1, NULL, NULL,
3684 &sem_info, NULL,
3685 false, base_fence);
3686 if (ret) {
3687 radv_loge("failed to submit CS %d\n", i);
3688 abort();
3689 }
3690
3691 fence_emitted = true;
3692 }
3693
3694 radv_free_sem_info(&sem_info);
3695
3696 }
3697
3698 if (fence) {
3699 if (!fence_emitted) {
3700 result = radv_signal_fence(queue, fence);
3701 if (result != VK_SUCCESS)
3702 return result;
3703 }
3704 }
3705
3706 return VK_SUCCESS;
3707 }
3708
3709 VkResult radv_CreateFence(
3710 VkDevice _device,
3711 const VkFenceCreateInfo* pCreateInfo,
3712 const VkAllocationCallbacks* pAllocator,
3713 VkFence* pFence)
3714 {
3715 RADV_FROM_HANDLE(radv_device, device, _device);
3716 const VkExportFenceCreateInfo *export =
3717 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3718 VkExternalFenceHandleTypeFlags handleTypes =
3719 export ? export->handleTypes : 0;
3720
3721 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3722 sizeof(*fence), 8,
3723 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3724
3725 if (!fence)
3726 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3727
3728 fence->fence_wsi = NULL;
3729 fence->temp_syncobj = 0;
3730 if (device->always_use_syncobj || handleTypes) {
3731 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3732 if (ret) {
3733 vk_free2(&device->alloc, pAllocator, fence);
3734 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3735 }
3736 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3737 device->ws->signal_syncobj(device->ws, fence->syncobj);
3738 }
3739 fence->fence = NULL;
3740 } else {
3741 fence->fence = device->ws->create_fence();
3742 if (!fence->fence) {
3743 vk_free2(&device->alloc, pAllocator, fence);
3744 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3745 }
3746 fence->syncobj = 0;
3747 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3748 device->ws->signal_fence(fence->fence);
3749 }
3750
3751 *pFence = radv_fence_to_handle(fence);
3752
3753 return VK_SUCCESS;
3754 }
3755
3756 void radv_DestroyFence(
3757 VkDevice _device,
3758 VkFence _fence,
3759 const VkAllocationCallbacks* pAllocator)
3760 {
3761 RADV_FROM_HANDLE(radv_device, device, _device);
3762 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3763
3764 if (!fence)
3765 return;
3766
3767 if (fence->temp_syncobj)
3768 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3769 if (fence->syncobj)
3770 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3771 if (fence->fence)
3772 device->ws->destroy_fence(fence->fence);
3773 if (fence->fence_wsi)
3774 fence->fence_wsi->destroy(fence->fence_wsi);
3775 vk_free2(&device->alloc, pAllocator, fence);
3776 }
3777
3778
3779 uint64_t radv_get_current_time(void)
3780 {
3781 struct timespec tv;
3782 clock_gettime(CLOCK_MONOTONIC, &tv);
3783 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3784 }
3785
3786 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3787 {
3788 uint64_t current_time = radv_get_current_time();
3789
3790 timeout = MIN2(UINT64_MAX - current_time, timeout);
3791
3792 return current_time + timeout;
3793 }
3794
3795
3796 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3797 uint32_t fenceCount, const VkFence *pFences)
3798 {
3799 for (uint32_t i = 0; i < fenceCount; ++i) {
3800 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3801 if (fence->fence == NULL || fence->syncobj ||
3802 fence->temp_syncobj || fence->fence_wsi ||
3803 (!device->ws->is_fence_waitable(fence->fence)))
3804 return false;
3805 }
3806 return true;
3807 }
3808
3809 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3810 {
3811 for (uint32_t i = 0; i < fenceCount; ++i) {
3812 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3813 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3814 return false;
3815 }
3816 return true;
3817 }
3818
3819 VkResult radv_WaitForFences(
3820 VkDevice _device,
3821 uint32_t fenceCount,
3822 const VkFence* pFences,
3823 VkBool32 waitAll,
3824 uint64_t timeout)
3825 {
3826 RADV_FROM_HANDLE(radv_device, device, _device);
3827 timeout = radv_get_absolute_timeout(timeout);
3828
3829 if (device->always_use_syncobj &&
3830 radv_all_fences_syncobj(fenceCount, pFences))
3831 {
3832 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3833 if (!handles)
3834 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3835
3836 for (uint32_t i = 0; i < fenceCount; ++i) {
3837 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3838 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3839 }
3840
3841 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3842
3843 free(handles);
3844 return success ? VK_SUCCESS : VK_TIMEOUT;
3845 }
3846
3847 if (!waitAll && fenceCount > 1) {
3848 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3849 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3850 uint32_t wait_count = 0;
3851 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3852 if (!fences)
3853 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3854
3855 for (uint32_t i = 0; i < fenceCount; ++i) {
3856 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3857
3858 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3859 free(fences);
3860 return VK_SUCCESS;
3861 }
3862
3863 fences[wait_count++] = fence->fence;
3864 }
3865
3866 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3867 waitAll, timeout - radv_get_current_time());
3868
3869 free(fences);
3870 return success ? VK_SUCCESS : VK_TIMEOUT;
3871 }
3872
3873 while(radv_get_current_time() <= timeout) {
3874 for (uint32_t i = 0; i < fenceCount; ++i) {
3875 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3876 return VK_SUCCESS;
3877 }
3878 }
3879 return VK_TIMEOUT;
3880 }
3881
3882 for (uint32_t i = 0; i < fenceCount; ++i) {
3883 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3884 bool expired = false;
3885
3886 if (fence->temp_syncobj) {
3887 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3888 return VK_TIMEOUT;
3889 continue;
3890 }
3891
3892 if (fence->syncobj) {
3893 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3894 return VK_TIMEOUT;
3895 continue;
3896 }
3897
3898 if (fence->fence) {
3899 if (!device->ws->is_fence_waitable(fence->fence)) {
3900 while(!device->ws->is_fence_waitable(fence->fence) &&
3901 radv_get_current_time() <= timeout)
3902 /* Do nothing */;
3903 }
3904
3905 expired = device->ws->fence_wait(device->ws,
3906 fence->fence,
3907 true, timeout);
3908 if (!expired)
3909 return VK_TIMEOUT;
3910 }
3911
3912 if (fence->fence_wsi) {
3913 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3914 if (result != VK_SUCCESS)
3915 return result;
3916 }
3917 }
3918
3919 return VK_SUCCESS;
3920 }
3921
3922 VkResult radv_ResetFences(VkDevice _device,
3923 uint32_t fenceCount,
3924 const VkFence *pFences)
3925 {
3926 RADV_FROM_HANDLE(radv_device, device, _device);
3927
3928 for (unsigned i = 0; i < fenceCount; ++i) {
3929 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3930 if (fence->fence)
3931 device->ws->reset_fence(fence->fence);
3932
3933 /* Per spec, we first restore the permanent payload, and then reset, so
3934 * having a temp syncobj should not skip resetting the permanent syncobj. */
3935 if (fence->temp_syncobj) {
3936 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3937 fence->temp_syncobj = 0;
3938 }
3939
3940 if (fence->syncobj) {
3941 device->ws->reset_syncobj(device->ws, fence->syncobj);
3942 }
3943 }
3944
3945 return VK_SUCCESS;
3946 }
3947
3948 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3949 {
3950 RADV_FROM_HANDLE(radv_device, device, _device);
3951 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3952
3953 if (fence->temp_syncobj) {
3954 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3955 return success ? VK_SUCCESS : VK_NOT_READY;
3956 }
3957
3958 if (fence->syncobj) {
3959 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3960 return success ? VK_SUCCESS : VK_NOT_READY;
3961 }
3962
3963 if (fence->fence) {
3964 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3965 return VK_NOT_READY;
3966 }
3967 if (fence->fence_wsi) {
3968 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3969
3970 if (result != VK_SUCCESS) {
3971 if (result == VK_TIMEOUT)
3972 return VK_NOT_READY;
3973 return result;
3974 }
3975 }
3976 return VK_SUCCESS;
3977 }
3978
3979
3980 // Queue semaphore functions
3981
3982 VkResult radv_CreateSemaphore(
3983 VkDevice _device,
3984 const VkSemaphoreCreateInfo* pCreateInfo,
3985 const VkAllocationCallbacks* pAllocator,
3986 VkSemaphore* pSemaphore)
3987 {
3988 RADV_FROM_HANDLE(radv_device, device, _device);
3989 const VkExportSemaphoreCreateInfo *export =
3990 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3991 VkExternalSemaphoreHandleTypeFlags handleTypes =
3992 export ? export->handleTypes : 0;
3993
3994 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3995 sizeof(*sem), 8,
3996 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3997 if (!sem)
3998 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3999
4000 sem->temp_syncobj = 0;
4001 /* create a syncobject if we are going to export this semaphore */
4002 if (device->always_use_syncobj || handleTypes) {
4003 assert (device->physical_device->rad_info.has_syncobj);
4004 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4005 if (ret) {
4006 vk_free2(&device->alloc, pAllocator, sem);
4007 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4008 }
4009 sem->sem = NULL;
4010 } else {
4011 sem->sem = device->ws->create_sem(device->ws);
4012 if (!sem->sem) {
4013 vk_free2(&device->alloc, pAllocator, sem);
4014 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4015 }
4016 sem->syncobj = 0;
4017 }
4018
4019 *pSemaphore = radv_semaphore_to_handle(sem);
4020 return VK_SUCCESS;
4021 }
4022
4023 void radv_DestroySemaphore(
4024 VkDevice _device,
4025 VkSemaphore _semaphore,
4026 const VkAllocationCallbacks* pAllocator)
4027 {
4028 RADV_FROM_HANDLE(radv_device, device, _device);
4029 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4030 if (!_semaphore)
4031 return;
4032
4033 if (sem->syncobj)
4034 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4035 else
4036 device->ws->destroy_sem(sem->sem);
4037 vk_free2(&device->alloc, pAllocator, sem);
4038 }
4039
4040 VkResult radv_CreateEvent(
4041 VkDevice _device,
4042 const VkEventCreateInfo* pCreateInfo,
4043 const VkAllocationCallbacks* pAllocator,
4044 VkEvent* pEvent)
4045 {
4046 RADV_FROM_HANDLE(radv_device, device, _device);
4047 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4048 sizeof(*event), 8,
4049 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4050
4051 if (!event)
4052 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4053
4054 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4055 RADEON_DOMAIN_GTT,
4056 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4057 RADV_BO_PRIORITY_FENCE);
4058 if (!event->bo) {
4059 vk_free2(&device->alloc, pAllocator, event);
4060 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4061 }
4062
4063 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4064
4065 *pEvent = radv_event_to_handle(event);
4066
4067 return VK_SUCCESS;
4068 }
4069
4070 void radv_DestroyEvent(
4071 VkDevice _device,
4072 VkEvent _event,
4073 const VkAllocationCallbacks* pAllocator)
4074 {
4075 RADV_FROM_HANDLE(radv_device, device, _device);
4076 RADV_FROM_HANDLE(radv_event, event, _event);
4077
4078 if (!event)
4079 return;
4080 device->ws->buffer_destroy(event->bo);
4081 vk_free2(&device->alloc, pAllocator, event);
4082 }
4083
4084 VkResult radv_GetEventStatus(
4085 VkDevice _device,
4086 VkEvent _event)
4087 {
4088 RADV_FROM_HANDLE(radv_event, event, _event);
4089
4090 if (*event->map == 1)
4091 return VK_EVENT_SET;
4092 return VK_EVENT_RESET;
4093 }
4094
4095 VkResult radv_SetEvent(
4096 VkDevice _device,
4097 VkEvent _event)
4098 {
4099 RADV_FROM_HANDLE(radv_event, event, _event);
4100 *event->map = 1;
4101
4102 return VK_SUCCESS;
4103 }
4104
4105 VkResult radv_ResetEvent(
4106 VkDevice _device,
4107 VkEvent _event)
4108 {
4109 RADV_FROM_HANDLE(radv_event, event, _event);
4110 *event->map = 0;
4111
4112 return VK_SUCCESS;
4113 }
4114
4115 VkResult radv_CreateBuffer(
4116 VkDevice _device,
4117 const VkBufferCreateInfo* pCreateInfo,
4118 const VkAllocationCallbacks* pAllocator,
4119 VkBuffer* pBuffer)
4120 {
4121 RADV_FROM_HANDLE(radv_device, device, _device);
4122 struct radv_buffer *buffer;
4123
4124 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4125
4126 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4127 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4128 if (buffer == NULL)
4129 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4130
4131 buffer->size = pCreateInfo->size;
4132 buffer->usage = pCreateInfo->usage;
4133 buffer->bo = NULL;
4134 buffer->offset = 0;
4135 buffer->flags = pCreateInfo->flags;
4136
4137 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4138 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4139
4140 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4141 buffer->bo = device->ws->buffer_create(device->ws,
4142 align64(buffer->size, 4096),
4143 4096, 0, RADEON_FLAG_VIRTUAL,
4144 RADV_BO_PRIORITY_VIRTUAL);
4145 if (!buffer->bo) {
4146 vk_free2(&device->alloc, pAllocator, buffer);
4147 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4148 }
4149 }
4150
4151 *pBuffer = radv_buffer_to_handle(buffer);
4152
4153 return VK_SUCCESS;
4154 }
4155
4156 void radv_DestroyBuffer(
4157 VkDevice _device,
4158 VkBuffer _buffer,
4159 const VkAllocationCallbacks* pAllocator)
4160 {
4161 RADV_FROM_HANDLE(radv_device, device, _device);
4162 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4163
4164 if (!buffer)
4165 return;
4166
4167 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4168 device->ws->buffer_destroy(buffer->bo);
4169
4170 vk_free2(&device->alloc, pAllocator, buffer);
4171 }
4172
4173 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4174 VkDevice device,
4175 const VkBufferDeviceAddressInfoEXT* pInfo)
4176 {
4177 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4178 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4179 }
4180
4181
4182 static inline unsigned
4183 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4184 {
4185 if (stencil)
4186 return plane->surface.u.legacy.stencil_tiling_index[level];
4187 else
4188 return plane->surface.u.legacy.tiling_index[level];
4189 }
4190
4191 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4192 {
4193 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4194 }
4195
4196 static uint32_t
4197 radv_init_dcc_control_reg(struct radv_device *device,
4198 struct radv_image_view *iview)
4199 {
4200 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4201 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4202 unsigned max_compressed_block_size;
4203 unsigned independent_64b_blocks;
4204
4205 if (!radv_image_has_dcc(iview->image))
4206 return 0;
4207
4208 if (iview->image->info.samples > 1) {
4209 if (iview->image->planes[0].surface.bpe == 1)
4210 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4211 else if (iview->image->planes[0].surface.bpe == 2)
4212 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4213 }
4214
4215 if (!device->physical_device->rad_info.has_dedicated_vram) {
4216 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4217 * dGPU and 64 for APU because all of our APUs to date use
4218 * DIMMs which have a request granularity size of 64B while all
4219 * other chips have a 32B request size.
4220 */
4221 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4222 }
4223
4224 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4225 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4226 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4227 /* If this DCC image is potentially going to be used in texture
4228 * fetches, we need some special settings.
4229 */
4230 independent_64b_blocks = 1;
4231 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4232 } else {
4233 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4234 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4235 * big as possible for better compression state.
4236 */
4237 independent_64b_blocks = 0;
4238 max_compressed_block_size = max_uncompressed_block_size;
4239 }
4240
4241 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4242 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4243 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4244 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4245 }
4246
4247 static void
4248 radv_initialise_color_surface(struct radv_device *device,
4249 struct radv_color_buffer_info *cb,
4250 struct radv_image_view *iview)
4251 {
4252 const struct vk_format_description *desc;
4253 unsigned ntype, format, swap, endian;
4254 unsigned blend_clamp = 0, blend_bypass = 0;
4255 uint64_t va;
4256 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4257 const struct radeon_surf *surf = &plane->surface;
4258
4259 desc = vk_format_description(iview->vk_format);
4260
4261 memset(cb, 0, sizeof(*cb));
4262
4263 /* Intensity is implemented as Red, so treat it that way. */
4264 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4265
4266 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4267
4268 cb->cb_color_base = va >> 8;
4269
4270 if (device->physical_device->rad_info.chip_class >= GFX9) {
4271 struct gfx9_surf_meta_flags meta;
4272 if (iview->image->dcc_offset)
4273 meta = surf->u.gfx9.dcc;
4274 else
4275 meta = surf->u.gfx9.cmask;
4276
4277 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4278 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4279 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4280 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4281
4282 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4283 cb->cb_color_base |= surf->tile_swizzle;
4284
4285 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4286 } else {
4287 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4288 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4289
4290 cb->cb_color_base += level_info->offset >> 8;
4291 if (level_info->mode == RADEON_SURF_MODE_2D)
4292 cb->cb_color_base |= surf->tile_swizzle;
4293
4294 pitch_tile_max = level_info->nblk_x / 8 - 1;
4295 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4296 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4297
4298 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4299 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4300 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4301
4302 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4303
4304 if (radv_image_has_fmask(iview->image)) {
4305 if (device->physical_device->rad_info.chip_class >= GFX7)
4306 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4307 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4308 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4309 } else {
4310 /* This must be set for fast clear to work without FMASK. */
4311 if (device->physical_device->rad_info.chip_class >= GFX7)
4312 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4313 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4314 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4315 }
4316 }
4317
4318 /* CMASK variables */
4319 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4320 va += iview->image->cmask.offset;
4321 cb->cb_color_cmask = va >> 8;
4322
4323 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4324 va += iview->image->dcc_offset;
4325 cb->cb_dcc_base = va >> 8;
4326 cb->cb_dcc_base |= surf->tile_swizzle;
4327
4328 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4329 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4330 S_028C6C_SLICE_MAX(max_slice);
4331
4332 if (iview->image->info.samples > 1) {
4333 unsigned log_samples = util_logbase2(iview->image->info.samples);
4334
4335 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4336 S_028C74_NUM_FRAGMENTS(log_samples);
4337 }
4338
4339 if (radv_image_has_fmask(iview->image)) {
4340 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4341 cb->cb_color_fmask = va >> 8;
4342 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4343 } else {
4344 cb->cb_color_fmask = cb->cb_color_base;
4345 }
4346
4347 ntype = radv_translate_color_numformat(iview->vk_format,
4348 desc,
4349 vk_format_get_first_non_void_channel(iview->vk_format));
4350 format = radv_translate_colorformat(iview->vk_format);
4351 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4352 radv_finishme("Illegal color\n");
4353 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4354 endian = radv_colorformat_endian_swap(format);
4355
4356 /* blend clamp should be set for all NORM/SRGB types */
4357 if (ntype == V_028C70_NUMBER_UNORM ||
4358 ntype == V_028C70_NUMBER_SNORM ||
4359 ntype == V_028C70_NUMBER_SRGB)
4360 blend_clamp = 1;
4361
4362 /* set blend bypass according to docs if SINT/UINT or
4363 8/24 COLOR variants */
4364 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4365 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4366 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4367 blend_clamp = 0;
4368 blend_bypass = 1;
4369 }
4370 #if 0
4371 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4372 (format == V_028C70_COLOR_8 ||
4373 format == V_028C70_COLOR_8_8 ||
4374 format == V_028C70_COLOR_8_8_8_8))
4375 ->color_is_int8 = true;
4376 #endif
4377 cb->cb_color_info = S_028C70_FORMAT(format) |
4378 S_028C70_COMP_SWAP(swap) |
4379 S_028C70_BLEND_CLAMP(blend_clamp) |
4380 S_028C70_BLEND_BYPASS(blend_bypass) |
4381 S_028C70_SIMPLE_FLOAT(1) |
4382 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4383 ntype != V_028C70_NUMBER_SNORM &&
4384 ntype != V_028C70_NUMBER_SRGB &&
4385 format != V_028C70_COLOR_8_24 &&
4386 format != V_028C70_COLOR_24_8) |
4387 S_028C70_NUMBER_TYPE(ntype) |
4388 S_028C70_ENDIAN(endian);
4389 if (radv_image_has_fmask(iview->image)) {
4390 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4391 if (device->physical_device->rad_info.chip_class == GFX6) {
4392 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4393 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4394 }
4395 }
4396
4397 if (radv_image_has_cmask(iview->image) &&
4398 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4399 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4400
4401 if (radv_dcc_enabled(iview->image, iview->base_mip))
4402 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4403
4404 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4405
4406 /* This must be set for fast clear to work without FMASK. */
4407 if (!radv_image_has_fmask(iview->image) &&
4408 device->physical_device->rad_info.chip_class == GFX6) {
4409 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4410 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4411 }
4412
4413 if (device->physical_device->rad_info.chip_class >= GFX9) {
4414 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4415
4416 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4417 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4418 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4419 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4420
4421 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4422 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4423 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4424 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4425 S_028C68_MIP0_HEIGHT(height - 1) |
4426 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4427 }
4428 }
4429
4430 static unsigned
4431 radv_calc_decompress_on_z_planes(struct radv_device *device,
4432 struct radv_image_view *iview)
4433 {
4434 unsigned max_zplanes = 0;
4435
4436 assert(radv_image_is_tc_compat_htile(iview->image));
4437
4438 if (device->physical_device->rad_info.chip_class >= GFX9) {
4439 /* Default value for 32-bit depth surfaces. */
4440 max_zplanes = 4;
4441
4442 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4443 iview->image->info.samples > 1)
4444 max_zplanes = 2;
4445
4446 max_zplanes = max_zplanes + 1;
4447 } else {
4448 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4449 /* Do not enable Z plane compression for 16-bit depth
4450 * surfaces because isn't supported on GFX8. Only
4451 * 32-bit depth surfaces are supported by the hardware.
4452 * This allows to maintain shader compatibility and to
4453 * reduce the number of depth decompressions.
4454 */
4455 max_zplanes = 1;
4456 } else {
4457 if (iview->image->info.samples <= 1)
4458 max_zplanes = 5;
4459 else if (iview->image->info.samples <= 4)
4460 max_zplanes = 3;
4461 else
4462 max_zplanes = 2;
4463 }
4464 }
4465
4466 return max_zplanes;
4467 }
4468
4469 static void
4470 radv_initialise_ds_surface(struct radv_device *device,
4471 struct radv_ds_buffer_info *ds,
4472 struct radv_image_view *iview)
4473 {
4474 unsigned level = iview->base_mip;
4475 unsigned format, stencil_format;
4476 uint64_t va, s_offs, z_offs;
4477 bool stencil_only = false;
4478 const struct radv_image_plane *plane = &iview->image->planes[0];
4479 const struct radeon_surf *surf = &plane->surface;
4480
4481 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4482
4483 memset(ds, 0, sizeof(*ds));
4484 switch (iview->image->vk_format) {
4485 case VK_FORMAT_D24_UNORM_S8_UINT:
4486 case VK_FORMAT_X8_D24_UNORM_PACK32:
4487 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4488 ds->offset_scale = 2.0f;
4489 break;
4490 case VK_FORMAT_D16_UNORM:
4491 case VK_FORMAT_D16_UNORM_S8_UINT:
4492 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4493 ds->offset_scale = 4.0f;
4494 break;
4495 case VK_FORMAT_D32_SFLOAT:
4496 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4497 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4498 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4499 ds->offset_scale = 1.0f;
4500 break;
4501 case VK_FORMAT_S8_UINT:
4502 stencil_only = true;
4503 break;
4504 default:
4505 break;
4506 }
4507
4508 format = radv_translate_dbformat(iview->image->vk_format);
4509 stencil_format = surf->has_stencil ?
4510 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4511
4512 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4513 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4514 S_028008_SLICE_MAX(max_slice);
4515
4516 ds->db_htile_data_base = 0;
4517 ds->db_htile_surface = 0;
4518
4519 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4520 s_offs = z_offs = va;
4521
4522 if (device->physical_device->rad_info.chip_class >= GFX9) {
4523 assert(surf->u.gfx9.surf_offset == 0);
4524 s_offs += surf->u.gfx9.stencil_offset;
4525
4526 ds->db_z_info = S_028038_FORMAT(format) |
4527 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4528 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4529 S_028038_MAXMIP(iview->image->info.levels - 1) |
4530 S_028038_ZRANGE_PRECISION(1);
4531 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4532 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4533
4534 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4535 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4536 ds->db_depth_view |= S_028008_MIPID(level);
4537
4538 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4539 S_02801C_Y_MAX(iview->image->info.height - 1);
4540
4541 if (radv_htile_enabled(iview->image, level)) {
4542 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4543
4544 if (radv_image_is_tc_compat_htile(iview->image)) {
4545 unsigned max_zplanes =
4546 radv_calc_decompress_on_z_planes(device, iview);
4547
4548 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4549 S_028038_ITERATE_FLUSH(1);
4550 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4551 }
4552
4553 if (!surf->has_stencil)
4554 /* Use all of the htile_buffer for depth if there's no stencil. */
4555 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4556 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4557 iview->image->htile_offset;
4558 ds->db_htile_data_base = va >> 8;
4559 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4560 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4561 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4562 }
4563 } else {
4564 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4565
4566 if (stencil_only)
4567 level_info = &surf->u.legacy.stencil_level[level];
4568
4569 z_offs += surf->u.legacy.level[level].offset;
4570 s_offs += surf->u.legacy.stencil_level[level].offset;
4571
4572 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4573 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4574 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4575
4576 if (iview->image->info.samples > 1)
4577 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4578
4579 if (device->physical_device->rad_info.chip_class >= GFX7) {
4580 struct radeon_info *info = &device->physical_device->rad_info;
4581 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4582 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4583 unsigned macro_index = surf->u.legacy.macro_tile_index;
4584 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4585 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4586 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4587
4588 if (stencil_only)
4589 tile_mode = stencil_tile_mode;
4590
4591 ds->db_depth_info |=
4592 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4593 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4594 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4595 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4596 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4597 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4598 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4599 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4600 } else {
4601 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4602 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4603 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4604 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4605 if (stencil_only)
4606 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4607 }
4608
4609 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4610 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4611 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4612
4613 if (radv_htile_enabled(iview->image, level)) {
4614 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4615
4616 if (!surf->has_stencil &&
4617 !radv_image_is_tc_compat_htile(iview->image))
4618 /* Use all of the htile_buffer for depth if there's no stencil. */
4619 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4620
4621 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4622 iview->image->htile_offset;
4623 ds->db_htile_data_base = va >> 8;
4624 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4625
4626 if (radv_image_is_tc_compat_htile(iview->image)) {
4627 unsigned max_zplanes =
4628 radv_calc_decompress_on_z_planes(device, iview);
4629
4630 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4631 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4632 }
4633 }
4634 }
4635
4636 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4637 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4638 }
4639
4640 VkResult radv_CreateFramebuffer(
4641 VkDevice _device,
4642 const VkFramebufferCreateInfo* pCreateInfo,
4643 const VkAllocationCallbacks* pAllocator,
4644 VkFramebuffer* pFramebuffer)
4645 {
4646 RADV_FROM_HANDLE(radv_device, device, _device);
4647 struct radv_framebuffer *framebuffer;
4648
4649 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4650
4651 size_t size = sizeof(*framebuffer) +
4652 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4653 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4654 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4655 if (framebuffer == NULL)
4656 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4657
4658 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4659 framebuffer->width = pCreateInfo->width;
4660 framebuffer->height = pCreateInfo->height;
4661 framebuffer->layers = pCreateInfo->layers;
4662 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4663 VkImageView _iview = pCreateInfo->pAttachments[i];
4664 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4665 framebuffer->attachments[i].attachment = iview;
4666 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4667 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4668 } else {
4669 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4670 }
4671 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4672 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4673 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4674 }
4675
4676 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4677 return VK_SUCCESS;
4678 }
4679
4680 void radv_DestroyFramebuffer(
4681 VkDevice _device,
4682 VkFramebuffer _fb,
4683 const VkAllocationCallbacks* pAllocator)
4684 {
4685 RADV_FROM_HANDLE(radv_device, device, _device);
4686 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4687
4688 if (!fb)
4689 return;
4690 vk_free2(&device->alloc, pAllocator, fb);
4691 }
4692
4693 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4694 {
4695 switch (address_mode) {
4696 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4697 return V_008F30_SQ_TEX_WRAP;
4698 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4699 return V_008F30_SQ_TEX_MIRROR;
4700 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4701 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4702 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4703 return V_008F30_SQ_TEX_CLAMP_BORDER;
4704 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4705 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4706 default:
4707 unreachable("illegal tex wrap mode");
4708 break;
4709 }
4710 }
4711
4712 static unsigned
4713 radv_tex_compare(VkCompareOp op)
4714 {
4715 switch (op) {
4716 case VK_COMPARE_OP_NEVER:
4717 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4718 case VK_COMPARE_OP_LESS:
4719 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4720 case VK_COMPARE_OP_EQUAL:
4721 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4722 case VK_COMPARE_OP_LESS_OR_EQUAL:
4723 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4724 case VK_COMPARE_OP_GREATER:
4725 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4726 case VK_COMPARE_OP_NOT_EQUAL:
4727 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4728 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4729 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4730 case VK_COMPARE_OP_ALWAYS:
4731 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4732 default:
4733 unreachable("illegal compare mode");
4734 break;
4735 }
4736 }
4737
4738 static unsigned
4739 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4740 {
4741 switch (filter) {
4742 case VK_FILTER_NEAREST:
4743 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4744 V_008F38_SQ_TEX_XY_FILTER_POINT);
4745 case VK_FILTER_LINEAR:
4746 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4747 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4748 case VK_FILTER_CUBIC_IMG:
4749 default:
4750 fprintf(stderr, "illegal texture filter");
4751 return 0;
4752 }
4753 }
4754
4755 static unsigned
4756 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4757 {
4758 switch (mode) {
4759 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4760 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4761 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4762 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4763 default:
4764 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4765 }
4766 }
4767
4768 static unsigned
4769 radv_tex_bordercolor(VkBorderColor bcolor)
4770 {
4771 switch (bcolor) {
4772 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4773 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4774 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4775 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4776 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4777 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4778 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4779 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4780 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4781 default:
4782 break;
4783 }
4784 return 0;
4785 }
4786
4787 static unsigned
4788 radv_tex_aniso_filter(unsigned filter)
4789 {
4790 if (filter < 2)
4791 return 0;
4792 if (filter < 4)
4793 return 1;
4794 if (filter < 8)
4795 return 2;
4796 if (filter < 16)
4797 return 3;
4798 return 4;
4799 }
4800
4801 static unsigned
4802 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4803 {
4804 switch (mode) {
4805 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4806 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4807 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4808 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4809 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4810 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4811 default:
4812 break;
4813 }
4814 return 0;
4815 }
4816
4817 static uint32_t
4818 radv_get_max_anisotropy(struct radv_device *device,
4819 const VkSamplerCreateInfo *pCreateInfo)
4820 {
4821 if (device->force_aniso >= 0)
4822 return device->force_aniso;
4823
4824 if (pCreateInfo->anisotropyEnable &&
4825 pCreateInfo->maxAnisotropy > 1.0f)
4826 return (uint32_t)pCreateInfo->maxAnisotropy;
4827
4828 return 0;
4829 }
4830
4831 static void
4832 radv_init_sampler(struct radv_device *device,
4833 struct radv_sampler *sampler,
4834 const VkSamplerCreateInfo *pCreateInfo)
4835 {
4836 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4837 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4838 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4839 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4840
4841 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4842 vk_find_struct_const(pCreateInfo->pNext,
4843 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4844 if (sampler_reduction)
4845 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4846
4847 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4848 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4849 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4850 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4851 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4852 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4853 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4854 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4855 S_008F30_DISABLE_CUBE_WRAP(0) |
4856 S_008F30_COMPAT_MODE(is_vi) |
4857 S_008F30_FILTER_MODE(filter_mode));
4858 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4859 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4860 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4861 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4862 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4863 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4864 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4865 S_008F38_MIP_POINT_PRECLAMP(0) |
4866 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4867 S_008F38_FILTER_PREC_FIX(1) |
4868 S_008F38_ANISO_OVERRIDE(is_vi));
4869 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4870 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4871 }
4872
4873 VkResult radv_CreateSampler(
4874 VkDevice _device,
4875 const VkSamplerCreateInfo* pCreateInfo,
4876 const VkAllocationCallbacks* pAllocator,
4877 VkSampler* pSampler)
4878 {
4879 RADV_FROM_HANDLE(radv_device, device, _device);
4880 struct radv_sampler *sampler;
4881
4882 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4883 vk_find_struct_const(pCreateInfo->pNext,
4884 SAMPLER_YCBCR_CONVERSION_INFO);
4885
4886 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4887
4888 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4889 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4890 if (!sampler)
4891 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4892
4893 radv_init_sampler(device, sampler, pCreateInfo);
4894
4895 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4896 *pSampler = radv_sampler_to_handle(sampler);
4897
4898 return VK_SUCCESS;
4899 }
4900
4901 void radv_DestroySampler(
4902 VkDevice _device,
4903 VkSampler _sampler,
4904 const VkAllocationCallbacks* pAllocator)
4905 {
4906 RADV_FROM_HANDLE(radv_device, device, _device);
4907 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4908
4909 if (!sampler)
4910 return;
4911 vk_free2(&device->alloc, pAllocator, sampler);
4912 }
4913
4914 /* vk_icd.h does not declare this function, so we declare it here to
4915 * suppress Wmissing-prototypes.
4916 */
4917 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4918 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4919
4920 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4921 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4922 {
4923 /* For the full details on loader interface versioning, see
4924 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4925 * What follows is a condensed summary, to help you navigate the large and
4926 * confusing official doc.
4927 *
4928 * - Loader interface v0 is incompatible with later versions. We don't
4929 * support it.
4930 *
4931 * - In loader interface v1:
4932 * - The first ICD entrypoint called by the loader is
4933 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4934 * entrypoint.
4935 * - The ICD must statically expose no other Vulkan symbol unless it is
4936 * linked with -Bsymbolic.
4937 * - Each dispatchable Vulkan handle created by the ICD must be
4938 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4939 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4940 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4941 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4942 * such loader-managed surfaces.
4943 *
4944 * - Loader interface v2 differs from v1 in:
4945 * - The first ICD entrypoint called by the loader is
4946 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4947 * statically expose this entrypoint.
4948 *
4949 * - Loader interface v3 differs from v2 in:
4950 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4951 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4952 * because the loader no longer does so.
4953 */
4954 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4955 return VK_SUCCESS;
4956 }
4957
4958 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4959 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4960 int *pFD)
4961 {
4962 RADV_FROM_HANDLE(radv_device, device, _device);
4963 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4964
4965 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4966
4967 /* At the moment, we support only the below handle types. */
4968 assert(pGetFdInfo->handleType ==
4969 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4970 pGetFdInfo->handleType ==
4971 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4972
4973 bool ret = radv_get_memory_fd(device, memory, pFD);
4974 if (ret == false)
4975 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4976 return VK_SUCCESS;
4977 }
4978
4979 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4980 VkExternalMemoryHandleTypeFlagBits handleType,
4981 int fd,
4982 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4983 {
4984 RADV_FROM_HANDLE(radv_device, device, _device);
4985
4986 switch (handleType) {
4987 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4988 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4989 return VK_SUCCESS;
4990
4991 default:
4992 /* The valid usage section for this function says:
4993 *
4994 * "handleType must not be one of the handle types defined as
4995 * opaque."
4996 *
4997 * So opaque handle types fall into the default "unsupported" case.
4998 */
4999 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5000 }
5001 }
5002
5003 static VkResult radv_import_opaque_fd(struct radv_device *device,
5004 int fd,
5005 uint32_t *syncobj)
5006 {
5007 uint32_t syncobj_handle = 0;
5008 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5009 if (ret != 0)
5010 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5011
5012 if (*syncobj)
5013 device->ws->destroy_syncobj(device->ws, *syncobj);
5014
5015 *syncobj = syncobj_handle;
5016 close(fd);
5017
5018 return VK_SUCCESS;
5019 }
5020
5021 static VkResult radv_import_sync_fd(struct radv_device *device,
5022 int fd,
5023 uint32_t *syncobj)
5024 {
5025 /* If we create a syncobj we do it locally so that if we have an error, we don't
5026 * leave a syncobj in an undetermined state in the fence. */
5027 uint32_t syncobj_handle = *syncobj;
5028 if (!syncobj_handle) {
5029 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5030 if (ret) {
5031 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5032 }
5033 }
5034
5035 if (fd == -1) {
5036 device->ws->signal_syncobj(device->ws, syncobj_handle);
5037 } else {
5038 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5039 if (ret != 0)
5040 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5041 }
5042
5043 *syncobj = syncobj_handle;
5044 if (fd != -1)
5045 close(fd);
5046
5047 return VK_SUCCESS;
5048 }
5049
5050 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5051 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5052 {
5053 RADV_FROM_HANDLE(radv_device, device, _device);
5054 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5055 uint32_t *syncobj_dst = NULL;
5056
5057 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5058 syncobj_dst = &sem->temp_syncobj;
5059 } else {
5060 syncobj_dst = &sem->syncobj;
5061 }
5062
5063 switch(pImportSemaphoreFdInfo->handleType) {
5064 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5065 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5066 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5067 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5068 default:
5069 unreachable("Unhandled semaphore handle type");
5070 }
5071 }
5072
5073 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5074 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5075 int *pFd)
5076 {
5077 RADV_FROM_HANDLE(radv_device, device, _device);
5078 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5079 int ret;
5080 uint32_t syncobj_handle;
5081
5082 if (sem->temp_syncobj)
5083 syncobj_handle = sem->temp_syncobj;
5084 else
5085 syncobj_handle = sem->syncobj;
5086
5087 switch(pGetFdInfo->handleType) {
5088 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5089 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5090 break;
5091 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5092 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5093 if (!ret) {
5094 if (sem->temp_syncobj) {
5095 close (sem->temp_syncobj);
5096 sem->temp_syncobj = 0;
5097 } else {
5098 device->ws->reset_syncobj(device->ws, syncobj_handle);
5099 }
5100 }
5101 break;
5102 default:
5103 unreachable("Unhandled semaphore handle type");
5104 }
5105
5106 if (ret)
5107 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5108 return VK_SUCCESS;
5109 }
5110
5111 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5112 VkPhysicalDevice physicalDevice,
5113 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5114 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5115 {
5116 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5117
5118 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5119 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5120 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5121 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5122 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5123 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5124 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5125 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5126 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5127 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5128 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5129 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5130 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5131 } else {
5132 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5133 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5134 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5135 }
5136 }
5137
5138 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5139 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5140 {
5141 RADV_FROM_HANDLE(radv_device, device, _device);
5142 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5143 uint32_t *syncobj_dst = NULL;
5144
5145
5146 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5147 syncobj_dst = &fence->temp_syncobj;
5148 } else {
5149 syncobj_dst = &fence->syncobj;
5150 }
5151
5152 switch(pImportFenceFdInfo->handleType) {
5153 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5154 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5155 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5156 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5157 default:
5158 unreachable("Unhandled fence handle type");
5159 }
5160 }
5161
5162 VkResult radv_GetFenceFdKHR(VkDevice _device,
5163 const VkFenceGetFdInfoKHR *pGetFdInfo,
5164 int *pFd)
5165 {
5166 RADV_FROM_HANDLE(radv_device, device, _device);
5167 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5168 int ret;
5169 uint32_t syncobj_handle;
5170
5171 if (fence->temp_syncobj)
5172 syncobj_handle = fence->temp_syncobj;
5173 else
5174 syncobj_handle = fence->syncobj;
5175
5176 switch(pGetFdInfo->handleType) {
5177 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5178 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5179 break;
5180 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5181 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5182 if (!ret) {
5183 if (fence->temp_syncobj) {
5184 close (fence->temp_syncobj);
5185 fence->temp_syncobj = 0;
5186 } else {
5187 device->ws->reset_syncobj(device->ws, syncobj_handle);
5188 }
5189 }
5190 break;
5191 default:
5192 unreachable("Unhandled fence handle type");
5193 }
5194
5195 if (ret)
5196 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5197 return VK_SUCCESS;
5198 }
5199
5200 void radv_GetPhysicalDeviceExternalFenceProperties(
5201 VkPhysicalDevice physicalDevice,
5202 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5203 VkExternalFenceProperties *pExternalFenceProperties)
5204 {
5205 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5206
5207 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5208 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5209 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5210 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5211 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5212 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5213 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5214 } else {
5215 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5216 pExternalFenceProperties->compatibleHandleTypes = 0;
5217 pExternalFenceProperties->externalFenceFeatures = 0;
5218 }
5219 }
5220
5221 VkResult
5222 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5223 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5224 const VkAllocationCallbacks* pAllocator,
5225 VkDebugReportCallbackEXT* pCallback)
5226 {
5227 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5228 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5229 pCreateInfo, pAllocator, &instance->alloc,
5230 pCallback);
5231 }
5232
5233 void
5234 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5235 VkDebugReportCallbackEXT _callback,
5236 const VkAllocationCallbacks* pAllocator)
5237 {
5238 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5239 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5240 _callback, pAllocator, &instance->alloc);
5241 }
5242
5243 void
5244 radv_DebugReportMessageEXT(VkInstance _instance,
5245 VkDebugReportFlagsEXT flags,
5246 VkDebugReportObjectTypeEXT objectType,
5247 uint64_t object,
5248 size_t location,
5249 int32_t messageCode,
5250 const char* pLayerPrefix,
5251 const char* pMessage)
5252 {
5253 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5254 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5255 object, location, messageCode, pLayerPrefix, pMessage);
5256 }
5257
5258 void
5259 radv_GetDeviceGroupPeerMemoryFeatures(
5260 VkDevice device,
5261 uint32_t heapIndex,
5262 uint32_t localDeviceIndex,
5263 uint32_t remoteDeviceIndex,
5264 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5265 {
5266 assert(localDeviceIndex == remoteDeviceIndex);
5267
5268 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5269 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5270 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5271 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5272 }
5273
5274 static const VkTimeDomainEXT radv_time_domains[] = {
5275 VK_TIME_DOMAIN_DEVICE_EXT,
5276 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5277 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5278 };
5279
5280 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5281 VkPhysicalDevice physicalDevice,
5282 uint32_t *pTimeDomainCount,
5283 VkTimeDomainEXT *pTimeDomains)
5284 {
5285 int d;
5286 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5287
5288 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5289 vk_outarray_append(&out, i) {
5290 *i = radv_time_domains[d];
5291 }
5292 }
5293
5294 return vk_outarray_status(&out);
5295 }
5296
5297 static uint64_t
5298 radv_clock_gettime(clockid_t clock_id)
5299 {
5300 struct timespec current;
5301 int ret;
5302
5303 ret = clock_gettime(clock_id, &current);
5304 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5305 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5306 if (ret < 0)
5307 return 0;
5308
5309 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5310 }
5311
5312 VkResult radv_GetCalibratedTimestampsEXT(
5313 VkDevice _device,
5314 uint32_t timestampCount,
5315 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5316 uint64_t *pTimestamps,
5317 uint64_t *pMaxDeviation)
5318 {
5319 RADV_FROM_HANDLE(radv_device, device, _device);
5320 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5321 int d;
5322 uint64_t begin, end;
5323 uint64_t max_clock_period = 0;
5324
5325 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5326
5327 for (d = 0; d < timestampCount; d++) {
5328 switch (pTimestampInfos[d].timeDomain) {
5329 case VK_TIME_DOMAIN_DEVICE_EXT:
5330 pTimestamps[d] = device->ws->query_value(device->ws,
5331 RADEON_TIMESTAMP);
5332 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5333 max_clock_period = MAX2(max_clock_period, device_period);
5334 break;
5335 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5336 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5337 max_clock_period = MAX2(max_clock_period, 1);
5338 break;
5339
5340 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5341 pTimestamps[d] = begin;
5342 break;
5343 default:
5344 pTimestamps[d] = 0;
5345 break;
5346 }
5347 }
5348
5349 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5350
5351 /*
5352 * The maximum deviation is the sum of the interval over which we
5353 * perform the sampling and the maximum period of any sampled
5354 * clock. That's because the maximum skew between any two sampled
5355 * clock edges is when the sampled clock with the largest period is
5356 * sampled at the end of that period but right at the beginning of the
5357 * sampling interval and some other clock is sampled right at the
5358 * begining of its sampling period and right at the end of the
5359 * sampling interval. Let's assume the GPU has the longest clock
5360 * period and that the application is sampling GPU and monotonic:
5361 *
5362 * s e
5363 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5364 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5365 *
5366 * g
5367 * 0 1 2 3
5368 * GPU -----_____-----_____-----_____-----_____
5369 *
5370 * m
5371 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5372 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5373 *
5374 * Interval <----------------->
5375 * Deviation <-------------------------->
5376 *
5377 * s = read(raw) 2
5378 * g = read(GPU) 1
5379 * m = read(monotonic) 2
5380 * e = read(raw) b
5381 *
5382 * We round the sample interval up by one tick to cover sampling error
5383 * in the interval clock
5384 */
5385
5386 uint64_t sample_interval = end - begin + 1;
5387
5388 *pMaxDeviation = sample_interval + max_clock_period;
5389
5390 return VK_SUCCESS;
5391 }
5392
5393 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5394 VkPhysicalDevice physicalDevice,
5395 VkSampleCountFlagBits samples,
5396 VkMultisamplePropertiesEXT* pMultisampleProperties)
5397 {
5398 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5399 VK_SAMPLE_COUNT_4_BIT |
5400 VK_SAMPLE_COUNT_8_BIT)) {
5401 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5402 } else {
5403 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5404 }
5405 }