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radv: Enable VK_KHR_shader_atomic_int64
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 /* Determine the number of threads per wave for all stages. */
387 device->cs_wave_size = 64;
388 device->ps_wave_size = 64;
389 device->ge_wave_size = 64;
390
391 if (device->rad_info.chip_class >= GFX10) {
392 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
393 device->cs_wave_size = 32;
394
395 /* For pixel shaders, wave64 is recommanded. */
396 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
397 device->ps_wave_size = 32;
398
399 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
400 device->ge_wave_size = 32;
401 }
402
403 radv_physical_device_init_mem_types(device);
404 radv_fill_device_extension_table(device, &device->supported_extensions);
405
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 device->ws->destroy(device->ws);
418 vk_error(instance, result);
419 goto fail;
420 }
421
422 return VK_SUCCESS;
423
424 fail:
425 close(fd);
426 if (master_fd != -1)
427 close(master_fd);
428 return result;
429 }
430
431 static void
432 radv_physical_device_finish(struct radv_physical_device *device)
433 {
434 radv_finish_wsi(device);
435 device->ws->destroy(device->ws);
436 disk_cache_destroy(device->disk_cache);
437 close(device->local_fd);
438 if (device->master_fd != -1)
439 close(device->master_fd);
440 }
441
442 static void *
443 default_alloc_func(void *pUserData, size_t size, size_t align,
444 VkSystemAllocationScope allocationScope)
445 {
446 return malloc(size);
447 }
448
449 static void *
450 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
451 size_t align, VkSystemAllocationScope allocationScope)
452 {
453 return realloc(pOriginal, size);
454 }
455
456 static void
457 default_free_func(void *pUserData, void *pMemory)
458 {
459 free(pMemory);
460 }
461
462 static const VkAllocationCallbacks default_alloc = {
463 .pUserData = NULL,
464 .pfnAllocation = default_alloc_func,
465 .pfnReallocation = default_realloc_func,
466 .pfnFree = default_free_func,
467 };
468
469 static const struct debug_control radv_debug_options[] = {
470 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
471 {"nodcc", RADV_DEBUG_NO_DCC},
472 {"shaders", RADV_DEBUG_DUMP_SHADERS},
473 {"nocache", RADV_DEBUG_NO_CACHE},
474 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
475 {"nohiz", RADV_DEBUG_NO_HIZ},
476 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
477 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
478 {"allbos", RADV_DEBUG_ALL_BOS},
479 {"noibs", RADV_DEBUG_NO_IBS},
480 {"spirv", RADV_DEBUG_DUMP_SPIRV},
481 {"vmfaults", RADV_DEBUG_VM_FAULTS},
482 {"zerovram", RADV_DEBUG_ZERO_VRAM},
483 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
484 {"nosisched", RADV_DEBUG_NO_SISCHED},
485 {"preoptir", RADV_DEBUG_PREOPTIR},
486 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
487 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
488 {"info", RADV_DEBUG_INFO},
489 {"errors", RADV_DEBUG_ERRORS},
490 {"startup", RADV_DEBUG_STARTUP},
491 {"checkir", RADV_DEBUG_CHECKIR},
492 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
493 {"nobinning", RADV_DEBUG_NOBINNING},
494 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
495 {"nongg", RADV_DEBUG_NO_NGG},
496 {NULL, 0}
497 };
498
499 const char *
500 radv_get_debug_option_name(int id)
501 {
502 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
503 return radv_debug_options[id].string;
504 }
505
506 static const struct debug_control radv_perftest_options[] = {
507 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
508 {"sisched", RADV_PERFTEST_SISCHED},
509 {"localbos", RADV_PERFTEST_LOCAL_BOS},
510 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
511 {"bolist", RADV_PERFTEST_BO_LIST},
512 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
513 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
514 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
515 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
516 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_perftest_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
524 return radv_perftest_options[id].string;
525 }
526
527 static void
528 radv_handle_per_app_options(struct radv_instance *instance,
529 const VkApplicationInfo *info)
530 {
531 const char *name = info ? info->pApplicationName : NULL;
532
533 if (!name)
534 return;
535
536 if (!strcmp(name, "Talos - Linux - 32bit") ||
537 !strcmp(name, "Talos - Linux - 64bit")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
539 /* Force enable LLVM sisched for Talos because it looks
540 * safe and it gives few more FPS.
541 */
542 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
543 }
544 } else if (!strcmp(name, "DOOM_VFR")) {
545 /* Work around a Doom VFR game bug */
546 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
547 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
548 /* Workaround for a WaW hazard when LLVM moves/merges
549 * load/store memory operations.
550 * See https://reviews.llvm.org/D61313
551 */
552 if (HAVE_LLVM < 0x900)
553 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
554 }
555 }
556
557 static int radv_get_instance_extension_index(const char *name)
558 {
559 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
560 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
561 return i;
562 }
563 return -1;
564 }
565
566 static const char radv_dri_options_xml[] =
567 DRI_CONF_BEGIN
568 DRI_CONF_SECTION_QUALITY
569 DRI_CONF_ADAPTIVE_SYNC("true")
570 DRI_CONF_SECTION_END
571 DRI_CONF_END;
572
573 static void radv_init_dri_options(struct radv_instance *instance)
574 {
575 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
576 driParseConfigFiles(&instance->dri_options,
577 &instance->available_dri_options,
578 0, "radv", NULL);
579 }
580
581 VkResult radv_CreateInstance(
582 const VkInstanceCreateInfo* pCreateInfo,
583 const VkAllocationCallbacks* pAllocator,
584 VkInstance* pInstance)
585 {
586 struct radv_instance *instance;
587 VkResult result;
588
589 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
590
591 uint32_t client_version;
592 if (pCreateInfo->pApplicationInfo &&
593 pCreateInfo->pApplicationInfo->apiVersion != 0) {
594 client_version = pCreateInfo->pApplicationInfo->apiVersion;
595 } else {
596 client_version = VK_API_VERSION_1_0;
597 }
598
599 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
600 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
601 if (!instance)
602 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
603
604 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
605
606 if (pAllocator)
607 instance->alloc = *pAllocator;
608 else
609 instance->alloc = default_alloc;
610
611 instance->apiVersion = client_version;
612 instance->physicalDeviceCount = -1;
613
614 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
615 radv_debug_options);
616
617 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
618 radv_perftest_options);
619
620
621 if (instance->debug_flags & RADV_DEBUG_STARTUP)
622 radv_logi("Created an instance");
623
624 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
625 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
626 int index = radv_get_instance_extension_index(ext_name);
627
628 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
629 vk_free2(&default_alloc, pAllocator, instance);
630 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
631 }
632
633 instance->enabled_extensions.extensions[index] = true;
634 }
635
636 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
637 if (result != VK_SUCCESS) {
638 vk_free2(&default_alloc, pAllocator, instance);
639 return vk_error(instance, result);
640 }
641
642 _mesa_locale_init();
643 glsl_type_singleton_init_or_ref();
644
645 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
646
647 radv_init_dri_options(instance);
648 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
649
650 *pInstance = radv_instance_to_handle(instance);
651
652 return VK_SUCCESS;
653 }
654
655 void radv_DestroyInstance(
656 VkInstance _instance,
657 const VkAllocationCallbacks* pAllocator)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660
661 if (!instance)
662 return;
663
664 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
665 radv_physical_device_finish(instance->physicalDevices + i);
666 }
667
668 VG(VALGRIND_DESTROY_MEMPOOL(instance));
669
670 glsl_type_singleton_decref();
671 _mesa_locale_fini();
672
673 driDestroyOptionCache(&instance->dri_options);
674 driDestroyOptionInfo(&instance->available_dri_options);
675
676 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
677
678 vk_free(&instance->alloc, instance);
679 }
680
681 static VkResult
682 radv_enumerate_devices(struct radv_instance *instance)
683 {
684 /* TODO: Check for more devices ? */
685 drmDevicePtr devices[8];
686 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
687 int max_devices;
688
689 instance->physicalDeviceCount = 0;
690
691 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
692
693 if (instance->debug_flags & RADV_DEBUG_STARTUP)
694 radv_logi("Found %d drm nodes", max_devices);
695
696 if (max_devices < 1)
697 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
698
699 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
700 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
701 devices[i]->bustype == DRM_BUS_PCI &&
702 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
703
704 result = radv_physical_device_init(instance->physicalDevices +
705 instance->physicalDeviceCount,
706 instance,
707 devices[i]);
708 if (result == VK_SUCCESS)
709 ++instance->physicalDeviceCount;
710 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 break;
712 }
713 }
714 drmFreeDevices(devices, max_devices);
715
716 return result;
717 }
718
719 VkResult radv_EnumeratePhysicalDevices(
720 VkInstance _instance,
721 uint32_t* pPhysicalDeviceCount,
722 VkPhysicalDevice* pPhysicalDevices)
723 {
724 RADV_FROM_HANDLE(radv_instance, instance, _instance);
725 VkResult result;
726
727 if (instance->physicalDeviceCount < 0) {
728 result = radv_enumerate_devices(instance);
729 if (result != VK_SUCCESS &&
730 result != VK_ERROR_INCOMPATIBLE_DRIVER)
731 return result;
732 }
733
734 if (!pPhysicalDevices) {
735 *pPhysicalDeviceCount = instance->physicalDeviceCount;
736 } else {
737 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
738 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
739 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
740 }
741
742 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
743 : VK_SUCCESS;
744 }
745
746 VkResult radv_EnumeratePhysicalDeviceGroups(
747 VkInstance _instance,
748 uint32_t* pPhysicalDeviceGroupCount,
749 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
750 {
751 RADV_FROM_HANDLE(radv_instance, instance, _instance);
752 VkResult result;
753
754 if (instance->physicalDeviceCount < 0) {
755 result = radv_enumerate_devices(instance);
756 if (result != VK_SUCCESS &&
757 result != VK_ERROR_INCOMPATIBLE_DRIVER)
758 return result;
759 }
760
761 if (!pPhysicalDeviceGroupProperties) {
762 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
763 } else {
764 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
765 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
766 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
767 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
768 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
769 }
770 }
771 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
772 : VK_SUCCESS;
773 }
774
775 void radv_GetPhysicalDeviceFeatures(
776 VkPhysicalDevice physicalDevice,
777 VkPhysicalDeviceFeatures* pFeatures)
778 {
779 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
780 memset(pFeatures, 0, sizeof(*pFeatures));
781
782 *pFeatures = (VkPhysicalDeviceFeatures) {
783 .robustBufferAccess = true,
784 .fullDrawIndexUint32 = true,
785 .imageCubeArray = true,
786 .independentBlend = true,
787 .geometryShader = true,
788 .tessellationShader = true,
789 .sampleRateShading = true,
790 .dualSrcBlend = true,
791 .logicOp = true,
792 .multiDrawIndirect = true,
793 .drawIndirectFirstInstance = true,
794 .depthClamp = true,
795 .depthBiasClamp = true,
796 .fillModeNonSolid = true,
797 .depthBounds = true,
798 .wideLines = true,
799 .largePoints = true,
800 .alphaToOne = true,
801 .multiViewport = true,
802 .samplerAnisotropy = true,
803 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
804 .textureCompressionASTC_LDR = false,
805 .textureCompressionBC = true,
806 .occlusionQueryPrecise = true,
807 .pipelineStatisticsQuery = true,
808 .vertexPipelineStoresAndAtomics = true,
809 .fragmentStoresAndAtomics = true,
810 .shaderTessellationAndGeometryPointSize = true,
811 .shaderImageGatherExtended = true,
812 .shaderStorageImageExtendedFormats = true,
813 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
814 .shaderUniformBufferArrayDynamicIndexing = true,
815 .shaderSampledImageArrayDynamicIndexing = true,
816 .shaderStorageBufferArrayDynamicIndexing = true,
817 .shaderStorageImageArrayDynamicIndexing = true,
818 .shaderStorageImageReadWithoutFormat = true,
819 .shaderStorageImageWriteWithoutFormat = true,
820 .shaderClipDistance = true,
821 .shaderCullDistance = true,
822 .shaderFloat64 = true,
823 .shaderInt64 = true,
824 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
825 .sparseBinding = true,
826 .variableMultisampleRate = true,
827 .inheritedQueries = true,
828 };
829 }
830
831 void radv_GetPhysicalDeviceFeatures2(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceFeatures2 *pFeatures)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 vk_foreach_struct(ext, pFeatures->pNext) {
837 switch (ext->sType) {
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
839 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
840 features->variablePointersStorageBuffer = true;
841 features->variablePointers = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
845 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
846 features->multiview = true;
847 features->multiviewGeometryShader = true;
848 features->multiviewTessellationShader = true;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
852 VkPhysicalDeviceShaderDrawParametersFeatures *features =
853 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
854 features->shaderDrawParameters = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
858 VkPhysicalDeviceProtectedMemoryFeatures *features =
859 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
860 features->protectedMemory = false;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
864 VkPhysicalDevice16BitStorageFeatures *features =
865 (VkPhysicalDevice16BitStorageFeatures*)ext;
866 bool enabled = pdevice->rad_info.chip_class >= GFX8;
867 features->storageBuffer16BitAccess = enabled;
868 features->uniformAndStorageBuffer16BitAccess = enabled;
869 features->storagePushConstant16 = enabled;
870 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
874 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
875 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
876 features->samplerYcbcrConversion = true;
877 break;
878 }
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
880 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
881 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
882 features->shaderInputAttachmentArrayDynamicIndexing = true;
883 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
884 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
885 features->shaderUniformBufferArrayNonUniformIndexing = true;
886 features->shaderSampledImageArrayNonUniformIndexing = true;
887 features->shaderStorageBufferArrayNonUniformIndexing = true;
888 features->shaderStorageImageArrayNonUniformIndexing = true;
889 features->shaderInputAttachmentArrayNonUniformIndexing = true;
890 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
891 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
892 features->descriptorBindingUniformBufferUpdateAfterBind = true;
893 features->descriptorBindingSampledImageUpdateAfterBind = true;
894 features->descriptorBindingStorageImageUpdateAfterBind = true;
895 features->descriptorBindingStorageBufferUpdateAfterBind = true;
896 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
897 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
898 features->descriptorBindingUpdateUnusedWhilePending = true;
899 features->descriptorBindingPartiallyBound = true;
900 features->descriptorBindingVariableDescriptorCount = true;
901 features->runtimeDescriptorArray = true;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
905 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
906 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
907 features->conditionalRendering = true;
908 features->inheritedConditionalRendering = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
912 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
913 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
914 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
915 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
919 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
920 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
921 features->transformFeedback = true;
922 features->geometryStreams = true;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
926 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
927 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
928 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
932 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
933 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
934 features->memoryPriority = VK_TRUE;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
938 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
939 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
940 features->bufferDeviceAddress = true;
941 features->bufferDeviceAddressCaptureReplay = false;
942 features->bufferDeviceAddressMultiDevice = false;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
946 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
947 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
948 features->depthClipEnable = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
952 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
953 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
954 features->hostQueryReset = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
958 VkPhysicalDevice8BitStorageFeaturesKHR *features =
959 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
960 bool enabled = pdevice->rad_info.chip_class >= GFX8;
961 features->storageBuffer8BitAccess = enabled;
962 features->uniformAndStorageBuffer8BitAccess = enabled;
963 features->storagePushConstant8 = enabled;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
967 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
968 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
969 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
970 features->shaderInt8 = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
974 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
975 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
976 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
977 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
981 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
982 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
983
984 features->inlineUniformBlock = true;
985 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
989 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
990 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
991 features->computeDerivativeGroupQuads = false;
992 features->computeDerivativeGroupLinear = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
996 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
997 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
998 features->ycbcrImageArrays = true;
999 break;
1000 }
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1002 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1003 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1004 features->uniformBufferStandardLayout = true;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1008 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1009 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1010 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1011 break;
1012 }
1013 default:
1014 break;
1015 }
1016 }
1017 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1018 }
1019
1020 void radv_GetPhysicalDeviceProperties(
1021 VkPhysicalDevice physicalDevice,
1022 VkPhysicalDeviceProperties* pProperties)
1023 {
1024 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1025 VkSampleCountFlags sample_counts = 0xf;
1026
1027 /* make sure that the entire descriptor set is addressable with a signed
1028 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1029 * be at most 2 GiB. the combined image & samples object count as one of
1030 * both. This limit is for the pipeline layout, not for the set layout, but
1031 * there is no set limit, so we just set a pipeline limit. I don't think
1032 * any app is going to hit this soon. */
1033 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1034 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1035 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1036 32 /* sampler, largest when combined with image */ +
1037 64 /* sampled image */ +
1038 64 /* storage image */);
1039
1040 VkPhysicalDeviceLimits limits = {
1041 .maxImageDimension1D = (1 << 14),
1042 .maxImageDimension2D = (1 << 14),
1043 .maxImageDimension3D = (1 << 11),
1044 .maxImageDimensionCube = (1 << 14),
1045 .maxImageArrayLayers = (1 << 11),
1046 .maxTexelBufferElements = 128 * 1024 * 1024,
1047 .maxUniformBufferRange = UINT32_MAX,
1048 .maxStorageBufferRange = UINT32_MAX,
1049 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1050 .maxMemoryAllocationCount = UINT32_MAX,
1051 .maxSamplerAllocationCount = 64 * 1024,
1052 .bufferImageGranularity = 64, /* A cache line */
1053 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1054 .maxBoundDescriptorSets = MAX_SETS,
1055 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1056 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1057 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1058 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1059 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1060 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1061 .maxPerStageResources = max_descriptor_set_size,
1062 .maxDescriptorSetSamplers = max_descriptor_set_size,
1063 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1064 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1065 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1066 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1067 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1068 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1069 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1070 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1071 .maxVertexInputBindings = MAX_VBS,
1072 .maxVertexInputAttributeOffset = 2047,
1073 .maxVertexInputBindingStride = 2048,
1074 .maxVertexOutputComponents = 128,
1075 .maxTessellationGenerationLevel = 64,
1076 .maxTessellationPatchSize = 32,
1077 .maxTessellationControlPerVertexInputComponents = 128,
1078 .maxTessellationControlPerVertexOutputComponents = 128,
1079 .maxTessellationControlPerPatchOutputComponents = 120,
1080 .maxTessellationControlTotalOutputComponents = 4096,
1081 .maxTessellationEvaluationInputComponents = 128,
1082 .maxTessellationEvaluationOutputComponents = 128,
1083 .maxGeometryShaderInvocations = 127,
1084 .maxGeometryInputComponents = 64,
1085 .maxGeometryOutputComponents = 128,
1086 .maxGeometryOutputVertices = 256,
1087 .maxGeometryTotalOutputComponents = 1024,
1088 .maxFragmentInputComponents = 128,
1089 .maxFragmentOutputAttachments = 8,
1090 .maxFragmentDualSrcAttachments = 1,
1091 .maxFragmentCombinedOutputResources = 8,
1092 .maxComputeSharedMemorySize = 32768,
1093 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1094 .maxComputeWorkGroupInvocations = 2048,
1095 .maxComputeWorkGroupSize = {
1096 2048,
1097 2048,
1098 2048
1099 },
1100 .subPixelPrecisionBits = 8,
1101 .subTexelPrecisionBits = 8,
1102 .mipmapPrecisionBits = 8,
1103 .maxDrawIndexedIndexValue = UINT32_MAX,
1104 .maxDrawIndirectCount = UINT32_MAX,
1105 .maxSamplerLodBias = 16,
1106 .maxSamplerAnisotropy = 16,
1107 .maxViewports = MAX_VIEWPORTS,
1108 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1109 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1110 .viewportSubPixelBits = 8,
1111 .minMemoryMapAlignment = 4096, /* A page */
1112 .minTexelBufferOffsetAlignment = 1,
1113 .minUniformBufferOffsetAlignment = 4,
1114 .minStorageBufferOffsetAlignment = 4,
1115 .minTexelOffset = -32,
1116 .maxTexelOffset = 31,
1117 .minTexelGatherOffset = -32,
1118 .maxTexelGatherOffset = 31,
1119 .minInterpolationOffset = -2,
1120 .maxInterpolationOffset = 2,
1121 .subPixelInterpolationOffsetBits = 8,
1122 .maxFramebufferWidth = (1 << 14),
1123 .maxFramebufferHeight = (1 << 14),
1124 .maxFramebufferLayers = (1 << 10),
1125 .framebufferColorSampleCounts = sample_counts,
1126 .framebufferDepthSampleCounts = sample_counts,
1127 .framebufferStencilSampleCounts = sample_counts,
1128 .framebufferNoAttachmentsSampleCounts = sample_counts,
1129 .maxColorAttachments = MAX_RTS,
1130 .sampledImageColorSampleCounts = sample_counts,
1131 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1132 .sampledImageDepthSampleCounts = sample_counts,
1133 .sampledImageStencilSampleCounts = sample_counts,
1134 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1135 .maxSampleMaskWords = 1,
1136 .timestampComputeAndGraphics = true,
1137 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1138 .maxClipDistances = 8,
1139 .maxCullDistances = 8,
1140 .maxCombinedClipAndCullDistances = 8,
1141 .discreteQueuePriorities = 2,
1142 .pointSizeRange = { 0.0, 8192.0 },
1143 .lineWidthRange = { 0.0, 7.9921875 },
1144 .pointSizeGranularity = (1.0 / 8.0),
1145 .lineWidthGranularity = (1.0 / 128.0),
1146 .strictLines = false, /* FINISHME */
1147 .standardSampleLocations = true,
1148 .optimalBufferCopyOffsetAlignment = 128,
1149 .optimalBufferCopyRowPitchAlignment = 128,
1150 .nonCoherentAtomSize = 64,
1151 };
1152
1153 *pProperties = (VkPhysicalDeviceProperties) {
1154 .apiVersion = radv_physical_device_api_version(pdevice),
1155 .driverVersion = vk_get_driver_version(),
1156 .vendorID = ATI_VENDOR_ID,
1157 .deviceID = pdevice->rad_info.pci_id,
1158 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1159 .limits = limits,
1160 .sparseProperties = {0},
1161 };
1162
1163 strcpy(pProperties->deviceName, pdevice->name);
1164 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1165 }
1166
1167 void radv_GetPhysicalDeviceProperties2(
1168 VkPhysicalDevice physicalDevice,
1169 VkPhysicalDeviceProperties2 *pProperties)
1170 {
1171 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1172 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1173
1174 vk_foreach_struct(ext, pProperties->pNext) {
1175 switch (ext->sType) {
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1177 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1178 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1179 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1183 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1184 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1185 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1186 properties->deviceLUIDValid = false;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1190 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1191 properties->maxMultiviewViewCount = MAX_VIEWS;
1192 properties->maxMultiviewInstanceIndex = INT_MAX;
1193 break;
1194 }
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1196 VkPhysicalDevicePointClippingProperties *properties =
1197 (VkPhysicalDevicePointClippingProperties*)ext;
1198 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1202 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1203 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1204 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1208 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1209 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1210 properties->minImportedHostPointerAlignment = 4096;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1214 VkPhysicalDeviceSubgroupProperties *properties =
1215 (VkPhysicalDeviceSubgroupProperties*)ext;
1216 properties->subgroupSize = 64;
1217 properties->supportedStages = VK_SHADER_STAGE_ALL;
1218 properties->supportedOperations =
1219 VK_SUBGROUP_FEATURE_BASIC_BIT |
1220 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1221 VK_SUBGROUP_FEATURE_QUAD_BIT |
1222 VK_SUBGROUP_FEATURE_VOTE_BIT;
1223 if (pdevice->rad_info.chip_class >= GFX8) {
1224 properties->supportedOperations |=
1225 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1226 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1227 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1228 }
1229 properties->quadOperationsInAllStages = true;
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1233 VkPhysicalDeviceMaintenance3Properties *properties =
1234 (VkPhysicalDeviceMaintenance3Properties*)ext;
1235 /* Make sure everything is addressable by a signed 32-bit int, and
1236 * our largest descriptors are 96 bytes. */
1237 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1238 /* Our buffer size fields allow only this much */
1239 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1243 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1244 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1245 /* GFX6-8 only support single channel min/max filter. */
1246 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1247 properties->filterMinmaxSingleComponentFormats = true;
1248 break;
1249 }
1250 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1251 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1252 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1253
1254 /* Shader engines. */
1255 properties->shaderEngineCount =
1256 pdevice->rad_info.max_se;
1257 properties->shaderArraysPerEngineCount =
1258 pdevice->rad_info.max_sh_per_se;
1259 properties->computeUnitsPerShaderArray =
1260 pdevice->rad_info.num_good_cu_per_sh;
1261 properties->simdPerComputeUnit = 4;
1262 properties->wavefrontsPerSimd =
1263 pdevice->rad_info.family == CHIP_TONGA ||
1264 pdevice->rad_info.family == CHIP_ICELAND ||
1265 pdevice->rad_info.family == CHIP_POLARIS10 ||
1266 pdevice->rad_info.family == CHIP_POLARIS11 ||
1267 pdevice->rad_info.family == CHIP_POLARIS12 ||
1268 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1269 properties->wavefrontSize = 64;
1270
1271 /* SGPR. */
1272 properties->sgprsPerSimd =
1273 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1274 properties->minSgprAllocation =
1275 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1276 properties->maxSgprAllocation =
1277 pdevice->rad_info.family == CHIP_TONGA ||
1278 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1279 properties->sgprAllocationGranularity =
1280 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1281
1282 /* VGPR. */
1283 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1284 properties->minVgprAllocation = 4;
1285 properties->maxVgprAllocation = 256;
1286 properties->vgprAllocationGranularity = 4;
1287 break;
1288 }
1289 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1290 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1291 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1292 properties->maxVertexAttribDivisor = UINT32_MAX;
1293 break;
1294 }
1295 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1296 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1297 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1298 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1299 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1300 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1301 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1302 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1303 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1304 properties->robustBufferAccessUpdateAfterBind = false;
1305 properties->quadDivergentImplicitLod = false;
1306
1307 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1308 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1309 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1310 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1311 32 /* sampler, largest when combined with image */ +
1312 64 /* sampled image */ +
1313 64 /* storage image */);
1314 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1315 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1316 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1317 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1318 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1319 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1320 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1321 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1322 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1323 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1324 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1325 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1326 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1327 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1328 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1332 VkPhysicalDeviceProtectedMemoryProperties *properties =
1333 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1334 properties->protectedNoFault = false;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1338 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1339 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1340 properties->primitiveOverestimationSize = 0;
1341 properties->maxExtraPrimitiveOverestimationSize = 0;
1342 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1343 properties->primitiveUnderestimation = VK_FALSE;
1344 properties->conservativePointAndLineRasterization = VK_FALSE;
1345 properties->degenerateTrianglesRasterized = VK_FALSE;
1346 properties->degenerateLinesRasterized = VK_FALSE;
1347 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1348 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1349 break;
1350 }
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1352 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1353 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1354 properties->pciDomain = pdevice->bus_info.domain;
1355 properties->pciBus = pdevice->bus_info.bus;
1356 properties->pciDevice = pdevice->bus_info.dev;
1357 properties->pciFunction = pdevice->bus_info.func;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1361 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1362 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1363
1364 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1365 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1366 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1367 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1368 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1369
1370 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1371 .major = 1,
1372 .minor = 1,
1373 .subminor = 2,
1374 .patch = 0,
1375 };
1376 break;
1377 }
1378 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1379 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1380 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1381 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1382 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1383 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1384 properties->maxTransformFeedbackStreamDataSize = 512;
1385 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1386 properties->maxTransformFeedbackBufferDataStride = 512;
1387 properties->transformFeedbackQueries = true;
1388 properties->transformFeedbackStreamsLinesTriangles = true;
1389 properties->transformFeedbackRasterizationStreamSelect = false;
1390 properties->transformFeedbackDraw = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1394 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1395 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1396
1397 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1398 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1399 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1400 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1401 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1402 break;
1403 }
1404 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1405 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1406 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1407 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1408 VK_SAMPLE_COUNT_4_BIT |
1409 VK_SAMPLE_COUNT_8_BIT;
1410 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1411 properties->sampleLocationCoordinateRange[0] = 0.0f;
1412 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1413 properties->sampleLocationSubPixelBits = 4;
1414 properties->variableSampleLocations = VK_FALSE;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1418 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1419 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1420
1421 /* We support all of the depth resolve modes */
1422 properties->supportedDepthResolveModes =
1423 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1424 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1425 VK_RESOLVE_MODE_MIN_BIT_KHR |
1426 VK_RESOLVE_MODE_MAX_BIT_KHR;
1427
1428 /* Average doesn't make sense for stencil so we don't support that */
1429 properties->supportedStencilResolveModes =
1430 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1431 VK_RESOLVE_MODE_MIN_BIT_KHR |
1432 VK_RESOLVE_MODE_MAX_BIT_KHR;
1433
1434 properties->independentResolveNone = VK_TRUE;
1435 properties->independentResolve = VK_TRUE;
1436 break;
1437 }
1438 default:
1439 break;
1440 }
1441 }
1442 }
1443
1444 static void radv_get_physical_device_queue_family_properties(
1445 struct radv_physical_device* pdevice,
1446 uint32_t* pCount,
1447 VkQueueFamilyProperties** pQueueFamilyProperties)
1448 {
1449 int num_queue_families = 1;
1450 int idx;
1451 if (pdevice->rad_info.num_compute_rings > 0 &&
1452 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1453 num_queue_families++;
1454
1455 if (pQueueFamilyProperties == NULL) {
1456 *pCount = num_queue_families;
1457 return;
1458 }
1459
1460 if (!*pCount)
1461 return;
1462
1463 idx = 0;
1464 if (*pCount >= 1) {
1465 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1466 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1467 VK_QUEUE_COMPUTE_BIT |
1468 VK_QUEUE_TRANSFER_BIT |
1469 VK_QUEUE_SPARSE_BINDING_BIT,
1470 .queueCount = 1,
1471 .timestampValidBits = 64,
1472 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1473 };
1474 idx++;
1475 }
1476
1477 if (pdevice->rad_info.num_compute_rings > 0 &&
1478 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1479 if (*pCount > idx) {
1480 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1481 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1482 VK_QUEUE_TRANSFER_BIT |
1483 VK_QUEUE_SPARSE_BINDING_BIT,
1484 .queueCount = pdevice->rad_info.num_compute_rings,
1485 .timestampValidBits = 64,
1486 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1487 };
1488 idx++;
1489 }
1490 }
1491 *pCount = idx;
1492 }
1493
1494 void radv_GetPhysicalDeviceQueueFamilyProperties(
1495 VkPhysicalDevice physicalDevice,
1496 uint32_t* pCount,
1497 VkQueueFamilyProperties* pQueueFamilyProperties)
1498 {
1499 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1500 if (!pQueueFamilyProperties) {
1501 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1502 return;
1503 }
1504 VkQueueFamilyProperties *properties[] = {
1505 pQueueFamilyProperties + 0,
1506 pQueueFamilyProperties + 1,
1507 pQueueFamilyProperties + 2,
1508 };
1509 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1510 assert(*pCount <= 3);
1511 }
1512
1513 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1514 VkPhysicalDevice physicalDevice,
1515 uint32_t* pCount,
1516 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1517 {
1518 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1519 if (!pQueueFamilyProperties) {
1520 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1521 return;
1522 }
1523 VkQueueFamilyProperties *properties[] = {
1524 &pQueueFamilyProperties[0].queueFamilyProperties,
1525 &pQueueFamilyProperties[1].queueFamilyProperties,
1526 &pQueueFamilyProperties[2].queueFamilyProperties,
1527 };
1528 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1529 assert(*pCount <= 3);
1530 }
1531
1532 void radv_GetPhysicalDeviceMemoryProperties(
1533 VkPhysicalDevice physicalDevice,
1534 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1535 {
1536 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1537
1538 *pMemoryProperties = physical_device->memory_properties;
1539 }
1540
1541 static void
1542 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1543 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1544 {
1545 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1546 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1547 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1548 uint64_t vram_size = radv_get_vram_size(device);
1549 uint64_t gtt_size = device->rad_info.gart_size;
1550 uint64_t heap_budget, heap_usage;
1551
1552 /* For all memory heaps, the computation of budget is as follow:
1553 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1554 *
1555 * The Vulkan spec 1.1.97 says that the budget should include any
1556 * currently allocated device memory.
1557 *
1558 * Note that the application heap usages are not really accurate (eg.
1559 * in presence of shared buffers).
1560 */
1561 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1562 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1563
1564 switch (device->mem_type_indices[i]) {
1565 case RADV_MEM_TYPE_VRAM:
1566 heap_usage = device->ws->query_value(device->ws,
1567 RADEON_ALLOCATED_VRAM);
1568
1569 heap_budget = vram_size -
1570 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1571 heap_usage;
1572
1573 memoryBudget->heapBudget[heap_index] = heap_budget;
1574 memoryBudget->heapUsage[heap_index] = heap_usage;
1575 break;
1576 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1577 heap_usage = device->ws->query_value(device->ws,
1578 RADEON_ALLOCATED_VRAM_VIS);
1579
1580 heap_budget = visible_vram_size -
1581 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1582 heap_usage;
1583
1584 memoryBudget->heapBudget[heap_index] = heap_budget;
1585 memoryBudget->heapUsage[heap_index] = heap_usage;
1586 break;
1587 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1588 heap_usage = device->ws->query_value(device->ws,
1589 RADEON_ALLOCATED_GTT);
1590
1591 heap_budget = gtt_size -
1592 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1593 heap_usage;
1594
1595 memoryBudget->heapBudget[heap_index] = heap_budget;
1596 memoryBudget->heapUsage[heap_index] = heap_usage;
1597 break;
1598 default:
1599 break;
1600 }
1601 }
1602
1603 /* The heapBudget and heapUsage values must be zero for array elements
1604 * greater than or equal to
1605 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1606 */
1607 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1608 memoryBudget->heapBudget[i] = 0;
1609 memoryBudget->heapUsage[i] = 0;
1610 }
1611 }
1612
1613 void radv_GetPhysicalDeviceMemoryProperties2(
1614 VkPhysicalDevice physicalDevice,
1615 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1616 {
1617 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1618 &pMemoryProperties->memoryProperties);
1619
1620 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1621 vk_find_struct(pMemoryProperties->pNext,
1622 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1623 if (memory_budget)
1624 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1625 }
1626
1627 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1628 VkDevice _device,
1629 VkExternalMemoryHandleTypeFlagBits handleType,
1630 const void *pHostPointer,
1631 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1632 {
1633 RADV_FROM_HANDLE(radv_device, device, _device);
1634
1635 switch (handleType)
1636 {
1637 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1638 const struct radv_physical_device *physical_device = device->physical_device;
1639 uint32_t memoryTypeBits = 0;
1640 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1641 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1642 memoryTypeBits = (1 << i);
1643 break;
1644 }
1645 }
1646 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1647 return VK_SUCCESS;
1648 }
1649 default:
1650 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1651 }
1652 }
1653
1654 static enum radeon_ctx_priority
1655 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1656 {
1657 /* Default to MEDIUM when a specific global priority isn't requested */
1658 if (!pObj)
1659 return RADEON_CTX_PRIORITY_MEDIUM;
1660
1661 switch(pObj->globalPriority) {
1662 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1663 return RADEON_CTX_PRIORITY_REALTIME;
1664 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1665 return RADEON_CTX_PRIORITY_HIGH;
1666 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1667 return RADEON_CTX_PRIORITY_MEDIUM;
1668 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1669 return RADEON_CTX_PRIORITY_LOW;
1670 default:
1671 unreachable("Illegal global priority value");
1672 return RADEON_CTX_PRIORITY_INVALID;
1673 }
1674 }
1675
1676 static int
1677 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1678 uint32_t queue_family_index, int idx,
1679 VkDeviceQueueCreateFlags flags,
1680 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1681 {
1682 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1683 queue->device = device;
1684 queue->queue_family_index = queue_family_index;
1685 queue->queue_idx = idx;
1686 queue->priority = radv_get_queue_global_priority(global_priority);
1687 queue->flags = flags;
1688
1689 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1690 if (!queue->hw_ctx)
1691 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1692
1693 return VK_SUCCESS;
1694 }
1695
1696 static void
1697 radv_queue_finish(struct radv_queue *queue)
1698 {
1699 if (queue->hw_ctx)
1700 queue->device->ws->ctx_destroy(queue->hw_ctx);
1701
1702 if (queue->initial_full_flush_preamble_cs)
1703 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1704 if (queue->initial_preamble_cs)
1705 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1706 if (queue->continue_preamble_cs)
1707 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1708 if (queue->descriptor_bo)
1709 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1710 if (queue->scratch_bo)
1711 queue->device->ws->buffer_destroy(queue->scratch_bo);
1712 if (queue->esgs_ring_bo)
1713 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1714 if (queue->gsvs_ring_bo)
1715 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1716 if (queue->tess_rings_bo)
1717 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1718 if (queue->compute_scratch_bo)
1719 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1720 }
1721
1722 static void
1723 radv_bo_list_init(struct radv_bo_list *bo_list)
1724 {
1725 pthread_mutex_init(&bo_list->mutex, NULL);
1726 bo_list->list.count = bo_list->capacity = 0;
1727 bo_list->list.bos = NULL;
1728 }
1729
1730 static void
1731 radv_bo_list_finish(struct radv_bo_list *bo_list)
1732 {
1733 free(bo_list->list.bos);
1734 pthread_mutex_destroy(&bo_list->mutex);
1735 }
1736
1737 static VkResult radv_bo_list_add(struct radv_device *device,
1738 struct radeon_winsys_bo *bo)
1739 {
1740 struct radv_bo_list *bo_list = &device->bo_list;
1741
1742 if (bo->is_local)
1743 return VK_SUCCESS;
1744
1745 if (unlikely(!device->use_global_bo_list))
1746 return VK_SUCCESS;
1747
1748 pthread_mutex_lock(&bo_list->mutex);
1749 if (bo_list->list.count == bo_list->capacity) {
1750 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1751 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1752
1753 if (!data) {
1754 pthread_mutex_unlock(&bo_list->mutex);
1755 return VK_ERROR_OUT_OF_HOST_MEMORY;
1756 }
1757
1758 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1759 bo_list->capacity = capacity;
1760 }
1761
1762 bo_list->list.bos[bo_list->list.count++] = bo;
1763 pthread_mutex_unlock(&bo_list->mutex);
1764 return VK_SUCCESS;
1765 }
1766
1767 static void radv_bo_list_remove(struct radv_device *device,
1768 struct radeon_winsys_bo *bo)
1769 {
1770 struct radv_bo_list *bo_list = &device->bo_list;
1771
1772 if (bo->is_local)
1773 return;
1774
1775 if (unlikely(!device->use_global_bo_list))
1776 return;
1777
1778 pthread_mutex_lock(&bo_list->mutex);
1779 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1780 if (bo_list->list.bos[i] == bo) {
1781 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1782 --bo_list->list.count;
1783 break;
1784 }
1785 }
1786 pthread_mutex_unlock(&bo_list->mutex);
1787 }
1788
1789 static void
1790 radv_device_init_gs_info(struct radv_device *device)
1791 {
1792 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1793 device->physical_device->rad_info.family);
1794 }
1795
1796 static int radv_get_device_extension_index(const char *name)
1797 {
1798 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1799 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1800 return i;
1801 }
1802 return -1;
1803 }
1804
1805 static int
1806 radv_get_int_debug_option(const char *name, int default_value)
1807 {
1808 const char *str;
1809 int result;
1810
1811 str = getenv(name);
1812 if (!str) {
1813 result = default_value;
1814 } else {
1815 char *endptr;
1816
1817 result = strtol(str, &endptr, 0);
1818 if (str == endptr) {
1819 /* No digits founs. */
1820 result = default_value;
1821 }
1822 }
1823
1824 return result;
1825 }
1826
1827 VkResult radv_CreateDevice(
1828 VkPhysicalDevice physicalDevice,
1829 const VkDeviceCreateInfo* pCreateInfo,
1830 const VkAllocationCallbacks* pAllocator,
1831 VkDevice* pDevice)
1832 {
1833 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1834 VkResult result;
1835 struct radv_device *device;
1836
1837 bool keep_shader_info = false;
1838
1839 /* Check enabled features */
1840 if (pCreateInfo->pEnabledFeatures) {
1841 VkPhysicalDeviceFeatures supported_features;
1842 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1843 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1844 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1845 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1846 for (uint32_t i = 0; i < num_features; i++) {
1847 if (enabled_feature[i] && !supported_feature[i])
1848 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1849 }
1850 }
1851
1852 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1853 sizeof(*device), 8,
1854 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1855 if (!device)
1856 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1857
1858 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1859 device->instance = physical_device->instance;
1860 device->physical_device = physical_device;
1861
1862 device->ws = physical_device->ws;
1863 if (pAllocator)
1864 device->alloc = *pAllocator;
1865 else
1866 device->alloc = physical_device->instance->alloc;
1867
1868 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1869 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1870 int index = radv_get_device_extension_index(ext_name);
1871 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1872 vk_free(&device->alloc, device);
1873 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1874 }
1875
1876 device->enabled_extensions.extensions[index] = true;
1877 }
1878
1879 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1880
1881 /* With update after bind we can't attach bo's to the command buffer
1882 * from the descriptor set anymore, so we have to use a global BO list.
1883 */
1884 device->use_global_bo_list =
1885 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1886 device->enabled_extensions.EXT_descriptor_indexing ||
1887 device->enabled_extensions.EXT_buffer_device_address;
1888
1889 mtx_init(&device->shader_slab_mutex, mtx_plain);
1890 list_inithead(&device->shader_slabs);
1891
1892 radv_bo_list_init(&device->bo_list);
1893
1894 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1895 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1896 uint32_t qfi = queue_create->queueFamilyIndex;
1897 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1898 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1899
1900 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1901
1902 device->queues[qfi] = vk_alloc(&device->alloc,
1903 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1904 if (!device->queues[qfi]) {
1905 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1906 goto fail;
1907 }
1908
1909 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1910
1911 device->queue_count[qfi] = queue_create->queueCount;
1912
1913 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1914 result = radv_queue_init(device, &device->queues[qfi][q],
1915 qfi, q, queue_create->flags,
1916 global_priority);
1917 if (result != VK_SUCCESS)
1918 goto fail;
1919 }
1920 }
1921
1922 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1923 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1924
1925 /* Disabled and not implemented for now. */
1926 device->dfsm_allowed = device->pbb_allowed &&
1927 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1928 device->physical_device->rad_info.family == CHIP_RAVEN2);
1929
1930 #ifdef ANDROID
1931 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1932 #endif
1933
1934 /* The maximum number of scratch waves. Scratch space isn't divided
1935 * evenly between CUs. The number is only a function of the number of CUs.
1936 * We can decrease the constant to decrease the scratch buffer size.
1937 *
1938 * sctx->scratch_waves must be >= the maximum possible size of
1939 * 1 threadgroup, so that the hw doesn't hang from being unable
1940 * to start any.
1941 *
1942 * The recommended value is 4 per CU at most. Higher numbers don't
1943 * bring much benefit, but they still occupy chip resources (think
1944 * async compute). I've seen ~2% performance difference between 4 and 32.
1945 */
1946 uint32_t max_threads_per_block = 2048;
1947 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1948 max_threads_per_block / 64);
1949
1950 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1951 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1952
1953 if (device->physical_device->rad_info.chip_class >= GFX7) {
1954 /* If the KMD allows it (there is a KMD hw register for it),
1955 * allow launching waves out-of-order.
1956 */
1957 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1958 }
1959
1960 radv_device_init_gs_info(device);
1961
1962 device->tess_offchip_block_dw_size =
1963 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1964 device->has_distributed_tess =
1965 device->physical_device->rad_info.chip_class >= GFX8 &&
1966 device->physical_device->rad_info.max_se >= 2;
1967
1968 if (getenv("RADV_TRACE_FILE")) {
1969 const char *filename = getenv("RADV_TRACE_FILE");
1970
1971 keep_shader_info = true;
1972
1973 if (!radv_init_trace(device))
1974 goto fail;
1975
1976 fprintf(stderr, "*****************************************************************************\n");
1977 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1978 fprintf(stderr, "*****************************************************************************\n");
1979
1980 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1981 radv_dump_enabled_options(device, stderr);
1982 }
1983
1984 device->keep_shader_info = keep_shader_info;
1985
1986 result = radv_device_init_meta(device);
1987 if (result != VK_SUCCESS)
1988 goto fail;
1989
1990 radv_device_init_msaa(device);
1991
1992 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1993 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1994 switch (family) {
1995 case RADV_QUEUE_GENERAL:
1996 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1997 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1998 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1999 break;
2000 case RADV_QUEUE_COMPUTE:
2001 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2002 radeon_emit(device->empty_cs[family], 0);
2003 break;
2004 }
2005 device->ws->cs_finalize(device->empty_cs[family]);
2006 }
2007
2008 if (device->physical_device->rad_info.chip_class >= GFX7)
2009 cik_create_gfx_config(device);
2010
2011 VkPipelineCacheCreateInfo ci;
2012 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2013 ci.pNext = NULL;
2014 ci.flags = 0;
2015 ci.pInitialData = NULL;
2016 ci.initialDataSize = 0;
2017 VkPipelineCache pc;
2018 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2019 &ci, NULL, &pc);
2020 if (result != VK_SUCCESS)
2021 goto fail_meta;
2022
2023 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2024
2025 device->force_aniso =
2026 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2027 if (device->force_aniso >= 0) {
2028 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2029 1 << util_logbase2(device->force_aniso));
2030 }
2031
2032 *pDevice = radv_device_to_handle(device);
2033 return VK_SUCCESS;
2034
2035 fail_meta:
2036 radv_device_finish_meta(device);
2037 fail:
2038 radv_bo_list_finish(&device->bo_list);
2039
2040 if (device->trace_bo)
2041 device->ws->buffer_destroy(device->trace_bo);
2042
2043 if (device->gfx_init)
2044 device->ws->buffer_destroy(device->gfx_init);
2045
2046 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2047 for (unsigned q = 0; q < device->queue_count[i]; q++)
2048 radv_queue_finish(&device->queues[i][q]);
2049 if (device->queue_count[i])
2050 vk_free(&device->alloc, device->queues[i]);
2051 }
2052
2053 vk_free(&device->alloc, device);
2054 return result;
2055 }
2056
2057 void radv_DestroyDevice(
2058 VkDevice _device,
2059 const VkAllocationCallbacks* pAllocator)
2060 {
2061 RADV_FROM_HANDLE(radv_device, device, _device);
2062
2063 if (!device)
2064 return;
2065
2066 if (device->trace_bo)
2067 device->ws->buffer_destroy(device->trace_bo);
2068
2069 if (device->gfx_init)
2070 device->ws->buffer_destroy(device->gfx_init);
2071
2072 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2073 for (unsigned q = 0; q < device->queue_count[i]; q++)
2074 radv_queue_finish(&device->queues[i][q]);
2075 if (device->queue_count[i])
2076 vk_free(&device->alloc, device->queues[i]);
2077 if (device->empty_cs[i])
2078 device->ws->cs_destroy(device->empty_cs[i]);
2079 }
2080 radv_device_finish_meta(device);
2081
2082 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2083 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2084
2085 radv_destroy_shader_slabs(device);
2086
2087 radv_bo_list_finish(&device->bo_list);
2088 vk_free(&device->alloc, device);
2089 }
2090
2091 VkResult radv_EnumerateInstanceLayerProperties(
2092 uint32_t* pPropertyCount,
2093 VkLayerProperties* pProperties)
2094 {
2095 if (pProperties == NULL) {
2096 *pPropertyCount = 0;
2097 return VK_SUCCESS;
2098 }
2099
2100 /* None supported at this time */
2101 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2102 }
2103
2104 VkResult radv_EnumerateDeviceLayerProperties(
2105 VkPhysicalDevice physicalDevice,
2106 uint32_t* pPropertyCount,
2107 VkLayerProperties* pProperties)
2108 {
2109 if (pProperties == NULL) {
2110 *pPropertyCount = 0;
2111 return VK_SUCCESS;
2112 }
2113
2114 /* None supported at this time */
2115 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2116 }
2117
2118 void radv_GetDeviceQueue2(
2119 VkDevice _device,
2120 const VkDeviceQueueInfo2* pQueueInfo,
2121 VkQueue* pQueue)
2122 {
2123 RADV_FROM_HANDLE(radv_device, device, _device);
2124 struct radv_queue *queue;
2125
2126 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2127 if (pQueueInfo->flags != queue->flags) {
2128 /* From the Vulkan 1.1.70 spec:
2129 *
2130 * "The queue returned by vkGetDeviceQueue2 must have the same
2131 * flags value from this structure as that used at device
2132 * creation time in a VkDeviceQueueCreateInfo instance. If no
2133 * matching flags were specified at device creation time then
2134 * pQueue will return VK_NULL_HANDLE."
2135 */
2136 *pQueue = VK_NULL_HANDLE;
2137 return;
2138 }
2139
2140 *pQueue = radv_queue_to_handle(queue);
2141 }
2142
2143 void radv_GetDeviceQueue(
2144 VkDevice _device,
2145 uint32_t queueFamilyIndex,
2146 uint32_t queueIndex,
2147 VkQueue* pQueue)
2148 {
2149 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2150 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2151 .queueFamilyIndex = queueFamilyIndex,
2152 .queueIndex = queueIndex
2153 };
2154
2155 radv_GetDeviceQueue2(_device, &info, pQueue);
2156 }
2157
2158 static void
2159 fill_geom_tess_rings(struct radv_queue *queue,
2160 uint32_t *map,
2161 bool add_sample_positions,
2162 uint32_t esgs_ring_size,
2163 struct radeon_winsys_bo *esgs_ring_bo,
2164 uint32_t gsvs_ring_size,
2165 struct radeon_winsys_bo *gsvs_ring_bo,
2166 uint32_t tess_factor_ring_size,
2167 uint32_t tess_offchip_ring_offset,
2168 uint32_t tess_offchip_ring_size,
2169 struct radeon_winsys_bo *tess_rings_bo)
2170 {
2171 uint32_t *desc = &map[4];
2172
2173 if (esgs_ring_bo) {
2174 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2175
2176 /* stride 0, num records - size, add tid, swizzle, elsize4,
2177 index stride 64 */
2178 desc[0] = esgs_va;
2179 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2180 S_008F04_SWIZZLE_ENABLE(true);
2181 desc[2] = esgs_ring_size;
2182 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2186 S_008F0C_INDEX_STRIDE(3) |
2187 S_008F0C_ADD_TID_ENABLE(1);
2188
2189 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2190 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2191 S_008F0C_OOB_SELECT(2) |
2192 S_008F0C_RESOURCE_LEVEL(1);
2193 } else {
2194 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2196 S_008F0C_ELEMENT_SIZE(1);
2197 }
2198
2199 /* GS entry for ES->GS ring */
2200 /* stride 0, num records - size, elsize0,
2201 index stride 0 */
2202 desc[4] = esgs_va;
2203 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2204 desc[6] = esgs_ring_size;
2205 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2206 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2207 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2208 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2209
2210 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2211 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2212 S_008F0C_OOB_SELECT(2) |
2213 S_008F0C_RESOURCE_LEVEL(1);
2214 } else {
2215 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2216 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2217 }
2218 }
2219
2220 desc += 8;
2221
2222 if (gsvs_ring_bo) {
2223 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2224
2225 /* VS entry for GS->VS ring */
2226 /* stride 0, num records - size, elsize0,
2227 index stride 0 */
2228 desc[0] = gsvs_va;
2229 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2230 desc[2] = gsvs_ring_size;
2231 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2232 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2233 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2234 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2235
2236 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2237 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2238 S_008F0C_OOB_SELECT(2) |
2239 S_008F0C_RESOURCE_LEVEL(1);
2240 } else {
2241 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2242 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2243 }
2244
2245 /* stride gsvs_itemsize, num records 64
2246 elsize 4, index stride 16 */
2247 /* shader will patch stride and desc[2] */
2248 desc[4] = gsvs_va;
2249 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2250 S_008F04_SWIZZLE_ENABLE(1);
2251 desc[6] = 0;
2252 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2253 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2254 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2255 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2256 S_008F0C_INDEX_STRIDE(1) |
2257 S_008F0C_ADD_TID_ENABLE(true);
2258
2259 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2260 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2261 S_008F0C_OOB_SELECT(2) |
2262 S_008F0C_RESOURCE_LEVEL(1);
2263 } else {
2264 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2265 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2266 S_008F0C_ELEMENT_SIZE(1);
2267 }
2268
2269 }
2270
2271 desc += 8;
2272
2273 if (tess_rings_bo) {
2274 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2275 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2276
2277 desc[0] = tess_va;
2278 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2279 desc[2] = tess_factor_ring_size;
2280 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2281 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2282 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2283 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2284
2285 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2286 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2287 S_008F0C_OOB_SELECT(3) |
2288 S_008F0C_RESOURCE_LEVEL(1);
2289 } else {
2290 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2291 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2292 }
2293
2294 desc[4] = tess_offchip_va;
2295 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2296 desc[6] = tess_offchip_ring_size;
2297 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2298 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2299 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2300 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2301
2302 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2303 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2304 S_008F0C_OOB_SELECT(3) |
2305 S_008F0C_RESOURCE_LEVEL(1);
2306 } else {
2307 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2308 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2309 }
2310 }
2311
2312 desc += 8;
2313
2314 if (add_sample_positions) {
2315 /* add sample positions after all rings */
2316 memcpy(desc, queue->device->sample_locations_1x, 8);
2317 desc += 2;
2318 memcpy(desc, queue->device->sample_locations_2x, 16);
2319 desc += 4;
2320 memcpy(desc, queue->device->sample_locations_4x, 32);
2321 desc += 8;
2322 memcpy(desc, queue->device->sample_locations_8x, 64);
2323 }
2324 }
2325
2326 static unsigned
2327 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2328 {
2329 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2330 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2331 device->physical_device->rad_info.family != CHIP_STONEY;
2332 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2333 unsigned max_offchip_buffers;
2334 unsigned offchip_granularity;
2335 unsigned hs_offchip_param;
2336
2337 /*
2338 * Per RadeonSI:
2339 * This must be one less than the maximum number due to a hw limitation.
2340 * Various hardware bugs need thGFX7
2341 *
2342 * Per AMDVLK:
2343 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2344 * Gfx7 should limit max_offchip_buffers to 508
2345 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2346 *
2347 * Follow AMDVLK here.
2348 */
2349 if (device->physical_device->rad_info.chip_class >= GFX10) {
2350 max_offchip_buffers_per_se = 256;
2351 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2352 device->physical_device->rad_info.chip_class == GFX7 ||
2353 device->physical_device->rad_info.chip_class == GFX6)
2354 --max_offchip_buffers_per_se;
2355
2356 max_offchip_buffers = max_offchip_buffers_per_se *
2357 device->physical_device->rad_info.max_se;
2358
2359 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2360 * around by setting 4K granularity.
2361 */
2362 if (device->tess_offchip_block_dw_size == 4096) {
2363 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2364 offchip_granularity = V_03093C_X_4K_DWORDS;
2365 } else {
2366 assert(device->tess_offchip_block_dw_size == 8192);
2367 offchip_granularity = V_03093C_X_8K_DWORDS;
2368 }
2369
2370 switch (device->physical_device->rad_info.chip_class) {
2371 case GFX6:
2372 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2373 break;
2374 case GFX7:
2375 case GFX8:
2376 case GFX9:
2377 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2378 break;
2379 case GFX10:
2380 break;
2381 default:
2382 break;
2383 }
2384
2385 *max_offchip_buffers_p = max_offchip_buffers;
2386 if (device->physical_device->rad_info.chip_class >= GFX7) {
2387 if (device->physical_device->rad_info.chip_class >= GFX8)
2388 --max_offchip_buffers;
2389 hs_offchip_param =
2390 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2391 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2392 } else {
2393 hs_offchip_param =
2394 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2395 }
2396 return hs_offchip_param;
2397 }
2398
2399 static void
2400 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2401 struct radeon_winsys_bo *esgs_ring_bo,
2402 uint32_t esgs_ring_size,
2403 struct radeon_winsys_bo *gsvs_ring_bo,
2404 uint32_t gsvs_ring_size)
2405 {
2406 if (!esgs_ring_bo && !gsvs_ring_bo)
2407 return;
2408
2409 if (esgs_ring_bo)
2410 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2411
2412 if (gsvs_ring_bo)
2413 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2414
2415 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2416 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2417 radeon_emit(cs, esgs_ring_size >> 8);
2418 radeon_emit(cs, gsvs_ring_size >> 8);
2419 } else {
2420 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2421 radeon_emit(cs, esgs_ring_size >> 8);
2422 radeon_emit(cs, gsvs_ring_size >> 8);
2423 }
2424 }
2425
2426 static void
2427 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2428 unsigned hs_offchip_param, unsigned tf_ring_size,
2429 struct radeon_winsys_bo *tess_rings_bo)
2430 {
2431 uint64_t tf_va;
2432
2433 if (!tess_rings_bo)
2434 return;
2435
2436 tf_va = radv_buffer_get_va(tess_rings_bo);
2437
2438 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2439
2440 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2441 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2442 S_030938_SIZE(tf_ring_size / 4));
2443 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2444 tf_va >> 8);
2445
2446 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2447 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2448 S_030984_BASE_HI(tf_va >> 40));
2449 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2450 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2451 S_030944_BASE_HI(tf_va >> 40));
2452 }
2453 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2454 hs_offchip_param);
2455 } else {
2456 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2457 S_008988_SIZE(tf_ring_size / 4));
2458 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2459 tf_va >> 8);
2460 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2461 hs_offchip_param);
2462 }
2463 }
2464
2465 static void
2466 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2467 struct radeon_winsys_bo *compute_scratch_bo)
2468 {
2469 uint64_t scratch_va;
2470
2471 if (!compute_scratch_bo)
2472 return;
2473
2474 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2475
2476 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2477
2478 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2479 radeon_emit(cs, scratch_va);
2480 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2481 S_008F04_SWIZZLE_ENABLE(1));
2482 }
2483
2484 static void
2485 radv_emit_global_shader_pointers(struct radv_queue *queue,
2486 struct radeon_cmdbuf *cs,
2487 struct radeon_winsys_bo *descriptor_bo)
2488 {
2489 uint64_t va;
2490
2491 if (!descriptor_bo)
2492 return;
2493
2494 va = radv_buffer_get_va(descriptor_bo);
2495
2496 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2497
2498 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2499 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2500 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2501 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2502 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2503
2504 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2505 radv_emit_shader_pointer(queue->device, cs, regs[i],
2506 va, true);
2507 }
2508 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2509 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2510 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2511 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2512 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2513
2514 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2515 radv_emit_shader_pointer(queue->device, cs, regs[i],
2516 va, true);
2517 }
2518 } else {
2519 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2520 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2521 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2522 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2523 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2524 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2525
2526 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2527 radv_emit_shader_pointer(queue->device, cs, regs[i],
2528 va, true);
2529 }
2530 }
2531 }
2532
2533 static void
2534 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2535 {
2536 struct radv_device *device = queue->device;
2537
2538 if (device->gfx_init) {
2539 uint64_t va = radv_buffer_get_va(device->gfx_init);
2540
2541 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2542 radeon_emit(cs, va);
2543 radeon_emit(cs, va >> 32);
2544 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2545
2546 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2547 } else {
2548 struct radv_physical_device *physical_device = device->physical_device;
2549 si_emit_graphics(physical_device, cs);
2550 }
2551 }
2552
2553 static void
2554 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2555 {
2556 struct radv_physical_device *physical_device = queue->device->physical_device;
2557 si_emit_compute(physical_device, cs);
2558 }
2559
2560 static VkResult
2561 radv_get_preamble_cs(struct radv_queue *queue,
2562 uint32_t scratch_size,
2563 uint32_t compute_scratch_size,
2564 uint32_t esgs_ring_size,
2565 uint32_t gsvs_ring_size,
2566 bool needs_tess_rings,
2567 bool needs_sample_positions,
2568 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2569 struct radeon_cmdbuf **initial_preamble_cs,
2570 struct radeon_cmdbuf **continue_preamble_cs)
2571 {
2572 struct radeon_winsys_bo *scratch_bo = NULL;
2573 struct radeon_winsys_bo *descriptor_bo = NULL;
2574 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2575 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2576 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2577 struct radeon_winsys_bo *tess_rings_bo = NULL;
2578 struct radeon_cmdbuf *dest_cs[3] = {0};
2579 bool add_tess_rings = false, add_sample_positions = false;
2580 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2581 unsigned max_offchip_buffers;
2582 unsigned hs_offchip_param = 0;
2583 unsigned tess_offchip_ring_offset;
2584 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2585 if (!queue->has_tess_rings) {
2586 if (needs_tess_rings)
2587 add_tess_rings = true;
2588 }
2589 if (!queue->has_sample_positions) {
2590 if (needs_sample_positions)
2591 add_sample_positions = true;
2592 }
2593 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2594 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2595 &max_offchip_buffers);
2596 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2597 tess_offchip_ring_size = max_offchip_buffers *
2598 queue->device->tess_offchip_block_dw_size * 4;
2599
2600 if (scratch_size <= queue->scratch_size &&
2601 compute_scratch_size <= queue->compute_scratch_size &&
2602 esgs_ring_size <= queue->esgs_ring_size &&
2603 gsvs_ring_size <= queue->gsvs_ring_size &&
2604 !add_tess_rings && !add_sample_positions &&
2605 queue->initial_preamble_cs) {
2606 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2607 *initial_preamble_cs = queue->initial_preamble_cs;
2608 *continue_preamble_cs = queue->continue_preamble_cs;
2609 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2610 *continue_preamble_cs = NULL;
2611 return VK_SUCCESS;
2612 }
2613
2614 if (scratch_size > queue->scratch_size) {
2615 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2616 scratch_size,
2617 4096,
2618 RADEON_DOMAIN_VRAM,
2619 ring_bo_flags,
2620 RADV_BO_PRIORITY_SCRATCH);
2621 if (!scratch_bo)
2622 goto fail;
2623 } else
2624 scratch_bo = queue->scratch_bo;
2625
2626 if (compute_scratch_size > queue->compute_scratch_size) {
2627 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2628 compute_scratch_size,
2629 4096,
2630 RADEON_DOMAIN_VRAM,
2631 ring_bo_flags,
2632 RADV_BO_PRIORITY_SCRATCH);
2633 if (!compute_scratch_bo)
2634 goto fail;
2635
2636 } else
2637 compute_scratch_bo = queue->compute_scratch_bo;
2638
2639 if (esgs_ring_size > queue->esgs_ring_size) {
2640 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2641 esgs_ring_size,
2642 4096,
2643 RADEON_DOMAIN_VRAM,
2644 ring_bo_flags,
2645 RADV_BO_PRIORITY_SCRATCH);
2646 if (!esgs_ring_bo)
2647 goto fail;
2648 } else {
2649 esgs_ring_bo = queue->esgs_ring_bo;
2650 esgs_ring_size = queue->esgs_ring_size;
2651 }
2652
2653 if (gsvs_ring_size > queue->gsvs_ring_size) {
2654 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2655 gsvs_ring_size,
2656 4096,
2657 RADEON_DOMAIN_VRAM,
2658 ring_bo_flags,
2659 RADV_BO_PRIORITY_SCRATCH);
2660 if (!gsvs_ring_bo)
2661 goto fail;
2662 } else {
2663 gsvs_ring_bo = queue->gsvs_ring_bo;
2664 gsvs_ring_size = queue->gsvs_ring_size;
2665 }
2666
2667 if (add_tess_rings) {
2668 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2669 tess_offchip_ring_offset + tess_offchip_ring_size,
2670 256,
2671 RADEON_DOMAIN_VRAM,
2672 ring_bo_flags,
2673 RADV_BO_PRIORITY_SCRATCH);
2674 if (!tess_rings_bo)
2675 goto fail;
2676 } else {
2677 tess_rings_bo = queue->tess_rings_bo;
2678 }
2679
2680 if (scratch_bo != queue->scratch_bo ||
2681 esgs_ring_bo != queue->esgs_ring_bo ||
2682 gsvs_ring_bo != queue->gsvs_ring_bo ||
2683 tess_rings_bo != queue->tess_rings_bo ||
2684 add_sample_positions) {
2685 uint32_t size = 0;
2686 if (gsvs_ring_bo || esgs_ring_bo ||
2687 tess_rings_bo || add_sample_positions) {
2688 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2689 if (add_sample_positions)
2690 size += 128; /* 64+32+16+8 = 120 bytes */
2691 }
2692 else if (scratch_bo)
2693 size = 8; /* 2 dword */
2694
2695 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2696 size,
2697 4096,
2698 RADEON_DOMAIN_VRAM,
2699 RADEON_FLAG_CPU_ACCESS |
2700 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2701 RADEON_FLAG_READ_ONLY,
2702 RADV_BO_PRIORITY_DESCRIPTOR);
2703 if (!descriptor_bo)
2704 goto fail;
2705 } else
2706 descriptor_bo = queue->descriptor_bo;
2707
2708 if (descriptor_bo != queue->descriptor_bo) {
2709 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2710
2711 if (scratch_bo) {
2712 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2713 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2714 S_008F04_SWIZZLE_ENABLE(1);
2715 map[0] = scratch_va;
2716 map[1] = rsrc1;
2717 }
2718
2719 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2720 fill_geom_tess_rings(queue, map, add_sample_positions,
2721 esgs_ring_size, esgs_ring_bo,
2722 gsvs_ring_size, gsvs_ring_bo,
2723 tess_factor_ring_size,
2724 tess_offchip_ring_offset,
2725 tess_offchip_ring_size,
2726 tess_rings_bo);
2727
2728 queue->device->ws->buffer_unmap(descriptor_bo);
2729 }
2730
2731 for(int i = 0; i < 3; ++i) {
2732 struct radeon_cmdbuf *cs = NULL;
2733 cs = queue->device->ws->cs_create(queue->device->ws,
2734 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2735 if (!cs)
2736 goto fail;
2737
2738 dest_cs[i] = cs;
2739
2740 if (scratch_bo)
2741 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2742
2743 /* Emit initial configuration. */
2744 switch (queue->queue_family_index) {
2745 case RADV_QUEUE_GENERAL:
2746 radv_init_graphics_state(cs, queue);
2747 break;
2748 case RADV_QUEUE_COMPUTE:
2749 radv_init_compute_state(cs, queue);
2750 break;
2751 case RADV_QUEUE_TRANSFER:
2752 break;
2753 }
2754
2755 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2757 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2758
2759 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2760 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2761 }
2762
2763 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2764 gsvs_ring_bo, gsvs_ring_size);
2765 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2766 tess_factor_ring_size, tess_rings_bo);
2767 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2768 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2769
2770 if (i == 0) {
2771 si_cs_emit_cache_flush(cs,
2772 queue->device->physical_device->rad_info.chip_class,
2773 NULL, 0,
2774 queue->queue_family_index == RING_COMPUTE &&
2775 queue->device->physical_device->rad_info.chip_class >= GFX7,
2776 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2777 RADV_CMD_FLAG_INV_ICACHE |
2778 RADV_CMD_FLAG_INV_SCACHE |
2779 RADV_CMD_FLAG_INV_VCACHE |
2780 RADV_CMD_FLAG_INV_L2 |
2781 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2782 } else if (i == 1) {
2783 si_cs_emit_cache_flush(cs,
2784 queue->device->physical_device->rad_info.chip_class,
2785 NULL, 0,
2786 queue->queue_family_index == RING_COMPUTE &&
2787 queue->device->physical_device->rad_info.chip_class >= GFX7,
2788 RADV_CMD_FLAG_INV_ICACHE |
2789 RADV_CMD_FLAG_INV_SCACHE |
2790 RADV_CMD_FLAG_INV_VCACHE |
2791 RADV_CMD_FLAG_INV_L2 |
2792 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2793 }
2794
2795 if (!queue->device->ws->cs_finalize(cs))
2796 goto fail;
2797 }
2798
2799 if (queue->initial_full_flush_preamble_cs)
2800 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2801
2802 if (queue->initial_preamble_cs)
2803 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2804
2805 if (queue->continue_preamble_cs)
2806 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2807
2808 queue->initial_full_flush_preamble_cs = dest_cs[0];
2809 queue->initial_preamble_cs = dest_cs[1];
2810 queue->continue_preamble_cs = dest_cs[2];
2811
2812 if (scratch_bo != queue->scratch_bo) {
2813 if (queue->scratch_bo)
2814 queue->device->ws->buffer_destroy(queue->scratch_bo);
2815 queue->scratch_bo = scratch_bo;
2816 queue->scratch_size = scratch_size;
2817 }
2818
2819 if (compute_scratch_bo != queue->compute_scratch_bo) {
2820 if (queue->compute_scratch_bo)
2821 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2822 queue->compute_scratch_bo = compute_scratch_bo;
2823 queue->compute_scratch_size = compute_scratch_size;
2824 }
2825
2826 if (esgs_ring_bo != queue->esgs_ring_bo) {
2827 if (queue->esgs_ring_bo)
2828 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2829 queue->esgs_ring_bo = esgs_ring_bo;
2830 queue->esgs_ring_size = esgs_ring_size;
2831 }
2832
2833 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2834 if (queue->gsvs_ring_bo)
2835 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2836 queue->gsvs_ring_bo = gsvs_ring_bo;
2837 queue->gsvs_ring_size = gsvs_ring_size;
2838 }
2839
2840 if (tess_rings_bo != queue->tess_rings_bo) {
2841 queue->tess_rings_bo = tess_rings_bo;
2842 queue->has_tess_rings = true;
2843 }
2844
2845 if (descriptor_bo != queue->descriptor_bo) {
2846 if (queue->descriptor_bo)
2847 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2848
2849 queue->descriptor_bo = descriptor_bo;
2850 }
2851
2852 if (add_sample_positions)
2853 queue->has_sample_positions = true;
2854
2855 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2856 *initial_preamble_cs = queue->initial_preamble_cs;
2857 *continue_preamble_cs = queue->continue_preamble_cs;
2858 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2859 *continue_preamble_cs = NULL;
2860 return VK_SUCCESS;
2861 fail:
2862 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2863 if (dest_cs[i])
2864 queue->device->ws->cs_destroy(dest_cs[i]);
2865 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2866 queue->device->ws->buffer_destroy(descriptor_bo);
2867 if (scratch_bo && scratch_bo != queue->scratch_bo)
2868 queue->device->ws->buffer_destroy(scratch_bo);
2869 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2870 queue->device->ws->buffer_destroy(compute_scratch_bo);
2871 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2872 queue->device->ws->buffer_destroy(esgs_ring_bo);
2873 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2874 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2875 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2876 queue->device->ws->buffer_destroy(tess_rings_bo);
2877 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2878 }
2879
2880 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2881 struct radv_winsys_sem_counts *counts,
2882 int num_sems,
2883 const VkSemaphore *sems,
2884 VkFence _fence,
2885 bool reset_temp)
2886 {
2887 int syncobj_idx = 0, sem_idx = 0;
2888
2889 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2890 return VK_SUCCESS;
2891
2892 for (uint32_t i = 0; i < num_sems; i++) {
2893 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2894
2895 if (sem->temp_syncobj || sem->syncobj)
2896 counts->syncobj_count++;
2897 else
2898 counts->sem_count++;
2899 }
2900
2901 if (_fence != VK_NULL_HANDLE) {
2902 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2903 if (fence->temp_syncobj || fence->syncobj)
2904 counts->syncobj_count++;
2905 }
2906
2907 if (counts->syncobj_count) {
2908 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2909 if (!counts->syncobj)
2910 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2911 }
2912
2913 if (counts->sem_count) {
2914 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2915 if (!counts->sem) {
2916 free(counts->syncobj);
2917 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2918 }
2919 }
2920
2921 for (uint32_t i = 0; i < num_sems; i++) {
2922 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2923
2924 if (sem->temp_syncobj) {
2925 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2926 }
2927 else if (sem->syncobj)
2928 counts->syncobj[syncobj_idx++] = sem->syncobj;
2929 else {
2930 assert(sem->sem);
2931 counts->sem[sem_idx++] = sem->sem;
2932 }
2933 }
2934
2935 if (_fence != VK_NULL_HANDLE) {
2936 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2937 if (fence->temp_syncobj)
2938 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2939 else if (fence->syncobj)
2940 counts->syncobj[syncobj_idx++] = fence->syncobj;
2941 }
2942
2943 return VK_SUCCESS;
2944 }
2945
2946 static void
2947 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2948 {
2949 free(sem_info->wait.syncobj);
2950 free(sem_info->wait.sem);
2951 free(sem_info->signal.syncobj);
2952 free(sem_info->signal.sem);
2953 }
2954
2955
2956 static void radv_free_temp_syncobjs(struct radv_device *device,
2957 int num_sems,
2958 const VkSemaphore *sems)
2959 {
2960 for (uint32_t i = 0; i < num_sems; i++) {
2961 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2962
2963 if (sem->temp_syncobj) {
2964 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2965 sem->temp_syncobj = 0;
2966 }
2967 }
2968 }
2969
2970 static VkResult
2971 radv_alloc_sem_info(struct radv_instance *instance,
2972 struct radv_winsys_sem_info *sem_info,
2973 int num_wait_sems,
2974 const VkSemaphore *wait_sems,
2975 int num_signal_sems,
2976 const VkSemaphore *signal_sems,
2977 VkFence fence)
2978 {
2979 VkResult ret;
2980 memset(sem_info, 0, sizeof(*sem_info));
2981
2982 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2983 if (ret)
2984 return ret;
2985 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2986 if (ret)
2987 radv_free_sem_info(sem_info);
2988
2989 /* caller can override these */
2990 sem_info->cs_emit_wait = true;
2991 sem_info->cs_emit_signal = true;
2992 return ret;
2993 }
2994
2995 /* Signals fence as soon as all the work currently put on queue is done. */
2996 static VkResult radv_signal_fence(struct radv_queue *queue,
2997 struct radv_fence *fence)
2998 {
2999 int ret;
3000 VkResult result;
3001 struct radv_winsys_sem_info sem_info;
3002
3003 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3004 radv_fence_to_handle(fence));
3005 if (result != VK_SUCCESS)
3006 return result;
3007
3008 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3009 &queue->device->empty_cs[queue->queue_family_index],
3010 1, NULL, NULL, &sem_info, NULL,
3011 false, fence->fence);
3012 radv_free_sem_info(&sem_info);
3013
3014 if (ret)
3015 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3016
3017 return VK_SUCCESS;
3018 }
3019
3020 VkResult radv_QueueSubmit(
3021 VkQueue _queue,
3022 uint32_t submitCount,
3023 const VkSubmitInfo* pSubmits,
3024 VkFence _fence)
3025 {
3026 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3027 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3028 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3029 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3030 int ret;
3031 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3032 uint32_t scratch_size = 0;
3033 uint32_t compute_scratch_size = 0;
3034 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3035 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3036 VkResult result;
3037 bool fence_emitted = false;
3038 bool tess_rings_needed = false;
3039 bool sample_positions_needed = false;
3040
3041 /* Do this first so failing to allocate scratch buffers can't result in
3042 * partially executed submissions. */
3043 for (uint32_t i = 0; i < submitCount; i++) {
3044 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3046 pSubmits[i].pCommandBuffers[j]);
3047
3048 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3049 compute_scratch_size = MAX2(compute_scratch_size,
3050 cmd_buffer->compute_scratch_size_needed);
3051 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3052 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3053 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3054 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3055 }
3056 }
3057
3058 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3059 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3060 sample_positions_needed, &initial_flush_preamble_cs,
3061 &initial_preamble_cs, &continue_preamble_cs);
3062 if (result != VK_SUCCESS)
3063 return result;
3064
3065 for (uint32_t i = 0; i < submitCount; i++) {
3066 struct radeon_cmdbuf **cs_array;
3067 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3068 bool can_patch = true;
3069 uint32_t advance;
3070 struct radv_winsys_sem_info sem_info;
3071
3072 result = radv_alloc_sem_info(queue->device->instance,
3073 &sem_info,
3074 pSubmits[i].waitSemaphoreCount,
3075 pSubmits[i].pWaitSemaphores,
3076 pSubmits[i].signalSemaphoreCount,
3077 pSubmits[i].pSignalSemaphores,
3078 _fence);
3079 if (result != VK_SUCCESS)
3080 return result;
3081
3082 if (!pSubmits[i].commandBufferCount) {
3083 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3084 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3085 &queue->device->empty_cs[queue->queue_family_index],
3086 1, NULL, NULL,
3087 &sem_info, NULL,
3088 false, base_fence);
3089 if (ret) {
3090 radv_loge("failed to submit CS %d\n", i);
3091 abort();
3092 }
3093 fence_emitted = true;
3094 }
3095 radv_free_sem_info(&sem_info);
3096 continue;
3097 }
3098
3099 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3100 (pSubmits[i].commandBufferCount));
3101
3102 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3104 pSubmits[i].pCommandBuffers[j]);
3105 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3106
3107 cs_array[j] = cmd_buffer->cs;
3108 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3109 can_patch = false;
3110
3111 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3112 }
3113
3114 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3115 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3116 const struct radv_winsys_bo_list *bo_list = NULL;
3117
3118 advance = MIN2(max_cs_submission,
3119 pSubmits[i].commandBufferCount - j);
3120
3121 if (queue->device->trace_bo)
3122 *queue->device->trace_id_ptr = 0;
3123
3124 sem_info.cs_emit_wait = j == 0;
3125 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3126
3127 if (unlikely(queue->device->use_global_bo_list)) {
3128 pthread_mutex_lock(&queue->device->bo_list.mutex);
3129 bo_list = &queue->device->bo_list.list;
3130 }
3131
3132 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3133 advance, initial_preamble, continue_preamble_cs,
3134 &sem_info, bo_list,
3135 can_patch, base_fence);
3136
3137 if (unlikely(queue->device->use_global_bo_list))
3138 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3139
3140 if (ret) {
3141 radv_loge("failed to submit CS %d\n", i);
3142 abort();
3143 }
3144 fence_emitted = true;
3145 if (queue->device->trace_bo) {
3146 radv_check_gpu_hangs(queue, cs_array[j]);
3147 }
3148 }
3149
3150 radv_free_temp_syncobjs(queue->device,
3151 pSubmits[i].waitSemaphoreCount,
3152 pSubmits[i].pWaitSemaphores);
3153 radv_free_sem_info(&sem_info);
3154 free(cs_array);
3155 }
3156
3157 if (fence) {
3158 if (!fence_emitted) {
3159 result = radv_signal_fence(queue, fence);
3160 if (result != VK_SUCCESS)
3161 return result;
3162 }
3163 }
3164
3165 return VK_SUCCESS;
3166 }
3167
3168 VkResult radv_QueueWaitIdle(
3169 VkQueue _queue)
3170 {
3171 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3172
3173 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3174 radv_queue_family_to_ring(queue->queue_family_index),
3175 queue->queue_idx);
3176 return VK_SUCCESS;
3177 }
3178
3179 VkResult radv_DeviceWaitIdle(
3180 VkDevice _device)
3181 {
3182 RADV_FROM_HANDLE(radv_device, device, _device);
3183
3184 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3185 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3186 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3187 }
3188 }
3189 return VK_SUCCESS;
3190 }
3191
3192 VkResult radv_EnumerateInstanceExtensionProperties(
3193 const char* pLayerName,
3194 uint32_t* pPropertyCount,
3195 VkExtensionProperties* pProperties)
3196 {
3197 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3198
3199 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3200 if (radv_supported_instance_extensions.extensions[i]) {
3201 vk_outarray_append(&out, prop) {
3202 *prop = radv_instance_extensions[i];
3203 }
3204 }
3205 }
3206
3207 return vk_outarray_status(&out);
3208 }
3209
3210 VkResult radv_EnumerateDeviceExtensionProperties(
3211 VkPhysicalDevice physicalDevice,
3212 const char* pLayerName,
3213 uint32_t* pPropertyCount,
3214 VkExtensionProperties* pProperties)
3215 {
3216 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3217 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3218
3219 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3220 if (device->supported_extensions.extensions[i]) {
3221 vk_outarray_append(&out, prop) {
3222 *prop = radv_device_extensions[i];
3223 }
3224 }
3225 }
3226
3227 return vk_outarray_status(&out);
3228 }
3229
3230 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3231 VkInstance _instance,
3232 const char* pName)
3233 {
3234 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3235
3236 return radv_lookup_entrypoint_checked(pName,
3237 instance ? instance->apiVersion : 0,
3238 instance ? &instance->enabled_extensions : NULL,
3239 NULL);
3240 }
3241
3242 /* The loader wants us to expose a second GetInstanceProcAddr function
3243 * to work around certain LD_PRELOAD issues seen in apps.
3244 */
3245 PUBLIC
3246 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3247 VkInstance instance,
3248 const char* pName);
3249
3250 PUBLIC
3251 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3252 VkInstance instance,
3253 const char* pName)
3254 {
3255 return radv_GetInstanceProcAddr(instance, pName);
3256 }
3257
3258 PUBLIC
3259 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3260 VkInstance _instance,
3261 const char* pName);
3262
3263 PUBLIC
3264 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3265 VkInstance _instance,
3266 const char* pName)
3267 {
3268 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3269
3270 return radv_lookup_physical_device_entrypoint_checked(pName,
3271 instance ? instance->apiVersion : 0,
3272 instance ? &instance->enabled_extensions : NULL);
3273 }
3274
3275 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3276 VkDevice _device,
3277 const char* pName)
3278 {
3279 RADV_FROM_HANDLE(radv_device, device, _device);
3280
3281 return radv_lookup_entrypoint_checked(pName,
3282 device->instance->apiVersion,
3283 &device->instance->enabled_extensions,
3284 &device->enabled_extensions);
3285 }
3286
3287 bool radv_get_memory_fd(struct radv_device *device,
3288 struct radv_device_memory *memory,
3289 int *pFD)
3290 {
3291 struct radeon_bo_metadata metadata;
3292
3293 if (memory->image) {
3294 radv_init_metadata(device, memory->image, &metadata);
3295 device->ws->buffer_set_metadata(memory->bo, &metadata);
3296 }
3297
3298 return device->ws->buffer_get_fd(device->ws, memory->bo,
3299 pFD);
3300 }
3301
3302 static VkResult radv_alloc_memory(struct radv_device *device,
3303 const VkMemoryAllocateInfo* pAllocateInfo,
3304 const VkAllocationCallbacks* pAllocator,
3305 VkDeviceMemory* pMem)
3306 {
3307 struct radv_device_memory *mem;
3308 VkResult result;
3309 enum radeon_bo_domain domain;
3310 uint32_t flags = 0;
3311 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3312
3313 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3314
3315 if (pAllocateInfo->allocationSize == 0) {
3316 /* Apparently, this is allowed */
3317 *pMem = VK_NULL_HANDLE;
3318 return VK_SUCCESS;
3319 }
3320
3321 const VkImportMemoryFdInfoKHR *import_info =
3322 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3323 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3324 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3325 const VkExportMemoryAllocateInfo *export_info =
3326 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3327 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3328 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3329
3330 const struct wsi_memory_allocate_info *wsi_info =
3331 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3332
3333 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3334 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3335 if (mem == NULL)
3336 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3337
3338 if (wsi_info && wsi_info->implicit_sync)
3339 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3340
3341 if (dedicate_info) {
3342 mem->image = radv_image_from_handle(dedicate_info->image);
3343 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3344 } else {
3345 mem->image = NULL;
3346 mem->buffer = NULL;
3347 }
3348
3349 float priority_float = 0.5;
3350 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3351 vk_find_struct_const(pAllocateInfo->pNext,
3352 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3353 if (priority_ext)
3354 priority_float = priority_ext->priority;
3355
3356 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3357 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3358
3359 mem->user_ptr = NULL;
3360
3361 if (import_info) {
3362 assert(import_info->handleType ==
3363 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3364 import_info->handleType ==
3365 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3366 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3367 priority, NULL, NULL);
3368 if (!mem->bo) {
3369 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3370 goto fail;
3371 } else {
3372 close(import_info->fd);
3373 }
3374 } else if (host_ptr_info) {
3375 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3376 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3377 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3378 pAllocateInfo->allocationSize,
3379 priority);
3380 if (!mem->bo) {
3381 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3382 goto fail;
3383 } else {
3384 mem->user_ptr = host_ptr_info->pHostPointer;
3385 }
3386 } else {
3387 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3388 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3389 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3390 domain = RADEON_DOMAIN_GTT;
3391 else
3392 domain = RADEON_DOMAIN_VRAM;
3393
3394 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3395 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3396 else
3397 flags |= RADEON_FLAG_CPU_ACCESS;
3398
3399 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3400 flags |= RADEON_FLAG_GTT_WC;
3401
3402 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3403 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3404 if (device->use_global_bo_list) {
3405 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3406 }
3407 }
3408
3409 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3410 domain, flags, priority);
3411
3412 if (!mem->bo) {
3413 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3414 goto fail;
3415 }
3416 mem->type_index = mem_type_index;
3417 }
3418
3419 result = radv_bo_list_add(device, mem->bo);
3420 if (result != VK_SUCCESS)
3421 goto fail_bo;
3422
3423 *pMem = radv_device_memory_to_handle(mem);
3424
3425 return VK_SUCCESS;
3426
3427 fail_bo:
3428 device->ws->buffer_destroy(mem->bo);
3429 fail:
3430 vk_free2(&device->alloc, pAllocator, mem);
3431
3432 return result;
3433 }
3434
3435 VkResult radv_AllocateMemory(
3436 VkDevice _device,
3437 const VkMemoryAllocateInfo* pAllocateInfo,
3438 const VkAllocationCallbacks* pAllocator,
3439 VkDeviceMemory* pMem)
3440 {
3441 RADV_FROM_HANDLE(radv_device, device, _device);
3442 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3443 }
3444
3445 void radv_FreeMemory(
3446 VkDevice _device,
3447 VkDeviceMemory _mem,
3448 const VkAllocationCallbacks* pAllocator)
3449 {
3450 RADV_FROM_HANDLE(radv_device, device, _device);
3451 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3452
3453 if (mem == NULL)
3454 return;
3455
3456 radv_bo_list_remove(device, mem->bo);
3457 device->ws->buffer_destroy(mem->bo);
3458 mem->bo = NULL;
3459
3460 vk_free2(&device->alloc, pAllocator, mem);
3461 }
3462
3463 VkResult radv_MapMemory(
3464 VkDevice _device,
3465 VkDeviceMemory _memory,
3466 VkDeviceSize offset,
3467 VkDeviceSize size,
3468 VkMemoryMapFlags flags,
3469 void** ppData)
3470 {
3471 RADV_FROM_HANDLE(radv_device, device, _device);
3472 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3473
3474 if (mem == NULL) {
3475 *ppData = NULL;
3476 return VK_SUCCESS;
3477 }
3478
3479 if (mem->user_ptr)
3480 *ppData = mem->user_ptr;
3481 else
3482 *ppData = device->ws->buffer_map(mem->bo);
3483
3484 if (*ppData) {
3485 *ppData += offset;
3486 return VK_SUCCESS;
3487 }
3488
3489 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3490 }
3491
3492 void radv_UnmapMemory(
3493 VkDevice _device,
3494 VkDeviceMemory _memory)
3495 {
3496 RADV_FROM_HANDLE(radv_device, device, _device);
3497 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3498
3499 if (mem == NULL)
3500 return;
3501
3502 if (mem->user_ptr == NULL)
3503 device->ws->buffer_unmap(mem->bo);
3504 }
3505
3506 VkResult radv_FlushMappedMemoryRanges(
3507 VkDevice _device,
3508 uint32_t memoryRangeCount,
3509 const VkMappedMemoryRange* pMemoryRanges)
3510 {
3511 return VK_SUCCESS;
3512 }
3513
3514 VkResult radv_InvalidateMappedMemoryRanges(
3515 VkDevice _device,
3516 uint32_t memoryRangeCount,
3517 const VkMappedMemoryRange* pMemoryRanges)
3518 {
3519 return VK_SUCCESS;
3520 }
3521
3522 void radv_GetBufferMemoryRequirements(
3523 VkDevice _device,
3524 VkBuffer _buffer,
3525 VkMemoryRequirements* pMemoryRequirements)
3526 {
3527 RADV_FROM_HANDLE(radv_device, device, _device);
3528 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3529
3530 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3531
3532 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3533 pMemoryRequirements->alignment = 4096;
3534 else
3535 pMemoryRequirements->alignment = 16;
3536
3537 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3538 }
3539
3540 void radv_GetBufferMemoryRequirements2(
3541 VkDevice device,
3542 const VkBufferMemoryRequirementsInfo2 *pInfo,
3543 VkMemoryRequirements2 *pMemoryRequirements)
3544 {
3545 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3546 &pMemoryRequirements->memoryRequirements);
3547 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3548 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3549 switch (ext->sType) {
3550 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3551 VkMemoryDedicatedRequirements *req =
3552 (VkMemoryDedicatedRequirements *) ext;
3553 req->requiresDedicatedAllocation = buffer->shareable;
3554 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3555 break;
3556 }
3557 default:
3558 break;
3559 }
3560 }
3561 }
3562
3563 void radv_GetImageMemoryRequirements(
3564 VkDevice _device,
3565 VkImage _image,
3566 VkMemoryRequirements* pMemoryRequirements)
3567 {
3568 RADV_FROM_HANDLE(radv_device, device, _device);
3569 RADV_FROM_HANDLE(radv_image, image, _image);
3570
3571 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3572
3573 pMemoryRequirements->size = image->size;
3574 pMemoryRequirements->alignment = image->alignment;
3575 }
3576
3577 void radv_GetImageMemoryRequirements2(
3578 VkDevice device,
3579 const VkImageMemoryRequirementsInfo2 *pInfo,
3580 VkMemoryRequirements2 *pMemoryRequirements)
3581 {
3582 radv_GetImageMemoryRequirements(device, pInfo->image,
3583 &pMemoryRequirements->memoryRequirements);
3584
3585 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3586
3587 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3588 switch (ext->sType) {
3589 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3590 VkMemoryDedicatedRequirements *req =
3591 (VkMemoryDedicatedRequirements *) ext;
3592 req->requiresDedicatedAllocation = image->shareable;
3593 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3594 break;
3595 }
3596 default:
3597 break;
3598 }
3599 }
3600 }
3601
3602 void radv_GetImageSparseMemoryRequirements(
3603 VkDevice device,
3604 VkImage image,
3605 uint32_t* pSparseMemoryRequirementCount,
3606 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3607 {
3608 stub();
3609 }
3610
3611 void radv_GetImageSparseMemoryRequirements2(
3612 VkDevice device,
3613 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3614 uint32_t* pSparseMemoryRequirementCount,
3615 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3616 {
3617 stub();
3618 }
3619
3620 void radv_GetDeviceMemoryCommitment(
3621 VkDevice device,
3622 VkDeviceMemory memory,
3623 VkDeviceSize* pCommittedMemoryInBytes)
3624 {
3625 *pCommittedMemoryInBytes = 0;
3626 }
3627
3628 VkResult radv_BindBufferMemory2(VkDevice device,
3629 uint32_t bindInfoCount,
3630 const VkBindBufferMemoryInfo *pBindInfos)
3631 {
3632 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3633 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3634 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3635
3636 if (mem) {
3637 buffer->bo = mem->bo;
3638 buffer->offset = pBindInfos[i].memoryOffset;
3639 } else {
3640 buffer->bo = NULL;
3641 }
3642 }
3643 return VK_SUCCESS;
3644 }
3645
3646 VkResult radv_BindBufferMemory(
3647 VkDevice device,
3648 VkBuffer buffer,
3649 VkDeviceMemory memory,
3650 VkDeviceSize memoryOffset)
3651 {
3652 const VkBindBufferMemoryInfo info = {
3653 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3654 .buffer = buffer,
3655 .memory = memory,
3656 .memoryOffset = memoryOffset
3657 };
3658
3659 return radv_BindBufferMemory2(device, 1, &info);
3660 }
3661
3662 VkResult radv_BindImageMemory2(VkDevice device,
3663 uint32_t bindInfoCount,
3664 const VkBindImageMemoryInfo *pBindInfos)
3665 {
3666 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3667 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3668 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3669
3670 if (mem) {
3671 image->bo = mem->bo;
3672 image->offset = pBindInfos[i].memoryOffset;
3673 } else {
3674 image->bo = NULL;
3675 image->offset = 0;
3676 }
3677 }
3678 return VK_SUCCESS;
3679 }
3680
3681
3682 VkResult radv_BindImageMemory(
3683 VkDevice device,
3684 VkImage image,
3685 VkDeviceMemory memory,
3686 VkDeviceSize memoryOffset)
3687 {
3688 const VkBindImageMemoryInfo info = {
3689 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3690 .image = image,
3691 .memory = memory,
3692 .memoryOffset = memoryOffset
3693 };
3694
3695 return radv_BindImageMemory2(device, 1, &info);
3696 }
3697
3698
3699 static void
3700 radv_sparse_buffer_bind_memory(struct radv_device *device,
3701 const VkSparseBufferMemoryBindInfo *bind)
3702 {
3703 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3704
3705 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3706 struct radv_device_memory *mem = NULL;
3707
3708 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3709 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3710
3711 device->ws->buffer_virtual_bind(buffer->bo,
3712 bind->pBinds[i].resourceOffset,
3713 bind->pBinds[i].size,
3714 mem ? mem->bo : NULL,
3715 bind->pBinds[i].memoryOffset);
3716 }
3717 }
3718
3719 static void
3720 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3721 const VkSparseImageOpaqueMemoryBindInfo *bind)
3722 {
3723 RADV_FROM_HANDLE(radv_image, image, bind->image);
3724
3725 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3726 struct radv_device_memory *mem = NULL;
3727
3728 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3729 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3730
3731 device->ws->buffer_virtual_bind(image->bo,
3732 bind->pBinds[i].resourceOffset,
3733 bind->pBinds[i].size,
3734 mem ? mem->bo : NULL,
3735 bind->pBinds[i].memoryOffset);
3736 }
3737 }
3738
3739 VkResult radv_QueueBindSparse(
3740 VkQueue _queue,
3741 uint32_t bindInfoCount,
3742 const VkBindSparseInfo* pBindInfo,
3743 VkFence _fence)
3744 {
3745 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3746 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3747 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3748 bool fence_emitted = false;
3749 VkResult result;
3750 int ret;
3751
3752 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3753 struct radv_winsys_sem_info sem_info;
3754 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3755 radv_sparse_buffer_bind_memory(queue->device,
3756 pBindInfo[i].pBufferBinds + j);
3757 }
3758
3759 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3760 radv_sparse_image_opaque_bind_memory(queue->device,
3761 pBindInfo[i].pImageOpaqueBinds + j);
3762 }
3763
3764 VkResult result;
3765 result = radv_alloc_sem_info(queue->device->instance,
3766 &sem_info,
3767 pBindInfo[i].waitSemaphoreCount,
3768 pBindInfo[i].pWaitSemaphores,
3769 pBindInfo[i].signalSemaphoreCount,
3770 pBindInfo[i].pSignalSemaphores,
3771 _fence);
3772 if (result != VK_SUCCESS)
3773 return result;
3774
3775 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3776 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3777 &queue->device->empty_cs[queue->queue_family_index],
3778 1, NULL, NULL,
3779 &sem_info, NULL,
3780 false, base_fence);
3781 if (ret) {
3782 radv_loge("failed to submit CS %d\n", i);
3783 abort();
3784 }
3785
3786 fence_emitted = true;
3787 }
3788
3789 radv_free_sem_info(&sem_info);
3790
3791 }
3792
3793 if (fence) {
3794 if (!fence_emitted) {
3795 result = radv_signal_fence(queue, fence);
3796 if (result != VK_SUCCESS)
3797 return result;
3798 }
3799 }
3800
3801 return VK_SUCCESS;
3802 }
3803
3804 VkResult radv_CreateFence(
3805 VkDevice _device,
3806 const VkFenceCreateInfo* pCreateInfo,
3807 const VkAllocationCallbacks* pAllocator,
3808 VkFence* pFence)
3809 {
3810 RADV_FROM_HANDLE(radv_device, device, _device);
3811 const VkExportFenceCreateInfo *export =
3812 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3813 VkExternalFenceHandleTypeFlags handleTypes =
3814 export ? export->handleTypes : 0;
3815
3816 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3817 sizeof(*fence), 8,
3818 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3819
3820 if (!fence)
3821 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3822
3823 fence->fence_wsi = NULL;
3824 fence->temp_syncobj = 0;
3825 if (device->always_use_syncobj || handleTypes) {
3826 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3827 if (ret) {
3828 vk_free2(&device->alloc, pAllocator, fence);
3829 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3830 }
3831 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3832 device->ws->signal_syncobj(device->ws, fence->syncobj);
3833 }
3834 fence->fence = NULL;
3835 } else {
3836 fence->fence = device->ws->create_fence();
3837 if (!fence->fence) {
3838 vk_free2(&device->alloc, pAllocator, fence);
3839 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3840 }
3841 fence->syncobj = 0;
3842 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3843 device->ws->signal_fence(fence->fence);
3844 }
3845
3846 *pFence = radv_fence_to_handle(fence);
3847
3848 return VK_SUCCESS;
3849 }
3850
3851 void radv_DestroyFence(
3852 VkDevice _device,
3853 VkFence _fence,
3854 const VkAllocationCallbacks* pAllocator)
3855 {
3856 RADV_FROM_HANDLE(radv_device, device, _device);
3857 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3858
3859 if (!fence)
3860 return;
3861
3862 if (fence->temp_syncobj)
3863 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3864 if (fence->syncobj)
3865 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3866 if (fence->fence)
3867 device->ws->destroy_fence(fence->fence);
3868 if (fence->fence_wsi)
3869 fence->fence_wsi->destroy(fence->fence_wsi);
3870 vk_free2(&device->alloc, pAllocator, fence);
3871 }
3872
3873
3874 uint64_t radv_get_current_time(void)
3875 {
3876 struct timespec tv;
3877 clock_gettime(CLOCK_MONOTONIC, &tv);
3878 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3879 }
3880
3881 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3882 {
3883 uint64_t current_time = radv_get_current_time();
3884
3885 timeout = MIN2(UINT64_MAX - current_time, timeout);
3886
3887 return current_time + timeout;
3888 }
3889
3890
3891 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3892 uint32_t fenceCount, const VkFence *pFences)
3893 {
3894 for (uint32_t i = 0; i < fenceCount; ++i) {
3895 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3896 if (fence->fence == NULL || fence->syncobj ||
3897 fence->temp_syncobj || fence->fence_wsi ||
3898 (!device->ws->is_fence_waitable(fence->fence)))
3899 return false;
3900 }
3901 return true;
3902 }
3903
3904 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3905 {
3906 for (uint32_t i = 0; i < fenceCount; ++i) {
3907 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3908 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3909 return false;
3910 }
3911 return true;
3912 }
3913
3914 VkResult radv_WaitForFences(
3915 VkDevice _device,
3916 uint32_t fenceCount,
3917 const VkFence* pFences,
3918 VkBool32 waitAll,
3919 uint64_t timeout)
3920 {
3921 RADV_FROM_HANDLE(radv_device, device, _device);
3922 timeout = radv_get_absolute_timeout(timeout);
3923
3924 if (device->always_use_syncobj &&
3925 radv_all_fences_syncobj(fenceCount, pFences))
3926 {
3927 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3928 if (!handles)
3929 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3930
3931 for (uint32_t i = 0; i < fenceCount; ++i) {
3932 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3933 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3934 }
3935
3936 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3937
3938 free(handles);
3939 return success ? VK_SUCCESS : VK_TIMEOUT;
3940 }
3941
3942 if (!waitAll && fenceCount > 1) {
3943 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3944 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3945 uint32_t wait_count = 0;
3946 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3947 if (!fences)
3948 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3949
3950 for (uint32_t i = 0; i < fenceCount; ++i) {
3951 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3952
3953 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3954 free(fences);
3955 return VK_SUCCESS;
3956 }
3957
3958 fences[wait_count++] = fence->fence;
3959 }
3960
3961 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3962 waitAll, timeout - radv_get_current_time());
3963
3964 free(fences);
3965 return success ? VK_SUCCESS : VK_TIMEOUT;
3966 }
3967
3968 while(radv_get_current_time() <= timeout) {
3969 for (uint32_t i = 0; i < fenceCount; ++i) {
3970 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3971 return VK_SUCCESS;
3972 }
3973 }
3974 return VK_TIMEOUT;
3975 }
3976
3977 for (uint32_t i = 0; i < fenceCount; ++i) {
3978 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3979 bool expired = false;
3980
3981 if (fence->temp_syncobj) {
3982 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3983 return VK_TIMEOUT;
3984 continue;
3985 }
3986
3987 if (fence->syncobj) {
3988 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3989 return VK_TIMEOUT;
3990 continue;
3991 }
3992
3993 if (fence->fence) {
3994 if (!device->ws->is_fence_waitable(fence->fence)) {
3995 while(!device->ws->is_fence_waitable(fence->fence) &&
3996 radv_get_current_time() <= timeout)
3997 /* Do nothing */;
3998 }
3999
4000 expired = device->ws->fence_wait(device->ws,
4001 fence->fence,
4002 true, timeout);
4003 if (!expired)
4004 return VK_TIMEOUT;
4005 }
4006
4007 if (fence->fence_wsi) {
4008 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4009 if (result != VK_SUCCESS)
4010 return result;
4011 }
4012 }
4013
4014 return VK_SUCCESS;
4015 }
4016
4017 VkResult radv_ResetFences(VkDevice _device,
4018 uint32_t fenceCount,
4019 const VkFence *pFences)
4020 {
4021 RADV_FROM_HANDLE(radv_device, device, _device);
4022
4023 for (unsigned i = 0; i < fenceCount; ++i) {
4024 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4025 if (fence->fence)
4026 device->ws->reset_fence(fence->fence);
4027
4028 /* Per spec, we first restore the permanent payload, and then reset, so
4029 * having a temp syncobj should not skip resetting the permanent syncobj. */
4030 if (fence->temp_syncobj) {
4031 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4032 fence->temp_syncobj = 0;
4033 }
4034
4035 if (fence->syncobj) {
4036 device->ws->reset_syncobj(device->ws, fence->syncobj);
4037 }
4038 }
4039
4040 return VK_SUCCESS;
4041 }
4042
4043 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4044 {
4045 RADV_FROM_HANDLE(radv_device, device, _device);
4046 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4047
4048 if (fence->temp_syncobj) {
4049 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4050 return success ? VK_SUCCESS : VK_NOT_READY;
4051 }
4052
4053 if (fence->syncobj) {
4054 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4055 return success ? VK_SUCCESS : VK_NOT_READY;
4056 }
4057
4058 if (fence->fence) {
4059 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4060 return VK_NOT_READY;
4061 }
4062 if (fence->fence_wsi) {
4063 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4064
4065 if (result != VK_SUCCESS) {
4066 if (result == VK_TIMEOUT)
4067 return VK_NOT_READY;
4068 return result;
4069 }
4070 }
4071 return VK_SUCCESS;
4072 }
4073
4074
4075 // Queue semaphore functions
4076
4077 VkResult radv_CreateSemaphore(
4078 VkDevice _device,
4079 const VkSemaphoreCreateInfo* pCreateInfo,
4080 const VkAllocationCallbacks* pAllocator,
4081 VkSemaphore* pSemaphore)
4082 {
4083 RADV_FROM_HANDLE(radv_device, device, _device);
4084 const VkExportSemaphoreCreateInfo *export =
4085 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4086 VkExternalSemaphoreHandleTypeFlags handleTypes =
4087 export ? export->handleTypes : 0;
4088
4089 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4090 sizeof(*sem), 8,
4091 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4092 if (!sem)
4093 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4094
4095 sem->temp_syncobj = 0;
4096 /* create a syncobject if we are going to export this semaphore */
4097 if (device->always_use_syncobj || handleTypes) {
4098 assert (device->physical_device->rad_info.has_syncobj);
4099 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4100 if (ret) {
4101 vk_free2(&device->alloc, pAllocator, sem);
4102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4103 }
4104 sem->sem = NULL;
4105 } else {
4106 sem->sem = device->ws->create_sem(device->ws);
4107 if (!sem->sem) {
4108 vk_free2(&device->alloc, pAllocator, sem);
4109 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4110 }
4111 sem->syncobj = 0;
4112 }
4113
4114 *pSemaphore = radv_semaphore_to_handle(sem);
4115 return VK_SUCCESS;
4116 }
4117
4118 void radv_DestroySemaphore(
4119 VkDevice _device,
4120 VkSemaphore _semaphore,
4121 const VkAllocationCallbacks* pAllocator)
4122 {
4123 RADV_FROM_HANDLE(radv_device, device, _device);
4124 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4125 if (!_semaphore)
4126 return;
4127
4128 if (sem->syncobj)
4129 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4130 else
4131 device->ws->destroy_sem(sem->sem);
4132 vk_free2(&device->alloc, pAllocator, sem);
4133 }
4134
4135 VkResult radv_CreateEvent(
4136 VkDevice _device,
4137 const VkEventCreateInfo* pCreateInfo,
4138 const VkAllocationCallbacks* pAllocator,
4139 VkEvent* pEvent)
4140 {
4141 RADV_FROM_HANDLE(radv_device, device, _device);
4142 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4143 sizeof(*event), 8,
4144 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4145
4146 if (!event)
4147 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4148
4149 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4150 RADEON_DOMAIN_GTT,
4151 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4152 RADV_BO_PRIORITY_FENCE);
4153 if (!event->bo) {
4154 vk_free2(&device->alloc, pAllocator, event);
4155 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4156 }
4157
4158 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4159
4160 *pEvent = radv_event_to_handle(event);
4161
4162 return VK_SUCCESS;
4163 }
4164
4165 void radv_DestroyEvent(
4166 VkDevice _device,
4167 VkEvent _event,
4168 const VkAllocationCallbacks* pAllocator)
4169 {
4170 RADV_FROM_HANDLE(radv_device, device, _device);
4171 RADV_FROM_HANDLE(radv_event, event, _event);
4172
4173 if (!event)
4174 return;
4175 device->ws->buffer_destroy(event->bo);
4176 vk_free2(&device->alloc, pAllocator, event);
4177 }
4178
4179 VkResult radv_GetEventStatus(
4180 VkDevice _device,
4181 VkEvent _event)
4182 {
4183 RADV_FROM_HANDLE(radv_event, event, _event);
4184
4185 if (*event->map == 1)
4186 return VK_EVENT_SET;
4187 return VK_EVENT_RESET;
4188 }
4189
4190 VkResult radv_SetEvent(
4191 VkDevice _device,
4192 VkEvent _event)
4193 {
4194 RADV_FROM_HANDLE(radv_event, event, _event);
4195 *event->map = 1;
4196
4197 return VK_SUCCESS;
4198 }
4199
4200 VkResult radv_ResetEvent(
4201 VkDevice _device,
4202 VkEvent _event)
4203 {
4204 RADV_FROM_HANDLE(radv_event, event, _event);
4205 *event->map = 0;
4206
4207 return VK_SUCCESS;
4208 }
4209
4210 VkResult radv_CreateBuffer(
4211 VkDevice _device,
4212 const VkBufferCreateInfo* pCreateInfo,
4213 const VkAllocationCallbacks* pAllocator,
4214 VkBuffer* pBuffer)
4215 {
4216 RADV_FROM_HANDLE(radv_device, device, _device);
4217 struct radv_buffer *buffer;
4218
4219 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4220
4221 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4223 if (buffer == NULL)
4224 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4225
4226 buffer->size = pCreateInfo->size;
4227 buffer->usage = pCreateInfo->usage;
4228 buffer->bo = NULL;
4229 buffer->offset = 0;
4230 buffer->flags = pCreateInfo->flags;
4231
4232 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4233 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4234
4235 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4236 buffer->bo = device->ws->buffer_create(device->ws,
4237 align64(buffer->size, 4096),
4238 4096, 0, RADEON_FLAG_VIRTUAL,
4239 RADV_BO_PRIORITY_VIRTUAL);
4240 if (!buffer->bo) {
4241 vk_free2(&device->alloc, pAllocator, buffer);
4242 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4243 }
4244 }
4245
4246 *pBuffer = radv_buffer_to_handle(buffer);
4247
4248 return VK_SUCCESS;
4249 }
4250
4251 void radv_DestroyBuffer(
4252 VkDevice _device,
4253 VkBuffer _buffer,
4254 const VkAllocationCallbacks* pAllocator)
4255 {
4256 RADV_FROM_HANDLE(radv_device, device, _device);
4257 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4258
4259 if (!buffer)
4260 return;
4261
4262 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4263 device->ws->buffer_destroy(buffer->bo);
4264
4265 vk_free2(&device->alloc, pAllocator, buffer);
4266 }
4267
4268 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4269 VkDevice device,
4270 const VkBufferDeviceAddressInfoEXT* pInfo)
4271 {
4272 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4273 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4274 }
4275
4276
4277 static inline unsigned
4278 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4279 {
4280 if (stencil)
4281 return plane->surface.u.legacy.stencil_tiling_index[level];
4282 else
4283 return plane->surface.u.legacy.tiling_index[level];
4284 }
4285
4286 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4287 {
4288 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4289 }
4290
4291 static uint32_t
4292 radv_init_dcc_control_reg(struct radv_device *device,
4293 struct radv_image_view *iview)
4294 {
4295 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4296 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4297 unsigned max_compressed_block_size;
4298 unsigned independent_128b_blocks;
4299 unsigned independent_64b_blocks;
4300
4301 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4302 return 0;
4303
4304 if (!device->physical_device->rad_info.has_dedicated_vram) {
4305 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4306 * dGPU and 64 for APU because all of our APUs to date use
4307 * DIMMs which have a request granularity size of 64B while all
4308 * other chips have a 32B request size.
4309 */
4310 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4311 }
4312
4313 if (device->physical_device->rad_info.chip_class >= GFX10) {
4314 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4315 independent_64b_blocks = 0;
4316 independent_128b_blocks = 1;
4317 } else {
4318 independent_128b_blocks = 0;
4319
4320 if (iview->image->info.samples > 1) {
4321 if (iview->image->planes[0].surface.bpe == 1)
4322 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4323 else if (iview->image->planes[0].surface.bpe == 2)
4324 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4325 }
4326
4327 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4328 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4329 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4330 /* If this DCC image is potentially going to be used in texture
4331 * fetches, we need some special settings.
4332 */
4333 independent_64b_blocks = 1;
4334 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4335 } else {
4336 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4337 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4338 * big as possible for better compression state.
4339 */
4340 independent_64b_blocks = 0;
4341 max_compressed_block_size = max_uncompressed_block_size;
4342 }
4343 }
4344
4345 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4346 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4347 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4348 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4349 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4350 }
4351
4352 static void
4353 radv_initialise_color_surface(struct radv_device *device,
4354 struct radv_color_buffer_info *cb,
4355 struct radv_image_view *iview)
4356 {
4357 const struct vk_format_description *desc;
4358 unsigned ntype, format, swap, endian;
4359 unsigned blend_clamp = 0, blend_bypass = 0;
4360 uint64_t va;
4361 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4362 const struct radeon_surf *surf = &plane->surface;
4363
4364 desc = vk_format_description(iview->vk_format);
4365
4366 memset(cb, 0, sizeof(*cb));
4367
4368 /* Intensity is implemented as Red, so treat it that way. */
4369 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4370
4371 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4372
4373 cb->cb_color_base = va >> 8;
4374
4375 if (device->physical_device->rad_info.chip_class >= GFX9) {
4376 struct gfx9_surf_meta_flags meta;
4377 if (iview->image->dcc_offset)
4378 meta = surf->u.gfx9.dcc;
4379 else
4380 meta = surf->u.gfx9.cmask;
4381
4382 if (device->physical_device->rad_info.chip_class >= GFX10) {
4383 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4384 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4385 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4386 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4387 } else {
4388 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4389 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4390 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4391 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4392 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4393 }
4394
4395 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4396 cb->cb_color_base |= surf->tile_swizzle;
4397 } else {
4398 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4399 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4400
4401 cb->cb_color_base += level_info->offset >> 8;
4402 if (level_info->mode == RADEON_SURF_MODE_2D)
4403 cb->cb_color_base |= surf->tile_swizzle;
4404
4405 pitch_tile_max = level_info->nblk_x / 8 - 1;
4406 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4407 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4408
4409 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4410 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4411 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4412
4413 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4414
4415 if (radv_image_has_fmask(iview->image)) {
4416 if (device->physical_device->rad_info.chip_class >= GFX7)
4417 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4418 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4419 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4420 } else {
4421 /* This must be set for fast clear to work without FMASK. */
4422 if (device->physical_device->rad_info.chip_class >= GFX7)
4423 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4424 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4425 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4426 }
4427 }
4428
4429 /* CMASK variables */
4430 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4431 va += iview->image->cmask.offset;
4432 cb->cb_color_cmask = va >> 8;
4433
4434 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4435 va += iview->image->dcc_offset;
4436
4437 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4438 device->physical_device->rad_info.chip_class <= GFX8)
4439 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4440
4441 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4442 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4443
4444 cb->cb_dcc_base = va >> 8;
4445 cb->cb_dcc_base |= dcc_tile_swizzle;
4446
4447 /* GFX10 field has the same base shift as the GFX6 field. */
4448 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4449 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4450 S_028C6C_SLICE_MAX_GFX10(max_slice);
4451
4452 if (iview->image->info.samples > 1) {
4453 unsigned log_samples = util_logbase2(iview->image->info.samples);
4454
4455 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4456 S_028C74_NUM_FRAGMENTS(log_samples);
4457 }
4458
4459 if (radv_image_has_fmask(iview->image)) {
4460 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4461 cb->cb_color_fmask = va >> 8;
4462 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4463 } else {
4464 cb->cb_color_fmask = cb->cb_color_base;
4465 }
4466
4467 ntype = radv_translate_color_numformat(iview->vk_format,
4468 desc,
4469 vk_format_get_first_non_void_channel(iview->vk_format));
4470 format = radv_translate_colorformat(iview->vk_format);
4471 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4472 radv_finishme("Illegal color\n");
4473 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4474 endian = radv_colorformat_endian_swap(format);
4475
4476 /* blend clamp should be set for all NORM/SRGB types */
4477 if (ntype == V_028C70_NUMBER_UNORM ||
4478 ntype == V_028C70_NUMBER_SNORM ||
4479 ntype == V_028C70_NUMBER_SRGB)
4480 blend_clamp = 1;
4481
4482 /* set blend bypass according to docs if SINT/UINT or
4483 8/24 COLOR variants */
4484 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4485 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4486 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4487 blend_clamp = 0;
4488 blend_bypass = 1;
4489 }
4490 #if 0
4491 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4492 (format == V_028C70_COLOR_8 ||
4493 format == V_028C70_COLOR_8_8 ||
4494 format == V_028C70_COLOR_8_8_8_8))
4495 ->color_is_int8 = true;
4496 #endif
4497 cb->cb_color_info = S_028C70_FORMAT(format) |
4498 S_028C70_COMP_SWAP(swap) |
4499 S_028C70_BLEND_CLAMP(blend_clamp) |
4500 S_028C70_BLEND_BYPASS(blend_bypass) |
4501 S_028C70_SIMPLE_FLOAT(1) |
4502 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4503 ntype != V_028C70_NUMBER_SNORM &&
4504 ntype != V_028C70_NUMBER_SRGB &&
4505 format != V_028C70_COLOR_8_24 &&
4506 format != V_028C70_COLOR_24_8) |
4507 S_028C70_NUMBER_TYPE(ntype) |
4508 S_028C70_ENDIAN(endian);
4509 if (radv_image_has_fmask(iview->image)) {
4510 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4511 if (device->physical_device->rad_info.chip_class == GFX6) {
4512 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4513 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4514 }
4515
4516 if (radv_image_is_tc_compat_cmask(iview->image)) {
4517 /* Allow the texture block to read FMASK directly
4518 * without decompressing it. This bit must be cleared
4519 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4520 * otherwise the operation doesn't happen.
4521 */
4522 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4523
4524 /* Set CMASK into a tiling format that allows the
4525 * texture block to read it.
4526 */
4527 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4528 }
4529 }
4530
4531 if (radv_image_has_cmask(iview->image) &&
4532 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4533 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4534
4535 if (radv_dcc_enabled(iview->image, iview->base_mip))
4536 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4537
4538 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4539
4540 /* This must be set for fast clear to work without FMASK. */
4541 if (!radv_image_has_fmask(iview->image) &&
4542 device->physical_device->rad_info.chip_class == GFX6) {
4543 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4544 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4545 }
4546
4547 if (device->physical_device->rad_info.chip_class >= GFX9) {
4548 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4549
4550 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4551 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4552 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4553 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4554
4555 if (device->physical_device->rad_info.chip_class >= GFX10) {
4556 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4557
4558 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4559 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4560 S_028EE0_RESOURCE_LEVEL(1);
4561 } else {
4562 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4563 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4564 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4565 }
4566
4567 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4568 S_028C68_MIP0_HEIGHT(height - 1) |
4569 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4570 }
4571 }
4572
4573 static unsigned
4574 radv_calc_decompress_on_z_planes(struct radv_device *device,
4575 struct radv_image_view *iview)
4576 {
4577 unsigned max_zplanes = 0;
4578
4579 assert(radv_image_is_tc_compat_htile(iview->image));
4580
4581 if (device->physical_device->rad_info.chip_class >= GFX9) {
4582 /* Default value for 32-bit depth surfaces. */
4583 max_zplanes = 4;
4584
4585 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4586 iview->image->info.samples > 1)
4587 max_zplanes = 2;
4588
4589 max_zplanes = max_zplanes + 1;
4590 } else {
4591 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4592 /* Do not enable Z plane compression for 16-bit depth
4593 * surfaces because isn't supported on GFX8. Only
4594 * 32-bit depth surfaces are supported by the hardware.
4595 * This allows to maintain shader compatibility and to
4596 * reduce the number of depth decompressions.
4597 */
4598 max_zplanes = 1;
4599 } else {
4600 if (iview->image->info.samples <= 1)
4601 max_zplanes = 5;
4602 else if (iview->image->info.samples <= 4)
4603 max_zplanes = 3;
4604 else
4605 max_zplanes = 2;
4606 }
4607 }
4608
4609 return max_zplanes;
4610 }
4611
4612 static void
4613 radv_initialise_ds_surface(struct radv_device *device,
4614 struct radv_ds_buffer_info *ds,
4615 struct radv_image_view *iview)
4616 {
4617 unsigned level = iview->base_mip;
4618 unsigned format, stencil_format;
4619 uint64_t va, s_offs, z_offs;
4620 bool stencil_only = false;
4621 const struct radv_image_plane *plane = &iview->image->planes[0];
4622 const struct radeon_surf *surf = &plane->surface;
4623
4624 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4625
4626 memset(ds, 0, sizeof(*ds));
4627 switch (iview->image->vk_format) {
4628 case VK_FORMAT_D24_UNORM_S8_UINT:
4629 case VK_FORMAT_X8_D24_UNORM_PACK32:
4630 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4631 ds->offset_scale = 2.0f;
4632 break;
4633 case VK_FORMAT_D16_UNORM:
4634 case VK_FORMAT_D16_UNORM_S8_UINT:
4635 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4636 ds->offset_scale = 4.0f;
4637 break;
4638 case VK_FORMAT_D32_SFLOAT:
4639 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4640 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4641 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4642 ds->offset_scale = 1.0f;
4643 break;
4644 case VK_FORMAT_S8_UINT:
4645 stencil_only = true;
4646 break;
4647 default:
4648 break;
4649 }
4650
4651 format = radv_translate_dbformat(iview->image->vk_format);
4652 stencil_format = surf->has_stencil ?
4653 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4654
4655 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4656 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4657 S_028008_SLICE_MAX(max_slice);
4658 if (device->physical_device->rad_info.chip_class >= GFX10) {
4659 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4660 S_028008_SLICE_MAX_HI(max_slice >> 11);
4661 }
4662
4663 ds->db_htile_data_base = 0;
4664 ds->db_htile_surface = 0;
4665
4666 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4667 s_offs = z_offs = va;
4668
4669 if (device->physical_device->rad_info.chip_class >= GFX9) {
4670 assert(surf->u.gfx9.surf_offset == 0);
4671 s_offs += surf->u.gfx9.stencil_offset;
4672
4673 ds->db_z_info = S_028038_FORMAT(format) |
4674 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4675 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4676 S_028038_MAXMIP(iview->image->info.levels - 1) |
4677 S_028038_ZRANGE_PRECISION(1);
4678 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4679 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4680
4681 if (device->physical_device->rad_info.chip_class == GFX9) {
4682 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4683 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4684 }
4685
4686 ds->db_depth_view |= S_028008_MIPID(level);
4687 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4688 S_02801C_Y_MAX(iview->image->info.height - 1);
4689
4690 if (radv_htile_enabled(iview->image, level)) {
4691 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4692
4693 if (radv_image_is_tc_compat_htile(iview->image)) {
4694 unsigned max_zplanes =
4695 radv_calc_decompress_on_z_planes(device, iview);
4696
4697 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4698
4699 if (device->physical_device->rad_info.chip_class >= GFX10) {
4700 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4701 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4702 } else {
4703 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4704 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4705 }
4706 }
4707
4708 if (!surf->has_stencil)
4709 /* Use all of the htile_buffer for depth if there's no stencil. */
4710 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4711 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4712 iview->image->htile_offset;
4713 ds->db_htile_data_base = va >> 8;
4714 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4715 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4716
4717 if (device->physical_device->rad_info.chip_class == GFX9) {
4718 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4719 }
4720 }
4721 } else {
4722 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4723
4724 if (stencil_only)
4725 level_info = &surf->u.legacy.stencil_level[level];
4726
4727 z_offs += surf->u.legacy.level[level].offset;
4728 s_offs += surf->u.legacy.stencil_level[level].offset;
4729
4730 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4731 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4732 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4733
4734 if (iview->image->info.samples > 1)
4735 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4736
4737 if (device->physical_device->rad_info.chip_class >= GFX7) {
4738 struct radeon_info *info = &device->physical_device->rad_info;
4739 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4740 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4741 unsigned macro_index = surf->u.legacy.macro_tile_index;
4742 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4743 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4744 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4745
4746 if (stencil_only)
4747 tile_mode = stencil_tile_mode;
4748
4749 ds->db_depth_info |=
4750 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4751 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4752 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4753 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4754 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4755 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4756 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4757 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4758 } else {
4759 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4760 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4761 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4762 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4763 if (stencil_only)
4764 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4765 }
4766
4767 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4768 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4769 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4770
4771 if (radv_htile_enabled(iview->image, level)) {
4772 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4773
4774 if (!surf->has_stencil &&
4775 !radv_image_is_tc_compat_htile(iview->image))
4776 /* Use all of the htile_buffer for depth if there's no stencil. */
4777 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4778
4779 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4780 iview->image->htile_offset;
4781 ds->db_htile_data_base = va >> 8;
4782 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4783
4784 if (radv_image_is_tc_compat_htile(iview->image)) {
4785 unsigned max_zplanes =
4786 radv_calc_decompress_on_z_planes(device, iview);
4787
4788 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4789 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4790 }
4791 }
4792 }
4793
4794 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4795 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4796 }
4797
4798 VkResult radv_CreateFramebuffer(
4799 VkDevice _device,
4800 const VkFramebufferCreateInfo* pCreateInfo,
4801 const VkAllocationCallbacks* pAllocator,
4802 VkFramebuffer* pFramebuffer)
4803 {
4804 RADV_FROM_HANDLE(radv_device, device, _device);
4805 struct radv_framebuffer *framebuffer;
4806
4807 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4808
4809 size_t size = sizeof(*framebuffer) +
4810 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4811 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4812 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4813 if (framebuffer == NULL)
4814 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4815
4816 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4817 framebuffer->width = pCreateInfo->width;
4818 framebuffer->height = pCreateInfo->height;
4819 framebuffer->layers = pCreateInfo->layers;
4820 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4821 VkImageView _iview = pCreateInfo->pAttachments[i];
4822 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4823 framebuffer->attachments[i].attachment = iview;
4824 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4825 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4826 } else {
4827 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4828 }
4829 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4830 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4831 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4832 }
4833
4834 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4835 return VK_SUCCESS;
4836 }
4837
4838 void radv_DestroyFramebuffer(
4839 VkDevice _device,
4840 VkFramebuffer _fb,
4841 const VkAllocationCallbacks* pAllocator)
4842 {
4843 RADV_FROM_HANDLE(radv_device, device, _device);
4844 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4845
4846 if (!fb)
4847 return;
4848 vk_free2(&device->alloc, pAllocator, fb);
4849 }
4850
4851 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4852 {
4853 switch (address_mode) {
4854 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4855 return V_008F30_SQ_TEX_WRAP;
4856 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4857 return V_008F30_SQ_TEX_MIRROR;
4858 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4859 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4860 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4861 return V_008F30_SQ_TEX_CLAMP_BORDER;
4862 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4863 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4864 default:
4865 unreachable("illegal tex wrap mode");
4866 break;
4867 }
4868 }
4869
4870 static unsigned
4871 radv_tex_compare(VkCompareOp op)
4872 {
4873 switch (op) {
4874 case VK_COMPARE_OP_NEVER:
4875 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4876 case VK_COMPARE_OP_LESS:
4877 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4878 case VK_COMPARE_OP_EQUAL:
4879 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4880 case VK_COMPARE_OP_LESS_OR_EQUAL:
4881 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4882 case VK_COMPARE_OP_GREATER:
4883 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4884 case VK_COMPARE_OP_NOT_EQUAL:
4885 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4886 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4887 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4888 case VK_COMPARE_OP_ALWAYS:
4889 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4890 default:
4891 unreachable("illegal compare mode");
4892 break;
4893 }
4894 }
4895
4896 static unsigned
4897 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4898 {
4899 switch (filter) {
4900 case VK_FILTER_NEAREST:
4901 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4902 V_008F38_SQ_TEX_XY_FILTER_POINT);
4903 case VK_FILTER_LINEAR:
4904 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4905 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4906 case VK_FILTER_CUBIC_IMG:
4907 default:
4908 fprintf(stderr, "illegal texture filter");
4909 return 0;
4910 }
4911 }
4912
4913 static unsigned
4914 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4915 {
4916 switch (mode) {
4917 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4918 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4919 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4920 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4921 default:
4922 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4923 }
4924 }
4925
4926 static unsigned
4927 radv_tex_bordercolor(VkBorderColor bcolor)
4928 {
4929 switch (bcolor) {
4930 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4931 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4932 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4933 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4934 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4935 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4936 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4937 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4938 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4939 default:
4940 break;
4941 }
4942 return 0;
4943 }
4944
4945 static unsigned
4946 radv_tex_aniso_filter(unsigned filter)
4947 {
4948 if (filter < 2)
4949 return 0;
4950 if (filter < 4)
4951 return 1;
4952 if (filter < 8)
4953 return 2;
4954 if (filter < 16)
4955 return 3;
4956 return 4;
4957 }
4958
4959 static unsigned
4960 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4961 {
4962 switch (mode) {
4963 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4964 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4965 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4966 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4967 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4968 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4969 default:
4970 break;
4971 }
4972 return 0;
4973 }
4974
4975 static uint32_t
4976 radv_get_max_anisotropy(struct radv_device *device,
4977 const VkSamplerCreateInfo *pCreateInfo)
4978 {
4979 if (device->force_aniso >= 0)
4980 return device->force_aniso;
4981
4982 if (pCreateInfo->anisotropyEnable &&
4983 pCreateInfo->maxAnisotropy > 1.0f)
4984 return (uint32_t)pCreateInfo->maxAnisotropy;
4985
4986 return 0;
4987 }
4988
4989 static void
4990 radv_init_sampler(struct radv_device *device,
4991 struct radv_sampler *sampler,
4992 const VkSamplerCreateInfo *pCreateInfo)
4993 {
4994 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4995 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4996 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4997 device->physical_device->rad_info.chip_class == GFX9;
4998 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4999
5000 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5001 vk_find_struct_const(pCreateInfo->pNext,
5002 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5003 if (sampler_reduction)
5004 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5005
5006 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5007 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5008 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5009 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5010 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5011 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5012 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5013 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5014 S_008F30_DISABLE_CUBE_WRAP(0) |
5015 S_008F30_COMPAT_MODE(compat_mode) |
5016 S_008F30_FILTER_MODE(filter_mode));
5017 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5018 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5019 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5020 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5021 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5022 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5023 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5024 S_008F38_MIP_POINT_PRECLAMP(0));
5025 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5026 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5027
5028 if (device->physical_device->rad_info.chip_class >= GFX10) {
5029 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5030 } else {
5031 sampler->state[2] |=
5032 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5033 S_008F38_FILTER_PREC_FIX(1) |
5034 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5035 }
5036 }
5037
5038 VkResult radv_CreateSampler(
5039 VkDevice _device,
5040 const VkSamplerCreateInfo* pCreateInfo,
5041 const VkAllocationCallbacks* pAllocator,
5042 VkSampler* pSampler)
5043 {
5044 RADV_FROM_HANDLE(radv_device, device, _device);
5045 struct radv_sampler *sampler;
5046
5047 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5048 vk_find_struct_const(pCreateInfo->pNext,
5049 SAMPLER_YCBCR_CONVERSION_INFO);
5050
5051 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5052
5053 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5054 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5055 if (!sampler)
5056 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5057
5058 radv_init_sampler(device, sampler, pCreateInfo);
5059
5060 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5061 *pSampler = radv_sampler_to_handle(sampler);
5062
5063 return VK_SUCCESS;
5064 }
5065
5066 void radv_DestroySampler(
5067 VkDevice _device,
5068 VkSampler _sampler,
5069 const VkAllocationCallbacks* pAllocator)
5070 {
5071 RADV_FROM_HANDLE(radv_device, device, _device);
5072 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5073
5074 if (!sampler)
5075 return;
5076 vk_free2(&device->alloc, pAllocator, sampler);
5077 }
5078
5079 /* vk_icd.h does not declare this function, so we declare it here to
5080 * suppress Wmissing-prototypes.
5081 */
5082 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5083 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5084
5085 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5086 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5087 {
5088 /* For the full details on loader interface versioning, see
5089 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5090 * What follows is a condensed summary, to help you navigate the large and
5091 * confusing official doc.
5092 *
5093 * - Loader interface v0 is incompatible with later versions. We don't
5094 * support it.
5095 *
5096 * - In loader interface v1:
5097 * - The first ICD entrypoint called by the loader is
5098 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5099 * entrypoint.
5100 * - The ICD must statically expose no other Vulkan symbol unless it is
5101 * linked with -Bsymbolic.
5102 * - Each dispatchable Vulkan handle created by the ICD must be
5103 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5104 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5105 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5106 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5107 * such loader-managed surfaces.
5108 *
5109 * - Loader interface v2 differs from v1 in:
5110 * - The first ICD entrypoint called by the loader is
5111 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5112 * statically expose this entrypoint.
5113 *
5114 * - Loader interface v3 differs from v2 in:
5115 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5116 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5117 * because the loader no longer does so.
5118 */
5119 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5120 return VK_SUCCESS;
5121 }
5122
5123 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5124 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5125 int *pFD)
5126 {
5127 RADV_FROM_HANDLE(radv_device, device, _device);
5128 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5129
5130 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5131
5132 /* At the moment, we support only the below handle types. */
5133 assert(pGetFdInfo->handleType ==
5134 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5135 pGetFdInfo->handleType ==
5136 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5137
5138 bool ret = radv_get_memory_fd(device, memory, pFD);
5139 if (ret == false)
5140 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5141 return VK_SUCCESS;
5142 }
5143
5144 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5145 VkExternalMemoryHandleTypeFlagBits handleType,
5146 int fd,
5147 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5148 {
5149 RADV_FROM_HANDLE(radv_device, device, _device);
5150
5151 switch (handleType) {
5152 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5153 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5154 return VK_SUCCESS;
5155
5156 default:
5157 /* The valid usage section for this function says:
5158 *
5159 * "handleType must not be one of the handle types defined as
5160 * opaque."
5161 *
5162 * So opaque handle types fall into the default "unsupported" case.
5163 */
5164 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5165 }
5166 }
5167
5168 static VkResult radv_import_opaque_fd(struct radv_device *device,
5169 int fd,
5170 uint32_t *syncobj)
5171 {
5172 uint32_t syncobj_handle = 0;
5173 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5174 if (ret != 0)
5175 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5176
5177 if (*syncobj)
5178 device->ws->destroy_syncobj(device->ws, *syncobj);
5179
5180 *syncobj = syncobj_handle;
5181 close(fd);
5182
5183 return VK_SUCCESS;
5184 }
5185
5186 static VkResult radv_import_sync_fd(struct radv_device *device,
5187 int fd,
5188 uint32_t *syncobj)
5189 {
5190 /* If we create a syncobj we do it locally so that if we have an error, we don't
5191 * leave a syncobj in an undetermined state in the fence. */
5192 uint32_t syncobj_handle = *syncobj;
5193 if (!syncobj_handle) {
5194 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5195 if (ret) {
5196 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5197 }
5198 }
5199
5200 if (fd == -1) {
5201 device->ws->signal_syncobj(device->ws, syncobj_handle);
5202 } else {
5203 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5204 if (ret != 0)
5205 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5206 }
5207
5208 *syncobj = syncobj_handle;
5209 if (fd != -1)
5210 close(fd);
5211
5212 return VK_SUCCESS;
5213 }
5214
5215 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5216 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5217 {
5218 RADV_FROM_HANDLE(radv_device, device, _device);
5219 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5220 uint32_t *syncobj_dst = NULL;
5221
5222 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5223 syncobj_dst = &sem->temp_syncobj;
5224 } else {
5225 syncobj_dst = &sem->syncobj;
5226 }
5227
5228 switch(pImportSemaphoreFdInfo->handleType) {
5229 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5230 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5231 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5232 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5233 default:
5234 unreachable("Unhandled semaphore handle type");
5235 }
5236 }
5237
5238 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5239 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5240 int *pFd)
5241 {
5242 RADV_FROM_HANDLE(radv_device, device, _device);
5243 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5244 int ret;
5245 uint32_t syncobj_handle;
5246
5247 if (sem->temp_syncobj)
5248 syncobj_handle = sem->temp_syncobj;
5249 else
5250 syncobj_handle = sem->syncobj;
5251
5252 switch(pGetFdInfo->handleType) {
5253 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5254 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5255 break;
5256 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5257 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5258 if (!ret) {
5259 if (sem->temp_syncobj) {
5260 close (sem->temp_syncobj);
5261 sem->temp_syncobj = 0;
5262 } else {
5263 device->ws->reset_syncobj(device->ws, syncobj_handle);
5264 }
5265 }
5266 break;
5267 default:
5268 unreachable("Unhandled semaphore handle type");
5269 }
5270
5271 if (ret)
5272 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5273 return VK_SUCCESS;
5274 }
5275
5276 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5277 VkPhysicalDevice physicalDevice,
5278 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5279 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5280 {
5281 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5282
5283 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5284 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5285 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5286 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5287 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5288 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5289 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5290 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5291 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5292 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5293 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5294 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5295 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5296 } else {
5297 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5298 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5299 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5300 }
5301 }
5302
5303 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5304 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5305 {
5306 RADV_FROM_HANDLE(radv_device, device, _device);
5307 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5308 uint32_t *syncobj_dst = NULL;
5309
5310
5311 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5312 syncobj_dst = &fence->temp_syncobj;
5313 } else {
5314 syncobj_dst = &fence->syncobj;
5315 }
5316
5317 switch(pImportFenceFdInfo->handleType) {
5318 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5319 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5320 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5321 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5322 default:
5323 unreachable("Unhandled fence handle type");
5324 }
5325 }
5326
5327 VkResult radv_GetFenceFdKHR(VkDevice _device,
5328 const VkFenceGetFdInfoKHR *pGetFdInfo,
5329 int *pFd)
5330 {
5331 RADV_FROM_HANDLE(radv_device, device, _device);
5332 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5333 int ret;
5334 uint32_t syncobj_handle;
5335
5336 if (fence->temp_syncobj)
5337 syncobj_handle = fence->temp_syncobj;
5338 else
5339 syncobj_handle = fence->syncobj;
5340
5341 switch(pGetFdInfo->handleType) {
5342 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5343 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5344 break;
5345 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5346 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5347 if (!ret) {
5348 if (fence->temp_syncobj) {
5349 close (fence->temp_syncobj);
5350 fence->temp_syncobj = 0;
5351 } else {
5352 device->ws->reset_syncobj(device->ws, syncobj_handle);
5353 }
5354 }
5355 break;
5356 default:
5357 unreachable("Unhandled fence handle type");
5358 }
5359
5360 if (ret)
5361 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5362 return VK_SUCCESS;
5363 }
5364
5365 void radv_GetPhysicalDeviceExternalFenceProperties(
5366 VkPhysicalDevice physicalDevice,
5367 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5368 VkExternalFenceProperties *pExternalFenceProperties)
5369 {
5370 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5371
5372 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5373 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5374 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5375 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5376 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5377 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5378 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5379 } else {
5380 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5381 pExternalFenceProperties->compatibleHandleTypes = 0;
5382 pExternalFenceProperties->externalFenceFeatures = 0;
5383 }
5384 }
5385
5386 VkResult
5387 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5388 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5389 const VkAllocationCallbacks* pAllocator,
5390 VkDebugReportCallbackEXT* pCallback)
5391 {
5392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5393 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5394 pCreateInfo, pAllocator, &instance->alloc,
5395 pCallback);
5396 }
5397
5398 void
5399 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5400 VkDebugReportCallbackEXT _callback,
5401 const VkAllocationCallbacks* pAllocator)
5402 {
5403 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5404 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5405 _callback, pAllocator, &instance->alloc);
5406 }
5407
5408 void
5409 radv_DebugReportMessageEXT(VkInstance _instance,
5410 VkDebugReportFlagsEXT flags,
5411 VkDebugReportObjectTypeEXT objectType,
5412 uint64_t object,
5413 size_t location,
5414 int32_t messageCode,
5415 const char* pLayerPrefix,
5416 const char* pMessage)
5417 {
5418 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5419 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5420 object, location, messageCode, pLayerPrefix, pMessage);
5421 }
5422
5423 void
5424 radv_GetDeviceGroupPeerMemoryFeatures(
5425 VkDevice device,
5426 uint32_t heapIndex,
5427 uint32_t localDeviceIndex,
5428 uint32_t remoteDeviceIndex,
5429 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5430 {
5431 assert(localDeviceIndex == remoteDeviceIndex);
5432
5433 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5434 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5435 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5436 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5437 }
5438
5439 static const VkTimeDomainEXT radv_time_domains[] = {
5440 VK_TIME_DOMAIN_DEVICE_EXT,
5441 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5442 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5443 };
5444
5445 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5446 VkPhysicalDevice physicalDevice,
5447 uint32_t *pTimeDomainCount,
5448 VkTimeDomainEXT *pTimeDomains)
5449 {
5450 int d;
5451 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5452
5453 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5454 vk_outarray_append(&out, i) {
5455 *i = radv_time_domains[d];
5456 }
5457 }
5458
5459 return vk_outarray_status(&out);
5460 }
5461
5462 static uint64_t
5463 radv_clock_gettime(clockid_t clock_id)
5464 {
5465 struct timespec current;
5466 int ret;
5467
5468 ret = clock_gettime(clock_id, &current);
5469 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5470 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5471 if (ret < 0)
5472 return 0;
5473
5474 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5475 }
5476
5477 VkResult radv_GetCalibratedTimestampsEXT(
5478 VkDevice _device,
5479 uint32_t timestampCount,
5480 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5481 uint64_t *pTimestamps,
5482 uint64_t *pMaxDeviation)
5483 {
5484 RADV_FROM_HANDLE(radv_device, device, _device);
5485 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5486 int d;
5487 uint64_t begin, end;
5488 uint64_t max_clock_period = 0;
5489
5490 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5491
5492 for (d = 0; d < timestampCount; d++) {
5493 switch (pTimestampInfos[d].timeDomain) {
5494 case VK_TIME_DOMAIN_DEVICE_EXT:
5495 pTimestamps[d] = device->ws->query_value(device->ws,
5496 RADEON_TIMESTAMP);
5497 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5498 max_clock_period = MAX2(max_clock_period, device_period);
5499 break;
5500 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5501 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5502 max_clock_period = MAX2(max_clock_period, 1);
5503 break;
5504
5505 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5506 pTimestamps[d] = begin;
5507 break;
5508 default:
5509 pTimestamps[d] = 0;
5510 break;
5511 }
5512 }
5513
5514 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5515
5516 /*
5517 * The maximum deviation is the sum of the interval over which we
5518 * perform the sampling and the maximum period of any sampled
5519 * clock. That's because the maximum skew between any two sampled
5520 * clock edges is when the sampled clock with the largest period is
5521 * sampled at the end of that period but right at the beginning of the
5522 * sampling interval and some other clock is sampled right at the
5523 * begining of its sampling period and right at the end of the
5524 * sampling interval. Let's assume the GPU has the longest clock
5525 * period and that the application is sampling GPU and monotonic:
5526 *
5527 * s e
5528 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5529 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5530 *
5531 * g
5532 * 0 1 2 3
5533 * GPU -----_____-----_____-----_____-----_____
5534 *
5535 * m
5536 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5537 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5538 *
5539 * Interval <----------------->
5540 * Deviation <-------------------------->
5541 *
5542 * s = read(raw) 2
5543 * g = read(GPU) 1
5544 * m = read(monotonic) 2
5545 * e = read(raw) b
5546 *
5547 * We round the sample interval up by one tick to cover sampling error
5548 * in the interval clock
5549 */
5550
5551 uint64_t sample_interval = end - begin + 1;
5552
5553 *pMaxDeviation = sample_interval + max_clock_period;
5554
5555 return VK_SUCCESS;
5556 }
5557
5558 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5559 VkPhysicalDevice physicalDevice,
5560 VkSampleCountFlagBits samples,
5561 VkMultisamplePropertiesEXT* pMultisampleProperties)
5562 {
5563 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5564 VK_SAMPLE_COUNT_4_BIT |
5565 VK_SAMPLE_COUNT_8_BIT)) {
5566 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5567 } else {
5568 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5569 }
5570 }