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radv: handle queue submission with no cs but semaphores
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "util/strtod.h"
37
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable;
48
49 static int
50 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
51 {
52 Dl_info info;
53 struct stat st;
54 if (!dladdr(ptr, &info) || !info.dli_fname) {
55 return -1;
56 }
57 if (stat(info.dli_fname, &st)) {
58 return -1;
59 }
60 *timestamp = st.st_mtim.tv_sec;
61 return 0;
62 }
63
64 static int
65 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
66 {
67 uint32_t mesa_timestamp, llvm_timestamp;
68 uint16_t f = family;
69 memset(uuid, 0, VK_UUID_SIZE);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
72 return -1;
73
74 memcpy(uuid, &mesa_timestamp, 4);
75 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
76 memcpy((char*)uuid + 8, &f, 2);
77 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
78 return 0;
79 }
80
81 static const VkExtensionProperties instance_extensions[] = {
82 {
83 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
84 .specVersion = 25,
85 },
86 #ifdef VK_USE_PLATFORM_XCB_KHR
87 {
88 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
89 .specVersion = 6,
90 },
91 #endif
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
93 {
94 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
95 .specVersion = 6,
96 },
97 #endif
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
99 {
100 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
101 .specVersion = 5,
102 },
103 #endif
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
117 .specVersion = 68,
118 },
119 {
120 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 };
132
133 static VkResult
134 radv_extensions_register(struct radv_instance *instance,
135 struct radv_extensions *extensions,
136 const VkExtensionProperties *new_ext,
137 uint32_t num_ext)
138 {
139 size_t new_size;
140 VkExtensionProperties *new_ptr;
141
142 assert(new_ext && num_ext > 0);
143
144 if (!new_ext)
145 return VK_ERROR_INITIALIZATION_FAILED;
146
147 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
148 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
149 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
150
151 /* Old array continues to be valid, update nothing */
152 if (!new_ptr)
153 return VK_ERROR_OUT_OF_HOST_MEMORY;
154
155 memcpy(&new_ptr[extensions->num_ext], new_ext,
156 num_ext * sizeof(VkExtensionProperties));
157 extensions->ext_array = new_ptr;
158 extensions->num_ext += num_ext;
159
160 return VK_SUCCESS;
161 }
162
163 static void
164 radv_extensions_finish(struct radv_instance *instance,
165 struct radv_extensions *extensions)
166 {
167 assert(extensions);
168
169 if (!extensions)
170 radv_loge("Attemted to free invalid extension struct\n");
171
172 if (extensions->ext_array)
173 vk_free(&instance->alloc, extensions->ext_array);
174 }
175
176 static bool
177 is_extension_enabled(const VkExtensionProperties *extensions,
178 size_t num_ext,
179 const char *name)
180 {
181 assert(extensions && name);
182
183 for (uint32_t i = 0; i < num_ext; i++) {
184 if (strcmp(name, extensions[i].extensionName) == 0)
185 return true;
186 }
187
188 return false;
189 }
190
191 static VkResult
192 radv_physical_device_init(struct radv_physical_device *device,
193 struct radv_instance *instance,
194 const char *path)
195 {
196 VkResult result;
197 drmVersionPtr version;
198 int fd;
199
200 fd = open(path, O_RDWR | O_CLOEXEC);
201 if (fd < 0)
202 return VK_ERROR_INCOMPATIBLE_DRIVER;
203
204 version = drmGetVersion(fd);
205 if (!version) {
206 close(fd);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
208 "failed to get version %s: %m", path);
209 }
210
211 if (strcmp(version->name, "amdgpu")) {
212 drmFreeVersion(version);
213 close(fd);
214 return VK_ERROR_INCOMPATIBLE_DRIVER;
215 }
216 drmFreeVersion(version);
217
218 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
219 device->instance = instance;
220 assert(strlen(path) < ARRAY_SIZE(device->path));
221 strncpy(device->path, path, ARRAY_SIZE(device->path));
222
223 device->ws = radv_amdgpu_winsys_create(fd);
224 if (!device->ws) {
225 result = VK_ERROR_INCOMPATIBLE_DRIVER;
226 goto fail;
227 }
228 device->ws->query_info(device->ws, &device->rad_info);
229 result = radv_init_wsi(device);
230 if (result != VK_SUCCESS) {
231 device->ws->destroy(device->ws);
232 goto fail;
233 }
234
235 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
236 radv_finish_wsi(device);
237 device->ws->destroy(device->ws);
238 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
239 "cannot generate UUID");
240 goto fail;
241 }
242
243 result = radv_extensions_register(instance,
244 &device->extensions,
245 common_device_extensions,
246 ARRAY_SIZE(common_device_extensions));
247 if (result != VK_SUCCESS)
248 goto fail;
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251 device->name = device->rad_info.name;
252 close(fd);
253 return VK_SUCCESS;
254
255 fail:
256 close(fd);
257 return result;
258 }
259
260 static void
261 radv_physical_device_finish(struct radv_physical_device *device)
262 {
263 radv_extensions_finish(device->instance, &device->extensions);
264 radv_finish_wsi(device);
265 device->ws->destroy(device->ws);
266 }
267
268
269 static void *
270 default_alloc_func(void *pUserData, size_t size, size_t align,
271 VkSystemAllocationScope allocationScope)
272 {
273 return malloc(size);
274 }
275
276 static void *
277 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
278 size_t align, VkSystemAllocationScope allocationScope)
279 {
280 return realloc(pOriginal, size);
281 }
282
283 static void
284 default_free_func(void *pUserData, void *pMemory)
285 {
286 free(pMemory);
287 }
288
289 static const VkAllocationCallbacks default_alloc = {
290 .pUserData = NULL,
291 .pfnAllocation = default_alloc_func,
292 .pfnReallocation = default_realloc_func,
293 .pfnFree = default_free_func,
294 };
295
296 static const struct debug_control radv_debug_options[] = {
297 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
298 {"nodcc", RADV_DEBUG_NO_DCC},
299 {"shaders", RADV_DEBUG_DUMP_SHADERS},
300 {"nocache", RADV_DEBUG_NO_CACHE},
301 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
302 {"nohiz", RADV_DEBUG_NO_HIZ},
303 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
304 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
305 {NULL, 0}
306 };
307
308 VkResult radv_CreateInstance(
309 const VkInstanceCreateInfo* pCreateInfo,
310 const VkAllocationCallbacks* pAllocator,
311 VkInstance* pInstance)
312 {
313 struct radv_instance *instance;
314
315 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
316
317 uint32_t client_version;
318 if (pCreateInfo->pApplicationInfo &&
319 pCreateInfo->pApplicationInfo->apiVersion != 0) {
320 client_version = pCreateInfo->pApplicationInfo->apiVersion;
321 } else {
322 client_version = VK_MAKE_VERSION(1, 0, 0);
323 }
324
325 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
326 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
327 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
328 "Client requested version %d.%d.%d",
329 VK_VERSION_MAJOR(client_version),
330 VK_VERSION_MINOR(client_version),
331 VK_VERSION_PATCH(client_version));
332 }
333
334 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
335 if (!is_extension_enabled(instance_extensions,
336 ARRAY_SIZE(instance_extensions),
337 pCreateInfo->ppEnabledExtensionNames[i]))
338 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
339 }
340
341 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
343 if (!instance)
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
345
346 memset(instance, 0, sizeof(*instance));
347
348 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
349
350 if (pAllocator)
351 instance->alloc = *pAllocator;
352 else
353 instance->alloc = default_alloc;
354
355 instance->apiVersion = client_version;
356 instance->physicalDeviceCount = -1;
357
358 _mesa_locale_init();
359
360 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
361
362 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
363 radv_debug_options);
364
365 *pInstance = radv_instance_to_handle(instance);
366
367 return VK_SUCCESS;
368 }
369
370 void radv_DestroyInstance(
371 VkInstance _instance,
372 const VkAllocationCallbacks* pAllocator)
373 {
374 RADV_FROM_HANDLE(radv_instance, instance, _instance);
375
376 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
377 radv_physical_device_finish(instance->physicalDevices + i);
378 }
379
380 VG(VALGRIND_DESTROY_MEMPOOL(instance));
381
382 _mesa_locale_fini();
383
384 vk_free(&instance->alloc, instance);
385 }
386
387 VkResult radv_EnumeratePhysicalDevices(
388 VkInstance _instance,
389 uint32_t* pPhysicalDeviceCount,
390 VkPhysicalDevice* pPhysicalDevices)
391 {
392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
393 VkResult result;
394
395 if (instance->physicalDeviceCount < 0) {
396 char path[20];
397 instance->physicalDeviceCount = 0;
398 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
399 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
400 result = radv_physical_device_init(instance->physicalDevices +
401 instance->physicalDeviceCount,
402 instance, path);
403 if (result == VK_SUCCESS)
404 ++instance->physicalDeviceCount;
405 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
406 return result;
407 }
408 }
409
410 if (!pPhysicalDevices) {
411 *pPhysicalDeviceCount = instance->physicalDeviceCount;
412 } else {
413 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
414 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
415 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
416 }
417
418 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
419 : VK_SUCCESS;
420 }
421
422 void radv_GetPhysicalDeviceFeatures(
423 VkPhysicalDevice physicalDevice,
424 VkPhysicalDeviceFeatures* pFeatures)
425 {
426 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
427
428 memset(pFeatures, 0, sizeof(*pFeatures));
429
430 *pFeatures = (VkPhysicalDeviceFeatures) {
431 .robustBufferAccess = true,
432 .fullDrawIndexUint32 = true,
433 .imageCubeArray = true,
434 .independentBlend = true,
435 .geometryShader = true,
436 .tessellationShader = false,
437 .sampleRateShading = false,
438 .dualSrcBlend = true,
439 .logicOp = true,
440 .multiDrawIndirect = true,
441 .drawIndirectFirstInstance = true,
442 .depthClamp = true,
443 .depthBiasClamp = true,
444 .fillModeNonSolid = true,
445 .depthBounds = true,
446 .wideLines = true,
447 .largePoints = true,
448 .alphaToOne = true,
449 .multiViewport = true,
450 .samplerAnisotropy = true,
451 .textureCompressionETC2 = false,
452 .textureCompressionASTC_LDR = false,
453 .textureCompressionBC = true,
454 .occlusionQueryPrecise = true,
455 .pipelineStatisticsQuery = false,
456 .vertexPipelineStoresAndAtomics = true,
457 .fragmentStoresAndAtomics = true,
458 .shaderTessellationAndGeometryPointSize = true,
459 .shaderImageGatherExtended = true,
460 .shaderStorageImageExtendedFormats = true,
461 .shaderStorageImageMultisample = false,
462 .shaderUniformBufferArrayDynamicIndexing = true,
463 .shaderSampledImageArrayDynamicIndexing = true,
464 .shaderStorageBufferArrayDynamicIndexing = true,
465 .shaderStorageImageArrayDynamicIndexing = true,
466 .shaderStorageImageReadWithoutFormat = false,
467 .shaderStorageImageWriteWithoutFormat = false,
468 .shaderClipDistance = true,
469 .shaderCullDistance = true,
470 .shaderFloat64 = true,
471 .shaderInt64 = false,
472 .shaderInt16 = false,
473 .alphaToOne = true,
474 .variableMultisampleRate = false,
475 .inheritedQueries = false,
476 };
477 }
478
479 void radv_GetPhysicalDeviceFeatures2KHR(
480 VkPhysicalDevice physicalDevice,
481 VkPhysicalDeviceFeatures2KHR *pFeatures)
482 {
483 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
484 }
485
486 void radv_GetPhysicalDeviceProperties(
487 VkPhysicalDevice physicalDevice,
488 VkPhysicalDeviceProperties* pProperties)
489 {
490 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
491 VkSampleCountFlags sample_counts = 0xf;
492 VkPhysicalDeviceLimits limits = {
493 .maxImageDimension1D = (1 << 14),
494 .maxImageDimension2D = (1 << 14),
495 .maxImageDimension3D = (1 << 11),
496 .maxImageDimensionCube = (1 << 14),
497 .maxImageArrayLayers = (1 << 11),
498 .maxTexelBufferElements = 128 * 1024 * 1024,
499 .maxUniformBufferRange = UINT32_MAX,
500 .maxStorageBufferRange = UINT32_MAX,
501 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
502 .maxMemoryAllocationCount = UINT32_MAX,
503 .maxSamplerAllocationCount = 64 * 1024,
504 .bufferImageGranularity = 64, /* A cache line */
505 .sparseAddressSpaceSize = 0,
506 .maxBoundDescriptorSets = MAX_SETS,
507 .maxPerStageDescriptorSamplers = 64,
508 .maxPerStageDescriptorUniformBuffers = 64,
509 .maxPerStageDescriptorStorageBuffers = 64,
510 .maxPerStageDescriptorSampledImages = 64,
511 .maxPerStageDescriptorStorageImages = 64,
512 .maxPerStageDescriptorInputAttachments = 64,
513 .maxPerStageResources = 128,
514 .maxDescriptorSetSamplers = 256,
515 .maxDescriptorSetUniformBuffers = 256,
516 .maxDescriptorSetUniformBuffersDynamic = 256,
517 .maxDescriptorSetStorageBuffers = 256,
518 .maxDescriptorSetStorageBuffersDynamic = 256,
519 .maxDescriptorSetSampledImages = 256,
520 .maxDescriptorSetStorageImages = 256,
521 .maxDescriptorSetInputAttachments = 256,
522 .maxVertexInputAttributes = 32,
523 .maxVertexInputBindings = 32,
524 .maxVertexInputAttributeOffset = 2047,
525 .maxVertexInputBindingStride = 2048,
526 .maxVertexOutputComponents = 128,
527 .maxTessellationGenerationLevel = 0,
528 .maxTessellationPatchSize = 0,
529 .maxTessellationControlPerVertexInputComponents = 0,
530 .maxTessellationControlPerVertexOutputComponents = 0,
531 .maxTessellationControlPerPatchOutputComponents = 0,
532 .maxTessellationControlTotalOutputComponents = 0,
533 .maxTessellationEvaluationInputComponents = 0,
534 .maxTessellationEvaluationOutputComponents = 0,
535 .maxGeometryShaderInvocations = 32,
536 .maxGeometryInputComponents = 64,
537 .maxGeometryOutputComponents = 128,
538 .maxGeometryOutputVertices = 256,
539 .maxGeometryTotalOutputComponents = 1024,
540 .maxFragmentInputComponents = 128,
541 .maxFragmentOutputAttachments = 8,
542 .maxFragmentDualSrcAttachments = 1,
543 .maxFragmentCombinedOutputResources = 8,
544 .maxComputeSharedMemorySize = 32768,
545 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
546 .maxComputeWorkGroupInvocations = 2048,
547 .maxComputeWorkGroupSize = {
548 2048,
549 2048,
550 2048
551 },
552 .subPixelPrecisionBits = 4 /* FIXME */,
553 .subTexelPrecisionBits = 4 /* FIXME */,
554 .mipmapPrecisionBits = 4 /* FIXME */,
555 .maxDrawIndexedIndexValue = UINT32_MAX,
556 .maxDrawIndirectCount = UINT32_MAX,
557 .maxSamplerLodBias = 16,
558 .maxSamplerAnisotropy = 16,
559 .maxViewports = MAX_VIEWPORTS,
560 .maxViewportDimensions = { (1 << 14), (1 << 14) },
561 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
562 .viewportSubPixelBits = 13, /* We take a float? */
563 .minMemoryMapAlignment = 4096, /* A page */
564 .minTexelBufferOffsetAlignment = 1,
565 .minUniformBufferOffsetAlignment = 4,
566 .minStorageBufferOffsetAlignment = 4,
567 .minTexelOffset = -32,
568 .maxTexelOffset = 31,
569 .minTexelGatherOffset = -32,
570 .maxTexelGatherOffset = 31,
571 .minInterpolationOffset = -2,
572 .maxInterpolationOffset = 2,
573 .subPixelInterpolationOffsetBits = 8,
574 .maxFramebufferWidth = (1 << 14),
575 .maxFramebufferHeight = (1 << 14),
576 .maxFramebufferLayers = (1 << 10),
577 .framebufferColorSampleCounts = sample_counts,
578 .framebufferDepthSampleCounts = sample_counts,
579 .framebufferStencilSampleCounts = sample_counts,
580 .framebufferNoAttachmentsSampleCounts = sample_counts,
581 .maxColorAttachments = MAX_RTS,
582 .sampledImageColorSampleCounts = sample_counts,
583 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
584 .sampledImageDepthSampleCounts = sample_counts,
585 .sampledImageStencilSampleCounts = sample_counts,
586 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
587 .maxSampleMaskWords = 1,
588 .timestampComputeAndGraphics = false,
589 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
590 .maxClipDistances = 8,
591 .maxCullDistances = 8,
592 .maxCombinedClipAndCullDistances = 8,
593 .discreteQueuePriorities = 1,
594 .pointSizeRange = { 0.125, 255.875 },
595 .lineWidthRange = { 0.0, 7.9921875 },
596 .pointSizeGranularity = (1.0 / 8.0),
597 .lineWidthGranularity = (1.0 / 128.0),
598 .strictLines = false, /* FINISHME */
599 .standardSampleLocations = true,
600 .optimalBufferCopyOffsetAlignment = 128,
601 .optimalBufferCopyRowPitchAlignment = 128,
602 .nonCoherentAtomSize = 64,
603 };
604
605 *pProperties = (VkPhysicalDeviceProperties) {
606 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
607 .driverVersion = 1,
608 .vendorID = 0x1002,
609 .deviceID = pdevice->rad_info.pci_id,
610 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
611 .limits = limits,
612 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
613 };
614
615 strcpy(pProperties->deviceName, pdevice->name);
616 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
617 }
618
619 void radv_GetPhysicalDeviceProperties2KHR(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceProperties2KHR *pProperties)
622 {
623 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
624 }
625
626 void radv_GetPhysicalDeviceQueueFamilyProperties(
627 VkPhysicalDevice physicalDevice,
628 uint32_t* pCount,
629 VkQueueFamilyProperties* pQueueFamilyProperties)
630 {
631 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
632 int num_queue_families = 1;
633 int idx;
634 if (pdevice->rad_info.compute_rings > 0 &&
635 pdevice->rad_info.chip_class >= CIK &&
636 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
637 num_queue_families++;
638
639 if (pQueueFamilyProperties == NULL) {
640 *pCount = num_queue_families;
641 return;
642 }
643
644 if (!*pCount)
645 return;
646
647 idx = 0;
648 if (*pCount >= 1) {
649 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
650 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
651 VK_QUEUE_COMPUTE_BIT |
652 VK_QUEUE_TRANSFER_BIT,
653 .queueCount = 1,
654 .timestampValidBits = 64,
655 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
656 };
657 idx++;
658 }
659
660 if (pdevice->rad_info.compute_rings > 0 &&
661 pdevice->rad_info.chip_class >= CIK &&
662 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
663 if (*pCount > idx) {
664 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
665 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
666 .queueCount = pdevice->rad_info.compute_rings,
667 .timestampValidBits = 64,
668 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
669 };
670 idx++;
671 }
672 }
673 *pCount = idx;
674 }
675
676 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
677 VkPhysicalDevice physicalDevice,
678 uint32_t* pCount,
679 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
680 {
681 return radv_GetPhysicalDeviceQueueFamilyProperties(physicalDevice,
682 pCount,
683 &pQueueFamilyProperties->queueFamilyProperties);
684 }
685
686 void radv_GetPhysicalDeviceMemoryProperties(
687 VkPhysicalDevice physicalDevice,
688 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
689 {
690 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
691
692 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
693
694 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
695 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
696 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
697 .heapIndex = RADV_MEM_HEAP_VRAM,
698 };
699 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
700 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
701 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
702 .heapIndex = RADV_MEM_HEAP_GTT,
703 };
704 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
705 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
706 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
707 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
708 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
709 };
710 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
711 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
712 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
713 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
714 .heapIndex = RADV_MEM_HEAP_GTT,
715 };
716
717 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
718
719 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
720 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
721 .size = physical_device->rad_info.vram_size -
722 physical_device->rad_info.visible_vram_size,
723 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
724 };
725 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
726 .size = physical_device->rad_info.visible_vram_size,
727 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
728 };
729 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
730 .size = physical_device->rad_info.gart_size,
731 .flags = 0,
732 };
733 }
734
735 void radv_GetPhysicalDeviceMemoryProperties2KHR(
736 VkPhysicalDevice physicalDevice,
737 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
738 {
739 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
740 &pMemoryProperties->memoryProperties);
741 }
742
743 static int
744 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
745 int queue_family_index, int idx)
746 {
747 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
748 queue->device = device;
749 queue->queue_family_index = queue_family_index;
750 queue->queue_idx = idx;
751
752 queue->hw_ctx = device->ws->ctx_create(device->ws);
753 if (!queue->hw_ctx)
754 return VK_ERROR_OUT_OF_HOST_MEMORY;
755
756 return VK_SUCCESS;
757 }
758
759 static void
760 radv_queue_finish(struct radv_queue *queue)
761 {
762 if (queue->hw_ctx)
763 queue->device->ws->ctx_destroy(queue->hw_ctx);
764
765 if (queue->preamble_cs)
766 queue->device->ws->cs_destroy(queue->preamble_cs);
767 if (queue->descriptor_bo)
768 queue->device->ws->buffer_destroy(queue->descriptor_bo);
769 if (queue->scratch_bo)
770 queue->device->ws->buffer_destroy(queue->scratch_bo);
771 if (queue->esgs_ring_bo)
772 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
773 if (queue->gsvs_ring_bo)
774 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
775 if (queue->compute_scratch_bo)
776 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
777 }
778
779 static void
780 radv_device_init_gs_info(struct radv_device *device)
781 {
782 switch (device->physical_device->rad_info.family) {
783 case CHIP_OLAND:
784 case CHIP_HAINAN:
785 case CHIP_KAVERI:
786 case CHIP_KABINI:
787 case CHIP_MULLINS:
788 case CHIP_ICELAND:
789 case CHIP_CARRIZO:
790 case CHIP_STONEY:
791 device->gs_table_depth = 16;
792 return;
793 case CHIP_TAHITI:
794 case CHIP_PITCAIRN:
795 case CHIP_VERDE:
796 case CHIP_BONAIRE:
797 case CHIP_HAWAII:
798 case CHIP_TONGA:
799 case CHIP_FIJI:
800 case CHIP_POLARIS10:
801 case CHIP_POLARIS11:
802 device->gs_table_depth = 32;
803 return;
804 default:
805 unreachable("unknown GPU");
806 }
807 }
808
809 VkResult radv_CreateDevice(
810 VkPhysicalDevice physicalDevice,
811 const VkDeviceCreateInfo* pCreateInfo,
812 const VkAllocationCallbacks* pAllocator,
813 VkDevice* pDevice)
814 {
815 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
816 VkResult result;
817 struct radv_device *device;
818
819 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
820 if (!is_extension_enabled(physical_device->extensions.ext_array,
821 physical_device->extensions.num_ext,
822 pCreateInfo->ppEnabledExtensionNames[i]))
823 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
824 }
825
826 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
827 sizeof(*device), 8,
828 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
829 if (!device)
830 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
831
832 memset(device, 0, sizeof(*device));
833
834 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
835 device->instance = physical_device->instance;
836 device->physical_device = physical_device;
837
838 device->debug_flags = device->instance->debug_flags;
839
840 device->ws = physical_device->ws;
841 if (pAllocator)
842 device->alloc = *pAllocator;
843 else
844 device->alloc = physical_device->instance->alloc;
845
846 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
847 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
848 uint32_t qfi = queue_create->queueFamilyIndex;
849
850 device->queues[qfi] = vk_alloc(&device->alloc,
851 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
852 if (!device->queues[qfi]) {
853 result = VK_ERROR_OUT_OF_HOST_MEMORY;
854 goto fail;
855 }
856
857 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
858
859 device->queue_count[qfi] = queue_create->queueCount;
860
861 for (unsigned q = 0; q < queue_create->queueCount; q++) {
862 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
863 if (result != VK_SUCCESS)
864 goto fail;
865 }
866 }
867
868 #if HAVE_LLVM < 0x0400
869 device->llvm_supports_spill = false;
870 #else
871 device->llvm_supports_spill = true;
872 #endif
873
874 /* The maximum number of scratch waves. Scratch space isn't divided
875 * evenly between CUs. The number is only a function of the number of CUs.
876 * We can decrease the constant to decrease the scratch buffer size.
877 *
878 * sctx->scratch_waves must be >= the maximum posible size of
879 * 1 threadgroup, so that the hw doesn't hang from being unable
880 * to start any.
881 *
882 * The recommended value is 4 per CU at most. Higher numbers don't
883 * bring much benefit, but they still occupy chip resources (think
884 * async compute). I've seen ~2% performance difference between 4 and 32.
885 */
886 uint32_t max_threads_per_block = 2048;
887 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
888 max_threads_per_block / 64);
889
890 radv_device_init_gs_info(device);
891
892 result = radv_device_init_meta(device);
893 if (result != VK_SUCCESS)
894 goto fail;
895
896 radv_device_init_msaa(device);
897
898 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
899 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
900 switch (family) {
901 case RADV_QUEUE_GENERAL:
902 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
903 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
904 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
905 break;
906 case RADV_QUEUE_COMPUTE:
907 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
908 radeon_emit(device->empty_cs[family], 0);
909 break;
910 }
911 device->ws->cs_finalize(device->empty_cs[family]);
912 }
913
914 if (getenv("RADV_TRACE_FILE")) {
915 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
916 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
917 if (!device->trace_bo)
918 goto fail;
919
920 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
921 if (!device->trace_id_ptr)
922 goto fail;
923 }
924
925 *pDevice = radv_device_to_handle(device);
926 return VK_SUCCESS;
927
928 fail:
929 if (device->trace_bo)
930 device->ws->buffer_destroy(device->trace_bo);
931
932 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
933 for (unsigned q = 0; q < device->queue_count[i]; q++)
934 radv_queue_finish(&device->queues[i][q]);
935 if (device->queue_count[i])
936 vk_free(&device->alloc, device->queues[i]);
937 }
938
939 vk_free(&device->alloc, device);
940 return result;
941 }
942
943 void radv_DestroyDevice(
944 VkDevice _device,
945 const VkAllocationCallbacks* pAllocator)
946 {
947 RADV_FROM_HANDLE(radv_device, device, _device);
948
949 if (device->trace_bo)
950 device->ws->buffer_destroy(device->trace_bo);
951
952 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
953 for (unsigned q = 0; q < device->queue_count[i]; q++)
954 radv_queue_finish(&device->queues[i][q]);
955 if (device->queue_count[i])
956 vk_free(&device->alloc, device->queues[i]);
957 }
958 radv_device_finish_meta(device);
959
960 vk_free(&device->alloc, device);
961 }
962
963 VkResult radv_EnumerateInstanceExtensionProperties(
964 const char* pLayerName,
965 uint32_t* pPropertyCount,
966 VkExtensionProperties* pProperties)
967 {
968 if (pProperties == NULL) {
969 *pPropertyCount = ARRAY_SIZE(instance_extensions);
970 return VK_SUCCESS;
971 }
972
973 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
974 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
975
976 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
977 return VK_INCOMPLETE;
978
979 return VK_SUCCESS;
980 }
981
982 VkResult radv_EnumerateDeviceExtensionProperties(
983 VkPhysicalDevice physicalDevice,
984 const char* pLayerName,
985 uint32_t* pPropertyCount,
986 VkExtensionProperties* pProperties)
987 {
988 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
989
990 if (pProperties == NULL) {
991 *pPropertyCount = pdevice->extensions.num_ext;
992 return VK_SUCCESS;
993 }
994
995 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
996 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
997
998 if (*pPropertyCount < pdevice->extensions.num_ext)
999 return VK_INCOMPLETE;
1000
1001 return VK_SUCCESS;
1002 }
1003
1004 VkResult radv_EnumerateInstanceLayerProperties(
1005 uint32_t* pPropertyCount,
1006 VkLayerProperties* pProperties)
1007 {
1008 if (pProperties == NULL) {
1009 *pPropertyCount = 0;
1010 return VK_SUCCESS;
1011 }
1012
1013 /* None supported at this time */
1014 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1015 }
1016
1017 VkResult radv_EnumerateDeviceLayerProperties(
1018 VkPhysicalDevice physicalDevice,
1019 uint32_t* pPropertyCount,
1020 VkLayerProperties* pProperties)
1021 {
1022 if (pProperties == NULL) {
1023 *pPropertyCount = 0;
1024 return VK_SUCCESS;
1025 }
1026
1027 /* None supported at this time */
1028 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1029 }
1030
1031 void radv_GetDeviceQueue(
1032 VkDevice _device,
1033 uint32_t queueFamilyIndex,
1034 uint32_t queueIndex,
1035 VkQueue* pQueue)
1036 {
1037 RADV_FROM_HANDLE(radv_device, device, _device);
1038
1039 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1040 }
1041
1042 static void radv_dump_trace(struct radv_device *device,
1043 struct radeon_winsys_cs *cs)
1044 {
1045 const char *filename = getenv("RADV_TRACE_FILE");
1046 FILE *f = fopen(filename, "w");
1047 if (!f) {
1048 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1049 return;
1050 }
1051
1052 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1053 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1054 fclose(f);
1055 }
1056
1057 static void
1058 fill_geom_rings(struct radv_queue *queue,
1059 uint32_t *map,
1060 uint32_t esgs_ring_size,
1061 struct radeon_winsys_bo *esgs_ring_bo,
1062 uint32_t gsvs_ring_size,
1063 struct radeon_winsys_bo *gsvs_ring_bo)
1064 {
1065 uint64_t esgs_va = 0, gsvs_va = 0;
1066 uint32_t *desc = &map[4];
1067
1068 if (esgs_ring_bo)
1069 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1070 if (gsvs_ring_bo)
1071 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1072
1073 /* stride 0, num records - size, add tid, swizzle, elsize4,
1074 index stride 64 */
1075 desc[0] = esgs_va;
1076 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1077 S_008F04_STRIDE(0) |
1078 S_008F04_SWIZZLE_ENABLE(true);
1079 desc[2] = esgs_ring_size;
1080 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1081 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1082 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1083 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1084 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1085 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1086 S_008F0C_ELEMENT_SIZE(1) |
1087 S_008F0C_INDEX_STRIDE(3) |
1088 S_008F0C_ADD_TID_ENABLE(true);
1089
1090 desc += 4;
1091 /* GS entry for ES->GS ring */
1092 /* stride 0, num records - size, elsize0,
1093 index stride 0 */
1094 desc[0] = esgs_va;
1095 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1096 S_008F04_STRIDE(0) |
1097 S_008F04_SWIZZLE_ENABLE(false);
1098 desc[2] = esgs_ring_size;
1099 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1100 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1101 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1102 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1103 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1104 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1105 S_008F0C_ELEMENT_SIZE(0) |
1106 S_008F0C_INDEX_STRIDE(0) |
1107 S_008F0C_ADD_TID_ENABLE(false);
1108
1109 desc += 4;
1110 /* VS entry for GS->VS ring */
1111 /* stride 0, num records - size, elsize0,
1112 index stride 0 */
1113 desc[0] = gsvs_va;
1114 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1115 S_008F04_STRIDE(0) |
1116 S_008F04_SWIZZLE_ENABLE(false);
1117 desc[2] = gsvs_ring_size;
1118 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1119 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1120 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1121 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1122 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1123 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1124 S_008F0C_ELEMENT_SIZE(0) |
1125 S_008F0C_INDEX_STRIDE(0) |
1126 S_008F0C_ADD_TID_ENABLE(false);
1127 desc += 4;
1128
1129 /* stride gsvs_itemsize, num records 64
1130 elsize 4, index stride 16 */
1131 /* shader will patch stride and desc[2] */
1132 desc[0] = gsvs_va;
1133 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1134 S_008F04_STRIDE(0) |
1135 S_008F04_SWIZZLE_ENABLE(true);
1136 desc[2] = 0;
1137 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1138 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1139 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1140 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1141 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1143 S_008F0C_ELEMENT_SIZE(1) |
1144 S_008F0C_INDEX_STRIDE(1) |
1145 S_008F0C_ADD_TID_ENABLE(true);
1146 }
1147
1148 static VkResult
1149 radv_get_preamble_cs(struct radv_queue *queue,
1150 uint32_t scratch_size,
1151 uint32_t compute_scratch_size,
1152 uint32_t esgs_ring_size,
1153 uint32_t gsvs_ring_size,
1154 struct radeon_winsys_cs **preamble_cs)
1155 {
1156 struct radeon_winsys_bo *scratch_bo = NULL;
1157 struct radeon_winsys_bo *descriptor_bo = NULL;
1158 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1159 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1160 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1161 struct radeon_winsys_cs *cs = NULL;
1162
1163 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size) {
1164 *preamble_cs = NULL;
1165 return VK_SUCCESS;
1166 }
1167
1168 if (scratch_size <= queue->scratch_size &&
1169 compute_scratch_size <= queue->compute_scratch_size &&
1170 esgs_ring_size <= queue->esgs_ring_size &&
1171 gsvs_ring_size <= queue->gsvs_ring_size) {
1172 *preamble_cs = queue->preamble_cs;
1173 return VK_SUCCESS;
1174 }
1175
1176 if (scratch_size > queue->scratch_size) {
1177 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1178 scratch_size,
1179 4096,
1180 RADEON_DOMAIN_VRAM,
1181 RADEON_FLAG_NO_CPU_ACCESS);
1182 if (!scratch_bo)
1183 goto fail;
1184 } else
1185 scratch_bo = queue->scratch_bo;
1186
1187 if (compute_scratch_size > queue->compute_scratch_size) {
1188 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1189 compute_scratch_size,
1190 4096,
1191 RADEON_DOMAIN_VRAM,
1192 RADEON_FLAG_NO_CPU_ACCESS);
1193 if (!compute_scratch_bo)
1194 goto fail;
1195
1196 } else
1197 compute_scratch_bo = queue->compute_scratch_bo;
1198
1199 if (esgs_ring_size > queue->esgs_ring_size) {
1200 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1201 esgs_ring_size,
1202 4096,
1203 RADEON_DOMAIN_VRAM,
1204 RADEON_FLAG_NO_CPU_ACCESS);
1205 if (!esgs_ring_bo)
1206 goto fail;
1207 } else {
1208 esgs_ring_bo = queue->esgs_ring_bo;
1209 esgs_ring_size = queue->esgs_ring_size;
1210 }
1211
1212 if (gsvs_ring_size > queue->gsvs_ring_size) {
1213 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1214 gsvs_ring_size,
1215 4096,
1216 RADEON_DOMAIN_VRAM,
1217 RADEON_FLAG_NO_CPU_ACCESS);
1218 if (!gsvs_ring_bo)
1219 goto fail;
1220 } else {
1221 gsvs_ring_bo = queue->gsvs_ring_bo;
1222 gsvs_ring_size = queue->gsvs_ring_size;
1223 }
1224
1225 if (scratch_bo != queue->scratch_bo ||
1226 esgs_ring_bo != queue->esgs_ring_bo ||
1227 gsvs_ring_bo != queue->gsvs_ring_bo) {
1228 uint32_t size = 0;
1229 if (gsvs_ring_bo || esgs_ring_bo)
1230 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1231 else if (scratch_bo)
1232 size = 8; /* 2 dword */
1233
1234 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1235 size,
1236 4096,
1237 RADEON_DOMAIN_VRAM,
1238 RADEON_FLAG_CPU_ACCESS);
1239 if (!descriptor_bo)
1240 goto fail;
1241 } else
1242 descriptor_bo = queue->descriptor_bo;
1243
1244 cs = queue->device->ws->cs_create(queue->device->ws,
1245 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1246 if (!cs)
1247 goto fail;
1248
1249
1250 if (scratch_bo)
1251 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1252
1253 if (esgs_ring_bo)
1254 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1255
1256 if (gsvs_ring_bo)
1257 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1258
1259 if (descriptor_bo)
1260 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1261
1262 if (descriptor_bo != queue->descriptor_bo) {
1263 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1264
1265 if (scratch_bo) {
1266 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1267 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1268 S_008F04_SWIZZLE_ENABLE(1);
1269 map[0] = scratch_va;
1270 map[1] = rsrc1;
1271 }
1272
1273 if (esgs_ring_bo || gsvs_ring_bo)
1274 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1275
1276 queue->device->ws->buffer_unmap(descriptor_bo);
1277 }
1278
1279 if (esgs_ring_bo || gsvs_ring_bo) {
1280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1281 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1282 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1283 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1284
1285 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1286 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1287 radeon_emit(cs, esgs_ring_size >> 8);
1288 radeon_emit(cs, gsvs_ring_size >> 8);
1289 } else {
1290 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1291 radeon_emit(cs, esgs_ring_size >> 8);
1292 radeon_emit(cs, gsvs_ring_size >> 8);
1293 }
1294 }
1295
1296 if (descriptor_bo) {
1297 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1298 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1299 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1300 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1301 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1302 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1303
1304 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1305
1306 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1307 radeon_set_sh_reg_seq(cs, regs[i], 2);
1308 radeon_emit(cs, va);
1309 radeon_emit(cs, va >> 32);
1310 }
1311 }
1312
1313 if (compute_scratch_bo) {
1314 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1315 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1316 S_008F04_SWIZZLE_ENABLE(1);
1317
1318 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1319
1320 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1321 radeon_emit(cs, scratch_va);
1322 radeon_emit(cs, rsrc1);
1323 }
1324
1325 if (!queue->device->ws->cs_finalize(cs))
1326 goto fail;
1327
1328 if (queue->preamble_cs)
1329 queue->device->ws->cs_destroy(queue->preamble_cs);
1330
1331 queue->preamble_cs = cs;
1332
1333 if (scratch_bo != queue->scratch_bo) {
1334 if (queue->scratch_bo)
1335 queue->device->ws->buffer_destroy(queue->scratch_bo);
1336 queue->scratch_bo = scratch_bo;
1337 queue->scratch_size = scratch_size;
1338 }
1339
1340 if (compute_scratch_bo != queue->compute_scratch_bo) {
1341 if (queue->compute_scratch_bo)
1342 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1343 queue->compute_scratch_bo = compute_scratch_bo;
1344 queue->compute_scratch_size = compute_scratch_size;
1345 }
1346
1347 if (esgs_ring_bo != queue->esgs_ring_bo) {
1348 if (queue->esgs_ring_bo)
1349 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1350 queue->esgs_ring_bo = esgs_ring_bo;
1351 queue->esgs_ring_size = esgs_ring_size;
1352 }
1353
1354 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1355 if (queue->gsvs_ring_bo)
1356 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1357 queue->gsvs_ring_bo = gsvs_ring_bo;
1358 queue->gsvs_ring_size = gsvs_ring_size;
1359 }
1360
1361 if (descriptor_bo != queue->descriptor_bo) {
1362 if (queue->descriptor_bo)
1363 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1364
1365 queue->descriptor_bo = descriptor_bo;
1366 }
1367
1368 *preamble_cs = cs;
1369 return VK_SUCCESS;
1370 fail:
1371 if (cs)
1372 queue->device->ws->cs_destroy(cs);
1373 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1374 queue->device->ws->buffer_destroy(descriptor_bo);
1375 if (scratch_bo && scratch_bo != queue->scratch_bo)
1376 queue->device->ws->buffer_destroy(scratch_bo);
1377 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1378 queue->device->ws->buffer_destroy(compute_scratch_bo);
1379 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1380 queue->device->ws->buffer_destroy(esgs_ring_bo);
1381 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1382 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1383 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1384 }
1385
1386 VkResult radv_QueueSubmit(
1387 VkQueue _queue,
1388 uint32_t submitCount,
1389 const VkSubmitInfo* pSubmits,
1390 VkFence _fence)
1391 {
1392 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1393 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1394 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1395 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1396 int ret;
1397 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1398 uint32_t scratch_size = 0;
1399 uint32_t compute_scratch_size = 0;
1400 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1401 struct radeon_winsys_cs *preamble_cs = NULL;
1402 VkResult result;
1403 bool fence_emitted = false;
1404
1405 /* Do this first so failing to allocate scratch buffers can't result in
1406 * partially executed submissions. */
1407 for (uint32_t i = 0; i < submitCount; i++) {
1408 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1410 pSubmits[i].pCommandBuffers[j]);
1411
1412 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1413 compute_scratch_size = MAX2(compute_scratch_size,
1414 cmd_buffer->compute_scratch_size_needed);
1415 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1416 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1417 }
1418 }
1419
1420 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size, esgs_ring_size, gsvs_ring_size, &preamble_cs);
1421 if (result != VK_SUCCESS)
1422 return result;
1423
1424 for (uint32_t i = 0; i < submitCount; i++) {
1425 struct radeon_winsys_cs **cs_array;
1426 bool can_patch = true;
1427 uint32_t advance;
1428
1429 if (!pSubmits[i].commandBufferCount) {
1430 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1431 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1432 &queue->device->empty_cs[queue->queue_family_index],
1433 1, NULL,
1434 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1435 pSubmits[i].waitSemaphoreCount,
1436 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1437 pSubmits[i].signalSemaphoreCount,
1438 false, base_fence);
1439 if (ret) {
1440 radv_loge("failed to submit CS %d\n", i);
1441 abort();
1442 }
1443 fence_emitted = true;
1444 }
1445 continue;
1446 }
1447
1448 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1449 pSubmits[i].commandBufferCount);
1450
1451 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1453 pSubmits[i].pCommandBuffers[j]);
1454 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1455
1456 cs_array[j] = cmd_buffer->cs;
1457 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1458 can_patch = false;
1459 }
1460
1461 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1462 advance = MIN2(max_cs_submission,
1463 pSubmits[i].commandBufferCount - j);
1464 bool b = j == 0;
1465 bool e = j + advance == pSubmits[i].commandBufferCount;
1466
1467 if (queue->device->trace_bo)
1468 *queue->device->trace_id_ptr = 0;
1469
1470 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1471 advance, preamble_cs,
1472 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1473 b ? pSubmits[i].waitSemaphoreCount : 0,
1474 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1475 e ? pSubmits[i].signalSemaphoreCount : 0,
1476 can_patch, base_fence);
1477
1478 if (ret) {
1479 radv_loge("failed to submit CS %d\n", i);
1480 abort();
1481 }
1482 fence_emitted = true;
1483 if (queue->device->trace_bo) {
1484 bool success = queue->device->ws->ctx_wait_idle(
1485 queue->hw_ctx,
1486 radv_queue_family_to_ring(
1487 queue->queue_family_index),
1488 queue->queue_idx);
1489
1490 if (!success) { /* Hang */
1491 radv_dump_trace(queue->device, cs_array[j]);
1492 abort();
1493 }
1494 }
1495 }
1496 free(cs_array);
1497 }
1498
1499 if (fence) {
1500 if (!fence_emitted)
1501 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1502 &queue->device->empty_cs[queue->queue_family_index],
1503 1, NULL, NULL, 0, NULL, 0,
1504 false, base_fence);
1505
1506 fence->submitted = true;
1507 }
1508
1509 return VK_SUCCESS;
1510 }
1511
1512 VkResult radv_QueueWaitIdle(
1513 VkQueue _queue)
1514 {
1515 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1516
1517 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1518 radv_queue_family_to_ring(queue->queue_family_index),
1519 queue->queue_idx);
1520 return VK_SUCCESS;
1521 }
1522
1523 VkResult radv_DeviceWaitIdle(
1524 VkDevice _device)
1525 {
1526 RADV_FROM_HANDLE(radv_device, device, _device);
1527
1528 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1529 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1530 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1531 }
1532 }
1533 return VK_SUCCESS;
1534 }
1535
1536 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1537 VkInstance instance,
1538 const char* pName)
1539 {
1540 return radv_lookup_entrypoint(pName);
1541 }
1542
1543 /* The loader wants us to expose a second GetInstanceProcAddr function
1544 * to work around certain LD_PRELOAD issues seen in apps.
1545 */
1546 PUBLIC
1547 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1548 VkInstance instance,
1549 const char* pName);
1550
1551 PUBLIC
1552 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1553 VkInstance instance,
1554 const char* pName)
1555 {
1556 return radv_GetInstanceProcAddr(instance, pName);
1557 }
1558
1559 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1560 VkDevice device,
1561 const char* pName)
1562 {
1563 return radv_lookup_entrypoint(pName);
1564 }
1565
1566 VkResult radv_AllocateMemory(
1567 VkDevice _device,
1568 const VkMemoryAllocateInfo* pAllocateInfo,
1569 const VkAllocationCallbacks* pAllocator,
1570 VkDeviceMemory* pMem)
1571 {
1572 RADV_FROM_HANDLE(radv_device, device, _device);
1573 struct radv_device_memory *mem;
1574 VkResult result;
1575 enum radeon_bo_domain domain;
1576 uint32_t flags = 0;
1577 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1578
1579 if (pAllocateInfo->allocationSize == 0) {
1580 /* Apparently, this is allowed */
1581 *pMem = VK_NULL_HANDLE;
1582 return VK_SUCCESS;
1583 }
1584
1585 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1586 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1587 if (mem == NULL)
1588 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1589
1590 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1591 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1592 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1593 domain = RADEON_DOMAIN_GTT;
1594 else
1595 domain = RADEON_DOMAIN_VRAM;
1596
1597 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1598 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1599 else
1600 flags |= RADEON_FLAG_CPU_ACCESS;
1601
1602 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1603 flags |= RADEON_FLAG_GTT_WC;
1604
1605 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1606 domain, flags);
1607
1608 if (!mem->bo) {
1609 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1610 goto fail;
1611 }
1612 mem->type_index = pAllocateInfo->memoryTypeIndex;
1613
1614 *pMem = radv_device_memory_to_handle(mem);
1615
1616 return VK_SUCCESS;
1617
1618 fail:
1619 vk_free2(&device->alloc, pAllocator, mem);
1620
1621 return result;
1622 }
1623
1624 void radv_FreeMemory(
1625 VkDevice _device,
1626 VkDeviceMemory _mem,
1627 const VkAllocationCallbacks* pAllocator)
1628 {
1629 RADV_FROM_HANDLE(radv_device, device, _device);
1630 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1631
1632 if (mem == NULL)
1633 return;
1634
1635 device->ws->buffer_destroy(mem->bo);
1636 mem->bo = NULL;
1637
1638 vk_free2(&device->alloc, pAllocator, mem);
1639 }
1640
1641 VkResult radv_MapMemory(
1642 VkDevice _device,
1643 VkDeviceMemory _memory,
1644 VkDeviceSize offset,
1645 VkDeviceSize size,
1646 VkMemoryMapFlags flags,
1647 void** ppData)
1648 {
1649 RADV_FROM_HANDLE(radv_device, device, _device);
1650 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1651
1652 if (mem == NULL) {
1653 *ppData = NULL;
1654 return VK_SUCCESS;
1655 }
1656
1657 *ppData = device->ws->buffer_map(mem->bo);
1658 if (*ppData) {
1659 *ppData += offset;
1660 return VK_SUCCESS;
1661 }
1662
1663 return VK_ERROR_MEMORY_MAP_FAILED;
1664 }
1665
1666 void radv_UnmapMemory(
1667 VkDevice _device,
1668 VkDeviceMemory _memory)
1669 {
1670 RADV_FROM_HANDLE(radv_device, device, _device);
1671 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1672
1673 if (mem == NULL)
1674 return;
1675
1676 device->ws->buffer_unmap(mem->bo);
1677 }
1678
1679 VkResult radv_FlushMappedMemoryRanges(
1680 VkDevice _device,
1681 uint32_t memoryRangeCount,
1682 const VkMappedMemoryRange* pMemoryRanges)
1683 {
1684 return VK_SUCCESS;
1685 }
1686
1687 VkResult radv_InvalidateMappedMemoryRanges(
1688 VkDevice _device,
1689 uint32_t memoryRangeCount,
1690 const VkMappedMemoryRange* pMemoryRanges)
1691 {
1692 return VK_SUCCESS;
1693 }
1694
1695 void radv_GetBufferMemoryRequirements(
1696 VkDevice device,
1697 VkBuffer _buffer,
1698 VkMemoryRequirements* pMemoryRequirements)
1699 {
1700 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1701
1702 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1703
1704 pMemoryRequirements->size = buffer->size;
1705 pMemoryRequirements->alignment = 16;
1706 }
1707
1708 void radv_GetImageMemoryRequirements(
1709 VkDevice device,
1710 VkImage _image,
1711 VkMemoryRequirements* pMemoryRequirements)
1712 {
1713 RADV_FROM_HANDLE(radv_image, image, _image);
1714
1715 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1716
1717 pMemoryRequirements->size = image->size;
1718 pMemoryRequirements->alignment = image->alignment;
1719 }
1720
1721 void radv_GetImageSparseMemoryRequirements(
1722 VkDevice device,
1723 VkImage image,
1724 uint32_t* pSparseMemoryRequirementCount,
1725 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1726 {
1727 stub();
1728 }
1729
1730 void radv_GetDeviceMemoryCommitment(
1731 VkDevice device,
1732 VkDeviceMemory memory,
1733 VkDeviceSize* pCommittedMemoryInBytes)
1734 {
1735 *pCommittedMemoryInBytes = 0;
1736 }
1737
1738 VkResult radv_BindBufferMemory(
1739 VkDevice device,
1740 VkBuffer _buffer,
1741 VkDeviceMemory _memory,
1742 VkDeviceSize memoryOffset)
1743 {
1744 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1745 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1746
1747 if (mem) {
1748 buffer->bo = mem->bo;
1749 buffer->offset = memoryOffset;
1750 } else {
1751 buffer->bo = NULL;
1752 buffer->offset = 0;
1753 }
1754
1755 return VK_SUCCESS;
1756 }
1757
1758 VkResult radv_BindImageMemory(
1759 VkDevice device,
1760 VkImage _image,
1761 VkDeviceMemory _memory,
1762 VkDeviceSize memoryOffset)
1763 {
1764 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1765 RADV_FROM_HANDLE(radv_image, image, _image);
1766
1767 if (mem) {
1768 image->bo = mem->bo;
1769 image->offset = memoryOffset;
1770 } else {
1771 image->bo = NULL;
1772 image->offset = 0;
1773 }
1774
1775 return VK_SUCCESS;
1776 }
1777
1778 VkResult radv_QueueBindSparse(
1779 VkQueue queue,
1780 uint32_t bindInfoCount,
1781 const VkBindSparseInfo* pBindInfo,
1782 VkFence fence)
1783 {
1784 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1785 }
1786
1787 VkResult radv_CreateFence(
1788 VkDevice _device,
1789 const VkFenceCreateInfo* pCreateInfo,
1790 const VkAllocationCallbacks* pAllocator,
1791 VkFence* pFence)
1792 {
1793 RADV_FROM_HANDLE(radv_device, device, _device);
1794 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1795 sizeof(*fence), 8,
1796 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1797
1798 if (!fence)
1799 return VK_ERROR_OUT_OF_HOST_MEMORY;
1800
1801 memset(fence, 0, sizeof(*fence));
1802 fence->submitted = false;
1803 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1804 fence->fence = device->ws->create_fence();
1805 if (!fence->fence) {
1806 vk_free2(&device->alloc, pAllocator, fence);
1807 return VK_ERROR_OUT_OF_HOST_MEMORY;
1808 }
1809
1810 *pFence = radv_fence_to_handle(fence);
1811
1812 return VK_SUCCESS;
1813 }
1814
1815 void radv_DestroyFence(
1816 VkDevice _device,
1817 VkFence _fence,
1818 const VkAllocationCallbacks* pAllocator)
1819 {
1820 RADV_FROM_HANDLE(radv_device, device, _device);
1821 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1822
1823 if (!fence)
1824 return;
1825 device->ws->destroy_fence(fence->fence);
1826 vk_free2(&device->alloc, pAllocator, fence);
1827 }
1828
1829 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1830 {
1831 uint64_t current_time;
1832 struct timespec tv;
1833
1834 clock_gettime(CLOCK_MONOTONIC, &tv);
1835 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1836
1837 timeout = MIN2(UINT64_MAX - current_time, timeout);
1838
1839 return current_time + timeout;
1840 }
1841
1842 VkResult radv_WaitForFences(
1843 VkDevice _device,
1844 uint32_t fenceCount,
1845 const VkFence* pFences,
1846 VkBool32 waitAll,
1847 uint64_t timeout)
1848 {
1849 RADV_FROM_HANDLE(radv_device, device, _device);
1850 timeout = radv_get_absolute_timeout(timeout);
1851
1852 if (!waitAll && fenceCount > 1) {
1853 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1854 }
1855
1856 for (uint32_t i = 0; i < fenceCount; ++i) {
1857 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1858 bool expired = false;
1859
1860 if (fence->signalled)
1861 continue;
1862
1863 if (!fence->submitted)
1864 return VK_TIMEOUT;
1865
1866 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1867 if (!expired)
1868 return VK_TIMEOUT;
1869
1870 fence->signalled = true;
1871 }
1872
1873 return VK_SUCCESS;
1874 }
1875
1876 VkResult radv_ResetFences(VkDevice device,
1877 uint32_t fenceCount,
1878 const VkFence *pFences)
1879 {
1880 for (unsigned i = 0; i < fenceCount; ++i) {
1881 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1882 fence->submitted = fence->signalled = false;
1883 }
1884
1885 return VK_SUCCESS;
1886 }
1887
1888 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1889 {
1890 RADV_FROM_HANDLE(radv_device, device, _device);
1891 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1892
1893 if (fence->signalled)
1894 return VK_SUCCESS;
1895 if (!fence->submitted)
1896 return VK_NOT_READY;
1897
1898 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1899 return VK_NOT_READY;
1900
1901 return VK_SUCCESS;
1902 }
1903
1904
1905 // Queue semaphore functions
1906
1907 VkResult radv_CreateSemaphore(
1908 VkDevice _device,
1909 const VkSemaphoreCreateInfo* pCreateInfo,
1910 const VkAllocationCallbacks* pAllocator,
1911 VkSemaphore* pSemaphore)
1912 {
1913 RADV_FROM_HANDLE(radv_device, device, _device);
1914 struct radeon_winsys_sem *sem;
1915
1916 sem = device->ws->create_sem(device->ws);
1917 if (!sem)
1918 return VK_ERROR_OUT_OF_HOST_MEMORY;
1919
1920 *pSemaphore = (VkSemaphore)sem;
1921 return VK_SUCCESS;
1922 }
1923
1924 void radv_DestroySemaphore(
1925 VkDevice _device,
1926 VkSemaphore _semaphore,
1927 const VkAllocationCallbacks* pAllocator)
1928 {
1929 RADV_FROM_HANDLE(radv_device, device, _device);
1930 struct radeon_winsys_sem *sem;
1931 if (!_semaphore)
1932 return;
1933
1934 sem = (struct radeon_winsys_sem *)_semaphore;
1935 device->ws->destroy_sem(sem);
1936 }
1937
1938 VkResult radv_CreateEvent(
1939 VkDevice _device,
1940 const VkEventCreateInfo* pCreateInfo,
1941 const VkAllocationCallbacks* pAllocator,
1942 VkEvent* pEvent)
1943 {
1944 RADV_FROM_HANDLE(radv_device, device, _device);
1945 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1946 sizeof(*event), 8,
1947 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1948
1949 if (!event)
1950 return VK_ERROR_OUT_OF_HOST_MEMORY;
1951
1952 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1953 RADEON_DOMAIN_GTT,
1954 RADEON_FLAG_CPU_ACCESS);
1955 if (!event->bo) {
1956 vk_free2(&device->alloc, pAllocator, event);
1957 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1958 }
1959
1960 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1961
1962 *pEvent = radv_event_to_handle(event);
1963
1964 return VK_SUCCESS;
1965 }
1966
1967 void radv_DestroyEvent(
1968 VkDevice _device,
1969 VkEvent _event,
1970 const VkAllocationCallbacks* pAllocator)
1971 {
1972 RADV_FROM_HANDLE(radv_device, device, _device);
1973 RADV_FROM_HANDLE(radv_event, event, _event);
1974
1975 if (!event)
1976 return;
1977 device->ws->buffer_destroy(event->bo);
1978 vk_free2(&device->alloc, pAllocator, event);
1979 }
1980
1981 VkResult radv_GetEventStatus(
1982 VkDevice _device,
1983 VkEvent _event)
1984 {
1985 RADV_FROM_HANDLE(radv_event, event, _event);
1986
1987 if (*event->map == 1)
1988 return VK_EVENT_SET;
1989 return VK_EVENT_RESET;
1990 }
1991
1992 VkResult radv_SetEvent(
1993 VkDevice _device,
1994 VkEvent _event)
1995 {
1996 RADV_FROM_HANDLE(radv_event, event, _event);
1997 *event->map = 1;
1998
1999 return VK_SUCCESS;
2000 }
2001
2002 VkResult radv_ResetEvent(
2003 VkDevice _device,
2004 VkEvent _event)
2005 {
2006 RADV_FROM_HANDLE(radv_event, event, _event);
2007 *event->map = 0;
2008
2009 return VK_SUCCESS;
2010 }
2011
2012 VkResult radv_CreateBuffer(
2013 VkDevice _device,
2014 const VkBufferCreateInfo* pCreateInfo,
2015 const VkAllocationCallbacks* pAllocator,
2016 VkBuffer* pBuffer)
2017 {
2018 RADV_FROM_HANDLE(radv_device, device, _device);
2019 struct radv_buffer *buffer;
2020
2021 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2022
2023 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2024 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2025 if (buffer == NULL)
2026 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2027
2028 buffer->size = pCreateInfo->size;
2029 buffer->usage = pCreateInfo->usage;
2030 buffer->bo = NULL;
2031 buffer->offset = 0;
2032
2033 *pBuffer = radv_buffer_to_handle(buffer);
2034
2035 return VK_SUCCESS;
2036 }
2037
2038 void radv_DestroyBuffer(
2039 VkDevice _device,
2040 VkBuffer _buffer,
2041 const VkAllocationCallbacks* pAllocator)
2042 {
2043 RADV_FROM_HANDLE(radv_device, device, _device);
2044 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2045
2046 if (!buffer)
2047 return;
2048
2049 vk_free2(&device->alloc, pAllocator, buffer);
2050 }
2051
2052 static inline unsigned
2053 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2054 {
2055 if (stencil)
2056 return image->surface.stencil_tiling_index[level];
2057 else
2058 return image->surface.tiling_index[level];
2059 }
2060
2061 static void
2062 radv_initialise_color_surface(struct radv_device *device,
2063 struct radv_color_buffer_info *cb,
2064 struct radv_image_view *iview)
2065 {
2066 const struct vk_format_description *desc;
2067 unsigned ntype, format, swap, endian;
2068 unsigned blend_clamp = 0, blend_bypass = 0;
2069 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2070 uint64_t va;
2071 const struct radeon_surf *surf = &iview->image->surface;
2072 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2073
2074 desc = vk_format_description(iview->vk_format);
2075
2076 memset(cb, 0, sizeof(*cb));
2077
2078 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2079 va += level_info->offset;
2080 cb->cb_color_base = va >> 8;
2081
2082 /* CMASK variables */
2083 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2084 va += iview->image->cmask.offset;
2085 cb->cb_color_cmask = va >> 8;
2086 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2087
2088 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2089 va += iview->image->dcc_offset;
2090 cb->cb_dcc_base = va >> 8;
2091
2092 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2093 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2094 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2095
2096 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2097 pitch_tile_max = level_info->nblk_x / 8 - 1;
2098 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2099 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2100
2101 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2102 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2103
2104 /* Intensity is implemented as Red, so treat it that way. */
2105 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2106 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2107
2108 if (iview->image->samples > 1) {
2109 unsigned log_samples = util_logbase2(iview->image->samples);
2110
2111 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2112 S_028C74_NUM_FRAGMENTS(log_samples);
2113 }
2114
2115 if (iview->image->fmask.size) {
2116 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2117 if (device->physical_device->rad_info.chip_class >= CIK)
2118 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2119 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2120 cb->cb_color_fmask = va >> 8;
2121 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2122 } else {
2123 /* This must be set for fast clear to work without FMASK. */
2124 if (device->physical_device->rad_info.chip_class >= CIK)
2125 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2126 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2127 cb->cb_color_fmask = cb->cb_color_base;
2128 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2129 }
2130
2131 ntype = radv_translate_color_numformat(iview->vk_format,
2132 desc,
2133 vk_format_get_first_non_void_channel(iview->vk_format));
2134 format = radv_translate_colorformat(iview->vk_format);
2135 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2136 radv_finishme("Illegal color\n");
2137 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2138 endian = radv_colorformat_endian_swap(format);
2139
2140 /* blend clamp should be set for all NORM/SRGB types */
2141 if (ntype == V_028C70_NUMBER_UNORM ||
2142 ntype == V_028C70_NUMBER_SNORM ||
2143 ntype == V_028C70_NUMBER_SRGB)
2144 blend_clamp = 1;
2145
2146 /* set blend bypass according to docs if SINT/UINT or
2147 8/24 COLOR variants */
2148 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2149 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2150 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2151 blend_clamp = 0;
2152 blend_bypass = 1;
2153 }
2154 #if 0
2155 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2156 (format == V_028C70_COLOR_8 ||
2157 format == V_028C70_COLOR_8_8 ||
2158 format == V_028C70_COLOR_8_8_8_8))
2159 ->color_is_int8 = true;
2160 #endif
2161 cb->cb_color_info = S_028C70_FORMAT(format) |
2162 S_028C70_COMP_SWAP(swap) |
2163 S_028C70_BLEND_CLAMP(blend_clamp) |
2164 S_028C70_BLEND_BYPASS(blend_bypass) |
2165 S_028C70_SIMPLE_FLOAT(1) |
2166 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2167 ntype != V_028C70_NUMBER_SNORM &&
2168 ntype != V_028C70_NUMBER_SRGB &&
2169 format != V_028C70_COLOR_8_24 &&
2170 format != V_028C70_COLOR_24_8) |
2171 S_028C70_NUMBER_TYPE(ntype) |
2172 S_028C70_ENDIAN(endian);
2173 if (iview->image->samples > 1)
2174 if (iview->image->fmask.size)
2175 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2176
2177 if (iview->image->cmask.size &&
2178 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2179 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2180
2181 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2182 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2183
2184 if (device->physical_device->rad_info.chip_class >= VI) {
2185 unsigned max_uncompressed_block_size = 2;
2186 if (iview->image->samples > 1) {
2187 if (iview->image->surface.bpe == 1)
2188 max_uncompressed_block_size = 0;
2189 else if (iview->image->surface.bpe == 2)
2190 max_uncompressed_block_size = 1;
2191 }
2192
2193 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2194 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2195 }
2196
2197 /* This must be set for fast clear to work without FMASK. */
2198 if (!iview->image->fmask.size &&
2199 device->physical_device->rad_info.chip_class == SI) {
2200 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2201 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2202 }
2203 }
2204
2205 static void
2206 radv_initialise_ds_surface(struct radv_device *device,
2207 struct radv_ds_buffer_info *ds,
2208 struct radv_image_view *iview)
2209 {
2210 unsigned level = iview->base_mip;
2211 unsigned format;
2212 uint64_t va, s_offs, z_offs;
2213 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2214 memset(ds, 0, sizeof(*ds));
2215 switch (iview->vk_format) {
2216 case VK_FORMAT_D24_UNORM_S8_UINT:
2217 case VK_FORMAT_X8_D24_UNORM_PACK32:
2218 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2219 ds->offset_scale = 2.0f;
2220 break;
2221 case VK_FORMAT_D16_UNORM:
2222 case VK_FORMAT_D16_UNORM_S8_UINT:
2223 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2224 ds->offset_scale = 4.0f;
2225 break;
2226 case VK_FORMAT_D32_SFLOAT:
2227 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2228 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2229 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2230 ds->offset_scale = 1.0f;
2231 break;
2232 default:
2233 break;
2234 }
2235
2236 format = radv_translate_dbformat(iview->vk_format);
2237 if (format == V_028040_Z_INVALID) {
2238 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2239 }
2240
2241 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2242 s_offs = z_offs = va;
2243 z_offs += iview->image->surface.level[level].offset;
2244 s_offs += iview->image->surface.stencil_level[level].offset;
2245
2246 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2247 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2248 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2249 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2250 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2251
2252 if (iview->image->samples > 1)
2253 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2254
2255 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2256 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2257 else
2258 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2259
2260 if (device->physical_device->rad_info.chip_class >= CIK) {
2261 struct radeon_info *info = &device->physical_device->rad_info;
2262 unsigned tiling_index = iview->image->surface.tiling_index[level];
2263 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2264 unsigned macro_index = iview->image->surface.macro_tile_index;
2265 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2266 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2267 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2268
2269 ds->db_depth_info |=
2270 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2271 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2272 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2273 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2274 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2275 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2276 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2277 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2278 } else {
2279 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2280 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2281 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2282 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2283 }
2284
2285 if (iview->image->htile.size && !level) {
2286 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2287 S_028040_ALLOW_EXPCLEAR(1);
2288
2289 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2290 /* Workaround: For a not yet understood reason, the
2291 * combination of MSAA, fast stencil clear and stencil
2292 * decompress messes with subsequent stencil buffer
2293 * uses. Problem was reproduced on Verde, Bonaire,
2294 * Tonga, and Carrizo.
2295 *
2296 * Disabling EXPCLEAR works around the problem.
2297 *
2298 * Check piglit's arb_texture_multisample-stencil-clear
2299 * test if you want to try changing this.
2300 */
2301 if (iview->image->samples <= 1)
2302 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2303 } else
2304 /* Use all of the htile_buffer for depth if there's no stencil. */
2305 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2306
2307 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2308 iview->image->htile.offset;
2309 ds->db_htile_data_base = va >> 8;
2310 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2311 } else {
2312 ds->db_htile_data_base = 0;
2313 ds->db_htile_surface = 0;
2314 }
2315
2316 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2317 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2318
2319 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2320 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2321 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2322 }
2323
2324 VkResult radv_CreateFramebuffer(
2325 VkDevice _device,
2326 const VkFramebufferCreateInfo* pCreateInfo,
2327 const VkAllocationCallbacks* pAllocator,
2328 VkFramebuffer* pFramebuffer)
2329 {
2330 RADV_FROM_HANDLE(radv_device, device, _device);
2331 struct radv_framebuffer *framebuffer;
2332
2333 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2334
2335 size_t size = sizeof(*framebuffer) +
2336 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2337 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2338 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2339 if (framebuffer == NULL)
2340 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2341
2342 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2343 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2344 VkImageView _iview = pCreateInfo->pAttachments[i];
2345 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2346 framebuffer->attachments[i].attachment = iview;
2347 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2348 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2349 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2350 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2351 }
2352 }
2353
2354 framebuffer->width = pCreateInfo->width;
2355 framebuffer->height = pCreateInfo->height;
2356 framebuffer->layers = pCreateInfo->layers;
2357
2358 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2359 return VK_SUCCESS;
2360 }
2361
2362 void radv_DestroyFramebuffer(
2363 VkDevice _device,
2364 VkFramebuffer _fb,
2365 const VkAllocationCallbacks* pAllocator)
2366 {
2367 RADV_FROM_HANDLE(radv_device, device, _device);
2368 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2369
2370 if (!fb)
2371 return;
2372 vk_free2(&device->alloc, pAllocator, fb);
2373 }
2374
2375 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2376 {
2377 switch (address_mode) {
2378 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2379 return V_008F30_SQ_TEX_WRAP;
2380 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2381 return V_008F30_SQ_TEX_MIRROR;
2382 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2383 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2384 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2385 return V_008F30_SQ_TEX_CLAMP_BORDER;
2386 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2387 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2388 default:
2389 unreachable("illegal tex wrap mode");
2390 break;
2391 }
2392 }
2393
2394 static unsigned
2395 radv_tex_compare(VkCompareOp op)
2396 {
2397 switch (op) {
2398 case VK_COMPARE_OP_NEVER:
2399 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2400 case VK_COMPARE_OP_LESS:
2401 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2402 case VK_COMPARE_OP_EQUAL:
2403 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2404 case VK_COMPARE_OP_LESS_OR_EQUAL:
2405 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2406 case VK_COMPARE_OP_GREATER:
2407 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2408 case VK_COMPARE_OP_NOT_EQUAL:
2409 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2410 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2411 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2412 case VK_COMPARE_OP_ALWAYS:
2413 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2414 default:
2415 unreachable("illegal compare mode");
2416 break;
2417 }
2418 }
2419
2420 static unsigned
2421 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2422 {
2423 switch (filter) {
2424 case VK_FILTER_NEAREST:
2425 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2426 V_008F38_SQ_TEX_XY_FILTER_POINT);
2427 case VK_FILTER_LINEAR:
2428 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2429 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2430 case VK_FILTER_CUBIC_IMG:
2431 default:
2432 fprintf(stderr, "illegal texture filter");
2433 return 0;
2434 }
2435 }
2436
2437 static unsigned
2438 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2439 {
2440 switch (mode) {
2441 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2442 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2443 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2444 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2445 default:
2446 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2447 }
2448 }
2449
2450 static unsigned
2451 radv_tex_bordercolor(VkBorderColor bcolor)
2452 {
2453 switch (bcolor) {
2454 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2455 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2456 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2457 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2458 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2459 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2460 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2461 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2462 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2463 default:
2464 break;
2465 }
2466 return 0;
2467 }
2468
2469 static unsigned
2470 radv_tex_aniso_filter(unsigned filter)
2471 {
2472 if (filter < 2)
2473 return 0;
2474 if (filter < 4)
2475 return 1;
2476 if (filter < 8)
2477 return 2;
2478 if (filter < 16)
2479 return 3;
2480 return 4;
2481 }
2482
2483 static void
2484 radv_init_sampler(struct radv_device *device,
2485 struct radv_sampler *sampler,
2486 const VkSamplerCreateInfo *pCreateInfo)
2487 {
2488 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2489 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2490 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2491 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2492
2493 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2494 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2495 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2496 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2497 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2498 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2499 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2500 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2501 S_008F30_DISABLE_CUBE_WRAP(0) |
2502 S_008F30_COMPAT_MODE(is_vi));
2503 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2504 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2505 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2506 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2507 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2508 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2509 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2510 S_008F38_MIP_POINT_PRECLAMP(1) |
2511 S_008F38_DISABLE_LSB_CEIL(1) |
2512 S_008F38_FILTER_PREC_FIX(1) |
2513 S_008F38_ANISO_OVERRIDE(is_vi));
2514 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2515 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2516 }
2517
2518 VkResult radv_CreateSampler(
2519 VkDevice _device,
2520 const VkSamplerCreateInfo* pCreateInfo,
2521 const VkAllocationCallbacks* pAllocator,
2522 VkSampler* pSampler)
2523 {
2524 RADV_FROM_HANDLE(radv_device, device, _device);
2525 struct radv_sampler *sampler;
2526
2527 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2528
2529 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2530 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2531 if (!sampler)
2532 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2533
2534 radv_init_sampler(device, sampler, pCreateInfo);
2535 *pSampler = radv_sampler_to_handle(sampler);
2536
2537 return VK_SUCCESS;
2538 }
2539
2540 void radv_DestroySampler(
2541 VkDevice _device,
2542 VkSampler _sampler,
2543 const VkAllocationCallbacks* pAllocator)
2544 {
2545 RADV_FROM_HANDLE(radv_device, device, _device);
2546 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2547
2548 if (!sampler)
2549 return;
2550 vk_free2(&device->alloc, pAllocator, sampler);
2551 }
2552
2553
2554 /* vk_icd.h does not declare this function, so we declare it here to
2555 * suppress Wmissing-prototypes.
2556 */
2557 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2558 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2559
2560 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2561 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2562 {
2563 /* For the full details on loader interface versioning, see
2564 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2565 * What follows is a condensed summary, to help you navigate the large and
2566 * confusing official doc.
2567 *
2568 * - Loader interface v0 is incompatible with later versions. We don't
2569 * support it.
2570 *
2571 * - In loader interface v1:
2572 * - The first ICD entrypoint called by the loader is
2573 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2574 * entrypoint.
2575 * - The ICD must statically expose no other Vulkan symbol unless it is
2576 * linked with -Bsymbolic.
2577 * - Each dispatchable Vulkan handle created by the ICD must be
2578 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2579 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2580 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2581 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2582 * such loader-managed surfaces.
2583 *
2584 * - Loader interface v2 differs from v1 in:
2585 * - The first ICD entrypoint called by the loader is
2586 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2587 * statically expose this entrypoint.
2588 *
2589 * - Loader interface v3 differs from v2 in:
2590 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2591 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2592 * because the loader no longer does so.
2593 */
2594 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2595 return VK_SUCCESS;
2596 }