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radv/gfx10: add Wave32 support for compute shaders
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 /* Determine the number of threads per wave for all stages. */
387 device->cs_wave_size = 64;
388
389 if (device->rad_info.chip_class >= GFX10) {
390 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
391 device->cs_wave_size = 32;
392 }
393
394 radv_physical_device_init_mem_types(device);
395 radv_fill_device_extension_table(device, &device->supported_extensions);
396
397 device->bus_info = *drm_device->businfo.pci;
398
399 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
400 ac_print_gpu_info(&device->rad_info);
401
402 /* The WSI is structured as a layer on top of the driver, so this has
403 * to be the last part of initialization (at least until we get other
404 * semi-layers).
405 */
406 result = radv_init_wsi(device);
407 if (result != VK_SUCCESS) {
408 device->ws->destroy(device->ws);
409 vk_error(instance, result);
410 goto fail;
411 }
412
413 return VK_SUCCESS;
414
415 fail:
416 close(fd);
417 if (master_fd != -1)
418 close(master_fd);
419 return result;
420 }
421
422 static void
423 radv_physical_device_finish(struct radv_physical_device *device)
424 {
425 radv_finish_wsi(device);
426 device->ws->destroy(device->ws);
427 disk_cache_destroy(device->disk_cache);
428 close(device->local_fd);
429 if (device->master_fd != -1)
430 close(device->master_fd);
431 }
432
433 static void *
434 default_alloc_func(void *pUserData, size_t size, size_t align,
435 VkSystemAllocationScope allocationScope)
436 {
437 return malloc(size);
438 }
439
440 static void *
441 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
442 size_t align, VkSystemAllocationScope allocationScope)
443 {
444 return realloc(pOriginal, size);
445 }
446
447 static void
448 default_free_func(void *pUserData, void *pMemory)
449 {
450 free(pMemory);
451 }
452
453 static const VkAllocationCallbacks default_alloc = {
454 .pUserData = NULL,
455 .pfnAllocation = default_alloc_func,
456 .pfnReallocation = default_realloc_func,
457 .pfnFree = default_free_func,
458 };
459
460 static const struct debug_control radv_debug_options[] = {
461 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
462 {"nodcc", RADV_DEBUG_NO_DCC},
463 {"shaders", RADV_DEBUG_DUMP_SHADERS},
464 {"nocache", RADV_DEBUG_NO_CACHE},
465 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
466 {"nohiz", RADV_DEBUG_NO_HIZ},
467 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
468 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
469 {"allbos", RADV_DEBUG_ALL_BOS},
470 {"noibs", RADV_DEBUG_NO_IBS},
471 {"spirv", RADV_DEBUG_DUMP_SPIRV},
472 {"vmfaults", RADV_DEBUG_VM_FAULTS},
473 {"zerovram", RADV_DEBUG_ZERO_VRAM},
474 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
475 {"nosisched", RADV_DEBUG_NO_SISCHED},
476 {"preoptir", RADV_DEBUG_PREOPTIR},
477 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
478 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
479 {"info", RADV_DEBUG_INFO},
480 {"errors", RADV_DEBUG_ERRORS},
481 {"startup", RADV_DEBUG_STARTUP},
482 {"checkir", RADV_DEBUG_CHECKIR},
483 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
484 {"nobinning", RADV_DEBUG_NOBINNING},
485 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
486 {"nongg", RADV_DEBUG_NO_NGG},
487 {NULL, 0}
488 };
489
490 const char *
491 radv_get_debug_option_name(int id)
492 {
493 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
494 return radv_debug_options[id].string;
495 }
496
497 static const struct debug_control radv_perftest_options[] = {
498 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
499 {"sisched", RADV_PERFTEST_SISCHED},
500 {"localbos", RADV_PERFTEST_LOCAL_BOS},
501 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
502 {"bolist", RADV_PERFTEST_BO_LIST},
503 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
504 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
505 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
506 {NULL, 0}
507 };
508
509 const char *
510 radv_get_perftest_option_name(int id)
511 {
512 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
513 return radv_perftest_options[id].string;
514 }
515
516 static void
517 radv_handle_per_app_options(struct radv_instance *instance,
518 const VkApplicationInfo *info)
519 {
520 const char *name = info ? info->pApplicationName : NULL;
521
522 if (!name)
523 return;
524
525 if (!strcmp(name, "Talos - Linux - 32bit") ||
526 !strcmp(name, "Talos - Linux - 64bit")) {
527 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
528 /* Force enable LLVM sisched for Talos because it looks
529 * safe and it gives few more FPS.
530 */
531 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
532 }
533 } else if (!strcmp(name, "DOOM_VFR")) {
534 /* Work around a Doom VFR game bug */
535 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
536 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
537 /* Workaround for a WaW hazard when LLVM moves/merges
538 * load/store memory operations.
539 * See https://reviews.llvm.org/D61313
540 */
541 if (HAVE_LLVM < 0x900)
542 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
543 }
544 }
545
546 static int radv_get_instance_extension_index(const char *name)
547 {
548 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
549 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
550 return i;
551 }
552 return -1;
553 }
554
555 static const char radv_dri_options_xml[] =
556 DRI_CONF_BEGIN
557 DRI_CONF_SECTION_QUALITY
558 DRI_CONF_ADAPTIVE_SYNC("true")
559 DRI_CONF_SECTION_END
560 DRI_CONF_END;
561
562 static void radv_init_dri_options(struct radv_instance *instance)
563 {
564 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
565 driParseConfigFiles(&instance->dri_options,
566 &instance->available_dri_options,
567 0, "radv", NULL);
568 }
569
570 VkResult radv_CreateInstance(
571 const VkInstanceCreateInfo* pCreateInfo,
572 const VkAllocationCallbacks* pAllocator,
573 VkInstance* pInstance)
574 {
575 struct radv_instance *instance;
576 VkResult result;
577
578 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
579
580 uint32_t client_version;
581 if (pCreateInfo->pApplicationInfo &&
582 pCreateInfo->pApplicationInfo->apiVersion != 0) {
583 client_version = pCreateInfo->pApplicationInfo->apiVersion;
584 } else {
585 client_version = VK_API_VERSION_1_0;
586 }
587
588 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
589 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
590 if (!instance)
591 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
592
593 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
594
595 if (pAllocator)
596 instance->alloc = *pAllocator;
597 else
598 instance->alloc = default_alloc;
599
600 instance->apiVersion = client_version;
601 instance->physicalDeviceCount = -1;
602
603 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
604 radv_debug_options);
605
606 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
607 radv_perftest_options);
608
609
610 if (instance->debug_flags & RADV_DEBUG_STARTUP)
611 radv_logi("Created an instance");
612
613 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
614 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
615 int index = radv_get_instance_extension_index(ext_name);
616
617 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
618 vk_free2(&default_alloc, pAllocator, instance);
619 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
620 }
621
622 instance->enabled_extensions.extensions[index] = true;
623 }
624
625 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
626 if (result != VK_SUCCESS) {
627 vk_free2(&default_alloc, pAllocator, instance);
628 return vk_error(instance, result);
629 }
630
631 _mesa_locale_init();
632 glsl_type_singleton_init_or_ref();
633
634 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
635
636 radv_init_dri_options(instance);
637 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
638
639 *pInstance = radv_instance_to_handle(instance);
640
641 return VK_SUCCESS;
642 }
643
644 void radv_DestroyInstance(
645 VkInstance _instance,
646 const VkAllocationCallbacks* pAllocator)
647 {
648 RADV_FROM_HANDLE(radv_instance, instance, _instance);
649
650 if (!instance)
651 return;
652
653 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
654 radv_physical_device_finish(instance->physicalDevices + i);
655 }
656
657 VG(VALGRIND_DESTROY_MEMPOOL(instance));
658
659 glsl_type_singleton_decref();
660 _mesa_locale_fini();
661
662 driDestroyOptionCache(&instance->dri_options);
663 driDestroyOptionInfo(&instance->available_dri_options);
664
665 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
666
667 vk_free(&instance->alloc, instance);
668 }
669
670 static VkResult
671 radv_enumerate_devices(struct radv_instance *instance)
672 {
673 /* TODO: Check for more devices ? */
674 drmDevicePtr devices[8];
675 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
676 int max_devices;
677
678 instance->physicalDeviceCount = 0;
679
680 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
681
682 if (instance->debug_flags & RADV_DEBUG_STARTUP)
683 radv_logi("Found %d drm nodes", max_devices);
684
685 if (max_devices < 1)
686 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
687
688 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
689 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
690 devices[i]->bustype == DRM_BUS_PCI &&
691 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
692
693 result = radv_physical_device_init(instance->physicalDevices +
694 instance->physicalDeviceCount,
695 instance,
696 devices[i]);
697 if (result == VK_SUCCESS)
698 ++instance->physicalDeviceCount;
699 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
700 break;
701 }
702 }
703 drmFreeDevices(devices, max_devices);
704
705 return result;
706 }
707
708 VkResult radv_EnumeratePhysicalDevices(
709 VkInstance _instance,
710 uint32_t* pPhysicalDeviceCount,
711 VkPhysicalDevice* pPhysicalDevices)
712 {
713 RADV_FROM_HANDLE(radv_instance, instance, _instance);
714 VkResult result;
715
716 if (instance->physicalDeviceCount < 0) {
717 result = radv_enumerate_devices(instance);
718 if (result != VK_SUCCESS &&
719 result != VK_ERROR_INCOMPATIBLE_DRIVER)
720 return result;
721 }
722
723 if (!pPhysicalDevices) {
724 *pPhysicalDeviceCount = instance->physicalDeviceCount;
725 } else {
726 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
727 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
728 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
729 }
730
731 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
732 : VK_SUCCESS;
733 }
734
735 VkResult radv_EnumeratePhysicalDeviceGroups(
736 VkInstance _instance,
737 uint32_t* pPhysicalDeviceGroupCount,
738 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
739 {
740 RADV_FROM_HANDLE(radv_instance, instance, _instance);
741 VkResult result;
742
743 if (instance->physicalDeviceCount < 0) {
744 result = radv_enumerate_devices(instance);
745 if (result != VK_SUCCESS &&
746 result != VK_ERROR_INCOMPATIBLE_DRIVER)
747 return result;
748 }
749
750 if (!pPhysicalDeviceGroupProperties) {
751 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
752 } else {
753 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
754 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
755 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
756 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
757 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
758 }
759 }
760 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
761 : VK_SUCCESS;
762 }
763
764 void radv_GetPhysicalDeviceFeatures(
765 VkPhysicalDevice physicalDevice,
766 VkPhysicalDeviceFeatures* pFeatures)
767 {
768 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
769 memset(pFeatures, 0, sizeof(*pFeatures));
770
771 *pFeatures = (VkPhysicalDeviceFeatures) {
772 .robustBufferAccess = true,
773 .fullDrawIndexUint32 = true,
774 .imageCubeArray = true,
775 .independentBlend = true,
776 .geometryShader = true,
777 .tessellationShader = true,
778 .sampleRateShading = true,
779 .dualSrcBlend = true,
780 .logicOp = true,
781 .multiDrawIndirect = true,
782 .drawIndirectFirstInstance = true,
783 .depthClamp = true,
784 .depthBiasClamp = true,
785 .fillModeNonSolid = true,
786 .depthBounds = true,
787 .wideLines = true,
788 .largePoints = true,
789 .alphaToOne = true,
790 .multiViewport = true,
791 .samplerAnisotropy = true,
792 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
793 .textureCompressionASTC_LDR = false,
794 .textureCompressionBC = true,
795 .occlusionQueryPrecise = true,
796 .pipelineStatisticsQuery = true,
797 .vertexPipelineStoresAndAtomics = true,
798 .fragmentStoresAndAtomics = true,
799 .shaderTessellationAndGeometryPointSize = true,
800 .shaderImageGatherExtended = true,
801 .shaderStorageImageExtendedFormats = true,
802 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
803 .shaderUniformBufferArrayDynamicIndexing = true,
804 .shaderSampledImageArrayDynamicIndexing = true,
805 .shaderStorageBufferArrayDynamicIndexing = true,
806 .shaderStorageImageArrayDynamicIndexing = true,
807 .shaderStorageImageReadWithoutFormat = true,
808 .shaderStorageImageWriteWithoutFormat = true,
809 .shaderClipDistance = true,
810 .shaderCullDistance = true,
811 .shaderFloat64 = true,
812 .shaderInt64 = true,
813 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
814 .sparseBinding = true,
815 .variableMultisampleRate = true,
816 .inheritedQueries = true,
817 };
818 }
819
820 void radv_GetPhysicalDeviceFeatures2(
821 VkPhysicalDevice physicalDevice,
822 VkPhysicalDeviceFeatures2 *pFeatures)
823 {
824 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
825 vk_foreach_struct(ext, pFeatures->pNext) {
826 switch (ext->sType) {
827 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
828 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
829 features->variablePointersStorageBuffer = true;
830 features->variablePointers = true;
831 break;
832 }
833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
834 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
835 features->multiview = true;
836 features->multiviewGeometryShader = true;
837 features->multiviewTessellationShader = true;
838 break;
839 }
840 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
841 VkPhysicalDeviceShaderDrawParametersFeatures *features =
842 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
843 features->shaderDrawParameters = true;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
847 VkPhysicalDeviceProtectedMemoryFeatures *features =
848 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
849 features->protectedMemory = false;
850 break;
851 }
852 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
853 VkPhysicalDevice16BitStorageFeatures *features =
854 (VkPhysicalDevice16BitStorageFeatures*)ext;
855 bool enabled = pdevice->rad_info.chip_class >= GFX8;
856 features->storageBuffer16BitAccess = enabled;
857 features->uniformAndStorageBuffer16BitAccess = enabled;
858 features->storagePushConstant16 = enabled;
859 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
860 break;
861 }
862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
863 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
864 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
865 features->samplerYcbcrConversion = true;
866 break;
867 }
868 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
869 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
870 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
871 features->shaderInputAttachmentArrayDynamicIndexing = true;
872 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
873 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
874 features->shaderUniformBufferArrayNonUniformIndexing = true;
875 features->shaderSampledImageArrayNonUniformIndexing = true;
876 features->shaderStorageBufferArrayNonUniformIndexing = true;
877 features->shaderStorageImageArrayNonUniformIndexing = true;
878 features->shaderInputAttachmentArrayNonUniformIndexing = true;
879 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
880 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
881 features->descriptorBindingUniformBufferUpdateAfterBind = true;
882 features->descriptorBindingSampledImageUpdateAfterBind = true;
883 features->descriptorBindingStorageImageUpdateAfterBind = true;
884 features->descriptorBindingStorageBufferUpdateAfterBind = true;
885 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
886 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
887 features->descriptorBindingUpdateUnusedWhilePending = true;
888 features->descriptorBindingPartiallyBound = true;
889 features->descriptorBindingVariableDescriptorCount = true;
890 features->runtimeDescriptorArray = true;
891 break;
892 }
893 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
894 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
895 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
896 features->conditionalRendering = true;
897 features->inheritedConditionalRendering = false;
898 break;
899 }
900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
901 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
902 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
903 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
904 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
905 break;
906 }
907 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
908 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
909 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
910 features->transformFeedback = true;
911 features->geometryStreams = true;
912 break;
913 }
914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
915 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
916 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
917 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
918 break;
919 }
920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
921 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
922 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
923 features->memoryPriority = VK_TRUE;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
927 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
928 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
929 features->bufferDeviceAddress = true;
930 features->bufferDeviceAddressCaptureReplay = false;
931 features->bufferDeviceAddressMultiDevice = false;
932 break;
933 }
934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
935 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
936 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
937 features->depthClipEnable = true;
938 break;
939 }
940 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
941 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
942 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
943 features->hostQueryReset = true;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
947 VkPhysicalDevice8BitStorageFeaturesKHR *features =
948 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
949 bool enabled = pdevice->rad_info.chip_class >= GFX8;
950 features->storageBuffer8BitAccess = enabled;
951 features->uniformAndStorageBuffer8BitAccess = enabled;
952 features->storagePushConstant8 = enabled;
953 break;
954 }
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
956 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
957 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
958 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
959 features->shaderInt8 = true;
960 break;
961 }
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
963 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
964 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
965 /* TODO: Enable this once the driver supports 64-bit
966 * compare&swap atomic operations.
967 */
968 features->shaderBufferInt64Atomics = false;
969 features->shaderSharedInt64Atomics = false;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
973 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
974 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
975
976 features->inlineUniformBlock = true;
977 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
981 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
982 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
983 features->computeDerivativeGroupQuads = false;
984 features->computeDerivativeGroupLinear = true;
985 break;
986 }
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
988 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
989 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
990 features->ycbcrImageArrays = true;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
994 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
995 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
996 features->uniformBufferStandardLayout = true;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1000 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1001 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1002 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1003 break;
1004 }
1005 default:
1006 break;
1007 }
1008 }
1009 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1010 }
1011
1012 void radv_GetPhysicalDeviceProperties(
1013 VkPhysicalDevice physicalDevice,
1014 VkPhysicalDeviceProperties* pProperties)
1015 {
1016 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1017 VkSampleCountFlags sample_counts = 0xf;
1018
1019 /* make sure that the entire descriptor set is addressable with a signed
1020 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1021 * be at most 2 GiB. the combined image & samples object count as one of
1022 * both. This limit is for the pipeline layout, not for the set layout, but
1023 * there is no set limit, so we just set a pipeline limit. I don't think
1024 * any app is going to hit this soon. */
1025 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1026 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1027 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1028 32 /* sampler, largest when combined with image */ +
1029 64 /* sampled image */ +
1030 64 /* storage image */);
1031
1032 VkPhysicalDeviceLimits limits = {
1033 .maxImageDimension1D = (1 << 14),
1034 .maxImageDimension2D = (1 << 14),
1035 .maxImageDimension3D = (1 << 11),
1036 .maxImageDimensionCube = (1 << 14),
1037 .maxImageArrayLayers = (1 << 11),
1038 .maxTexelBufferElements = 128 * 1024 * 1024,
1039 .maxUniformBufferRange = UINT32_MAX,
1040 .maxStorageBufferRange = UINT32_MAX,
1041 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1042 .maxMemoryAllocationCount = UINT32_MAX,
1043 .maxSamplerAllocationCount = 64 * 1024,
1044 .bufferImageGranularity = 64, /* A cache line */
1045 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1046 .maxBoundDescriptorSets = MAX_SETS,
1047 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1048 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1049 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1050 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1051 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1052 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1053 .maxPerStageResources = max_descriptor_set_size,
1054 .maxDescriptorSetSamplers = max_descriptor_set_size,
1055 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1056 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1057 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1058 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1059 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1060 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1061 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1062 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1063 .maxVertexInputBindings = MAX_VBS,
1064 .maxVertexInputAttributeOffset = 2047,
1065 .maxVertexInputBindingStride = 2048,
1066 .maxVertexOutputComponents = 128,
1067 .maxTessellationGenerationLevel = 64,
1068 .maxTessellationPatchSize = 32,
1069 .maxTessellationControlPerVertexInputComponents = 128,
1070 .maxTessellationControlPerVertexOutputComponents = 128,
1071 .maxTessellationControlPerPatchOutputComponents = 120,
1072 .maxTessellationControlTotalOutputComponents = 4096,
1073 .maxTessellationEvaluationInputComponents = 128,
1074 .maxTessellationEvaluationOutputComponents = 128,
1075 .maxGeometryShaderInvocations = 127,
1076 .maxGeometryInputComponents = 64,
1077 .maxGeometryOutputComponents = 128,
1078 .maxGeometryOutputVertices = 256,
1079 .maxGeometryTotalOutputComponents = 1024,
1080 .maxFragmentInputComponents = 128,
1081 .maxFragmentOutputAttachments = 8,
1082 .maxFragmentDualSrcAttachments = 1,
1083 .maxFragmentCombinedOutputResources = 8,
1084 .maxComputeSharedMemorySize = 32768,
1085 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1086 .maxComputeWorkGroupInvocations = 2048,
1087 .maxComputeWorkGroupSize = {
1088 2048,
1089 2048,
1090 2048
1091 },
1092 .subPixelPrecisionBits = 8,
1093 .subTexelPrecisionBits = 8,
1094 .mipmapPrecisionBits = 8,
1095 .maxDrawIndexedIndexValue = UINT32_MAX,
1096 .maxDrawIndirectCount = UINT32_MAX,
1097 .maxSamplerLodBias = 16,
1098 .maxSamplerAnisotropy = 16,
1099 .maxViewports = MAX_VIEWPORTS,
1100 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1101 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1102 .viewportSubPixelBits = 8,
1103 .minMemoryMapAlignment = 4096, /* A page */
1104 .minTexelBufferOffsetAlignment = 1,
1105 .minUniformBufferOffsetAlignment = 4,
1106 .minStorageBufferOffsetAlignment = 4,
1107 .minTexelOffset = -32,
1108 .maxTexelOffset = 31,
1109 .minTexelGatherOffset = -32,
1110 .maxTexelGatherOffset = 31,
1111 .minInterpolationOffset = -2,
1112 .maxInterpolationOffset = 2,
1113 .subPixelInterpolationOffsetBits = 8,
1114 .maxFramebufferWidth = (1 << 14),
1115 .maxFramebufferHeight = (1 << 14),
1116 .maxFramebufferLayers = (1 << 10),
1117 .framebufferColorSampleCounts = sample_counts,
1118 .framebufferDepthSampleCounts = sample_counts,
1119 .framebufferStencilSampleCounts = sample_counts,
1120 .framebufferNoAttachmentsSampleCounts = sample_counts,
1121 .maxColorAttachments = MAX_RTS,
1122 .sampledImageColorSampleCounts = sample_counts,
1123 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1124 .sampledImageDepthSampleCounts = sample_counts,
1125 .sampledImageStencilSampleCounts = sample_counts,
1126 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1127 .maxSampleMaskWords = 1,
1128 .timestampComputeAndGraphics = true,
1129 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1130 .maxClipDistances = 8,
1131 .maxCullDistances = 8,
1132 .maxCombinedClipAndCullDistances = 8,
1133 .discreteQueuePriorities = 2,
1134 .pointSizeRange = { 0.0, 8192.0 },
1135 .lineWidthRange = { 0.0, 7.9921875 },
1136 .pointSizeGranularity = (1.0 / 8.0),
1137 .lineWidthGranularity = (1.0 / 128.0),
1138 .strictLines = false, /* FINISHME */
1139 .standardSampleLocations = true,
1140 .optimalBufferCopyOffsetAlignment = 128,
1141 .optimalBufferCopyRowPitchAlignment = 128,
1142 .nonCoherentAtomSize = 64,
1143 };
1144
1145 *pProperties = (VkPhysicalDeviceProperties) {
1146 .apiVersion = radv_physical_device_api_version(pdevice),
1147 .driverVersion = vk_get_driver_version(),
1148 .vendorID = ATI_VENDOR_ID,
1149 .deviceID = pdevice->rad_info.pci_id,
1150 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1151 .limits = limits,
1152 .sparseProperties = {0},
1153 };
1154
1155 strcpy(pProperties->deviceName, pdevice->name);
1156 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1157 }
1158
1159 void radv_GetPhysicalDeviceProperties2(
1160 VkPhysicalDevice physicalDevice,
1161 VkPhysicalDeviceProperties2 *pProperties)
1162 {
1163 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1164 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1165
1166 vk_foreach_struct(ext, pProperties->pNext) {
1167 switch (ext->sType) {
1168 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1169 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1170 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1171 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1172 break;
1173 }
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1175 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1176 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1177 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1178 properties->deviceLUIDValid = false;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1182 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1183 properties->maxMultiviewViewCount = MAX_VIEWS;
1184 properties->maxMultiviewInstanceIndex = INT_MAX;
1185 break;
1186 }
1187 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1188 VkPhysicalDevicePointClippingProperties *properties =
1189 (VkPhysicalDevicePointClippingProperties*)ext;
1190 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1191 break;
1192 }
1193 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1194 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1195 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1196 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1197 break;
1198 }
1199 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1200 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1201 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1202 properties->minImportedHostPointerAlignment = 4096;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1206 VkPhysicalDeviceSubgroupProperties *properties =
1207 (VkPhysicalDeviceSubgroupProperties*)ext;
1208 properties->subgroupSize = 64;
1209 properties->supportedStages = VK_SHADER_STAGE_ALL;
1210 properties->supportedOperations =
1211 VK_SUBGROUP_FEATURE_BASIC_BIT |
1212 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1213 VK_SUBGROUP_FEATURE_QUAD_BIT |
1214 VK_SUBGROUP_FEATURE_VOTE_BIT;
1215 if (pdevice->rad_info.chip_class >= GFX8) {
1216 properties->supportedOperations |=
1217 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1218 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1219 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1220 }
1221 properties->quadOperationsInAllStages = true;
1222 break;
1223 }
1224 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1225 VkPhysicalDeviceMaintenance3Properties *properties =
1226 (VkPhysicalDeviceMaintenance3Properties*)ext;
1227 /* Make sure everything is addressable by a signed 32-bit int, and
1228 * our largest descriptors are 96 bytes. */
1229 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1230 /* Our buffer size fields allow only this much */
1231 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1232 break;
1233 }
1234 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1235 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1236 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1237 /* GFX6-8 only support single channel min/max filter. */
1238 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1239 properties->filterMinmaxSingleComponentFormats = true;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1243 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1244 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1245
1246 /* Shader engines. */
1247 properties->shaderEngineCount =
1248 pdevice->rad_info.max_se;
1249 properties->shaderArraysPerEngineCount =
1250 pdevice->rad_info.max_sh_per_se;
1251 properties->computeUnitsPerShaderArray =
1252 pdevice->rad_info.num_good_cu_per_sh;
1253 properties->simdPerComputeUnit = 4;
1254 properties->wavefrontsPerSimd =
1255 pdevice->rad_info.family == CHIP_TONGA ||
1256 pdevice->rad_info.family == CHIP_ICELAND ||
1257 pdevice->rad_info.family == CHIP_POLARIS10 ||
1258 pdevice->rad_info.family == CHIP_POLARIS11 ||
1259 pdevice->rad_info.family == CHIP_POLARIS12 ||
1260 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1261 properties->wavefrontSize = 64;
1262
1263 /* SGPR. */
1264 properties->sgprsPerSimd =
1265 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1266 properties->minSgprAllocation =
1267 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1268 properties->maxSgprAllocation =
1269 pdevice->rad_info.family == CHIP_TONGA ||
1270 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1271 properties->sgprAllocationGranularity =
1272 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1273
1274 /* VGPR. */
1275 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1276 properties->minVgprAllocation = 4;
1277 properties->maxVgprAllocation = 256;
1278 properties->vgprAllocationGranularity = 4;
1279 break;
1280 }
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1282 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1283 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1284 properties->maxVertexAttribDivisor = UINT32_MAX;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1288 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1289 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1290 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1291 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1292 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1293 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1294 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1295 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1296 properties->robustBufferAccessUpdateAfterBind = false;
1297 properties->quadDivergentImplicitLod = false;
1298
1299 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1300 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1301 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1302 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1303 32 /* sampler, largest when combined with image */ +
1304 64 /* sampled image */ +
1305 64 /* storage image */);
1306 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1307 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1308 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1309 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1310 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1311 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1312 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1313 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1314 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1315 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1316 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1317 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1318 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1319 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1320 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1321 break;
1322 }
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1324 VkPhysicalDeviceProtectedMemoryProperties *properties =
1325 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1326 properties->protectedNoFault = false;
1327 break;
1328 }
1329 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1330 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1331 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1332 properties->primitiveOverestimationSize = 0;
1333 properties->maxExtraPrimitiveOverestimationSize = 0;
1334 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1335 properties->primitiveUnderestimation = VK_FALSE;
1336 properties->conservativePointAndLineRasterization = VK_FALSE;
1337 properties->degenerateTrianglesRasterized = VK_FALSE;
1338 properties->degenerateLinesRasterized = VK_FALSE;
1339 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1340 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1344 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1345 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1346 properties->pciDomain = pdevice->bus_info.domain;
1347 properties->pciBus = pdevice->bus_info.bus;
1348 properties->pciDevice = pdevice->bus_info.dev;
1349 properties->pciFunction = pdevice->bus_info.func;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1353 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1354 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1355
1356 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1357 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1358 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1359 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1360 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1361
1362 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1363 .major = 1,
1364 .minor = 1,
1365 .subminor = 2,
1366 .patch = 0,
1367 };
1368 break;
1369 }
1370 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1371 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1372 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1373 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1374 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1375 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1376 properties->maxTransformFeedbackStreamDataSize = 512;
1377 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1378 properties->maxTransformFeedbackBufferDataStride = 512;
1379 properties->transformFeedbackQueries = true;
1380 properties->transformFeedbackStreamsLinesTriangles = true;
1381 properties->transformFeedbackRasterizationStreamSelect = false;
1382 properties->transformFeedbackDraw = true;
1383 break;
1384 }
1385 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1386 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1387 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1388
1389 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1390 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1391 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1392 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1393 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1394 break;
1395 }
1396 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1397 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1398 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1399 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1400 VK_SAMPLE_COUNT_4_BIT |
1401 VK_SAMPLE_COUNT_8_BIT;
1402 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1403 properties->sampleLocationCoordinateRange[0] = 0.0f;
1404 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1405 properties->sampleLocationSubPixelBits = 4;
1406 properties->variableSampleLocations = VK_FALSE;
1407 break;
1408 }
1409 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1410 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1411 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1412
1413 /* We support all of the depth resolve modes */
1414 properties->supportedDepthResolveModes =
1415 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1416 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1417 VK_RESOLVE_MODE_MIN_BIT_KHR |
1418 VK_RESOLVE_MODE_MAX_BIT_KHR;
1419
1420 /* Average doesn't make sense for stencil so we don't support that */
1421 properties->supportedStencilResolveModes =
1422 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1423 VK_RESOLVE_MODE_MIN_BIT_KHR |
1424 VK_RESOLVE_MODE_MAX_BIT_KHR;
1425
1426 properties->independentResolveNone = VK_TRUE;
1427 properties->independentResolve = VK_TRUE;
1428 break;
1429 }
1430 default:
1431 break;
1432 }
1433 }
1434 }
1435
1436 static void radv_get_physical_device_queue_family_properties(
1437 struct radv_physical_device* pdevice,
1438 uint32_t* pCount,
1439 VkQueueFamilyProperties** pQueueFamilyProperties)
1440 {
1441 int num_queue_families = 1;
1442 int idx;
1443 if (pdevice->rad_info.num_compute_rings > 0 &&
1444 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1445 num_queue_families++;
1446
1447 if (pQueueFamilyProperties == NULL) {
1448 *pCount = num_queue_families;
1449 return;
1450 }
1451
1452 if (!*pCount)
1453 return;
1454
1455 idx = 0;
1456 if (*pCount >= 1) {
1457 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1458 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1459 VK_QUEUE_COMPUTE_BIT |
1460 VK_QUEUE_TRANSFER_BIT |
1461 VK_QUEUE_SPARSE_BINDING_BIT,
1462 .queueCount = 1,
1463 .timestampValidBits = 64,
1464 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1465 };
1466 idx++;
1467 }
1468
1469 if (pdevice->rad_info.num_compute_rings > 0 &&
1470 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1471 if (*pCount > idx) {
1472 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1473 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1474 VK_QUEUE_TRANSFER_BIT |
1475 VK_QUEUE_SPARSE_BINDING_BIT,
1476 .queueCount = pdevice->rad_info.num_compute_rings,
1477 .timestampValidBits = 64,
1478 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1479 };
1480 idx++;
1481 }
1482 }
1483 *pCount = idx;
1484 }
1485
1486 void radv_GetPhysicalDeviceQueueFamilyProperties(
1487 VkPhysicalDevice physicalDevice,
1488 uint32_t* pCount,
1489 VkQueueFamilyProperties* pQueueFamilyProperties)
1490 {
1491 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1492 if (!pQueueFamilyProperties) {
1493 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1494 return;
1495 }
1496 VkQueueFamilyProperties *properties[] = {
1497 pQueueFamilyProperties + 0,
1498 pQueueFamilyProperties + 1,
1499 pQueueFamilyProperties + 2,
1500 };
1501 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1502 assert(*pCount <= 3);
1503 }
1504
1505 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1506 VkPhysicalDevice physicalDevice,
1507 uint32_t* pCount,
1508 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1509 {
1510 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1511 if (!pQueueFamilyProperties) {
1512 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1513 return;
1514 }
1515 VkQueueFamilyProperties *properties[] = {
1516 &pQueueFamilyProperties[0].queueFamilyProperties,
1517 &pQueueFamilyProperties[1].queueFamilyProperties,
1518 &pQueueFamilyProperties[2].queueFamilyProperties,
1519 };
1520 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1521 assert(*pCount <= 3);
1522 }
1523
1524 void radv_GetPhysicalDeviceMemoryProperties(
1525 VkPhysicalDevice physicalDevice,
1526 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1527 {
1528 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1529
1530 *pMemoryProperties = physical_device->memory_properties;
1531 }
1532
1533 static void
1534 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1535 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1536 {
1537 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1538 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1539 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1540 uint64_t vram_size = radv_get_vram_size(device);
1541 uint64_t gtt_size = device->rad_info.gart_size;
1542 uint64_t heap_budget, heap_usage;
1543
1544 /* For all memory heaps, the computation of budget is as follow:
1545 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1546 *
1547 * The Vulkan spec 1.1.97 says that the budget should include any
1548 * currently allocated device memory.
1549 *
1550 * Note that the application heap usages are not really accurate (eg.
1551 * in presence of shared buffers).
1552 */
1553 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1554 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1555
1556 switch (device->mem_type_indices[i]) {
1557 case RADV_MEM_TYPE_VRAM:
1558 heap_usage = device->ws->query_value(device->ws,
1559 RADEON_ALLOCATED_VRAM);
1560
1561 heap_budget = vram_size -
1562 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1563 heap_usage;
1564
1565 memoryBudget->heapBudget[heap_index] = heap_budget;
1566 memoryBudget->heapUsage[heap_index] = heap_usage;
1567 break;
1568 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1569 heap_usage = device->ws->query_value(device->ws,
1570 RADEON_ALLOCATED_VRAM_VIS);
1571
1572 heap_budget = visible_vram_size -
1573 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1574 heap_usage;
1575
1576 memoryBudget->heapBudget[heap_index] = heap_budget;
1577 memoryBudget->heapUsage[heap_index] = heap_usage;
1578 break;
1579 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1580 heap_usage = device->ws->query_value(device->ws,
1581 RADEON_ALLOCATED_GTT);
1582
1583 heap_budget = gtt_size -
1584 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1585 heap_usage;
1586
1587 memoryBudget->heapBudget[heap_index] = heap_budget;
1588 memoryBudget->heapUsage[heap_index] = heap_usage;
1589 break;
1590 default:
1591 break;
1592 }
1593 }
1594
1595 /* The heapBudget and heapUsage values must be zero for array elements
1596 * greater than or equal to
1597 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1598 */
1599 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1600 memoryBudget->heapBudget[i] = 0;
1601 memoryBudget->heapUsage[i] = 0;
1602 }
1603 }
1604
1605 void radv_GetPhysicalDeviceMemoryProperties2(
1606 VkPhysicalDevice physicalDevice,
1607 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1608 {
1609 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1610 &pMemoryProperties->memoryProperties);
1611
1612 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1613 vk_find_struct(pMemoryProperties->pNext,
1614 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1615 if (memory_budget)
1616 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1617 }
1618
1619 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1620 VkDevice _device,
1621 VkExternalMemoryHandleTypeFlagBits handleType,
1622 const void *pHostPointer,
1623 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1624 {
1625 RADV_FROM_HANDLE(radv_device, device, _device);
1626
1627 switch (handleType)
1628 {
1629 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1630 const struct radv_physical_device *physical_device = device->physical_device;
1631 uint32_t memoryTypeBits = 0;
1632 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1633 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1634 memoryTypeBits = (1 << i);
1635 break;
1636 }
1637 }
1638 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1639 return VK_SUCCESS;
1640 }
1641 default:
1642 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1643 }
1644 }
1645
1646 static enum radeon_ctx_priority
1647 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1648 {
1649 /* Default to MEDIUM when a specific global priority isn't requested */
1650 if (!pObj)
1651 return RADEON_CTX_PRIORITY_MEDIUM;
1652
1653 switch(pObj->globalPriority) {
1654 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1655 return RADEON_CTX_PRIORITY_REALTIME;
1656 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1657 return RADEON_CTX_PRIORITY_HIGH;
1658 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1659 return RADEON_CTX_PRIORITY_MEDIUM;
1660 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1661 return RADEON_CTX_PRIORITY_LOW;
1662 default:
1663 unreachable("Illegal global priority value");
1664 return RADEON_CTX_PRIORITY_INVALID;
1665 }
1666 }
1667
1668 static int
1669 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1670 uint32_t queue_family_index, int idx,
1671 VkDeviceQueueCreateFlags flags,
1672 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1673 {
1674 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1675 queue->device = device;
1676 queue->queue_family_index = queue_family_index;
1677 queue->queue_idx = idx;
1678 queue->priority = radv_get_queue_global_priority(global_priority);
1679 queue->flags = flags;
1680
1681 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1682 if (!queue->hw_ctx)
1683 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1684
1685 return VK_SUCCESS;
1686 }
1687
1688 static void
1689 radv_queue_finish(struct radv_queue *queue)
1690 {
1691 if (queue->hw_ctx)
1692 queue->device->ws->ctx_destroy(queue->hw_ctx);
1693
1694 if (queue->initial_full_flush_preamble_cs)
1695 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1696 if (queue->initial_preamble_cs)
1697 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1698 if (queue->continue_preamble_cs)
1699 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1700 if (queue->descriptor_bo)
1701 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1702 if (queue->scratch_bo)
1703 queue->device->ws->buffer_destroy(queue->scratch_bo);
1704 if (queue->esgs_ring_bo)
1705 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1706 if (queue->gsvs_ring_bo)
1707 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1708 if (queue->tess_rings_bo)
1709 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1710 if (queue->compute_scratch_bo)
1711 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1712 }
1713
1714 static void
1715 radv_bo_list_init(struct radv_bo_list *bo_list)
1716 {
1717 pthread_mutex_init(&bo_list->mutex, NULL);
1718 bo_list->list.count = bo_list->capacity = 0;
1719 bo_list->list.bos = NULL;
1720 }
1721
1722 static void
1723 radv_bo_list_finish(struct radv_bo_list *bo_list)
1724 {
1725 free(bo_list->list.bos);
1726 pthread_mutex_destroy(&bo_list->mutex);
1727 }
1728
1729 static VkResult radv_bo_list_add(struct radv_device *device,
1730 struct radeon_winsys_bo *bo)
1731 {
1732 struct radv_bo_list *bo_list = &device->bo_list;
1733
1734 if (bo->is_local)
1735 return VK_SUCCESS;
1736
1737 if (unlikely(!device->use_global_bo_list))
1738 return VK_SUCCESS;
1739
1740 pthread_mutex_lock(&bo_list->mutex);
1741 if (bo_list->list.count == bo_list->capacity) {
1742 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1743 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1744
1745 if (!data) {
1746 pthread_mutex_unlock(&bo_list->mutex);
1747 return VK_ERROR_OUT_OF_HOST_MEMORY;
1748 }
1749
1750 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1751 bo_list->capacity = capacity;
1752 }
1753
1754 bo_list->list.bos[bo_list->list.count++] = bo;
1755 pthread_mutex_unlock(&bo_list->mutex);
1756 return VK_SUCCESS;
1757 }
1758
1759 static void radv_bo_list_remove(struct radv_device *device,
1760 struct radeon_winsys_bo *bo)
1761 {
1762 struct radv_bo_list *bo_list = &device->bo_list;
1763
1764 if (bo->is_local)
1765 return;
1766
1767 if (unlikely(!device->use_global_bo_list))
1768 return;
1769
1770 pthread_mutex_lock(&bo_list->mutex);
1771 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1772 if (bo_list->list.bos[i] == bo) {
1773 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1774 --bo_list->list.count;
1775 break;
1776 }
1777 }
1778 pthread_mutex_unlock(&bo_list->mutex);
1779 }
1780
1781 static void
1782 radv_device_init_gs_info(struct radv_device *device)
1783 {
1784 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1785 device->physical_device->rad_info.family);
1786 }
1787
1788 static int radv_get_device_extension_index(const char *name)
1789 {
1790 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1791 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1792 return i;
1793 }
1794 return -1;
1795 }
1796
1797 static int
1798 radv_get_int_debug_option(const char *name, int default_value)
1799 {
1800 const char *str;
1801 int result;
1802
1803 str = getenv(name);
1804 if (!str) {
1805 result = default_value;
1806 } else {
1807 char *endptr;
1808
1809 result = strtol(str, &endptr, 0);
1810 if (str == endptr) {
1811 /* No digits founs. */
1812 result = default_value;
1813 }
1814 }
1815
1816 return result;
1817 }
1818
1819 VkResult radv_CreateDevice(
1820 VkPhysicalDevice physicalDevice,
1821 const VkDeviceCreateInfo* pCreateInfo,
1822 const VkAllocationCallbacks* pAllocator,
1823 VkDevice* pDevice)
1824 {
1825 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1826 VkResult result;
1827 struct radv_device *device;
1828
1829 bool keep_shader_info = false;
1830
1831 /* Check enabled features */
1832 if (pCreateInfo->pEnabledFeatures) {
1833 VkPhysicalDeviceFeatures supported_features;
1834 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1835 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1836 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1837 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1838 for (uint32_t i = 0; i < num_features; i++) {
1839 if (enabled_feature[i] && !supported_feature[i])
1840 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1841 }
1842 }
1843
1844 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1845 sizeof(*device), 8,
1846 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1847 if (!device)
1848 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1849
1850 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1851 device->instance = physical_device->instance;
1852 device->physical_device = physical_device;
1853
1854 device->ws = physical_device->ws;
1855 if (pAllocator)
1856 device->alloc = *pAllocator;
1857 else
1858 device->alloc = physical_device->instance->alloc;
1859
1860 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1861 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1862 int index = radv_get_device_extension_index(ext_name);
1863 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1864 vk_free(&device->alloc, device);
1865 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1866 }
1867
1868 device->enabled_extensions.extensions[index] = true;
1869 }
1870
1871 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1872
1873 /* With update after bind we can't attach bo's to the command buffer
1874 * from the descriptor set anymore, so we have to use a global BO list.
1875 */
1876 device->use_global_bo_list =
1877 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1878 device->enabled_extensions.EXT_descriptor_indexing ||
1879 device->enabled_extensions.EXT_buffer_device_address;
1880
1881 mtx_init(&device->shader_slab_mutex, mtx_plain);
1882 list_inithead(&device->shader_slabs);
1883
1884 radv_bo_list_init(&device->bo_list);
1885
1886 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1887 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1888 uint32_t qfi = queue_create->queueFamilyIndex;
1889 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1890 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1891
1892 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1893
1894 device->queues[qfi] = vk_alloc(&device->alloc,
1895 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1896 if (!device->queues[qfi]) {
1897 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1898 goto fail;
1899 }
1900
1901 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1902
1903 device->queue_count[qfi] = queue_create->queueCount;
1904
1905 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1906 result = radv_queue_init(device, &device->queues[qfi][q],
1907 qfi, q, queue_create->flags,
1908 global_priority);
1909 if (result != VK_SUCCESS)
1910 goto fail;
1911 }
1912 }
1913
1914 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1915 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1916
1917 /* Disabled and not implemented for now. */
1918 device->dfsm_allowed = device->pbb_allowed &&
1919 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1920 device->physical_device->rad_info.family == CHIP_RAVEN2);
1921
1922 #ifdef ANDROID
1923 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1924 #endif
1925
1926 /* The maximum number of scratch waves. Scratch space isn't divided
1927 * evenly between CUs. The number is only a function of the number of CUs.
1928 * We can decrease the constant to decrease the scratch buffer size.
1929 *
1930 * sctx->scratch_waves must be >= the maximum possible size of
1931 * 1 threadgroup, so that the hw doesn't hang from being unable
1932 * to start any.
1933 *
1934 * The recommended value is 4 per CU at most. Higher numbers don't
1935 * bring much benefit, but they still occupy chip resources (think
1936 * async compute). I've seen ~2% performance difference between 4 and 32.
1937 */
1938 uint32_t max_threads_per_block = 2048;
1939 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1940 max_threads_per_block / 64);
1941
1942 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1943 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1944
1945 if (device->physical_device->rad_info.chip_class >= GFX7) {
1946 /* If the KMD allows it (there is a KMD hw register for it),
1947 * allow launching waves out-of-order.
1948 */
1949 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1950 }
1951
1952 radv_device_init_gs_info(device);
1953
1954 device->tess_offchip_block_dw_size =
1955 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1956 device->has_distributed_tess =
1957 device->physical_device->rad_info.chip_class >= GFX8 &&
1958 device->physical_device->rad_info.max_se >= 2;
1959
1960 if (getenv("RADV_TRACE_FILE")) {
1961 const char *filename = getenv("RADV_TRACE_FILE");
1962
1963 keep_shader_info = true;
1964
1965 if (!radv_init_trace(device))
1966 goto fail;
1967
1968 fprintf(stderr, "*****************************************************************************\n");
1969 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1970 fprintf(stderr, "*****************************************************************************\n");
1971
1972 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1973 radv_dump_enabled_options(device, stderr);
1974 }
1975
1976 device->keep_shader_info = keep_shader_info;
1977
1978 result = radv_device_init_meta(device);
1979 if (result != VK_SUCCESS)
1980 goto fail;
1981
1982 radv_device_init_msaa(device);
1983
1984 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1985 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1986 switch (family) {
1987 case RADV_QUEUE_GENERAL:
1988 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1989 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1990 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1991 break;
1992 case RADV_QUEUE_COMPUTE:
1993 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1994 radeon_emit(device->empty_cs[family], 0);
1995 break;
1996 }
1997 device->ws->cs_finalize(device->empty_cs[family]);
1998 }
1999
2000 if (device->physical_device->rad_info.chip_class >= GFX7)
2001 cik_create_gfx_config(device);
2002
2003 VkPipelineCacheCreateInfo ci;
2004 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2005 ci.pNext = NULL;
2006 ci.flags = 0;
2007 ci.pInitialData = NULL;
2008 ci.initialDataSize = 0;
2009 VkPipelineCache pc;
2010 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2011 &ci, NULL, &pc);
2012 if (result != VK_SUCCESS)
2013 goto fail_meta;
2014
2015 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2016
2017 device->force_aniso =
2018 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2019 if (device->force_aniso >= 0) {
2020 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2021 1 << util_logbase2(device->force_aniso));
2022 }
2023
2024 *pDevice = radv_device_to_handle(device);
2025 return VK_SUCCESS;
2026
2027 fail_meta:
2028 radv_device_finish_meta(device);
2029 fail:
2030 radv_bo_list_finish(&device->bo_list);
2031
2032 if (device->trace_bo)
2033 device->ws->buffer_destroy(device->trace_bo);
2034
2035 if (device->gfx_init)
2036 device->ws->buffer_destroy(device->gfx_init);
2037
2038 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2039 for (unsigned q = 0; q < device->queue_count[i]; q++)
2040 radv_queue_finish(&device->queues[i][q]);
2041 if (device->queue_count[i])
2042 vk_free(&device->alloc, device->queues[i]);
2043 }
2044
2045 vk_free(&device->alloc, device);
2046 return result;
2047 }
2048
2049 void radv_DestroyDevice(
2050 VkDevice _device,
2051 const VkAllocationCallbacks* pAllocator)
2052 {
2053 RADV_FROM_HANDLE(radv_device, device, _device);
2054
2055 if (!device)
2056 return;
2057
2058 if (device->trace_bo)
2059 device->ws->buffer_destroy(device->trace_bo);
2060
2061 if (device->gfx_init)
2062 device->ws->buffer_destroy(device->gfx_init);
2063
2064 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2065 for (unsigned q = 0; q < device->queue_count[i]; q++)
2066 radv_queue_finish(&device->queues[i][q]);
2067 if (device->queue_count[i])
2068 vk_free(&device->alloc, device->queues[i]);
2069 if (device->empty_cs[i])
2070 device->ws->cs_destroy(device->empty_cs[i]);
2071 }
2072 radv_device_finish_meta(device);
2073
2074 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2075 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2076
2077 radv_destroy_shader_slabs(device);
2078
2079 radv_bo_list_finish(&device->bo_list);
2080 vk_free(&device->alloc, device);
2081 }
2082
2083 VkResult radv_EnumerateInstanceLayerProperties(
2084 uint32_t* pPropertyCount,
2085 VkLayerProperties* pProperties)
2086 {
2087 if (pProperties == NULL) {
2088 *pPropertyCount = 0;
2089 return VK_SUCCESS;
2090 }
2091
2092 /* None supported at this time */
2093 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2094 }
2095
2096 VkResult radv_EnumerateDeviceLayerProperties(
2097 VkPhysicalDevice physicalDevice,
2098 uint32_t* pPropertyCount,
2099 VkLayerProperties* pProperties)
2100 {
2101 if (pProperties == NULL) {
2102 *pPropertyCount = 0;
2103 return VK_SUCCESS;
2104 }
2105
2106 /* None supported at this time */
2107 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2108 }
2109
2110 void radv_GetDeviceQueue2(
2111 VkDevice _device,
2112 const VkDeviceQueueInfo2* pQueueInfo,
2113 VkQueue* pQueue)
2114 {
2115 RADV_FROM_HANDLE(radv_device, device, _device);
2116 struct radv_queue *queue;
2117
2118 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2119 if (pQueueInfo->flags != queue->flags) {
2120 /* From the Vulkan 1.1.70 spec:
2121 *
2122 * "The queue returned by vkGetDeviceQueue2 must have the same
2123 * flags value from this structure as that used at device
2124 * creation time in a VkDeviceQueueCreateInfo instance. If no
2125 * matching flags were specified at device creation time then
2126 * pQueue will return VK_NULL_HANDLE."
2127 */
2128 *pQueue = VK_NULL_HANDLE;
2129 return;
2130 }
2131
2132 *pQueue = radv_queue_to_handle(queue);
2133 }
2134
2135 void radv_GetDeviceQueue(
2136 VkDevice _device,
2137 uint32_t queueFamilyIndex,
2138 uint32_t queueIndex,
2139 VkQueue* pQueue)
2140 {
2141 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2142 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2143 .queueFamilyIndex = queueFamilyIndex,
2144 .queueIndex = queueIndex
2145 };
2146
2147 radv_GetDeviceQueue2(_device, &info, pQueue);
2148 }
2149
2150 static void
2151 fill_geom_tess_rings(struct radv_queue *queue,
2152 uint32_t *map,
2153 bool add_sample_positions,
2154 uint32_t esgs_ring_size,
2155 struct radeon_winsys_bo *esgs_ring_bo,
2156 uint32_t gsvs_ring_size,
2157 struct radeon_winsys_bo *gsvs_ring_bo,
2158 uint32_t tess_factor_ring_size,
2159 uint32_t tess_offchip_ring_offset,
2160 uint32_t tess_offchip_ring_size,
2161 struct radeon_winsys_bo *tess_rings_bo)
2162 {
2163 uint32_t *desc = &map[4];
2164
2165 if (esgs_ring_bo) {
2166 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2167
2168 /* stride 0, num records - size, add tid, swizzle, elsize4,
2169 index stride 64 */
2170 desc[0] = esgs_va;
2171 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2172 S_008F04_SWIZZLE_ENABLE(true);
2173 desc[2] = esgs_ring_size;
2174 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2175 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2176 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2177 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2178 S_008F0C_INDEX_STRIDE(3) |
2179 S_008F0C_ADD_TID_ENABLE(1);
2180
2181 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2182 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2183 S_008F0C_OOB_SELECT(2) |
2184 S_008F0C_RESOURCE_LEVEL(1);
2185 } else {
2186 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2187 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2188 S_008F0C_ELEMENT_SIZE(1);
2189 }
2190
2191 /* GS entry for ES->GS ring */
2192 /* stride 0, num records - size, elsize0,
2193 index stride 0 */
2194 desc[4] = esgs_va;
2195 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2196 desc[6] = esgs_ring_size;
2197 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2198 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2199 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2200 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2201
2202 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2203 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2204 S_008F0C_OOB_SELECT(2) |
2205 S_008F0C_RESOURCE_LEVEL(1);
2206 } else {
2207 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2208 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2209 }
2210 }
2211
2212 desc += 8;
2213
2214 if (gsvs_ring_bo) {
2215 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2216
2217 /* VS entry for GS->VS ring */
2218 /* stride 0, num records - size, elsize0,
2219 index stride 0 */
2220 desc[0] = gsvs_va;
2221 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2222 desc[2] = gsvs_ring_size;
2223 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2224 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2225 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2226 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2227
2228 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2229 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2230 S_008F0C_OOB_SELECT(2) |
2231 S_008F0C_RESOURCE_LEVEL(1);
2232 } else {
2233 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2235 }
2236
2237 /* stride gsvs_itemsize, num records 64
2238 elsize 4, index stride 16 */
2239 /* shader will patch stride and desc[2] */
2240 desc[4] = gsvs_va;
2241 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2242 S_008F04_SWIZZLE_ENABLE(1);
2243 desc[6] = 0;
2244 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2245 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2246 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2247 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2248 S_008F0C_INDEX_STRIDE(1) |
2249 S_008F0C_ADD_TID_ENABLE(true);
2250
2251 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2252 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2253 S_008F0C_OOB_SELECT(2) |
2254 S_008F0C_RESOURCE_LEVEL(1);
2255 } else {
2256 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2258 S_008F0C_ELEMENT_SIZE(1);
2259 }
2260
2261 }
2262
2263 desc += 8;
2264
2265 if (tess_rings_bo) {
2266 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2267 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2268
2269 desc[0] = tess_va;
2270 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2271 desc[2] = tess_factor_ring_size;
2272 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2273 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2274 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2275 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2276
2277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2278 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2279 S_008F0C_OOB_SELECT(3) |
2280 S_008F0C_RESOURCE_LEVEL(1);
2281 } else {
2282 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2284 }
2285
2286 desc[4] = tess_offchip_va;
2287 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2288 desc[6] = tess_offchip_ring_size;
2289 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2290 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2291 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2292 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2293
2294 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2295 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2296 S_008F0C_OOB_SELECT(3) |
2297 S_008F0C_RESOURCE_LEVEL(1);
2298 } else {
2299 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2300 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2301 }
2302 }
2303
2304 desc += 8;
2305
2306 if (add_sample_positions) {
2307 /* add sample positions after all rings */
2308 memcpy(desc, queue->device->sample_locations_1x, 8);
2309 desc += 2;
2310 memcpy(desc, queue->device->sample_locations_2x, 16);
2311 desc += 4;
2312 memcpy(desc, queue->device->sample_locations_4x, 32);
2313 desc += 8;
2314 memcpy(desc, queue->device->sample_locations_8x, 64);
2315 }
2316 }
2317
2318 static unsigned
2319 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2320 {
2321 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2322 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2323 device->physical_device->rad_info.family != CHIP_STONEY;
2324 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2325 unsigned max_offchip_buffers;
2326 unsigned offchip_granularity;
2327 unsigned hs_offchip_param;
2328
2329 /*
2330 * Per RadeonSI:
2331 * This must be one less than the maximum number due to a hw limitation.
2332 * Various hardware bugs need thGFX7
2333 *
2334 * Per AMDVLK:
2335 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2336 * Gfx7 should limit max_offchip_buffers to 508
2337 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2338 *
2339 * Follow AMDVLK here.
2340 */
2341 if (device->physical_device->rad_info.chip_class >= GFX10) {
2342 max_offchip_buffers_per_se = 256;
2343 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2344 device->physical_device->rad_info.chip_class == GFX7 ||
2345 device->physical_device->rad_info.chip_class == GFX6)
2346 --max_offchip_buffers_per_se;
2347
2348 max_offchip_buffers = max_offchip_buffers_per_se *
2349 device->physical_device->rad_info.max_se;
2350
2351 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2352 * around by setting 4K granularity.
2353 */
2354 if (device->tess_offchip_block_dw_size == 4096) {
2355 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2356 offchip_granularity = V_03093C_X_4K_DWORDS;
2357 } else {
2358 assert(device->tess_offchip_block_dw_size == 8192);
2359 offchip_granularity = V_03093C_X_8K_DWORDS;
2360 }
2361
2362 switch (device->physical_device->rad_info.chip_class) {
2363 case GFX6:
2364 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2365 break;
2366 case GFX7:
2367 case GFX8:
2368 case GFX9:
2369 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2370 break;
2371 case GFX10:
2372 break;
2373 default:
2374 break;
2375 }
2376
2377 *max_offchip_buffers_p = max_offchip_buffers;
2378 if (device->physical_device->rad_info.chip_class >= GFX7) {
2379 if (device->physical_device->rad_info.chip_class >= GFX8)
2380 --max_offchip_buffers;
2381 hs_offchip_param =
2382 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2383 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2384 } else {
2385 hs_offchip_param =
2386 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2387 }
2388 return hs_offchip_param;
2389 }
2390
2391 static void
2392 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2393 struct radeon_winsys_bo *esgs_ring_bo,
2394 uint32_t esgs_ring_size,
2395 struct radeon_winsys_bo *gsvs_ring_bo,
2396 uint32_t gsvs_ring_size)
2397 {
2398 if (!esgs_ring_bo && !gsvs_ring_bo)
2399 return;
2400
2401 if (esgs_ring_bo)
2402 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2403
2404 if (gsvs_ring_bo)
2405 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2406
2407 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2408 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2409 radeon_emit(cs, esgs_ring_size >> 8);
2410 radeon_emit(cs, gsvs_ring_size >> 8);
2411 } else {
2412 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2413 radeon_emit(cs, esgs_ring_size >> 8);
2414 radeon_emit(cs, gsvs_ring_size >> 8);
2415 }
2416 }
2417
2418 static void
2419 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2420 unsigned hs_offchip_param, unsigned tf_ring_size,
2421 struct radeon_winsys_bo *tess_rings_bo)
2422 {
2423 uint64_t tf_va;
2424
2425 if (!tess_rings_bo)
2426 return;
2427
2428 tf_va = radv_buffer_get_va(tess_rings_bo);
2429
2430 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2431
2432 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2433 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2434 S_030938_SIZE(tf_ring_size / 4));
2435 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2436 tf_va >> 8);
2437
2438 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2439 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2440 S_030984_BASE_HI(tf_va >> 40));
2441 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2442 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2443 S_030944_BASE_HI(tf_va >> 40));
2444 }
2445 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2446 hs_offchip_param);
2447 } else {
2448 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2449 S_008988_SIZE(tf_ring_size / 4));
2450 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2451 tf_va >> 8);
2452 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2453 hs_offchip_param);
2454 }
2455 }
2456
2457 static void
2458 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2459 struct radeon_winsys_bo *compute_scratch_bo)
2460 {
2461 uint64_t scratch_va;
2462
2463 if (!compute_scratch_bo)
2464 return;
2465
2466 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2467
2468 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2469
2470 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2471 radeon_emit(cs, scratch_va);
2472 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2473 S_008F04_SWIZZLE_ENABLE(1));
2474 }
2475
2476 static void
2477 radv_emit_global_shader_pointers(struct radv_queue *queue,
2478 struct radeon_cmdbuf *cs,
2479 struct radeon_winsys_bo *descriptor_bo)
2480 {
2481 uint64_t va;
2482
2483 if (!descriptor_bo)
2484 return;
2485
2486 va = radv_buffer_get_va(descriptor_bo);
2487
2488 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2489
2490 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2491 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2492 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2493 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2494 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2495
2496 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2497 radv_emit_shader_pointer(queue->device, cs, regs[i],
2498 va, true);
2499 }
2500 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2501 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2502 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2503 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2504 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2505
2506 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2507 radv_emit_shader_pointer(queue->device, cs, regs[i],
2508 va, true);
2509 }
2510 } else {
2511 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2512 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2513 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2514 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2515 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2516 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2517
2518 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2519 radv_emit_shader_pointer(queue->device, cs, regs[i],
2520 va, true);
2521 }
2522 }
2523 }
2524
2525 static void
2526 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2527 {
2528 struct radv_device *device = queue->device;
2529
2530 if (device->gfx_init) {
2531 uint64_t va = radv_buffer_get_va(device->gfx_init);
2532
2533 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2534 radeon_emit(cs, va);
2535 radeon_emit(cs, va >> 32);
2536 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2537
2538 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2539 } else {
2540 struct radv_physical_device *physical_device = device->physical_device;
2541 si_emit_graphics(physical_device, cs);
2542 }
2543 }
2544
2545 static void
2546 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2547 {
2548 struct radv_physical_device *physical_device = queue->device->physical_device;
2549 si_emit_compute(physical_device, cs);
2550 }
2551
2552 static VkResult
2553 radv_get_preamble_cs(struct radv_queue *queue,
2554 uint32_t scratch_size,
2555 uint32_t compute_scratch_size,
2556 uint32_t esgs_ring_size,
2557 uint32_t gsvs_ring_size,
2558 bool needs_tess_rings,
2559 bool needs_sample_positions,
2560 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2561 struct radeon_cmdbuf **initial_preamble_cs,
2562 struct radeon_cmdbuf **continue_preamble_cs)
2563 {
2564 struct radeon_winsys_bo *scratch_bo = NULL;
2565 struct radeon_winsys_bo *descriptor_bo = NULL;
2566 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2567 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2568 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2569 struct radeon_winsys_bo *tess_rings_bo = NULL;
2570 struct radeon_cmdbuf *dest_cs[3] = {0};
2571 bool add_tess_rings = false, add_sample_positions = false;
2572 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2573 unsigned max_offchip_buffers;
2574 unsigned hs_offchip_param = 0;
2575 unsigned tess_offchip_ring_offset;
2576 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2577 if (!queue->has_tess_rings) {
2578 if (needs_tess_rings)
2579 add_tess_rings = true;
2580 }
2581 if (!queue->has_sample_positions) {
2582 if (needs_sample_positions)
2583 add_sample_positions = true;
2584 }
2585 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2586 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2587 &max_offchip_buffers);
2588 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2589 tess_offchip_ring_size = max_offchip_buffers *
2590 queue->device->tess_offchip_block_dw_size * 4;
2591
2592 if (scratch_size <= queue->scratch_size &&
2593 compute_scratch_size <= queue->compute_scratch_size &&
2594 esgs_ring_size <= queue->esgs_ring_size &&
2595 gsvs_ring_size <= queue->gsvs_ring_size &&
2596 !add_tess_rings && !add_sample_positions &&
2597 queue->initial_preamble_cs) {
2598 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2599 *initial_preamble_cs = queue->initial_preamble_cs;
2600 *continue_preamble_cs = queue->continue_preamble_cs;
2601 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2602 *continue_preamble_cs = NULL;
2603 return VK_SUCCESS;
2604 }
2605
2606 if (scratch_size > queue->scratch_size) {
2607 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2608 scratch_size,
2609 4096,
2610 RADEON_DOMAIN_VRAM,
2611 ring_bo_flags,
2612 RADV_BO_PRIORITY_SCRATCH);
2613 if (!scratch_bo)
2614 goto fail;
2615 } else
2616 scratch_bo = queue->scratch_bo;
2617
2618 if (compute_scratch_size > queue->compute_scratch_size) {
2619 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2620 compute_scratch_size,
2621 4096,
2622 RADEON_DOMAIN_VRAM,
2623 ring_bo_flags,
2624 RADV_BO_PRIORITY_SCRATCH);
2625 if (!compute_scratch_bo)
2626 goto fail;
2627
2628 } else
2629 compute_scratch_bo = queue->compute_scratch_bo;
2630
2631 if (esgs_ring_size > queue->esgs_ring_size) {
2632 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2633 esgs_ring_size,
2634 4096,
2635 RADEON_DOMAIN_VRAM,
2636 ring_bo_flags,
2637 RADV_BO_PRIORITY_SCRATCH);
2638 if (!esgs_ring_bo)
2639 goto fail;
2640 } else {
2641 esgs_ring_bo = queue->esgs_ring_bo;
2642 esgs_ring_size = queue->esgs_ring_size;
2643 }
2644
2645 if (gsvs_ring_size > queue->gsvs_ring_size) {
2646 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2647 gsvs_ring_size,
2648 4096,
2649 RADEON_DOMAIN_VRAM,
2650 ring_bo_flags,
2651 RADV_BO_PRIORITY_SCRATCH);
2652 if (!gsvs_ring_bo)
2653 goto fail;
2654 } else {
2655 gsvs_ring_bo = queue->gsvs_ring_bo;
2656 gsvs_ring_size = queue->gsvs_ring_size;
2657 }
2658
2659 if (add_tess_rings) {
2660 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2661 tess_offchip_ring_offset + tess_offchip_ring_size,
2662 256,
2663 RADEON_DOMAIN_VRAM,
2664 ring_bo_flags,
2665 RADV_BO_PRIORITY_SCRATCH);
2666 if (!tess_rings_bo)
2667 goto fail;
2668 } else {
2669 tess_rings_bo = queue->tess_rings_bo;
2670 }
2671
2672 if (scratch_bo != queue->scratch_bo ||
2673 esgs_ring_bo != queue->esgs_ring_bo ||
2674 gsvs_ring_bo != queue->gsvs_ring_bo ||
2675 tess_rings_bo != queue->tess_rings_bo ||
2676 add_sample_positions) {
2677 uint32_t size = 0;
2678 if (gsvs_ring_bo || esgs_ring_bo ||
2679 tess_rings_bo || add_sample_positions) {
2680 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2681 if (add_sample_positions)
2682 size += 128; /* 64+32+16+8 = 120 bytes */
2683 }
2684 else if (scratch_bo)
2685 size = 8; /* 2 dword */
2686
2687 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2688 size,
2689 4096,
2690 RADEON_DOMAIN_VRAM,
2691 RADEON_FLAG_CPU_ACCESS |
2692 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2693 RADEON_FLAG_READ_ONLY,
2694 RADV_BO_PRIORITY_DESCRIPTOR);
2695 if (!descriptor_bo)
2696 goto fail;
2697 } else
2698 descriptor_bo = queue->descriptor_bo;
2699
2700 if (descriptor_bo != queue->descriptor_bo) {
2701 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2702
2703 if (scratch_bo) {
2704 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2705 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2706 S_008F04_SWIZZLE_ENABLE(1);
2707 map[0] = scratch_va;
2708 map[1] = rsrc1;
2709 }
2710
2711 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2712 fill_geom_tess_rings(queue, map, add_sample_positions,
2713 esgs_ring_size, esgs_ring_bo,
2714 gsvs_ring_size, gsvs_ring_bo,
2715 tess_factor_ring_size,
2716 tess_offchip_ring_offset,
2717 tess_offchip_ring_size,
2718 tess_rings_bo);
2719
2720 queue->device->ws->buffer_unmap(descriptor_bo);
2721 }
2722
2723 for(int i = 0; i < 3; ++i) {
2724 struct radeon_cmdbuf *cs = NULL;
2725 cs = queue->device->ws->cs_create(queue->device->ws,
2726 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2727 if (!cs)
2728 goto fail;
2729
2730 dest_cs[i] = cs;
2731
2732 if (scratch_bo)
2733 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2734
2735 /* Emit initial configuration. */
2736 switch (queue->queue_family_index) {
2737 case RADV_QUEUE_GENERAL:
2738 radv_init_graphics_state(cs, queue);
2739 break;
2740 case RADV_QUEUE_COMPUTE:
2741 radv_init_compute_state(cs, queue);
2742 break;
2743 case RADV_QUEUE_TRANSFER:
2744 break;
2745 }
2746
2747 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2748 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2749 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2750
2751 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2752 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2753 }
2754
2755 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2756 gsvs_ring_bo, gsvs_ring_size);
2757 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2758 tess_factor_ring_size, tess_rings_bo);
2759 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2760 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2761
2762 if (i == 0) {
2763 si_cs_emit_cache_flush(cs,
2764 queue->device->physical_device->rad_info.chip_class,
2765 NULL, 0,
2766 queue->queue_family_index == RING_COMPUTE &&
2767 queue->device->physical_device->rad_info.chip_class >= GFX7,
2768 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2769 RADV_CMD_FLAG_INV_ICACHE |
2770 RADV_CMD_FLAG_INV_SCACHE |
2771 RADV_CMD_FLAG_INV_VCACHE |
2772 RADV_CMD_FLAG_INV_L2 |
2773 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2774 } else if (i == 1) {
2775 si_cs_emit_cache_flush(cs,
2776 queue->device->physical_device->rad_info.chip_class,
2777 NULL, 0,
2778 queue->queue_family_index == RING_COMPUTE &&
2779 queue->device->physical_device->rad_info.chip_class >= GFX7,
2780 RADV_CMD_FLAG_INV_ICACHE |
2781 RADV_CMD_FLAG_INV_SCACHE |
2782 RADV_CMD_FLAG_INV_VCACHE |
2783 RADV_CMD_FLAG_INV_L2 |
2784 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2785 }
2786
2787 if (!queue->device->ws->cs_finalize(cs))
2788 goto fail;
2789 }
2790
2791 if (queue->initial_full_flush_preamble_cs)
2792 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2793
2794 if (queue->initial_preamble_cs)
2795 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2796
2797 if (queue->continue_preamble_cs)
2798 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2799
2800 queue->initial_full_flush_preamble_cs = dest_cs[0];
2801 queue->initial_preamble_cs = dest_cs[1];
2802 queue->continue_preamble_cs = dest_cs[2];
2803
2804 if (scratch_bo != queue->scratch_bo) {
2805 if (queue->scratch_bo)
2806 queue->device->ws->buffer_destroy(queue->scratch_bo);
2807 queue->scratch_bo = scratch_bo;
2808 queue->scratch_size = scratch_size;
2809 }
2810
2811 if (compute_scratch_bo != queue->compute_scratch_bo) {
2812 if (queue->compute_scratch_bo)
2813 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2814 queue->compute_scratch_bo = compute_scratch_bo;
2815 queue->compute_scratch_size = compute_scratch_size;
2816 }
2817
2818 if (esgs_ring_bo != queue->esgs_ring_bo) {
2819 if (queue->esgs_ring_bo)
2820 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2821 queue->esgs_ring_bo = esgs_ring_bo;
2822 queue->esgs_ring_size = esgs_ring_size;
2823 }
2824
2825 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2826 if (queue->gsvs_ring_bo)
2827 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2828 queue->gsvs_ring_bo = gsvs_ring_bo;
2829 queue->gsvs_ring_size = gsvs_ring_size;
2830 }
2831
2832 if (tess_rings_bo != queue->tess_rings_bo) {
2833 queue->tess_rings_bo = tess_rings_bo;
2834 queue->has_tess_rings = true;
2835 }
2836
2837 if (descriptor_bo != queue->descriptor_bo) {
2838 if (queue->descriptor_bo)
2839 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2840
2841 queue->descriptor_bo = descriptor_bo;
2842 }
2843
2844 if (add_sample_positions)
2845 queue->has_sample_positions = true;
2846
2847 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2848 *initial_preamble_cs = queue->initial_preamble_cs;
2849 *continue_preamble_cs = queue->continue_preamble_cs;
2850 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2851 *continue_preamble_cs = NULL;
2852 return VK_SUCCESS;
2853 fail:
2854 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2855 if (dest_cs[i])
2856 queue->device->ws->cs_destroy(dest_cs[i]);
2857 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2858 queue->device->ws->buffer_destroy(descriptor_bo);
2859 if (scratch_bo && scratch_bo != queue->scratch_bo)
2860 queue->device->ws->buffer_destroy(scratch_bo);
2861 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2862 queue->device->ws->buffer_destroy(compute_scratch_bo);
2863 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2864 queue->device->ws->buffer_destroy(esgs_ring_bo);
2865 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2866 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2867 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2868 queue->device->ws->buffer_destroy(tess_rings_bo);
2869 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2870 }
2871
2872 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2873 struct radv_winsys_sem_counts *counts,
2874 int num_sems,
2875 const VkSemaphore *sems,
2876 VkFence _fence,
2877 bool reset_temp)
2878 {
2879 int syncobj_idx = 0, sem_idx = 0;
2880
2881 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2882 return VK_SUCCESS;
2883
2884 for (uint32_t i = 0; i < num_sems; i++) {
2885 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2886
2887 if (sem->temp_syncobj || sem->syncobj)
2888 counts->syncobj_count++;
2889 else
2890 counts->sem_count++;
2891 }
2892
2893 if (_fence != VK_NULL_HANDLE) {
2894 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2895 if (fence->temp_syncobj || fence->syncobj)
2896 counts->syncobj_count++;
2897 }
2898
2899 if (counts->syncobj_count) {
2900 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2901 if (!counts->syncobj)
2902 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2903 }
2904
2905 if (counts->sem_count) {
2906 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2907 if (!counts->sem) {
2908 free(counts->syncobj);
2909 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2910 }
2911 }
2912
2913 for (uint32_t i = 0; i < num_sems; i++) {
2914 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2915
2916 if (sem->temp_syncobj) {
2917 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2918 }
2919 else if (sem->syncobj)
2920 counts->syncobj[syncobj_idx++] = sem->syncobj;
2921 else {
2922 assert(sem->sem);
2923 counts->sem[sem_idx++] = sem->sem;
2924 }
2925 }
2926
2927 if (_fence != VK_NULL_HANDLE) {
2928 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2929 if (fence->temp_syncobj)
2930 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2931 else if (fence->syncobj)
2932 counts->syncobj[syncobj_idx++] = fence->syncobj;
2933 }
2934
2935 return VK_SUCCESS;
2936 }
2937
2938 static void
2939 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2940 {
2941 free(sem_info->wait.syncobj);
2942 free(sem_info->wait.sem);
2943 free(sem_info->signal.syncobj);
2944 free(sem_info->signal.sem);
2945 }
2946
2947
2948 static void radv_free_temp_syncobjs(struct radv_device *device,
2949 int num_sems,
2950 const VkSemaphore *sems)
2951 {
2952 for (uint32_t i = 0; i < num_sems; i++) {
2953 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2954
2955 if (sem->temp_syncobj) {
2956 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2957 sem->temp_syncobj = 0;
2958 }
2959 }
2960 }
2961
2962 static VkResult
2963 radv_alloc_sem_info(struct radv_instance *instance,
2964 struct radv_winsys_sem_info *sem_info,
2965 int num_wait_sems,
2966 const VkSemaphore *wait_sems,
2967 int num_signal_sems,
2968 const VkSemaphore *signal_sems,
2969 VkFence fence)
2970 {
2971 VkResult ret;
2972 memset(sem_info, 0, sizeof(*sem_info));
2973
2974 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2975 if (ret)
2976 return ret;
2977 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2978 if (ret)
2979 radv_free_sem_info(sem_info);
2980
2981 /* caller can override these */
2982 sem_info->cs_emit_wait = true;
2983 sem_info->cs_emit_signal = true;
2984 return ret;
2985 }
2986
2987 /* Signals fence as soon as all the work currently put on queue is done. */
2988 static VkResult radv_signal_fence(struct radv_queue *queue,
2989 struct radv_fence *fence)
2990 {
2991 int ret;
2992 VkResult result;
2993 struct radv_winsys_sem_info sem_info;
2994
2995 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2996 radv_fence_to_handle(fence));
2997 if (result != VK_SUCCESS)
2998 return result;
2999
3000 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3001 &queue->device->empty_cs[queue->queue_family_index],
3002 1, NULL, NULL, &sem_info, NULL,
3003 false, fence->fence);
3004 radv_free_sem_info(&sem_info);
3005
3006 if (ret)
3007 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3008
3009 return VK_SUCCESS;
3010 }
3011
3012 VkResult radv_QueueSubmit(
3013 VkQueue _queue,
3014 uint32_t submitCount,
3015 const VkSubmitInfo* pSubmits,
3016 VkFence _fence)
3017 {
3018 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3019 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3020 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3021 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3022 int ret;
3023 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3024 uint32_t scratch_size = 0;
3025 uint32_t compute_scratch_size = 0;
3026 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3027 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3028 VkResult result;
3029 bool fence_emitted = false;
3030 bool tess_rings_needed = false;
3031 bool sample_positions_needed = false;
3032
3033 /* Do this first so failing to allocate scratch buffers can't result in
3034 * partially executed submissions. */
3035 for (uint32_t i = 0; i < submitCount; i++) {
3036 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3038 pSubmits[i].pCommandBuffers[j]);
3039
3040 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3041 compute_scratch_size = MAX2(compute_scratch_size,
3042 cmd_buffer->compute_scratch_size_needed);
3043 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3044 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3045 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3046 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3047 }
3048 }
3049
3050 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3051 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3052 sample_positions_needed, &initial_flush_preamble_cs,
3053 &initial_preamble_cs, &continue_preamble_cs);
3054 if (result != VK_SUCCESS)
3055 return result;
3056
3057 for (uint32_t i = 0; i < submitCount; i++) {
3058 struct radeon_cmdbuf **cs_array;
3059 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3060 bool can_patch = true;
3061 uint32_t advance;
3062 struct radv_winsys_sem_info sem_info;
3063
3064 result = radv_alloc_sem_info(queue->device->instance,
3065 &sem_info,
3066 pSubmits[i].waitSemaphoreCount,
3067 pSubmits[i].pWaitSemaphores,
3068 pSubmits[i].signalSemaphoreCount,
3069 pSubmits[i].pSignalSemaphores,
3070 _fence);
3071 if (result != VK_SUCCESS)
3072 return result;
3073
3074 if (!pSubmits[i].commandBufferCount) {
3075 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3076 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3077 &queue->device->empty_cs[queue->queue_family_index],
3078 1, NULL, NULL,
3079 &sem_info, NULL,
3080 false, base_fence);
3081 if (ret) {
3082 radv_loge("failed to submit CS %d\n", i);
3083 abort();
3084 }
3085 fence_emitted = true;
3086 }
3087 radv_free_sem_info(&sem_info);
3088 continue;
3089 }
3090
3091 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3092 (pSubmits[i].commandBufferCount));
3093
3094 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3096 pSubmits[i].pCommandBuffers[j]);
3097 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3098
3099 cs_array[j] = cmd_buffer->cs;
3100 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3101 can_patch = false;
3102
3103 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3104 }
3105
3106 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3107 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3108 const struct radv_winsys_bo_list *bo_list = NULL;
3109
3110 advance = MIN2(max_cs_submission,
3111 pSubmits[i].commandBufferCount - j);
3112
3113 if (queue->device->trace_bo)
3114 *queue->device->trace_id_ptr = 0;
3115
3116 sem_info.cs_emit_wait = j == 0;
3117 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3118
3119 if (unlikely(queue->device->use_global_bo_list)) {
3120 pthread_mutex_lock(&queue->device->bo_list.mutex);
3121 bo_list = &queue->device->bo_list.list;
3122 }
3123
3124 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3125 advance, initial_preamble, continue_preamble_cs,
3126 &sem_info, bo_list,
3127 can_patch, base_fence);
3128
3129 if (unlikely(queue->device->use_global_bo_list))
3130 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3131
3132 if (ret) {
3133 radv_loge("failed to submit CS %d\n", i);
3134 abort();
3135 }
3136 fence_emitted = true;
3137 if (queue->device->trace_bo) {
3138 radv_check_gpu_hangs(queue, cs_array[j]);
3139 }
3140 }
3141
3142 radv_free_temp_syncobjs(queue->device,
3143 pSubmits[i].waitSemaphoreCount,
3144 pSubmits[i].pWaitSemaphores);
3145 radv_free_sem_info(&sem_info);
3146 free(cs_array);
3147 }
3148
3149 if (fence) {
3150 if (!fence_emitted) {
3151 result = radv_signal_fence(queue, fence);
3152 if (result != VK_SUCCESS)
3153 return result;
3154 }
3155 }
3156
3157 return VK_SUCCESS;
3158 }
3159
3160 VkResult radv_QueueWaitIdle(
3161 VkQueue _queue)
3162 {
3163 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3164
3165 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3166 radv_queue_family_to_ring(queue->queue_family_index),
3167 queue->queue_idx);
3168 return VK_SUCCESS;
3169 }
3170
3171 VkResult radv_DeviceWaitIdle(
3172 VkDevice _device)
3173 {
3174 RADV_FROM_HANDLE(radv_device, device, _device);
3175
3176 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3177 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3178 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3179 }
3180 }
3181 return VK_SUCCESS;
3182 }
3183
3184 VkResult radv_EnumerateInstanceExtensionProperties(
3185 const char* pLayerName,
3186 uint32_t* pPropertyCount,
3187 VkExtensionProperties* pProperties)
3188 {
3189 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3190
3191 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3192 if (radv_supported_instance_extensions.extensions[i]) {
3193 vk_outarray_append(&out, prop) {
3194 *prop = radv_instance_extensions[i];
3195 }
3196 }
3197 }
3198
3199 return vk_outarray_status(&out);
3200 }
3201
3202 VkResult radv_EnumerateDeviceExtensionProperties(
3203 VkPhysicalDevice physicalDevice,
3204 const char* pLayerName,
3205 uint32_t* pPropertyCount,
3206 VkExtensionProperties* pProperties)
3207 {
3208 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3209 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3210
3211 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3212 if (device->supported_extensions.extensions[i]) {
3213 vk_outarray_append(&out, prop) {
3214 *prop = radv_device_extensions[i];
3215 }
3216 }
3217 }
3218
3219 return vk_outarray_status(&out);
3220 }
3221
3222 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3223 VkInstance _instance,
3224 const char* pName)
3225 {
3226 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3227
3228 return radv_lookup_entrypoint_checked(pName,
3229 instance ? instance->apiVersion : 0,
3230 instance ? &instance->enabled_extensions : NULL,
3231 NULL);
3232 }
3233
3234 /* The loader wants us to expose a second GetInstanceProcAddr function
3235 * to work around certain LD_PRELOAD issues seen in apps.
3236 */
3237 PUBLIC
3238 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3239 VkInstance instance,
3240 const char* pName);
3241
3242 PUBLIC
3243 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3244 VkInstance instance,
3245 const char* pName)
3246 {
3247 return radv_GetInstanceProcAddr(instance, pName);
3248 }
3249
3250 PUBLIC
3251 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3252 VkInstance _instance,
3253 const char* pName);
3254
3255 PUBLIC
3256 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3257 VkInstance _instance,
3258 const char* pName)
3259 {
3260 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3261
3262 return radv_lookup_physical_device_entrypoint_checked(pName,
3263 instance ? instance->apiVersion : 0,
3264 instance ? &instance->enabled_extensions : NULL);
3265 }
3266
3267 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3268 VkDevice _device,
3269 const char* pName)
3270 {
3271 RADV_FROM_HANDLE(radv_device, device, _device);
3272
3273 return radv_lookup_entrypoint_checked(pName,
3274 device->instance->apiVersion,
3275 &device->instance->enabled_extensions,
3276 &device->enabled_extensions);
3277 }
3278
3279 bool radv_get_memory_fd(struct radv_device *device,
3280 struct radv_device_memory *memory,
3281 int *pFD)
3282 {
3283 struct radeon_bo_metadata metadata;
3284
3285 if (memory->image) {
3286 radv_init_metadata(device, memory->image, &metadata);
3287 device->ws->buffer_set_metadata(memory->bo, &metadata);
3288 }
3289
3290 return device->ws->buffer_get_fd(device->ws, memory->bo,
3291 pFD);
3292 }
3293
3294 static VkResult radv_alloc_memory(struct radv_device *device,
3295 const VkMemoryAllocateInfo* pAllocateInfo,
3296 const VkAllocationCallbacks* pAllocator,
3297 VkDeviceMemory* pMem)
3298 {
3299 struct radv_device_memory *mem;
3300 VkResult result;
3301 enum radeon_bo_domain domain;
3302 uint32_t flags = 0;
3303 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3304
3305 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3306
3307 if (pAllocateInfo->allocationSize == 0) {
3308 /* Apparently, this is allowed */
3309 *pMem = VK_NULL_HANDLE;
3310 return VK_SUCCESS;
3311 }
3312
3313 const VkImportMemoryFdInfoKHR *import_info =
3314 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3315 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3316 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3317 const VkExportMemoryAllocateInfo *export_info =
3318 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3319 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3320 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3321
3322 const struct wsi_memory_allocate_info *wsi_info =
3323 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3324
3325 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3326 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3327 if (mem == NULL)
3328 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3329
3330 if (wsi_info && wsi_info->implicit_sync)
3331 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3332
3333 if (dedicate_info) {
3334 mem->image = radv_image_from_handle(dedicate_info->image);
3335 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3336 } else {
3337 mem->image = NULL;
3338 mem->buffer = NULL;
3339 }
3340
3341 float priority_float = 0.5;
3342 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3343 vk_find_struct_const(pAllocateInfo->pNext,
3344 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3345 if (priority_ext)
3346 priority_float = priority_ext->priority;
3347
3348 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3349 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3350
3351 mem->user_ptr = NULL;
3352
3353 if (import_info) {
3354 assert(import_info->handleType ==
3355 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3356 import_info->handleType ==
3357 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3358 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3359 priority, NULL, NULL);
3360 if (!mem->bo) {
3361 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3362 goto fail;
3363 } else {
3364 close(import_info->fd);
3365 }
3366 } else if (host_ptr_info) {
3367 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3368 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3369 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3370 pAllocateInfo->allocationSize,
3371 priority);
3372 if (!mem->bo) {
3373 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3374 goto fail;
3375 } else {
3376 mem->user_ptr = host_ptr_info->pHostPointer;
3377 }
3378 } else {
3379 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3380 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3381 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3382 domain = RADEON_DOMAIN_GTT;
3383 else
3384 domain = RADEON_DOMAIN_VRAM;
3385
3386 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3387 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3388 else
3389 flags |= RADEON_FLAG_CPU_ACCESS;
3390
3391 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3392 flags |= RADEON_FLAG_GTT_WC;
3393
3394 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3395 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3396 if (device->use_global_bo_list) {
3397 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3398 }
3399 }
3400
3401 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3402 domain, flags, priority);
3403
3404 if (!mem->bo) {
3405 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3406 goto fail;
3407 }
3408 mem->type_index = mem_type_index;
3409 }
3410
3411 result = radv_bo_list_add(device, mem->bo);
3412 if (result != VK_SUCCESS)
3413 goto fail_bo;
3414
3415 *pMem = radv_device_memory_to_handle(mem);
3416
3417 return VK_SUCCESS;
3418
3419 fail_bo:
3420 device->ws->buffer_destroy(mem->bo);
3421 fail:
3422 vk_free2(&device->alloc, pAllocator, mem);
3423
3424 return result;
3425 }
3426
3427 VkResult radv_AllocateMemory(
3428 VkDevice _device,
3429 const VkMemoryAllocateInfo* pAllocateInfo,
3430 const VkAllocationCallbacks* pAllocator,
3431 VkDeviceMemory* pMem)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3435 }
3436
3437 void radv_FreeMemory(
3438 VkDevice _device,
3439 VkDeviceMemory _mem,
3440 const VkAllocationCallbacks* pAllocator)
3441 {
3442 RADV_FROM_HANDLE(radv_device, device, _device);
3443 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3444
3445 if (mem == NULL)
3446 return;
3447
3448 radv_bo_list_remove(device, mem->bo);
3449 device->ws->buffer_destroy(mem->bo);
3450 mem->bo = NULL;
3451
3452 vk_free2(&device->alloc, pAllocator, mem);
3453 }
3454
3455 VkResult radv_MapMemory(
3456 VkDevice _device,
3457 VkDeviceMemory _memory,
3458 VkDeviceSize offset,
3459 VkDeviceSize size,
3460 VkMemoryMapFlags flags,
3461 void** ppData)
3462 {
3463 RADV_FROM_HANDLE(radv_device, device, _device);
3464 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3465
3466 if (mem == NULL) {
3467 *ppData = NULL;
3468 return VK_SUCCESS;
3469 }
3470
3471 if (mem->user_ptr)
3472 *ppData = mem->user_ptr;
3473 else
3474 *ppData = device->ws->buffer_map(mem->bo);
3475
3476 if (*ppData) {
3477 *ppData += offset;
3478 return VK_SUCCESS;
3479 }
3480
3481 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3482 }
3483
3484 void radv_UnmapMemory(
3485 VkDevice _device,
3486 VkDeviceMemory _memory)
3487 {
3488 RADV_FROM_HANDLE(radv_device, device, _device);
3489 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3490
3491 if (mem == NULL)
3492 return;
3493
3494 if (mem->user_ptr == NULL)
3495 device->ws->buffer_unmap(mem->bo);
3496 }
3497
3498 VkResult radv_FlushMappedMemoryRanges(
3499 VkDevice _device,
3500 uint32_t memoryRangeCount,
3501 const VkMappedMemoryRange* pMemoryRanges)
3502 {
3503 return VK_SUCCESS;
3504 }
3505
3506 VkResult radv_InvalidateMappedMemoryRanges(
3507 VkDevice _device,
3508 uint32_t memoryRangeCount,
3509 const VkMappedMemoryRange* pMemoryRanges)
3510 {
3511 return VK_SUCCESS;
3512 }
3513
3514 void radv_GetBufferMemoryRequirements(
3515 VkDevice _device,
3516 VkBuffer _buffer,
3517 VkMemoryRequirements* pMemoryRequirements)
3518 {
3519 RADV_FROM_HANDLE(radv_device, device, _device);
3520 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3521
3522 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3523
3524 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3525 pMemoryRequirements->alignment = 4096;
3526 else
3527 pMemoryRequirements->alignment = 16;
3528
3529 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3530 }
3531
3532 void radv_GetBufferMemoryRequirements2(
3533 VkDevice device,
3534 const VkBufferMemoryRequirementsInfo2 *pInfo,
3535 VkMemoryRequirements2 *pMemoryRequirements)
3536 {
3537 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3538 &pMemoryRequirements->memoryRequirements);
3539 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3540 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3541 switch (ext->sType) {
3542 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3543 VkMemoryDedicatedRequirements *req =
3544 (VkMemoryDedicatedRequirements *) ext;
3545 req->requiresDedicatedAllocation = buffer->shareable;
3546 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3547 break;
3548 }
3549 default:
3550 break;
3551 }
3552 }
3553 }
3554
3555 void radv_GetImageMemoryRequirements(
3556 VkDevice _device,
3557 VkImage _image,
3558 VkMemoryRequirements* pMemoryRequirements)
3559 {
3560 RADV_FROM_HANDLE(radv_device, device, _device);
3561 RADV_FROM_HANDLE(radv_image, image, _image);
3562
3563 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3564
3565 pMemoryRequirements->size = image->size;
3566 pMemoryRequirements->alignment = image->alignment;
3567 }
3568
3569 void radv_GetImageMemoryRequirements2(
3570 VkDevice device,
3571 const VkImageMemoryRequirementsInfo2 *pInfo,
3572 VkMemoryRequirements2 *pMemoryRequirements)
3573 {
3574 radv_GetImageMemoryRequirements(device, pInfo->image,
3575 &pMemoryRequirements->memoryRequirements);
3576
3577 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3578
3579 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3580 switch (ext->sType) {
3581 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3582 VkMemoryDedicatedRequirements *req =
3583 (VkMemoryDedicatedRequirements *) ext;
3584 req->requiresDedicatedAllocation = image->shareable;
3585 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3586 break;
3587 }
3588 default:
3589 break;
3590 }
3591 }
3592 }
3593
3594 void radv_GetImageSparseMemoryRequirements(
3595 VkDevice device,
3596 VkImage image,
3597 uint32_t* pSparseMemoryRequirementCount,
3598 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3599 {
3600 stub();
3601 }
3602
3603 void radv_GetImageSparseMemoryRequirements2(
3604 VkDevice device,
3605 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3606 uint32_t* pSparseMemoryRequirementCount,
3607 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3608 {
3609 stub();
3610 }
3611
3612 void radv_GetDeviceMemoryCommitment(
3613 VkDevice device,
3614 VkDeviceMemory memory,
3615 VkDeviceSize* pCommittedMemoryInBytes)
3616 {
3617 *pCommittedMemoryInBytes = 0;
3618 }
3619
3620 VkResult radv_BindBufferMemory2(VkDevice device,
3621 uint32_t bindInfoCount,
3622 const VkBindBufferMemoryInfo *pBindInfos)
3623 {
3624 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3625 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3626 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3627
3628 if (mem) {
3629 buffer->bo = mem->bo;
3630 buffer->offset = pBindInfos[i].memoryOffset;
3631 } else {
3632 buffer->bo = NULL;
3633 }
3634 }
3635 return VK_SUCCESS;
3636 }
3637
3638 VkResult radv_BindBufferMemory(
3639 VkDevice device,
3640 VkBuffer buffer,
3641 VkDeviceMemory memory,
3642 VkDeviceSize memoryOffset)
3643 {
3644 const VkBindBufferMemoryInfo info = {
3645 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3646 .buffer = buffer,
3647 .memory = memory,
3648 .memoryOffset = memoryOffset
3649 };
3650
3651 return radv_BindBufferMemory2(device, 1, &info);
3652 }
3653
3654 VkResult radv_BindImageMemory2(VkDevice device,
3655 uint32_t bindInfoCount,
3656 const VkBindImageMemoryInfo *pBindInfos)
3657 {
3658 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3659 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3660 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3661
3662 if (mem) {
3663 image->bo = mem->bo;
3664 image->offset = pBindInfos[i].memoryOffset;
3665 } else {
3666 image->bo = NULL;
3667 image->offset = 0;
3668 }
3669 }
3670 return VK_SUCCESS;
3671 }
3672
3673
3674 VkResult radv_BindImageMemory(
3675 VkDevice device,
3676 VkImage image,
3677 VkDeviceMemory memory,
3678 VkDeviceSize memoryOffset)
3679 {
3680 const VkBindImageMemoryInfo info = {
3681 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3682 .image = image,
3683 .memory = memory,
3684 .memoryOffset = memoryOffset
3685 };
3686
3687 return radv_BindImageMemory2(device, 1, &info);
3688 }
3689
3690
3691 static void
3692 radv_sparse_buffer_bind_memory(struct radv_device *device,
3693 const VkSparseBufferMemoryBindInfo *bind)
3694 {
3695 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3696
3697 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3698 struct radv_device_memory *mem = NULL;
3699
3700 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3701 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3702
3703 device->ws->buffer_virtual_bind(buffer->bo,
3704 bind->pBinds[i].resourceOffset,
3705 bind->pBinds[i].size,
3706 mem ? mem->bo : NULL,
3707 bind->pBinds[i].memoryOffset);
3708 }
3709 }
3710
3711 static void
3712 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3713 const VkSparseImageOpaqueMemoryBindInfo *bind)
3714 {
3715 RADV_FROM_HANDLE(radv_image, image, bind->image);
3716
3717 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3718 struct radv_device_memory *mem = NULL;
3719
3720 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3721 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3722
3723 device->ws->buffer_virtual_bind(image->bo,
3724 bind->pBinds[i].resourceOffset,
3725 bind->pBinds[i].size,
3726 mem ? mem->bo : NULL,
3727 bind->pBinds[i].memoryOffset);
3728 }
3729 }
3730
3731 VkResult radv_QueueBindSparse(
3732 VkQueue _queue,
3733 uint32_t bindInfoCount,
3734 const VkBindSparseInfo* pBindInfo,
3735 VkFence _fence)
3736 {
3737 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3738 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3739 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3740 bool fence_emitted = false;
3741 VkResult result;
3742 int ret;
3743
3744 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3745 struct radv_winsys_sem_info sem_info;
3746 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3747 radv_sparse_buffer_bind_memory(queue->device,
3748 pBindInfo[i].pBufferBinds + j);
3749 }
3750
3751 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3752 radv_sparse_image_opaque_bind_memory(queue->device,
3753 pBindInfo[i].pImageOpaqueBinds + j);
3754 }
3755
3756 VkResult result;
3757 result = radv_alloc_sem_info(queue->device->instance,
3758 &sem_info,
3759 pBindInfo[i].waitSemaphoreCount,
3760 pBindInfo[i].pWaitSemaphores,
3761 pBindInfo[i].signalSemaphoreCount,
3762 pBindInfo[i].pSignalSemaphores,
3763 _fence);
3764 if (result != VK_SUCCESS)
3765 return result;
3766
3767 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3768 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3769 &queue->device->empty_cs[queue->queue_family_index],
3770 1, NULL, NULL,
3771 &sem_info, NULL,
3772 false, base_fence);
3773 if (ret) {
3774 radv_loge("failed to submit CS %d\n", i);
3775 abort();
3776 }
3777
3778 fence_emitted = true;
3779 }
3780
3781 radv_free_sem_info(&sem_info);
3782
3783 }
3784
3785 if (fence) {
3786 if (!fence_emitted) {
3787 result = radv_signal_fence(queue, fence);
3788 if (result != VK_SUCCESS)
3789 return result;
3790 }
3791 }
3792
3793 return VK_SUCCESS;
3794 }
3795
3796 VkResult radv_CreateFence(
3797 VkDevice _device,
3798 const VkFenceCreateInfo* pCreateInfo,
3799 const VkAllocationCallbacks* pAllocator,
3800 VkFence* pFence)
3801 {
3802 RADV_FROM_HANDLE(radv_device, device, _device);
3803 const VkExportFenceCreateInfo *export =
3804 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3805 VkExternalFenceHandleTypeFlags handleTypes =
3806 export ? export->handleTypes : 0;
3807
3808 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3809 sizeof(*fence), 8,
3810 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3811
3812 if (!fence)
3813 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3814
3815 fence->fence_wsi = NULL;
3816 fence->temp_syncobj = 0;
3817 if (device->always_use_syncobj || handleTypes) {
3818 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3819 if (ret) {
3820 vk_free2(&device->alloc, pAllocator, fence);
3821 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3822 }
3823 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3824 device->ws->signal_syncobj(device->ws, fence->syncobj);
3825 }
3826 fence->fence = NULL;
3827 } else {
3828 fence->fence = device->ws->create_fence();
3829 if (!fence->fence) {
3830 vk_free2(&device->alloc, pAllocator, fence);
3831 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3832 }
3833 fence->syncobj = 0;
3834 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3835 device->ws->signal_fence(fence->fence);
3836 }
3837
3838 *pFence = radv_fence_to_handle(fence);
3839
3840 return VK_SUCCESS;
3841 }
3842
3843 void radv_DestroyFence(
3844 VkDevice _device,
3845 VkFence _fence,
3846 const VkAllocationCallbacks* pAllocator)
3847 {
3848 RADV_FROM_HANDLE(radv_device, device, _device);
3849 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3850
3851 if (!fence)
3852 return;
3853
3854 if (fence->temp_syncobj)
3855 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3856 if (fence->syncobj)
3857 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3858 if (fence->fence)
3859 device->ws->destroy_fence(fence->fence);
3860 if (fence->fence_wsi)
3861 fence->fence_wsi->destroy(fence->fence_wsi);
3862 vk_free2(&device->alloc, pAllocator, fence);
3863 }
3864
3865
3866 uint64_t radv_get_current_time(void)
3867 {
3868 struct timespec tv;
3869 clock_gettime(CLOCK_MONOTONIC, &tv);
3870 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3871 }
3872
3873 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3874 {
3875 uint64_t current_time = radv_get_current_time();
3876
3877 timeout = MIN2(UINT64_MAX - current_time, timeout);
3878
3879 return current_time + timeout;
3880 }
3881
3882
3883 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3884 uint32_t fenceCount, const VkFence *pFences)
3885 {
3886 for (uint32_t i = 0; i < fenceCount; ++i) {
3887 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3888 if (fence->fence == NULL || fence->syncobj ||
3889 fence->temp_syncobj || fence->fence_wsi ||
3890 (!device->ws->is_fence_waitable(fence->fence)))
3891 return false;
3892 }
3893 return true;
3894 }
3895
3896 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3897 {
3898 for (uint32_t i = 0; i < fenceCount; ++i) {
3899 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3900 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3901 return false;
3902 }
3903 return true;
3904 }
3905
3906 VkResult radv_WaitForFences(
3907 VkDevice _device,
3908 uint32_t fenceCount,
3909 const VkFence* pFences,
3910 VkBool32 waitAll,
3911 uint64_t timeout)
3912 {
3913 RADV_FROM_HANDLE(radv_device, device, _device);
3914 timeout = radv_get_absolute_timeout(timeout);
3915
3916 if (device->always_use_syncobj &&
3917 radv_all_fences_syncobj(fenceCount, pFences))
3918 {
3919 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3920 if (!handles)
3921 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3922
3923 for (uint32_t i = 0; i < fenceCount; ++i) {
3924 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3925 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3926 }
3927
3928 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3929
3930 free(handles);
3931 return success ? VK_SUCCESS : VK_TIMEOUT;
3932 }
3933
3934 if (!waitAll && fenceCount > 1) {
3935 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3936 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3937 uint32_t wait_count = 0;
3938 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3939 if (!fences)
3940 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3941
3942 for (uint32_t i = 0; i < fenceCount; ++i) {
3943 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3944
3945 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3946 free(fences);
3947 return VK_SUCCESS;
3948 }
3949
3950 fences[wait_count++] = fence->fence;
3951 }
3952
3953 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3954 waitAll, timeout - radv_get_current_time());
3955
3956 free(fences);
3957 return success ? VK_SUCCESS : VK_TIMEOUT;
3958 }
3959
3960 while(radv_get_current_time() <= timeout) {
3961 for (uint32_t i = 0; i < fenceCount; ++i) {
3962 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3963 return VK_SUCCESS;
3964 }
3965 }
3966 return VK_TIMEOUT;
3967 }
3968
3969 for (uint32_t i = 0; i < fenceCount; ++i) {
3970 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3971 bool expired = false;
3972
3973 if (fence->temp_syncobj) {
3974 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3975 return VK_TIMEOUT;
3976 continue;
3977 }
3978
3979 if (fence->syncobj) {
3980 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3981 return VK_TIMEOUT;
3982 continue;
3983 }
3984
3985 if (fence->fence) {
3986 if (!device->ws->is_fence_waitable(fence->fence)) {
3987 while(!device->ws->is_fence_waitable(fence->fence) &&
3988 radv_get_current_time() <= timeout)
3989 /* Do nothing */;
3990 }
3991
3992 expired = device->ws->fence_wait(device->ws,
3993 fence->fence,
3994 true, timeout);
3995 if (!expired)
3996 return VK_TIMEOUT;
3997 }
3998
3999 if (fence->fence_wsi) {
4000 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4001 if (result != VK_SUCCESS)
4002 return result;
4003 }
4004 }
4005
4006 return VK_SUCCESS;
4007 }
4008
4009 VkResult radv_ResetFences(VkDevice _device,
4010 uint32_t fenceCount,
4011 const VkFence *pFences)
4012 {
4013 RADV_FROM_HANDLE(radv_device, device, _device);
4014
4015 for (unsigned i = 0; i < fenceCount; ++i) {
4016 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4017 if (fence->fence)
4018 device->ws->reset_fence(fence->fence);
4019
4020 /* Per spec, we first restore the permanent payload, and then reset, so
4021 * having a temp syncobj should not skip resetting the permanent syncobj. */
4022 if (fence->temp_syncobj) {
4023 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4024 fence->temp_syncobj = 0;
4025 }
4026
4027 if (fence->syncobj) {
4028 device->ws->reset_syncobj(device->ws, fence->syncobj);
4029 }
4030 }
4031
4032 return VK_SUCCESS;
4033 }
4034
4035 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4036 {
4037 RADV_FROM_HANDLE(radv_device, device, _device);
4038 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4039
4040 if (fence->temp_syncobj) {
4041 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4042 return success ? VK_SUCCESS : VK_NOT_READY;
4043 }
4044
4045 if (fence->syncobj) {
4046 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4047 return success ? VK_SUCCESS : VK_NOT_READY;
4048 }
4049
4050 if (fence->fence) {
4051 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4052 return VK_NOT_READY;
4053 }
4054 if (fence->fence_wsi) {
4055 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4056
4057 if (result != VK_SUCCESS) {
4058 if (result == VK_TIMEOUT)
4059 return VK_NOT_READY;
4060 return result;
4061 }
4062 }
4063 return VK_SUCCESS;
4064 }
4065
4066
4067 // Queue semaphore functions
4068
4069 VkResult radv_CreateSemaphore(
4070 VkDevice _device,
4071 const VkSemaphoreCreateInfo* pCreateInfo,
4072 const VkAllocationCallbacks* pAllocator,
4073 VkSemaphore* pSemaphore)
4074 {
4075 RADV_FROM_HANDLE(radv_device, device, _device);
4076 const VkExportSemaphoreCreateInfo *export =
4077 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4078 VkExternalSemaphoreHandleTypeFlags handleTypes =
4079 export ? export->handleTypes : 0;
4080
4081 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4082 sizeof(*sem), 8,
4083 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4084 if (!sem)
4085 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4086
4087 sem->temp_syncobj = 0;
4088 /* create a syncobject if we are going to export this semaphore */
4089 if (device->always_use_syncobj || handleTypes) {
4090 assert (device->physical_device->rad_info.has_syncobj);
4091 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4092 if (ret) {
4093 vk_free2(&device->alloc, pAllocator, sem);
4094 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4095 }
4096 sem->sem = NULL;
4097 } else {
4098 sem->sem = device->ws->create_sem(device->ws);
4099 if (!sem->sem) {
4100 vk_free2(&device->alloc, pAllocator, sem);
4101 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4102 }
4103 sem->syncobj = 0;
4104 }
4105
4106 *pSemaphore = radv_semaphore_to_handle(sem);
4107 return VK_SUCCESS;
4108 }
4109
4110 void radv_DestroySemaphore(
4111 VkDevice _device,
4112 VkSemaphore _semaphore,
4113 const VkAllocationCallbacks* pAllocator)
4114 {
4115 RADV_FROM_HANDLE(radv_device, device, _device);
4116 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4117 if (!_semaphore)
4118 return;
4119
4120 if (sem->syncobj)
4121 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4122 else
4123 device->ws->destroy_sem(sem->sem);
4124 vk_free2(&device->alloc, pAllocator, sem);
4125 }
4126
4127 VkResult radv_CreateEvent(
4128 VkDevice _device,
4129 const VkEventCreateInfo* pCreateInfo,
4130 const VkAllocationCallbacks* pAllocator,
4131 VkEvent* pEvent)
4132 {
4133 RADV_FROM_HANDLE(radv_device, device, _device);
4134 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4135 sizeof(*event), 8,
4136 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4137
4138 if (!event)
4139 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4140
4141 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4142 RADEON_DOMAIN_GTT,
4143 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4144 RADV_BO_PRIORITY_FENCE);
4145 if (!event->bo) {
4146 vk_free2(&device->alloc, pAllocator, event);
4147 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4148 }
4149
4150 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4151
4152 *pEvent = radv_event_to_handle(event);
4153
4154 return VK_SUCCESS;
4155 }
4156
4157 void radv_DestroyEvent(
4158 VkDevice _device,
4159 VkEvent _event,
4160 const VkAllocationCallbacks* pAllocator)
4161 {
4162 RADV_FROM_HANDLE(radv_device, device, _device);
4163 RADV_FROM_HANDLE(radv_event, event, _event);
4164
4165 if (!event)
4166 return;
4167 device->ws->buffer_destroy(event->bo);
4168 vk_free2(&device->alloc, pAllocator, event);
4169 }
4170
4171 VkResult radv_GetEventStatus(
4172 VkDevice _device,
4173 VkEvent _event)
4174 {
4175 RADV_FROM_HANDLE(radv_event, event, _event);
4176
4177 if (*event->map == 1)
4178 return VK_EVENT_SET;
4179 return VK_EVENT_RESET;
4180 }
4181
4182 VkResult radv_SetEvent(
4183 VkDevice _device,
4184 VkEvent _event)
4185 {
4186 RADV_FROM_HANDLE(radv_event, event, _event);
4187 *event->map = 1;
4188
4189 return VK_SUCCESS;
4190 }
4191
4192 VkResult radv_ResetEvent(
4193 VkDevice _device,
4194 VkEvent _event)
4195 {
4196 RADV_FROM_HANDLE(radv_event, event, _event);
4197 *event->map = 0;
4198
4199 return VK_SUCCESS;
4200 }
4201
4202 VkResult radv_CreateBuffer(
4203 VkDevice _device,
4204 const VkBufferCreateInfo* pCreateInfo,
4205 const VkAllocationCallbacks* pAllocator,
4206 VkBuffer* pBuffer)
4207 {
4208 RADV_FROM_HANDLE(radv_device, device, _device);
4209 struct radv_buffer *buffer;
4210
4211 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4212
4213 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4214 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4215 if (buffer == NULL)
4216 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4217
4218 buffer->size = pCreateInfo->size;
4219 buffer->usage = pCreateInfo->usage;
4220 buffer->bo = NULL;
4221 buffer->offset = 0;
4222 buffer->flags = pCreateInfo->flags;
4223
4224 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4225 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4226
4227 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4228 buffer->bo = device->ws->buffer_create(device->ws,
4229 align64(buffer->size, 4096),
4230 4096, 0, RADEON_FLAG_VIRTUAL,
4231 RADV_BO_PRIORITY_VIRTUAL);
4232 if (!buffer->bo) {
4233 vk_free2(&device->alloc, pAllocator, buffer);
4234 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4235 }
4236 }
4237
4238 *pBuffer = radv_buffer_to_handle(buffer);
4239
4240 return VK_SUCCESS;
4241 }
4242
4243 void radv_DestroyBuffer(
4244 VkDevice _device,
4245 VkBuffer _buffer,
4246 const VkAllocationCallbacks* pAllocator)
4247 {
4248 RADV_FROM_HANDLE(radv_device, device, _device);
4249 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4250
4251 if (!buffer)
4252 return;
4253
4254 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4255 device->ws->buffer_destroy(buffer->bo);
4256
4257 vk_free2(&device->alloc, pAllocator, buffer);
4258 }
4259
4260 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4261 VkDevice device,
4262 const VkBufferDeviceAddressInfoEXT* pInfo)
4263 {
4264 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4265 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4266 }
4267
4268
4269 static inline unsigned
4270 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4271 {
4272 if (stencil)
4273 return plane->surface.u.legacy.stencil_tiling_index[level];
4274 else
4275 return plane->surface.u.legacy.tiling_index[level];
4276 }
4277
4278 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4279 {
4280 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4281 }
4282
4283 static uint32_t
4284 radv_init_dcc_control_reg(struct radv_device *device,
4285 struct radv_image_view *iview)
4286 {
4287 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4288 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4289 unsigned max_compressed_block_size;
4290 unsigned independent_128b_blocks;
4291 unsigned independent_64b_blocks;
4292
4293 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4294 return 0;
4295
4296 if (!device->physical_device->rad_info.has_dedicated_vram) {
4297 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4298 * dGPU and 64 for APU because all of our APUs to date use
4299 * DIMMs which have a request granularity size of 64B while all
4300 * other chips have a 32B request size.
4301 */
4302 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4303 }
4304
4305 if (device->physical_device->rad_info.chip_class >= GFX10) {
4306 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4307 independent_64b_blocks = 0;
4308 independent_128b_blocks = 1;
4309 } else {
4310 independent_128b_blocks = 0;
4311
4312 if (iview->image->info.samples > 1) {
4313 if (iview->image->planes[0].surface.bpe == 1)
4314 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4315 else if (iview->image->planes[0].surface.bpe == 2)
4316 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4317 }
4318
4319 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4320 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4321 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4322 /* If this DCC image is potentially going to be used in texture
4323 * fetches, we need some special settings.
4324 */
4325 independent_64b_blocks = 1;
4326 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4327 } else {
4328 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4329 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4330 * big as possible for better compression state.
4331 */
4332 independent_64b_blocks = 0;
4333 max_compressed_block_size = max_uncompressed_block_size;
4334 }
4335 }
4336
4337 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4338 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4339 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4340 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4341 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4342 }
4343
4344 static void
4345 radv_initialise_color_surface(struct radv_device *device,
4346 struct radv_color_buffer_info *cb,
4347 struct radv_image_view *iview)
4348 {
4349 const struct vk_format_description *desc;
4350 unsigned ntype, format, swap, endian;
4351 unsigned blend_clamp = 0, blend_bypass = 0;
4352 uint64_t va;
4353 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4354 const struct radeon_surf *surf = &plane->surface;
4355
4356 desc = vk_format_description(iview->vk_format);
4357
4358 memset(cb, 0, sizeof(*cb));
4359
4360 /* Intensity is implemented as Red, so treat it that way. */
4361 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4362
4363 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4364
4365 cb->cb_color_base = va >> 8;
4366
4367 if (device->physical_device->rad_info.chip_class >= GFX9) {
4368 struct gfx9_surf_meta_flags meta;
4369 if (iview->image->dcc_offset)
4370 meta = surf->u.gfx9.dcc;
4371 else
4372 meta = surf->u.gfx9.cmask;
4373
4374 if (device->physical_device->rad_info.chip_class >= GFX10) {
4375 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4376 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4377 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4378 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4379 } else {
4380 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4381 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4382 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4383 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4384 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4385 }
4386
4387 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4388 cb->cb_color_base |= surf->tile_swizzle;
4389 } else {
4390 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4391 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4392
4393 cb->cb_color_base += level_info->offset >> 8;
4394 if (level_info->mode == RADEON_SURF_MODE_2D)
4395 cb->cb_color_base |= surf->tile_swizzle;
4396
4397 pitch_tile_max = level_info->nblk_x / 8 - 1;
4398 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4399 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4400
4401 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4402 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4403 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4404
4405 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4406
4407 if (radv_image_has_fmask(iview->image)) {
4408 if (device->physical_device->rad_info.chip_class >= GFX7)
4409 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4410 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4411 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4412 } else {
4413 /* This must be set for fast clear to work without FMASK. */
4414 if (device->physical_device->rad_info.chip_class >= GFX7)
4415 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4416 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4417 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4418 }
4419 }
4420
4421 /* CMASK variables */
4422 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4423 va += iview->image->cmask.offset;
4424 cb->cb_color_cmask = va >> 8;
4425
4426 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4427 va += iview->image->dcc_offset;
4428
4429 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4430 device->physical_device->rad_info.chip_class <= GFX8)
4431 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4432
4433 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4434 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4435
4436 cb->cb_dcc_base = va >> 8;
4437 cb->cb_dcc_base |= dcc_tile_swizzle;
4438
4439 /* GFX10 field has the same base shift as the GFX6 field. */
4440 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4441 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4442 S_028C6C_SLICE_MAX_GFX10(max_slice);
4443
4444 if (iview->image->info.samples > 1) {
4445 unsigned log_samples = util_logbase2(iview->image->info.samples);
4446
4447 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4448 S_028C74_NUM_FRAGMENTS(log_samples);
4449 }
4450
4451 if (radv_image_has_fmask(iview->image)) {
4452 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4453 cb->cb_color_fmask = va >> 8;
4454 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4455 } else {
4456 cb->cb_color_fmask = cb->cb_color_base;
4457 }
4458
4459 ntype = radv_translate_color_numformat(iview->vk_format,
4460 desc,
4461 vk_format_get_first_non_void_channel(iview->vk_format));
4462 format = radv_translate_colorformat(iview->vk_format);
4463 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4464 radv_finishme("Illegal color\n");
4465 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4466 endian = radv_colorformat_endian_swap(format);
4467
4468 /* blend clamp should be set for all NORM/SRGB types */
4469 if (ntype == V_028C70_NUMBER_UNORM ||
4470 ntype == V_028C70_NUMBER_SNORM ||
4471 ntype == V_028C70_NUMBER_SRGB)
4472 blend_clamp = 1;
4473
4474 /* set blend bypass according to docs if SINT/UINT or
4475 8/24 COLOR variants */
4476 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4477 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4478 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4479 blend_clamp = 0;
4480 blend_bypass = 1;
4481 }
4482 #if 0
4483 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4484 (format == V_028C70_COLOR_8 ||
4485 format == V_028C70_COLOR_8_8 ||
4486 format == V_028C70_COLOR_8_8_8_8))
4487 ->color_is_int8 = true;
4488 #endif
4489 cb->cb_color_info = S_028C70_FORMAT(format) |
4490 S_028C70_COMP_SWAP(swap) |
4491 S_028C70_BLEND_CLAMP(blend_clamp) |
4492 S_028C70_BLEND_BYPASS(blend_bypass) |
4493 S_028C70_SIMPLE_FLOAT(1) |
4494 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4495 ntype != V_028C70_NUMBER_SNORM &&
4496 ntype != V_028C70_NUMBER_SRGB &&
4497 format != V_028C70_COLOR_8_24 &&
4498 format != V_028C70_COLOR_24_8) |
4499 S_028C70_NUMBER_TYPE(ntype) |
4500 S_028C70_ENDIAN(endian);
4501 if (radv_image_has_fmask(iview->image)) {
4502 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4503 if (device->physical_device->rad_info.chip_class == GFX6) {
4504 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4505 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4506 }
4507
4508 if (radv_image_is_tc_compat_cmask(iview->image)) {
4509 /* Allow the texture block to read FMASK directly
4510 * without decompressing it. This bit must be cleared
4511 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4512 * otherwise the operation doesn't happen.
4513 */
4514 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4515
4516 /* Set CMASK into a tiling format that allows the
4517 * texture block to read it.
4518 */
4519 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4520 }
4521 }
4522
4523 if (radv_image_has_cmask(iview->image) &&
4524 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4525 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4526
4527 if (radv_dcc_enabled(iview->image, iview->base_mip))
4528 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4529
4530 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4531
4532 /* This must be set for fast clear to work without FMASK. */
4533 if (!radv_image_has_fmask(iview->image) &&
4534 device->physical_device->rad_info.chip_class == GFX6) {
4535 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4536 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4537 }
4538
4539 if (device->physical_device->rad_info.chip_class >= GFX9) {
4540 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4541
4542 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4543 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4544 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4545 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4546
4547 if (device->physical_device->rad_info.chip_class >= GFX10) {
4548 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4549
4550 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4551 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4552 S_028EE0_RESOURCE_LEVEL(1);
4553 } else {
4554 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4555 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4556 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4557 }
4558
4559 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4560 S_028C68_MIP0_HEIGHT(height - 1) |
4561 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4562 }
4563 }
4564
4565 static unsigned
4566 radv_calc_decompress_on_z_planes(struct radv_device *device,
4567 struct radv_image_view *iview)
4568 {
4569 unsigned max_zplanes = 0;
4570
4571 assert(radv_image_is_tc_compat_htile(iview->image));
4572
4573 if (device->physical_device->rad_info.chip_class >= GFX9) {
4574 /* Default value for 32-bit depth surfaces. */
4575 max_zplanes = 4;
4576
4577 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4578 iview->image->info.samples > 1)
4579 max_zplanes = 2;
4580
4581 max_zplanes = max_zplanes + 1;
4582 } else {
4583 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4584 /* Do not enable Z plane compression for 16-bit depth
4585 * surfaces because isn't supported on GFX8. Only
4586 * 32-bit depth surfaces are supported by the hardware.
4587 * This allows to maintain shader compatibility and to
4588 * reduce the number of depth decompressions.
4589 */
4590 max_zplanes = 1;
4591 } else {
4592 if (iview->image->info.samples <= 1)
4593 max_zplanes = 5;
4594 else if (iview->image->info.samples <= 4)
4595 max_zplanes = 3;
4596 else
4597 max_zplanes = 2;
4598 }
4599 }
4600
4601 return max_zplanes;
4602 }
4603
4604 static void
4605 radv_initialise_ds_surface(struct radv_device *device,
4606 struct radv_ds_buffer_info *ds,
4607 struct radv_image_view *iview)
4608 {
4609 unsigned level = iview->base_mip;
4610 unsigned format, stencil_format;
4611 uint64_t va, s_offs, z_offs;
4612 bool stencil_only = false;
4613 const struct radv_image_plane *plane = &iview->image->planes[0];
4614 const struct radeon_surf *surf = &plane->surface;
4615
4616 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4617
4618 memset(ds, 0, sizeof(*ds));
4619 switch (iview->image->vk_format) {
4620 case VK_FORMAT_D24_UNORM_S8_UINT:
4621 case VK_FORMAT_X8_D24_UNORM_PACK32:
4622 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4623 ds->offset_scale = 2.0f;
4624 break;
4625 case VK_FORMAT_D16_UNORM:
4626 case VK_FORMAT_D16_UNORM_S8_UINT:
4627 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4628 ds->offset_scale = 4.0f;
4629 break;
4630 case VK_FORMAT_D32_SFLOAT:
4631 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4632 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4633 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4634 ds->offset_scale = 1.0f;
4635 break;
4636 case VK_FORMAT_S8_UINT:
4637 stencil_only = true;
4638 break;
4639 default:
4640 break;
4641 }
4642
4643 format = radv_translate_dbformat(iview->image->vk_format);
4644 stencil_format = surf->has_stencil ?
4645 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4646
4647 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4648 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4649 S_028008_SLICE_MAX(max_slice);
4650 if (device->physical_device->rad_info.chip_class >= GFX10) {
4651 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4652 S_028008_SLICE_MAX_HI(max_slice >> 11);
4653 }
4654
4655 ds->db_htile_data_base = 0;
4656 ds->db_htile_surface = 0;
4657
4658 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4659 s_offs = z_offs = va;
4660
4661 if (device->physical_device->rad_info.chip_class >= GFX9) {
4662 assert(surf->u.gfx9.surf_offset == 0);
4663 s_offs += surf->u.gfx9.stencil_offset;
4664
4665 ds->db_z_info = S_028038_FORMAT(format) |
4666 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4667 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4668 S_028038_MAXMIP(iview->image->info.levels - 1) |
4669 S_028038_ZRANGE_PRECISION(1);
4670 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4671 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4672
4673 if (device->physical_device->rad_info.chip_class == GFX9) {
4674 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4675 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4676 }
4677
4678 ds->db_depth_view |= S_028008_MIPID(level);
4679 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4680 S_02801C_Y_MAX(iview->image->info.height - 1);
4681
4682 if (radv_htile_enabled(iview->image, level)) {
4683 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4684
4685 if (radv_image_is_tc_compat_htile(iview->image)) {
4686 unsigned max_zplanes =
4687 radv_calc_decompress_on_z_planes(device, iview);
4688
4689 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4690
4691 if (device->physical_device->rad_info.chip_class >= GFX10) {
4692 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4693 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4694 } else {
4695 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4696 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4697 }
4698 }
4699
4700 if (!surf->has_stencil)
4701 /* Use all of the htile_buffer for depth if there's no stencil. */
4702 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4703 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4704 iview->image->htile_offset;
4705 ds->db_htile_data_base = va >> 8;
4706 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4707 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4708
4709 if (device->physical_device->rad_info.chip_class == GFX9) {
4710 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4711 }
4712 }
4713 } else {
4714 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4715
4716 if (stencil_only)
4717 level_info = &surf->u.legacy.stencil_level[level];
4718
4719 z_offs += surf->u.legacy.level[level].offset;
4720 s_offs += surf->u.legacy.stencil_level[level].offset;
4721
4722 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4723 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4724 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4725
4726 if (iview->image->info.samples > 1)
4727 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4728
4729 if (device->physical_device->rad_info.chip_class >= GFX7) {
4730 struct radeon_info *info = &device->physical_device->rad_info;
4731 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4732 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4733 unsigned macro_index = surf->u.legacy.macro_tile_index;
4734 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4735 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4736 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4737
4738 if (stencil_only)
4739 tile_mode = stencil_tile_mode;
4740
4741 ds->db_depth_info |=
4742 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4743 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4744 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4745 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4746 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4747 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4748 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4749 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4750 } else {
4751 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4752 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4753 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4754 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4755 if (stencil_only)
4756 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4757 }
4758
4759 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4760 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4761 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4762
4763 if (radv_htile_enabled(iview->image, level)) {
4764 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4765
4766 if (!surf->has_stencil &&
4767 !radv_image_is_tc_compat_htile(iview->image))
4768 /* Use all of the htile_buffer for depth if there's no stencil. */
4769 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4770
4771 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4772 iview->image->htile_offset;
4773 ds->db_htile_data_base = va >> 8;
4774 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4775
4776 if (radv_image_is_tc_compat_htile(iview->image)) {
4777 unsigned max_zplanes =
4778 radv_calc_decompress_on_z_planes(device, iview);
4779
4780 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4781 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4782 }
4783 }
4784 }
4785
4786 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4787 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4788 }
4789
4790 VkResult radv_CreateFramebuffer(
4791 VkDevice _device,
4792 const VkFramebufferCreateInfo* pCreateInfo,
4793 const VkAllocationCallbacks* pAllocator,
4794 VkFramebuffer* pFramebuffer)
4795 {
4796 RADV_FROM_HANDLE(radv_device, device, _device);
4797 struct radv_framebuffer *framebuffer;
4798
4799 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4800
4801 size_t size = sizeof(*framebuffer) +
4802 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4803 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4804 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4805 if (framebuffer == NULL)
4806 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4807
4808 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4809 framebuffer->width = pCreateInfo->width;
4810 framebuffer->height = pCreateInfo->height;
4811 framebuffer->layers = pCreateInfo->layers;
4812 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4813 VkImageView _iview = pCreateInfo->pAttachments[i];
4814 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4815 framebuffer->attachments[i].attachment = iview;
4816 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4817 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4818 } else {
4819 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4820 }
4821 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4822 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4823 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4824 }
4825
4826 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4827 return VK_SUCCESS;
4828 }
4829
4830 void radv_DestroyFramebuffer(
4831 VkDevice _device,
4832 VkFramebuffer _fb,
4833 const VkAllocationCallbacks* pAllocator)
4834 {
4835 RADV_FROM_HANDLE(radv_device, device, _device);
4836 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4837
4838 if (!fb)
4839 return;
4840 vk_free2(&device->alloc, pAllocator, fb);
4841 }
4842
4843 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4844 {
4845 switch (address_mode) {
4846 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4847 return V_008F30_SQ_TEX_WRAP;
4848 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4849 return V_008F30_SQ_TEX_MIRROR;
4850 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4851 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4852 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4853 return V_008F30_SQ_TEX_CLAMP_BORDER;
4854 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4855 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4856 default:
4857 unreachable("illegal tex wrap mode");
4858 break;
4859 }
4860 }
4861
4862 static unsigned
4863 radv_tex_compare(VkCompareOp op)
4864 {
4865 switch (op) {
4866 case VK_COMPARE_OP_NEVER:
4867 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4868 case VK_COMPARE_OP_LESS:
4869 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4870 case VK_COMPARE_OP_EQUAL:
4871 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4872 case VK_COMPARE_OP_LESS_OR_EQUAL:
4873 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4874 case VK_COMPARE_OP_GREATER:
4875 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4876 case VK_COMPARE_OP_NOT_EQUAL:
4877 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4878 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4879 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4880 case VK_COMPARE_OP_ALWAYS:
4881 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4882 default:
4883 unreachable("illegal compare mode");
4884 break;
4885 }
4886 }
4887
4888 static unsigned
4889 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4890 {
4891 switch (filter) {
4892 case VK_FILTER_NEAREST:
4893 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4894 V_008F38_SQ_TEX_XY_FILTER_POINT);
4895 case VK_FILTER_LINEAR:
4896 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4897 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4898 case VK_FILTER_CUBIC_IMG:
4899 default:
4900 fprintf(stderr, "illegal texture filter");
4901 return 0;
4902 }
4903 }
4904
4905 static unsigned
4906 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4907 {
4908 switch (mode) {
4909 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4910 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4911 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4912 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4913 default:
4914 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4915 }
4916 }
4917
4918 static unsigned
4919 radv_tex_bordercolor(VkBorderColor bcolor)
4920 {
4921 switch (bcolor) {
4922 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4923 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4924 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4925 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4926 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4927 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4928 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4929 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4930 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4931 default:
4932 break;
4933 }
4934 return 0;
4935 }
4936
4937 static unsigned
4938 radv_tex_aniso_filter(unsigned filter)
4939 {
4940 if (filter < 2)
4941 return 0;
4942 if (filter < 4)
4943 return 1;
4944 if (filter < 8)
4945 return 2;
4946 if (filter < 16)
4947 return 3;
4948 return 4;
4949 }
4950
4951 static unsigned
4952 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4953 {
4954 switch (mode) {
4955 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4956 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4957 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4958 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4959 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4960 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4961 default:
4962 break;
4963 }
4964 return 0;
4965 }
4966
4967 static uint32_t
4968 radv_get_max_anisotropy(struct radv_device *device,
4969 const VkSamplerCreateInfo *pCreateInfo)
4970 {
4971 if (device->force_aniso >= 0)
4972 return device->force_aniso;
4973
4974 if (pCreateInfo->anisotropyEnable &&
4975 pCreateInfo->maxAnisotropy > 1.0f)
4976 return (uint32_t)pCreateInfo->maxAnisotropy;
4977
4978 return 0;
4979 }
4980
4981 static void
4982 radv_init_sampler(struct radv_device *device,
4983 struct radv_sampler *sampler,
4984 const VkSamplerCreateInfo *pCreateInfo)
4985 {
4986 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4987 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4988 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4989 device->physical_device->rad_info.chip_class == GFX9;
4990 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4991
4992 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4993 vk_find_struct_const(pCreateInfo->pNext,
4994 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4995 if (sampler_reduction)
4996 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4997
4998 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4999 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5000 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5001 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5002 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5003 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5004 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5005 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5006 S_008F30_DISABLE_CUBE_WRAP(0) |
5007 S_008F30_COMPAT_MODE(compat_mode) |
5008 S_008F30_FILTER_MODE(filter_mode));
5009 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5010 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5011 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5012 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5013 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5014 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5015 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5016 S_008F38_MIP_POINT_PRECLAMP(0));
5017 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5018 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5019
5020 if (device->physical_device->rad_info.chip_class >= GFX10) {
5021 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5022 } else {
5023 sampler->state[2] |=
5024 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5025 S_008F38_FILTER_PREC_FIX(1) |
5026 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5027 }
5028 }
5029
5030 VkResult radv_CreateSampler(
5031 VkDevice _device,
5032 const VkSamplerCreateInfo* pCreateInfo,
5033 const VkAllocationCallbacks* pAllocator,
5034 VkSampler* pSampler)
5035 {
5036 RADV_FROM_HANDLE(radv_device, device, _device);
5037 struct radv_sampler *sampler;
5038
5039 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5040 vk_find_struct_const(pCreateInfo->pNext,
5041 SAMPLER_YCBCR_CONVERSION_INFO);
5042
5043 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5044
5045 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5046 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5047 if (!sampler)
5048 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5049
5050 radv_init_sampler(device, sampler, pCreateInfo);
5051
5052 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5053 *pSampler = radv_sampler_to_handle(sampler);
5054
5055 return VK_SUCCESS;
5056 }
5057
5058 void radv_DestroySampler(
5059 VkDevice _device,
5060 VkSampler _sampler,
5061 const VkAllocationCallbacks* pAllocator)
5062 {
5063 RADV_FROM_HANDLE(radv_device, device, _device);
5064 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5065
5066 if (!sampler)
5067 return;
5068 vk_free2(&device->alloc, pAllocator, sampler);
5069 }
5070
5071 /* vk_icd.h does not declare this function, so we declare it here to
5072 * suppress Wmissing-prototypes.
5073 */
5074 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5075 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5076
5077 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5078 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5079 {
5080 /* For the full details on loader interface versioning, see
5081 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5082 * What follows is a condensed summary, to help you navigate the large and
5083 * confusing official doc.
5084 *
5085 * - Loader interface v0 is incompatible with later versions. We don't
5086 * support it.
5087 *
5088 * - In loader interface v1:
5089 * - The first ICD entrypoint called by the loader is
5090 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5091 * entrypoint.
5092 * - The ICD must statically expose no other Vulkan symbol unless it is
5093 * linked with -Bsymbolic.
5094 * - Each dispatchable Vulkan handle created by the ICD must be
5095 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5096 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5097 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5098 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5099 * such loader-managed surfaces.
5100 *
5101 * - Loader interface v2 differs from v1 in:
5102 * - The first ICD entrypoint called by the loader is
5103 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5104 * statically expose this entrypoint.
5105 *
5106 * - Loader interface v3 differs from v2 in:
5107 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5108 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5109 * because the loader no longer does so.
5110 */
5111 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5112 return VK_SUCCESS;
5113 }
5114
5115 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5116 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5117 int *pFD)
5118 {
5119 RADV_FROM_HANDLE(radv_device, device, _device);
5120 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5121
5122 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5123
5124 /* At the moment, we support only the below handle types. */
5125 assert(pGetFdInfo->handleType ==
5126 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5127 pGetFdInfo->handleType ==
5128 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5129
5130 bool ret = radv_get_memory_fd(device, memory, pFD);
5131 if (ret == false)
5132 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5133 return VK_SUCCESS;
5134 }
5135
5136 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5137 VkExternalMemoryHandleTypeFlagBits handleType,
5138 int fd,
5139 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5140 {
5141 RADV_FROM_HANDLE(radv_device, device, _device);
5142
5143 switch (handleType) {
5144 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5145 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5146 return VK_SUCCESS;
5147
5148 default:
5149 /* The valid usage section for this function says:
5150 *
5151 * "handleType must not be one of the handle types defined as
5152 * opaque."
5153 *
5154 * So opaque handle types fall into the default "unsupported" case.
5155 */
5156 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5157 }
5158 }
5159
5160 static VkResult radv_import_opaque_fd(struct radv_device *device,
5161 int fd,
5162 uint32_t *syncobj)
5163 {
5164 uint32_t syncobj_handle = 0;
5165 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5166 if (ret != 0)
5167 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5168
5169 if (*syncobj)
5170 device->ws->destroy_syncobj(device->ws, *syncobj);
5171
5172 *syncobj = syncobj_handle;
5173 close(fd);
5174
5175 return VK_SUCCESS;
5176 }
5177
5178 static VkResult radv_import_sync_fd(struct radv_device *device,
5179 int fd,
5180 uint32_t *syncobj)
5181 {
5182 /* If we create a syncobj we do it locally so that if we have an error, we don't
5183 * leave a syncobj in an undetermined state in the fence. */
5184 uint32_t syncobj_handle = *syncobj;
5185 if (!syncobj_handle) {
5186 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5187 if (ret) {
5188 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5189 }
5190 }
5191
5192 if (fd == -1) {
5193 device->ws->signal_syncobj(device->ws, syncobj_handle);
5194 } else {
5195 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5196 if (ret != 0)
5197 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5198 }
5199
5200 *syncobj = syncobj_handle;
5201 if (fd != -1)
5202 close(fd);
5203
5204 return VK_SUCCESS;
5205 }
5206
5207 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5208 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5209 {
5210 RADV_FROM_HANDLE(radv_device, device, _device);
5211 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5212 uint32_t *syncobj_dst = NULL;
5213
5214 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5215 syncobj_dst = &sem->temp_syncobj;
5216 } else {
5217 syncobj_dst = &sem->syncobj;
5218 }
5219
5220 switch(pImportSemaphoreFdInfo->handleType) {
5221 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5222 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5223 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5224 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5225 default:
5226 unreachable("Unhandled semaphore handle type");
5227 }
5228 }
5229
5230 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5231 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5232 int *pFd)
5233 {
5234 RADV_FROM_HANDLE(radv_device, device, _device);
5235 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5236 int ret;
5237 uint32_t syncobj_handle;
5238
5239 if (sem->temp_syncobj)
5240 syncobj_handle = sem->temp_syncobj;
5241 else
5242 syncobj_handle = sem->syncobj;
5243
5244 switch(pGetFdInfo->handleType) {
5245 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5246 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5247 break;
5248 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5249 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5250 if (!ret) {
5251 if (sem->temp_syncobj) {
5252 close (sem->temp_syncobj);
5253 sem->temp_syncobj = 0;
5254 } else {
5255 device->ws->reset_syncobj(device->ws, syncobj_handle);
5256 }
5257 }
5258 break;
5259 default:
5260 unreachable("Unhandled semaphore handle type");
5261 }
5262
5263 if (ret)
5264 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5265 return VK_SUCCESS;
5266 }
5267
5268 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5269 VkPhysicalDevice physicalDevice,
5270 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5271 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5272 {
5273 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5274
5275 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5276 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5277 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5278 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5279 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5280 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5281 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5282 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5283 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5284 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5285 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5286 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5287 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5288 } else {
5289 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5290 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5291 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5292 }
5293 }
5294
5295 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5296 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5297 {
5298 RADV_FROM_HANDLE(radv_device, device, _device);
5299 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5300 uint32_t *syncobj_dst = NULL;
5301
5302
5303 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5304 syncobj_dst = &fence->temp_syncobj;
5305 } else {
5306 syncobj_dst = &fence->syncobj;
5307 }
5308
5309 switch(pImportFenceFdInfo->handleType) {
5310 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5311 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5312 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5313 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5314 default:
5315 unreachable("Unhandled fence handle type");
5316 }
5317 }
5318
5319 VkResult radv_GetFenceFdKHR(VkDevice _device,
5320 const VkFenceGetFdInfoKHR *pGetFdInfo,
5321 int *pFd)
5322 {
5323 RADV_FROM_HANDLE(radv_device, device, _device);
5324 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5325 int ret;
5326 uint32_t syncobj_handle;
5327
5328 if (fence->temp_syncobj)
5329 syncobj_handle = fence->temp_syncobj;
5330 else
5331 syncobj_handle = fence->syncobj;
5332
5333 switch(pGetFdInfo->handleType) {
5334 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5335 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5336 break;
5337 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5338 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5339 if (!ret) {
5340 if (fence->temp_syncobj) {
5341 close (fence->temp_syncobj);
5342 fence->temp_syncobj = 0;
5343 } else {
5344 device->ws->reset_syncobj(device->ws, syncobj_handle);
5345 }
5346 }
5347 break;
5348 default:
5349 unreachable("Unhandled fence handle type");
5350 }
5351
5352 if (ret)
5353 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5354 return VK_SUCCESS;
5355 }
5356
5357 void radv_GetPhysicalDeviceExternalFenceProperties(
5358 VkPhysicalDevice physicalDevice,
5359 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5360 VkExternalFenceProperties *pExternalFenceProperties)
5361 {
5362 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5363
5364 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5365 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5366 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5367 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5368 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5369 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5370 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5371 } else {
5372 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5373 pExternalFenceProperties->compatibleHandleTypes = 0;
5374 pExternalFenceProperties->externalFenceFeatures = 0;
5375 }
5376 }
5377
5378 VkResult
5379 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5380 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5381 const VkAllocationCallbacks* pAllocator,
5382 VkDebugReportCallbackEXT* pCallback)
5383 {
5384 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5385 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5386 pCreateInfo, pAllocator, &instance->alloc,
5387 pCallback);
5388 }
5389
5390 void
5391 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5392 VkDebugReportCallbackEXT _callback,
5393 const VkAllocationCallbacks* pAllocator)
5394 {
5395 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5396 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5397 _callback, pAllocator, &instance->alloc);
5398 }
5399
5400 void
5401 radv_DebugReportMessageEXT(VkInstance _instance,
5402 VkDebugReportFlagsEXT flags,
5403 VkDebugReportObjectTypeEXT objectType,
5404 uint64_t object,
5405 size_t location,
5406 int32_t messageCode,
5407 const char* pLayerPrefix,
5408 const char* pMessage)
5409 {
5410 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5411 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5412 object, location, messageCode, pLayerPrefix, pMessage);
5413 }
5414
5415 void
5416 radv_GetDeviceGroupPeerMemoryFeatures(
5417 VkDevice device,
5418 uint32_t heapIndex,
5419 uint32_t localDeviceIndex,
5420 uint32_t remoteDeviceIndex,
5421 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5422 {
5423 assert(localDeviceIndex == remoteDeviceIndex);
5424
5425 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5426 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5427 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5428 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5429 }
5430
5431 static const VkTimeDomainEXT radv_time_domains[] = {
5432 VK_TIME_DOMAIN_DEVICE_EXT,
5433 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5434 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5435 };
5436
5437 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5438 VkPhysicalDevice physicalDevice,
5439 uint32_t *pTimeDomainCount,
5440 VkTimeDomainEXT *pTimeDomains)
5441 {
5442 int d;
5443 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5444
5445 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5446 vk_outarray_append(&out, i) {
5447 *i = radv_time_domains[d];
5448 }
5449 }
5450
5451 return vk_outarray_status(&out);
5452 }
5453
5454 static uint64_t
5455 radv_clock_gettime(clockid_t clock_id)
5456 {
5457 struct timespec current;
5458 int ret;
5459
5460 ret = clock_gettime(clock_id, &current);
5461 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5462 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5463 if (ret < 0)
5464 return 0;
5465
5466 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5467 }
5468
5469 VkResult radv_GetCalibratedTimestampsEXT(
5470 VkDevice _device,
5471 uint32_t timestampCount,
5472 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5473 uint64_t *pTimestamps,
5474 uint64_t *pMaxDeviation)
5475 {
5476 RADV_FROM_HANDLE(radv_device, device, _device);
5477 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5478 int d;
5479 uint64_t begin, end;
5480 uint64_t max_clock_period = 0;
5481
5482 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5483
5484 for (d = 0; d < timestampCount; d++) {
5485 switch (pTimestampInfos[d].timeDomain) {
5486 case VK_TIME_DOMAIN_DEVICE_EXT:
5487 pTimestamps[d] = device->ws->query_value(device->ws,
5488 RADEON_TIMESTAMP);
5489 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5490 max_clock_period = MAX2(max_clock_period, device_period);
5491 break;
5492 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5493 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5494 max_clock_period = MAX2(max_clock_period, 1);
5495 break;
5496
5497 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5498 pTimestamps[d] = begin;
5499 break;
5500 default:
5501 pTimestamps[d] = 0;
5502 break;
5503 }
5504 }
5505
5506 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5507
5508 /*
5509 * The maximum deviation is the sum of the interval over which we
5510 * perform the sampling and the maximum period of any sampled
5511 * clock. That's because the maximum skew between any two sampled
5512 * clock edges is when the sampled clock with the largest period is
5513 * sampled at the end of that period but right at the beginning of the
5514 * sampling interval and some other clock is sampled right at the
5515 * begining of its sampling period and right at the end of the
5516 * sampling interval. Let's assume the GPU has the longest clock
5517 * period and that the application is sampling GPU and monotonic:
5518 *
5519 * s e
5520 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5521 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5522 *
5523 * g
5524 * 0 1 2 3
5525 * GPU -----_____-----_____-----_____-----_____
5526 *
5527 * m
5528 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5529 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5530 *
5531 * Interval <----------------->
5532 * Deviation <-------------------------->
5533 *
5534 * s = read(raw) 2
5535 * g = read(GPU) 1
5536 * m = read(monotonic) 2
5537 * e = read(raw) b
5538 *
5539 * We round the sample interval up by one tick to cover sampling error
5540 * in the interval clock
5541 */
5542
5543 uint64_t sample_interval = end - begin + 1;
5544
5545 *pMaxDeviation = sample_interval + max_clock_period;
5546
5547 return VK_SUCCESS;
5548 }
5549
5550 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5551 VkPhysicalDevice physicalDevice,
5552 VkSampleCountFlagBits samples,
5553 VkMultisamplePropertiesEXT* pMultisampleProperties)
5554 {
5555 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5556 VK_SAMPLE_COUNT_4_BIT |
5557 VK_SAMPLE_COUNT_8_BIT)) {
5558 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5559 } else {
5560 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5561 }
5562 }