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radv/gfx10: adjust SGPRs/VGPRs related info
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44 #include <llvm/Config/llvm-config.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/xmlpool.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static int
88 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
89 {
90 struct mesa_sha1 ctx;
91 unsigned char sha1[20];
92 unsigned ptr_size = sizeof(void*);
93
94 memset(uuid, 0, VK_UUID_SIZE);
95 _mesa_sha1_init(&ctx);
96
97 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
98 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
99 return -1;
100
101 _mesa_sha1_update(&ctx, &family, sizeof(family));
102 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
103 _mesa_sha1_final(&ctx, sha1);
104
105 memcpy(uuid, sha1, VK_UUID_SIZE);
106 return 0;
107 }
108
109 static void
110 radv_get_driver_uuid(void *uuid)
111 {
112 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
113 }
114
115 static void
116 radv_get_device_uuid(struct radeon_info *info, void *uuid)
117 {
118 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
119 }
120
121 static uint64_t
122 radv_get_visible_vram_size(struct radv_physical_device *device)
123 {
124 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
125 }
126
127 static uint64_t
128 radv_get_vram_size(struct radv_physical_device *device)
129 {
130 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
131 }
132
133 static bool
134 radv_is_mem_type_vram(enum radv_mem_type type)
135 {
136 return type == RADV_MEM_TYPE_VRAM ||
137 type == RADV_MEM_TYPE_VRAM_UNCACHED;
138 }
139
140 static bool
141 radv_is_mem_type_vram_visible(enum radv_mem_type type)
142 {
143 return type == RADV_MEM_TYPE_VRAM_CPU_ACCESS ||
144 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
145 }
146 static bool
147 radv_is_mem_type_gtt_wc(enum radv_mem_type type)
148 {
149 return type == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
150 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
151 }
152
153 static bool
154 radv_is_mem_type_gtt_cached(enum radv_mem_type type)
155 {
156 return type == RADV_MEM_TYPE_GTT_CACHED ||
157 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
158 }
159
160 static bool
161 radv_is_mem_type_uncached(enum radv_mem_type type)
162 {
163 return type == RADV_MEM_TYPE_VRAM_UNCACHED ||
164 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED ||
165 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED ||
166 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
167 }
168
169 static void
170 radv_physical_device_init_mem_types(struct radv_physical_device *device)
171 {
172 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
173 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
174 uint64_t vram_size = radv_get_vram_size(device);
175 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
176 device->memory_properties.memoryHeapCount = 0;
177 if (vram_size > 0) {
178 vram_index = device->memory_properties.memoryHeapCount++;
179 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
180 .size = vram_size,
181 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
182 };
183 }
184 if (visible_vram_size) {
185 visible_vram_index = device->memory_properties.memoryHeapCount++;
186 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
187 .size = visible_vram_size,
188 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
189 };
190 }
191 if (device->rad_info.gart_size > 0) {
192 gart_index = device->memory_properties.memoryHeapCount++;
193 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
194 .size = device->rad_info.gart_size,
195 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
196 };
197 }
198
199 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
200 unsigned type_count = 0;
201 if (vram_index >= 0) {
202 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
203 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
204 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
205 .heapIndex = vram_index,
206 };
207 }
208 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
209 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
210 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
211 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
212 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
213 .heapIndex = gart_index,
214 };
215 }
216 if (visible_vram_index >= 0) {
217 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
218 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
219 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
220 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
221 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
222 .heapIndex = visible_vram_index,
223 };
224 }
225 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
226 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
227 * as they have identical property flags, and according to the
228 * spec, for types with identical flags, the one with greater
229 * performance must be given a lower index. */
230 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
231 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
232 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
233 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
234 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
235 .heapIndex = gart_index,
236 };
237 }
238 if (gart_index >= 0) {
239 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
242 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
243 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
244 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
245 .heapIndex = gart_index,
246 };
247 }
248 device->memory_properties.memoryTypeCount = type_count;
249
250 if (device->rad_info.has_l2_uncached) {
251 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
252 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
253
254 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
255 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
256 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
257 enum radv_mem_type mem_type_id;
258
259 switch (device->mem_type_indices[i]) {
260 case RADV_MEM_TYPE_VRAM:
261 mem_type_id = RADV_MEM_TYPE_VRAM_UNCACHED;
262 break;
263 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
264 mem_type_id = RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
265 break;
266 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
267 mem_type_id = RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
268 break;
269 case RADV_MEM_TYPE_GTT_CACHED:
270 mem_type_id = RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
271 break;
272 default:
273 unreachable("invalid memory type");
274 }
275
276 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
277 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
278 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
279
280 device->mem_type_indices[type_count] = mem_type_id;
281 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
282 .propertyFlags = property_flags,
283 .heapIndex = mem_type.heapIndex,
284 };
285 }
286 }
287 device->memory_properties.memoryTypeCount = type_count;
288 }
289 }
290
291 static VkResult
292 radv_physical_device_init(struct radv_physical_device *device,
293 struct radv_instance *instance,
294 drmDevicePtr drm_device)
295 {
296 VkResult result;
297 int fd = -1;
298 int master_fd = -1;
299
300 if (drm_device) {
301 const char *path = drm_device->nodes[DRM_NODE_RENDER];
302 drmVersionPtr version;
303
304 fd = open(path, O_RDWR | O_CLOEXEC);
305 if (fd < 0) {
306 if (instance->debug_flags & RADV_DEBUG_STARTUP)
307 radv_logi("Could not open device '%s'", path);
308
309 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
310 }
311
312 version = drmGetVersion(fd);
313 if (!version) {
314 close(fd);
315
316 if (instance->debug_flags & RADV_DEBUG_STARTUP)
317 radv_logi("Could not get the kernel driver version for device '%s'", path);
318
319 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
320 "failed to get version %s: %m", path);
321 }
322
323 if (strcmp(version->name, "amdgpu")) {
324 drmFreeVersion(version);
325 close(fd);
326
327 if (instance->debug_flags & RADV_DEBUG_STARTUP)
328 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
329
330 return VK_ERROR_INCOMPATIBLE_DRIVER;
331 }
332 drmFreeVersion(version);
333
334 if (instance->debug_flags & RADV_DEBUG_STARTUP)
335 radv_logi("Found compatible device '%s'.", path);
336 }
337
338 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
339 device->instance = instance;
340
341 if (drm_device) {
342 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
343 instance->perftest_flags);
344 } else {
345 device->ws = radv_null_winsys_create();
346 }
347
348 if (!device->ws) {
349 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
350 goto fail;
351 }
352
353 if (instance->enabled_extensions.KHR_display) {
354 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
355 if (master_fd >= 0) {
356 uint32_t accel_working = 0;
357 struct drm_amdgpu_info request = {
358 .return_pointer = (uintptr_t)&accel_working,
359 .return_size = sizeof(accel_working),
360 .query = AMDGPU_INFO_ACCEL_WORKING
361 };
362
363 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
364 close(master_fd);
365 master_fd = -1;
366 }
367 }
368 }
369
370 device->master_fd = master_fd;
371 device->local_fd = fd;
372 device->ws->query_info(device->ws, &device->rad_info);
373
374 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
375
376 snprintf(device->name, sizeof(device->name),
377 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
378 device->rad_info.name);
379
380 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
381 device->ws->destroy(device->ws);
382 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
383 "cannot generate UUID");
384 goto fail;
385 }
386
387 /* These flags affect shader compilation. */
388 uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
389
390 /* The gpu id is already embedded in the uuid so we just pass "radv"
391 * when creating the cache.
392 */
393 char buf[VK_UUID_SIZE * 2 + 1];
394 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
395 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
396
397 if (device->rad_info.chip_class < GFX8)
398 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
399
400 radv_get_driver_uuid(&device->driver_uuid);
401 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
402
403 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
404 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
405
406 device->dcc_msaa_allowed =
407 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
408
409 device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
410 (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
411
412 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
413 device->rad_info.family != CHIP_NAVI14 &&
414 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
415 if (device->use_aco && device->use_ngg) {
416 fprintf(stderr, "WARNING: disabling NGG because ACO is used.\n");
417 device->use_ngg = false;
418 }
419
420 device->use_ngg_streamout = false;
421
422 /* Determine the number of threads per wave for all stages. */
423 device->cs_wave_size = 64;
424 device->ps_wave_size = 64;
425 device->ge_wave_size = 64;
426
427 if (device->rad_info.chip_class >= GFX10) {
428 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
429 device->cs_wave_size = 32;
430
431 /* For pixel shaders, wave64 is recommanded. */
432 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
433 device->ps_wave_size = 32;
434
435 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
436 device->ge_wave_size = 32;
437 }
438
439 radv_physical_device_init_mem_types(device);
440 radv_fill_device_extension_table(device, &device->supported_extensions);
441
442 if (drm_device)
443 device->bus_info = *drm_device->businfo.pci;
444
445 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
446 ac_print_gpu_info(&device->rad_info);
447
448 /* The WSI is structured as a layer on top of the driver, so this has
449 * to be the last part of initialization (at least until we get other
450 * semi-layers).
451 */
452 result = radv_init_wsi(device);
453 if (result != VK_SUCCESS) {
454 device->ws->destroy(device->ws);
455 vk_error(instance, result);
456 goto fail;
457 }
458
459 return VK_SUCCESS;
460
461 fail:
462 close(fd);
463 if (master_fd != -1)
464 close(master_fd);
465 return result;
466 }
467
468 static void
469 radv_physical_device_finish(struct radv_physical_device *device)
470 {
471 radv_finish_wsi(device);
472 device->ws->destroy(device->ws);
473 disk_cache_destroy(device->disk_cache);
474 close(device->local_fd);
475 if (device->master_fd != -1)
476 close(device->master_fd);
477 }
478
479 static void *
480 default_alloc_func(void *pUserData, size_t size, size_t align,
481 VkSystemAllocationScope allocationScope)
482 {
483 return malloc(size);
484 }
485
486 static void *
487 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
488 size_t align, VkSystemAllocationScope allocationScope)
489 {
490 return realloc(pOriginal, size);
491 }
492
493 static void
494 default_free_func(void *pUserData, void *pMemory)
495 {
496 free(pMemory);
497 }
498
499 static const VkAllocationCallbacks default_alloc = {
500 .pUserData = NULL,
501 .pfnAllocation = default_alloc_func,
502 .pfnReallocation = default_realloc_func,
503 .pfnFree = default_free_func,
504 };
505
506 static const struct debug_control radv_debug_options[] = {
507 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
508 {"nodcc", RADV_DEBUG_NO_DCC},
509 {"shaders", RADV_DEBUG_DUMP_SHADERS},
510 {"nocache", RADV_DEBUG_NO_CACHE},
511 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
512 {"nohiz", RADV_DEBUG_NO_HIZ},
513 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
514 {"allbos", RADV_DEBUG_ALL_BOS},
515 {"noibs", RADV_DEBUG_NO_IBS},
516 {"spirv", RADV_DEBUG_DUMP_SPIRV},
517 {"vmfaults", RADV_DEBUG_VM_FAULTS},
518 {"zerovram", RADV_DEBUG_ZERO_VRAM},
519 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
520 {"preoptir", RADV_DEBUG_PREOPTIR},
521 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
522 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
523 {"info", RADV_DEBUG_INFO},
524 {"errors", RADV_DEBUG_ERRORS},
525 {"startup", RADV_DEBUG_STARTUP},
526 {"checkir", RADV_DEBUG_CHECKIR},
527 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
528 {"nobinning", RADV_DEBUG_NOBINNING},
529 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
530 {"nongg", RADV_DEBUG_NO_NGG},
531 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
532 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
533 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
534 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
535 {NULL, 0}
536 };
537
538 const char *
539 radv_get_debug_option_name(int id)
540 {
541 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
542 return radv_debug_options[id].string;
543 }
544
545 static const struct debug_control radv_perftest_options[] = {
546 {"localbos", RADV_PERFTEST_LOCAL_BOS},
547 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
548 {"bolist", RADV_PERFTEST_BO_LIST},
549 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
550 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
551 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
552 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
553 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
554 {"dfsm", RADV_PERFTEST_DFSM},
555 {"aco", RADV_PERFTEST_ACO},
556 {NULL, 0}
557 };
558
559 const char *
560 radv_get_perftest_option_name(int id)
561 {
562 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
563 return radv_perftest_options[id].string;
564 }
565
566 static void
567 radv_handle_per_app_options(struct radv_instance *instance,
568 const VkApplicationInfo *info)
569 {
570 const char *name = info ? info->pApplicationName : NULL;
571
572 if (!name)
573 return;
574
575 if (!strcmp(name, "DOOM_VFR")) {
576 /* Work around a Doom VFR game bug */
577 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
578 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
579 /* Workaround for a WaW hazard when LLVM moves/merges
580 * load/store memory operations.
581 * See https://reviews.llvm.org/D61313
582 */
583 if (LLVM_VERSION_MAJOR < 9)
584 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
585 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
586 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT) &&
587 !(instance->perftest_flags & RADV_PERFTEST_ACO)) {
588 /* Force enable VK_AMD_shader_ballot because it looks
589 * safe and it gives a nice boost (+20% on Vega 56 at
590 * this time). It also prevents corruption on LLVM.
591 */
592 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
593 }
594 } else if (!strcmp(name, "Fledge")) {
595 /*
596 * Zero VRAM for "The Surge 2"
597 *
598 * This avoid a hang when when rendering any level. Likely
599 * uninitialized data in an indirect draw.
600 */
601 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
602 }
603 }
604
605 static int radv_get_instance_extension_index(const char *name)
606 {
607 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
608 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
609 return i;
610 }
611 return -1;
612 }
613
614 static const char radv_dri_options_xml[] =
615 DRI_CONF_BEGIN
616 DRI_CONF_SECTION_PERFORMANCE
617 DRI_CONF_ADAPTIVE_SYNC("true")
618 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
619 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
620 DRI_CONF_SECTION_END
621
622 DRI_CONF_SECTION_DEBUG
623 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
624 DRI_CONF_SECTION_END
625 DRI_CONF_END;
626
627 static void radv_init_dri_options(struct radv_instance *instance)
628 {
629 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
630 driParseConfigFiles(&instance->dri_options,
631 &instance->available_dri_options,
632 0, "radv", NULL,
633 instance->engineName,
634 instance->engineVersion);
635 }
636
637 VkResult radv_CreateInstance(
638 const VkInstanceCreateInfo* pCreateInfo,
639 const VkAllocationCallbacks* pAllocator,
640 VkInstance* pInstance)
641 {
642 struct radv_instance *instance;
643 VkResult result;
644
645 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
646
647 uint32_t client_version;
648 if (pCreateInfo->pApplicationInfo &&
649 pCreateInfo->pApplicationInfo->apiVersion != 0) {
650 client_version = pCreateInfo->pApplicationInfo->apiVersion;
651 } else {
652 client_version = VK_API_VERSION_1_0;
653 }
654
655 const char *engine_name = NULL;
656 uint32_t engine_version = 0;
657 if (pCreateInfo->pApplicationInfo) {
658 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
659 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
660 }
661
662 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 if (!instance)
665 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
666
667 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
668
669 if (pAllocator)
670 instance->alloc = *pAllocator;
671 else
672 instance->alloc = default_alloc;
673
674 instance->apiVersion = client_version;
675 instance->physicalDeviceCount = -1;
676
677 /* Get secure compile thread count. NOTE: We cap this at 32 */
678 #define MAX_SC_PROCS 32
679 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
680 if (num_sc_threads)
681 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
682
683 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
684 radv_debug_options);
685
686 /* Disable memory cache when secure compile is set */
687 if (radv_device_use_secure_compile(instance))
688 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
689
690 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
691 radv_perftest_options);
692
693 if (instance->perftest_flags & RADV_PERFTEST_ACO)
694 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
695
696 if (instance->debug_flags & RADV_DEBUG_STARTUP)
697 radv_logi("Created an instance");
698
699 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
700 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
701 int index = radv_get_instance_extension_index(ext_name);
702
703 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
704 vk_free2(&default_alloc, pAllocator, instance);
705 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
706 }
707
708 instance->enabled_extensions.extensions[index] = true;
709 }
710
711 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
712 if (result != VK_SUCCESS) {
713 vk_free2(&default_alloc, pAllocator, instance);
714 return vk_error(instance, result);
715 }
716
717 instance->engineName = vk_strdup(&instance->alloc, engine_name,
718 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
719 instance->engineVersion = engine_version;
720
721 glsl_type_singleton_init_or_ref();
722
723 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
724
725 radv_init_dri_options(instance);
726 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
727
728 *pInstance = radv_instance_to_handle(instance);
729
730 return VK_SUCCESS;
731 }
732
733 void radv_DestroyInstance(
734 VkInstance _instance,
735 const VkAllocationCallbacks* pAllocator)
736 {
737 RADV_FROM_HANDLE(radv_instance, instance, _instance);
738
739 if (!instance)
740 return;
741
742 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
743 radv_physical_device_finish(instance->physicalDevices + i);
744 }
745
746 vk_free(&instance->alloc, instance->engineName);
747
748 VG(VALGRIND_DESTROY_MEMPOOL(instance));
749
750 glsl_type_singleton_decref();
751
752 driDestroyOptionCache(&instance->dri_options);
753 driDestroyOptionInfo(&instance->available_dri_options);
754
755 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
756
757 vk_free(&instance->alloc, instance);
758 }
759
760 static VkResult
761 radv_enumerate_devices(struct radv_instance *instance)
762 {
763 /* TODO: Check for more devices ? */
764 drmDevicePtr devices[8];
765 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
766 int max_devices;
767
768 instance->physicalDeviceCount = 0;
769
770 if (getenv("RADV_FORCE_FAMILY")) {
771 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
772 * device that allows to test the compiler without having an
773 * AMDGPU instance.
774 */
775 result = radv_physical_device_init(instance->physicalDevices +
776 instance->physicalDeviceCount,
777 instance, NULL);
778
779 ++instance->physicalDeviceCount;
780 return VK_SUCCESS;
781 }
782
783 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
784
785 if (instance->debug_flags & RADV_DEBUG_STARTUP)
786 radv_logi("Found %d drm nodes", max_devices);
787
788 if (max_devices < 1)
789 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
790
791 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
792 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
793 devices[i]->bustype == DRM_BUS_PCI &&
794 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
795
796 result = radv_physical_device_init(instance->physicalDevices +
797 instance->physicalDeviceCount,
798 instance,
799 devices[i]);
800 if (result == VK_SUCCESS)
801 ++instance->physicalDeviceCount;
802 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
803 break;
804 }
805 }
806 drmFreeDevices(devices, max_devices);
807
808 return result;
809 }
810
811 VkResult radv_EnumeratePhysicalDevices(
812 VkInstance _instance,
813 uint32_t* pPhysicalDeviceCount,
814 VkPhysicalDevice* pPhysicalDevices)
815 {
816 RADV_FROM_HANDLE(radv_instance, instance, _instance);
817 VkResult result;
818
819 if (instance->physicalDeviceCount < 0) {
820 result = radv_enumerate_devices(instance);
821 if (result != VK_SUCCESS &&
822 result != VK_ERROR_INCOMPATIBLE_DRIVER)
823 return result;
824 }
825
826 if (!pPhysicalDevices) {
827 *pPhysicalDeviceCount = instance->physicalDeviceCount;
828 } else {
829 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
830 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
831 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
832 }
833
834 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
835 : VK_SUCCESS;
836 }
837
838 VkResult radv_EnumeratePhysicalDeviceGroups(
839 VkInstance _instance,
840 uint32_t* pPhysicalDeviceGroupCount,
841 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
842 {
843 RADV_FROM_HANDLE(radv_instance, instance, _instance);
844 VkResult result;
845
846 if (instance->physicalDeviceCount < 0) {
847 result = radv_enumerate_devices(instance);
848 if (result != VK_SUCCESS &&
849 result != VK_ERROR_INCOMPATIBLE_DRIVER)
850 return result;
851 }
852
853 if (!pPhysicalDeviceGroupProperties) {
854 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
855 } else {
856 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
857 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
858 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
859 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
860 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
861 }
862 }
863 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
864 : VK_SUCCESS;
865 }
866
867 void radv_GetPhysicalDeviceFeatures(
868 VkPhysicalDevice physicalDevice,
869 VkPhysicalDeviceFeatures* pFeatures)
870 {
871 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
872 memset(pFeatures, 0, sizeof(*pFeatures));
873
874 *pFeatures = (VkPhysicalDeviceFeatures) {
875 .robustBufferAccess = true,
876 .fullDrawIndexUint32 = true,
877 .imageCubeArray = true,
878 .independentBlend = true,
879 .geometryShader = true,
880 .tessellationShader = true,
881 .sampleRateShading = true,
882 .dualSrcBlend = true,
883 .logicOp = true,
884 .multiDrawIndirect = true,
885 .drawIndirectFirstInstance = true,
886 .depthClamp = true,
887 .depthBiasClamp = true,
888 .fillModeNonSolid = true,
889 .depthBounds = true,
890 .wideLines = true,
891 .largePoints = true,
892 .alphaToOne = true,
893 .multiViewport = true,
894 .samplerAnisotropy = true,
895 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
896 .textureCompressionASTC_LDR = false,
897 .textureCompressionBC = true,
898 .occlusionQueryPrecise = true,
899 .pipelineStatisticsQuery = true,
900 .vertexPipelineStoresAndAtomics = true,
901 .fragmentStoresAndAtomics = true,
902 .shaderTessellationAndGeometryPointSize = true,
903 .shaderImageGatherExtended = true,
904 .shaderStorageImageExtendedFormats = true,
905 .shaderStorageImageMultisample = true,
906 .shaderUniformBufferArrayDynamicIndexing = true,
907 .shaderSampledImageArrayDynamicIndexing = true,
908 .shaderStorageBufferArrayDynamicIndexing = true,
909 .shaderStorageImageArrayDynamicIndexing = true,
910 .shaderStorageImageReadWithoutFormat = true,
911 .shaderStorageImageWriteWithoutFormat = true,
912 .shaderClipDistance = true,
913 .shaderCullDistance = true,
914 .shaderFloat64 = true,
915 .shaderInt64 = true,
916 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
917 .sparseBinding = true,
918 .variableMultisampleRate = true,
919 .inheritedQueries = true,
920 };
921 }
922
923 void radv_GetPhysicalDeviceFeatures2(
924 VkPhysicalDevice physicalDevice,
925 VkPhysicalDeviceFeatures2 *pFeatures)
926 {
927 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
928 vk_foreach_struct(ext, pFeatures->pNext) {
929 switch (ext->sType) {
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
931 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
932 features->variablePointersStorageBuffer = true;
933 features->variablePointers = true;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
937 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
938 features->multiview = true;
939 features->multiviewGeometryShader = true;
940 features->multiviewTessellationShader = true;
941 break;
942 }
943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
944 VkPhysicalDeviceShaderDrawParametersFeatures *features =
945 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
946 features->shaderDrawParameters = true;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
950 VkPhysicalDeviceProtectedMemoryFeatures *features =
951 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
952 features->protectedMemory = false;
953 break;
954 }
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
956 VkPhysicalDevice16BitStorageFeatures *features =
957 (VkPhysicalDevice16BitStorageFeatures*)ext;
958 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
959 features->storageBuffer16BitAccess = enabled;
960 features->uniformAndStorageBuffer16BitAccess = enabled;
961 features->storagePushConstant16 = enabled;
962 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
963 break;
964 }
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
966 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
967 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
968 features->samplerYcbcrConversion = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
972 VkPhysicalDeviceDescriptorIndexingFeatures *features =
973 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
974 features->shaderInputAttachmentArrayDynamicIndexing = true;
975 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
976 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
977 features->shaderUniformBufferArrayNonUniformIndexing = true;
978 features->shaderSampledImageArrayNonUniformIndexing = true;
979 features->shaderStorageBufferArrayNonUniformIndexing = true;
980 features->shaderStorageImageArrayNonUniformIndexing = true;
981 features->shaderInputAttachmentArrayNonUniformIndexing = true;
982 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
983 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
984 features->descriptorBindingUniformBufferUpdateAfterBind = true;
985 features->descriptorBindingSampledImageUpdateAfterBind = true;
986 features->descriptorBindingStorageImageUpdateAfterBind = true;
987 features->descriptorBindingStorageBufferUpdateAfterBind = true;
988 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
989 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
990 features->descriptorBindingUpdateUnusedWhilePending = true;
991 features->descriptorBindingPartiallyBound = true;
992 features->descriptorBindingVariableDescriptorCount = true;
993 features->runtimeDescriptorArray = true;
994 break;
995 }
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
997 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
998 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
999 features->conditionalRendering = true;
1000 features->inheritedConditionalRendering = false;
1001 break;
1002 }
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1004 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1005 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1006 features->vertexAttributeInstanceRateDivisor = true;
1007 features->vertexAttributeInstanceRateZeroDivisor = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1011 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1012 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1013 features->transformFeedback = true;
1014 features->geometryStreams = !pdevice->use_ngg_streamout;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1018 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1019 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1020 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1021 break;
1022 }
1023 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1024 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1025 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1026 features->memoryPriority = true;
1027 break;
1028 }
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1030 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1031 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1032 features->bufferDeviceAddress = true;
1033 features->bufferDeviceAddressCaptureReplay = false;
1034 features->bufferDeviceAddressMultiDevice = false;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1038 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1039 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1040 features->bufferDeviceAddress = true;
1041 features->bufferDeviceAddressCaptureReplay = false;
1042 features->bufferDeviceAddressMultiDevice = false;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1046 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1047 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1048 features->depthClipEnable = true;
1049 break;
1050 }
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1052 VkPhysicalDeviceHostQueryResetFeatures *features =
1053 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1054 features->hostQueryReset = true;
1055 break;
1056 }
1057 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1058 VkPhysicalDevice8BitStorageFeatures *features =
1059 (VkPhysicalDevice8BitStorageFeatures *)ext;
1060 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1061 features->storageBuffer8BitAccess = enabled;
1062 features->uniformAndStorageBuffer8BitAccess = enabled;
1063 features->storagePushConstant8 = enabled;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1067 VkPhysicalDeviceShaderFloat16Int8Features *features =
1068 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1069 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1070 features->shaderInt8 = !pdevice->use_aco;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1074 VkPhysicalDeviceShaderAtomicInt64Features *features =
1075 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1076 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1077 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1078 break;
1079 }
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1081 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1082 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1083 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1084 break;
1085 }
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1087 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1088 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1089
1090 features->inlineUniformBlock = true;
1091 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1092 break;
1093 }
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1095 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1096 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1097 features->computeDerivativeGroupQuads = false;
1098 features->computeDerivativeGroupLinear = true;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1102 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1103 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1104 features->ycbcrImageArrays = true;
1105 break;
1106 }
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1108 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1109 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1110 features->uniformBufferStandardLayout = true;
1111 break;
1112 }
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1114 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1115 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1116 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1117 break;
1118 }
1119 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1120 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1121 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1122 features->imagelessFramebuffer = true;
1123 break;
1124 }
1125 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1126 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1127 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1128 features->pipelineExecutableInfo = true;
1129 break;
1130 }
1131 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1132 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1133 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1134 features->shaderSubgroupClock = true;
1135 features->shaderDeviceClock = false;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1139 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1140 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1141 features->texelBufferAlignment = true;
1142 break;
1143 }
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1145 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1146 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1147 features->timelineSemaphore = true;
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1151 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1152 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1153 features->subgroupSizeControl = true;
1154 features->computeFullSubgroups = true;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1158 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1159 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1160 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1164 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1165 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1166 features->shaderSubgroupExtendedTypes = true;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1170 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1171 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1172 features->separateDepthStencilLayouts = true;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1176 VkPhysicalDeviceVulkan11Features *features =
1177 (VkPhysicalDeviceVulkan11Features *)ext;
1178 features->storageBuffer16BitAccess = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1179 features->uniformAndStorageBuffer16BitAccess = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1180 features->storagePushConstant16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1181 features->storageInputOutput16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
1182 features->multiview = true;
1183 features->multiviewGeometryShader = true;
1184 features->multiviewTessellationShader = true;
1185 features->variablePointersStorageBuffer = true;
1186 features->variablePointers = true;
1187 features->protectedMemory = false;
1188 features->samplerYcbcrConversion = true;
1189 features->shaderDrawParameters = true;
1190 break;
1191 }
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1193 VkPhysicalDeviceVulkan12Features *features =
1194 (VkPhysicalDeviceVulkan12Features *)ext;
1195 features->samplerMirrorClampToEdge = true;
1196 features->drawIndirectCount = true;
1197 features->storageBuffer8BitAccess = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1198 features->uniformAndStorageBuffer8BitAccess = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1199 features->storagePushConstant8 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1200 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1201 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1202 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1203 features->shaderInt8 = !pdevice->use_aco;
1204 features->descriptorIndexing = true;
1205 features->shaderInputAttachmentArrayDynamicIndexing = true;
1206 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1207 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1208 features->shaderUniformBufferArrayNonUniformIndexing = true;
1209 features->shaderSampledImageArrayNonUniformIndexing = true;
1210 features->shaderStorageBufferArrayNonUniformIndexing = true;
1211 features->shaderStorageImageArrayNonUniformIndexing = true;
1212 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1213 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1214 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1215 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1216 features->descriptorBindingSampledImageUpdateAfterBind = true;
1217 features->descriptorBindingStorageImageUpdateAfterBind = true;
1218 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1219 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1220 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1221 features->descriptorBindingUpdateUnusedWhilePending = true;
1222 features->descriptorBindingPartiallyBound = true;
1223 features->descriptorBindingVariableDescriptorCount = true;
1224 features->runtimeDescriptorArray = true;
1225 features->samplerFilterMinmax = true;
1226 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1227 features->imagelessFramebuffer = true;
1228 features->uniformBufferStandardLayout = true;
1229 features->shaderSubgroupExtendedTypes = true;
1230 features->separateDepthStencilLayouts = true;
1231 features->hostQueryReset = true;
1232 features->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1233 features->bufferDeviceAddress = true;
1234 features->bufferDeviceAddressCaptureReplay = false;
1235 features->bufferDeviceAddressMultiDevice = false;
1236 features->vulkanMemoryModel = false;
1237 features->vulkanMemoryModelDeviceScope = false;
1238 features->vulkanMemoryModelAvailabilityVisibilityChains = false;
1239 features->shaderOutputViewportIndex = true;
1240 features->shaderOutputLayer = true;
1241 features->subgroupBroadcastDynamicId = true;
1242 break;
1243 }
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1245 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1246 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1247 features->rectangularLines = false;
1248 features->bresenhamLines = true;
1249 features->smoothLines = false;
1250 features->stippledRectangularLines = false;
1251 features->stippledBresenhamLines = true;
1252 features->stippledSmoothLines = false;
1253 break;
1254 }
1255 default:
1256 break;
1257 }
1258 }
1259 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1260 }
1261
1262 static size_t
1263 radv_max_descriptor_set_size()
1264 {
1265 /* make sure that the entire descriptor set is addressable with a signed
1266 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1267 * be at most 2 GiB. the combined image & samples object count as one of
1268 * both. This limit is for the pipeline layout, not for the set layout, but
1269 * there is no set limit, so we just set a pipeline limit. I don't think
1270 * any app is going to hit this soon. */
1271 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1272 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1273 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1274 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1275 32 /* sampler, largest when combined with image */ +
1276 64 /* sampled image */ +
1277 64 /* storage image */);
1278 }
1279
1280 void radv_GetPhysicalDeviceProperties(
1281 VkPhysicalDevice physicalDevice,
1282 VkPhysicalDeviceProperties* pProperties)
1283 {
1284 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1285 VkSampleCountFlags sample_counts = 0xf;
1286
1287 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1288
1289 VkPhysicalDeviceLimits limits = {
1290 .maxImageDimension1D = (1 << 14),
1291 .maxImageDimension2D = (1 << 14),
1292 .maxImageDimension3D = (1 << 11),
1293 .maxImageDimensionCube = (1 << 14),
1294 .maxImageArrayLayers = (1 << 11),
1295 .maxTexelBufferElements = 128 * 1024 * 1024,
1296 .maxUniformBufferRange = UINT32_MAX,
1297 .maxStorageBufferRange = UINT32_MAX,
1298 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1299 .maxMemoryAllocationCount = UINT32_MAX,
1300 .maxSamplerAllocationCount = 64 * 1024,
1301 .bufferImageGranularity = 64, /* A cache line */
1302 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1303 .maxBoundDescriptorSets = MAX_SETS,
1304 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1305 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1306 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1307 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1308 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1309 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1310 .maxPerStageResources = max_descriptor_set_size,
1311 .maxDescriptorSetSamplers = max_descriptor_set_size,
1312 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1313 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1314 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1315 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1316 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1317 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1318 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1319 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1320 .maxVertexInputBindings = MAX_VBS,
1321 .maxVertexInputAttributeOffset = 2047,
1322 .maxVertexInputBindingStride = 2048,
1323 .maxVertexOutputComponents = 128,
1324 .maxTessellationGenerationLevel = 64,
1325 .maxTessellationPatchSize = 32,
1326 .maxTessellationControlPerVertexInputComponents = 128,
1327 .maxTessellationControlPerVertexOutputComponents = 128,
1328 .maxTessellationControlPerPatchOutputComponents = 120,
1329 .maxTessellationControlTotalOutputComponents = 4096,
1330 .maxTessellationEvaluationInputComponents = 128,
1331 .maxTessellationEvaluationOutputComponents = 128,
1332 .maxGeometryShaderInvocations = 127,
1333 .maxGeometryInputComponents = 64,
1334 .maxGeometryOutputComponents = 128,
1335 .maxGeometryOutputVertices = 256,
1336 .maxGeometryTotalOutputComponents = 1024,
1337 .maxFragmentInputComponents = 128,
1338 .maxFragmentOutputAttachments = 8,
1339 .maxFragmentDualSrcAttachments = 1,
1340 .maxFragmentCombinedOutputResources = 8,
1341 .maxComputeSharedMemorySize = 32768,
1342 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1343 .maxComputeWorkGroupInvocations = 1024,
1344 .maxComputeWorkGroupSize = {
1345 1024,
1346 1024,
1347 1024
1348 },
1349 .subPixelPrecisionBits = 8,
1350 .subTexelPrecisionBits = 8,
1351 .mipmapPrecisionBits = 8,
1352 .maxDrawIndexedIndexValue = UINT32_MAX,
1353 .maxDrawIndirectCount = UINT32_MAX,
1354 .maxSamplerLodBias = 16,
1355 .maxSamplerAnisotropy = 16,
1356 .maxViewports = MAX_VIEWPORTS,
1357 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1358 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1359 .viewportSubPixelBits = 8,
1360 .minMemoryMapAlignment = 4096, /* A page */
1361 .minTexelBufferOffsetAlignment = 4,
1362 .minUniformBufferOffsetAlignment = 4,
1363 .minStorageBufferOffsetAlignment = 4,
1364 .minTexelOffset = -32,
1365 .maxTexelOffset = 31,
1366 .minTexelGatherOffset = -32,
1367 .maxTexelGatherOffset = 31,
1368 .minInterpolationOffset = -2,
1369 .maxInterpolationOffset = 2,
1370 .subPixelInterpolationOffsetBits = 8,
1371 .maxFramebufferWidth = (1 << 14),
1372 .maxFramebufferHeight = (1 << 14),
1373 .maxFramebufferLayers = (1 << 10),
1374 .framebufferColorSampleCounts = sample_counts,
1375 .framebufferDepthSampleCounts = sample_counts,
1376 .framebufferStencilSampleCounts = sample_counts,
1377 .framebufferNoAttachmentsSampleCounts = sample_counts,
1378 .maxColorAttachments = MAX_RTS,
1379 .sampledImageColorSampleCounts = sample_counts,
1380 .sampledImageIntegerSampleCounts = sample_counts,
1381 .sampledImageDepthSampleCounts = sample_counts,
1382 .sampledImageStencilSampleCounts = sample_counts,
1383 .storageImageSampleCounts = sample_counts,
1384 .maxSampleMaskWords = 1,
1385 .timestampComputeAndGraphics = true,
1386 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1387 .maxClipDistances = 8,
1388 .maxCullDistances = 8,
1389 .maxCombinedClipAndCullDistances = 8,
1390 .discreteQueuePriorities = 2,
1391 .pointSizeRange = { 0.0, 8192.0 },
1392 .lineWidthRange = { 0.0, 8192.0 },
1393 .pointSizeGranularity = (1.0 / 8.0),
1394 .lineWidthGranularity = (1.0 / 8.0),
1395 .strictLines = false, /* FINISHME */
1396 .standardSampleLocations = true,
1397 .optimalBufferCopyOffsetAlignment = 128,
1398 .optimalBufferCopyRowPitchAlignment = 128,
1399 .nonCoherentAtomSize = 64,
1400 };
1401
1402 *pProperties = (VkPhysicalDeviceProperties) {
1403 .apiVersion = radv_physical_device_api_version(pdevice),
1404 .driverVersion = vk_get_driver_version(),
1405 .vendorID = ATI_VENDOR_ID,
1406 .deviceID = pdevice->rad_info.pci_id,
1407 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1408 .limits = limits,
1409 .sparseProperties = {0},
1410 };
1411
1412 strcpy(pProperties->deviceName, pdevice->name);
1413 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1414 }
1415
1416 static void
1417 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1418 VkPhysicalDeviceVulkan11Properties *p)
1419 {
1420 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1421
1422 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1423 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1424 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1425 /* The LUID is for Windows. */
1426 p->deviceLUIDValid = false;
1427 p->deviceNodeMask = 0;
1428
1429 p->subgroupSize = RADV_SUBGROUP_SIZE;
1430 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL;
1431 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1432 VK_SUBGROUP_FEATURE_VOTE_BIT |
1433 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1434 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1435 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1436 VK_SUBGROUP_FEATURE_QUAD_BIT;
1437
1438 if (pdevice->rad_info.chip_class == GFX8 ||
1439 pdevice->rad_info.chip_class == GFX9) {
1440 p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1441 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1442 }
1443 p->subgroupQuadOperationsInAllStages = true;
1444
1445 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1446 p->maxMultiviewViewCount = MAX_VIEWS;
1447 p->maxMultiviewInstanceIndex = INT_MAX;
1448 p->protectedNoFault = false;
1449 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1450 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1451 }
1452
1453 static void
1454 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1455 VkPhysicalDeviceVulkan12Properties *p)
1456 {
1457 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1458
1459 p->driverID = VK_DRIVER_ID_MESA_RADV;
1460 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1461 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1462 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1463 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1464 p->conformanceVersion = (VkConformanceVersion) {
1465 .major = 1,
1466 .minor = 2,
1467 .subminor = 0,
1468 .patch = 0,
1469 };
1470
1471 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1472 * controlled by the same config register.
1473 */
1474 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1475 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1476
1477 /* Do not allow both preserving and flushing denorms because different
1478 * shaders in the same pipeline can have different settings and this
1479 * won't work for merged shaders. To make it work, this requires LLVM
1480 * support for changing the register. The same logic applies for the
1481 * rounding modes because they are configured with the same config
1482 * register. TODO: we can enable a lot of these for ACO when it
1483 * supports all stages.
1484 */
1485 p->shaderDenormFlushToZeroFloat32 = true;
1486 p->shaderDenormPreserveFloat32 = false;
1487 p->shaderRoundingModeRTEFloat32 = true;
1488 p->shaderRoundingModeRTZFloat32 = false;
1489 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1490
1491 p->shaderDenormFlushToZeroFloat16 = false;
1492 p->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1493 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
1494 p->shaderRoundingModeRTZFloat16 = false;
1495 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1496
1497 p->shaderDenormFlushToZeroFloat64 = false;
1498 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1499 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1500 p->shaderRoundingModeRTZFloat64 = false;
1501 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1502
1503 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1504 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1505 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1506 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1507 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1508 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1509 p->robustBufferAccessUpdateAfterBind = false;
1510 p->quadDivergentImplicitLod = false;
1511
1512 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1513 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1514 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1515 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1516 32 /* sampler, largest when combined with image */ +
1517 64 /* sampled image */ +
1518 64 /* storage image */);
1519 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1520 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1521 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1522 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1523 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1524 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1525 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1526 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1527 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1528 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1529 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1530 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1531 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1532 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1533 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1534
1535 /* We support all of the depth resolve modes */
1536 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1537 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1538 VK_RESOLVE_MODE_MIN_BIT_KHR |
1539 VK_RESOLVE_MODE_MAX_BIT_KHR;
1540
1541 /* Average doesn't make sense for stencil so we don't support that */
1542 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1543 VK_RESOLVE_MODE_MIN_BIT_KHR |
1544 VK_RESOLVE_MODE_MAX_BIT_KHR;
1545
1546 p->independentResolveNone = true;
1547 p->independentResolve = true;
1548
1549 /* GFX6-8 only support single channel min/max filter. */
1550 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1551 p->filterMinmaxSingleComponentFormats = true;
1552
1553 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1554
1555 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1556 }
1557
1558 void radv_GetPhysicalDeviceProperties2(
1559 VkPhysicalDevice physicalDevice,
1560 VkPhysicalDeviceProperties2 *pProperties)
1561 {
1562 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1563 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1564
1565 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1566 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1567 };
1568 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1569
1570 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1571 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1572 };
1573 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1574
1575 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1576 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1577 sizeof(core_##major##_##minor.core_property))
1578
1579 #define CORE_PROPERTY(major, minor, property) \
1580 CORE_RENAMED_PROPERTY(major, minor, property, property)
1581
1582 vk_foreach_struct(ext, pProperties->pNext) {
1583 switch (ext->sType) {
1584 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1585 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1586 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1587 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1588 break;
1589 }
1590 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1591 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1592 CORE_PROPERTY(1, 1, deviceUUID);
1593 CORE_PROPERTY(1, 1, driverUUID);
1594 CORE_PROPERTY(1, 1, deviceLUID);
1595 CORE_PROPERTY(1, 1, deviceLUIDValid);
1596 break;
1597 }
1598 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1599 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1600 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1601 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1602 break;
1603 }
1604 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1605 VkPhysicalDevicePointClippingProperties *properties =
1606 (VkPhysicalDevicePointClippingProperties*)ext;
1607 CORE_PROPERTY(1, 1, pointClippingBehavior);
1608 break;
1609 }
1610 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1611 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1612 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1613 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1614 break;
1615 }
1616 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1617 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1618 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1619 properties->minImportedHostPointerAlignment = 4096;
1620 break;
1621 }
1622 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1623 VkPhysicalDeviceSubgroupProperties *properties =
1624 (VkPhysicalDeviceSubgroupProperties*)ext;
1625 CORE_PROPERTY(1, 1, subgroupSize);
1626 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1627 subgroupSupportedStages);
1628 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1629 subgroupSupportedOperations);
1630 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1631 subgroupQuadOperationsInAllStages);
1632 break;
1633 }
1634 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1635 VkPhysicalDeviceMaintenance3Properties *properties =
1636 (VkPhysicalDeviceMaintenance3Properties*)ext;
1637 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1638 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1639 break;
1640 }
1641 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1642 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1643 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1644 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1645 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1646 break;
1647 }
1648 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1649 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1650 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1651
1652 /* Shader engines. */
1653 properties->shaderEngineCount =
1654 pdevice->rad_info.max_se;
1655 properties->shaderArraysPerEngineCount =
1656 pdevice->rad_info.max_sh_per_se;
1657 properties->computeUnitsPerShaderArray =
1658 pdevice->rad_info.num_good_cu_per_sh;
1659 properties->simdPerComputeUnit =
1660 pdevice->rad_info.num_simd_per_compute_unit;
1661 properties->wavefrontsPerSimd =
1662 pdevice->rad_info.family == CHIP_TONGA ||
1663 pdevice->rad_info.family == CHIP_ICELAND ||
1664 pdevice->rad_info.family == CHIP_POLARIS10 ||
1665 pdevice->rad_info.family == CHIP_POLARIS11 ||
1666 pdevice->rad_info.family == CHIP_POLARIS12 ||
1667 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1668 properties->wavefrontSize = 64;
1669
1670 /* SGPR. */
1671 properties->sgprsPerSimd =
1672 pdevice->rad_info.num_physical_sgprs_per_simd;
1673 properties->minSgprAllocation =
1674 pdevice->rad_info.min_sgpr_alloc;
1675 properties->maxSgprAllocation =
1676 pdevice->rad_info.max_sgpr_alloc;
1677 properties->sgprAllocationGranularity =
1678 pdevice->rad_info.sgpr_alloc_granularity;
1679
1680 /* VGPR. */
1681 properties->vgprsPerSimd =
1682 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1683 properties->minVgprAllocation =
1684 pdevice->rad_info.min_vgpr_alloc;
1685 properties->maxVgprAllocation =
1686 pdevice->rad_info.max_vgpr_alloc;
1687 properties->vgprAllocationGranularity =
1688 pdevice->rad_info.vgpr_alloc_granularity;
1689 break;
1690 }
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1692 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1693 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1694
1695 properties->shaderCoreFeatures = 0;
1696 properties->activeComputeUnitCount =
1697 pdevice->rad_info.num_good_compute_units;
1698 break;
1699 }
1700 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1701 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1702 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1703 properties->maxVertexAttribDivisor = UINT32_MAX;
1704 break;
1705 }
1706 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1707 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1708 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1709 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1710 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1711 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1712 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1713 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1714 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1715 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1716 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1717 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1718 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1719 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1720 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1721 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1722 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1723 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1724 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1725 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1726 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1727 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1728 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1729 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1730 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1731 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1732 break;
1733 }
1734 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1735 VkPhysicalDeviceProtectedMemoryProperties *properties =
1736 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1737 CORE_PROPERTY(1, 1, protectedNoFault);
1738 break;
1739 }
1740 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1741 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1742 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1743 properties->primitiveOverestimationSize = 0;
1744 properties->maxExtraPrimitiveOverestimationSize = 0;
1745 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1746 properties->primitiveUnderestimation = false;
1747 properties->conservativePointAndLineRasterization = false;
1748 properties->degenerateTrianglesRasterized = false;
1749 properties->degenerateLinesRasterized = false;
1750 properties->fullyCoveredFragmentShaderInputVariable = false;
1751 properties->conservativeRasterizationPostDepthCoverage = false;
1752 break;
1753 }
1754 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1755 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1756 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1757 properties->pciDomain = pdevice->bus_info.domain;
1758 properties->pciBus = pdevice->bus_info.bus;
1759 properties->pciDevice = pdevice->bus_info.dev;
1760 properties->pciFunction = pdevice->bus_info.func;
1761 break;
1762 }
1763 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1764 VkPhysicalDeviceDriverProperties *properties =
1765 (VkPhysicalDeviceDriverProperties *) ext;
1766 CORE_PROPERTY(1, 2, driverID);
1767 CORE_PROPERTY(1, 2, driverName);
1768 CORE_PROPERTY(1, 2, driverInfo);
1769 CORE_PROPERTY(1, 2, conformanceVersion);
1770 break;
1771 }
1772 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1773 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1774 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1775 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1776 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1777 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1778 properties->maxTransformFeedbackStreamDataSize = 512;
1779 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1780 properties->maxTransformFeedbackBufferDataStride = 512;
1781 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1782 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1783 properties->transformFeedbackRasterizationStreamSelect = false;
1784 properties->transformFeedbackDraw = true;
1785 break;
1786 }
1787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1788 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1789 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1790
1791 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1792 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1793 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1794 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1795 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1796 break;
1797 }
1798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1799 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1800 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1801 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1802 VK_SAMPLE_COUNT_4_BIT |
1803 VK_SAMPLE_COUNT_8_BIT;
1804 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1805 properties->sampleLocationCoordinateRange[0] = 0.0f;
1806 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1807 properties->sampleLocationSubPixelBits = 4;
1808 properties->variableSampleLocations = false;
1809 break;
1810 }
1811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1812 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1813 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1814 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1815 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1816 CORE_PROPERTY(1, 2, independentResolveNone);
1817 CORE_PROPERTY(1, 2, independentResolve);
1818 break;
1819 }
1820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1821 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1822 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1823 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1824 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1825 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1826 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1827 break;
1828 }
1829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1830 VkPhysicalDeviceFloatControlsProperties *properties =
1831 (VkPhysicalDeviceFloatControlsProperties *)ext;
1832 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1833 CORE_PROPERTY(1, 2, roundingModeIndependence);
1834 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1835 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1836 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1837 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1838 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1839 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1840 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1841 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1842 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1843 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1844 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1845 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1846 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1847 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1848 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1849 break;
1850 }
1851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1852 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1853 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1854 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1855 break;
1856 }
1857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1858 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1859 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1860 props->minSubgroupSize = 64;
1861 props->maxSubgroupSize = 64;
1862 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1863 props->requiredSubgroupSizeStages = 0;
1864
1865 if (pdevice->rad_info.chip_class >= GFX10) {
1866 /* Only GFX10+ supports wave32. */
1867 props->minSubgroupSize = 32;
1868 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1869 }
1870 break;
1871 }
1872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1873 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1874 break;
1875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1876 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1877 break;
1878 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1879 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1880 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1881 props->lineSubPixelPrecisionBits = 4;
1882 break;
1883 }
1884 default:
1885 break;
1886 }
1887 }
1888 }
1889
1890 static void radv_get_physical_device_queue_family_properties(
1891 struct radv_physical_device* pdevice,
1892 uint32_t* pCount,
1893 VkQueueFamilyProperties** pQueueFamilyProperties)
1894 {
1895 int num_queue_families = 1;
1896 int idx;
1897 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1898 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1899 num_queue_families++;
1900
1901 if (pQueueFamilyProperties == NULL) {
1902 *pCount = num_queue_families;
1903 return;
1904 }
1905
1906 if (!*pCount)
1907 return;
1908
1909 idx = 0;
1910 if (*pCount >= 1) {
1911 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1912 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1913 VK_QUEUE_COMPUTE_BIT |
1914 VK_QUEUE_TRANSFER_BIT |
1915 VK_QUEUE_SPARSE_BINDING_BIT,
1916 .queueCount = 1,
1917 .timestampValidBits = 64,
1918 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1919 };
1920 idx++;
1921 }
1922
1923 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1924 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1925 if (*pCount > idx) {
1926 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1927 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1928 VK_QUEUE_TRANSFER_BIT |
1929 VK_QUEUE_SPARSE_BINDING_BIT,
1930 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1931 .timestampValidBits = 64,
1932 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1933 };
1934 idx++;
1935 }
1936 }
1937 *pCount = idx;
1938 }
1939
1940 void radv_GetPhysicalDeviceQueueFamilyProperties(
1941 VkPhysicalDevice physicalDevice,
1942 uint32_t* pCount,
1943 VkQueueFamilyProperties* pQueueFamilyProperties)
1944 {
1945 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1946 if (!pQueueFamilyProperties) {
1947 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1948 return;
1949 }
1950 VkQueueFamilyProperties *properties[] = {
1951 pQueueFamilyProperties + 0,
1952 pQueueFamilyProperties + 1,
1953 pQueueFamilyProperties + 2,
1954 };
1955 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1956 assert(*pCount <= 3);
1957 }
1958
1959 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1960 VkPhysicalDevice physicalDevice,
1961 uint32_t* pCount,
1962 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1963 {
1964 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1965 if (!pQueueFamilyProperties) {
1966 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1967 return;
1968 }
1969 VkQueueFamilyProperties *properties[] = {
1970 &pQueueFamilyProperties[0].queueFamilyProperties,
1971 &pQueueFamilyProperties[1].queueFamilyProperties,
1972 &pQueueFamilyProperties[2].queueFamilyProperties,
1973 };
1974 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1975 assert(*pCount <= 3);
1976 }
1977
1978 void radv_GetPhysicalDeviceMemoryProperties(
1979 VkPhysicalDevice physicalDevice,
1980 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1981 {
1982 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1983
1984 *pMemoryProperties = physical_device->memory_properties;
1985 }
1986
1987 static void
1988 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1989 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1990 {
1991 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1992 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1993 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1994 uint64_t vram_size = radv_get_vram_size(device);
1995 uint64_t gtt_size = device->rad_info.gart_size;
1996 uint64_t heap_budget, heap_usage;
1997
1998 /* For all memory heaps, the computation of budget is as follow:
1999 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2000 *
2001 * The Vulkan spec 1.1.97 says that the budget should include any
2002 * currently allocated device memory.
2003 *
2004 * Note that the application heap usages are not really accurate (eg.
2005 * in presence of shared buffers).
2006 */
2007 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2008 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2009
2010 if (radv_is_mem_type_vram(device->mem_type_indices[i])) {
2011 heap_usage = device->ws->query_value(device->ws,
2012 RADEON_ALLOCATED_VRAM);
2013
2014 heap_budget = vram_size -
2015 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2016 heap_usage;
2017
2018 memoryBudget->heapBudget[heap_index] = heap_budget;
2019 memoryBudget->heapUsage[heap_index] = heap_usage;
2020 } else if (radv_is_mem_type_vram_visible(device->mem_type_indices[i])) {
2021 heap_usage = device->ws->query_value(device->ws,
2022 RADEON_ALLOCATED_VRAM_VIS);
2023
2024 heap_budget = visible_vram_size -
2025 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2026 heap_usage;
2027
2028 memoryBudget->heapBudget[heap_index] = heap_budget;
2029 memoryBudget->heapUsage[heap_index] = heap_usage;
2030 } else if (radv_is_mem_type_gtt_wc(device->mem_type_indices[i])) {
2031 heap_usage = device->ws->query_value(device->ws,
2032 RADEON_ALLOCATED_GTT);
2033
2034 heap_budget = gtt_size -
2035 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2036 heap_usage;
2037
2038 memoryBudget->heapBudget[heap_index] = heap_budget;
2039 memoryBudget->heapUsage[heap_index] = heap_usage;
2040 }
2041 }
2042
2043 /* The heapBudget and heapUsage values must be zero for array elements
2044 * greater than or equal to
2045 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2046 */
2047 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2048 memoryBudget->heapBudget[i] = 0;
2049 memoryBudget->heapUsage[i] = 0;
2050 }
2051 }
2052
2053 void radv_GetPhysicalDeviceMemoryProperties2(
2054 VkPhysicalDevice physicalDevice,
2055 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2056 {
2057 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2058 &pMemoryProperties->memoryProperties);
2059
2060 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2061 vk_find_struct(pMemoryProperties->pNext,
2062 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2063 if (memory_budget)
2064 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2065 }
2066
2067 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2068 VkDevice _device,
2069 VkExternalMemoryHandleTypeFlagBits handleType,
2070 const void *pHostPointer,
2071 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2072 {
2073 RADV_FROM_HANDLE(radv_device, device, _device);
2074
2075 switch (handleType)
2076 {
2077 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2078 const struct radv_physical_device *physical_device = device->physical_device;
2079 uint32_t memoryTypeBits = 0;
2080 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2081 if (radv_is_mem_type_gtt_cached(physical_device->mem_type_indices[i])) {
2082 memoryTypeBits = (1 << i);
2083 break;
2084 }
2085 }
2086 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2087 return VK_SUCCESS;
2088 }
2089 default:
2090 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2091 }
2092 }
2093
2094 static enum radeon_ctx_priority
2095 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2096 {
2097 /* Default to MEDIUM when a specific global priority isn't requested */
2098 if (!pObj)
2099 return RADEON_CTX_PRIORITY_MEDIUM;
2100
2101 switch(pObj->globalPriority) {
2102 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2103 return RADEON_CTX_PRIORITY_REALTIME;
2104 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2105 return RADEON_CTX_PRIORITY_HIGH;
2106 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2107 return RADEON_CTX_PRIORITY_MEDIUM;
2108 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2109 return RADEON_CTX_PRIORITY_LOW;
2110 default:
2111 unreachable("Illegal global priority value");
2112 return RADEON_CTX_PRIORITY_INVALID;
2113 }
2114 }
2115
2116 static int
2117 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2118 uint32_t queue_family_index, int idx,
2119 VkDeviceQueueCreateFlags flags,
2120 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2121 {
2122 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2123 queue->device = device;
2124 queue->queue_family_index = queue_family_index;
2125 queue->queue_idx = idx;
2126 queue->priority = radv_get_queue_global_priority(global_priority);
2127 queue->flags = flags;
2128
2129 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
2130 if (!queue->hw_ctx)
2131 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2132
2133 list_inithead(&queue->pending_submissions);
2134 pthread_mutex_init(&queue->pending_mutex, NULL);
2135
2136 return VK_SUCCESS;
2137 }
2138
2139 static void
2140 radv_queue_finish(struct radv_queue *queue)
2141 {
2142 pthread_mutex_destroy(&queue->pending_mutex);
2143
2144 if (queue->hw_ctx)
2145 queue->device->ws->ctx_destroy(queue->hw_ctx);
2146
2147 if (queue->initial_full_flush_preamble_cs)
2148 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2149 if (queue->initial_preamble_cs)
2150 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2151 if (queue->continue_preamble_cs)
2152 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2153 if (queue->descriptor_bo)
2154 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2155 if (queue->scratch_bo)
2156 queue->device->ws->buffer_destroy(queue->scratch_bo);
2157 if (queue->esgs_ring_bo)
2158 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2159 if (queue->gsvs_ring_bo)
2160 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2161 if (queue->tess_rings_bo)
2162 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2163 if (queue->gds_bo)
2164 queue->device->ws->buffer_destroy(queue->gds_bo);
2165 if (queue->gds_oa_bo)
2166 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2167 if (queue->compute_scratch_bo)
2168 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2169 }
2170
2171 static void
2172 radv_bo_list_init(struct radv_bo_list *bo_list)
2173 {
2174 pthread_mutex_init(&bo_list->mutex, NULL);
2175 bo_list->list.count = bo_list->capacity = 0;
2176 bo_list->list.bos = NULL;
2177 }
2178
2179 static void
2180 radv_bo_list_finish(struct radv_bo_list *bo_list)
2181 {
2182 free(bo_list->list.bos);
2183 pthread_mutex_destroy(&bo_list->mutex);
2184 }
2185
2186 static VkResult radv_bo_list_add(struct radv_device *device,
2187 struct radeon_winsys_bo *bo)
2188 {
2189 struct radv_bo_list *bo_list = &device->bo_list;
2190
2191 if (bo->is_local)
2192 return VK_SUCCESS;
2193
2194 if (unlikely(!device->use_global_bo_list))
2195 return VK_SUCCESS;
2196
2197 pthread_mutex_lock(&bo_list->mutex);
2198 if (bo_list->list.count == bo_list->capacity) {
2199 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2200 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2201
2202 if (!data) {
2203 pthread_mutex_unlock(&bo_list->mutex);
2204 return VK_ERROR_OUT_OF_HOST_MEMORY;
2205 }
2206
2207 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2208 bo_list->capacity = capacity;
2209 }
2210
2211 bo_list->list.bos[bo_list->list.count++] = bo;
2212 pthread_mutex_unlock(&bo_list->mutex);
2213 return VK_SUCCESS;
2214 }
2215
2216 static void radv_bo_list_remove(struct radv_device *device,
2217 struct radeon_winsys_bo *bo)
2218 {
2219 struct radv_bo_list *bo_list = &device->bo_list;
2220
2221 if (bo->is_local)
2222 return;
2223
2224 if (unlikely(!device->use_global_bo_list))
2225 return;
2226
2227 pthread_mutex_lock(&bo_list->mutex);
2228 for(unsigned i = 0; i < bo_list->list.count; ++i) {
2229 if (bo_list->list.bos[i] == bo) {
2230 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2231 --bo_list->list.count;
2232 break;
2233 }
2234 }
2235 pthread_mutex_unlock(&bo_list->mutex);
2236 }
2237
2238 static void
2239 radv_device_init_gs_info(struct radv_device *device)
2240 {
2241 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2242 device->physical_device->rad_info.family);
2243 }
2244
2245 static int radv_get_device_extension_index(const char *name)
2246 {
2247 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2248 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2249 return i;
2250 }
2251 return -1;
2252 }
2253
2254 static int
2255 radv_get_int_debug_option(const char *name, int default_value)
2256 {
2257 const char *str;
2258 int result;
2259
2260 str = getenv(name);
2261 if (!str) {
2262 result = default_value;
2263 } else {
2264 char *endptr;
2265
2266 result = strtol(str, &endptr, 0);
2267 if (str == endptr) {
2268 /* No digits founs. */
2269 result = default_value;
2270 }
2271 }
2272
2273 return result;
2274 }
2275
2276 static int install_seccomp_filter() {
2277
2278 struct sock_filter filter[] = {
2279 /* Check arch is 64bit x86 */
2280 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2281 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2282
2283 /* Futex is required for mutex locks */
2284 #if defined __NR__newselect
2285 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2286 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2287 #elif defined __NR_select
2288 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2289 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2290 #else
2291 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2292 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2293 #endif
2294
2295 /* Allow system exit calls for the forked process */
2296 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2297 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2298
2299 /* Allow system read calls */
2300 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2301 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2302
2303 /* Allow system write calls */
2304 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2305 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2306
2307 /* Allow system brk calls (we need this for malloc) */
2308 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2309 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2310
2311 /* Futex is required for mutex locks */
2312 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2313 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2314
2315 /* Return error if we hit a system call not on the whitelist */
2316 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2317
2318 /* Allow whitelisted system calls */
2319 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2320 };
2321
2322 struct sock_fprog prog = {
2323 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2324 .filter = filter,
2325 };
2326
2327 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2328 return -1;
2329
2330 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2331 return -1;
2332
2333 return 0;
2334 }
2335
2336 /* Helper function with timeout support for reading from the pipe between
2337 * processes used for secure compile.
2338 */
2339 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2340 {
2341 fd_set fds;
2342 struct timeval tv;
2343
2344 FD_ZERO(&fds);
2345 FD_SET(fd, &fds);
2346
2347 while (true) {
2348 /* We can't rely on the value of tv after calling select() so
2349 * we must reset it on each iteration of the loop.
2350 */
2351 tv.tv_sec = 5;
2352 tv.tv_usec = 0;
2353
2354 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2355
2356 if (rval == -1) {
2357 /* select error */
2358 return false;
2359 } else if (rval) {
2360 ssize_t bytes_read = read(fd, buf, size);
2361 if (bytes_read < 0)
2362 return false;
2363
2364 buf += bytes_read;
2365 size -= bytes_read;
2366 if (size == 0)
2367 return true;
2368 } else {
2369 /* select timeout */
2370 return false;
2371 }
2372 }
2373 }
2374
2375 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2376 {
2377 DIR *d;
2378 struct dirent *dir;
2379 d = opendir("/proc/self/fd");
2380 if (!d)
2381 return false;
2382 int dir_fd = dirfd(d);
2383
2384 while ((dir = readdir(d)) != NULL) {
2385 if (dir->d_name[0] == '.')
2386 continue;
2387
2388 int fd = atoi(dir->d_name);
2389 if (fd == dir_fd)
2390 continue;
2391
2392 bool keep = false;
2393 for (int i = 0; !keep && i < keep_fd_count; ++i)
2394 if (keep_fds[i] == fd)
2395 keep = true;
2396
2397 if (keep)
2398 continue;
2399
2400 close(fd);
2401 }
2402 closedir(d);
2403 return true;
2404 }
2405
2406 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2407 int *fd_server, int *fd_client,
2408 unsigned process, bool make_fifo)
2409 {
2410 bool result = false;
2411 char *fifo_server_path = NULL;
2412 char *fifo_client_path = NULL;
2413
2414 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2415 goto open_fifo_exit;
2416
2417 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2418 goto open_fifo_exit;
2419
2420 if (make_fifo) {
2421 int file1 = mkfifo(fifo_server_path, 0666);
2422 if(file1 < 0)
2423 goto open_fifo_exit;
2424
2425 int file2 = mkfifo(fifo_client_path, 0666);
2426 if(file2 < 0)
2427 goto open_fifo_exit;
2428 }
2429
2430 *fd_server = open(fifo_server_path, O_RDWR);
2431 if(*fd_server < 1)
2432 goto open_fifo_exit;
2433
2434 *fd_client = open(fifo_client_path, O_RDWR);
2435 if(*fd_client < 1) {
2436 close(*fd_server);
2437 goto open_fifo_exit;
2438 }
2439
2440 result = true;
2441
2442 open_fifo_exit:
2443 free(fifo_server_path);
2444 free(fifo_client_path);
2445
2446 return result;
2447 }
2448
2449 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2450 int fd_idle_device_output)
2451 {
2452 int fd_secure_input;
2453 int fd_secure_output;
2454 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2455 &fd_secure_input,
2456 &fd_secure_output,
2457 process, false);
2458
2459 enum radv_secure_compile_type sc_type;
2460
2461 const int needed_fds[] = {
2462 fd_secure_input,
2463 fd_secure_output,
2464 fd_idle_device_output,
2465 };
2466
2467 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2468 install_seccomp_filter() == -1) {
2469 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2470 } else {
2471 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2472 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2473 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2474 }
2475
2476 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2477
2478 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2479 goto secure_compile_exit;
2480
2481 while (true) {
2482 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2483
2484 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2485 struct radv_pipeline *pipeline;
2486 bool sc_read = true;
2487
2488 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2489 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2490
2491 pipeline->device = device;
2492
2493 /* Read pipeline layout */
2494 struct radv_pipeline_layout layout;
2495 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2496 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2497 if (!sc_read)
2498 goto secure_compile_exit;
2499
2500 for (uint32_t set = 0; set < layout.num_sets; set++) {
2501 uint32_t layout_size;
2502 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2503 if (!sc_read)
2504 goto secure_compile_exit;
2505
2506 layout.set[set].layout = malloc(layout_size);
2507 layout.set[set].layout->layout_size = layout_size;
2508 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2509 layout.set[set].layout->layout_size, true);
2510 }
2511
2512 pipeline->layout = &layout;
2513
2514 /* Read pipeline key */
2515 struct radv_pipeline_key key;
2516 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2517
2518 /* Read pipeline create flags */
2519 VkPipelineCreateFlags flags;
2520 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2521
2522 /* Read stage and shader information */
2523 uint32_t num_stages;
2524 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2525 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2526 if (!sc_read)
2527 goto secure_compile_exit;
2528
2529 for (uint32_t i = 0; i < num_stages; i++) {
2530
2531 /* Read stage */
2532 gl_shader_stage stage;
2533 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2534
2535 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2536
2537 /* Read entry point name */
2538 size_t name_size;
2539 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2540 if (!sc_read)
2541 goto secure_compile_exit;
2542
2543 char *ep_name = malloc(name_size);
2544 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2545 pStage->pName = ep_name;
2546
2547 /* Read shader module */
2548 size_t module_size;
2549 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2550 if (!sc_read)
2551 goto secure_compile_exit;
2552
2553 struct radv_shader_module *module = malloc(module_size);
2554 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2555 pStage->module = radv_shader_module_to_handle(module);
2556
2557 /* Read specialization info */
2558 bool has_spec_info;
2559 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2560 if (!sc_read)
2561 goto secure_compile_exit;
2562
2563 if (has_spec_info) {
2564 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2565 pStage->pSpecializationInfo = specInfo;
2566
2567 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2568 if (!sc_read)
2569 goto secure_compile_exit;
2570
2571 void *si_data = malloc(specInfo->dataSize);
2572 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2573 specInfo->pData = si_data;
2574
2575 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2576 if (!sc_read)
2577 goto secure_compile_exit;
2578
2579 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2580 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2581 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2582 if (!sc_read)
2583 goto secure_compile_exit;
2584 }
2585
2586 specInfo->pMapEntries = mapEntries;
2587 }
2588
2589 pStages[stage] = pStage;
2590 }
2591
2592 /* Compile the shaders */
2593 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2594 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2595
2596 /* free memory allocated above */
2597 for (uint32_t set = 0; set < layout.num_sets; set++)
2598 free(layout.set[set].layout);
2599
2600 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2601 if (!pStages[i])
2602 continue;
2603
2604 free((void *) pStages[i]->pName);
2605 free(radv_shader_module_from_handle(pStages[i]->module));
2606 if (pStages[i]->pSpecializationInfo) {
2607 free((void *) pStages[i]->pSpecializationInfo->pData);
2608 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2609 free((void *) pStages[i]->pSpecializationInfo);
2610 }
2611 free((void *) pStages[i]);
2612 }
2613
2614 vk_free(&device->alloc, pipeline);
2615
2616 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2617 write(fd_secure_output, &sc_type, sizeof(sc_type));
2618
2619 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2620 goto secure_compile_exit;
2621 }
2622 }
2623
2624 secure_compile_exit:
2625 close(fd_secure_input);
2626 close(fd_secure_output);
2627 close(fd_idle_device_output);
2628 _exit(0);
2629 }
2630
2631 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2632 {
2633 int fd_secure_input[2];
2634 int fd_secure_output[2];
2635
2636 /* create pipe descriptors (used to communicate between processes) */
2637 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2638 return RADV_SC_TYPE_INIT_FAILURE;
2639
2640
2641 int sc_pid;
2642 if ((sc_pid = fork()) == 0) {
2643 device->sc_state->secure_compile_thread_counter = process;
2644 run_secure_compile_device(device, process, fd_secure_output[1]);
2645 } else {
2646 if (sc_pid == -1)
2647 return RADV_SC_TYPE_INIT_FAILURE;
2648
2649 /* Read the init result returned from the secure process */
2650 enum radv_secure_compile_type sc_type;
2651 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2652
2653 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2654 close(fd_secure_input[0]);
2655 close(fd_secure_input[1]);
2656 close(fd_secure_output[1]);
2657 close(fd_secure_output[0]);
2658 int status;
2659 waitpid(sc_pid, &status, 0);
2660
2661 return RADV_SC_TYPE_INIT_FAILURE;
2662 } else {
2663 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2664 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2665
2666 close(fd_secure_input[0]);
2667 close(fd_secure_input[1]);
2668 close(fd_secure_output[1]);
2669 close(fd_secure_output[0]);
2670
2671 int status;
2672 waitpid(sc_pid, &status, 0);
2673 }
2674 }
2675
2676 return RADV_SC_TYPE_INIT_SUCCESS;
2677 }
2678
2679 /* Run a bare bones fork of a device that was forked right after its creation.
2680 * This device will have low overhead when it is forked again before each
2681 * pipeline compilation. This device sits idle and its only job is to fork
2682 * itself.
2683 */
2684 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2685 int fd_secure_input, int fd_secure_output)
2686 {
2687 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2688 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2689 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2690
2691 write(fd_secure_output, &sc_type, sizeof(sc_type));
2692
2693 while (true) {
2694 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2695
2696 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2697 sc_type = fork_secure_compile_device(device, process);
2698
2699 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2700 goto secure_compile_exit;
2701
2702 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2703 goto secure_compile_exit;
2704 }
2705 }
2706
2707 secure_compile_exit:
2708 close(fd_secure_input);
2709 close(fd_secure_output);
2710 _exit(0);
2711 }
2712
2713 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2714 {
2715 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2716
2717 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2718 write(fd_secure_input, &sc_type, sizeof(sc_type));
2719
2720 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2721 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2722
2723 int status;
2724 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2725 }
2726
2727 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2728 {
2729 device->sc_state = vk_zalloc(&device->alloc,
2730 sizeof(struct radv_secure_compile_state),
2731 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2732
2733 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2734
2735 pid_t upid = getpid();
2736 time_t seconds = time(NULL);
2737
2738 char *uid;
2739 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2740 return VK_ERROR_INITIALIZATION_FAILED;
2741
2742 device->sc_state->uid = uid;
2743
2744 uint8_t sc_threads = device->instance->num_sc_threads;
2745 int fd_secure_input[MAX_SC_PROCS][2];
2746 int fd_secure_output[MAX_SC_PROCS][2];
2747
2748 /* create pipe descriptors (used to communicate between processes) */
2749 for (unsigned i = 0; i < sc_threads; i++) {
2750 if (pipe(fd_secure_input[i]) == -1 ||
2751 pipe(fd_secure_output[i]) == -1) {
2752 return VK_ERROR_INITIALIZATION_FAILED;
2753 }
2754 }
2755
2756 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2757 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2758 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2759
2760 for (unsigned process = 0; process < sc_threads; process++) {
2761 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2762 device->sc_state->secure_compile_thread_counter = process;
2763 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2764 } else {
2765 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2766 return VK_ERROR_INITIALIZATION_FAILED;
2767
2768 /* Read the init result returned from the secure process */
2769 enum radv_secure_compile_type sc_type;
2770 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2771
2772 bool fifo_result;
2773 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2774 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2775 &device->sc_state->secure_compile_processes[process].fd_server,
2776 &device->sc_state->secure_compile_processes[process].fd_client,
2777 process, true);
2778
2779 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2780 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2781 }
2782
2783 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2784 close(fd_secure_input[process][0]);
2785 close(fd_secure_input[process][1]);
2786 close(fd_secure_output[process][1]);
2787 close(fd_secure_output[process][0]);
2788 int status;
2789 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2790
2791 /* Destroy any forks that were created sucessfully */
2792 for (unsigned i = 0; i < process; i++) {
2793 destroy_secure_compile_device(device, i);
2794 }
2795
2796 return VK_ERROR_INITIALIZATION_FAILED;
2797 }
2798 }
2799 }
2800 return VK_SUCCESS;
2801 }
2802
2803 static VkResult
2804 radv_create_pthread_cond(pthread_cond_t *cond)
2805 {
2806 pthread_condattr_t condattr;
2807 if (pthread_condattr_init(&condattr)) {
2808 return VK_ERROR_INITIALIZATION_FAILED;
2809 }
2810
2811 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2812 pthread_condattr_destroy(&condattr);
2813 return VK_ERROR_INITIALIZATION_FAILED;
2814 }
2815 if (pthread_cond_init(cond, &condattr)) {
2816 pthread_condattr_destroy(&condattr);
2817 return VK_ERROR_INITIALIZATION_FAILED;
2818 }
2819 pthread_condattr_destroy(&condattr);
2820 return VK_SUCCESS;
2821 }
2822
2823 VkResult radv_CreateDevice(
2824 VkPhysicalDevice physicalDevice,
2825 const VkDeviceCreateInfo* pCreateInfo,
2826 const VkAllocationCallbacks* pAllocator,
2827 VkDevice* pDevice)
2828 {
2829 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2830 VkResult result;
2831 struct radv_device *device;
2832
2833 bool keep_shader_info = false;
2834
2835 /* Check enabled features */
2836 if (pCreateInfo->pEnabledFeatures) {
2837 VkPhysicalDeviceFeatures supported_features;
2838 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2839 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2840 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
2841 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2842 for (uint32_t i = 0; i < num_features; i++) {
2843 if (enabled_feature[i] && !supported_feature[i])
2844 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2845 }
2846 }
2847
2848 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2849 sizeof(*device), 8,
2850 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2851 if (!device)
2852 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2853
2854 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2855 device->instance = physical_device->instance;
2856 device->physical_device = physical_device;
2857
2858 device->ws = physical_device->ws;
2859 if (pAllocator)
2860 device->alloc = *pAllocator;
2861 else
2862 device->alloc = physical_device->instance->alloc;
2863
2864 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2865 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2866 int index = radv_get_device_extension_index(ext_name);
2867 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2868 vk_free(&device->alloc, device);
2869 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2870 }
2871
2872 device->enabled_extensions.extensions[index] = true;
2873 }
2874
2875 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2876
2877 /* With update after bind we can't attach bo's to the command buffer
2878 * from the descriptor set anymore, so we have to use a global BO list.
2879 */
2880 device->use_global_bo_list =
2881 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2882 device->enabled_extensions.EXT_descriptor_indexing ||
2883 device->enabled_extensions.EXT_buffer_device_address ||
2884 device->enabled_extensions.KHR_buffer_device_address;
2885
2886 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
2887 pCreateInfo->pEnabledFeatures->robustBufferAccess;
2888
2889 mtx_init(&device->shader_slab_mutex, mtx_plain);
2890 list_inithead(&device->shader_slabs);
2891
2892 radv_bo_list_init(&device->bo_list);
2893
2894 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2895 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2896 uint32_t qfi = queue_create->queueFamilyIndex;
2897 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2898 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2899
2900 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2901
2902 device->queues[qfi] = vk_alloc(&device->alloc,
2903 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2904 if (!device->queues[qfi]) {
2905 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2906 goto fail;
2907 }
2908
2909 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2910
2911 device->queue_count[qfi] = queue_create->queueCount;
2912
2913 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2914 result = radv_queue_init(device, &device->queues[qfi][q],
2915 qfi, q, queue_create->flags,
2916 global_priority);
2917 if (result != VK_SUCCESS)
2918 goto fail;
2919 }
2920 }
2921
2922 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2923 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2924
2925 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2926 device->dfsm_allowed = device->pbb_allowed &&
2927 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2928
2929 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2930
2931 /* The maximum number of scratch waves. Scratch space isn't divided
2932 * evenly between CUs. The number is only a function of the number of CUs.
2933 * We can decrease the constant to decrease the scratch buffer size.
2934 *
2935 * sctx->scratch_waves must be >= the maximum possible size of
2936 * 1 threadgroup, so that the hw doesn't hang from being unable
2937 * to start any.
2938 *
2939 * The recommended value is 4 per CU at most. Higher numbers don't
2940 * bring much benefit, but they still occupy chip resources (think
2941 * async compute). I've seen ~2% performance difference between 4 and 32.
2942 */
2943 uint32_t max_threads_per_block = 2048;
2944 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2945 max_threads_per_block / 64);
2946
2947 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2948
2949 if (device->physical_device->rad_info.chip_class >= GFX7) {
2950 /* If the KMD allows it (there is a KMD hw register for it),
2951 * allow launching waves out-of-order.
2952 */
2953 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2954 }
2955
2956 radv_device_init_gs_info(device);
2957
2958 device->tess_offchip_block_dw_size =
2959 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2960
2961 if (getenv("RADV_TRACE_FILE")) {
2962 const char *filename = getenv("RADV_TRACE_FILE");
2963
2964 keep_shader_info = true;
2965
2966 if (!radv_init_trace(device))
2967 goto fail;
2968
2969 fprintf(stderr, "*****************************************************************************\n");
2970 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2971 fprintf(stderr, "*****************************************************************************\n");
2972
2973 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2974 radv_dump_enabled_options(device, stderr);
2975 }
2976
2977 /* Temporarily disable secure compile while we create meta shaders, etc */
2978 uint8_t sc_threads = device->instance->num_sc_threads;
2979 if (sc_threads)
2980 device->instance->num_sc_threads = 0;
2981
2982 device->keep_shader_info = keep_shader_info;
2983 result = radv_device_init_meta(device);
2984 if (result != VK_SUCCESS)
2985 goto fail;
2986
2987 radv_device_init_msaa(device);
2988
2989 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2990 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2991 switch (family) {
2992 case RADV_QUEUE_GENERAL:
2993 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2994 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2995 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2996 break;
2997 case RADV_QUEUE_COMPUTE:
2998 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2999 radeon_emit(device->empty_cs[family], 0);
3000 break;
3001 }
3002 device->ws->cs_finalize(device->empty_cs[family]);
3003 }
3004
3005 if (device->physical_device->rad_info.chip_class >= GFX7)
3006 cik_create_gfx_config(device);
3007
3008 VkPipelineCacheCreateInfo ci;
3009 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
3010 ci.pNext = NULL;
3011 ci.flags = 0;
3012 ci.pInitialData = NULL;
3013 ci.initialDataSize = 0;
3014 VkPipelineCache pc;
3015 result = radv_CreatePipelineCache(radv_device_to_handle(device),
3016 &ci, NULL, &pc);
3017 if (result != VK_SUCCESS)
3018 goto fail_meta;
3019
3020 device->mem_cache = radv_pipeline_cache_from_handle(pc);
3021
3022 result = radv_create_pthread_cond(&device->timeline_cond);
3023 if (result != VK_SUCCESS)
3024 goto fail_mem_cache;
3025
3026 device->force_aniso =
3027 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3028 if (device->force_aniso >= 0) {
3029 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
3030 1 << util_logbase2(device->force_aniso));
3031 }
3032
3033 /* Fork device for secure compile as required */
3034 device->instance->num_sc_threads = sc_threads;
3035 if (radv_device_use_secure_compile(device->instance)) {
3036
3037 result = fork_secure_compile_idle_device(device);
3038 if (result != VK_SUCCESS)
3039 goto fail_meta;
3040 }
3041
3042 *pDevice = radv_device_to_handle(device);
3043 return VK_SUCCESS;
3044
3045 fail_mem_cache:
3046 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3047 fail_meta:
3048 radv_device_finish_meta(device);
3049 fail:
3050 radv_bo_list_finish(&device->bo_list);
3051
3052 if (device->trace_bo)
3053 device->ws->buffer_destroy(device->trace_bo);
3054
3055 if (device->gfx_init)
3056 device->ws->buffer_destroy(device->gfx_init);
3057
3058 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3059 for (unsigned q = 0; q < device->queue_count[i]; q++)
3060 radv_queue_finish(&device->queues[i][q]);
3061 if (device->queue_count[i])
3062 vk_free(&device->alloc, device->queues[i]);
3063 }
3064
3065 vk_free(&device->alloc, device);
3066 return result;
3067 }
3068
3069 void radv_DestroyDevice(
3070 VkDevice _device,
3071 const VkAllocationCallbacks* pAllocator)
3072 {
3073 RADV_FROM_HANDLE(radv_device, device, _device);
3074
3075 if (!device)
3076 return;
3077
3078 if (device->trace_bo)
3079 device->ws->buffer_destroy(device->trace_bo);
3080
3081 if (device->gfx_init)
3082 device->ws->buffer_destroy(device->gfx_init);
3083
3084 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3085 for (unsigned q = 0; q < device->queue_count[i]; q++)
3086 radv_queue_finish(&device->queues[i][q]);
3087 if (device->queue_count[i])
3088 vk_free(&device->alloc, device->queues[i]);
3089 if (device->empty_cs[i])
3090 device->ws->cs_destroy(device->empty_cs[i]);
3091 }
3092 radv_device_finish_meta(device);
3093
3094 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
3095 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3096
3097 radv_destroy_shader_slabs(device);
3098
3099 pthread_cond_destroy(&device->timeline_cond);
3100 radv_bo_list_finish(&device->bo_list);
3101 if (radv_device_use_secure_compile(device->instance)) {
3102 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
3103 destroy_secure_compile_device(device, i);
3104 }
3105 }
3106
3107 if (device->sc_state) {
3108 free(device->sc_state->uid);
3109 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
3110 }
3111 vk_free(&device->alloc, device->sc_state);
3112 vk_free(&device->alloc, device);
3113 }
3114
3115 VkResult radv_EnumerateInstanceLayerProperties(
3116 uint32_t* pPropertyCount,
3117 VkLayerProperties* pProperties)
3118 {
3119 if (pProperties == NULL) {
3120 *pPropertyCount = 0;
3121 return VK_SUCCESS;
3122 }
3123
3124 /* None supported at this time */
3125 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3126 }
3127
3128 VkResult radv_EnumerateDeviceLayerProperties(
3129 VkPhysicalDevice physicalDevice,
3130 uint32_t* pPropertyCount,
3131 VkLayerProperties* pProperties)
3132 {
3133 if (pProperties == NULL) {
3134 *pPropertyCount = 0;
3135 return VK_SUCCESS;
3136 }
3137
3138 /* None supported at this time */
3139 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3140 }
3141
3142 void radv_GetDeviceQueue2(
3143 VkDevice _device,
3144 const VkDeviceQueueInfo2* pQueueInfo,
3145 VkQueue* pQueue)
3146 {
3147 RADV_FROM_HANDLE(radv_device, device, _device);
3148 struct radv_queue *queue;
3149
3150 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3151 if (pQueueInfo->flags != queue->flags) {
3152 /* From the Vulkan 1.1.70 spec:
3153 *
3154 * "The queue returned by vkGetDeviceQueue2 must have the same
3155 * flags value from this structure as that used at device
3156 * creation time in a VkDeviceQueueCreateInfo instance. If no
3157 * matching flags were specified at device creation time then
3158 * pQueue will return VK_NULL_HANDLE."
3159 */
3160 *pQueue = VK_NULL_HANDLE;
3161 return;
3162 }
3163
3164 *pQueue = radv_queue_to_handle(queue);
3165 }
3166
3167 void radv_GetDeviceQueue(
3168 VkDevice _device,
3169 uint32_t queueFamilyIndex,
3170 uint32_t queueIndex,
3171 VkQueue* pQueue)
3172 {
3173 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3174 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3175 .queueFamilyIndex = queueFamilyIndex,
3176 .queueIndex = queueIndex
3177 };
3178
3179 radv_GetDeviceQueue2(_device, &info, pQueue);
3180 }
3181
3182 static void
3183 fill_geom_tess_rings(struct radv_queue *queue,
3184 uint32_t *map,
3185 bool add_sample_positions,
3186 uint32_t esgs_ring_size,
3187 struct radeon_winsys_bo *esgs_ring_bo,
3188 uint32_t gsvs_ring_size,
3189 struct radeon_winsys_bo *gsvs_ring_bo,
3190 uint32_t tess_factor_ring_size,
3191 uint32_t tess_offchip_ring_offset,
3192 uint32_t tess_offchip_ring_size,
3193 struct radeon_winsys_bo *tess_rings_bo)
3194 {
3195 uint32_t *desc = &map[4];
3196
3197 if (esgs_ring_bo) {
3198 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3199
3200 /* stride 0, num records - size, add tid, swizzle, elsize4,
3201 index stride 64 */
3202 desc[0] = esgs_va;
3203 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3204 S_008F04_SWIZZLE_ENABLE(true);
3205 desc[2] = esgs_ring_size;
3206 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3207 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3208 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3209 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3210 S_008F0C_INDEX_STRIDE(3) |
3211 S_008F0C_ADD_TID_ENABLE(1);
3212
3213 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3214 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3215 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3216 S_008F0C_RESOURCE_LEVEL(1);
3217 } else {
3218 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3219 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3220 S_008F0C_ELEMENT_SIZE(1);
3221 }
3222
3223 /* GS entry for ES->GS ring */
3224 /* stride 0, num records - size, elsize0,
3225 index stride 0 */
3226 desc[4] = esgs_va;
3227 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3228 desc[6] = esgs_ring_size;
3229 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3233
3234 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3235 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3236 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3237 S_008F0C_RESOURCE_LEVEL(1);
3238 } else {
3239 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3241 }
3242 }
3243
3244 desc += 8;
3245
3246 if (gsvs_ring_bo) {
3247 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3248
3249 /* VS entry for GS->VS ring */
3250 /* stride 0, num records - size, elsize0,
3251 index stride 0 */
3252 desc[0] = gsvs_va;
3253 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3254 desc[2] = gsvs_ring_size;
3255 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3256 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3257 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3258 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3259
3260 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3261 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3262 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3263 S_008F0C_RESOURCE_LEVEL(1);
3264 } else {
3265 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3266 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3267 }
3268
3269 /* stride gsvs_itemsize, num records 64
3270 elsize 4, index stride 16 */
3271 /* shader will patch stride and desc[2] */
3272 desc[4] = gsvs_va;
3273 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3274 S_008F04_SWIZZLE_ENABLE(1);
3275 desc[6] = 0;
3276 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3280 S_008F0C_INDEX_STRIDE(1) |
3281 S_008F0C_ADD_TID_ENABLE(true);
3282
3283 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3284 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3285 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3286 S_008F0C_RESOURCE_LEVEL(1);
3287 } else {
3288 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3290 S_008F0C_ELEMENT_SIZE(1);
3291 }
3292
3293 }
3294
3295 desc += 8;
3296
3297 if (tess_rings_bo) {
3298 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3299 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3300
3301 desc[0] = tess_va;
3302 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3303 desc[2] = tess_factor_ring_size;
3304 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3308
3309 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3310 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3311 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3312 S_008F0C_RESOURCE_LEVEL(1);
3313 } else {
3314 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3315 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3316 }
3317
3318 desc[4] = tess_offchip_va;
3319 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3320 desc[6] = tess_offchip_ring_size;
3321 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3322 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3323 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3324 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3325
3326 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3327 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3328 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3329 S_008F0C_RESOURCE_LEVEL(1);
3330 } else {
3331 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3332 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3333 }
3334 }
3335
3336 desc += 8;
3337
3338 if (add_sample_positions) {
3339 /* add sample positions after all rings */
3340 memcpy(desc, queue->device->sample_locations_1x, 8);
3341 desc += 2;
3342 memcpy(desc, queue->device->sample_locations_2x, 16);
3343 desc += 4;
3344 memcpy(desc, queue->device->sample_locations_4x, 32);
3345 desc += 8;
3346 memcpy(desc, queue->device->sample_locations_8x, 64);
3347 }
3348 }
3349
3350 static unsigned
3351 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3352 {
3353 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3354 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3355 device->physical_device->rad_info.family != CHIP_STONEY;
3356 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3357 unsigned max_offchip_buffers;
3358 unsigned offchip_granularity;
3359 unsigned hs_offchip_param;
3360
3361 /*
3362 * Per RadeonSI:
3363 * This must be one less than the maximum number due to a hw limitation.
3364 * Various hardware bugs need thGFX7
3365 *
3366 * Per AMDVLK:
3367 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3368 * Gfx7 should limit max_offchip_buffers to 508
3369 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3370 *
3371 * Follow AMDVLK here.
3372 */
3373 if (device->physical_device->rad_info.chip_class >= GFX10) {
3374 max_offchip_buffers_per_se = 256;
3375 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3376 device->physical_device->rad_info.chip_class == GFX7 ||
3377 device->physical_device->rad_info.chip_class == GFX6)
3378 --max_offchip_buffers_per_se;
3379
3380 max_offchip_buffers = max_offchip_buffers_per_se *
3381 device->physical_device->rad_info.max_se;
3382
3383 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3384 * around by setting 4K granularity.
3385 */
3386 if (device->tess_offchip_block_dw_size == 4096) {
3387 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3388 offchip_granularity = V_03093C_X_4K_DWORDS;
3389 } else {
3390 assert(device->tess_offchip_block_dw_size == 8192);
3391 offchip_granularity = V_03093C_X_8K_DWORDS;
3392 }
3393
3394 switch (device->physical_device->rad_info.chip_class) {
3395 case GFX6:
3396 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3397 break;
3398 case GFX7:
3399 case GFX8:
3400 case GFX9:
3401 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3402 break;
3403 case GFX10:
3404 break;
3405 default:
3406 break;
3407 }
3408
3409 *max_offchip_buffers_p = max_offchip_buffers;
3410 if (device->physical_device->rad_info.chip_class >= GFX7) {
3411 if (device->physical_device->rad_info.chip_class >= GFX8)
3412 --max_offchip_buffers;
3413 hs_offchip_param =
3414 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3415 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3416 } else {
3417 hs_offchip_param =
3418 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3419 }
3420 return hs_offchip_param;
3421 }
3422
3423 static void
3424 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3425 struct radeon_winsys_bo *esgs_ring_bo,
3426 uint32_t esgs_ring_size,
3427 struct radeon_winsys_bo *gsvs_ring_bo,
3428 uint32_t gsvs_ring_size)
3429 {
3430 if (!esgs_ring_bo && !gsvs_ring_bo)
3431 return;
3432
3433 if (esgs_ring_bo)
3434 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3435
3436 if (gsvs_ring_bo)
3437 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3438
3439 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3440 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3441 radeon_emit(cs, esgs_ring_size >> 8);
3442 radeon_emit(cs, gsvs_ring_size >> 8);
3443 } else {
3444 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3445 radeon_emit(cs, esgs_ring_size >> 8);
3446 radeon_emit(cs, gsvs_ring_size >> 8);
3447 }
3448 }
3449
3450 static void
3451 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3452 unsigned hs_offchip_param, unsigned tf_ring_size,
3453 struct radeon_winsys_bo *tess_rings_bo)
3454 {
3455 uint64_t tf_va;
3456
3457 if (!tess_rings_bo)
3458 return;
3459
3460 tf_va = radv_buffer_get_va(tess_rings_bo);
3461
3462 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3463
3464 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3465 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3466 S_030938_SIZE(tf_ring_size / 4));
3467 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3468 tf_va >> 8);
3469
3470 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3471 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3472 S_030984_BASE_HI(tf_va >> 40));
3473 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3474 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3475 S_030944_BASE_HI(tf_va >> 40));
3476 }
3477 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3478 hs_offchip_param);
3479 } else {
3480 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3481 S_008988_SIZE(tf_ring_size / 4));
3482 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3483 tf_va >> 8);
3484 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3485 hs_offchip_param);
3486 }
3487 }
3488
3489 static void
3490 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3491 uint32_t size_per_wave, uint32_t waves,
3492 struct radeon_winsys_bo *scratch_bo)
3493 {
3494 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3495 return;
3496
3497 if (!scratch_bo)
3498 return;
3499
3500 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3501
3502 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3503 S_0286E8_WAVES(waves) |
3504 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3505 }
3506
3507 static void
3508 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3509 uint32_t size_per_wave, uint32_t waves,
3510 struct radeon_winsys_bo *compute_scratch_bo)
3511 {
3512 uint64_t scratch_va;
3513
3514 if (!compute_scratch_bo)
3515 return;
3516
3517 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3518
3519 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3520
3521 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3522 radeon_emit(cs, scratch_va);
3523 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3524 S_008F04_SWIZZLE_ENABLE(1));
3525
3526 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3527 S_00B860_WAVES(waves) |
3528 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3529 }
3530
3531 static void
3532 radv_emit_global_shader_pointers(struct radv_queue *queue,
3533 struct radeon_cmdbuf *cs,
3534 struct radeon_winsys_bo *descriptor_bo)
3535 {
3536 uint64_t va;
3537
3538 if (!descriptor_bo)
3539 return;
3540
3541 va = radv_buffer_get_va(descriptor_bo);
3542
3543 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3544
3545 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3546 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3547 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3548 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3549 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3550
3551 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3552 radv_emit_shader_pointer(queue->device, cs, regs[i],
3553 va, true);
3554 }
3555 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3556 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3557 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3558 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3559 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3560
3561 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3562 radv_emit_shader_pointer(queue->device, cs, regs[i],
3563 va, true);
3564 }
3565 } else {
3566 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3567 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3568 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3569 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3570 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3571 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3572
3573 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3574 radv_emit_shader_pointer(queue->device, cs, regs[i],
3575 va, true);
3576 }
3577 }
3578 }
3579
3580 static void
3581 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3582 {
3583 struct radv_device *device = queue->device;
3584
3585 if (device->gfx_init) {
3586 uint64_t va = radv_buffer_get_va(device->gfx_init);
3587
3588 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3589 radeon_emit(cs, va);
3590 radeon_emit(cs, va >> 32);
3591 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3592
3593 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3594 } else {
3595 struct radv_physical_device *physical_device = device->physical_device;
3596 si_emit_graphics(physical_device, cs);
3597 }
3598 }
3599
3600 static void
3601 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3602 {
3603 struct radv_physical_device *physical_device = queue->device->physical_device;
3604 si_emit_compute(physical_device, cs);
3605 }
3606
3607 static VkResult
3608 radv_get_preamble_cs(struct radv_queue *queue,
3609 uint32_t scratch_size_per_wave,
3610 uint32_t scratch_waves,
3611 uint32_t compute_scratch_size_per_wave,
3612 uint32_t compute_scratch_waves,
3613 uint32_t esgs_ring_size,
3614 uint32_t gsvs_ring_size,
3615 bool needs_tess_rings,
3616 bool needs_gds,
3617 bool needs_gds_oa,
3618 bool needs_sample_positions,
3619 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3620 struct radeon_cmdbuf **initial_preamble_cs,
3621 struct radeon_cmdbuf **continue_preamble_cs)
3622 {
3623 struct radeon_winsys_bo *scratch_bo = NULL;
3624 struct radeon_winsys_bo *descriptor_bo = NULL;
3625 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3626 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3627 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3628 struct radeon_winsys_bo *tess_rings_bo = NULL;
3629 struct radeon_winsys_bo *gds_bo = NULL;
3630 struct radeon_winsys_bo *gds_oa_bo = NULL;
3631 struct radeon_cmdbuf *dest_cs[3] = {0};
3632 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3633 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3634 unsigned max_offchip_buffers;
3635 unsigned hs_offchip_param = 0;
3636 unsigned tess_offchip_ring_offset;
3637 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3638 if (!queue->has_tess_rings) {
3639 if (needs_tess_rings)
3640 add_tess_rings = true;
3641 }
3642 if (!queue->has_gds) {
3643 if (needs_gds)
3644 add_gds = true;
3645 }
3646 if (!queue->has_gds_oa) {
3647 if (needs_gds_oa)
3648 add_gds_oa = true;
3649 }
3650 if (!queue->has_sample_positions) {
3651 if (needs_sample_positions)
3652 add_sample_positions = true;
3653 }
3654 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3655 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3656 &max_offchip_buffers);
3657 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3658 tess_offchip_ring_size = max_offchip_buffers *
3659 queue->device->tess_offchip_block_dw_size * 4;
3660
3661 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3662 if (scratch_size_per_wave)
3663 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3664 else
3665 scratch_waves = 0;
3666
3667 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3668 if (compute_scratch_size_per_wave)
3669 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3670 else
3671 compute_scratch_waves = 0;
3672
3673 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3674 scratch_waves <= queue->scratch_waves &&
3675 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3676 compute_scratch_waves <= queue->compute_scratch_waves &&
3677 esgs_ring_size <= queue->esgs_ring_size &&
3678 gsvs_ring_size <= queue->gsvs_ring_size &&
3679 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3680 queue->initial_preamble_cs) {
3681 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3682 *initial_preamble_cs = queue->initial_preamble_cs;
3683 *continue_preamble_cs = queue->continue_preamble_cs;
3684 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3685 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3686 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3687 *continue_preamble_cs = NULL;
3688 return VK_SUCCESS;
3689 }
3690
3691 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3692 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3693 if (scratch_size > queue_scratch_size) {
3694 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3695 scratch_size,
3696 4096,
3697 RADEON_DOMAIN_VRAM,
3698 ring_bo_flags,
3699 RADV_BO_PRIORITY_SCRATCH);
3700 if (!scratch_bo)
3701 goto fail;
3702 } else
3703 scratch_bo = queue->scratch_bo;
3704
3705 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3706 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3707 if (compute_scratch_size > compute_queue_scratch_size) {
3708 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3709 compute_scratch_size,
3710 4096,
3711 RADEON_DOMAIN_VRAM,
3712 ring_bo_flags,
3713 RADV_BO_PRIORITY_SCRATCH);
3714 if (!compute_scratch_bo)
3715 goto fail;
3716
3717 } else
3718 compute_scratch_bo = queue->compute_scratch_bo;
3719
3720 if (esgs_ring_size > queue->esgs_ring_size) {
3721 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3722 esgs_ring_size,
3723 4096,
3724 RADEON_DOMAIN_VRAM,
3725 ring_bo_flags,
3726 RADV_BO_PRIORITY_SCRATCH);
3727 if (!esgs_ring_bo)
3728 goto fail;
3729 } else {
3730 esgs_ring_bo = queue->esgs_ring_bo;
3731 esgs_ring_size = queue->esgs_ring_size;
3732 }
3733
3734 if (gsvs_ring_size > queue->gsvs_ring_size) {
3735 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3736 gsvs_ring_size,
3737 4096,
3738 RADEON_DOMAIN_VRAM,
3739 ring_bo_flags,
3740 RADV_BO_PRIORITY_SCRATCH);
3741 if (!gsvs_ring_bo)
3742 goto fail;
3743 } else {
3744 gsvs_ring_bo = queue->gsvs_ring_bo;
3745 gsvs_ring_size = queue->gsvs_ring_size;
3746 }
3747
3748 if (add_tess_rings) {
3749 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3750 tess_offchip_ring_offset + tess_offchip_ring_size,
3751 256,
3752 RADEON_DOMAIN_VRAM,
3753 ring_bo_flags,
3754 RADV_BO_PRIORITY_SCRATCH);
3755 if (!tess_rings_bo)
3756 goto fail;
3757 } else {
3758 tess_rings_bo = queue->tess_rings_bo;
3759 }
3760
3761 if (add_gds) {
3762 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3763
3764 /* 4 streamout GDS counters.
3765 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3766 */
3767 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3768 256, 4,
3769 RADEON_DOMAIN_GDS,
3770 ring_bo_flags,
3771 RADV_BO_PRIORITY_SCRATCH);
3772 if (!gds_bo)
3773 goto fail;
3774 } else {
3775 gds_bo = queue->gds_bo;
3776 }
3777
3778 if (add_gds_oa) {
3779 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3780
3781 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3782 4, 1,
3783 RADEON_DOMAIN_OA,
3784 ring_bo_flags,
3785 RADV_BO_PRIORITY_SCRATCH);
3786 if (!gds_oa_bo)
3787 goto fail;
3788 } else {
3789 gds_oa_bo = queue->gds_oa_bo;
3790 }
3791
3792 if (scratch_bo != queue->scratch_bo ||
3793 esgs_ring_bo != queue->esgs_ring_bo ||
3794 gsvs_ring_bo != queue->gsvs_ring_bo ||
3795 tess_rings_bo != queue->tess_rings_bo ||
3796 add_sample_positions) {
3797 uint32_t size = 0;
3798 if (gsvs_ring_bo || esgs_ring_bo ||
3799 tess_rings_bo || add_sample_positions) {
3800 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3801 if (add_sample_positions)
3802 size += 128; /* 64+32+16+8 = 120 bytes */
3803 }
3804 else if (scratch_bo)
3805 size = 8; /* 2 dword */
3806
3807 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3808 size,
3809 4096,
3810 RADEON_DOMAIN_VRAM,
3811 RADEON_FLAG_CPU_ACCESS |
3812 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3813 RADEON_FLAG_READ_ONLY,
3814 RADV_BO_PRIORITY_DESCRIPTOR);
3815 if (!descriptor_bo)
3816 goto fail;
3817 } else
3818 descriptor_bo = queue->descriptor_bo;
3819
3820 if (descriptor_bo != queue->descriptor_bo) {
3821 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3822
3823 if (scratch_bo) {
3824 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3825 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3826 S_008F04_SWIZZLE_ENABLE(1);
3827 map[0] = scratch_va;
3828 map[1] = rsrc1;
3829 }
3830
3831 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3832 fill_geom_tess_rings(queue, map, add_sample_positions,
3833 esgs_ring_size, esgs_ring_bo,
3834 gsvs_ring_size, gsvs_ring_bo,
3835 tess_factor_ring_size,
3836 tess_offchip_ring_offset,
3837 tess_offchip_ring_size,
3838 tess_rings_bo);
3839
3840 queue->device->ws->buffer_unmap(descriptor_bo);
3841 }
3842
3843 for(int i = 0; i < 3; ++i) {
3844 struct radeon_cmdbuf *cs = NULL;
3845 cs = queue->device->ws->cs_create(queue->device->ws,
3846 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3847 if (!cs)
3848 goto fail;
3849
3850 dest_cs[i] = cs;
3851
3852 if (scratch_bo)
3853 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3854
3855 /* Emit initial configuration. */
3856 switch (queue->queue_family_index) {
3857 case RADV_QUEUE_GENERAL:
3858 radv_init_graphics_state(cs, queue);
3859 break;
3860 case RADV_QUEUE_COMPUTE:
3861 radv_init_compute_state(cs, queue);
3862 break;
3863 case RADV_QUEUE_TRANSFER:
3864 break;
3865 }
3866
3867 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3868 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3869 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3870
3871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3872 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3873 }
3874
3875 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3876 gsvs_ring_bo, gsvs_ring_size);
3877 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3878 tess_factor_ring_size, tess_rings_bo);
3879 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3880 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3881 compute_scratch_waves, compute_scratch_bo);
3882 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3883 scratch_waves, scratch_bo);
3884
3885 if (gds_bo)
3886 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3887 if (gds_oa_bo)
3888 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3889
3890 if (queue->device->trace_bo)
3891 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3892
3893 if (i == 0) {
3894 si_cs_emit_cache_flush(cs,
3895 queue->device->physical_device->rad_info.chip_class,
3896 NULL, 0,
3897 queue->queue_family_index == RING_COMPUTE &&
3898 queue->device->physical_device->rad_info.chip_class >= GFX7,
3899 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3900 RADV_CMD_FLAG_INV_ICACHE |
3901 RADV_CMD_FLAG_INV_SCACHE |
3902 RADV_CMD_FLAG_INV_VCACHE |
3903 RADV_CMD_FLAG_INV_L2 |
3904 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3905 } else if (i == 1) {
3906 si_cs_emit_cache_flush(cs,
3907 queue->device->physical_device->rad_info.chip_class,
3908 NULL, 0,
3909 queue->queue_family_index == RING_COMPUTE &&
3910 queue->device->physical_device->rad_info.chip_class >= GFX7,
3911 RADV_CMD_FLAG_INV_ICACHE |
3912 RADV_CMD_FLAG_INV_SCACHE |
3913 RADV_CMD_FLAG_INV_VCACHE |
3914 RADV_CMD_FLAG_INV_L2 |
3915 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3916 }
3917
3918 if (!queue->device->ws->cs_finalize(cs))
3919 goto fail;
3920 }
3921
3922 if (queue->initial_full_flush_preamble_cs)
3923 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3924
3925 if (queue->initial_preamble_cs)
3926 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3927
3928 if (queue->continue_preamble_cs)
3929 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3930
3931 queue->initial_full_flush_preamble_cs = dest_cs[0];
3932 queue->initial_preamble_cs = dest_cs[1];
3933 queue->continue_preamble_cs = dest_cs[2];
3934
3935 if (scratch_bo != queue->scratch_bo) {
3936 if (queue->scratch_bo)
3937 queue->device->ws->buffer_destroy(queue->scratch_bo);
3938 queue->scratch_bo = scratch_bo;
3939 }
3940 queue->scratch_size_per_wave = scratch_size_per_wave;
3941 queue->scratch_waves = scratch_waves;
3942
3943 if (compute_scratch_bo != queue->compute_scratch_bo) {
3944 if (queue->compute_scratch_bo)
3945 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3946 queue->compute_scratch_bo = compute_scratch_bo;
3947 }
3948 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3949 queue->compute_scratch_waves = compute_scratch_waves;
3950
3951 if (esgs_ring_bo != queue->esgs_ring_bo) {
3952 if (queue->esgs_ring_bo)
3953 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3954 queue->esgs_ring_bo = esgs_ring_bo;
3955 queue->esgs_ring_size = esgs_ring_size;
3956 }
3957
3958 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3959 if (queue->gsvs_ring_bo)
3960 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3961 queue->gsvs_ring_bo = gsvs_ring_bo;
3962 queue->gsvs_ring_size = gsvs_ring_size;
3963 }
3964
3965 if (tess_rings_bo != queue->tess_rings_bo) {
3966 queue->tess_rings_bo = tess_rings_bo;
3967 queue->has_tess_rings = true;
3968 }
3969
3970 if (gds_bo != queue->gds_bo) {
3971 queue->gds_bo = gds_bo;
3972 queue->has_gds = true;
3973 }
3974
3975 if (gds_oa_bo != queue->gds_oa_bo) {
3976 queue->gds_oa_bo = gds_oa_bo;
3977 queue->has_gds_oa = true;
3978 }
3979
3980 if (descriptor_bo != queue->descriptor_bo) {
3981 if (queue->descriptor_bo)
3982 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3983
3984 queue->descriptor_bo = descriptor_bo;
3985 }
3986
3987 if (add_sample_positions)
3988 queue->has_sample_positions = true;
3989
3990 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3991 *initial_preamble_cs = queue->initial_preamble_cs;
3992 *continue_preamble_cs = queue->continue_preamble_cs;
3993 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3994 *continue_preamble_cs = NULL;
3995 return VK_SUCCESS;
3996 fail:
3997 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3998 if (dest_cs[i])
3999 queue->device->ws->cs_destroy(dest_cs[i]);
4000 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
4001 queue->device->ws->buffer_destroy(descriptor_bo);
4002 if (scratch_bo && scratch_bo != queue->scratch_bo)
4003 queue->device->ws->buffer_destroy(scratch_bo);
4004 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
4005 queue->device->ws->buffer_destroy(compute_scratch_bo);
4006 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
4007 queue->device->ws->buffer_destroy(esgs_ring_bo);
4008 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
4009 queue->device->ws->buffer_destroy(gsvs_ring_bo);
4010 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
4011 queue->device->ws->buffer_destroy(tess_rings_bo);
4012 if (gds_bo && gds_bo != queue->gds_bo)
4013 queue->device->ws->buffer_destroy(gds_bo);
4014 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
4015 queue->device->ws->buffer_destroy(gds_oa_bo);
4016
4017 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4018 }
4019
4020 static VkResult radv_alloc_sem_counts(struct radv_device *device,
4021 struct radv_winsys_sem_counts *counts,
4022 int num_sems,
4023 struct radv_semaphore_part **sems,
4024 const uint64_t *timeline_values,
4025 VkFence _fence,
4026 bool is_signal)
4027 {
4028 int syncobj_idx = 0, sem_idx = 0;
4029
4030 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
4031 return VK_SUCCESS;
4032
4033 for (uint32_t i = 0; i < num_sems; i++) {
4034 switch(sems[i]->kind) {
4035 case RADV_SEMAPHORE_SYNCOBJ:
4036 counts->syncobj_count++;
4037 break;
4038 case RADV_SEMAPHORE_WINSYS:
4039 counts->sem_count++;
4040 break;
4041 case RADV_SEMAPHORE_NONE:
4042 break;
4043 case RADV_SEMAPHORE_TIMELINE:
4044 counts->syncobj_count++;
4045 break;
4046 }
4047 }
4048
4049 if (_fence != VK_NULL_HANDLE) {
4050 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4051 if (fence->temp_syncobj || fence->syncobj)
4052 counts->syncobj_count++;
4053 }
4054
4055 if (counts->syncobj_count) {
4056 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
4057 if (!counts->syncobj)
4058 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4059 }
4060
4061 if (counts->sem_count) {
4062 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
4063 if (!counts->sem) {
4064 free(counts->syncobj);
4065 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4066 }
4067 }
4068
4069 for (uint32_t i = 0; i < num_sems; i++) {
4070 switch(sems[i]->kind) {
4071 case RADV_SEMAPHORE_NONE:
4072 unreachable("Empty semaphore");
4073 break;
4074 case RADV_SEMAPHORE_SYNCOBJ:
4075 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
4076 break;
4077 case RADV_SEMAPHORE_WINSYS:
4078 counts->sem[sem_idx++] = sems[i]->ws_sem;
4079 break;
4080 case RADV_SEMAPHORE_TIMELINE: {
4081 pthread_mutex_lock(&sems[i]->timeline.mutex);
4082 struct radv_timeline_point *point = NULL;
4083 if (is_signal) {
4084 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4085 } else {
4086 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4087 }
4088
4089 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4090
4091 if (point) {
4092 counts->syncobj[syncobj_idx++] = point->syncobj;
4093 } else {
4094 /* Explicitly remove the semaphore so we might not find
4095 * a point later post-submit. */
4096 sems[i] = NULL;
4097 }
4098 break;
4099 }
4100 }
4101 }
4102
4103 if (_fence != VK_NULL_HANDLE) {
4104 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4105 if (fence->temp_syncobj)
4106 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
4107 else if (fence->syncobj)
4108 counts->syncobj[syncobj_idx++] = fence->syncobj;
4109 }
4110
4111 assert(syncobj_idx <= counts->syncobj_count);
4112 counts->syncobj_count = syncobj_idx;
4113
4114 return VK_SUCCESS;
4115 }
4116
4117 static void
4118 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4119 {
4120 free(sem_info->wait.syncobj);
4121 free(sem_info->wait.sem);
4122 free(sem_info->signal.syncobj);
4123 free(sem_info->signal.sem);
4124 }
4125
4126
4127 static void radv_free_temp_syncobjs(struct radv_device *device,
4128 int num_sems,
4129 struct radv_semaphore_part *sems)
4130 {
4131 for (uint32_t i = 0; i < num_sems; i++) {
4132 radv_destroy_semaphore_part(device, sems + i);
4133 }
4134 }
4135
4136 static VkResult
4137 radv_alloc_sem_info(struct radv_device *device,
4138 struct radv_winsys_sem_info *sem_info,
4139 int num_wait_sems,
4140 struct radv_semaphore_part **wait_sems,
4141 const uint64_t *wait_values,
4142 int num_signal_sems,
4143 struct radv_semaphore_part **signal_sems,
4144 const uint64_t *signal_values,
4145 VkFence fence)
4146 {
4147 VkResult ret;
4148 memset(sem_info, 0, sizeof(*sem_info));
4149
4150 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4151 if (ret)
4152 return ret;
4153 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4154 if (ret)
4155 radv_free_sem_info(sem_info);
4156
4157 /* caller can override these */
4158 sem_info->cs_emit_wait = true;
4159 sem_info->cs_emit_signal = true;
4160 return ret;
4161 }
4162
4163 static void
4164 radv_finalize_timelines(struct radv_device *device,
4165 uint32_t num_wait_sems,
4166 struct radv_semaphore_part **wait_sems,
4167 const uint64_t *wait_values,
4168 uint32_t num_signal_sems,
4169 struct radv_semaphore_part **signal_sems,
4170 const uint64_t *signal_values,
4171 struct list_head *processing_list)
4172 {
4173 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4174 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4175 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4176 struct radv_timeline_point *point =
4177 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4178 point->wait_count -= 2;
4179 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4180 }
4181 }
4182 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4183 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4184 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4185 struct radv_timeline_point *point =
4186 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4187 signal_sems[i]->timeline.highest_submitted =
4188 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4189 point->wait_count -= 2;
4190 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4191 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4192 }
4193 }
4194 }
4195
4196 static void
4197 radv_sparse_buffer_bind_memory(struct radv_device *device,
4198 const VkSparseBufferMemoryBindInfo *bind)
4199 {
4200 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4201
4202 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4203 struct radv_device_memory *mem = NULL;
4204
4205 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4206 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4207
4208 device->ws->buffer_virtual_bind(buffer->bo,
4209 bind->pBinds[i].resourceOffset,
4210 bind->pBinds[i].size,
4211 mem ? mem->bo : NULL,
4212 bind->pBinds[i].memoryOffset);
4213 }
4214 }
4215
4216 static void
4217 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4218 const VkSparseImageOpaqueMemoryBindInfo *bind)
4219 {
4220 RADV_FROM_HANDLE(radv_image, image, bind->image);
4221
4222 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4223 struct radv_device_memory *mem = NULL;
4224
4225 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4226 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4227
4228 device->ws->buffer_virtual_bind(image->bo,
4229 bind->pBinds[i].resourceOffset,
4230 bind->pBinds[i].size,
4231 mem ? mem->bo : NULL,
4232 bind->pBinds[i].memoryOffset);
4233 }
4234 }
4235
4236 static VkResult
4237 radv_get_preambles(struct radv_queue *queue,
4238 const VkCommandBuffer *cmd_buffers,
4239 uint32_t cmd_buffer_count,
4240 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4241 struct radeon_cmdbuf **initial_preamble_cs,
4242 struct radeon_cmdbuf **continue_preamble_cs)
4243 {
4244 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4245 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4246 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4247 bool tess_rings_needed = false;
4248 bool gds_needed = false;
4249 bool gds_oa_needed = false;
4250 bool sample_positions_needed = false;
4251
4252 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4254 cmd_buffers[j]);
4255
4256 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4257 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4258 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4259 cmd_buffer->compute_scratch_size_per_wave_needed);
4260 compute_waves_wanted = MAX2(compute_waves_wanted,
4261 cmd_buffer->compute_scratch_waves_wanted);
4262 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4263 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4264 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4265 gds_needed |= cmd_buffer->gds_needed;
4266 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4267 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4268 }
4269
4270 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4271 compute_scratch_size_per_wave, compute_waves_wanted,
4272 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4273 gds_needed, gds_oa_needed, sample_positions_needed,
4274 initial_full_flush_preamble_cs,
4275 initial_preamble_cs, continue_preamble_cs);
4276 }
4277
4278 struct radv_deferred_queue_submission {
4279 struct radv_queue *queue;
4280 VkCommandBuffer *cmd_buffers;
4281 uint32_t cmd_buffer_count;
4282
4283 /* Sparse bindings that happen on a queue. */
4284 VkSparseBufferMemoryBindInfo *buffer_binds;
4285 uint32_t buffer_bind_count;
4286 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4287 uint32_t image_opaque_bind_count;
4288
4289 bool flush_caches;
4290 VkShaderStageFlags wait_dst_stage_mask;
4291 struct radv_semaphore_part **wait_semaphores;
4292 uint32_t wait_semaphore_count;
4293 struct radv_semaphore_part **signal_semaphores;
4294 uint32_t signal_semaphore_count;
4295 VkFence fence;
4296
4297 uint64_t *wait_values;
4298 uint64_t *signal_values;
4299
4300 struct radv_semaphore_part *temporary_semaphore_parts;
4301 uint32_t temporary_semaphore_part_count;
4302
4303 struct list_head queue_pending_list;
4304 uint32_t submission_wait_count;
4305 struct radv_timeline_waiter *wait_nodes;
4306
4307 struct list_head processing_list;
4308 };
4309
4310 struct radv_queue_submission {
4311 const VkCommandBuffer *cmd_buffers;
4312 uint32_t cmd_buffer_count;
4313
4314 /* Sparse bindings that happen on a queue. */
4315 const VkSparseBufferMemoryBindInfo *buffer_binds;
4316 uint32_t buffer_bind_count;
4317 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4318 uint32_t image_opaque_bind_count;
4319
4320 bool flush_caches;
4321 VkPipelineStageFlags wait_dst_stage_mask;
4322 const VkSemaphore *wait_semaphores;
4323 uint32_t wait_semaphore_count;
4324 const VkSemaphore *signal_semaphores;
4325 uint32_t signal_semaphore_count;
4326 VkFence fence;
4327
4328 const uint64_t *wait_values;
4329 uint32_t wait_value_count;
4330 const uint64_t *signal_values;
4331 uint32_t signal_value_count;
4332 };
4333
4334 static VkResult
4335 radv_create_deferred_submission(struct radv_queue *queue,
4336 const struct radv_queue_submission *submission,
4337 struct radv_deferred_queue_submission **out)
4338 {
4339 struct radv_deferred_queue_submission *deferred = NULL;
4340 size_t size = sizeof(struct radv_deferred_queue_submission);
4341
4342 uint32_t temporary_count = 0;
4343 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4344 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4345 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4346 ++temporary_count;
4347 }
4348
4349 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4350 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4351 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4352 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4353 size += temporary_count * sizeof(struct radv_semaphore_part);
4354 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4355 size += submission->wait_value_count * sizeof(uint64_t);
4356 size += submission->signal_value_count * sizeof(uint64_t);
4357 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4358
4359 deferred = calloc(1, size);
4360 if (!deferred)
4361 return VK_ERROR_OUT_OF_HOST_MEMORY;
4362
4363 deferred->queue = queue;
4364
4365 deferred->cmd_buffers = (void*)(deferred + 1);
4366 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4367 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4368 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4369
4370 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4371 deferred->buffer_bind_count = submission->buffer_bind_count;
4372 memcpy(deferred->buffer_binds, submission->buffer_binds,
4373 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4374
4375 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4376 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4377 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4378 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4379
4380 deferred->flush_caches = submission->flush_caches;
4381 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4382
4383 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4384 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4385
4386 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4387 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4388
4389 deferred->fence = submission->fence;
4390
4391 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4392 deferred->temporary_semaphore_part_count = temporary_count;
4393
4394 uint32_t temporary_idx = 0;
4395 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4396 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4397 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4398 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4399 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4400 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4401 ++temporary_idx;
4402 } else
4403 deferred->wait_semaphores[i] = &semaphore->permanent;
4404 }
4405
4406 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4407 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4408 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4409 deferred->signal_semaphores[i] = &semaphore->temporary;
4410 } else {
4411 deferred->signal_semaphores[i] = &semaphore->permanent;
4412 }
4413 }
4414
4415 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4416 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4417 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4418 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4419
4420 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4421 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4422 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4423 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4424
4425 *out = deferred;
4426 return VK_SUCCESS;
4427 }
4428
4429 static void
4430 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4431 struct list_head *processing_list)
4432 {
4433 uint32_t wait_cnt = 0;
4434 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4435 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4436 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4437 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4438 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4439 ++wait_cnt;
4440 waiter->value = submission->wait_values[i];
4441 waiter->submission = submission;
4442 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4443 ++waiter;
4444 }
4445 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4446 }
4447 }
4448
4449 pthread_mutex_lock(&submission->queue->pending_mutex);
4450
4451 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4452 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4453
4454 pthread_mutex_unlock(&submission->queue->pending_mutex);
4455
4456 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4457 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4458 * submission. */
4459 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4460 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4461 list_addtail(&submission->processing_list, processing_list);
4462 }
4463 }
4464
4465 static void
4466 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4467 struct list_head *processing_list)
4468 {
4469 pthread_mutex_lock(&submission->queue->pending_mutex);
4470 list_del(&submission->queue_pending_list);
4471
4472 /* trigger the next submission in the queue. */
4473 if (!list_is_empty(&submission->queue->pending_submissions)) {
4474 struct radv_deferred_queue_submission *next_submission =
4475 list_first_entry(&submission->queue->pending_submissions,
4476 struct radv_deferred_queue_submission,
4477 queue_pending_list);
4478 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4479 list_addtail(&next_submission->processing_list, processing_list);
4480 }
4481 }
4482 pthread_mutex_unlock(&submission->queue->pending_mutex);
4483
4484 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4485 }
4486
4487 static VkResult
4488 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4489 struct list_head *processing_list)
4490 {
4491 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4492 struct radv_queue *queue = submission->queue;
4493 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4494 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4495 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4496 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4497 bool can_patch = true;
4498 uint32_t advance;
4499 struct radv_winsys_sem_info sem_info;
4500 VkResult result;
4501 int ret;
4502 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4503 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4504 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4505
4506 result = radv_get_preambles(queue, submission->cmd_buffers,
4507 submission->cmd_buffer_count,
4508 &initial_preamble_cs,
4509 &initial_flush_preamble_cs,
4510 &continue_preamble_cs);
4511 if (result != VK_SUCCESS)
4512 goto fail;
4513
4514 result = radv_alloc_sem_info(queue->device,
4515 &sem_info,
4516 submission->wait_semaphore_count,
4517 submission->wait_semaphores,
4518 submission->wait_values,
4519 submission->signal_semaphore_count,
4520 submission->signal_semaphores,
4521 submission->signal_values,
4522 submission->fence);
4523 if (result != VK_SUCCESS)
4524 goto fail;
4525
4526 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4527 radv_sparse_buffer_bind_memory(queue->device,
4528 submission->buffer_binds + i);
4529 }
4530
4531 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4532 radv_sparse_image_opaque_bind_memory(queue->device,
4533 submission->image_opaque_binds + i);
4534 }
4535
4536 if (!submission->cmd_buffer_count) {
4537 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4538 &queue->device->empty_cs[queue->queue_family_index],
4539 1, NULL, NULL,
4540 &sem_info, NULL,
4541 false, base_fence);
4542 if (ret) {
4543 radv_loge("failed to submit CS\n");
4544 abort();
4545 }
4546
4547 goto success;
4548 } else {
4549 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4550 (submission->cmd_buffer_count));
4551
4552 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4554 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4555
4556 cs_array[j] = cmd_buffer->cs;
4557 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4558 can_patch = false;
4559
4560 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4561 }
4562
4563 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4564 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4565 const struct radv_winsys_bo_list *bo_list = NULL;
4566
4567 advance = MIN2(max_cs_submission,
4568 submission->cmd_buffer_count - j);
4569
4570 if (queue->device->trace_bo)
4571 *queue->device->trace_id_ptr = 0;
4572
4573 sem_info.cs_emit_wait = j == 0;
4574 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4575
4576 if (unlikely(queue->device->use_global_bo_list)) {
4577 pthread_mutex_lock(&queue->device->bo_list.mutex);
4578 bo_list = &queue->device->bo_list.list;
4579 }
4580
4581 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4582 advance, initial_preamble, continue_preamble_cs,
4583 &sem_info, bo_list,
4584 can_patch, base_fence);
4585
4586 if (unlikely(queue->device->use_global_bo_list))
4587 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4588
4589 if (ret) {
4590 radv_loge("failed to submit CS\n");
4591 abort();
4592 }
4593 if (queue->device->trace_bo) {
4594 radv_check_gpu_hangs(queue, cs_array[j]);
4595 }
4596 }
4597
4598 free(cs_array);
4599 }
4600
4601 success:
4602 radv_free_temp_syncobjs(queue->device,
4603 submission->temporary_semaphore_part_count,
4604 submission->temporary_semaphore_parts);
4605 radv_finalize_timelines(queue->device,
4606 submission->wait_semaphore_count,
4607 submission->wait_semaphores,
4608 submission->wait_values,
4609 submission->signal_semaphore_count,
4610 submission->signal_semaphores,
4611 submission->signal_values,
4612 processing_list);
4613 /* Has to happen after timeline finalization to make sure the
4614 * condition variable is only triggered when timelines and queue have
4615 * been updated. */
4616 radv_queue_submission_update_queue(submission, processing_list);
4617 radv_free_sem_info(&sem_info);
4618 free(submission);
4619 return VK_SUCCESS;
4620
4621 fail:
4622 radv_free_temp_syncobjs(queue->device,
4623 submission->temporary_semaphore_part_count,
4624 submission->temporary_semaphore_parts);
4625 free(submission);
4626 return VK_ERROR_DEVICE_LOST;
4627 }
4628
4629 static VkResult
4630 radv_process_submissions(struct list_head *processing_list)
4631 {
4632 while(!list_is_empty(processing_list)) {
4633 struct radv_deferred_queue_submission *submission =
4634 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4635 list_del(&submission->processing_list);
4636
4637 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4638 if (result != VK_SUCCESS)
4639 return result;
4640 }
4641 return VK_SUCCESS;
4642 }
4643
4644 static VkResult radv_queue_submit(struct radv_queue *queue,
4645 const struct radv_queue_submission *submission)
4646 {
4647 struct radv_deferred_queue_submission *deferred = NULL;
4648
4649 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4650 if (result != VK_SUCCESS)
4651 return result;
4652
4653 struct list_head processing_list;
4654 list_inithead(&processing_list);
4655
4656 radv_queue_enqueue_submission(deferred, &processing_list);
4657 return radv_process_submissions(&processing_list);
4658 }
4659
4660 /* Signals fence as soon as all the work currently put on queue is done. */
4661 static VkResult radv_signal_fence(struct radv_queue *queue,
4662 VkFence fence)
4663 {
4664 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4665 .fence = fence
4666 });
4667 }
4668
4669 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4670 {
4671 return info->commandBufferCount ||
4672 info->waitSemaphoreCount ||
4673 info->signalSemaphoreCount;
4674 }
4675
4676 VkResult radv_QueueSubmit(
4677 VkQueue _queue,
4678 uint32_t submitCount,
4679 const VkSubmitInfo* pSubmits,
4680 VkFence fence)
4681 {
4682 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4683 VkResult result;
4684 uint32_t fence_idx = 0;
4685 bool flushed_caches = false;
4686
4687 if (fence != VK_NULL_HANDLE) {
4688 for (uint32_t i = 0; i < submitCount; ++i)
4689 if (radv_submit_has_effects(pSubmits + i))
4690 fence_idx = i;
4691 } else
4692 fence_idx = UINT32_MAX;
4693
4694 for (uint32_t i = 0; i < submitCount; i++) {
4695 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4696 continue;
4697
4698 VkPipelineStageFlags wait_dst_stage_mask = 0;
4699 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4700 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4701 }
4702
4703 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4704 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4705
4706 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4707 .cmd_buffers = pSubmits[i].pCommandBuffers,
4708 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4709 .wait_dst_stage_mask = wait_dst_stage_mask,
4710 .flush_caches = !flushed_caches,
4711 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4712 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4713 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4714 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4715 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4716 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4717 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4718 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4719 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4720 });
4721 if (result != VK_SUCCESS)
4722 return result;
4723
4724 flushed_caches = true;
4725 }
4726
4727 if (fence != VK_NULL_HANDLE && !submitCount) {
4728 result = radv_signal_fence(queue, fence);
4729 if (result != VK_SUCCESS)
4730 return result;
4731 }
4732
4733 return VK_SUCCESS;
4734 }
4735
4736 VkResult radv_QueueWaitIdle(
4737 VkQueue _queue)
4738 {
4739 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4740
4741 pthread_mutex_lock(&queue->pending_mutex);
4742 while (!list_is_empty(&queue->pending_submissions)) {
4743 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4744 }
4745 pthread_mutex_unlock(&queue->pending_mutex);
4746
4747 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4748 radv_queue_family_to_ring(queue->queue_family_index),
4749 queue->queue_idx);
4750 return VK_SUCCESS;
4751 }
4752
4753 VkResult radv_DeviceWaitIdle(
4754 VkDevice _device)
4755 {
4756 RADV_FROM_HANDLE(radv_device, device, _device);
4757
4758 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4759 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4760 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4761 }
4762 }
4763 return VK_SUCCESS;
4764 }
4765
4766 VkResult radv_EnumerateInstanceExtensionProperties(
4767 const char* pLayerName,
4768 uint32_t* pPropertyCount,
4769 VkExtensionProperties* pProperties)
4770 {
4771 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4772
4773 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4774 if (radv_supported_instance_extensions.extensions[i]) {
4775 vk_outarray_append(&out, prop) {
4776 *prop = radv_instance_extensions[i];
4777 }
4778 }
4779 }
4780
4781 return vk_outarray_status(&out);
4782 }
4783
4784 VkResult radv_EnumerateDeviceExtensionProperties(
4785 VkPhysicalDevice physicalDevice,
4786 const char* pLayerName,
4787 uint32_t* pPropertyCount,
4788 VkExtensionProperties* pProperties)
4789 {
4790 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4791 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4792
4793 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4794 if (device->supported_extensions.extensions[i]) {
4795 vk_outarray_append(&out, prop) {
4796 *prop = radv_device_extensions[i];
4797 }
4798 }
4799 }
4800
4801 return vk_outarray_status(&out);
4802 }
4803
4804 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4805 VkInstance _instance,
4806 const char* pName)
4807 {
4808 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4809 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4810
4811 if (unchecked) {
4812 return radv_lookup_entrypoint_unchecked(pName);
4813 } else {
4814 return radv_lookup_entrypoint_checked(pName,
4815 instance ? instance->apiVersion : 0,
4816 instance ? &instance->enabled_extensions : NULL,
4817 NULL);
4818 }
4819 }
4820
4821 /* The loader wants us to expose a second GetInstanceProcAddr function
4822 * to work around certain LD_PRELOAD issues seen in apps.
4823 */
4824 PUBLIC
4825 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4826 VkInstance instance,
4827 const char* pName);
4828
4829 PUBLIC
4830 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4831 VkInstance instance,
4832 const char* pName)
4833 {
4834 return radv_GetInstanceProcAddr(instance, pName);
4835 }
4836
4837 PUBLIC
4838 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4839 VkInstance _instance,
4840 const char* pName);
4841
4842 PUBLIC
4843 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4844 VkInstance _instance,
4845 const char* pName)
4846 {
4847 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4848
4849 return radv_lookup_physical_device_entrypoint_checked(pName,
4850 instance ? instance->apiVersion : 0,
4851 instance ? &instance->enabled_extensions : NULL);
4852 }
4853
4854 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4855 VkDevice _device,
4856 const char* pName)
4857 {
4858 RADV_FROM_HANDLE(radv_device, device, _device);
4859 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4860
4861 if (unchecked) {
4862 return radv_lookup_entrypoint_unchecked(pName);
4863 } else {
4864 return radv_lookup_entrypoint_checked(pName,
4865 device->instance->apiVersion,
4866 &device->instance->enabled_extensions,
4867 &device->enabled_extensions);
4868 }
4869 }
4870
4871 bool radv_get_memory_fd(struct radv_device *device,
4872 struct radv_device_memory *memory,
4873 int *pFD)
4874 {
4875 struct radeon_bo_metadata metadata;
4876
4877 if (memory->image) {
4878 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
4879 radv_init_metadata(device, memory->image, &metadata);
4880 device->ws->buffer_set_metadata(memory->bo, &metadata);
4881 }
4882
4883 return device->ws->buffer_get_fd(device->ws, memory->bo,
4884 pFD);
4885 }
4886
4887
4888 static void radv_free_memory(struct radv_device *device,
4889 const VkAllocationCallbacks* pAllocator,
4890 struct radv_device_memory *mem)
4891 {
4892 if (mem == NULL)
4893 return;
4894
4895 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4896 if (mem->android_hardware_buffer)
4897 AHardwareBuffer_release(mem->android_hardware_buffer);
4898 #endif
4899
4900 if (mem->bo) {
4901 radv_bo_list_remove(device, mem->bo);
4902 device->ws->buffer_destroy(mem->bo);
4903 mem->bo = NULL;
4904 }
4905
4906 vk_free2(&device->alloc, pAllocator, mem);
4907 }
4908
4909 static VkResult radv_alloc_memory(struct radv_device *device,
4910 const VkMemoryAllocateInfo* pAllocateInfo,
4911 const VkAllocationCallbacks* pAllocator,
4912 VkDeviceMemory* pMem)
4913 {
4914 struct radv_device_memory *mem;
4915 VkResult result;
4916 enum radeon_bo_domain domain;
4917 uint32_t flags = 0;
4918 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
4919
4920 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4921
4922 const VkImportMemoryFdInfoKHR *import_info =
4923 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4924 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4925 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4926 const VkExportMemoryAllocateInfo *export_info =
4927 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4928 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4929 vk_find_struct_const(pAllocateInfo->pNext,
4930 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4931 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4932 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4933
4934 const struct wsi_memory_allocate_info *wsi_info =
4935 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4936
4937 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4938 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4939 /* Apparently, this is allowed */
4940 *pMem = VK_NULL_HANDLE;
4941 return VK_SUCCESS;
4942 }
4943
4944 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
4945 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4946 if (mem == NULL)
4947 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4948
4949 if (wsi_info && wsi_info->implicit_sync)
4950 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4951
4952 if (dedicate_info) {
4953 mem->image = radv_image_from_handle(dedicate_info->image);
4954 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4955 } else {
4956 mem->image = NULL;
4957 mem->buffer = NULL;
4958 }
4959
4960 float priority_float = 0.5;
4961 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4962 vk_find_struct_const(pAllocateInfo->pNext,
4963 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4964 if (priority_ext)
4965 priority_float = priority_ext->priority;
4966
4967 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4968 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4969
4970 mem->user_ptr = NULL;
4971 mem->bo = NULL;
4972
4973 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4974 mem->android_hardware_buffer = NULL;
4975 #endif
4976
4977 if (ahb_import_info) {
4978 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4979 if (result != VK_SUCCESS)
4980 goto fail;
4981 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4982 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4983 if (result != VK_SUCCESS)
4984 goto fail;
4985 } else if (import_info) {
4986 assert(import_info->handleType ==
4987 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4988 import_info->handleType ==
4989 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4990 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4991 priority, NULL);
4992 if (!mem->bo) {
4993 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4994 goto fail;
4995 } else {
4996 close(import_info->fd);
4997 }
4998 } else if (host_ptr_info) {
4999 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5000 assert(radv_is_mem_type_gtt_cached(mem_type_index));
5001 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5002 pAllocateInfo->allocationSize,
5003 priority);
5004 if (!mem->bo) {
5005 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5006 goto fail;
5007 } else {
5008 mem->user_ptr = host_ptr_info->pHostPointer;
5009 }
5010 } else {
5011 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5012 if (radv_is_mem_type_gtt_wc(mem_type_index) ||
5013 radv_is_mem_type_gtt_cached(mem_type_index))
5014 domain = RADEON_DOMAIN_GTT;
5015 else
5016 domain = RADEON_DOMAIN_VRAM;
5017
5018 if (radv_is_mem_type_vram(mem_type_index))
5019 flags |= RADEON_FLAG_NO_CPU_ACCESS;
5020 else
5021 flags |= RADEON_FLAG_CPU_ACCESS;
5022
5023 if (radv_is_mem_type_gtt_wc(mem_type_index))
5024 flags |= RADEON_FLAG_GTT_WC;
5025
5026 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5027 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5028 if (device->use_global_bo_list) {
5029 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5030 }
5031 }
5032
5033 if (radv_is_mem_type_uncached(mem_type_index)) {
5034 assert(device->physical_device->rad_info.has_l2_uncached);
5035 flags |= RADEON_FLAG_VA_UNCACHED;
5036 }
5037
5038 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5039 domain, flags, priority);
5040
5041 if (!mem->bo) {
5042 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5043 goto fail;
5044 }
5045 mem->type_index = mem_type_index;
5046 }
5047
5048 result = radv_bo_list_add(device, mem->bo);
5049 if (result != VK_SUCCESS)
5050 goto fail;
5051
5052 *pMem = radv_device_memory_to_handle(mem);
5053
5054 return VK_SUCCESS;
5055
5056 fail:
5057 radv_free_memory(device, pAllocator,mem);
5058
5059 return result;
5060 }
5061
5062 VkResult radv_AllocateMemory(
5063 VkDevice _device,
5064 const VkMemoryAllocateInfo* pAllocateInfo,
5065 const VkAllocationCallbacks* pAllocator,
5066 VkDeviceMemory* pMem)
5067 {
5068 RADV_FROM_HANDLE(radv_device, device, _device);
5069 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5070 }
5071
5072 void radv_FreeMemory(
5073 VkDevice _device,
5074 VkDeviceMemory _mem,
5075 const VkAllocationCallbacks* pAllocator)
5076 {
5077 RADV_FROM_HANDLE(radv_device, device, _device);
5078 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5079
5080 radv_free_memory(device, pAllocator, mem);
5081 }
5082
5083 VkResult radv_MapMemory(
5084 VkDevice _device,
5085 VkDeviceMemory _memory,
5086 VkDeviceSize offset,
5087 VkDeviceSize size,
5088 VkMemoryMapFlags flags,
5089 void** ppData)
5090 {
5091 RADV_FROM_HANDLE(radv_device, device, _device);
5092 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5093
5094 if (mem == NULL) {
5095 *ppData = NULL;
5096 return VK_SUCCESS;
5097 }
5098
5099 if (mem->user_ptr)
5100 *ppData = mem->user_ptr;
5101 else
5102 *ppData = device->ws->buffer_map(mem->bo);
5103
5104 if (*ppData) {
5105 *ppData += offset;
5106 return VK_SUCCESS;
5107 }
5108
5109 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5110 }
5111
5112 void radv_UnmapMemory(
5113 VkDevice _device,
5114 VkDeviceMemory _memory)
5115 {
5116 RADV_FROM_HANDLE(radv_device, device, _device);
5117 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5118
5119 if (mem == NULL)
5120 return;
5121
5122 if (mem->user_ptr == NULL)
5123 device->ws->buffer_unmap(mem->bo);
5124 }
5125
5126 VkResult radv_FlushMappedMemoryRanges(
5127 VkDevice _device,
5128 uint32_t memoryRangeCount,
5129 const VkMappedMemoryRange* pMemoryRanges)
5130 {
5131 return VK_SUCCESS;
5132 }
5133
5134 VkResult radv_InvalidateMappedMemoryRanges(
5135 VkDevice _device,
5136 uint32_t memoryRangeCount,
5137 const VkMappedMemoryRange* pMemoryRanges)
5138 {
5139 return VK_SUCCESS;
5140 }
5141
5142 void radv_GetBufferMemoryRequirements(
5143 VkDevice _device,
5144 VkBuffer _buffer,
5145 VkMemoryRequirements* pMemoryRequirements)
5146 {
5147 RADV_FROM_HANDLE(radv_device, device, _device);
5148 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5149
5150 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5151
5152 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5153 pMemoryRequirements->alignment = 4096;
5154 else
5155 pMemoryRequirements->alignment = 16;
5156
5157 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5158 }
5159
5160 void radv_GetBufferMemoryRequirements2(
5161 VkDevice device,
5162 const VkBufferMemoryRequirementsInfo2 *pInfo,
5163 VkMemoryRequirements2 *pMemoryRequirements)
5164 {
5165 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5166 &pMemoryRequirements->memoryRequirements);
5167 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5168 switch (ext->sType) {
5169 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5170 VkMemoryDedicatedRequirements *req =
5171 (VkMemoryDedicatedRequirements *) ext;
5172 req->requiresDedicatedAllocation = false;
5173 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5174 break;
5175 }
5176 default:
5177 break;
5178 }
5179 }
5180 }
5181
5182 void radv_GetImageMemoryRequirements(
5183 VkDevice _device,
5184 VkImage _image,
5185 VkMemoryRequirements* pMemoryRequirements)
5186 {
5187 RADV_FROM_HANDLE(radv_device, device, _device);
5188 RADV_FROM_HANDLE(radv_image, image, _image);
5189
5190 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5191
5192 pMemoryRequirements->size = image->size;
5193 pMemoryRequirements->alignment = image->alignment;
5194 }
5195
5196 void radv_GetImageMemoryRequirements2(
5197 VkDevice device,
5198 const VkImageMemoryRequirementsInfo2 *pInfo,
5199 VkMemoryRequirements2 *pMemoryRequirements)
5200 {
5201 radv_GetImageMemoryRequirements(device, pInfo->image,
5202 &pMemoryRequirements->memoryRequirements);
5203
5204 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5205
5206 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5207 switch (ext->sType) {
5208 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5209 VkMemoryDedicatedRequirements *req =
5210 (VkMemoryDedicatedRequirements *) ext;
5211 req->requiresDedicatedAllocation = image->shareable &&
5212 image->tiling != VK_IMAGE_TILING_LINEAR;
5213 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5214 break;
5215 }
5216 default:
5217 break;
5218 }
5219 }
5220 }
5221
5222 void radv_GetImageSparseMemoryRequirements(
5223 VkDevice device,
5224 VkImage image,
5225 uint32_t* pSparseMemoryRequirementCount,
5226 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5227 {
5228 stub();
5229 }
5230
5231 void radv_GetImageSparseMemoryRequirements2(
5232 VkDevice device,
5233 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5234 uint32_t* pSparseMemoryRequirementCount,
5235 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5236 {
5237 stub();
5238 }
5239
5240 void radv_GetDeviceMemoryCommitment(
5241 VkDevice device,
5242 VkDeviceMemory memory,
5243 VkDeviceSize* pCommittedMemoryInBytes)
5244 {
5245 *pCommittedMemoryInBytes = 0;
5246 }
5247
5248 VkResult radv_BindBufferMemory2(VkDevice device,
5249 uint32_t bindInfoCount,
5250 const VkBindBufferMemoryInfo *pBindInfos)
5251 {
5252 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5253 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5254 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5255
5256 if (mem) {
5257 buffer->bo = mem->bo;
5258 buffer->offset = pBindInfos[i].memoryOffset;
5259 } else {
5260 buffer->bo = NULL;
5261 }
5262 }
5263 return VK_SUCCESS;
5264 }
5265
5266 VkResult radv_BindBufferMemory(
5267 VkDevice device,
5268 VkBuffer buffer,
5269 VkDeviceMemory memory,
5270 VkDeviceSize memoryOffset)
5271 {
5272 const VkBindBufferMemoryInfo info = {
5273 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5274 .buffer = buffer,
5275 .memory = memory,
5276 .memoryOffset = memoryOffset
5277 };
5278
5279 return radv_BindBufferMemory2(device, 1, &info);
5280 }
5281
5282 VkResult radv_BindImageMemory2(VkDevice device,
5283 uint32_t bindInfoCount,
5284 const VkBindImageMemoryInfo *pBindInfos)
5285 {
5286 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5287 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5288 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5289
5290 if (mem) {
5291 image->bo = mem->bo;
5292 image->offset = pBindInfos[i].memoryOffset;
5293 } else {
5294 image->bo = NULL;
5295 image->offset = 0;
5296 }
5297 }
5298 return VK_SUCCESS;
5299 }
5300
5301
5302 VkResult radv_BindImageMemory(
5303 VkDevice device,
5304 VkImage image,
5305 VkDeviceMemory memory,
5306 VkDeviceSize memoryOffset)
5307 {
5308 const VkBindImageMemoryInfo info = {
5309 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5310 .image = image,
5311 .memory = memory,
5312 .memoryOffset = memoryOffset
5313 };
5314
5315 return radv_BindImageMemory2(device, 1, &info);
5316 }
5317
5318 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5319 {
5320 return info->bufferBindCount ||
5321 info->imageOpaqueBindCount ||
5322 info->imageBindCount ||
5323 info->waitSemaphoreCount ||
5324 info->signalSemaphoreCount;
5325 }
5326
5327 VkResult radv_QueueBindSparse(
5328 VkQueue _queue,
5329 uint32_t bindInfoCount,
5330 const VkBindSparseInfo* pBindInfo,
5331 VkFence fence)
5332 {
5333 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5334 VkResult result;
5335 uint32_t fence_idx = 0;
5336
5337 if (fence != VK_NULL_HANDLE) {
5338 for (uint32_t i = 0; i < bindInfoCount; ++i)
5339 if (radv_sparse_bind_has_effects(pBindInfo + i))
5340 fence_idx = i;
5341 } else
5342 fence_idx = UINT32_MAX;
5343
5344 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5345 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5346 continue;
5347
5348 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5349 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5350
5351 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5352 .buffer_binds = pBindInfo[i].pBufferBinds,
5353 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5354 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5355 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5356 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5357 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5358 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5359 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5360 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5361 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5362 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5363 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5364 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5365 });
5366
5367 if (result != VK_SUCCESS)
5368 return result;
5369 }
5370
5371 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5372 result = radv_signal_fence(queue, fence);
5373 if (result != VK_SUCCESS)
5374 return result;
5375 }
5376
5377 return VK_SUCCESS;
5378 }
5379
5380 VkResult radv_CreateFence(
5381 VkDevice _device,
5382 const VkFenceCreateInfo* pCreateInfo,
5383 const VkAllocationCallbacks* pAllocator,
5384 VkFence* pFence)
5385 {
5386 RADV_FROM_HANDLE(radv_device, device, _device);
5387 const VkExportFenceCreateInfo *export =
5388 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5389 VkExternalFenceHandleTypeFlags handleTypes =
5390 export ? export->handleTypes : 0;
5391
5392 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5393 sizeof(*fence), 8,
5394 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5395
5396 if (!fence)
5397 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5398
5399 fence->fence_wsi = NULL;
5400 fence->temp_syncobj = 0;
5401 if (device->always_use_syncobj || handleTypes) {
5402 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5403 if (ret) {
5404 vk_free2(&device->alloc, pAllocator, fence);
5405 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5406 }
5407 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5408 device->ws->signal_syncobj(device->ws, fence->syncobj);
5409 }
5410 fence->fence = NULL;
5411 } else {
5412 fence->fence = device->ws->create_fence();
5413 if (!fence->fence) {
5414 vk_free2(&device->alloc, pAllocator, fence);
5415 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5416 }
5417 fence->syncobj = 0;
5418 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5419 device->ws->signal_fence(fence->fence);
5420 }
5421
5422 *pFence = radv_fence_to_handle(fence);
5423
5424 return VK_SUCCESS;
5425 }
5426
5427 void radv_DestroyFence(
5428 VkDevice _device,
5429 VkFence _fence,
5430 const VkAllocationCallbacks* pAllocator)
5431 {
5432 RADV_FROM_HANDLE(radv_device, device, _device);
5433 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5434
5435 if (!fence)
5436 return;
5437
5438 if (fence->temp_syncobj)
5439 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5440 if (fence->syncobj)
5441 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5442 if (fence->fence)
5443 device->ws->destroy_fence(fence->fence);
5444 if (fence->fence_wsi)
5445 fence->fence_wsi->destroy(fence->fence_wsi);
5446 vk_free2(&device->alloc, pAllocator, fence);
5447 }
5448
5449
5450 uint64_t radv_get_current_time(void)
5451 {
5452 struct timespec tv;
5453 clock_gettime(CLOCK_MONOTONIC, &tv);
5454 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5455 }
5456
5457 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5458 {
5459 uint64_t current_time = radv_get_current_time();
5460
5461 timeout = MIN2(UINT64_MAX - current_time, timeout);
5462
5463 return current_time + timeout;
5464 }
5465
5466
5467 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5468 uint32_t fenceCount, const VkFence *pFences)
5469 {
5470 for (uint32_t i = 0; i < fenceCount; ++i) {
5471 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5472 if (fence->fence == NULL || fence->syncobj ||
5473 fence->temp_syncobj || fence->fence_wsi ||
5474 (!device->ws->is_fence_waitable(fence->fence)))
5475 return false;
5476 }
5477 return true;
5478 }
5479
5480 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5481 {
5482 for (uint32_t i = 0; i < fenceCount; ++i) {
5483 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5484 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5485 return false;
5486 }
5487 return true;
5488 }
5489
5490 VkResult radv_WaitForFences(
5491 VkDevice _device,
5492 uint32_t fenceCount,
5493 const VkFence* pFences,
5494 VkBool32 waitAll,
5495 uint64_t timeout)
5496 {
5497 RADV_FROM_HANDLE(radv_device, device, _device);
5498 timeout = radv_get_absolute_timeout(timeout);
5499
5500 if (device->always_use_syncobj &&
5501 radv_all_fences_syncobj(fenceCount, pFences))
5502 {
5503 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5504 if (!handles)
5505 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5506
5507 for (uint32_t i = 0; i < fenceCount; ++i) {
5508 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5509 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5510 }
5511
5512 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5513
5514 free(handles);
5515 return success ? VK_SUCCESS : VK_TIMEOUT;
5516 }
5517
5518 if (!waitAll && fenceCount > 1) {
5519 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5520 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5521 uint32_t wait_count = 0;
5522 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5523 if (!fences)
5524 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5525
5526 for (uint32_t i = 0; i < fenceCount; ++i) {
5527 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5528
5529 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5530 free(fences);
5531 return VK_SUCCESS;
5532 }
5533
5534 fences[wait_count++] = fence->fence;
5535 }
5536
5537 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5538 waitAll, timeout - radv_get_current_time());
5539
5540 free(fences);
5541 return success ? VK_SUCCESS : VK_TIMEOUT;
5542 }
5543
5544 while(radv_get_current_time() <= timeout) {
5545 for (uint32_t i = 0; i < fenceCount; ++i) {
5546 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5547 return VK_SUCCESS;
5548 }
5549 }
5550 return VK_TIMEOUT;
5551 }
5552
5553 for (uint32_t i = 0; i < fenceCount; ++i) {
5554 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5555 bool expired = false;
5556
5557 if (fence->temp_syncobj) {
5558 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5559 return VK_TIMEOUT;
5560 continue;
5561 }
5562
5563 if (fence->syncobj) {
5564 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5565 return VK_TIMEOUT;
5566 continue;
5567 }
5568
5569 if (fence->fence) {
5570 if (!device->ws->is_fence_waitable(fence->fence)) {
5571 while(!device->ws->is_fence_waitable(fence->fence) &&
5572 radv_get_current_time() <= timeout)
5573 /* Do nothing */;
5574 }
5575
5576 expired = device->ws->fence_wait(device->ws,
5577 fence->fence,
5578 true, timeout);
5579 if (!expired)
5580 return VK_TIMEOUT;
5581 }
5582
5583 if (fence->fence_wsi) {
5584 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5585 if (result != VK_SUCCESS)
5586 return result;
5587 }
5588 }
5589
5590 return VK_SUCCESS;
5591 }
5592
5593 VkResult radv_ResetFences(VkDevice _device,
5594 uint32_t fenceCount,
5595 const VkFence *pFences)
5596 {
5597 RADV_FROM_HANDLE(radv_device, device, _device);
5598
5599 for (unsigned i = 0; i < fenceCount; ++i) {
5600 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5601 if (fence->fence)
5602 device->ws->reset_fence(fence->fence);
5603
5604 /* Per spec, we first restore the permanent payload, and then reset, so
5605 * having a temp syncobj should not skip resetting the permanent syncobj. */
5606 if (fence->temp_syncobj) {
5607 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5608 fence->temp_syncobj = 0;
5609 }
5610
5611 if (fence->syncobj) {
5612 device->ws->reset_syncobj(device->ws, fence->syncobj);
5613 }
5614 }
5615
5616 return VK_SUCCESS;
5617 }
5618
5619 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5620 {
5621 RADV_FROM_HANDLE(radv_device, device, _device);
5622 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5623
5624 if (fence->temp_syncobj) {
5625 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5626 return success ? VK_SUCCESS : VK_NOT_READY;
5627 }
5628
5629 if (fence->syncobj) {
5630 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5631 return success ? VK_SUCCESS : VK_NOT_READY;
5632 }
5633
5634 if (fence->fence) {
5635 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5636 return VK_NOT_READY;
5637 }
5638 if (fence->fence_wsi) {
5639 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5640
5641 if (result != VK_SUCCESS) {
5642 if (result == VK_TIMEOUT)
5643 return VK_NOT_READY;
5644 return result;
5645 }
5646 }
5647 return VK_SUCCESS;
5648 }
5649
5650
5651 // Queue semaphore functions
5652
5653 static void
5654 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5655 {
5656 timeline->highest_signaled = value;
5657 timeline->highest_submitted = value;
5658 list_inithead(&timeline->points);
5659 list_inithead(&timeline->free_points);
5660 list_inithead(&timeline->waiters);
5661 pthread_mutex_init(&timeline->mutex, NULL);
5662 }
5663
5664 static void
5665 radv_destroy_timeline(struct radv_device *device,
5666 struct radv_timeline *timeline)
5667 {
5668 list_for_each_entry_safe(struct radv_timeline_point, point,
5669 &timeline->free_points, list) {
5670 list_del(&point->list);
5671 device->ws->destroy_syncobj(device->ws, point->syncobj);
5672 free(point);
5673 }
5674 list_for_each_entry_safe(struct radv_timeline_point, point,
5675 &timeline->points, list) {
5676 list_del(&point->list);
5677 device->ws->destroy_syncobj(device->ws, point->syncobj);
5678 free(point);
5679 }
5680 pthread_mutex_destroy(&timeline->mutex);
5681 }
5682
5683 static void
5684 radv_timeline_gc_locked(struct radv_device *device,
5685 struct radv_timeline *timeline)
5686 {
5687 list_for_each_entry_safe(struct radv_timeline_point, point,
5688 &timeline->points, list) {
5689 if (point->wait_count || point->value > timeline->highest_submitted)
5690 return;
5691
5692 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5693 timeline->highest_signaled = point->value;
5694 list_del(&point->list);
5695 list_add(&point->list, &timeline->free_points);
5696 }
5697 }
5698 }
5699
5700 static struct radv_timeline_point *
5701 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5702 struct radv_timeline *timeline,
5703 uint64_t p)
5704 {
5705 radv_timeline_gc_locked(device, timeline);
5706
5707 if (p <= timeline->highest_signaled)
5708 return NULL;
5709
5710 list_for_each_entry(struct radv_timeline_point, point,
5711 &timeline->points, list) {
5712 if (point->value >= p) {
5713 ++point->wait_count;
5714 return point;
5715 }
5716 }
5717 return NULL;
5718 }
5719
5720 static struct radv_timeline_point *
5721 radv_timeline_add_point_locked(struct radv_device *device,
5722 struct radv_timeline *timeline,
5723 uint64_t p)
5724 {
5725 radv_timeline_gc_locked(device, timeline);
5726
5727 struct radv_timeline_point *ret = NULL;
5728 struct radv_timeline_point *prev = NULL;
5729
5730 if (p <= timeline->highest_signaled)
5731 return NULL;
5732
5733 list_for_each_entry(struct radv_timeline_point, point,
5734 &timeline->points, list) {
5735 if (point->value == p) {
5736 return NULL;
5737 }
5738
5739 if (point->value < p)
5740 prev = point;
5741 }
5742
5743 if (list_is_empty(&timeline->free_points)) {
5744 ret = malloc(sizeof(struct radv_timeline_point));
5745 device->ws->create_syncobj(device->ws, &ret->syncobj);
5746 } else {
5747 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5748 list_del(&ret->list);
5749
5750 device->ws->reset_syncobj(device->ws, ret->syncobj);
5751 }
5752
5753 ret->value = p;
5754 ret->wait_count = 1;
5755
5756 if (prev) {
5757 list_add(&ret->list, &prev->list);
5758 } else {
5759 list_addtail(&ret->list, &timeline->points);
5760 }
5761 return ret;
5762 }
5763
5764
5765 static VkResult
5766 radv_timeline_wait_locked(struct radv_device *device,
5767 struct radv_timeline *timeline,
5768 uint64_t value,
5769 uint64_t abs_timeout)
5770 {
5771 while(timeline->highest_submitted < value) {
5772 struct timespec abstime;
5773 timespec_from_nsec(&abstime, abs_timeout);
5774
5775 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5776
5777 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5778 return VK_TIMEOUT;
5779 }
5780
5781 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5782 if (!point)
5783 return VK_SUCCESS;
5784
5785 pthread_mutex_unlock(&timeline->mutex);
5786
5787 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5788
5789 pthread_mutex_lock(&timeline->mutex);
5790 point->wait_count--;
5791 return success ? VK_SUCCESS : VK_TIMEOUT;
5792 }
5793
5794 static void
5795 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5796 struct list_head *processing_list)
5797 {
5798 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5799 &timeline->waiters, list) {
5800 if (waiter->value > timeline->highest_submitted)
5801 continue;
5802
5803 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5804 list_addtail(&waiter->submission->processing_list, processing_list);
5805 }
5806 list_del(&waiter->list);
5807 }
5808 }
5809
5810 static
5811 void radv_destroy_semaphore_part(struct radv_device *device,
5812 struct radv_semaphore_part *part)
5813 {
5814 switch(part->kind) {
5815 case RADV_SEMAPHORE_NONE:
5816 break;
5817 case RADV_SEMAPHORE_WINSYS:
5818 device->ws->destroy_sem(part->ws_sem);
5819 break;
5820 case RADV_SEMAPHORE_TIMELINE:
5821 radv_destroy_timeline(device, &part->timeline);
5822 break;
5823 case RADV_SEMAPHORE_SYNCOBJ:
5824 device->ws->destroy_syncobj(device->ws, part->syncobj);
5825 break;
5826 }
5827 part->kind = RADV_SEMAPHORE_NONE;
5828 }
5829
5830 static VkSemaphoreTypeKHR
5831 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5832 {
5833 const VkSemaphoreTypeCreateInfo *type_info =
5834 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
5835
5836 if (!type_info)
5837 return VK_SEMAPHORE_TYPE_BINARY;
5838
5839 if (initial_value)
5840 *initial_value = type_info->initialValue;
5841 return type_info->semaphoreType;
5842 }
5843
5844 VkResult radv_CreateSemaphore(
5845 VkDevice _device,
5846 const VkSemaphoreCreateInfo* pCreateInfo,
5847 const VkAllocationCallbacks* pAllocator,
5848 VkSemaphore* pSemaphore)
5849 {
5850 RADV_FROM_HANDLE(radv_device, device, _device);
5851 const VkExportSemaphoreCreateInfo *export =
5852 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5853 VkExternalSemaphoreHandleTypeFlags handleTypes =
5854 export ? export->handleTypes : 0;
5855 uint64_t initial_value = 0;
5856 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5857
5858 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
5859 sizeof(*sem), 8,
5860 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5861 if (!sem)
5862 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5863
5864 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5865 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5866
5867 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
5868 radv_create_timeline(&sem->permanent.timeline, initial_value);
5869 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5870 } else if (device->always_use_syncobj || handleTypes) {
5871 assert (device->physical_device->rad_info.has_syncobj);
5872 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
5873 if (ret) {
5874 vk_free2(&device->alloc, pAllocator, sem);
5875 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5876 }
5877 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5878 } else {
5879 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5880 if (!sem->permanent.ws_sem) {
5881 vk_free2(&device->alloc, pAllocator, sem);
5882 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5883 }
5884 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5885 }
5886
5887 *pSemaphore = radv_semaphore_to_handle(sem);
5888 return VK_SUCCESS;
5889 }
5890
5891 void radv_DestroySemaphore(
5892 VkDevice _device,
5893 VkSemaphore _semaphore,
5894 const VkAllocationCallbacks* pAllocator)
5895 {
5896 RADV_FROM_HANDLE(radv_device, device, _device);
5897 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5898 if (!_semaphore)
5899 return;
5900
5901 radv_destroy_semaphore_part(device, &sem->temporary);
5902 radv_destroy_semaphore_part(device, &sem->permanent);
5903 vk_free2(&device->alloc, pAllocator, sem);
5904 }
5905
5906 VkResult
5907 radv_GetSemaphoreCounterValue(VkDevice _device,
5908 VkSemaphore _semaphore,
5909 uint64_t* pValue)
5910 {
5911 RADV_FROM_HANDLE(radv_device, device, _device);
5912 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5913
5914 struct radv_semaphore_part *part =
5915 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5916
5917 switch (part->kind) {
5918 case RADV_SEMAPHORE_TIMELINE: {
5919 pthread_mutex_lock(&part->timeline.mutex);
5920 radv_timeline_gc_locked(device, &part->timeline);
5921 *pValue = part->timeline.highest_signaled;
5922 pthread_mutex_unlock(&part->timeline.mutex);
5923 return VK_SUCCESS;
5924 }
5925 case RADV_SEMAPHORE_NONE:
5926 case RADV_SEMAPHORE_SYNCOBJ:
5927 case RADV_SEMAPHORE_WINSYS:
5928 unreachable("Invalid semaphore type");
5929 }
5930 unreachable("Unhandled semaphore type");
5931 }
5932
5933
5934 static VkResult
5935 radv_wait_timelines(struct radv_device *device,
5936 const VkSemaphoreWaitInfo* pWaitInfo,
5937 uint64_t abs_timeout)
5938 {
5939 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5940 for (;;) {
5941 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5942 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5943 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5944 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5945 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5946
5947 if (result == VK_SUCCESS)
5948 return VK_SUCCESS;
5949 }
5950 if (radv_get_current_time() > abs_timeout)
5951 return VK_TIMEOUT;
5952 }
5953 }
5954
5955 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5956 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5957 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5958 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5959 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5960
5961 if (result != VK_SUCCESS)
5962 return result;
5963 }
5964 return VK_SUCCESS;
5965 }
5966 VkResult
5967 radv_WaitSemaphores(VkDevice _device,
5968 const VkSemaphoreWaitInfo* pWaitInfo,
5969 uint64_t timeout)
5970 {
5971 RADV_FROM_HANDLE(radv_device, device, _device);
5972 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5973 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5974 }
5975
5976 VkResult
5977 radv_SignalSemaphore(VkDevice _device,
5978 const VkSemaphoreSignalInfo* pSignalInfo)
5979 {
5980 RADV_FROM_HANDLE(radv_device, device, _device);
5981 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5982
5983 struct radv_semaphore_part *part =
5984 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5985
5986 switch(part->kind) {
5987 case RADV_SEMAPHORE_TIMELINE: {
5988 pthread_mutex_lock(&part->timeline.mutex);
5989 radv_timeline_gc_locked(device, &part->timeline);
5990 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5991 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5992
5993 struct list_head processing_list;
5994 list_inithead(&processing_list);
5995 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5996 pthread_mutex_unlock(&part->timeline.mutex);
5997
5998 return radv_process_submissions(&processing_list);
5999 }
6000 case RADV_SEMAPHORE_NONE:
6001 case RADV_SEMAPHORE_SYNCOBJ:
6002 case RADV_SEMAPHORE_WINSYS:
6003 unreachable("Invalid semaphore type");
6004 }
6005 return VK_SUCCESS;
6006 }
6007
6008
6009
6010 VkResult radv_CreateEvent(
6011 VkDevice _device,
6012 const VkEventCreateInfo* pCreateInfo,
6013 const VkAllocationCallbacks* pAllocator,
6014 VkEvent* pEvent)
6015 {
6016 RADV_FROM_HANDLE(radv_device, device, _device);
6017 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
6018 sizeof(*event), 8,
6019 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6020
6021 if (!event)
6022 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6023
6024 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6025 RADEON_DOMAIN_GTT,
6026 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6027 RADV_BO_PRIORITY_FENCE);
6028 if (!event->bo) {
6029 vk_free2(&device->alloc, pAllocator, event);
6030 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6031 }
6032
6033 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6034
6035 *pEvent = radv_event_to_handle(event);
6036
6037 return VK_SUCCESS;
6038 }
6039
6040 void radv_DestroyEvent(
6041 VkDevice _device,
6042 VkEvent _event,
6043 const VkAllocationCallbacks* pAllocator)
6044 {
6045 RADV_FROM_HANDLE(radv_device, device, _device);
6046 RADV_FROM_HANDLE(radv_event, event, _event);
6047
6048 if (!event)
6049 return;
6050 device->ws->buffer_destroy(event->bo);
6051 vk_free2(&device->alloc, pAllocator, event);
6052 }
6053
6054 VkResult radv_GetEventStatus(
6055 VkDevice _device,
6056 VkEvent _event)
6057 {
6058 RADV_FROM_HANDLE(radv_event, event, _event);
6059
6060 if (*event->map == 1)
6061 return VK_EVENT_SET;
6062 return VK_EVENT_RESET;
6063 }
6064
6065 VkResult radv_SetEvent(
6066 VkDevice _device,
6067 VkEvent _event)
6068 {
6069 RADV_FROM_HANDLE(radv_event, event, _event);
6070 *event->map = 1;
6071
6072 return VK_SUCCESS;
6073 }
6074
6075 VkResult radv_ResetEvent(
6076 VkDevice _device,
6077 VkEvent _event)
6078 {
6079 RADV_FROM_HANDLE(radv_event, event, _event);
6080 *event->map = 0;
6081
6082 return VK_SUCCESS;
6083 }
6084
6085 VkResult radv_CreateBuffer(
6086 VkDevice _device,
6087 const VkBufferCreateInfo* pCreateInfo,
6088 const VkAllocationCallbacks* pAllocator,
6089 VkBuffer* pBuffer)
6090 {
6091 RADV_FROM_HANDLE(radv_device, device, _device);
6092 struct radv_buffer *buffer;
6093
6094 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6095
6096 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
6097 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6098 if (buffer == NULL)
6099 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6100
6101 buffer->size = pCreateInfo->size;
6102 buffer->usage = pCreateInfo->usage;
6103 buffer->bo = NULL;
6104 buffer->offset = 0;
6105 buffer->flags = pCreateInfo->flags;
6106
6107 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6108 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6109
6110 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6111 buffer->bo = device->ws->buffer_create(device->ws,
6112 align64(buffer->size, 4096),
6113 4096, 0, RADEON_FLAG_VIRTUAL,
6114 RADV_BO_PRIORITY_VIRTUAL);
6115 if (!buffer->bo) {
6116 vk_free2(&device->alloc, pAllocator, buffer);
6117 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6118 }
6119 }
6120
6121 *pBuffer = radv_buffer_to_handle(buffer);
6122
6123 return VK_SUCCESS;
6124 }
6125
6126 void radv_DestroyBuffer(
6127 VkDevice _device,
6128 VkBuffer _buffer,
6129 const VkAllocationCallbacks* pAllocator)
6130 {
6131 RADV_FROM_HANDLE(radv_device, device, _device);
6132 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6133
6134 if (!buffer)
6135 return;
6136
6137 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
6138 device->ws->buffer_destroy(buffer->bo);
6139
6140 vk_free2(&device->alloc, pAllocator, buffer);
6141 }
6142
6143 VkDeviceAddress radv_GetBufferDeviceAddress(
6144 VkDevice device,
6145 const VkBufferDeviceAddressInfo* pInfo)
6146 {
6147 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6148 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6149 }
6150
6151
6152 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6153 const VkBufferDeviceAddressInfo* pInfo)
6154 {
6155 return 0;
6156 }
6157
6158 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6159 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6160 {
6161 return 0;
6162 }
6163
6164 static inline unsigned
6165 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6166 {
6167 if (stencil)
6168 return plane->surface.u.legacy.stencil_tiling_index[level];
6169 else
6170 return plane->surface.u.legacy.tiling_index[level];
6171 }
6172
6173 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6174 {
6175 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6176 }
6177
6178 static uint32_t
6179 radv_init_dcc_control_reg(struct radv_device *device,
6180 struct radv_image_view *iview)
6181 {
6182 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6183 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6184 unsigned max_compressed_block_size;
6185 unsigned independent_128b_blocks;
6186 unsigned independent_64b_blocks;
6187
6188 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6189 return 0;
6190
6191 if (!device->physical_device->rad_info.has_dedicated_vram) {
6192 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6193 * dGPU and 64 for APU because all of our APUs to date use
6194 * DIMMs which have a request granularity size of 64B while all
6195 * other chips have a 32B request size.
6196 */
6197 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6198 }
6199
6200 if (device->physical_device->rad_info.chip_class >= GFX10) {
6201 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6202 independent_64b_blocks = 0;
6203 independent_128b_blocks = 1;
6204 } else {
6205 independent_128b_blocks = 0;
6206
6207 if (iview->image->info.samples > 1) {
6208 if (iview->image->planes[0].surface.bpe == 1)
6209 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6210 else if (iview->image->planes[0].surface.bpe == 2)
6211 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6212 }
6213
6214 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6215 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6216 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6217 /* If this DCC image is potentially going to be used in texture
6218 * fetches, we need some special settings.
6219 */
6220 independent_64b_blocks = 1;
6221 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6222 } else {
6223 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6224 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6225 * big as possible for better compression state.
6226 */
6227 independent_64b_blocks = 0;
6228 max_compressed_block_size = max_uncompressed_block_size;
6229 }
6230 }
6231
6232 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6233 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6234 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6235 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6236 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6237 }
6238
6239 void
6240 radv_initialise_color_surface(struct radv_device *device,
6241 struct radv_color_buffer_info *cb,
6242 struct radv_image_view *iview)
6243 {
6244 const struct vk_format_description *desc;
6245 unsigned ntype, format, swap, endian;
6246 unsigned blend_clamp = 0, blend_bypass = 0;
6247 uint64_t va;
6248 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6249 const struct radeon_surf *surf = &plane->surface;
6250
6251 desc = vk_format_description(iview->vk_format);
6252
6253 memset(cb, 0, sizeof(*cb));
6254
6255 /* Intensity is implemented as Red, so treat it that way. */
6256 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6257
6258 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6259
6260 cb->cb_color_base = va >> 8;
6261
6262 if (device->physical_device->rad_info.chip_class >= GFX9) {
6263 struct gfx9_surf_meta_flags meta;
6264 if (iview->image->dcc_offset)
6265 meta = surf->u.gfx9.dcc;
6266 else
6267 meta = surf->u.gfx9.cmask;
6268
6269 if (device->physical_device->rad_info.chip_class >= GFX10) {
6270 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6271 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6272 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6273 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6274 } else {
6275 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6276 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6277 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6278 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6279 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6280 }
6281
6282 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6283 cb->cb_color_base |= surf->tile_swizzle;
6284 } else {
6285 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6286 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6287
6288 cb->cb_color_base += level_info->offset >> 8;
6289 if (level_info->mode == RADEON_SURF_MODE_2D)
6290 cb->cb_color_base |= surf->tile_swizzle;
6291
6292 pitch_tile_max = level_info->nblk_x / 8 - 1;
6293 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6294 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6295
6296 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6297 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6298 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6299
6300 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6301
6302 if (radv_image_has_fmask(iview->image)) {
6303 if (device->physical_device->rad_info.chip_class >= GFX7)
6304 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6305 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6306 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6307 } else {
6308 /* This must be set for fast clear to work without FMASK. */
6309 if (device->physical_device->rad_info.chip_class >= GFX7)
6310 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6311 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6312 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6313 }
6314 }
6315
6316 /* CMASK variables */
6317 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6318 va += iview->image->cmask_offset;
6319 cb->cb_color_cmask = va >> 8;
6320
6321 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6322 va += iview->image->dcc_offset;
6323
6324 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6325 device->physical_device->rad_info.chip_class <= GFX8)
6326 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6327
6328 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6329 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6330
6331 cb->cb_dcc_base = va >> 8;
6332 cb->cb_dcc_base |= dcc_tile_swizzle;
6333
6334 /* GFX10 field has the same base shift as the GFX6 field. */
6335 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6336 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6337 S_028C6C_SLICE_MAX_GFX10(max_slice);
6338
6339 if (iview->image->info.samples > 1) {
6340 unsigned log_samples = util_logbase2(iview->image->info.samples);
6341
6342 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6343 S_028C74_NUM_FRAGMENTS(log_samples);
6344 }
6345
6346 if (radv_image_has_fmask(iview->image)) {
6347 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6348 cb->cb_color_fmask = va >> 8;
6349 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6350 } else {
6351 cb->cb_color_fmask = cb->cb_color_base;
6352 }
6353
6354 ntype = radv_translate_color_numformat(iview->vk_format,
6355 desc,
6356 vk_format_get_first_non_void_channel(iview->vk_format));
6357 format = radv_translate_colorformat(iview->vk_format);
6358 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6359 radv_finishme("Illegal color\n");
6360 swap = radv_translate_colorswap(iview->vk_format, false);
6361 endian = radv_colorformat_endian_swap(format);
6362
6363 /* blend clamp should be set for all NORM/SRGB types */
6364 if (ntype == V_028C70_NUMBER_UNORM ||
6365 ntype == V_028C70_NUMBER_SNORM ||
6366 ntype == V_028C70_NUMBER_SRGB)
6367 blend_clamp = 1;
6368
6369 /* set blend bypass according to docs if SINT/UINT or
6370 8/24 COLOR variants */
6371 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6372 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6373 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6374 blend_clamp = 0;
6375 blend_bypass = 1;
6376 }
6377 #if 0
6378 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6379 (format == V_028C70_COLOR_8 ||
6380 format == V_028C70_COLOR_8_8 ||
6381 format == V_028C70_COLOR_8_8_8_8))
6382 ->color_is_int8 = true;
6383 #endif
6384 cb->cb_color_info = S_028C70_FORMAT(format) |
6385 S_028C70_COMP_SWAP(swap) |
6386 S_028C70_BLEND_CLAMP(blend_clamp) |
6387 S_028C70_BLEND_BYPASS(blend_bypass) |
6388 S_028C70_SIMPLE_FLOAT(1) |
6389 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6390 ntype != V_028C70_NUMBER_SNORM &&
6391 ntype != V_028C70_NUMBER_SRGB &&
6392 format != V_028C70_COLOR_8_24 &&
6393 format != V_028C70_COLOR_24_8) |
6394 S_028C70_NUMBER_TYPE(ntype) |
6395 S_028C70_ENDIAN(endian);
6396 if (radv_image_has_fmask(iview->image)) {
6397 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6398 if (device->physical_device->rad_info.chip_class == GFX6) {
6399 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6400 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6401 }
6402
6403 if (radv_image_is_tc_compat_cmask(iview->image)) {
6404 /* Allow the texture block to read FMASK directly
6405 * without decompressing it. This bit must be cleared
6406 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6407 * otherwise the operation doesn't happen.
6408 */
6409 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6410
6411 /* Set CMASK into a tiling format that allows the
6412 * texture block to read it.
6413 */
6414 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6415 }
6416 }
6417
6418 if (radv_image_has_cmask(iview->image) &&
6419 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6420 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6421
6422 if (radv_dcc_enabled(iview->image, iview->base_mip))
6423 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6424
6425 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6426
6427 /* This must be set for fast clear to work without FMASK. */
6428 if (!radv_image_has_fmask(iview->image) &&
6429 device->physical_device->rad_info.chip_class == GFX6) {
6430 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6431 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6432 }
6433
6434 if (device->physical_device->rad_info.chip_class >= GFX9) {
6435 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6436
6437 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6438 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6439 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6440 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6441
6442 if (device->physical_device->rad_info.chip_class >= GFX10) {
6443 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6444
6445 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6446 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6447 S_028EE0_RESOURCE_LEVEL(1);
6448 } else {
6449 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6450 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6451 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6452 }
6453
6454 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6455 S_028C68_MIP0_HEIGHT(height - 1) |
6456 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6457 }
6458 }
6459
6460 static unsigned
6461 radv_calc_decompress_on_z_planes(struct radv_device *device,
6462 struct radv_image_view *iview)
6463 {
6464 unsigned max_zplanes = 0;
6465
6466 assert(radv_image_is_tc_compat_htile(iview->image));
6467
6468 if (device->physical_device->rad_info.chip_class >= GFX9) {
6469 /* Default value for 32-bit depth surfaces. */
6470 max_zplanes = 4;
6471
6472 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6473 iview->image->info.samples > 1)
6474 max_zplanes = 2;
6475
6476 max_zplanes = max_zplanes + 1;
6477 } else {
6478 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6479 /* Do not enable Z plane compression for 16-bit depth
6480 * surfaces because isn't supported on GFX8. Only
6481 * 32-bit depth surfaces are supported by the hardware.
6482 * This allows to maintain shader compatibility and to
6483 * reduce the number of depth decompressions.
6484 */
6485 max_zplanes = 1;
6486 } else {
6487 if (iview->image->info.samples <= 1)
6488 max_zplanes = 5;
6489 else if (iview->image->info.samples <= 4)
6490 max_zplanes = 3;
6491 else
6492 max_zplanes = 2;
6493 }
6494 }
6495
6496 return max_zplanes;
6497 }
6498
6499 void
6500 radv_initialise_ds_surface(struct radv_device *device,
6501 struct radv_ds_buffer_info *ds,
6502 struct radv_image_view *iview)
6503 {
6504 unsigned level = iview->base_mip;
6505 unsigned format, stencil_format;
6506 uint64_t va, s_offs, z_offs;
6507 bool stencil_only = false;
6508 const struct radv_image_plane *plane = &iview->image->planes[0];
6509 const struct radeon_surf *surf = &plane->surface;
6510
6511 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6512
6513 memset(ds, 0, sizeof(*ds));
6514 switch (iview->image->vk_format) {
6515 case VK_FORMAT_D24_UNORM_S8_UINT:
6516 case VK_FORMAT_X8_D24_UNORM_PACK32:
6517 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6518 ds->offset_scale = 2.0f;
6519 break;
6520 case VK_FORMAT_D16_UNORM:
6521 case VK_FORMAT_D16_UNORM_S8_UINT:
6522 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6523 ds->offset_scale = 4.0f;
6524 break;
6525 case VK_FORMAT_D32_SFLOAT:
6526 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6527 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6528 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6529 ds->offset_scale = 1.0f;
6530 break;
6531 case VK_FORMAT_S8_UINT:
6532 stencil_only = true;
6533 break;
6534 default:
6535 break;
6536 }
6537
6538 format = radv_translate_dbformat(iview->image->vk_format);
6539 stencil_format = surf->has_stencil ?
6540 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6541
6542 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6543 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6544 S_028008_SLICE_MAX(max_slice);
6545 if (device->physical_device->rad_info.chip_class >= GFX10) {
6546 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6547 S_028008_SLICE_MAX_HI(max_slice >> 11);
6548 }
6549
6550 ds->db_htile_data_base = 0;
6551 ds->db_htile_surface = 0;
6552
6553 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6554 s_offs = z_offs = va;
6555
6556 if (device->physical_device->rad_info.chip_class >= GFX9) {
6557 assert(surf->u.gfx9.surf_offset == 0);
6558 s_offs += surf->u.gfx9.stencil_offset;
6559
6560 ds->db_z_info = S_028038_FORMAT(format) |
6561 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6562 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6563 S_028038_MAXMIP(iview->image->info.levels - 1) |
6564 S_028038_ZRANGE_PRECISION(1);
6565 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6566 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6567
6568 if (device->physical_device->rad_info.chip_class == GFX9) {
6569 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6570 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6571 }
6572
6573 ds->db_depth_view |= S_028008_MIPID(level);
6574 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6575 S_02801C_Y_MAX(iview->image->info.height - 1);
6576
6577 if (radv_htile_enabled(iview->image, level)) {
6578 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6579
6580 if (radv_image_is_tc_compat_htile(iview->image)) {
6581 unsigned max_zplanes =
6582 radv_calc_decompress_on_z_planes(device, iview);
6583
6584 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6585
6586 if (device->physical_device->rad_info.chip_class >= GFX10) {
6587 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6588 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6589 } else {
6590 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6591 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6592 }
6593 }
6594
6595 if (!surf->has_stencil)
6596 /* Use all of the htile_buffer for depth if there's no stencil. */
6597 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6598 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6599 iview->image->htile_offset;
6600 ds->db_htile_data_base = va >> 8;
6601 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6602 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6603
6604 if (device->physical_device->rad_info.chip_class == GFX9) {
6605 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6606 }
6607 }
6608 } else {
6609 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6610
6611 if (stencil_only)
6612 level_info = &surf->u.legacy.stencil_level[level];
6613
6614 z_offs += surf->u.legacy.level[level].offset;
6615 s_offs += surf->u.legacy.stencil_level[level].offset;
6616
6617 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6618 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6619 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6620
6621 if (iview->image->info.samples > 1)
6622 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6623
6624 if (device->physical_device->rad_info.chip_class >= GFX7) {
6625 struct radeon_info *info = &device->physical_device->rad_info;
6626 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6627 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6628 unsigned macro_index = surf->u.legacy.macro_tile_index;
6629 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6630 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6631 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6632
6633 if (stencil_only)
6634 tile_mode = stencil_tile_mode;
6635
6636 ds->db_depth_info |=
6637 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6638 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6639 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6640 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6641 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6642 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6643 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6644 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6645 } else {
6646 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6647 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6648 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6649 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6650 if (stencil_only)
6651 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6652 }
6653
6654 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6655 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6656 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6657
6658 if (radv_htile_enabled(iview->image, level)) {
6659 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6660
6661 if (!surf->has_stencil &&
6662 !radv_image_is_tc_compat_htile(iview->image))
6663 /* Use all of the htile_buffer for depth if there's no stencil. */
6664 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6665
6666 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6667 iview->image->htile_offset;
6668 ds->db_htile_data_base = va >> 8;
6669 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6670
6671 if (radv_image_is_tc_compat_htile(iview->image)) {
6672 unsigned max_zplanes =
6673 radv_calc_decompress_on_z_planes(device, iview);
6674
6675 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6676 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6677 }
6678 }
6679 }
6680
6681 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6682 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6683 }
6684
6685 VkResult radv_CreateFramebuffer(
6686 VkDevice _device,
6687 const VkFramebufferCreateInfo* pCreateInfo,
6688 const VkAllocationCallbacks* pAllocator,
6689 VkFramebuffer* pFramebuffer)
6690 {
6691 RADV_FROM_HANDLE(radv_device, device, _device);
6692 struct radv_framebuffer *framebuffer;
6693 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6694 vk_find_struct_const(pCreateInfo->pNext,
6695 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6696
6697 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6698
6699 size_t size = sizeof(*framebuffer);
6700 if (!imageless_create_info)
6701 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6702 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6703 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6704 if (framebuffer == NULL)
6705 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6706
6707 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6708 framebuffer->width = pCreateInfo->width;
6709 framebuffer->height = pCreateInfo->height;
6710 framebuffer->layers = pCreateInfo->layers;
6711 if (imageless_create_info) {
6712 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6713 const VkFramebufferAttachmentImageInfo *attachment =
6714 imageless_create_info->pAttachmentImageInfos + i;
6715 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6716 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6717 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6718 }
6719 } else {
6720 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6721 VkImageView _iview = pCreateInfo->pAttachments[i];
6722 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6723 framebuffer->attachments[i] = iview;
6724 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6725 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6726 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6727 }
6728 }
6729
6730 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6731 return VK_SUCCESS;
6732 }
6733
6734 void radv_DestroyFramebuffer(
6735 VkDevice _device,
6736 VkFramebuffer _fb,
6737 const VkAllocationCallbacks* pAllocator)
6738 {
6739 RADV_FROM_HANDLE(radv_device, device, _device);
6740 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6741
6742 if (!fb)
6743 return;
6744 vk_free2(&device->alloc, pAllocator, fb);
6745 }
6746
6747 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6748 {
6749 switch (address_mode) {
6750 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6751 return V_008F30_SQ_TEX_WRAP;
6752 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6753 return V_008F30_SQ_TEX_MIRROR;
6754 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6755 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6756 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6757 return V_008F30_SQ_TEX_CLAMP_BORDER;
6758 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6759 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6760 default:
6761 unreachable("illegal tex wrap mode");
6762 break;
6763 }
6764 }
6765
6766 static unsigned
6767 radv_tex_compare(VkCompareOp op)
6768 {
6769 switch (op) {
6770 case VK_COMPARE_OP_NEVER:
6771 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6772 case VK_COMPARE_OP_LESS:
6773 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6774 case VK_COMPARE_OP_EQUAL:
6775 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6776 case VK_COMPARE_OP_LESS_OR_EQUAL:
6777 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6778 case VK_COMPARE_OP_GREATER:
6779 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6780 case VK_COMPARE_OP_NOT_EQUAL:
6781 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6782 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6783 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6784 case VK_COMPARE_OP_ALWAYS:
6785 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6786 default:
6787 unreachable("illegal compare mode");
6788 break;
6789 }
6790 }
6791
6792 static unsigned
6793 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6794 {
6795 switch (filter) {
6796 case VK_FILTER_NEAREST:
6797 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6798 V_008F38_SQ_TEX_XY_FILTER_POINT);
6799 case VK_FILTER_LINEAR:
6800 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6801 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6802 case VK_FILTER_CUBIC_IMG:
6803 default:
6804 fprintf(stderr, "illegal texture filter");
6805 return 0;
6806 }
6807 }
6808
6809 static unsigned
6810 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6811 {
6812 switch (mode) {
6813 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6814 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6815 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6816 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6817 default:
6818 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6819 }
6820 }
6821
6822 static unsigned
6823 radv_tex_bordercolor(VkBorderColor bcolor)
6824 {
6825 switch (bcolor) {
6826 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6827 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6828 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6829 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6830 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6831 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6832 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6833 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6834 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6835 default:
6836 break;
6837 }
6838 return 0;
6839 }
6840
6841 static unsigned
6842 radv_tex_aniso_filter(unsigned filter)
6843 {
6844 if (filter < 2)
6845 return 0;
6846 if (filter < 4)
6847 return 1;
6848 if (filter < 8)
6849 return 2;
6850 if (filter < 16)
6851 return 3;
6852 return 4;
6853 }
6854
6855 static unsigned
6856 radv_tex_filter_mode(VkSamplerReductionMode mode)
6857 {
6858 switch (mode) {
6859 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6860 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6861 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6862 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6863 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6864 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6865 default:
6866 break;
6867 }
6868 return 0;
6869 }
6870
6871 static uint32_t
6872 radv_get_max_anisotropy(struct radv_device *device,
6873 const VkSamplerCreateInfo *pCreateInfo)
6874 {
6875 if (device->force_aniso >= 0)
6876 return device->force_aniso;
6877
6878 if (pCreateInfo->anisotropyEnable &&
6879 pCreateInfo->maxAnisotropy > 1.0f)
6880 return (uint32_t)pCreateInfo->maxAnisotropy;
6881
6882 return 0;
6883 }
6884
6885 static void
6886 radv_init_sampler(struct radv_device *device,
6887 struct radv_sampler *sampler,
6888 const VkSamplerCreateInfo *pCreateInfo)
6889 {
6890 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6891 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6892 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6893 device->physical_device->rad_info.chip_class == GFX9;
6894 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6895 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6896
6897 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
6898 vk_find_struct_const(pCreateInfo->pNext,
6899 SAMPLER_REDUCTION_MODE_CREATE_INFO);
6900 if (sampler_reduction)
6901 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6902
6903 if (pCreateInfo->compareEnable)
6904 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
6905
6906 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6907 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6908 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6909 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6910 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
6911 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6912 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6913 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6914 S_008F30_DISABLE_CUBE_WRAP(0) |
6915 S_008F30_COMPAT_MODE(compat_mode) |
6916 S_008F30_FILTER_MODE(filter_mode));
6917 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6918 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6919 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6920 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6921 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6922 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6923 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6924 S_008F38_MIP_POINT_PRECLAMP(0));
6925 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6926 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
6927
6928 if (device->physical_device->rad_info.chip_class >= GFX10) {
6929 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6930 } else {
6931 sampler->state[2] |=
6932 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6933 S_008F38_FILTER_PREC_FIX(1) |
6934 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6935 }
6936 }
6937
6938 VkResult radv_CreateSampler(
6939 VkDevice _device,
6940 const VkSamplerCreateInfo* pCreateInfo,
6941 const VkAllocationCallbacks* pAllocator,
6942 VkSampler* pSampler)
6943 {
6944 RADV_FROM_HANDLE(radv_device, device, _device);
6945 struct radv_sampler *sampler;
6946
6947 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
6948 vk_find_struct_const(pCreateInfo->pNext,
6949 SAMPLER_YCBCR_CONVERSION_INFO);
6950
6951 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
6952
6953 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
6954 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6955 if (!sampler)
6956 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6957
6958 radv_init_sampler(device, sampler, pCreateInfo);
6959
6960 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
6961 *pSampler = radv_sampler_to_handle(sampler);
6962
6963 return VK_SUCCESS;
6964 }
6965
6966 void radv_DestroySampler(
6967 VkDevice _device,
6968 VkSampler _sampler,
6969 const VkAllocationCallbacks* pAllocator)
6970 {
6971 RADV_FROM_HANDLE(radv_device, device, _device);
6972 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
6973
6974 if (!sampler)
6975 return;
6976 vk_free2(&device->alloc, pAllocator, sampler);
6977 }
6978
6979 /* vk_icd.h does not declare this function, so we declare it here to
6980 * suppress Wmissing-prototypes.
6981 */
6982 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6983 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
6984
6985 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6986 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
6987 {
6988 /* For the full details on loader interface versioning, see
6989 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
6990 * What follows is a condensed summary, to help you navigate the large and
6991 * confusing official doc.
6992 *
6993 * - Loader interface v0 is incompatible with later versions. We don't
6994 * support it.
6995 *
6996 * - In loader interface v1:
6997 * - The first ICD entrypoint called by the loader is
6998 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
6999 * entrypoint.
7000 * - The ICD must statically expose no other Vulkan symbol unless it is
7001 * linked with -Bsymbolic.
7002 * - Each dispatchable Vulkan handle created by the ICD must be
7003 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7004 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7005 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7006 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7007 * such loader-managed surfaces.
7008 *
7009 * - Loader interface v2 differs from v1 in:
7010 * - The first ICD entrypoint called by the loader is
7011 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7012 * statically expose this entrypoint.
7013 *
7014 * - Loader interface v3 differs from v2 in:
7015 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7016 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7017 * because the loader no longer does so.
7018 */
7019 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7020 return VK_SUCCESS;
7021 }
7022
7023 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7024 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7025 int *pFD)
7026 {
7027 RADV_FROM_HANDLE(radv_device, device, _device);
7028 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7029
7030 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7031
7032 /* At the moment, we support only the below handle types. */
7033 assert(pGetFdInfo->handleType ==
7034 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7035 pGetFdInfo->handleType ==
7036 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7037
7038 bool ret = radv_get_memory_fd(device, memory, pFD);
7039 if (ret == false)
7040 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7041 return VK_SUCCESS;
7042 }
7043
7044 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7045 VkExternalMemoryHandleTypeFlagBits handleType,
7046 int fd,
7047 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7048 {
7049 RADV_FROM_HANDLE(radv_device, device, _device);
7050
7051 switch (handleType) {
7052 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
7053 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
7054 return VK_SUCCESS;
7055
7056 default:
7057 /* The valid usage section for this function says:
7058 *
7059 * "handleType must not be one of the handle types defined as
7060 * opaque."
7061 *
7062 * So opaque handle types fall into the default "unsupported" case.
7063 */
7064 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7065 }
7066 }
7067
7068 static VkResult radv_import_opaque_fd(struct radv_device *device,
7069 int fd,
7070 uint32_t *syncobj)
7071 {
7072 uint32_t syncobj_handle = 0;
7073 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7074 if (ret != 0)
7075 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7076
7077 if (*syncobj)
7078 device->ws->destroy_syncobj(device->ws, *syncobj);
7079
7080 *syncobj = syncobj_handle;
7081 close(fd);
7082
7083 return VK_SUCCESS;
7084 }
7085
7086 static VkResult radv_import_sync_fd(struct radv_device *device,
7087 int fd,
7088 uint32_t *syncobj)
7089 {
7090 /* If we create a syncobj we do it locally so that if we have an error, we don't
7091 * leave a syncobj in an undetermined state in the fence. */
7092 uint32_t syncobj_handle = *syncobj;
7093 if (!syncobj_handle) {
7094 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
7095 if (ret) {
7096 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7097 }
7098 }
7099
7100 if (fd == -1) {
7101 device->ws->signal_syncobj(device->ws, syncobj_handle);
7102 } else {
7103 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7104 if (ret != 0)
7105 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7106 }
7107
7108 *syncobj = syncobj_handle;
7109 if (fd != -1)
7110 close(fd);
7111
7112 return VK_SUCCESS;
7113 }
7114
7115 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7116 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7117 {
7118 RADV_FROM_HANDLE(radv_device, device, _device);
7119 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7120 VkResult result;
7121 struct radv_semaphore_part *dst = NULL;
7122
7123 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7124 dst = &sem->temporary;
7125 } else {
7126 dst = &sem->permanent;
7127 }
7128
7129 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7130
7131 switch(pImportSemaphoreFdInfo->handleType) {
7132 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7133 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7134 break;
7135 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7136 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7137 break;
7138 default:
7139 unreachable("Unhandled semaphore handle type");
7140 }
7141
7142 if (result == VK_SUCCESS) {
7143 dst->syncobj = syncobj;
7144 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7145 }
7146
7147 return result;
7148 }
7149
7150 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7151 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7152 int *pFd)
7153 {
7154 RADV_FROM_HANDLE(radv_device, device, _device);
7155 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7156 int ret;
7157 uint32_t syncobj_handle;
7158
7159 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7160 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7161 syncobj_handle = sem->temporary.syncobj;
7162 } else {
7163 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7164 syncobj_handle = sem->permanent.syncobj;
7165 }
7166
7167 switch(pGetFdInfo->handleType) {
7168 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7169 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7170 break;
7171 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7172 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7173 if (!ret) {
7174 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7175 radv_destroy_semaphore_part(device, &sem->temporary);
7176 } else {
7177 device->ws->reset_syncobj(device->ws, syncobj_handle);
7178 }
7179 }
7180 break;
7181 default:
7182 unreachable("Unhandled semaphore handle type");
7183 }
7184
7185 if (ret)
7186 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7187 return VK_SUCCESS;
7188 }
7189
7190 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7191 VkPhysicalDevice physicalDevice,
7192 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7193 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7194 {
7195 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7196 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7197
7198 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7199 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7200 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7201 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7202
7203 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7204 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7205 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7206 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7207 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7208 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7209 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7210 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7211 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7212 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7213 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7214 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7215 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7216 } else {
7217 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7218 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7219 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7220 }
7221 }
7222
7223 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7224 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7225 {
7226 RADV_FROM_HANDLE(radv_device, device, _device);
7227 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7228 uint32_t *syncobj_dst = NULL;
7229
7230
7231 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7232 syncobj_dst = &fence->temp_syncobj;
7233 } else {
7234 syncobj_dst = &fence->syncobj;
7235 }
7236
7237 switch(pImportFenceFdInfo->handleType) {
7238 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7239 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7240 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7241 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7242 default:
7243 unreachable("Unhandled fence handle type");
7244 }
7245 }
7246
7247 VkResult radv_GetFenceFdKHR(VkDevice _device,
7248 const VkFenceGetFdInfoKHR *pGetFdInfo,
7249 int *pFd)
7250 {
7251 RADV_FROM_HANDLE(radv_device, device, _device);
7252 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7253 int ret;
7254 uint32_t syncobj_handle;
7255
7256 if (fence->temp_syncobj)
7257 syncobj_handle = fence->temp_syncobj;
7258 else
7259 syncobj_handle = fence->syncobj;
7260
7261 switch(pGetFdInfo->handleType) {
7262 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7263 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7264 break;
7265 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7266 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7267 if (!ret) {
7268 if (fence->temp_syncobj) {
7269 close (fence->temp_syncobj);
7270 fence->temp_syncobj = 0;
7271 } else {
7272 device->ws->reset_syncobj(device->ws, syncobj_handle);
7273 }
7274 }
7275 break;
7276 default:
7277 unreachable("Unhandled fence handle type");
7278 }
7279
7280 if (ret)
7281 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7282 return VK_SUCCESS;
7283 }
7284
7285 void radv_GetPhysicalDeviceExternalFenceProperties(
7286 VkPhysicalDevice physicalDevice,
7287 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7288 VkExternalFenceProperties *pExternalFenceProperties)
7289 {
7290 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7291
7292 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7293 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7294 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7295 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7296 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7297 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7298 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7299 } else {
7300 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7301 pExternalFenceProperties->compatibleHandleTypes = 0;
7302 pExternalFenceProperties->externalFenceFeatures = 0;
7303 }
7304 }
7305
7306 VkResult
7307 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7308 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7309 const VkAllocationCallbacks* pAllocator,
7310 VkDebugReportCallbackEXT* pCallback)
7311 {
7312 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7313 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7314 pCreateInfo, pAllocator, &instance->alloc,
7315 pCallback);
7316 }
7317
7318 void
7319 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7320 VkDebugReportCallbackEXT _callback,
7321 const VkAllocationCallbacks* pAllocator)
7322 {
7323 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7324 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7325 _callback, pAllocator, &instance->alloc);
7326 }
7327
7328 void
7329 radv_DebugReportMessageEXT(VkInstance _instance,
7330 VkDebugReportFlagsEXT flags,
7331 VkDebugReportObjectTypeEXT objectType,
7332 uint64_t object,
7333 size_t location,
7334 int32_t messageCode,
7335 const char* pLayerPrefix,
7336 const char* pMessage)
7337 {
7338 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7339 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7340 object, location, messageCode, pLayerPrefix, pMessage);
7341 }
7342
7343 void
7344 radv_GetDeviceGroupPeerMemoryFeatures(
7345 VkDevice device,
7346 uint32_t heapIndex,
7347 uint32_t localDeviceIndex,
7348 uint32_t remoteDeviceIndex,
7349 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7350 {
7351 assert(localDeviceIndex == remoteDeviceIndex);
7352
7353 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7354 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7355 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7356 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7357 }
7358
7359 static const VkTimeDomainEXT radv_time_domains[] = {
7360 VK_TIME_DOMAIN_DEVICE_EXT,
7361 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7362 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7363 };
7364
7365 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7366 VkPhysicalDevice physicalDevice,
7367 uint32_t *pTimeDomainCount,
7368 VkTimeDomainEXT *pTimeDomains)
7369 {
7370 int d;
7371 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7372
7373 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7374 vk_outarray_append(&out, i) {
7375 *i = radv_time_domains[d];
7376 }
7377 }
7378
7379 return vk_outarray_status(&out);
7380 }
7381
7382 static uint64_t
7383 radv_clock_gettime(clockid_t clock_id)
7384 {
7385 struct timespec current;
7386 int ret;
7387
7388 ret = clock_gettime(clock_id, &current);
7389 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7390 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7391 if (ret < 0)
7392 return 0;
7393
7394 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7395 }
7396
7397 VkResult radv_GetCalibratedTimestampsEXT(
7398 VkDevice _device,
7399 uint32_t timestampCount,
7400 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7401 uint64_t *pTimestamps,
7402 uint64_t *pMaxDeviation)
7403 {
7404 RADV_FROM_HANDLE(radv_device, device, _device);
7405 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7406 int d;
7407 uint64_t begin, end;
7408 uint64_t max_clock_period = 0;
7409
7410 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7411
7412 for (d = 0; d < timestampCount; d++) {
7413 switch (pTimestampInfos[d].timeDomain) {
7414 case VK_TIME_DOMAIN_DEVICE_EXT:
7415 pTimestamps[d] = device->ws->query_value(device->ws,
7416 RADEON_TIMESTAMP);
7417 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7418 max_clock_period = MAX2(max_clock_period, device_period);
7419 break;
7420 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7421 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7422 max_clock_period = MAX2(max_clock_period, 1);
7423 break;
7424
7425 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7426 pTimestamps[d] = begin;
7427 break;
7428 default:
7429 pTimestamps[d] = 0;
7430 break;
7431 }
7432 }
7433
7434 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7435
7436 /*
7437 * The maximum deviation is the sum of the interval over which we
7438 * perform the sampling and the maximum period of any sampled
7439 * clock. That's because the maximum skew between any two sampled
7440 * clock edges is when the sampled clock with the largest period is
7441 * sampled at the end of that period but right at the beginning of the
7442 * sampling interval and some other clock is sampled right at the
7443 * begining of its sampling period and right at the end of the
7444 * sampling interval. Let's assume the GPU has the longest clock
7445 * period and that the application is sampling GPU and monotonic:
7446 *
7447 * s e
7448 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7449 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7450 *
7451 * g
7452 * 0 1 2 3
7453 * GPU -----_____-----_____-----_____-----_____
7454 *
7455 * m
7456 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7457 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7458 *
7459 * Interval <----------------->
7460 * Deviation <-------------------------->
7461 *
7462 * s = read(raw) 2
7463 * g = read(GPU) 1
7464 * m = read(monotonic) 2
7465 * e = read(raw) b
7466 *
7467 * We round the sample interval up by one tick to cover sampling error
7468 * in the interval clock
7469 */
7470
7471 uint64_t sample_interval = end - begin + 1;
7472
7473 *pMaxDeviation = sample_interval + max_clock_period;
7474
7475 return VK_SUCCESS;
7476 }
7477
7478 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7479 VkPhysicalDevice physicalDevice,
7480 VkSampleCountFlagBits samples,
7481 VkMultisamplePropertiesEXT* pMultisampleProperties)
7482 {
7483 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7484 VK_SAMPLE_COUNT_4_BIT |
7485 VK_SAMPLE_COUNT_8_BIT)) {
7486 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7487 } else {
7488 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7489 }
7490 }