2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_private.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
46 #include "util/debug.h"
49 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
51 uint32_t mesa_timestamp
, llvm_timestamp
;
53 memset(uuid
, 0, VK_UUID_SIZE
);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
58 memcpy(uuid
, &mesa_timestamp
, 4);
59 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
60 memcpy((char*)uuid
+ 8, &f
, 2);
61 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
66 radv_get_device_uuid(drmDevicePtr device
, void *uuid
) {
67 memset(uuid
, 0, VK_UUID_SIZE
);
68 memcpy((char*)uuid
+ 0, &device
->businfo
.pci
->domain
, 2);
69 memcpy((char*)uuid
+ 2, &device
->businfo
.pci
->bus
, 1);
70 memcpy((char*)uuid
+ 3, &device
->businfo
.pci
->dev
, 1);
71 memcpy((char*)uuid
+ 4, &device
->businfo
.pci
->func
, 1);
74 static const VkExtensionProperties instance_extensions
[] = {
76 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
79 #ifdef VK_USE_PLATFORM_XCB_KHR
81 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
87 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
93 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
98 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
102 .extensionName
= VK_KHX_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
107 static const VkExtensionProperties common_device_extensions
[] = {
109 .extensionName
= VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME
,
113 .extensionName
= VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME
,
117 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
121 .extensionName
= VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME
,
125 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
129 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
133 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
137 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
141 .extensionName
= VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME
,
145 .extensionName
= VK_KHX_EXTERNAL_MEMORY_EXTENSION_NAME
,
149 .extensionName
= VK_KHX_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
155 radv_extensions_register(struct radv_instance
*instance
,
156 struct radv_extensions
*extensions
,
157 const VkExtensionProperties
*new_ext
,
161 VkExtensionProperties
*new_ptr
;
163 assert(new_ext
&& num_ext
> 0);
166 return VK_ERROR_INITIALIZATION_FAILED
;
168 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
169 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
170 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
172 /* Old array continues to be valid, update nothing */
174 return VK_ERROR_OUT_OF_HOST_MEMORY
;
176 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
177 num_ext
* sizeof(VkExtensionProperties
));
178 extensions
->ext_array
= new_ptr
;
179 extensions
->num_ext
+= num_ext
;
185 radv_extensions_finish(struct radv_instance
*instance
,
186 struct radv_extensions
*extensions
)
191 radv_loge("Attemted to free invalid extension struct\n");
193 if (extensions
->ext_array
)
194 vk_free(&instance
->alloc
, extensions
->ext_array
);
198 is_extension_enabled(const VkExtensionProperties
*extensions
,
202 assert(extensions
&& name
);
204 for (uint32_t i
= 0; i
< num_ext
; i
++) {
205 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
213 get_chip_name(enum radeon_family family
)
216 case CHIP_TAHITI
: return "AMD RADV TAHITI";
217 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
218 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
219 case CHIP_OLAND
: return "AMD RADV OLAND";
220 case CHIP_HAINAN
: return "AMD RADV HAINAN";
221 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
222 case CHIP_KAVERI
: return "AMD RADV KAVERI";
223 case CHIP_KABINI
: return "AMD RADV KABINI";
224 case CHIP_HAWAII
: return "AMD RADV HAWAII";
225 case CHIP_MULLINS
: return "AMD RADV MULLINS";
226 case CHIP_TONGA
: return "AMD RADV TONGA";
227 case CHIP_ICELAND
: return "AMD RADV ICELAND";
228 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
229 case CHIP_FIJI
: return "AMD RADV FIJI";
230 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
231 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
232 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
233 case CHIP_STONEY
: return "AMD RADV STONEY";
234 case CHIP_VEGA10
: return "AMD RADV VEGA";
235 case CHIP_RAVEN
: return "AMD RADV RAVEN";
236 default: return "AMD RADV unknown";
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
250 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
252 return VK_ERROR_INCOMPATIBLE_DRIVER
;
254 version
= drmGetVersion(fd
);
257 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
258 "failed to get version %s: %m", path
);
261 if (strcmp(version
->name
, "amdgpu")) {
262 drmFreeVersion(version
);
264 return VK_ERROR_INCOMPATIBLE_DRIVER
;
266 drmFreeVersion(version
);
268 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 device
->instance
= instance
;
270 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
271 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
273 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
274 instance
->perftest_flags
);
276 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
280 device
->local_fd
= fd
;
281 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
282 result
= radv_init_wsi(device
);
283 if (result
!= VK_SUCCESS
) {
284 device
->ws
->destroy(device
->ws
);
288 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
289 radv_finish_wsi(device
);
290 device
->ws
->destroy(device
->ws
);
291 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
292 "cannot generate UUID");
296 result
= radv_extensions_register(instance
,
298 common_device_extensions
,
299 ARRAY_SIZE(common_device_extensions
));
300 if (result
!= VK_SUCCESS
)
303 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
304 device
->name
= get_chip_name(device
->rad_info
.family
);
306 radv_get_device_uuid(drm_device
, device
->device_uuid
);
308 if (device
->rad_info
.family
== CHIP_STONEY
||
309 device
->rad_info
.chip_class
>= GFX9
) {
310 device
->has_rbplus
= true;
311 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
322 radv_physical_device_finish(struct radv_physical_device
*device
)
324 radv_extensions_finish(device
->instance
, &device
->extensions
);
325 radv_finish_wsi(device
);
326 device
->ws
->destroy(device
->ws
);
327 close(device
->local_fd
);
331 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
332 VkSystemAllocationScope allocationScope
)
338 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
339 size_t align
, VkSystemAllocationScope allocationScope
)
341 return realloc(pOriginal
, size
);
345 default_free_func(void *pUserData
, void *pMemory
)
350 static const VkAllocationCallbacks default_alloc
= {
352 .pfnAllocation
= default_alloc_func
,
353 .pfnReallocation
= default_realloc_func
,
354 .pfnFree
= default_free_func
,
357 static const struct debug_control radv_debug_options
[] = {
358 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
359 {"nodcc", RADV_DEBUG_NO_DCC
},
360 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
361 {"nocache", RADV_DEBUG_NO_CACHE
},
362 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
363 {"nohiz", RADV_DEBUG_NO_HIZ
},
364 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
365 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
366 {"allbos", RADV_DEBUG_ALL_BOS
},
367 {"noibs", RADV_DEBUG_NO_IBS
},
371 static const struct debug_control radv_perftest_options
[] = {
372 {"batchchain", RADV_PERFTEST_BATCHCHAIN
},
373 {"sisched", RADV_PERFTEST_SISCHED
},
377 VkResult
radv_CreateInstance(
378 const VkInstanceCreateInfo
* pCreateInfo
,
379 const VkAllocationCallbacks
* pAllocator
,
380 VkInstance
* pInstance
)
382 struct radv_instance
*instance
;
384 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
386 uint32_t client_version
;
387 if (pCreateInfo
->pApplicationInfo
&&
388 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
389 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
391 client_version
= VK_MAKE_VERSION(1, 0, 0);
394 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
395 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
396 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
397 "Client requested version %d.%d.%d",
398 VK_VERSION_MAJOR(client_version
),
399 VK_VERSION_MINOR(client_version
),
400 VK_VERSION_PATCH(client_version
));
403 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
404 if (!is_extension_enabled(instance_extensions
,
405 ARRAY_SIZE(instance_extensions
),
406 pCreateInfo
->ppEnabledExtensionNames
[i
]))
407 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
410 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
411 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
413 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
415 memset(instance
, 0, sizeof(*instance
));
417 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
420 instance
->alloc
= *pAllocator
;
422 instance
->alloc
= default_alloc
;
424 instance
->apiVersion
= client_version
;
425 instance
->physicalDeviceCount
= -1;
429 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
431 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
434 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
435 radv_perftest_options
);
437 *pInstance
= radv_instance_to_handle(instance
);
442 void radv_DestroyInstance(
443 VkInstance _instance
,
444 const VkAllocationCallbacks
* pAllocator
)
446 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
451 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
452 radv_physical_device_finish(instance
->physicalDevices
+ i
);
455 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
459 vk_free(&instance
->alloc
, instance
);
463 radv_enumerate_devices(struct radv_instance
*instance
)
465 /* TODO: Check for more devices ? */
466 drmDevicePtr devices
[8];
467 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
470 instance
->physicalDeviceCount
= 0;
472 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
474 return VK_ERROR_INCOMPATIBLE_DRIVER
;
476 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
477 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
478 devices
[i
]->bustype
== DRM_BUS_PCI
&&
479 devices
[i
]->deviceinfo
.pci
->vendor_id
== 0x1002) {
481 result
= radv_physical_device_init(instance
->physicalDevices
+
482 instance
->physicalDeviceCount
,
485 if (result
== VK_SUCCESS
)
486 ++instance
->physicalDeviceCount
;
487 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
491 drmFreeDevices(devices
, max_devices
);
496 VkResult
radv_EnumeratePhysicalDevices(
497 VkInstance _instance
,
498 uint32_t* pPhysicalDeviceCount
,
499 VkPhysicalDevice
* pPhysicalDevices
)
501 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
504 if (instance
->physicalDeviceCount
< 0) {
505 result
= radv_enumerate_devices(instance
);
506 if (result
!= VK_SUCCESS
&&
507 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
511 if (!pPhysicalDevices
) {
512 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
514 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
515 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
516 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
519 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
523 void radv_GetPhysicalDeviceFeatures(
524 VkPhysicalDevice physicalDevice
,
525 VkPhysicalDeviceFeatures
* pFeatures
)
527 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
528 bool is_gfx9
= pdevice
->rad_info
.chip_class
>= GFX9
;
529 memset(pFeatures
, 0, sizeof(*pFeatures
));
531 *pFeatures
= (VkPhysicalDeviceFeatures
) {
532 .robustBufferAccess
= true,
533 .fullDrawIndexUint32
= true,
534 .imageCubeArray
= true,
535 .independentBlend
= true,
536 .geometryShader
= !is_gfx9
,
537 .tessellationShader
= !is_gfx9
,
538 .sampleRateShading
= false,
539 .dualSrcBlend
= true,
541 .multiDrawIndirect
= true,
542 .drawIndirectFirstInstance
= true,
544 .depthBiasClamp
= true,
545 .fillModeNonSolid
= true,
550 .multiViewport
= true,
551 .samplerAnisotropy
= true,
552 .textureCompressionETC2
= false,
553 .textureCompressionASTC_LDR
= false,
554 .textureCompressionBC
= true,
555 .occlusionQueryPrecise
= true,
556 .pipelineStatisticsQuery
= true,
557 .vertexPipelineStoresAndAtomics
= true,
558 .fragmentStoresAndAtomics
= true,
559 .shaderTessellationAndGeometryPointSize
= true,
560 .shaderImageGatherExtended
= true,
561 .shaderStorageImageExtendedFormats
= true,
562 .shaderStorageImageMultisample
= false,
563 .shaderUniformBufferArrayDynamicIndexing
= true,
564 .shaderSampledImageArrayDynamicIndexing
= true,
565 .shaderStorageBufferArrayDynamicIndexing
= true,
566 .shaderStorageImageArrayDynamicIndexing
= true,
567 .shaderStorageImageReadWithoutFormat
= true,
568 .shaderStorageImageWriteWithoutFormat
= true,
569 .shaderClipDistance
= true,
570 .shaderCullDistance
= true,
571 .shaderFloat64
= true,
573 .shaderInt16
= false,
574 .sparseBinding
= true,
575 .variableMultisampleRate
= true,
576 .inheritedQueries
= true,
580 void radv_GetPhysicalDeviceFeatures2KHR(
581 VkPhysicalDevice physicalDevice
,
582 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
584 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
587 void radv_GetPhysicalDeviceProperties(
588 VkPhysicalDevice physicalDevice
,
589 VkPhysicalDeviceProperties
* pProperties
)
591 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
592 VkSampleCountFlags sample_counts
= 0xf;
594 /* make sure that the entire descriptor set is addressable with a signed
595 * 32-bit int. So the sum of all limits scaled by descriptor size has to
596 * be at most 2 GiB. the combined image & samples object count as one of
597 * both. This limit is for the pipeline layout, not for the set layout, but
598 * there is no set limit, so we just set a pipeline limit. I don't think
599 * any app is going to hit this soon. */
600 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
601 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
602 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
603 32 /* sampler, largest when combined with image */ +
604 64 /* sampled image */ +
605 64 /* storage image */);
607 VkPhysicalDeviceLimits limits
= {
608 .maxImageDimension1D
= (1 << 14),
609 .maxImageDimension2D
= (1 << 14),
610 .maxImageDimension3D
= (1 << 11),
611 .maxImageDimensionCube
= (1 << 14),
612 .maxImageArrayLayers
= (1 << 11),
613 .maxTexelBufferElements
= 128 * 1024 * 1024,
614 .maxUniformBufferRange
= UINT32_MAX
,
615 .maxStorageBufferRange
= UINT32_MAX
,
616 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
617 .maxMemoryAllocationCount
= UINT32_MAX
,
618 .maxSamplerAllocationCount
= 64 * 1024,
619 .bufferImageGranularity
= 64, /* A cache line */
620 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
621 .maxBoundDescriptorSets
= MAX_SETS
,
622 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
623 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
624 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
625 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
626 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
627 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
628 .maxPerStageResources
= max_descriptor_set_size
,
629 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
630 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
631 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
632 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
633 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
634 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
635 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
636 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
637 .maxVertexInputAttributes
= 32,
638 .maxVertexInputBindings
= 32,
639 .maxVertexInputAttributeOffset
= 2047,
640 .maxVertexInputBindingStride
= 2048,
641 .maxVertexOutputComponents
= 128,
642 .maxTessellationGenerationLevel
= 64,
643 .maxTessellationPatchSize
= 32,
644 .maxTessellationControlPerVertexInputComponents
= 128,
645 .maxTessellationControlPerVertexOutputComponents
= 128,
646 .maxTessellationControlPerPatchOutputComponents
= 120,
647 .maxTessellationControlTotalOutputComponents
= 4096,
648 .maxTessellationEvaluationInputComponents
= 128,
649 .maxTessellationEvaluationOutputComponents
= 128,
650 .maxGeometryShaderInvocations
= 127,
651 .maxGeometryInputComponents
= 64,
652 .maxGeometryOutputComponents
= 128,
653 .maxGeometryOutputVertices
= 256,
654 .maxGeometryTotalOutputComponents
= 1024,
655 .maxFragmentInputComponents
= 128,
656 .maxFragmentOutputAttachments
= 8,
657 .maxFragmentDualSrcAttachments
= 1,
658 .maxFragmentCombinedOutputResources
= 8,
659 .maxComputeSharedMemorySize
= 32768,
660 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
661 .maxComputeWorkGroupInvocations
= 2048,
662 .maxComputeWorkGroupSize
= {
667 .subPixelPrecisionBits
= 4 /* FIXME */,
668 .subTexelPrecisionBits
= 4 /* FIXME */,
669 .mipmapPrecisionBits
= 4 /* FIXME */,
670 .maxDrawIndexedIndexValue
= UINT32_MAX
,
671 .maxDrawIndirectCount
= UINT32_MAX
,
672 .maxSamplerLodBias
= 16,
673 .maxSamplerAnisotropy
= 16,
674 .maxViewports
= MAX_VIEWPORTS
,
675 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
676 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
677 .viewportSubPixelBits
= 13, /* We take a float? */
678 .minMemoryMapAlignment
= 4096, /* A page */
679 .minTexelBufferOffsetAlignment
= 1,
680 .minUniformBufferOffsetAlignment
= 4,
681 .minStorageBufferOffsetAlignment
= 4,
682 .minTexelOffset
= -32,
683 .maxTexelOffset
= 31,
684 .minTexelGatherOffset
= -32,
685 .maxTexelGatherOffset
= 31,
686 .minInterpolationOffset
= -2,
687 .maxInterpolationOffset
= 2,
688 .subPixelInterpolationOffsetBits
= 8,
689 .maxFramebufferWidth
= (1 << 14),
690 .maxFramebufferHeight
= (1 << 14),
691 .maxFramebufferLayers
= (1 << 10),
692 .framebufferColorSampleCounts
= sample_counts
,
693 .framebufferDepthSampleCounts
= sample_counts
,
694 .framebufferStencilSampleCounts
= sample_counts
,
695 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
696 .maxColorAttachments
= MAX_RTS
,
697 .sampledImageColorSampleCounts
= sample_counts
,
698 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
699 .sampledImageDepthSampleCounts
= sample_counts
,
700 .sampledImageStencilSampleCounts
= sample_counts
,
701 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
702 .maxSampleMaskWords
= 1,
703 .timestampComputeAndGraphics
= true,
704 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
705 .maxClipDistances
= 8,
706 .maxCullDistances
= 8,
707 .maxCombinedClipAndCullDistances
= 8,
708 .discreteQueuePriorities
= 1,
709 .pointSizeRange
= { 0.125, 255.875 },
710 .lineWidthRange
= { 0.0, 7.9921875 },
711 .pointSizeGranularity
= (1.0 / 8.0),
712 .lineWidthGranularity
= (1.0 / 128.0),
713 .strictLines
= false, /* FINISHME */
714 .standardSampleLocations
= true,
715 .optimalBufferCopyOffsetAlignment
= 128,
716 .optimalBufferCopyRowPitchAlignment
= 128,
717 .nonCoherentAtomSize
= 64,
720 *pProperties
= (VkPhysicalDeviceProperties
) {
721 .apiVersion
= VK_MAKE_VERSION(1, 0, 42),
722 .driverVersion
= vk_get_driver_version(),
724 .deviceID
= pdevice
->rad_info
.pci_id
,
725 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
727 .sparseProperties
= {0},
730 strcpy(pProperties
->deviceName
, pdevice
->name
);
731 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
734 void radv_GetPhysicalDeviceProperties2KHR(
735 VkPhysicalDevice physicalDevice
,
736 VkPhysicalDeviceProperties2KHR
*pProperties
)
738 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
739 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
741 vk_foreach_struct(ext
, pProperties
->pNext
) {
742 switch (ext
->sType
) {
743 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
744 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
745 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
746 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHX
: {
750 VkPhysicalDeviceIDPropertiesKHX
*properties
= (VkPhysicalDeviceIDPropertiesKHX
*)ext
;
751 radv_device_get_cache_uuid(0, properties
->driverUUID
);
752 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
753 properties
->deviceLUIDValid
= false;
762 static void radv_get_physical_device_queue_family_properties(
763 struct radv_physical_device
* pdevice
,
765 VkQueueFamilyProperties
** pQueueFamilyProperties
)
767 int num_queue_families
= 1;
769 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
770 pdevice
->rad_info
.chip_class
>= CIK
&&
771 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
772 num_queue_families
++;
774 if (pQueueFamilyProperties
== NULL
) {
775 *pCount
= num_queue_families
;
784 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
785 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
786 VK_QUEUE_COMPUTE_BIT
|
787 VK_QUEUE_TRANSFER_BIT
|
788 VK_QUEUE_SPARSE_BINDING_BIT
,
790 .timestampValidBits
= 64,
791 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
796 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
797 pdevice
->rad_info
.chip_class
>= CIK
&&
798 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
800 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
801 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
802 VK_QUEUE_TRANSFER_BIT
|
803 VK_QUEUE_SPARSE_BINDING_BIT
,
804 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
805 .timestampValidBits
= 64,
806 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
814 void radv_GetPhysicalDeviceQueueFamilyProperties(
815 VkPhysicalDevice physicalDevice
,
817 VkQueueFamilyProperties
* pQueueFamilyProperties
)
819 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
820 if (!pQueueFamilyProperties
) {
821 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
824 VkQueueFamilyProperties
*properties
[] = {
825 pQueueFamilyProperties
+ 0,
826 pQueueFamilyProperties
+ 1,
827 pQueueFamilyProperties
+ 2,
829 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
830 assert(*pCount
<= 3);
833 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
834 VkPhysicalDevice physicalDevice
,
836 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
838 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
839 if (!pQueueFamilyProperties
) {
840 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
843 VkQueueFamilyProperties
*properties
[] = {
844 &pQueueFamilyProperties
[0].queueFamilyProperties
,
845 &pQueueFamilyProperties
[1].queueFamilyProperties
,
846 &pQueueFamilyProperties
[2].queueFamilyProperties
,
848 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
849 assert(*pCount
<= 3);
852 void radv_GetPhysicalDeviceMemoryProperties(
853 VkPhysicalDevice physicalDevice
,
854 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
856 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
858 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
860 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
861 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
862 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
863 .heapIndex
= RADV_MEM_HEAP_VRAM
,
865 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
866 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
867 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
868 .heapIndex
= RADV_MEM_HEAP_GTT
,
870 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
871 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
872 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
873 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
874 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
876 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
877 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
878 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
879 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
880 .heapIndex
= RADV_MEM_HEAP_GTT
,
883 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
885 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
886 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
887 .size
= physical_device
->rad_info
.vram_size
-
888 physical_device
->rad_info
.vram_vis_size
,
889 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
891 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
892 .size
= physical_device
->rad_info
.vram_vis_size
,
893 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
895 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
896 .size
= physical_device
->rad_info
.gart_size
,
901 void radv_GetPhysicalDeviceMemoryProperties2KHR(
902 VkPhysicalDevice physicalDevice
,
903 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
905 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
906 &pMemoryProperties
->memoryProperties
);
910 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
911 int queue_family_index
, int idx
)
913 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
914 queue
->device
= device
;
915 queue
->queue_family_index
= queue_family_index
;
916 queue
->queue_idx
= idx
;
918 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
920 return VK_ERROR_OUT_OF_HOST_MEMORY
;
926 radv_queue_finish(struct radv_queue
*queue
)
929 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
931 if (queue
->initial_preamble_cs
)
932 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
933 if (queue
->continue_preamble_cs
)
934 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
935 if (queue
->descriptor_bo
)
936 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
937 if (queue
->scratch_bo
)
938 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
939 if (queue
->esgs_ring_bo
)
940 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
941 if (queue
->gsvs_ring_bo
)
942 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
943 if (queue
->tess_factor_ring_bo
)
944 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
945 if (queue
->tess_offchip_ring_bo
)
946 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
947 if (queue
->compute_scratch_bo
)
948 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
952 radv_device_init_gs_info(struct radv_device
*device
)
954 switch (device
->physical_device
->rad_info
.family
) {
963 device
->gs_table_depth
= 16;
977 device
->gs_table_depth
= 32;
980 unreachable("unknown GPU");
984 VkResult
radv_CreateDevice(
985 VkPhysicalDevice physicalDevice
,
986 const VkDeviceCreateInfo
* pCreateInfo
,
987 const VkAllocationCallbacks
* pAllocator
,
990 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
992 struct radv_device
*device
;
994 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
995 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
996 physical_device
->extensions
.num_ext
,
997 pCreateInfo
->ppEnabledExtensionNames
[i
]))
998 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
1001 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
1003 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1005 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1007 memset(device
, 0, sizeof(*device
));
1009 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1010 device
->instance
= physical_device
->instance
;
1011 device
->physical_device
= physical_device
;
1013 device
->debug_flags
= device
->instance
->debug_flags
;
1015 device
->ws
= physical_device
->ws
;
1017 device
->alloc
= *pAllocator
;
1019 device
->alloc
= physical_device
->instance
->alloc
;
1021 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1022 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1023 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1025 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1026 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1027 if (!device
->queues
[qfi
]) {
1028 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1032 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1034 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1036 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1037 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
1038 if (result
!= VK_SUCCESS
)
1043 #if HAVE_LLVM < 0x0400
1044 device
->llvm_supports_spill
= false;
1046 device
->llvm_supports_spill
= true;
1049 /* The maximum number of scratch waves. Scratch space isn't divided
1050 * evenly between CUs. The number is only a function of the number of CUs.
1051 * We can decrease the constant to decrease the scratch buffer size.
1053 * sctx->scratch_waves must be >= the maximum posible size of
1054 * 1 threadgroup, so that the hw doesn't hang from being unable
1057 * The recommended value is 4 per CU at most. Higher numbers don't
1058 * bring much benefit, but they still occupy chip resources (think
1059 * async compute). I've seen ~2% performance difference between 4 and 32.
1061 uint32_t max_threads_per_block
= 2048;
1062 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1063 max_threads_per_block
/ 64);
1065 radv_device_init_gs_info(device
);
1067 device
->tess_offchip_block_dw_size
=
1068 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1069 device
->has_distributed_tess
=
1070 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1071 device
->physical_device
->rad_info
.max_se
>= 2;
1073 result
= radv_device_init_meta(device
);
1074 if (result
!= VK_SUCCESS
)
1077 radv_device_init_msaa(device
);
1079 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1080 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1082 case RADV_QUEUE_GENERAL
:
1083 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1084 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1085 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1087 case RADV_QUEUE_COMPUTE
:
1088 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1089 radeon_emit(device
->empty_cs
[family
], 0);
1092 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1094 device
->flush_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1096 case RADV_QUEUE_GENERAL
:
1097 case RADV_QUEUE_COMPUTE
:
1098 si_cs_emit_cache_flush(device
->flush_cs
[family
],
1100 device
->physical_device
->rad_info
.chip_class
,
1102 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1103 RADV_CMD_FLAG_INV_ICACHE
|
1104 RADV_CMD_FLAG_INV_SMEM_L1
|
1105 RADV_CMD_FLAG_INV_VMEM_L1
|
1106 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1109 device
->ws
->cs_finalize(device
->flush_cs
[family
]);
1111 device
->flush_shader_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1113 case RADV_QUEUE_GENERAL
:
1114 case RADV_QUEUE_COMPUTE
:
1115 si_cs_emit_cache_flush(device
->flush_shader_cs
[family
],
1117 device
->physical_device
->rad_info
.chip_class
,
1119 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1120 family
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) |
1121 RADV_CMD_FLAG_INV_ICACHE
|
1122 RADV_CMD_FLAG_INV_SMEM_L1
|
1123 RADV_CMD_FLAG_INV_VMEM_L1
|
1124 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1127 device
->ws
->cs_finalize(device
->flush_shader_cs
[family
]);
1130 if (getenv("RADV_TRACE_FILE")) {
1131 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
1132 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
1133 if (!device
->trace_bo
)
1136 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
1137 if (!device
->trace_id_ptr
)
1141 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1142 cik_create_gfx_config(device
);
1144 VkPipelineCacheCreateInfo ci
;
1145 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1148 ci
.pInitialData
= NULL
;
1149 ci
.initialDataSize
= 0;
1151 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1153 if (result
!= VK_SUCCESS
)
1156 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1158 *pDevice
= radv_device_to_handle(device
);
1162 if (device
->trace_bo
)
1163 device
->ws
->buffer_destroy(device
->trace_bo
);
1165 if (device
->gfx_init
)
1166 device
->ws
->buffer_destroy(device
->gfx_init
);
1168 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1169 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1170 radv_queue_finish(&device
->queues
[i
][q
]);
1171 if (device
->queue_count
[i
])
1172 vk_free(&device
->alloc
, device
->queues
[i
]);
1175 vk_free(&device
->alloc
, device
);
1179 void radv_DestroyDevice(
1181 const VkAllocationCallbacks
* pAllocator
)
1183 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1188 if (device
->trace_bo
)
1189 device
->ws
->buffer_destroy(device
->trace_bo
);
1191 if (device
->gfx_init
)
1192 device
->ws
->buffer_destroy(device
->gfx_init
);
1194 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1195 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1196 radv_queue_finish(&device
->queues
[i
][q
]);
1197 if (device
->queue_count
[i
])
1198 vk_free(&device
->alloc
, device
->queues
[i
]);
1199 if (device
->empty_cs
[i
])
1200 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1201 if (device
->flush_cs
[i
])
1202 device
->ws
->cs_destroy(device
->flush_cs
[i
]);
1203 if (device
->flush_shader_cs
[i
])
1204 device
->ws
->cs_destroy(device
->flush_shader_cs
[i
]);
1206 radv_device_finish_meta(device
);
1208 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1209 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1211 vk_free(&device
->alloc
, device
);
1214 VkResult
radv_EnumerateInstanceExtensionProperties(
1215 const char* pLayerName
,
1216 uint32_t* pPropertyCount
,
1217 VkExtensionProperties
* pProperties
)
1219 if (pProperties
== NULL
) {
1220 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1224 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1225 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1227 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1228 return VK_INCOMPLETE
;
1233 VkResult
radv_EnumerateDeviceExtensionProperties(
1234 VkPhysicalDevice physicalDevice
,
1235 const char* pLayerName
,
1236 uint32_t* pPropertyCount
,
1237 VkExtensionProperties
* pProperties
)
1239 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1241 if (pProperties
== NULL
) {
1242 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1246 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1247 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1249 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1250 return VK_INCOMPLETE
;
1255 VkResult
radv_EnumerateInstanceLayerProperties(
1256 uint32_t* pPropertyCount
,
1257 VkLayerProperties
* pProperties
)
1259 if (pProperties
== NULL
) {
1260 *pPropertyCount
= 0;
1264 /* None supported at this time */
1265 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1268 VkResult
radv_EnumerateDeviceLayerProperties(
1269 VkPhysicalDevice physicalDevice
,
1270 uint32_t* pPropertyCount
,
1271 VkLayerProperties
* pProperties
)
1273 if (pProperties
== NULL
) {
1274 *pPropertyCount
= 0;
1278 /* None supported at this time */
1279 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1282 void radv_GetDeviceQueue(
1284 uint32_t queueFamilyIndex
,
1285 uint32_t queueIndex
,
1288 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1290 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1293 static void radv_dump_trace(struct radv_device
*device
,
1294 struct radeon_winsys_cs
*cs
)
1296 const char *filename
= getenv("RADV_TRACE_FILE");
1297 FILE *f
= fopen(filename
, "w");
1299 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1303 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1304 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1309 fill_geom_tess_rings(struct radv_queue
*queue
,
1311 bool add_sample_positions
,
1312 uint32_t esgs_ring_size
,
1313 struct radeon_winsys_bo
*esgs_ring_bo
,
1314 uint32_t gsvs_ring_size
,
1315 struct radeon_winsys_bo
*gsvs_ring_bo
,
1316 uint32_t tess_factor_ring_size
,
1317 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1318 uint32_t tess_offchip_ring_size
,
1319 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1321 uint64_t esgs_va
= 0, gsvs_va
= 0;
1322 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1323 uint32_t *desc
= &map
[4];
1326 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1328 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1329 if (tess_factor_ring_bo
)
1330 tess_factor_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1331 if (tess_offchip_ring_bo
)
1332 tess_offchip_va
= queue
->device
->ws
->buffer_get_va(tess_offchip_ring_bo
);
1334 /* stride 0, num records - size, add tid, swizzle, elsize4,
1337 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1338 S_008F04_STRIDE(0) |
1339 S_008F04_SWIZZLE_ENABLE(true);
1340 desc
[2] = esgs_ring_size
;
1341 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1342 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1343 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1344 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1345 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1346 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1347 S_008F0C_ELEMENT_SIZE(1) |
1348 S_008F0C_INDEX_STRIDE(3) |
1349 S_008F0C_ADD_TID_ENABLE(true);
1352 /* GS entry for ES->GS ring */
1353 /* stride 0, num records - size, elsize0,
1356 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1357 S_008F04_STRIDE(0) |
1358 S_008F04_SWIZZLE_ENABLE(false);
1359 desc
[2] = esgs_ring_size
;
1360 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1364 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1366 S_008F0C_ELEMENT_SIZE(0) |
1367 S_008F0C_INDEX_STRIDE(0) |
1368 S_008F0C_ADD_TID_ENABLE(false);
1371 /* VS entry for GS->VS ring */
1372 /* stride 0, num records - size, elsize0,
1375 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1376 S_008F04_STRIDE(0) |
1377 S_008F04_SWIZZLE_ENABLE(false);
1378 desc
[2] = gsvs_ring_size
;
1379 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1383 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1385 S_008F0C_ELEMENT_SIZE(0) |
1386 S_008F0C_INDEX_STRIDE(0) |
1387 S_008F0C_ADD_TID_ENABLE(false);
1390 /* stride gsvs_itemsize, num records 64
1391 elsize 4, index stride 16 */
1392 /* shader will patch stride and desc[2] */
1394 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1395 S_008F04_STRIDE(0) |
1396 S_008F04_SWIZZLE_ENABLE(true);
1398 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1399 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1400 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1401 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1402 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1403 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1404 S_008F0C_ELEMENT_SIZE(1) |
1405 S_008F0C_INDEX_STRIDE(1) |
1406 S_008F0C_ADD_TID_ENABLE(true);
1409 desc
[0] = tess_factor_va
;
1410 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1411 S_008F04_STRIDE(0) |
1412 S_008F04_SWIZZLE_ENABLE(false);
1413 desc
[2] = tess_factor_ring_size
;
1414 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1415 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1416 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1417 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1418 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1419 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1420 S_008F0C_ELEMENT_SIZE(0) |
1421 S_008F0C_INDEX_STRIDE(0) |
1422 S_008F0C_ADD_TID_ENABLE(false);
1425 desc
[0] = tess_offchip_va
;
1426 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1427 S_008F04_STRIDE(0) |
1428 S_008F04_SWIZZLE_ENABLE(false);
1429 desc
[2] = tess_offchip_ring_size
;
1430 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1431 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1432 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1433 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1434 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1435 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1436 S_008F0C_ELEMENT_SIZE(0) |
1437 S_008F0C_INDEX_STRIDE(0) |
1438 S_008F0C_ADD_TID_ENABLE(false);
1441 /* add sample positions after all rings */
1442 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1444 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1446 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1448 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1450 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1454 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1456 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1457 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1458 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1459 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1460 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1461 device
->physical_device
->rad_info
.max_se
;
1462 unsigned offchip_granularity
;
1463 unsigned hs_offchip_param
;
1464 switch (device
->tess_offchip_block_dw_size
) {
1469 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1472 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1476 switch (device
->physical_device
->rad_info
.chip_class
) {
1478 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1484 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1488 *max_offchip_buffers_p
= max_offchip_buffers
;
1489 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1490 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1491 --max_offchip_buffers
;
1493 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1494 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1497 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1499 return hs_offchip_param
;
1503 radv_get_preamble_cs(struct radv_queue
*queue
,
1504 uint32_t scratch_size
,
1505 uint32_t compute_scratch_size
,
1506 uint32_t esgs_ring_size
,
1507 uint32_t gsvs_ring_size
,
1508 bool needs_tess_rings
,
1509 bool needs_sample_positions
,
1510 struct radeon_winsys_cs
**initial_preamble_cs
,
1511 struct radeon_winsys_cs
**continue_preamble_cs
)
1513 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1514 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1515 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1516 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1517 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1518 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1519 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1520 struct radeon_winsys_cs
*dest_cs
[2] = {0};
1521 bool add_tess_rings
= false, add_sample_positions
= false;
1522 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1523 unsigned max_offchip_buffers
;
1524 unsigned hs_offchip_param
= 0;
1525 if (!queue
->has_tess_rings
) {
1526 if (needs_tess_rings
)
1527 add_tess_rings
= true;
1529 if (!queue
->has_sample_positions
) {
1530 if (needs_sample_positions
)
1531 add_sample_positions
= true;
1533 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1534 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1535 &max_offchip_buffers
);
1536 tess_offchip_ring_size
= max_offchip_buffers
*
1537 queue
->device
->tess_offchip_block_dw_size
* 4;
1539 if (scratch_size
<= queue
->scratch_size
&&
1540 compute_scratch_size
<= queue
->compute_scratch_size
&&
1541 esgs_ring_size
<= queue
->esgs_ring_size
&&
1542 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1543 !add_tess_rings
&& !add_sample_positions
&&
1544 queue
->initial_preamble_cs
) {
1545 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1546 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1547 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1548 *continue_preamble_cs
= NULL
;
1552 if (scratch_size
> queue
->scratch_size
) {
1553 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1557 RADEON_FLAG_NO_CPU_ACCESS
);
1561 scratch_bo
= queue
->scratch_bo
;
1563 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1564 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1565 compute_scratch_size
,
1568 RADEON_FLAG_NO_CPU_ACCESS
);
1569 if (!compute_scratch_bo
)
1573 compute_scratch_bo
= queue
->compute_scratch_bo
;
1575 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1576 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1580 RADEON_FLAG_NO_CPU_ACCESS
);
1584 esgs_ring_bo
= queue
->esgs_ring_bo
;
1585 esgs_ring_size
= queue
->esgs_ring_size
;
1588 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1589 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1593 RADEON_FLAG_NO_CPU_ACCESS
);
1597 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1598 gsvs_ring_size
= queue
->gsvs_ring_size
;
1601 if (add_tess_rings
) {
1602 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1603 tess_factor_ring_size
,
1606 RADEON_FLAG_NO_CPU_ACCESS
);
1607 if (!tess_factor_ring_bo
)
1609 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1610 tess_offchip_ring_size
,
1613 RADEON_FLAG_NO_CPU_ACCESS
);
1614 if (!tess_offchip_ring_bo
)
1617 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1618 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1621 if (scratch_bo
!= queue
->scratch_bo
||
1622 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1623 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1624 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1625 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1627 if (gsvs_ring_bo
|| esgs_ring_bo
||
1628 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1629 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1630 if (add_sample_positions
)
1631 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1633 else if (scratch_bo
)
1634 size
= 8; /* 2 dword */
1636 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1640 RADEON_FLAG_CPU_ACCESS
);
1644 descriptor_bo
= queue
->descriptor_bo
;
1646 for(int i
= 0; i
< 2; ++i
) {
1647 struct radeon_winsys_cs
*cs
= NULL
;
1648 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1649 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1656 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1659 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1662 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1664 if (tess_factor_ring_bo
)
1665 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1667 if (tess_offchip_ring_bo
)
1668 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1671 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1673 if (descriptor_bo
!= queue
->descriptor_bo
) {
1674 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1677 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1678 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1679 S_008F04_SWIZZLE_ENABLE(1);
1680 map
[0] = scratch_va
;
1684 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1685 add_sample_positions
)
1686 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1687 esgs_ring_size
, esgs_ring_bo
,
1688 gsvs_ring_size
, gsvs_ring_bo
,
1689 tess_factor_ring_size
, tess_factor_ring_bo
,
1690 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1692 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1695 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1696 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1697 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1698 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1699 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1702 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1703 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1704 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1705 radeon_emit(cs
, esgs_ring_size
>> 8);
1706 radeon_emit(cs
, gsvs_ring_size
>> 8);
1708 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1709 radeon_emit(cs
, esgs_ring_size
>> 8);
1710 radeon_emit(cs
, gsvs_ring_size
>> 8);
1714 if (tess_factor_ring_bo
) {
1715 uint64_t tf_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1716 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1717 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1718 S_030938_SIZE(tess_factor_ring_size
/ 4));
1719 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1721 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1722 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1725 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1727 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1728 S_008988_SIZE(tess_factor_ring_size
/ 4));
1729 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1731 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1736 if (descriptor_bo
) {
1737 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1738 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1739 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1740 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1741 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1742 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1744 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1746 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1747 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1748 radeon_emit(cs
, va
);
1749 radeon_emit(cs
, va
>> 32);
1753 if (compute_scratch_bo
) {
1754 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1755 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1756 S_008F04_SWIZZLE_ENABLE(1);
1758 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1760 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1761 radeon_emit(cs
, scratch_va
);
1762 radeon_emit(cs
, rsrc1
);
1766 si_cs_emit_cache_flush(cs
,
1768 queue
->device
->physical_device
->rad_info
.chip_class
,
1770 queue
->queue_family_index
== RING_COMPUTE
&&
1771 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1772 RADV_CMD_FLAG_INV_ICACHE
|
1773 RADV_CMD_FLAG_INV_SMEM_L1
|
1774 RADV_CMD_FLAG_INV_VMEM_L1
|
1775 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1778 if (!queue
->device
->ws
->cs_finalize(cs
))
1782 if (queue
->initial_preamble_cs
)
1783 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1785 if (queue
->continue_preamble_cs
)
1786 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1788 queue
->initial_preamble_cs
= dest_cs
[0];
1789 queue
->continue_preamble_cs
= dest_cs
[1];
1791 if (scratch_bo
!= queue
->scratch_bo
) {
1792 if (queue
->scratch_bo
)
1793 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1794 queue
->scratch_bo
= scratch_bo
;
1795 queue
->scratch_size
= scratch_size
;
1798 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1799 if (queue
->compute_scratch_bo
)
1800 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1801 queue
->compute_scratch_bo
= compute_scratch_bo
;
1802 queue
->compute_scratch_size
= compute_scratch_size
;
1805 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1806 if (queue
->esgs_ring_bo
)
1807 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1808 queue
->esgs_ring_bo
= esgs_ring_bo
;
1809 queue
->esgs_ring_size
= esgs_ring_size
;
1812 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1813 if (queue
->gsvs_ring_bo
)
1814 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1815 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1816 queue
->gsvs_ring_size
= gsvs_ring_size
;
1819 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1820 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1823 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1824 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1825 queue
->has_tess_rings
= true;
1828 if (descriptor_bo
!= queue
->descriptor_bo
) {
1829 if (queue
->descriptor_bo
)
1830 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1832 queue
->descriptor_bo
= descriptor_bo
;
1835 if (add_sample_positions
)
1836 queue
->has_sample_positions
= true;
1838 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1839 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1840 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1841 *continue_preamble_cs
= NULL
;
1844 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1846 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1847 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1848 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1849 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1850 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1851 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1852 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1853 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1854 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1855 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1856 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1857 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1858 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1859 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1860 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1861 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1864 VkResult
radv_QueueSubmit(
1866 uint32_t submitCount
,
1867 const VkSubmitInfo
* pSubmits
,
1870 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1871 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1872 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1873 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1875 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1876 uint32_t scratch_size
= 0;
1877 uint32_t compute_scratch_size
= 0;
1878 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1879 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1881 bool fence_emitted
= false;
1882 bool tess_rings_needed
= false;
1883 bool sample_positions_needed
= false;
1885 /* Do this first so failing to allocate scratch buffers can't result in
1886 * partially executed submissions. */
1887 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1888 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1889 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1890 pSubmits
[i
].pCommandBuffers
[j
]);
1892 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1893 compute_scratch_size
= MAX2(compute_scratch_size
,
1894 cmd_buffer
->compute_scratch_size_needed
);
1895 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1896 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1897 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1898 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1902 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1903 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1904 sample_positions_needed
,
1905 &initial_preamble_cs
, &continue_preamble_cs
);
1906 if (result
!= VK_SUCCESS
)
1909 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1910 struct radeon_winsys_cs
**cs_array
;
1911 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1912 bool can_patch
= !do_flush
;
1915 if (!pSubmits
[i
].commandBufferCount
) {
1916 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1917 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1918 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1920 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1921 pSubmits
[i
].waitSemaphoreCount
,
1922 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1923 pSubmits
[i
].signalSemaphoreCount
,
1926 radv_loge("failed to submit CS %d\n", i
);
1929 fence_emitted
= true;
1934 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1935 (pSubmits
[i
].commandBufferCount
+ do_flush
));
1938 cs_array
[0] = pSubmits
[i
].waitSemaphoreCount
?
1939 queue
->device
->flush_shader_cs
[queue
->queue_family_index
] :
1940 queue
->device
->flush_cs
[queue
->queue_family_index
];
1942 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1943 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1944 pSubmits
[i
].pCommandBuffers
[j
]);
1945 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1947 cs_array
[j
+ do_flush
] = cmd_buffer
->cs
;
1948 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1952 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
+ do_flush
; j
+= advance
) {
1953 advance
= MIN2(max_cs_submission
,
1954 pSubmits
[i
].commandBufferCount
+ do_flush
- j
);
1956 bool e
= j
+ advance
== pSubmits
[i
].commandBufferCount
+ do_flush
;
1958 if (queue
->device
->trace_bo
)
1959 *queue
->device
->trace_id_ptr
= 0;
1961 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1962 advance
, initial_preamble_cs
, continue_preamble_cs
,
1963 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1964 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1965 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1966 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1967 can_patch
, base_fence
);
1970 radv_loge("failed to submit CS %d\n", i
);
1973 fence_emitted
= true;
1974 if (queue
->device
->trace_bo
) {
1975 bool success
= queue
->device
->ws
->ctx_wait_idle(
1977 radv_queue_family_to_ring(
1978 queue
->queue_family_index
),
1981 if (!success
) { /* Hang */
1982 radv_dump_trace(queue
->device
, cs_array
[j
]);
1992 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1993 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1994 1, NULL
, NULL
, NULL
, 0, NULL
, 0,
1997 fence
->submitted
= true;
2003 VkResult
radv_QueueWaitIdle(
2006 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2008 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2009 radv_queue_family_to_ring(queue
->queue_family_index
),
2014 VkResult
radv_DeviceWaitIdle(
2017 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2019 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2020 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2021 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2027 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2028 VkInstance instance
,
2031 return radv_lookup_entrypoint(pName
);
2034 /* The loader wants us to expose a second GetInstanceProcAddr function
2035 * to work around certain LD_PRELOAD issues seen in apps.
2038 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2039 VkInstance instance
,
2043 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2044 VkInstance instance
,
2047 return radv_GetInstanceProcAddr(instance
, pName
);
2050 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2054 return radv_lookup_entrypoint(pName
);
2057 bool radv_get_memory_fd(struct radv_device
*device
,
2058 struct radv_device_memory
*memory
,
2061 struct radeon_bo_metadata metadata
;
2063 if (memory
->image
) {
2064 radv_init_metadata(device
, memory
->image
, &metadata
);
2065 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2068 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2072 VkResult
radv_AllocateMemory(
2074 const VkMemoryAllocateInfo
* pAllocateInfo
,
2075 const VkAllocationCallbacks
* pAllocator
,
2076 VkDeviceMemory
* pMem
)
2078 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2079 struct radv_device_memory
*mem
;
2081 enum radeon_bo_domain domain
;
2084 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2086 if (pAllocateInfo
->allocationSize
== 0) {
2087 /* Apparently, this is allowed */
2088 *pMem
= VK_NULL_HANDLE
;
2092 const VkImportMemoryFdInfoKHX
*import_info
=
2093 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHX
);
2094 const VkDedicatedAllocationMemoryAllocateInfoNV
*dedicate_info
=
2095 vk_find_struct_const(pAllocateInfo
->pNext
, DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV
);
2097 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2098 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2100 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2102 if (dedicate_info
) {
2103 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2104 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2111 assert(import_info
->handleType
==
2112 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
2113 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2116 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX
;
2122 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2123 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2124 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2125 domain
= RADEON_DOMAIN_GTT
;
2127 domain
= RADEON_DOMAIN_VRAM
;
2129 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2130 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2132 flags
|= RADEON_FLAG_CPU_ACCESS
;
2134 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2135 flags
|= RADEON_FLAG_GTT_WC
;
2137 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
2141 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2144 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2146 *pMem
= radv_device_memory_to_handle(mem
);
2151 vk_free2(&device
->alloc
, pAllocator
, mem
);
2156 void radv_FreeMemory(
2158 VkDeviceMemory _mem
,
2159 const VkAllocationCallbacks
* pAllocator
)
2161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2162 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2167 device
->ws
->buffer_destroy(mem
->bo
);
2170 vk_free2(&device
->alloc
, pAllocator
, mem
);
2173 VkResult
radv_MapMemory(
2175 VkDeviceMemory _memory
,
2176 VkDeviceSize offset
,
2178 VkMemoryMapFlags flags
,
2181 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2182 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2189 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2195 return VK_ERROR_MEMORY_MAP_FAILED
;
2198 void radv_UnmapMemory(
2200 VkDeviceMemory _memory
)
2202 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2203 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2208 device
->ws
->buffer_unmap(mem
->bo
);
2211 VkResult
radv_FlushMappedMemoryRanges(
2213 uint32_t memoryRangeCount
,
2214 const VkMappedMemoryRange
* pMemoryRanges
)
2219 VkResult
radv_InvalidateMappedMemoryRanges(
2221 uint32_t memoryRangeCount
,
2222 const VkMappedMemoryRange
* pMemoryRanges
)
2227 void radv_GetBufferMemoryRequirements(
2230 VkMemoryRequirements
* pMemoryRequirements
)
2232 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2234 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2236 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2237 pMemoryRequirements
->alignment
= 4096;
2239 pMemoryRequirements
->alignment
= 16;
2241 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2244 void radv_GetImageMemoryRequirements(
2247 VkMemoryRequirements
* pMemoryRequirements
)
2249 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2251 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2253 pMemoryRequirements
->size
= image
->size
;
2254 pMemoryRequirements
->alignment
= image
->alignment
;
2257 void radv_GetImageSparseMemoryRequirements(
2260 uint32_t* pSparseMemoryRequirementCount
,
2261 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2266 void radv_GetDeviceMemoryCommitment(
2268 VkDeviceMemory memory
,
2269 VkDeviceSize
* pCommittedMemoryInBytes
)
2271 *pCommittedMemoryInBytes
= 0;
2274 VkResult
radv_BindBufferMemory(
2277 VkDeviceMemory _memory
,
2278 VkDeviceSize memoryOffset
)
2280 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2281 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2284 buffer
->bo
= mem
->bo
;
2285 buffer
->offset
= memoryOffset
;
2294 VkResult
radv_BindImageMemory(
2297 VkDeviceMemory _memory
,
2298 VkDeviceSize memoryOffset
)
2300 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2301 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2304 image
->bo
= mem
->bo
;
2305 image
->offset
= memoryOffset
;
2316 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2317 const VkSparseBufferMemoryBindInfo
*bind
)
2319 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2321 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2322 struct radv_device_memory
*mem
= NULL
;
2324 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2325 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2327 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2328 bind
->pBinds
[i
].resourceOffset
,
2329 bind
->pBinds
[i
].size
,
2330 mem
? mem
->bo
: NULL
,
2331 bind
->pBinds
[i
].memoryOffset
);
2336 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2337 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2339 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2341 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2342 struct radv_device_memory
*mem
= NULL
;
2344 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2345 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2347 device
->ws
->buffer_virtual_bind(image
->bo
,
2348 bind
->pBinds
[i
].resourceOffset
,
2349 bind
->pBinds
[i
].size
,
2350 mem
? mem
->bo
: NULL
,
2351 bind
->pBinds
[i
].memoryOffset
);
2355 VkResult
radv_QueueBindSparse(
2357 uint32_t bindInfoCount
,
2358 const VkBindSparseInfo
* pBindInfo
,
2361 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2362 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2363 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2364 bool fence_emitted
= false;
2366 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2367 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2368 radv_sparse_buffer_bind_memory(queue
->device
,
2369 pBindInfo
[i
].pBufferBinds
+ j
);
2372 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2373 radv_sparse_image_opaque_bind_memory(queue
->device
,
2374 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2377 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2378 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2379 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2381 (struct radeon_winsys_sem
**)pBindInfo
[i
].pWaitSemaphores
,
2382 pBindInfo
[i
].waitSemaphoreCount
,
2383 (struct radeon_winsys_sem
**)pBindInfo
[i
].pSignalSemaphores
,
2384 pBindInfo
[i
].signalSemaphoreCount
,
2386 fence_emitted
= true;
2388 fence
->submitted
= true;
2392 if (fence
&& !fence_emitted
) {
2393 fence
->signalled
= true;
2399 VkResult
radv_CreateFence(
2401 const VkFenceCreateInfo
* pCreateInfo
,
2402 const VkAllocationCallbacks
* pAllocator
,
2405 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2406 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2408 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2411 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2413 memset(fence
, 0, sizeof(*fence
));
2414 fence
->submitted
= false;
2415 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2416 fence
->fence
= device
->ws
->create_fence();
2417 if (!fence
->fence
) {
2418 vk_free2(&device
->alloc
, pAllocator
, fence
);
2419 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2422 *pFence
= radv_fence_to_handle(fence
);
2427 void radv_DestroyFence(
2430 const VkAllocationCallbacks
* pAllocator
)
2432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2433 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2437 device
->ws
->destroy_fence(fence
->fence
);
2438 vk_free2(&device
->alloc
, pAllocator
, fence
);
2441 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2443 uint64_t current_time
;
2446 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2447 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2449 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2451 return current_time
+ timeout
;
2454 VkResult
radv_WaitForFences(
2456 uint32_t fenceCount
,
2457 const VkFence
* pFences
,
2461 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2462 timeout
= radv_get_absolute_timeout(timeout
);
2464 if (!waitAll
&& fenceCount
> 1) {
2465 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2468 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2469 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2470 bool expired
= false;
2472 if (fence
->signalled
)
2475 if (!fence
->submitted
)
2478 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2482 fence
->signalled
= true;
2488 VkResult
radv_ResetFences(VkDevice device
,
2489 uint32_t fenceCount
,
2490 const VkFence
*pFences
)
2492 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2493 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2494 fence
->submitted
= fence
->signalled
= false;
2500 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2502 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2503 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2505 if (fence
->signalled
)
2507 if (!fence
->submitted
)
2508 return VK_NOT_READY
;
2510 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2511 return VK_NOT_READY
;
2517 // Queue semaphore functions
2519 VkResult
radv_CreateSemaphore(
2521 const VkSemaphoreCreateInfo
* pCreateInfo
,
2522 const VkAllocationCallbacks
* pAllocator
,
2523 VkSemaphore
* pSemaphore
)
2525 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2526 struct radeon_winsys_sem
*sem
;
2528 sem
= device
->ws
->create_sem(device
->ws
);
2530 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2532 *pSemaphore
= radeon_winsys_sem_to_handle(sem
);
2536 void radv_DestroySemaphore(
2538 VkSemaphore _semaphore
,
2539 const VkAllocationCallbacks
* pAllocator
)
2541 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2542 RADV_FROM_HANDLE(radeon_winsys_sem
, sem
, _semaphore
);
2546 device
->ws
->destroy_sem(sem
);
2549 VkResult
radv_CreateEvent(
2551 const VkEventCreateInfo
* pCreateInfo
,
2552 const VkAllocationCallbacks
* pAllocator
,
2555 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2556 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2558 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2561 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2563 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2565 RADEON_FLAG_CPU_ACCESS
);
2567 vk_free2(&device
->alloc
, pAllocator
, event
);
2568 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2571 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2573 *pEvent
= radv_event_to_handle(event
);
2578 void radv_DestroyEvent(
2581 const VkAllocationCallbacks
* pAllocator
)
2583 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2584 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2588 device
->ws
->buffer_destroy(event
->bo
);
2589 vk_free2(&device
->alloc
, pAllocator
, event
);
2592 VkResult
radv_GetEventStatus(
2596 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2598 if (*event
->map
== 1)
2599 return VK_EVENT_SET
;
2600 return VK_EVENT_RESET
;
2603 VkResult
radv_SetEvent(
2607 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2613 VkResult
radv_ResetEvent(
2617 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2623 VkResult
radv_CreateBuffer(
2625 const VkBufferCreateInfo
* pCreateInfo
,
2626 const VkAllocationCallbacks
* pAllocator
,
2629 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2630 struct radv_buffer
*buffer
;
2632 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2634 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2635 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2637 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2639 buffer
->size
= pCreateInfo
->size
;
2640 buffer
->usage
= pCreateInfo
->usage
;
2643 buffer
->flags
= pCreateInfo
->flags
;
2645 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2646 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2647 align64(buffer
->size
, 4096),
2648 4096, 0, RADEON_FLAG_VIRTUAL
);
2650 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2651 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2655 *pBuffer
= radv_buffer_to_handle(buffer
);
2660 void radv_DestroyBuffer(
2663 const VkAllocationCallbacks
* pAllocator
)
2665 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2666 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2671 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2672 device
->ws
->buffer_destroy(buffer
->bo
);
2674 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2677 static inline unsigned
2678 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2681 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2683 return image
->surface
.u
.legacy
.tiling_index
[level
];
2686 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2688 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2692 radv_initialise_color_surface(struct radv_device
*device
,
2693 struct radv_color_buffer_info
*cb
,
2694 struct radv_image_view
*iview
)
2696 const struct vk_format_description
*desc
;
2697 unsigned ntype
, format
, swap
, endian
;
2698 unsigned blend_clamp
= 0, blend_bypass
= 0;
2700 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2702 desc
= vk_format_description(iview
->vk_format
);
2704 memset(cb
, 0, sizeof(*cb
));
2706 /* Intensity is implemented as Red, so treat it that way. */
2707 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2709 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2711 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2712 struct gfx9_surf_meta_flags meta
;
2713 if (iview
->image
->dcc_offset
)
2714 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
2716 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
2718 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2719 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2720 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2721 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2723 va
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
2725 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2726 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2728 va
+= level_info
->offset
;
2730 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2731 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2732 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2734 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2735 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2736 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2738 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2739 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2741 if (iview
->image
->fmask
.size
) {
2742 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2743 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2744 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2745 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2747 /* This must be set for fast clear to work without FMASK. */
2748 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2749 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2750 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2751 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2755 cb
->cb_color_base
= va
>> 8;
2757 /* CMASK variables */
2758 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2759 va
+= iview
->image
->cmask
.offset
;
2760 cb
->cb_color_cmask
= va
>> 8;
2762 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2763 va
+= iview
->image
->dcc_offset
;
2764 cb
->cb_dcc_base
= va
>> 8;
2766 uint32_t max_slice
= radv_surface_layer_count(iview
);
2767 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2768 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2770 if (iview
->image
->info
.samples
> 1) {
2771 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2773 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2774 S_028C74_NUM_FRAGMENTS(log_samples
);
2777 if (iview
->image
->fmask
.size
) {
2778 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2779 cb
->cb_color_fmask
= va
>> 8;
2781 cb
->cb_color_fmask
= cb
->cb_color_base
;
2784 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2786 vk_format_get_first_non_void_channel(iview
->vk_format
));
2787 format
= radv_translate_colorformat(iview
->vk_format
);
2788 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2789 radv_finishme("Illegal color\n");
2790 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2791 endian
= radv_colorformat_endian_swap(format
);
2793 /* blend clamp should be set for all NORM/SRGB types */
2794 if (ntype
== V_028C70_NUMBER_UNORM
||
2795 ntype
== V_028C70_NUMBER_SNORM
||
2796 ntype
== V_028C70_NUMBER_SRGB
)
2799 /* set blend bypass according to docs if SINT/UINT or
2800 8/24 COLOR variants */
2801 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2802 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2803 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2808 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2809 (format
== V_028C70_COLOR_8
||
2810 format
== V_028C70_COLOR_8_8
||
2811 format
== V_028C70_COLOR_8_8_8_8
))
2812 ->color_is_int8
= true;
2814 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2815 S_028C70_COMP_SWAP(swap
) |
2816 S_028C70_BLEND_CLAMP(blend_clamp
) |
2817 S_028C70_BLEND_BYPASS(blend_bypass
) |
2818 S_028C70_SIMPLE_FLOAT(1) |
2819 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2820 ntype
!= V_028C70_NUMBER_SNORM
&&
2821 ntype
!= V_028C70_NUMBER_SRGB
&&
2822 format
!= V_028C70_COLOR_8_24
&&
2823 format
!= V_028C70_COLOR_24_8
) |
2824 S_028C70_NUMBER_TYPE(ntype
) |
2825 S_028C70_ENDIAN(endian
);
2826 if (iview
->image
->info
.samples
> 1)
2827 if (iview
->image
->fmask
.size
)
2828 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2830 if (iview
->image
->cmask
.size
&&
2831 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2832 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2834 if (iview
->image
->surface
.dcc_size
&& iview
->base_mip
< surf
->num_dcc_levels
)
2835 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2837 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2838 unsigned max_uncompressed_block_size
= 2;
2839 if (iview
->image
->info
.samples
> 1) {
2840 if (iview
->image
->surface
.bpe
== 1)
2841 max_uncompressed_block_size
= 0;
2842 else if (iview
->image
->surface
.bpe
== 2)
2843 max_uncompressed_block_size
= 1;
2846 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2847 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2850 /* This must be set for fast clear to work without FMASK. */
2851 if (!iview
->image
->fmask
.size
&&
2852 device
->physical_device
->rad_info
.chip_class
== SI
) {
2853 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
2854 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2857 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2858 uint32_t max_slice
= radv_surface_layer_count(iview
);
2859 unsigned mip0_depth
= iview
->base_layer
+ max_slice
- 1;
2861 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
2862 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2863 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
2864 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->image
->info
.width
- 1) |
2865 S_028C68_MIP0_HEIGHT(iview
->image
->info
.height
- 1) |
2866 S_028C68_MAX_MIP(iview
->image
->info
.levels
);
2868 cb
->gfx9_epitch
= S_0287A0_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
2874 radv_initialise_ds_surface(struct radv_device
*device
,
2875 struct radv_ds_buffer_info
*ds
,
2876 struct radv_image_view
*iview
)
2878 unsigned level
= iview
->base_mip
;
2879 unsigned format
, stencil_format
;
2880 uint64_t va
, s_offs
, z_offs
;
2881 bool stencil_only
= false;
2882 memset(ds
, 0, sizeof(*ds
));
2883 switch (iview
->image
->vk_format
) {
2884 case VK_FORMAT_D24_UNORM_S8_UINT
:
2885 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2886 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2887 ds
->offset_scale
= 2.0f
;
2889 case VK_FORMAT_D16_UNORM
:
2890 case VK_FORMAT_D16_UNORM_S8_UINT
:
2891 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2892 ds
->offset_scale
= 4.0f
;
2894 case VK_FORMAT_D32_SFLOAT
:
2895 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2896 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2897 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2898 ds
->offset_scale
= 1.0f
;
2900 case VK_FORMAT_S8_UINT
:
2901 stencil_only
= true;
2907 format
= radv_translate_dbformat(iview
->image
->vk_format
);
2908 stencil_format
= iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
?
2909 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2911 uint32_t max_slice
= radv_surface_layer_count(iview
);
2912 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2913 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2915 ds
->db_htile_data_base
= 0;
2916 ds
->db_htile_surface
= 0;
2918 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2919 s_offs
= z_offs
= va
;
2921 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2922 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
2923 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
2925 ds
->db_z_info
= S_028038_FORMAT(format
) |
2926 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
2927 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2928 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
2929 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
2930 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2932 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
2933 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
2934 ds
->db_depth_view
|= S_028008_MIPID(level
);
2936 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
2937 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
2939 /* Only use HTILE for the first level. */
2940 if (iview
->image
->surface
.htile_size
&& !level
) {
2941 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
2943 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
2944 /* Use all of the htile_buffer for depth if there's no stencil. */
2945 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2946 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2947 iview
->image
->htile_offset
;
2948 ds
->db_htile_data_base
= va
>> 8;
2949 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2950 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2951 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
2954 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
2957 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
2959 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
2960 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
2962 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2963 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2964 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
2966 if (iview
->image
->info
.samples
> 1)
2967 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
2969 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2970 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2971 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
2972 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2973 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
2974 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2975 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2976 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2979 tile_mode
= stencil_tile_mode
;
2981 ds
->db_depth_info
|=
2982 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2983 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2984 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2985 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2986 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2987 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2988 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2989 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2991 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2992 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2993 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2994 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2997 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2998 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2999 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
3001 if (iview
->image
->surface
.htile_size
&& !level
) {
3002 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
3004 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
3005 /* Use all of the htile_buffer for depth if there's no stencil. */
3006 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3008 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3009 iview
->image
->htile_offset
;
3010 ds
->db_htile_data_base
= va
>> 8;
3011 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3015 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3016 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3019 VkResult
radv_CreateFramebuffer(
3021 const VkFramebufferCreateInfo
* pCreateInfo
,
3022 const VkAllocationCallbacks
* pAllocator
,
3023 VkFramebuffer
* pFramebuffer
)
3025 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3026 struct radv_framebuffer
*framebuffer
;
3028 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3030 size_t size
= sizeof(*framebuffer
) +
3031 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3032 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3033 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3034 if (framebuffer
== NULL
)
3035 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3037 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3038 framebuffer
->width
= pCreateInfo
->width
;
3039 framebuffer
->height
= pCreateInfo
->height
;
3040 framebuffer
->layers
= pCreateInfo
->layers
;
3041 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3042 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3043 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3044 framebuffer
->attachments
[i
].attachment
= iview
;
3045 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3046 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3047 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3048 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3050 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3051 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3052 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3055 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3059 void radv_DestroyFramebuffer(
3062 const VkAllocationCallbacks
* pAllocator
)
3064 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3065 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3069 vk_free2(&device
->alloc
, pAllocator
, fb
);
3072 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3074 switch (address_mode
) {
3075 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3076 return V_008F30_SQ_TEX_WRAP
;
3077 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3078 return V_008F30_SQ_TEX_MIRROR
;
3079 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3080 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3081 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3082 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3083 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3084 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3086 unreachable("illegal tex wrap mode");
3092 radv_tex_compare(VkCompareOp op
)
3095 case VK_COMPARE_OP_NEVER
:
3096 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3097 case VK_COMPARE_OP_LESS
:
3098 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3099 case VK_COMPARE_OP_EQUAL
:
3100 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3101 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3102 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3103 case VK_COMPARE_OP_GREATER
:
3104 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3105 case VK_COMPARE_OP_NOT_EQUAL
:
3106 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3107 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3108 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3109 case VK_COMPARE_OP_ALWAYS
:
3110 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3112 unreachable("illegal compare mode");
3118 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3121 case VK_FILTER_NEAREST
:
3122 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3123 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3124 case VK_FILTER_LINEAR
:
3125 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3126 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3127 case VK_FILTER_CUBIC_IMG
:
3129 fprintf(stderr
, "illegal texture filter");
3135 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3138 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3139 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3140 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3141 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3143 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3148 radv_tex_bordercolor(VkBorderColor bcolor
)
3151 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3152 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3153 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3154 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3155 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3156 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3157 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3158 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3159 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3167 radv_tex_aniso_filter(unsigned filter
)
3181 radv_init_sampler(struct radv_device
*device
,
3182 struct radv_sampler
*sampler
,
3183 const VkSamplerCreateInfo
*pCreateInfo
)
3185 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3186 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3187 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3188 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3190 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3191 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3192 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3193 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3194 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3195 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3196 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3197 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3198 S_008F30_DISABLE_CUBE_WRAP(0) |
3199 S_008F30_COMPAT_MODE(is_vi
));
3200 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3201 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3202 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3203 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3204 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3205 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3206 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3207 S_008F38_MIP_POINT_PRECLAMP(0) |
3208 S_008F38_DISABLE_LSB_CEIL(1) |
3209 S_008F38_FILTER_PREC_FIX(1) |
3210 S_008F38_ANISO_OVERRIDE(is_vi
));
3211 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3212 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3215 VkResult
radv_CreateSampler(
3217 const VkSamplerCreateInfo
* pCreateInfo
,
3218 const VkAllocationCallbacks
* pAllocator
,
3219 VkSampler
* pSampler
)
3221 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3222 struct radv_sampler
*sampler
;
3224 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3226 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3231 radv_init_sampler(device
, sampler
, pCreateInfo
);
3232 *pSampler
= radv_sampler_to_handle(sampler
);
3237 void radv_DestroySampler(
3240 const VkAllocationCallbacks
* pAllocator
)
3242 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3243 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3247 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3250 /* vk_icd.h does not declare this function, so we declare it here to
3251 * suppress Wmissing-prototypes.
3253 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3254 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3256 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3257 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3259 /* For the full details on loader interface versioning, see
3260 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3261 * What follows is a condensed summary, to help you navigate the large and
3262 * confusing official doc.
3264 * - Loader interface v0 is incompatible with later versions. We don't
3267 * - In loader interface v1:
3268 * - The first ICD entrypoint called by the loader is
3269 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3271 * - The ICD must statically expose no other Vulkan symbol unless it is
3272 * linked with -Bsymbolic.
3273 * - Each dispatchable Vulkan handle created by the ICD must be
3274 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3275 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3276 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3277 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3278 * such loader-managed surfaces.
3280 * - Loader interface v2 differs from v1 in:
3281 * - The first ICD entrypoint called by the loader is
3282 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3283 * statically expose this entrypoint.
3285 * - Loader interface v3 differs from v2 in:
3286 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3287 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3288 * because the loader no longer does so.
3290 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3294 VkResult
radv_GetMemoryFdKHX(VkDevice _device
,
3295 VkDeviceMemory _memory
,
3296 VkExternalMemoryHandleTypeFlagsKHX handleType
,
3299 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3300 RADV_FROM_HANDLE(radv_device_memory
, memory
, _memory
);
3302 /* We support only one handle type. */
3303 assert(handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
3305 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3307 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3311 VkResult
radv_GetMemoryFdPropertiesKHX(VkDevice _device
,
3312 VkExternalMemoryHandleTypeFlagBitsKHX handleType
,
3314 VkMemoryFdPropertiesKHX
*pMemoryFdProperties
)
3316 /* The valid usage section for this function says:
3318 * "handleType must not be one of the handle types defined as opaque."
3320 * Since we only handle opaque handles for now, there are no FD properties.
3322 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX
;