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radv: replace memset()+strcpy() with snprintf()
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
367
368 /* Out-of-order primitive rasterization. */
369 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
370 device->rad_info.max_se >= 2;
371 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
372 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
373
374 device->dcc_msaa_allowed =
375 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
376
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
379 (device->rad_info.chip_class >= GFX8 &&
380 device->rad_info.me_fw_feature >= 41);
381
382 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
383 device->rad_info.chip_class >= GFX10;
384
385 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
386
387 radv_physical_device_init_mem_types(device);
388 radv_fill_device_extension_table(device, &device->supported_extensions);
389
390 device->bus_info = *drm_device->businfo.pci;
391
392 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
393 ac_print_gpu_info(&device->rad_info);
394
395 /* The WSI is structured as a layer on top of the driver, so this has
396 * to be the last part of initialization (at least until we get other
397 * semi-layers).
398 */
399 result = radv_init_wsi(device);
400 if (result != VK_SUCCESS) {
401 device->ws->destroy(device->ws);
402 vk_error(instance, result);
403 goto fail;
404 }
405
406 return VK_SUCCESS;
407
408 fail:
409 close(fd);
410 if (master_fd != -1)
411 close(master_fd);
412 return result;
413 }
414
415 static void
416 radv_physical_device_finish(struct radv_physical_device *device)
417 {
418 radv_finish_wsi(device);
419 device->ws->destroy(device->ws);
420 disk_cache_destroy(device->disk_cache);
421 close(device->local_fd);
422 if (device->master_fd != -1)
423 close(device->master_fd);
424 }
425
426 static void *
427 default_alloc_func(void *pUserData, size_t size, size_t align,
428 VkSystemAllocationScope allocationScope)
429 {
430 return malloc(size);
431 }
432
433 static void *
434 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
435 size_t align, VkSystemAllocationScope allocationScope)
436 {
437 return realloc(pOriginal, size);
438 }
439
440 static void
441 default_free_func(void *pUserData, void *pMemory)
442 {
443 free(pMemory);
444 }
445
446 static const VkAllocationCallbacks default_alloc = {
447 .pUserData = NULL,
448 .pfnAllocation = default_alloc_func,
449 .pfnReallocation = default_realloc_func,
450 .pfnFree = default_free_func,
451 };
452
453 static const struct debug_control radv_debug_options[] = {
454 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
455 {"nodcc", RADV_DEBUG_NO_DCC},
456 {"shaders", RADV_DEBUG_DUMP_SHADERS},
457 {"nocache", RADV_DEBUG_NO_CACHE},
458 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
459 {"nohiz", RADV_DEBUG_NO_HIZ},
460 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
461 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
462 {"allbos", RADV_DEBUG_ALL_BOS},
463 {"noibs", RADV_DEBUG_NO_IBS},
464 {"spirv", RADV_DEBUG_DUMP_SPIRV},
465 {"vmfaults", RADV_DEBUG_VM_FAULTS},
466 {"zerovram", RADV_DEBUG_ZERO_VRAM},
467 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
468 {"nosisched", RADV_DEBUG_NO_SISCHED},
469 {"preoptir", RADV_DEBUG_PREOPTIR},
470 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
471 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
472 {"info", RADV_DEBUG_INFO},
473 {"errors", RADV_DEBUG_ERRORS},
474 {"startup", RADV_DEBUG_STARTUP},
475 {"checkir", RADV_DEBUG_CHECKIR},
476 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
477 {"nobinning", RADV_DEBUG_NOBINNING},
478 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
479 {"nongg", RADV_DEBUG_NO_NGG},
480 {NULL, 0}
481 };
482
483 const char *
484 radv_get_debug_option_name(int id)
485 {
486 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
487 return radv_debug_options[id].string;
488 }
489
490 static const struct debug_control radv_perftest_options[] = {
491 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
492 {"sisched", RADV_PERFTEST_SISCHED},
493 {"localbos", RADV_PERFTEST_LOCAL_BOS},
494 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
495 {"bolist", RADV_PERFTEST_BO_LIST},
496 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
497 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
498 {NULL, 0}
499 };
500
501 const char *
502 radv_get_perftest_option_name(int id)
503 {
504 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
505 return radv_perftest_options[id].string;
506 }
507
508 static void
509 radv_handle_per_app_options(struct radv_instance *instance,
510 const VkApplicationInfo *info)
511 {
512 const char *name = info ? info->pApplicationName : NULL;
513
514 if (!name)
515 return;
516
517 if (!strcmp(name, "Talos - Linux - 32bit") ||
518 !strcmp(name, "Talos - Linux - 64bit")) {
519 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
520 /* Force enable LLVM sisched for Talos because it looks
521 * safe and it gives few more FPS.
522 */
523 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
524 }
525 } else if (!strcmp(name, "DOOM_VFR")) {
526 /* Work around a Doom VFR game bug */
527 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
528 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
529 /* Workaround for a WaW hazard when LLVM moves/merges
530 * load/store memory operations.
531 * See https://reviews.llvm.org/D61313
532 */
533 if (HAVE_LLVM < 0x900)
534 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
535 }
536 }
537
538 static int radv_get_instance_extension_index(const char *name)
539 {
540 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
541 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
542 return i;
543 }
544 return -1;
545 }
546
547 static const char radv_dri_options_xml[] =
548 DRI_CONF_BEGIN
549 DRI_CONF_SECTION_QUALITY
550 DRI_CONF_ADAPTIVE_SYNC("true")
551 DRI_CONF_SECTION_END
552 DRI_CONF_END;
553
554 static void radv_init_dri_options(struct radv_instance *instance)
555 {
556 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
557 driParseConfigFiles(&instance->dri_options,
558 &instance->available_dri_options,
559 0, "radv", NULL);
560 }
561
562 VkResult radv_CreateInstance(
563 const VkInstanceCreateInfo* pCreateInfo,
564 const VkAllocationCallbacks* pAllocator,
565 VkInstance* pInstance)
566 {
567 struct radv_instance *instance;
568 VkResult result;
569
570 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
571
572 uint32_t client_version;
573 if (pCreateInfo->pApplicationInfo &&
574 pCreateInfo->pApplicationInfo->apiVersion != 0) {
575 client_version = pCreateInfo->pApplicationInfo->apiVersion;
576 } else {
577 client_version = VK_API_VERSION_1_0;
578 }
579
580 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
581 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
582 if (!instance)
583 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
584
585 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
586
587 if (pAllocator)
588 instance->alloc = *pAllocator;
589 else
590 instance->alloc = default_alloc;
591
592 instance->apiVersion = client_version;
593 instance->physicalDeviceCount = -1;
594
595 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
596 radv_debug_options);
597
598 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
599 radv_perftest_options);
600
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Created an instance");
604
605 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
606 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
607 int index = radv_get_instance_extension_index(ext_name);
608
609 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
610 vk_free2(&default_alloc, pAllocator, instance);
611 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
612 }
613
614 instance->enabled_extensions.extensions[index] = true;
615 }
616
617 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
618 if (result != VK_SUCCESS) {
619 vk_free2(&default_alloc, pAllocator, instance);
620 return vk_error(instance, result);
621 }
622
623 _mesa_locale_init();
624 glsl_type_singleton_init_or_ref();
625
626 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
627
628 radv_init_dri_options(instance);
629 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
630
631 *pInstance = radv_instance_to_handle(instance);
632
633 return VK_SUCCESS;
634 }
635
636 void radv_DestroyInstance(
637 VkInstance _instance,
638 const VkAllocationCallbacks* pAllocator)
639 {
640 RADV_FROM_HANDLE(radv_instance, instance, _instance);
641
642 if (!instance)
643 return;
644
645 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
646 radv_physical_device_finish(instance->physicalDevices + i);
647 }
648
649 VG(VALGRIND_DESTROY_MEMPOOL(instance));
650
651 glsl_type_singleton_decref();
652 _mesa_locale_fini();
653
654 driDestroyOptionCache(&instance->dri_options);
655 driDestroyOptionInfo(&instance->available_dri_options);
656
657 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
658
659 vk_free(&instance->alloc, instance);
660 }
661
662 static VkResult
663 radv_enumerate_devices(struct radv_instance *instance)
664 {
665 /* TODO: Check for more devices ? */
666 drmDevicePtr devices[8];
667 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
668 int max_devices;
669
670 instance->physicalDeviceCount = 0;
671
672 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
673
674 if (instance->debug_flags & RADV_DEBUG_STARTUP)
675 radv_logi("Found %d drm nodes", max_devices);
676
677 if (max_devices < 1)
678 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
679
680 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
681 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
682 devices[i]->bustype == DRM_BUS_PCI &&
683 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
684
685 result = radv_physical_device_init(instance->physicalDevices +
686 instance->physicalDeviceCount,
687 instance,
688 devices[i]);
689 if (result == VK_SUCCESS)
690 ++instance->physicalDeviceCount;
691 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 break;
693 }
694 }
695 drmFreeDevices(devices, max_devices);
696
697 return result;
698 }
699
700 VkResult radv_EnumeratePhysicalDevices(
701 VkInstance _instance,
702 uint32_t* pPhysicalDeviceCount,
703 VkPhysicalDevice* pPhysicalDevices)
704 {
705 RADV_FROM_HANDLE(radv_instance, instance, _instance);
706 VkResult result;
707
708 if (instance->physicalDeviceCount < 0) {
709 result = radv_enumerate_devices(instance);
710 if (result != VK_SUCCESS &&
711 result != VK_ERROR_INCOMPATIBLE_DRIVER)
712 return result;
713 }
714
715 if (!pPhysicalDevices) {
716 *pPhysicalDeviceCount = instance->physicalDeviceCount;
717 } else {
718 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
719 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
720 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
721 }
722
723 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
724 : VK_SUCCESS;
725 }
726
727 VkResult radv_EnumeratePhysicalDeviceGroups(
728 VkInstance _instance,
729 uint32_t* pPhysicalDeviceGroupCount,
730 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
731 {
732 RADV_FROM_HANDLE(radv_instance, instance, _instance);
733 VkResult result;
734
735 if (instance->physicalDeviceCount < 0) {
736 result = radv_enumerate_devices(instance);
737 if (result != VK_SUCCESS &&
738 result != VK_ERROR_INCOMPATIBLE_DRIVER)
739 return result;
740 }
741
742 if (!pPhysicalDeviceGroupProperties) {
743 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
744 } else {
745 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
746 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
747 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
748 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
749 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
750 }
751 }
752 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
753 : VK_SUCCESS;
754 }
755
756 void radv_GetPhysicalDeviceFeatures(
757 VkPhysicalDevice physicalDevice,
758 VkPhysicalDeviceFeatures* pFeatures)
759 {
760 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
761 memset(pFeatures, 0, sizeof(*pFeatures));
762
763 *pFeatures = (VkPhysicalDeviceFeatures) {
764 .robustBufferAccess = true,
765 .fullDrawIndexUint32 = true,
766 .imageCubeArray = true,
767 .independentBlend = true,
768 .geometryShader = true,
769 .tessellationShader = true,
770 .sampleRateShading = true,
771 .dualSrcBlend = true,
772 .logicOp = true,
773 .multiDrawIndirect = true,
774 .drawIndirectFirstInstance = true,
775 .depthClamp = true,
776 .depthBiasClamp = true,
777 .fillModeNonSolid = true,
778 .depthBounds = true,
779 .wideLines = true,
780 .largePoints = true,
781 .alphaToOne = true,
782 .multiViewport = true,
783 .samplerAnisotropy = true,
784 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
785 .textureCompressionASTC_LDR = false,
786 .textureCompressionBC = true,
787 .occlusionQueryPrecise = true,
788 .pipelineStatisticsQuery = true,
789 .vertexPipelineStoresAndAtomics = true,
790 .fragmentStoresAndAtomics = true,
791 .shaderTessellationAndGeometryPointSize = true,
792 .shaderImageGatherExtended = true,
793 .shaderStorageImageExtendedFormats = true,
794 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
795 .shaderUniformBufferArrayDynamicIndexing = true,
796 .shaderSampledImageArrayDynamicIndexing = true,
797 .shaderStorageBufferArrayDynamicIndexing = true,
798 .shaderStorageImageArrayDynamicIndexing = true,
799 .shaderStorageImageReadWithoutFormat = true,
800 .shaderStorageImageWriteWithoutFormat = true,
801 .shaderClipDistance = true,
802 .shaderCullDistance = true,
803 .shaderFloat64 = true,
804 .shaderInt64 = true,
805 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
806 .sparseBinding = true,
807 .variableMultisampleRate = true,
808 .inheritedQueries = true,
809 };
810 }
811
812 void radv_GetPhysicalDeviceFeatures2(
813 VkPhysicalDevice physicalDevice,
814 VkPhysicalDeviceFeatures2 *pFeatures)
815 {
816 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
817 vk_foreach_struct(ext, pFeatures->pNext) {
818 switch (ext->sType) {
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
820 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
821 features->variablePointersStorageBuffer = true;
822 features->variablePointers = true;
823 break;
824 }
825 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
826 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
827 features->multiview = true;
828 features->multiviewGeometryShader = true;
829 features->multiviewTessellationShader = true;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
833 VkPhysicalDeviceShaderDrawParametersFeatures *features =
834 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
835 features->shaderDrawParameters = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
839 VkPhysicalDeviceProtectedMemoryFeatures *features =
840 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
841 features->protectedMemory = false;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
845 VkPhysicalDevice16BitStorageFeatures *features =
846 (VkPhysicalDevice16BitStorageFeatures*)ext;
847 bool enabled = pdevice->rad_info.chip_class >= GFX8;
848 features->storageBuffer16BitAccess = enabled;
849 features->uniformAndStorageBuffer16BitAccess = enabled;
850 features->storagePushConstant16 = enabled;
851 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
852 break;
853 }
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
855 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
856 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
857 features->samplerYcbcrConversion = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
861 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
862 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
863 features->shaderInputAttachmentArrayDynamicIndexing = true;
864 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
865 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
866 features->shaderUniformBufferArrayNonUniformIndexing = true;
867 features->shaderSampledImageArrayNonUniformIndexing = true;
868 features->shaderStorageBufferArrayNonUniformIndexing = true;
869 features->shaderStorageImageArrayNonUniformIndexing = true;
870 features->shaderInputAttachmentArrayNonUniformIndexing = true;
871 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
872 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
873 features->descriptorBindingUniformBufferUpdateAfterBind = true;
874 features->descriptorBindingSampledImageUpdateAfterBind = true;
875 features->descriptorBindingStorageImageUpdateAfterBind = true;
876 features->descriptorBindingStorageBufferUpdateAfterBind = true;
877 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
878 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
879 features->descriptorBindingUpdateUnusedWhilePending = true;
880 features->descriptorBindingPartiallyBound = true;
881 features->descriptorBindingVariableDescriptorCount = true;
882 features->runtimeDescriptorArray = true;
883 break;
884 }
885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
886 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
887 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
888 features->conditionalRendering = true;
889 features->inheritedConditionalRendering = false;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
893 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
894 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
895 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
896 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
897 break;
898 }
899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
900 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
901 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
902 features->transformFeedback = true;
903 features->geometryStreams = true;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
907 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
908 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
909 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
910 break;
911 }
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
913 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
914 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
915 features->memoryPriority = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
919 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
920 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
921 features->bufferDeviceAddress = true;
922 features->bufferDeviceAddressCaptureReplay = false;
923 features->bufferDeviceAddressMultiDevice = false;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
927 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
928 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
929 features->depthClipEnable = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
933 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
934 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
935 features->hostQueryReset = true;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
939 VkPhysicalDevice8BitStorageFeaturesKHR *features =
940 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
941 bool enabled = pdevice->rad_info.chip_class >= GFX8;
942 features->storageBuffer8BitAccess = enabled;
943 features->uniformAndStorageBuffer8BitAccess = enabled;
944 features->storagePushConstant8 = enabled;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
948 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
949 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
950 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
951 features->shaderInt8 = true;
952 break;
953 }
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
955 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
956 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
957 /* TODO: Enable this once the driver supports 64-bit
958 * compare&swap atomic operations.
959 */
960 features->shaderBufferInt64Atomics = false;
961 features->shaderSharedInt64Atomics = false;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
965 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
966 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
967
968 features->inlineUniformBlock = true;
969 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
973 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
974 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
975 features->computeDerivativeGroupQuads = false;
976 features->computeDerivativeGroupLinear = true;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
980 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
981 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
982 features->ycbcrImageArrays = true;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
986 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
987 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
988 features->uniformBufferStandardLayout = true;
989 break;
990 }
991 default:
992 break;
993 }
994 }
995 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
996 }
997
998 void radv_GetPhysicalDeviceProperties(
999 VkPhysicalDevice physicalDevice,
1000 VkPhysicalDeviceProperties* pProperties)
1001 {
1002 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1003 VkSampleCountFlags sample_counts = 0xf;
1004
1005 /* make sure that the entire descriptor set is addressable with a signed
1006 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1007 * be at most 2 GiB. the combined image & samples object count as one of
1008 * both. This limit is for the pipeline layout, not for the set layout, but
1009 * there is no set limit, so we just set a pipeline limit. I don't think
1010 * any app is going to hit this soon. */
1011 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1012 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1013 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1014 32 /* sampler, largest when combined with image */ +
1015 64 /* sampled image */ +
1016 64 /* storage image */);
1017
1018 VkPhysicalDeviceLimits limits = {
1019 .maxImageDimension1D = (1 << 14),
1020 .maxImageDimension2D = (1 << 14),
1021 .maxImageDimension3D = (1 << 11),
1022 .maxImageDimensionCube = (1 << 14),
1023 .maxImageArrayLayers = (1 << 11),
1024 .maxTexelBufferElements = 128 * 1024 * 1024,
1025 .maxUniformBufferRange = UINT32_MAX,
1026 .maxStorageBufferRange = UINT32_MAX,
1027 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1028 .maxMemoryAllocationCount = UINT32_MAX,
1029 .maxSamplerAllocationCount = 64 * 1024,
1030 .bufferImageGranularity = 64, /* A cache line */
1031 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1032 .maxBoundDescriptorSets = MAX_SETS,
1033 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1034 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1035 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1036 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1037 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1038 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1039 .maxPerStageResources = max_descriptor_set_size,
1040 .maxDescriptorSetSamplers = max_descriptor_set_size,
1041 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1042 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1043 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1044 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1045 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1046 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1047 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1048 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1049 .maxVertexInputBindings = MAX_VBS,
1050 .maxVertexInputAttributeOffset = 2047,
1051 .maxVertexInputBindingStride = 2048,
1052 .maxVertexOutputComponents = 128,
1053 .maxTessellationGenerationLevel = 64,
1054 .maxTessellationPatchSize = 32,
1055 .maxTessellationControlPerVertexInputComponents = 128,
1056 .maxTessellationControlPerVertexOutputComponents = 128,
1057 .maxTessellationControlPerPatchOutputComponents = 120,
1058 .maxTessellationControlTotalOutputComponents = 4096,
1059 .maxTessellationEvaluationInputComponents = 128,
1060 .maxTessellationEvaluationOutputComponents = 128,
1061 .maxGeometryShaderInvocations = 127,
1062 .maxGeometryInputComponents = 64,
1063 .maxGeometryOutputComponents = 128,
1064 .maxGeometryOutputVertices = 256,
1065 .maxGeometryTotalOutputComponents = 1024,
1066 .maxFragmentInputComponents = 128,
1067 .maxFragmentOutputAttachments = 8,
1068 .maxFragmentDualSrcAttachments = 1,
1069 .maxFragmentCombinedOutputResources = 8,
1070 .maxComputeSharedMemorySize = 32768,
1071 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1072 .maxComputeWorkGroupInvocations = 2048,
1073 .maxComputeWorkGroupSize = {
1074 2048,
1075 2048,
1076 2048
1077 },
1078 .subPixelPrecisionBits = 8,
1079 .subTexelPrecisionBits = 8,
1080 .mipmapPrecisionBits = 8,
1081 .maxDrawIndexedIndexValue = UINT32_MAX,
1082 .maxDrawIndirectCount = UINT32_MAX,
1083 .maxSamplerLodBias = 16,
1084 .maxSamplerAnisotropy = 16,
1085 .maxViewports = MAX_VIEWPORTS,
1086 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1087 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1088 .viewportSubPixelBits = 8,
1089 .minMemoryMapAlignment = 4096, /* A page */
1090 .minTexelBufferOffsetAlignment = 1,
1091 .minUniformBufferOffsetAlignment = 4,
1092 .minStorageBufferOffsetAlignment = 4,
1093 .minTexelOffset = -32,
1094 .maxTexelOffset = 31,
1095 .minTexelGatherOffset = -32,
1096 .maxTexelGatherOffset = 31,
1097 .minInterpolationOffset = -2,
1098 .maxInterpolationOffset = 2,
1099 .subPixelInterpolationOffsetBits = 8,
1100 .maxFramebufferWidth = (1 << 14),
1101 .maxFramebufferHeight = (1 << 14),
1102 .maxFramebufferLayers = (1 << 10),
1103 .framebufferColorSampleCounts = sample_counts,
1104 .framebufferDepthSampleCounts = sample_counts,
1105 .framebufferStencilSampleCounts = sample_counts,
1106 .framebufferNoAttachmentsSampleCounts = sample_counts,
1107 .maxColorAttachments = MAX_RTS,
1108 .sampledImageColorSampleCounts = sample_counts,
1109 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1110 .sampledImageDepthSampleCounts = sample_counts,
1111 .sampledImageStencilSampleCounts = sample_counts,
1112 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1113 .maxSampleMaskWords = 1,
1114 .timestampComputeAndGraphics = true,
1115 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1116 .maxClipDistances = 8,
1117 .maxCullDistances = 8,
1118 .maxCombinedClipAndCullDistances = 8,
1119 .discreteQueuePriorities = 2,
1120 .pointSizeRange = { 0.0, 8192.0 },
1121 .lineWidthRange = { 0.0, 7.9921875 },
1122 .pointSizeGranularity = (1.0 / 8.0),
1123 .lineWidthGranularity = (1.0 / 128.0),
1124 .strictLines = false, /* FINISHME */
1125 .standardSampleLocations = true,
1126 .optimalBufferCopyOffsetAlignment = 128,
1127 .optimalBufferCopyRowPitchAlignment = 128,
1128 .nonCoherentAtomSize = 64,
1129 };
1130
1131 *pProperties = (VkPhysicalDeviceProperties) {
1132 .apiVersion = radv_physical_device_api_version(pdevice),
1133 .driverVersion = vk_get_driver_version(),
1134 .vendorID = ATI_VENDOR_ID,
1135 .deviceID = pdevice->rad_info.pci_id,
1136 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1137 .limits = limits,
1138 .sparseProperties = {0},
1139 };
1140
1141 strcpy(pProperties->deviceName, pdevice->name);
1142 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1143 }
1144
1145 void radv_GetPhysicalDeviceProperties2(
1146 VkPhysicalDevice physicalDevice,
1147 VkPhysicalDeviceProperties2 *pProperties)
1148 {
1149 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1150 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1151
1152 vk_foreach_struct(ext, pProperties->pNext) {
1153 switch (ext->sType) {
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1155 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1156 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1157 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1161 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1162 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1163 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1164 properties->deviceLUIDValid = false;
1165 break;
1166 }
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1168 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1169 properties->maxMultiviewViewCount = MAX_VIEWS;
1170 properties->maxMultiviewInstanceIndex = INT_MAX;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1174 VkPhysicalDevicePointClippingProperties *properties =
1175 (VkPhysicalDevicePointClippingProperties*)ext;
1176 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1180 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1181 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1182 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1186 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1187 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1188 properties->minImportedHostPointerAlignment = 4096;
1189 break;
1190 }
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1192 VkPhysicalDeviceSubgroupProperties *properties =
1193 (VkPhysicalDeviceSubgroupProperties*)ext;
1194 properties->subgroupSize = 64;
1195 properties->supportedStages = VK_SHADER_STAGE_ALL;
1196 properties->supportedOperations =
1197 VK_SUBGROUP_FEATURE_BASIC_BIT |
1198 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1199 VK_SUBGROUP_FEATURE_QUAD_BIT |
1200 VK_SUBGROUP_FEATURE_VOTE_BIT;
1201 if (pdevice->rad_info.chip_class >= GFX8) {
1202 properties->supportedOperations |=
1203 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1204 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1205 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1206 }
1207 properties->quadOperationsInAllStages = true;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1211 VkPhysicalDeviceMaintenance3Properties *properties =
1212 (VkPhysicalDeviceMaintenance3Properties*)ext;
1213 /* Make sure everything is addressable by a signed 32-bit int, and
1214 * our largest descriptors are 96 bytes. */
1215 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1216 /* Our buffer size fields allow only this much */
1217 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1221 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1222 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1223 /* GFX6-8 only support single channel min/max filter. */
1224 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1225 properties->filterMinmaxSingleComponentFormats = true;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1229 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1230 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1231
1232 /* Shader engines. */
1233 properties->shaderEngineCount =
1234 pdevice->rad_info.max_se;
1235 properties->shaderArraysPerEngineCount =
1236 pdevice->rad_info.max_sh_per_se;
1237 properties->computeUnitsPerShaderArray =
1238 pdevice->rad_info.num_good_cu_per_sh;
1239 properties->simdPerComputeUnit = 4;
1240 properties->wavefrontsPerSimd =
1241 pdevice->rad_info.family == CHIP_TONGA ||
1242 pdevice->rad_info.family == CHIP_ICELAND ||
1243 pdevice->rad_info.family == CHIP_POLARIS10 ||
1244 pdevice->rad_info.family == CHIP_POLARIS11 ||
1245 pdevice->rad_info.family == CHIP_POLARIS12 ||
1246 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1247 properties->wavefrontSize = 64;
1248
1249 /* SGPR. */
1250 properties->sgprsPerSimd =
1251 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1252 properties->minSgprAllocation =
1253 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1254 properties->maxSgprAllocation =
1255 pdevice->rad_info.family == CHIP_TONGA ||
1256 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1257 properties->sgprAllocationGranularity =
1258 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1259
1260 /* VGPR. */
1261 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1262 properties->minVgprAllocation = 4;
1263 properties->maxVgprAllocation = 256;
1264 properties->vgprAllocationGranularity = 4;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1268 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1269 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1270 properties->maxVertexAttribDivisor = UINT32_MAX;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1274 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1275 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1276 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1277 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1278 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1279 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1280 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1281 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1282 properties->robustBufferAccessUpdateAfterBind = false;
1283 properties->quadDivergentImplicitLod = false;
1284
1285 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1286 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1287 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1289 32 /* sampler, largest when combined with image */ +
1290 64 /* sampled image */ +
1291 64 /* storage image */);
1292 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1295 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1296 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1297 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1298 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1299 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1301 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1302 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1303 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1304 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1305 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1306 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1310 VkPhysicalDeviceProtectedMemoryProperties *properties =
1311 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1312 properties->protectedNoFault = false;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1316 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1317 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1318 properties->primitiveOverestimationSize = 0;
1319 properties->maxExtraPrimitiveOverestimationSize = 0;
1320 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1321 properties->primitiveUnderestimation = VK_FALSE;
1322 properties->conservativePointAndLineRasterization = VK_FALSE;
1323 properties->degenerateTrianglesRasterized = VK_FALSE;
1324 properties->degenerateLinesRasterized = VK_FALSE;
1325 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1326 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1327 break;
1328 }
1329 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1330 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1331 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1332 properties->pciDomain = pdevice->bus_info.domain;
1333 properties->pciBus = pdevice->bus_info.bus;
1334 properties->pciDevice = pdevice->bus_info.dev;
1335 properties->pciFunction = pdevice->bus_info.func;
1336 break;
1337 }
1338 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1339 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1340 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1341
1342 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1343 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1344 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1345 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1346 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1347
1348 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1349 .major = 1,
1350 .minor = 1,
1351 .subminor = 2,
1352 .patch = 0,
1353 };
1354 break;
1355 }
1356 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1357 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1358 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1359 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1360 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1361 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1362 properties->maxTransformFeedbackStreamDataSize = 512;
1363 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1364 properties->maxTransformFeedbackBufferDataStride = 512;
1365 properties->transformFeedbackQueries = true;
1366 properties->transformFeedbackStreamsLinesTriangles = true;
1367 properties->transformFeedbackRasterizationStreamSelect = false;
1368 properties->transformFeedbackDraw = true;
1369 break;
1370 }
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1372 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1373 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1374
1375 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1376 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1377 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1378 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1379 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1380 break;
1381 }
1382 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1383 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1384 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1385 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1386 VK_SAMPLE_COUNT_4_BIT |
1387 VK_SAMPLE_COUNT_8_BIT;
1388 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1389 properties->sampleLocationCoordinateRange[0] = 0.0f;
1390 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1391 properties->sampleLocationSubPixelBits = 4;
1392 properties->variableSampleLocations = VK_FALSE;
1393 break;
1394 }
1395 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1396 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1397 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1398
1399 /* We support all of the depth resolve modes */
1400 properties->supportedDepthResolveModes =
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1402 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1403 VK_RESOLVE_MODE_MIN_BIT_KHR |
1404 VK_RESOLVE_MODE_MAX_BIT_KHR;
1405
1406 /* Average doesn't make sense for stencil so we don't support that */
1407 properties->supportedStencilResolveModes =
1408 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1409 VK_RESOLVE_MODE_MIN_BIT_KHR |
1410 VK_RESOLVE_MODE_MAX_BIT_KHR;
1411
1412 properties->independentResolveNone = VK_TRUE;
1413 properties->independentResolve = VK_TRUE;
1414 break;
1415 }
1416 default:
1417 break;
1418 }
1419 }
1420 }
1421
1422 static void radv_get_physical_device_queue_family_properties(
1423 struct radv_physical_device* pdevice,
1424 uint32_t* pCount,
1425 VkQueueFamilyProperties** pQueueFamilyProperties)
1426 {
1427 int num_queue_families = 1;
1428 int idx;
1429 if (pdevice->rad_info.num_compute_rings > 0 &&
1430 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1431 num_queue_families++;
1432
1433 if (pQueueFamilyProperties == NULL) {
1434 *pCount = num_queue_families;
1435 return;
1436 }
1437
1438 if (!*pCount)
1439 return;
1440
1441 idx = 0;
1442 if (*pCount >= 1) {
1443 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1444 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1445 VK_QUEUE_COMPUTE_BIT |
1446 VK_QUEUE_TRANSFER_BIT |
1447 VK_QUEUE_SPARSE_BINDING_BIT,
1448 .queueCount = 1,
1449 .timestampValidBits = 64,
1450 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1451 };
1452 idx++;
1453 }
1454
1455 if (pdevice->rad_info.num_compute_rings > 0 &&
1456 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1457 if (*pCount > idx) {
1458 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1459 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1460 VK_QUEUE_TRANSFER_BIT |
1461 VK_QUEUE_SPARSE_BINDING_BIT,
1462 .queueCount = pdevice->rad_info.num_compute_rings,
1463 .timestampValidBits = 64,
1464 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1465 };
1466 idx++;
1467 }
1468 }
1469 *pCount = idx;
1470 }
1471
1472 void radv_GetPhysicalDeviceQueueFamilyProperties(
1473 VkPhysicalDevice physicalDevice,
1474 uint32_t* pCount,
1475 VkQueueFamilyProperties* pQueueFamilyProperties)
1476 {
1477 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1478 if (!pQueueFamilyProperties) {
1479 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1480 return;
1481 }
1482 VkQueueFamilyProperties *properties[] = {
1483 pQueueFamilyProperties + 0,
1484 pQueueFamilyProperties + 1,
1485 pQueueFamilyProperties + 2,
1486 };
1487 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1488 assert(*pCount <= 3);
1489 }
1490
1491 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1492 VkPhysicalDevice physicalDevice,
1493 uint32_t* pCount,
1494 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1495 {
1496 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1497 if (!pQueueFamilyProperties) {
1498 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1499 return;
1500 }
1501 VkQueueFamilyProperties *properties[] = {
1502 &pQueueFamilyProperties[0].queueFamilyProperties,
1503 &pQueueFamilyProperties[1].queueFamilyProperties,
1504 &pQueueFamilyProperties[2].queueFamilyProperties,
1505 };
1506 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1507 assert(*pCount <= 3);
1508 }
1509
1510 void radv_GetPhysicalDeviceMemoryProperties(
1511 VkPhysicalDevice physicalDevice,
1512 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1513 {
1514 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1515
1516 *pMemoryProperties = physical_device->memory_properties;
1517 }
1518
1519 static void
1520 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1521 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1522 {
1523 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1524 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1525 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1526 uint64_t vram_size = radv_get_vram_size(device);
1527 uint64_t gtt_size = device->rad_info.gart_size;
1528 uint64_t heap_budget, heap_usage;
1529
1530 /* For all memory heaps, the computation of budget is as follow:
1531 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1532 *
1533 * The Vulkan spec 1.1.97 says that the budget should include any
1534 * currently allocated device memory.
1535 *
1536 * Note that the application heap usages are not really accurate (eg.
1537 * in presence of shared buffers).
1538 */
1539 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1540 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1541
1542 switch (device->mem_type_indices[i]) {
1543 case RADV_MEM_TYPE_VRAM:
1544 heap_usage = device->ws->query_value(device->ws,
1545 RADEON_ALLOCATED_VRAM);
1546
1547 heap_budget = vram_size -
1548 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1549 heap_usage;
1550
1551 memoryBudget->heapBudget[heap_index] = heap_budget;
1552 memoryBudget->heapUsage[heap_index] = heap_usage;
1553 break;
1554 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1555 heap_usage = device->ws->query_value(device->ws,
1556 RADEON_ALLOCATED_VRAM_VIS);
1557
1558 heap_budget = visible_vram_size -
1559 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1560 heap_usage;
1561
1562 memoryBudget->heapBudget[heap_index] = heap_budget;
1563 memoryBudget->heapUsage[heap_index] = heap_usage;
1564 break;
1565 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1566 heap_usage = device->ws->query_value(device->ws,
1567 RADEON_ALLOCATED_GTT);
1568
1569 heap_budget = gtt_size -
1570 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1571 heap_usage;
1572
1573 memoryBudget->heapBudget[heap_index] = heap_budget;
1574 memoryBudget->heapUsage[heap_index] = heap_usage;
1575 break;
1576 default:
1577 break;
1578 }
1579 }
1580
1581 /* The heapBudget and heapUsage values must be zero for array elements
1582 * greater than or equal to
1583 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1584 */
1585 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1586 memoryBudget->heapBudget[i] = 0;
1587 memoryBudget->heapUsage[i] = 0;
1588 }
1589 }
1590
1591 void radv_GetPhysicalDeviceMemoryProperties2(
1592 VkPhysicalDevice physicalDevice,
1593 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1594 {
1595 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1596 &pMemoryProperties->memoryProperties);
1597
1598 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1599 vk_find_struct(pMemoryProperties->pNext,
1600 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1601 if (memory_budget)
1602 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1603 }
1604
1605 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1606 VkDevice _device,
1607 VkExternalMemoryHandleTypeFlagBits handleType,
1608 const void *pHostPointer,
1609 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612
1613 switch (handleType)
1614 {
1615 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1616 const struct radv_physical_device *physical_device = device->physical_device;
1617 uint32_t memoryTypeBits = 0;
1618 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1619 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1620 memoryTypeBits = (1 << i);
1621 break;
1622 }
1623 }
1624 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1625 return VK_SUCCESS;
1626 }
1627 default:
1628 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1629 }
1630 }
1631
1632 static enum radeon_ctx_priority
1633 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1634 {
1635 /* Default to MEDIUM when a specific global priority isn't requested */
1636 if (!pObj)
1637 return RADEON_CTX_PRIORITY_MEDIUM;
1638
1639 switch(pObj->globalPriority) {
1640 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1641 return RADEON_CTX_PRIORITY_REALTIME;
1642 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1643 return RADEON_CTX_PRIORITY_HIGH;
1644 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1645 return RADEON_CTX_PRIORITY_MEDIUM;
1646 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1647 return RADEON_CTX_PRIORITY_LOW;
1648 default:
1649 unreachable("Illegal global priority value");
1650 return RADEON_CTX_PRIORITY_INVALID;
1651 }
1652 }
1653
1654 static int
1655 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1656 uint32_t queue_family_index, int idx,
1657 VkDeviceQueueCreateFlags flags,
1658 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1659 {
1660 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1661 queue->device = device;
1662 queue->queue_family_index = queue_family_index;
1663 queue->queue_idx = idx;
1664 queue->priority = radv_get_queue_global_priority(global_priority);
1665 queue->flags = flags;
1666
1667 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1668 if (!queue->hw_ctx)
1669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1670
1671 return VK_SUCCESS;
1672 }
1673
1674 static void
1675 radv_queue_finish(struct radv_queue *queue)
1676 {
1677 if (queue->hw_ctx)
1678 queue->device->ws->ctx_destroy(queue->hw_ctx);
1679
1680 if (queue->initial_full_flush_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1682 if (queue->initial_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1684 if (queue->continue_preamble_cs)
1685 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1686 if (queue->descriptor_bo)
1687 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1688 if (queue->scratch_bo)
1689 queue->device->ws->buffer_destroy(queue->scratch_bo);
1690 if (queue->esgs_ring_bo)
1691 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1692 if (queue->gsvs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1694 if (queue->tess_rings_bo)
1695 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1696 if (queue->compute_scratch_bo)
1697 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1698 }
1699
1700 static void
1701 radv_bo_list_init(struct radv_bo_list *bo_list)
1702 {
1703 pthread_mutex_init(&bo_list->mutex, NULL);
1704 bo_list->list.count = bo_list->capacity = 0;
1705 bo_list->list.bos = NULL;
1706 }
1707
1708 static void
1709 radv_bo_list_finish(struct radv_bo_list *bo_list)
1710 {
1711 free(bo_list->list.bos);
1712 pthread_mutex_destroy(&bo_list->mutex);
1713 }
1714
1715 static VkResult radv_bo_list_add(struct radv_device *device,
1716 struct radeon_winsys_bo *bo)
1717 {
1718 struct radv_bo_list *bo_list = &device->bo_list;
1719
1720 if (bo->is_local)
1721 return VK_SUCCESS;
1722
1723 if (unlikely(!device->use_global_bo_list))
1724 return VK_SUCCESS;
1725
1726 pthread_mutex_lock(&bo_list->mutex);
1727 if (bo_list->list.count == bo_list->capacity) {
1728 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1729 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1730
1731 if (!data) {
1732 pthread_mutex_unlock(&bo_list->mutex);
1733 return VK_ERROR_OUT_OF_HOST_MEMORY;
1734 }
1735
1736 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1737 bo_list->capacity = capacity;
1738 }
1739
1740 bo_list->list.bos[bo_list->list.count++] = bo;
1741 pthread_mutex_unlock(&bo_list->mutex);
1742 return VK_SUCCESS;
1743 }
1744
1745 static void radv_bo_list_remove(struct radv_device *device,
1746 struct radeon_winsys_bo *bo)
1747 {
1748 struct radv_bo_list *bo_list = &device->bo_list;
1749
1750 if (bo->is_local)
1751 return;
1752
1753 if (unlikely(!device->use_global_bo_list))
1754 return;
1755
1756 pthread_mutex_lock(&bo_list->mutex);
1757 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1758 if (bo_list->list.bos[i] == bo) {
1759 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1760 --bo_list->list.count;
1761 break;
1762 }
1763 }
1764 pthread_mutex_unlock(&bo_list->mutex);
1765 }
1766
1767 static void
1768 radv_device_init_gs_info(struct radv_device *device)
1769 {
1770 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1771 device->physical_device->rad_info.family);
1772 }
1773
1774 static int radv_get_device_extension_index(const char *name)
1775 {
1776 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1777 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1778 return i;
1779 }
1780 return -1;
1781 }
1782
1783 static int
1784 radv_get_int_debug_option(const char *name, int default_value)
1785 {
1786 const char *str;
1787 int result;
1788
1789 str = getenv(name);
1790 if (!str) {
1791 result = default_value;
1792 } else {
1793 char *endptr;
1794
1795 result = strtol(str, &endptr, 0);
1796 if (str == endptr) {
1797 /* No digits founs. */
1798 result = default_value;
1799 }
1800 }
1801
1802 return result;
1803 }
1804
1805 VkResult radv_CreateDevice(
1806 VkPhysicalDevice physicalDevice,
1807 const VkDeviceCreateInfo* pCreateInfo,
1808 const VkAllocationCallbacks* pAllocator,
1809 VkDevice* pDevice)
1810 {
1811 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1812 VkResult result;
1813 struct radv_device *device;
1814
1815 bool keep_shader_info = false;
1816
1817 /* Check enabled features */
1818 if (pCreateInfo->pEnabledFeatures) {
1819 VkPhysicalDeviceFeatures supported_features;
1820 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1821 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1822 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1823 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1824 for (uint32_t i = 0; i < num_features; i++) {
1825 if (enabled_feature[i] && !supported_feature[i])
1826 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1827 }
1828 }
1829
1830 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1831 sizeof(*device), 8,
1832 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1833 if (!device)
1834 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1835
1836 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1837 device->instance = physical_device->instance;
1838 device->physical_device = physical_device;
1839
1840 device->ws = physical_device->ws;
1841 if (pAllocator)
1842 device->alloc = *pAllocator;
1843 else
1844 device->alloc = physical_device->instance->alloc;
1845
1846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1847 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1848 int index = radv_get_device_extension_index(ext_name);
1849 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1850 vk_free(&device->alloc, device);
1851 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1852 }
1853
1854 device->enabled_extensions.extensions[index] = true;
1855 }
1856
1857 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1858
1859 /* With update after bind we can't attach bo's to the command buffer
1860 * from the descriptor set anymore, so we have to use a global BO list.
1861 */
1862 device->use_global_bo_list =
1863 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1864 device->enabled_extensions.EXT_descriptor_indexing ||
1865 device->enabled_extensions.EXT_buffer_device_address;
1866
1867 mtx_init(&device->shader_slab_mutex, mtx_plain);
1868 list_inithead(&device->shader_slabs);
1869
1870 radv_bo_list_init(&device->bo_list);
1871
1872 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1873 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1874 uint32_t qfi = queue_create->queueFamilyIndex;
1875 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1876 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1877
1878 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1879
1880 device->queues[qfi] = vk_alloc(&device->alloc,
1881 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1882 if (!device->queues[qfi]) {
1883 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1884 goto fail;
1885 }
1886
1887 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1888
1889 device->queue_count[qfi] = queue_create->queueCount;
1890
1891 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1892 result = radv_queue_init(device, &device->queues[qfi][q],
1893 qfi, q, queue_create->flags,
1894 global_priority);
1895 if (result != VK_SUCCESS)
1896 goto fail;
1897 }
1898 }
1899
1900 /* TODO: Enable binning for GFX10. */
1901 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1902 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1903
1904 /* Disabled and not implemented for now. */
1905 device->dfsm_allowed = device->pbb_allowed &&
1906 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1907 device->physical_device->rad_info.family == CHIP_RAVEN2);
1908
1909 #ifdef ANDROID
1910 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1911 #endif
1912
1913 /* The maximum number of scratch waves. Scratch space isn't divided
1914 * evenly between CUs. The number is only a function of the number of CUs.
1915 * We can decrease the constant to decrease the scratch buffer size.
1916 *
1917 * sctx->scratch_waves must be >= the maximum possible size of
1918 * 1 threadgroup, so that the hw doesn't hang from being unable
1919 * to start any.
1920 *
1921 * The recommended value is 4 per CU at most. Higher numbers don't
1922 * bring much benefit, but they still occupy chip resources (think
1923 * async compute). I've seen ~2% performance difference between 4 and 32.
1924 */
1925 uint32_t max_threads_per_block = 2048;
1926 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1927 max_threads_per_block / 64);
1928
1929 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1930
1931 if (device->physical_device->rad_info.chip_class >= GFX7) {
1932 /* If the KMD allows it (there is a KMD hw register for it),
1933 * allow launching waves out-of-order.
1934 */
1935 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1936 }
1937
1938 radv_device_init_gs_info(device);
1939
1940 device->tess_offchip_block_dw_size =
1941 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1942 device->has_distributed_tess =
1943 device->physical_device->rad_info.chip_class >= GFX8 &&
1944 device->physical_device->rad_info.max_se >= 2;
1945
1946 if (getenv("RADV_TRACE_FILE")) {
1947 const char *filename = getenv("RADV_TRACE_FILE");
1948
1949 keep_shader_info = true;
1950
1951 if (!radv_init_trace(device))
1952 goto fail;
1953
1954 fprintf(stderr, "*****************************************************************************\n");
1955 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1956 fprintf(stderr, "*****************************************************************************\n");
1957
1958 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1959 radv_dump_enabled_options(device, stderr);
1960 }
1961
1962 device->keep_shader_info = keep_shader_info;
1963
1964 result = radv_device_init_meta(device);
1965 if (result != VK_SUCCESS)
1966 goto fail;
1967
1968 radv_device_init_msaa(device);
1969
1970 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1971 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1972 switch (family) {
1973 case RADV_QUEUE_GENERAL:
1974 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1975 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1976 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1977 break;
1978 case RADV_QUEUE_COMPUTE:
1979 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(device->empty_cs[family], 0);
1981 break;
1982 }
1983 device->ws->cs_finalize(device->empty_cs[family]);
1984 }
1985
1986 if (device->physical_device->rad_info.chip_class >= GFX7)
1987 cik_create_gfx_config(device);
1988
1989 VkPipelineCacheCreateInfo ci;
1990 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1991 ci.pNext = NULL;
1992 ci.flags = 0;
1993 ci.pInitialData = NULL;
1994 ci.initialDataSize = 0;
1995 VkPipelineCache pc;
1996 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1997 &ci, NULL, &pc);
1998 if (result != VK_SUCCESS)
1999 goto fail_meta;
2000
2001 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2002
2003 device->force_aniso =
2004 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2005 if (device->force_aniso >= 0) {
2006 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2007 1 << util_logbase2(device->force_aniso));
2008 }
2009
2010 *pDevice = radv_device_to_handle(device);
2011 return VK_SUCCESS;
2012
2013 fail_meta:
2014 radv_device_finish_meta(device);
2015 fail:
2016 radv_bo_list_finish(&device->bo_list);
2017
2018 if (device->trace_bo)
2019 device->ws->buffer_destroy(device->trace_bo);
2020
2021 if (device->gfx_init)
2022 device->ws->buffer_destroy(device->gfx_init);
2023
2024 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2025 for (unsigned q = 0; q < device->queue_count[i]; q++)
2026 radv_queue_finish(&device->queues[i][q]);
2027 if (device->queue_count[i])
2028 vk_free(&device->alloc, device->queues[i]);
2029 }
2030
2031 vk_free(&device->alloc, device);
2032 return result;
2033 }
2034
2035 void radv_DestroyDevice(
2036 VkDevice _device,
2037 const VkAllocationCallbacks* pAllocator)
2038 {
2039 RADV_FROM_HANDLE(radv_device, device, _device);
2040
2041 if (!device)
2042 return;
2043
2044 if (device->trace_bo)
2045 device->ws->buffer_destroy(device->trace_bo);
2046
2047 if (device->gfx_init)
2048 device->ws->buffer_destroy(device->gfx_init);
2049
2050 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2051 for (unsigned q = 0; q < device->queue_count[i]; q++)
2052 radv_queue_finish(&device->queues[i][q]);
2053 if (device->queue_count[i])
2054 vk_free(&device->alloc, device->queues[i]);
2055 if (device->empty_cs[i])
2056 device->ws->cs_destroy(device->empty_cs[i]);
2057 }
2058 radv_device_finish_meta(device);
2059
2060 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2061 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2062
2063 radv_destroy_shader_slabs(device);
2064
2065 radv_bo_list_finish(&device->bo_list);
2066 vk_free(&device->alloc, device);
2067 }
2068
2069 VkResult radv_EnumerateInstanceLayerProperties(
2070 uint32_t* pPropertyCount,
2071 VkLayerProperties* pProperties)
2072 {
2073 if (pProperties == NULL) {
2074 *pPropertyCount = 0;
2075 return VK_SUCCESS;
2076 }
2077
2078 /* None supported at this time */
2079 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2080 }
2081
2082 VkResult radv_EnumerateDeviceLayerProperties(
2083 VkPhysicalDevice physicalDevice,
2084 uint32_t* pPropertyCount,
2085 VkLayerProperties* pProperties)
2086 {
2087 if (pProperties == NULL) {
2088 *pPropertyCount = 0;
2089 return VK_SUCCESS;
2090 }
2091
2092 /* None supported at this time */
2093 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2094 }
2095
2096 void radv_GetDeviceQueue2(
2097 VkDevice _device,
2098 const VkDeviceQueueInfo2* pQueueInfo,
2099 VkQueue* pQueue)
2100 {
2101 RADV_FROM_HANDLE(radv_device, device, _device);
2102 struct radv_queue *queue;
2103
2104 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2105 if (pQueueInfo->flags != queue->flags) {
2106 /* From the Vulkan 1.1.70 spec:
2107 *
2108 * "The queue returned by vkGetDeviceQueue2 must have the same
2109 * flags value from this structure as that used at device
2110 * creation time in a VkDeviceQueueCreateInfo instance. If no
2111 * matching flags were specified at device creation time then
2112 * pQueue will return VK_NULL_HANDLE."
2113 */
2114 *pQueue = VK_NULL_HANDLE;
2115 return;
2116 }
2117
2118 *pQueue = radv_queue_to_handle(queue);
2119 }
2120
2121 void radv_GetDeviceQueue(
2122 VkDevice _device,
2123 uint32_t queueFamilyIndex,
2124 uint32_t queueIndex,
2125 VkQueue* pQueue)
2126 {
2127 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2128 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2129 .queueFamilyIndex = queueFamilyIndex,
2130 .queueIndex = queueIndex
2131 };
2132
2133 radv_GetDeviceQueue2(_device, &info, pQueue);
2134 }
2135
2136 static void
2137 fill_geom_tess_rings(struct radv_queue *queue,
2138 uint32_t *map,
2139 bool add_sample_positions,
2140 uint32_t esgs_ring_size,
2141 struct radeon_winsys_bo *esgs_ring_bo,
2142 uint32_t gsvs_ring_size,
2143 struct radeon_winsys_bo *gsvs_ring_bo,
2144 uint32_t tess_factor_ring_size,
2145 uint32_t tess_offchip_ring_offset,
2146 uint32_t tess_offchip_ring_size,
2147 struct radeon_winsys_bo *tess_rings_bo)
2148 {
2149 uint32_t *desc = &map[4];
2150
2151 if (esgs_ring_bo) {
2152 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2153
2154 /* stride 0, num records - size, add tid, swizzle, elsize4,
2155 index stride 64 */
2156 desc[0] = esgs_va;
2157 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2158 S_008F04_STRIDE(0) |
2159 S_008F04_SWIZZLE_ENABLE(true);
2160 desc[2] = esgs_ring_size;
2161 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2165 S_008F0C_ELEMENT_SIZE(1) |
2166 S_008F0C_INDEX_STRIDE(3) |
2167 S_008F0C_ADD_TID_ENABLE(true);
2168
2169 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2170 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2171 S_008F0C_OOB_SELECT(2) |
2172 S_008F0C_RESOURCE_LEVEL(1);
2173 } else {
2174 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2176 }
2177
2178 /* GS entry for ES->GS ring */
2179 /* stride 0, num records - size, elsize0,
2180 index stride 0 */
2181 desc[4] = esgs_va;
2182 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2183 S_008F04_STRIDE(0) |
2184 S_008F04_SWIZZLE_ENABLE(false);
2185 desc[6] = esgs_ring_size;
2186 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2187 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2188 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2189 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2190 S_008F0C_ELEMENT_SIZE(0) |
2191 S_008F0C_INDEX_STRIDE(0) |
2192 S_008F0C_ADD_TID_ENABLE(false);
2193
2194 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2195 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2196 S_008F0C_OOB_SELECT(2) |
2197 S_008F0C_RESOURCE_LEVEL(1);
2198 } else {
2199 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2201 }
2202 }
2203
2204 desc += 8;
2205
2206 if (gsvs_ring_bo) {
2207 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2208
2209 /* VS entry for GS->VS ring */
2210 /* stride 0, num records - size, elsize0,
2211 index stride 0 */
2212 desc[0] = gsvs_va;
2213 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2214 S_008F04_STRIDE(0) |
2215 S_008F04_SWIZZLE_ENABLE(false);
2216 desc[2] = gsvs_ring_size;
2217 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2218 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2219 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2220 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2221 S_008F0C_ELEMENT_SIZE(0) |
2222 S_008F0C_INDEX_STRIDE(0) |
2223 S_008F0C_ADD_TID_ENABLE(false);
2224
2225 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2226 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2227 S_008F0C_OOB_SELECT(2) |
2228 S_008F0C_RESOURCE_LEVEL(1);
2229 } else {
2230 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2232 }
2233
2234 /* stride gsvs_itemsize, num records 64
2235 elsize 4, index stride 16 */
2236 /* shader will patch stride and desc[2] */
2237 desc[4] = gsvs_va;
2238 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2239 S_008F04_STRIDE(0) |
2240 S_008F04_SWIZZLE_ENABLE(true);
2241 desc[6] = 0;
2242 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2246 S_008F0C_ELEMENT_SIZE(1) |
2247 S_008F0C_INDEX_STRIDE(1) |
2248 S_008F0C_ADD_TID_ENABLE(true);
2249
2250 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2251 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2254 } else {
2255 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2257 }
2258
2259 }
2260
2261 desc += 8;
2262
2263 if (tess_rings_bo) {
2264 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2265 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2266
2267 desc[0] = tess_va;
2268 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2269 S_008F04_STRIDE(0) |
2270 S_008F04_SWIZZLE_ENABLE(false);
2271 desc[2] = tess_factor_ring_size;
2272 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2273 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2274 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2275 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2276
2277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2278 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2279 S_008F0C_OOB_SELECT(3) |
2280 S_008F0C_RESOURCE_LEVEL(1);
2281 } else {
2282 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2284 }
2285
2286 desc[4] = tess_offchip_va;
2287 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2288 S_008F04_STRIDE(0) |
2289 S_008F04_SWIZZLE_ENABLE(false);
2290 desc[6] = tess_offchip_ring_size;
2291 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2292 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2293 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2294 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2295
2296 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2297 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2298 S_008F0C_OOB_SELECT(3) |
2299 S_008F0C_RESOURCE_LEVEL(1);
2300 } else {
2301 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2302 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2303 }
2304 }
2305
2306 desc += 8;
2307
2308 if (add_sample_positions) {
2309 /* add sample positions after all rings */
2310 memcpy(desc, queue->device->sample_locations_1x, 8);
2311 desc += 2;
2312 memcpy(desc, queue->device->sample_locations_2x, 16);
2313 desc += 4;
2314 memcpy(desc, queue->device->sample_locations_4x, 32);
2315 desc += 8;
2316 memcpy(desc, queue->device->sample_locations_8x, 64);
2317 }
2318 }
2319
2320 static unsigned
2321 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2322 {
2323 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2324 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2325 device->physical_device->rad_info.family != CHIP_STONEY;
2326 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2327 unsigned max_offchip_buffers;
2328 unsigned offchip_granularity;
2329 unsigned hs_offchip_param;
2330
2331 /*
2332 * Per RadeonSI:
2333 * This must be one less than the maximum number due to a hw limitation.
2334 * Various hardware bugs need thGFX7
2335 *
2336 * Per AMDVLK:
2337 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2338 * Gfx7 should limit max_offchip_buffers to 508
2339 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2340 *
2341 * Follow AMDVLK here.
2342 */
2343 if (device->physical_device->rad_info.chip_class >= GFX10) {
2344 max_offchip_buffers_per_se = 256;
2345 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2346 device->physical_device->rad_info.chip_class == GFX7 ||
2347 device->physical_device->rad_info.chip_class == GFX6)
2348 --max_offchip_buffers_per_se;
2349
2350 max_offchip_buffers = max_offchip_buffers_per_se *
2351 device->physical_device->rad_info.max_se;
2352
2353 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2354 * around by setting 4K granularity.
2355 */
2356 if (device->tess_offchip_block_dw_size == 4096) {
2357 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2358 offchip_granularity = V_03093C_X_4K_DWORDS;
2359 } else {
2360 assert(device->tess_offchip_block_dw_size == 8192);
2361 offchip_granularity = V_03093C_X_8K_DWORDS;
2362 }
2363
2364 switch (device->physical_device->rad_info.chip_class) {
2365 case GFX6:
2366 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2367 break;
2368 case GFX7:
2369 case GFX8:
2370 case GFX9:
2371 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2372 break;
2373 case GFX10:
2374 break;
2375 default:
2376 break;
2377 }
2378
2379 *max_offchip_buffers_p = max_offchip_buffers;
2380 if (device->physical_device->rad_info.chip_class >= GFX7) {
2381 if (device->physical_device->rad_info.chip_class >= GFX8)
2382 --max_offchip_buffers;
2383 hs_offchip_param =
2384 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2385 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2386 } else {
2387 hs_offchip_param =
2388 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2389 }
2390 return hs_offchip_param;
2391 }
2392
2393 static void
2394 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2395 struct radeon_winsys_bo *esgs_ring_bo,
2396 uint32_t esgs_ring_size,
2397 struct radeon_winsys_bo *gsvs_ring_bo,
2398 uint32_t gsvs_ring_size)
2399 {
2400 if (!esgs_ring_bo && !gsvs_ring_bo)
2401 return;
2402
2403 if (esgs_ring_bo)
2404 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2405
2406 if (gsvs_ring_bo)
2407 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2408
2409 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2410 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2411 radeon_emit(cs, esgs_ring_size >> 8);
2412 radeon_emit(cs, gsvs_ring_size >> 8);
2413 } else {
2414 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2415 radeon_emit(cs, esgs_ring_size >> 8);
2416 radeon_emit(cs, gsvs_ring_size >> 8);
2417 }
2418 }
2419
2420 static void
2421 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2422 unsigned hs_offchip_param, unsigned tf_ring_size,
2423 struct radeon_winsys_bo *tess_rings_bo)
2424 {
2425 uint64_t tf_va;
2426
2427 if (!tess_rings_bo)
2428 return;
2429
2430 tf_va = radv_buffer_get_va(tess_rings_bo);
2431
2432 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2433
2434 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2435 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2436 S_030938_SIZE(tf_ring_size / 4));
2437 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2438 tf_va >> 8);
2439
2440 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2441 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2442 S_030984_BASE_HI(tf_va >> 40));
2443 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2444 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2445 S_030944_BASE_HI(tf_va >> 40));
2446 }
2447 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2448 hs_offchip_param);
2449 } else {
2450 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2451 S_008988_SIZE(tf_ring_size / 4));
2452 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2453 tf_va >> 8);
2454 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2455 hs_offchip_param);
2456 }
2457 }
2458
2459 static void
2460 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2461 struct radeon_winsys_bo *compute_scratch_bo)
2462 {
2463 uint64_t scratch_va;
2464
2465 if (!compute_scratch_bo)
2466 return;
2467
2468 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2469
2470 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2471
2472 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2473 radeon_emit(cs, scratch_va);
2474 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2475 S_008F04_SWIZZLE_ENABLE(1));
2476 }
2477
2478 static void
2479 radv_emit_global_shader_pointers(struct radv_queue *queue,
2480 struct radeon_cmdbuf *cs,
2481 struct radeon_winsys_bo *descriptor_bo)
2482 {
2483 uint64_t va;
2484
2485 if (!descriptor_bo)
2486 return;
2487
2488 va = radv_buffer_get_va(descriptor_bo);
2489
2490 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2491
2492 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2493 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2494 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2495 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2496 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2497
2498 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2499 radv_emit_shader_pointer(queue->device, cs, regs[i],
2500 va, true);
2501 }
2502 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2503 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2504 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2505 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2506 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2507
2508 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2509 radv_emit_shader_pointer(queue->device, cs, regs[i],
2510 va, true);
2511 }
2512 } else {
2513 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2514 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2515 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2516 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2517 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2518 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2519
2520 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2521 radv_emit_shader_pointer(queue->device, cs, regs[i],
2522 va, true);
2523 }
2524 }
2525 }
2526
2527 static void
2528 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2529 {
2530 struct radv_device *device = queue->device;
2531
2532 if (device->gfx_init) {
2533 uint64_t va = radv_buffer_get_va(device->gfx_init);
2534
2535 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2536 radeon_emit(cs, va);
2537 radeon_emit(cs, va >> 32);
2538 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2539
2540 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2541 } else {
2542 struct radv_physical_device *physical_device = device->physical_device;
2543 si_emit_graphics(physical_device, cs);
2544 }
2545 }
2546
2547 static void
2548 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2549 {
2550 struct radv_physical_device *physical_device = queue->device->physical_device;
2551 si_emit_compute(physical_device, cs);
2552 }
2553
2554 static VkResult
2555 radv_get_preamble_cs(struct radv_queue *queue,
2556 uint32_t scratch_size,
2557 uint32_t compute_scratch_size,
2558 uint32_t esgs_ring_size,
2559 uint32_t gsvs_ring_size,
2560 bool needs_tess_rings,
2561 bool needs_sample_positions,
2562 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2563 struct radeon_cmdbuf **initial_preamble_cs,
2564 struct radeon_cmdbuf **continue_preamble_cs)
2565 {
2566 struct radeon_winsys_bo *scratch_bo = NULL;
2567 struct radeon_winsys_bo *descriptor_bo = NULL;
2568 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2569 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2570 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2571 struct radeon_winsys_bo *tess_rings_bo = NULL;
2572 struct radeon_cmdbuf *dest_cs[3] = {0};
2573 bool add_tess_rings = false, add_sample_positions = false;
2574 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2575 unsigned max_offchip_buffers;
2576 unsigned hs_offchip_param = 0;
2577 unsigned tess_offchip_ring_offset;
2578 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2579 if (!queue->has_tess_rings) {
2580 if (needs_tess_rings)
2581 add_tess_rings = true;
2582 }
2583 if (!queue->has_sample_positions) {
2584 if (needs_sample_positions)
2585 add_sample_positions = true;
2586 }
2587 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2588 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2589 &max_offchip_buffers);
2590 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2591 tess_offchip_ring_size = max_offchip_buffers *
2592 queue->device->tess_offchip_block_dw_size * 4;
2593
2594 if (scratch_size <= queue->scratch_size &&
2595 compute_scratch_size <= queue->compute_scratch_size &&
2596 esgs_ring_size <= queue->esgs_ring_size &&
2597 gsvs_ring_size <= queue->gsvs_ring_size &&
2598 !add_tess_rings && !add_sample_positions &&
2599 queue->initial_preamble_cs) {
2600 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2601 *initial_preamble_cs = queue->initial_preamble_cs;
2602 *continue_preamble_cs = queue->continue_preamble_cs;
2603 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2604 *continue_preamble_cs = NULL;
2605 return VK_SUCCESS;
2606 }
2607
2608 if (scratch_size > queue->scratch_size) {
2609 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2610 scratch_size,
2611 4096,
2612 RADEON_DOMAIN_VRAM,
2613 ring_bo_flags,
2614 RADV_BO_PRIORITY_SCRATCH);
2615 if (!scratch_bo)
2616 goto fail;
2617 } else
2618 scratch_bo = queue->scratch_bo;
2619
2620 if (compute_scratch_size > queue->compute_scratch_size) {
2621 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2622 compute_scratch_size,
2623 4096,
2624 RADEON_DOMAIN_VRAM,
2625 ring_bo_flags,
2626 RADV_BO_PRIORITY_SCRATCH);
2627 if (!compute_scratch_bo)
2628 goto fail;
2629
2630 } else
2631 compute_scratch_bo = queue->compute_scratch_bo;
2632
2633 if (esgs_ring_size > queue->esgs_ring_size) {
2634 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2635 esgs_ring_size,
2636 4096,
2637 RADEON_DOMAIN_VRAM,
2638 ring_bo_flags,
2639 RADV_BO_PRIORITY_SCRATCH);
2640 if (!esgs_ring_bo)
2641 goto fail;
2642 } else {
2643 esgs_ring_bo = queue->esgs_ring_bo;
2644 esgs_ring_size = queue->esgs_ring_size;
2645 }
2646
2647 if (gsvs_ring_size > queue->gsvs_ring_size) {
2648 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2649 gsvs_ring_size,
2650 4096,
2651 RADEON_DOMAIN_VRAM,
2652 ring_bo_flags,
2653 RADV_BO_PRIORITY_SCRATCH);
2654 if (!gsvs_ring_bo)
2655 goto fail;
2656 } else {
2657 gsvs_ring_bo = queue->gsvs_ring_bo;
2658 gsvs_ring_size = queue->gsvs_ring_size;
2659 }
2660
2661 if (add_tess_rings) {
2662 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2663 tess_offchip_ring_offset + tess_offchip_ring_size,
2664 256,
2665 RADEON_DOMAIN_VRAM,
2666 ring_bo_flags,
2667 RADV_BO_PRIORITY_SCRATCH);
2668 if (!tess_rings_bo)
2669 goto fail;
2670 } else {
2671 tess_rings_bo = queue->tess_rings_bo;
2672 }
2673
2674 if (scratch_bo != queue->scratch_bo ||
2675 esgs_ring_bo != queue->esgs_ring_bo ||
2676 gsvs_ring_bo != queue->gsvs_ring_bo ||
2677 tess_rings_bo != queue->tess_rings_bo ||
2678 add_sample_positions) {
2679 uint32_t size = 0;
2680 if (gsvs_ring_bo || esgs_ring_bo ||
2681 tess_rings_bo || add_sample_positions) {
2682 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2683 if (add_sample_positions)
2684 size += 128; /* 64+32+16+8 = 120 bytes */
2685 }
2686 else if (scratch_bo)
2687 size = 8; /* 2 dword */
2688
2689 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2690 size,
2691 4096,
2692 RADEON_DOMAIN_VRAM,
2693 RADEON_FLAG_CPU_ACCESS |
2694 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2695 RADEON_FLAG_READ_ONLY,
2696 RADV_BO_PRIORITY_DESCRIPTOR);
2697 if (!descriptor_bo)
2698 goto fail;
2699 } else
2700 descriptor_bo = queue->descriptor_bo;
2701
2702 if (descriptor_bo != queue->descriptor_bo) {
2703 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2704
2705 if (scratch_bo) {
2706 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2707 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2708 S_008F04_SWIZZLE_ENABLE(1);
2709 map[0] = scratch_va;
2710 map[1] = rsrc1;
2711 }
2712
2713 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2714 fill_geom_tess_rings(queue, map, add_sample_positions,
2715 esgs_ring_size, esgs_ring_bo,
2716 gsvs_ring_size, gsvs_ring_bo,
2717 tess_factor_ring_size,
2718 tess_offchip_ring_offset,
2719 tess_offchip_ring_size,
2720 tess_rings_bo);
2721
2722 queue->device->ws->buffer_unmap(descriptor_bo);
2723 }
2724
2725 for(int i = 0; i < 3; ++i) {
2726 struct radeon_cmdbuf *cs = NULL;
2727 cs = queue->device->ws->cs_create(queue->device->ws,
2728 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2729 if (!cs)
2730 goto fail;
2731
2732 dest_cs[i] = cs;
2733
2734 if (scratch_bo)
2735 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2736
2737 /* Emit initial configuration. */
2738 switch (queue->queue_family_index) {
2739 case RADV_QUEUE_GENERAL:
2740 radv_init_graphics_state(cs, queue);
2741 break;
2742 case RADV_QUEUE_COMPUTE:
2743 radv_init_compute_state(cs, queue);
2744 break;
2745 case RADV_QUEUE_TRANSFER:
2746 break;
2747 }
2748
2749 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2750 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2751 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2752
2753 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2754 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2755 }
2756
2757 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2758 gsvs_ring_bo, gsvs_ring_size);
2759 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2760 tess_factor_ring_size, tess_rings_bo);
2761 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2762 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2763
2764 if (i == 0) {
2765 si_cs_emit_cache_flush(cs,
2766 queue->device->physical_device->rad_info.chip_class,
2767 NULL, 0,
2768 queue->queue_family_index == RING_COMPUTE &&
2769 queue->device->physical_device->rad_info.chip_class >= GFX7,
2770 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2771 RADV_CMD_FLAG_INV_ICACHE |
2772 RADV_CMD_FLAG_INV_SCACHE |
2773 RADV_CMD_FLAG_INV_VCACHE |
2774 RADV_CMD_FLAG_INV_L2 |
2775 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2776 } else if (i == 1) {
2777 si_cs_emit_cache_flush(cs,
2778 queue->device->physical_device->rad_info.chip_class,
2779 NULL, 0,
2780 queue->queue_family_index == RING_COMPUTE &&
2781 queue->device->physical_device->rad_info.chip_class >= GFX7,
2782 RADV_CMD_FLAG_INV_ICACHE |
2783 RADV_CMD_FLAG_INV_SCACHE |
2784 RADV_CMD_FLAG_INV_VCACHE |
2785 RADV_CMD_FLAG_INV_L2 |
2786 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2787 }
2788
2789 if (!queue->device->ws->cs_finalize(cs))
2790 goto fail;
2791 }
2792
2793 if (queue->initial_full_flush_preamble_cs)
2794 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2795
2796 if (queue->initial_preamble_cs)
2797 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2798
2799 if (queue->continue_preamble_cs)
2800 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2801
2802 queue->initial_full_flush_preamble_cs = dest_cs[0];
2803 queue->initial_preamble_cs = dest_cs[1];
2804 queue->continue_preamble_cs = dest_cs[2];
2805
2806 if (scratch_bo != queue->scratch_bo) {
2807 if (queue->scratch_bo)
2808 queue->device->ws->buffer_destroy(queue->scratch_bo);
2809 queue->scratch_bo = scratch_bo;
2810 queue->scratch_size = scratch_size;
2811 }
2812
2813 if (compute_scratch_bo != queue->compute_scratch_bo) {
2814 if (queue->compute_scratch_bo)
2815 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2816 queue->compute_scratch_bo = compute_scratch_bo;
2817 queue->compute_scratch_size = compute_scratch_size;
2818 }
2819
2820 if (esgs_ring_bo != queue->esgs_ring_bo) {
2821 if (queue->esgs_ring_bo)
2822 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2823 queue->esgs_ring_bo = esgs_ring_bo;
2824 queue->esgs_ring_size = esgs_ring_size;
2825 }
2826
2827 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2828 if (queue->gsvs_ring_bo)
2829 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2830 queue->gsvs_ring_bo = gsvs_ring_bo;
2831 queue->gsvs_ring_size = gsvs_ring_size;
2832 }
2833
2834 if (tess_rings_bo != queue->tess_rings_bo) {
2835 queue->tess_rings_bo = tess_rings_bo;
2836 queue->has_tess_rings = true;
2837 }
2838
2839 if (descriptor_bo != queue->descriptor_bo) {
2840 if (queue->descriptor_bo)
2841 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2842
2843 queue->descriptor_bo = descriptor_bo;
2844 }
2845
2846 if (add_sample_positions)
2847 queue->has_sample_positions = true;
2848
2849 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2850 *initial_preamble_cs = queue->initial_preamble_cs;
2851 *continue_preamble_cs = queue->continue_preamble_cs;
2852 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2853 *continue_preamble_cs = NULL;
2854 return VK_SUCCESS;
2855 fail:
2856 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2857 if (dest_cs[i])
2858 queue->device->ws->cs_destroy(dest_cs[i]);
2859 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2860 queue->device->ws->buffer_destroy(descriptor_bo);
2861 if (scratch_bo && scratch_bo != queue->scratch_bo)
2862 queue->device->ws->buffer_destroy(scratch_bo);
2863 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2864 queue->device->ws->buffer_destroy(compute_scratch_bo);
2865 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2866 queue->device->ws->buffer_destroy(esgs_ring_bo);
2867 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2868 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2869 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2870 queue->device->ws->buffer_destroy(tess_rings_bo);
2871 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2872 }
2873
2874 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2875 struct radv_winsys_sem_counts *counts,
2876 int num_sems,
2877 const VkSemaphore *sems,
2878 VkFence _fence,
2879 bool reset_temp)
2880 {
2881 int syncobj_idx = 0, sem_idx = 0;
2882
2883 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2884 return VK_SUCCESS;
2885
2886 for (uint32_t i = 0; i < num_sems; i++) {
2887 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2888
2889 if (sem->temp_syncobj || sem->syncobj)
2890 counts->syncobj_count++;
2891 else
2892 counts->sem_count++;
2893 }
2894
2895 if (_fence != VK_NULL_HANDLE) {
2896 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2897 if (fence->temp_syncobj || fence->syncobj)
2898 counts->syncobj_count++;
2899 }
2900
2901 if (counts->syncobj_count) {
2902 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2903 if (!counts->syncobj)
2904 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2905 }
2906
2907 if (counts->sem_count) {
2908 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2909 if (!counts->sem) {
2910 free(counts->syncobj);
2911 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2912 }
2913 }
2914
2915 for (uint32_t i = 0; i < num_sems; i++) {
2916 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2917
2918 if (sem->temp_syncobj) {
2919 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2920 }
2921 else if (sem->syncobj)
2922 counts->syncobj[syncobj_idx++] = sem->syncobj;
2923 else {
2924 assert(sem->sem);
2925 counts->sem[sem_idx++] = sem->sem;
2926 }
2927 }
2928
2929 if (_fence != VK_NULL_HANDLE) {
2930 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2931 if (fence->temp_syncobj)
2932 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2933 else if (fence->syncobj)
2934 counts->syncobj[syncobj_idx++] = fence->syncobj;
2935 }
2936
2937 return VK_SUCCESS;
2938 }
2939
2940 static void
2941 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2942 {
2943 free(sem_info->wait.syncobj);
2944 free(sem_info->wait.sem);
2945 free(sem_info->signal.syncobj);
2946 free(sem_info->signal.sem);
2947 }
2948
2949
2950 static void radv_free_temp_syncobjs(struct radv_device *device,
2951 int num_sems,
2952 const VkSemaphore *sems)
2953 {
2954 for (uint32_t i = 0; i < num_sems; i++) {
2955 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2956
2957 if (sem->temp_syncobj) {
2958 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2959 sem->temp_syncobj = 0;
2960 }
2961 }
2962 }
2963
2964 static VkResult
2965 radv_alloc_sem_info(struct radv_instance *instance,
2966 struct radv_winsys_sem_info *sem_info,
2967 int num_wait_sems,
2968 const VkSemaphore *wait_sems,
2969 int num_signal_sems,
2970 const VkSemaphore *signal_sems,
2971 VkFence fence)
2972 {
2973 VkResult ret;
2974 memset(sem_info, 0, sizeof(*sem_info));
2975
2976 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2977 if (ret)
2978 return ret;
2979 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2980 if (ret)
2981 radv_free_sem_info(sem_info);
2982
2983 /* caller can override these */
2984 sem_info->cs_emit_wait = true;
2985 sem_info->cs_emit_signal = true;
2986 return ret;
2987 }
2988
2989 /* Signals fence as soon as all the work currently put on queue is done. */
2990 static VkResult radv_signal_fence(struct radv_queue *queue,
2991 struct radv_fence *fence)
2992 {
2993 int ret;
2994 VkResult result;
2995 struct radv_winsys_sem_info sem_info;
2996
2997 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2998 radv_fence_to_handle(fence));
2999 if (result != VK_SUCCESS)
3000 return result;
3001
3002 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3003 &queue->device->empty_cs[queue->queue_family_index],
3004 1, NULL, NULL, &sem_info, NULL,
3005 false, fence->fence);
3006 radv_free_sem_info(&sem_info);
3007
3008 if (ret)
3009 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3010
3011 return VK_SUCCESS;
3012 }
3013
3014 VkResult radv_QueueSubmit(
3015 VkQueue _queue,
3016 uint32_t submitCount,
3017 const VkSubmitInfo* pSubmits,
3018 VkFence _fence)
3019 {
3020 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3021 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3022 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3023 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3024 int ret;
3025 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3026 uint32_t scratch_size = 0;
3027 uint32_t compute_scratch_size = 0;
3028 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3029 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3030 VkResult result;
3031 bool fence_emitted = false;
3032 bool tess_rings_needed = false;
3033 bool sample_positions_needed = false;
3034
3035 /* Do this first so failing to allocate scratch buffers can't result in
3036 * partially executed submissions. */
3037 for (uint32_t i = 0; i < submitCount; i++) {
3038 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3039 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3040 pSubmits[i].pCommandBuffers[j]);
3041
3042 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3043 compute_scratch_size = MAX2(compute_scratch_size,
3044 cmd_buffer->compute_scratch_size_needed);
3045 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3046 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3047 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3048 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3049 }
3050 }
3051
3052 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3053 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3054 sample_positions_needed, &initial_flush_preamble_cs,
3055 &initial_preamble_cs, &continue_preamble_cs);
3056 if (result != VK_SUCCESS)
3057 return result;
3058
3059 for (uint32_t i = 0; i < submitCount; i++) {
3060 struct radeon_cmdbuf **cs_array;
3061 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3062 bool can_patch = true;
3063 uint32_t advance;
3064 struct radv_winsys_sem_info sem_info;
3065
3066 result = radv_alloc_sem_info(queue->device->instance,
3067 &sem_info,
3068 pSubmits[i].waitSemaphoreCount,
3069 pSubmits[i].pWaitSemaphores,
3070 pSubmits[i].signalSemaphoreCount,
3071 pSubmits[i].pSignalSemaphores,
3072 _fence);
3073 if (result != VK_SUCCESS)
3074 return result;
3075
3076 if (!pSubmits[i].commandBufferCount) {
3077 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3078 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3079 &queue->device->empty_cs[queue->queue_family_index],
3080 1, NULL, NULL,
3081 &sem_info, NULL,
3082 false, base_fence);
3083 if (ret) {
3084 radv_loge("failed to submit CS %d\n", i);
3085 abort();
3086 }
3087 fence_emitted = true;
3088 }
3089 radv_free_sem_info(&sem_info);
3090 continue;
3091 }
3092
3093 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3094 (pSubmits[i].commandBufferCount));
3095
3096 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3098 pSubmits[i].pCommandBuffers[j]);
3099 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3100
3101 cs_array[j] = cmd_buffer->cs;
3102 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3103 can_patch = false;
3104
3105 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3106 }
3107
3108 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3109 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3110 const struct radv_winsys_bo_list *bo_list = NULL;
3111
3112 advance = MIN2(max_cs_submission,
3113 pSubmits[i].commandBufferCount - j);
3114
3115 if (queue->device->trace_bo)
3116 *queue->device->trace_id_ptr = 0;
3117
3118 sem_info.cs_emit_wait = j == 0;
3119 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3120
3121 if (unlikely(queue->device->use_global_bo_list)) {
3122 pthread_mutex_lock(&queue->device->bo_list.mutex);
3123 bo_list = &queue->device->bo_list.list;
3124 }
3125
3126 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3127 advance, initial_preamble, continue_preamble_cs,
3128 &sem_info, bo_list,
3129 can_patch, base_fence);
3130
3131 if (unlikely(queue->device->use_global_bo_list))
3132 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3133
3134 if (ret) {
3135 radv_loge("failed to submit CS %d\n", i);
3136 abort();
3137 }
3138 fence_emitted = true;
3139 if (queue->device->trace_bo) {
3140 radv_check_gpu_hangs(queue, cs_array[j]);
3141 }
3142 }
3143
3144 radv_free_temp_syncobjs(queue->device,
3145 pSubmits[i].waitSemaphoreCount,
3146 pSubmits[i].pWaitSemaphores);
3147 radv_free_sem_info(&sem_info);
3148 free(cs_array);
3149 }
3150
3151 if (fence) {
3152 if (!fence_emitted) {
3153 result = radv_signal_fence(queue, fence);
3154 if (result != VK_SUCCESS)
3155 return result;
3156 }
3157 }
3158
3159 return VK_SUCCESS;
3160 }
3161
3162 VkResult radv_QueueWaitIdle(
3163 VkQueue _queue)
3164 {
3165 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3166
3167 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3168 radv_queue_family_to_ring(queue->queue_family_index),
3169 queue->queue_idx);
3170 return VK_SUCCESS;
3171 }
3172
3173 VkResult radv_DeviceWaitIdle(
3174 VkDevice _device)
3175 {
3176 RADV_FROM_HANDLE(radv_device, device, _device);
3177
3178 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3179 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3180 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3181 }
3182 }
3183 return VK_SUCCESS;
3184 }
3185
3186 VkResult radv_EnumerateInstanceExtensionProperties(
3187 const char* pLayerName,
3188 uint32_t* pPropertyCount,
3189 VkExtensionProperties* pProperties)
3190 {
3191 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3192
3193 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3194 if (radv_supported_instance_extensions.extensions[i]) {
3195 vk_outarray_append(&out, prop) {
3196 *prop = radv_instance_extensions[i];
3197 }
3198 }
3199 }
3200
3201 return vk_outarray_status(&out);
3202 }
3203
3204 VkResult radv_EnumerateDeviceExtensionProperties(
3205 VkPhysicalDevice physicalDevice,
3206 const char* pLayerName,
3207 uint32_t* pPropertyCount,
3208 VkExtensionProperties* pProperties)
3209 {
3210 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3211 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3212
3213 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3214 if (device->supported_extensions.extensions[i]) {
3215 vk_outarray_append(&out, prop) {
3216 *prop = radv_device_extensions[i];
3217 }
3218 }
3219 }
3220
3221 return vk_outarray_status(&out);
3222 }
3223
3224 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3225 VkInstance _instance,
3226 const char* pName)
3227 {
3228 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3229
3230 return radv_lookup_entrypoint_checked(pName,
3231 instance ? instance->apiVersion : 0,
3232 instance ? &instance->enabled_extensions : NULL,
3233 NULL);
3234 }
3235
3236 /* The loader wants us to expose a second GetInstanceProcAddr function
3237 * to work around certain LD_PRELOAD issues seen in apps.
3238 */
3239 PUBLIC
3240 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3241 VkInstance instance,
3242 const char* pName);
3243
3244 PUBLIC
3245 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3246 VkInstance instance,
3247 const char* pName)
3248 {
3249 return radv_GetInstanceProcAddr(instance, pName);
3250 }
3251
3252 PUBLIC
3253 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3254 VkInstance _instance,
3255 const char* pName);
3256
3257 PUBLIC
3258 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3259 VkInstance _instance,
3260 const char* pName)
3261 {
3262 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3263
3264 return radv_lookup_physical_device_entrypoint_checked(pName,
3265 instance ? instance->apiVersion : 0,
3266 instance ? &instance->enabled_extensions : NULL);
3267 }
3268
3269 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3270 VkDevice _device,
3271 const char* pName)
3272 {
3273 RADV_FROM_HANDLE(radv_device, device, _device);
3274
3275 return radv_lookup_entrypoint_checked(pName,
3276 device->instance->apiVersion,
3277 &device->instance->enabled_extensions,
3278 &device->enabled_extensions);
3279 }
3280
3281 bool radv_get_memory_fd(struct radv_device *device,
3282 struct radv_device_memory *memory,
3283 int *pFD)
3284 {
3285 struct radeon_bo_metadata metadata;
3286
3287 if (memory->image) {
3288 radv_init_metadata(device, memory->image, &metadata);
3289 device->ws->buffer_set_metadata(memory->bo, &metadata);
3290 }
3291
3292 return device->ws->buffer_get_fd(device->ws, memory->bo,
3293 pFD);
3294 }
3295
3296 static VkResult radv_alloc_memory(struct radv_device *device,
3297 const VkMemoryAllocateInfo* pAllocateInfo,
3298 const VkAllocationCallbacks* pAllocator,
3299 VkDeviceMemory* pMem)
3300 {
3301 struct radv_device_memory *mem;
3302 VkResult result;
3303 enum radeon_bo_domain domain;
3304 uint32_t flags = 0;
3305 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3306
3307 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3308
3309 if (pAllocateInfo->allocationSize == 0) {
3310 /* Apparently, this is allowed */
3311 *pMem = VK_NULL_HANDLE;
3312 return VK_SUCCESS;
3313 }
3314
3315 const VkImportMemoryFdInfoKHR *import_info =
3316 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3317 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3318 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3319 const VkExportMemoryAllocateInfo *export_info =
3320 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3321 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3322 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3323
3324 const struct wsi_memory_allocate_info *wsi_info =
3325 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3326
3327 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3328 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3329 if (mem == NULL)
3330 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3331
3332 if (wsi_info && wsi_info->implicit_sync)
3333 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3334
3335 if (dedicate_info) {
3336 mem->image = radv_image_from_handle(dedicate_info->image);
3337 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3338 } else {
3339 mem->image = NULL;
3340 mem->buffer = NULL;
3341 }
3342
3343 float priority_float = 0.5;
3344 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3345 vk_find_struct_const(pAllocateInfo->pNext,
3346 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3347 if (priority_ext)
3348 priority_float = priority_ext->priority;
3349
3350 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3351 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3352
3353 mem->user_ptr = NULL;
3354
3355 if (import_info) {
3356 assert(import_info->handleType ==
3357 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3358 import_info->handleType ==
3359 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3360 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3361 priority, NULL, NULL);
3362 if (!mem->bo) {
3363 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3364 goto fail;
3365 } else {
3366 close(import_info->fd);
3367 }
3368 } else if (host_ptr_info) {
3369 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3370 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3371 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3372 pAllocateInfo->allocationSize,
3373 priority);
3374 if (!mem->bo) {
3375 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3376 goto fail;
3377 } else {
3378 mem->user_ptr = host_ptr_info->pHostPointer;
3379 }
3380 } else {
3381 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3382 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3383 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3384 domain = RADEON_DOMAIN_GTT;
3385 else
3386 domain = RADEON_DOMAIN_VRAM;
3387
3388 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3389 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3390 else
3391 flags |= RADEON_FLAG_CPU_ACCESS;
3392
3393 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3394 flags |= RADEON_FLAG_GTT_WC;
3395
3396 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3397 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3398 if (device->use_global_bo_list) {
3399 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3400 }
3401 }
3402
3403 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3404 domain, flags, priority);
3405
3406 if (!mem->bo) {
3407 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3408 goto fail;
3409 }
3410 mem->type_index = mem_type_index;
3411 }
3412
3413 result = radv_bo_list_add(device, mem->bo);
3414 if (result != VK_SUCCESS)
3415 goto fail_bo;
3416
3417 *pMem = radv_device_memory_to_handle(mem);
3418
3419 return VK_SUCCESS;
3420
3421 fail_bo:
3422 device->ws->buffer_destroy(mem->bo);
3423 fail:
3424 vk_free2(&device->alloc, pAllocator, mem);
3425
3426 return result;
3427 }
3428
3429 VkResult radv_AllocateMemory(
3430 VkDevice _device,
3431 const VkMemoryAllocateInfo* pAllocateInfo,
3432 const VkAllocationCallbacks* pAllocator,
3433 VkDeviceMemory* pMem)
3434 {
3435 RADV_FROM_HANDLE(radv_device, device, _device);
3436 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3437 }
3438
3439 void radv_FreeMemory(
3440 VkDevice _device,
3441 VkDeviceMemory _mem,
3442 const VkAllocationCallbacks* pAllocator)
3443 {
3444 RADV_FROM_HANDLE(radv_device, device, _device);
3445 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3446
3447 if (mem == NULL)
3448 return;
3449
3450 radv_bo_list_remove(device, mem->bo);
3451 device->ws->buffer_destroy(mem->bo);
3452 mem->bo = NULL;
3453
3454 vk_free2(&device->alloc, pAllocator, mem);
3455 }
3456
3457 VkResult radv_MapMemory(
3458 VkDevice _device,
3459 VkDeviceMemory _memory,
3460 VkDeviceSize offset,
3461 VkDeviceSize size,
3462 VkMemoryMapFlags flags,
3463 void** ppData)
3464 {
3465 RADV_FROM_HANDLE(radv_device, device, _device);
3466 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3467
3468 if (mem == NULL) {
3469 *ppData = NULL;
3470 return VK_SUCCESS;
3471 }
3472
3473 if (mem->user_ptr)
3474 *ppData = mem->user_ptr;
3475 else
3476 *ppData = device->ws->buffer_map(mem->bo);
3477
3478 if (*ppData) {
3479 *ppData += offset;
3480 return VK_SUCCESS;
3481 }
3482
3483 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3484 }
3485
3486 void radv_UnmapMemory(
3487 VkDevice _device,
3488 VkDeviceMemory _memory)
3489 {
3490 RADV_FROM_HANDLE(radv_device, device, _device);
3491 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3492
3493 if (mem == NULL)
3494 return;
3495
3496 if (mem->user_ptr == NULL)
3497 device->ws->buffer_unmap(mem->bo);
3498 }
3499
3500 VkResult radv_FlushMappedMemoryRanges(
3501 VkDevice _device,
3502 uint32_t memoryRangeCount,
3503 const VkMappedMemoryRange* pMemoryRanges)
3504 {
3505 return VK_SUCCESS;
3506 }
3507
3508 VkResult radv_InvalidateMappedMemoryRanges(
3509 VkDevice _device,
3510 uint32_t memoryRangeCount,
3511 const VkMappedMemoryRange* pMemoryRanges)
3512 {
3513 return VK_SUCCESS;
3514 }
3515
3516 void radv_GetBufferMemoryRequirements(
3517 VkDevice _device,
3518 VkBuffer _buffer,
3519 VkMemoryRequirements* pMemoryRequirements)
3520 {
3521 RADV_FROM_HANDLE(radv_device, device, _device);
3522 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3523
3524 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3525
3526 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3527 pMemoryRequirements->alignment = 4096;
3528 else
3529 pMemoryRequirements->alignment = 16;
3530
3531 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3532 }
3533
3534 void radv_GetBufferMemoryRequirements2(
3535 VkDevice device,
3536 const VkBufferMemoryRequirementsInfo2 *pInfo,
3537 VkMemoryRequirements2 *pMemoryRequirements)
3538 {
3539 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3540 &pMemoryRequirements->memoryRequirements);
3541 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3542 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3543 switch (ext->sType) {
3544 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3545 VkMemoryDedicatedRequirements *req =
3546 (VkMemoryDedicatedRequirements *) ext;
3547 req->requiresDedicatedAllocation = buffer->shareable;
3548 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3549 break;
3550 }
3551 default:
3552 break;
3553 }
3554 }
3555 }
3556
3557 void radv_GetImageMemoryRequirements(
3558 VkDevice _device,
3559 VkImage _image,
3560 VkMemoryRequirements* pMemoryRequirements)
3561 {
3562 RADV_FROM_HANDLE(radv_device, device, _device);
3563 RADV_FROM_HANDLE(radv_image, image, _image);
3564
3565 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3566
3567 pMemoryRequirements->size = image->size;
3568 pMemoryRequirements->alignment = image->alignment;
3569 }
3570
3571 void radv_GetImageMemoryRequirements2(
3572 VkDevice device,
3573 const VkImageMemoryRequirementsInfo2 *pInfo,
3574 VkMemoryRequirements2 *pMemoryRequirements)
3575 {
3576 radv_GetImageMemoryRequirements(device, pInfo->image,
3577 &pMemoryRequirements->memoryRequirements);
3578
3579 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3580
3581 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3582 switch (ext->sType) {
3583 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3584 VkMemoryDedicatedRequirements *req =
3585 (VkMemoryDedicatedRequirements *) ext;
3586 req->requiresDedicatedAllocation = image->shareable;
3587 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3588 break;
3589 }
3590 default:
3591 break;
3592 }
3593 }
3594 }
3595
3596 void radv_GetImageSparseMemoryRequirements(
3597 VkDevice device,
3598 VkImage image,
3599 uint32_t* pSparseMemoryRequirementCount,
3600 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3601 {
3602 stub();
3603 }
3604
3605 void radv_GetImageSparseMemoryRequirements2(
3606 VkDevice device,
3607 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3608 uint32_t* pSparseMemoryRequirementCount,
3609 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3610 {
3611 stub();
3612 }
3613
3614 void radv_GetDeviceMemoryCommitment(
3615 VkDevice device,
3616 VkDeviceMemory memory,
3617 VkDeviceSize* pCommittedMemoryInBytes)
3618 {
3619 *pCommittedMemoryInBytes = 0;
3620 }
3621
3622 VkResult radv_BindBufferMemory2(VkDevice device,
3623 uint32_t bindInfoCount,
3624 const VkBindBufferMemoryInfo *pBindInfos)
3625 {
3626 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3627 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3628 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3629
3630 if (mem) {
3631 buffer->bo = mem->bo;
3632 buffer->offset = pBindInfos[i].memoryOffset;
3633 } else {
3634 buffer->bo = NULL;
3635 }
3636 }
3637 return VK_SUCCESS;
3638 }
3639
3640 VkResult radv_BindBufferMemory(
3641 VkDevice device,
3642 VkBuffer buffer,
3643 VkDeviceMemory memory,
3644 VkDeviceSize memoryOffset)
3645 {
3646 const VkBindBufferMemoryInfo info = {
3647 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3648 .buffer = buffer,
3649 .memory = memory,
3650 .memoryOffset = memoryOffset
3651 };
3652
3653 return radv_BindBufferMemory2(device, 1, &info);
3654 }
3655
3656 VkResult radv_BindImageMemory2(VkDevice device,
3657 uint32_t bindInfoCount,
3658 const VkBindImageMemoryInfo *pBindInfos)
3659 {
3660 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3661 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3662 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3663
3664 if (mem) {
3665 image->bo = mem->bo;
3666 image->offset = pBindInfos[i].memoryOffset;
3667 } else {
3668 image->bo = NULL;
3669 image->offset = 0;
3670 }
3671 }
3672 return VK_SUCCESS;
3673 }
3674
3675
3676 VkResult radv_BindImageMemory(
3677 VkDevice device,
3678 VkImage image,
3679 VkDeviceMemory memory,
3680 VkDeviceSize memoryOffset)
3681 {
3682 const VkBindImageMemoryInfo info = {
3683 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3684 .image = image,
3685 .memory = memory,
3686 .memoryOffset = memoryOffset
3687 };
3688
3689 return radv_BindImageMemory2(device, 1, &info);
3690 }
3691
3692
3693 static void
3694 radv_sparse_buffer_bind_memory(struct radv_device *device,
3695 const VkSparseBufferMemoryBindInfo *bind)
3696 {
3697 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3698
3699 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3700 struct radv_device_memory *mem = NULL;
3701
3702 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3703 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3704
3705 device->ws->buffer_virtual_bind(buffer->bo,
3706 bind->pBinds[i].resourceOffset,
3707 bind->pBinds[i].size,
3708 mem ? mem->bo : NULL,
3709 bind->pBinds[i].memoryOffset);
3710 }
3711 }
3712
3713 static void
3714 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3715 const VkSparseImageOpaqueMemoryBindInfo *bind)
3716 {
3717 RADV_FROM_HANDLE(radv_image, image, bind->image);
3718
3719 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3720 struct radv_device_memory *mem = NULL;
3721
3722 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3723 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3724
3725 device->ws->buffer_virtual_bind(image->bo,
3726 bind->pBinds[i].resourceOffset,
3727 bind->pBinds[i].size,
3728 mem ? mem->bo : NULL,
3729 bind->pBinds[i].memoryOffset);
3730 }
3731 }
3732
3733 VkResult radv_QueueBindSparse(
3734 VkQueue _queue,
3735 uint32_t bindInfoCount,
3736 const VkBindSparseInfo* pBindInfo,
3737 VkFence _fence)
3738 {
3739 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3740 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3741 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3742 bool fence_emitted = false;
3743 VkResult result;
3744 int ret;
3745
3746 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3747 struct radv_winsys_sem_info sem_info;
3748 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3749 radv_sparse_buffer_bind_memory(queue->device,
3750 pBindInfo[i].pBufferBinds + j);
3751 }
3752
3753 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3754 radv_sparse_image_opaque_bind_memory(queue->device,
3755 pBindInfo[i].pImageOpaqueBinds + j);
3756 }
3757
3758 VkResult result;
3759 result = radv_alloc_sem_info(queue->device->instance,
3760 &sem_info,
3761 pBindInfo[i].waitSemaphoreCount,
3762 pBindInfo[i].pWaitSemaphores,
3763 pBindInfo[i].signalSemaphoreCount,
3764 pBindInfo[i].pSignalSemaphores,
3765 _fence);
3766 if (result != VK_SUCCESS)
3767 return result;
3768
3769 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3770 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3771 &queue->device->empty_cs[queue->queue_family_index],
3772 1, NULL, NULL,
3773 &sem_info, NULL,
3774 false, base_fence);
3775 if (ret) {
3776 radv_loge("failed to submit CS %d\n", i);
3777 abort();
3778 }
3779
3780 fence_emitted = true;
3781 }
3782
3783 radv_free_sem_info(&sem_info);
3784
3785 }
3786
3787 if (fence) {
3788 if (!fence_emitted) {
3789 result = radv_signal_fence(queue, fence);
3790 if (result != VK_SUCCESS)
3791 return result;
3792 }
3793 }
3794
3795 return VK_SUCCESS;
3796 }
3797
3798 VkResult radv_CreateFence(
3799 VkDevice _device,
3800 const VkFenceCreateInfo* pCreateInfo,
3801 const VkAllocationCallbacks* pAllocator,
3802 VkFence* pFence)
3803 {
3804 RADV_FROM_HANDLE(radv_device, device, _device);
3805 const VkExportFenceCreateInfo *export =
3806 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3807 VkExternalFenceHandleTypeFlags handleTypes =
3808 export ? export->handleTypes : 0;
3809
3810 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3811 sizeof(*fence), 8,
3812 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3813
3814 if (!fence)
3815 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3816
3817 fence->fence_wsi = NULL;
3818 fence->temp_syncobj = 0;
3819 if (device->always_use_syncobj || handleTypes) {
3820 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3821 if (ret) {
3822 vk_free2(&device->alloc, pAllocator, fence);
3823 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3824 }
3825 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3826 device->ws->signal_syncobj(device->ws, fence->syncobj);
3827 }
3828 fence->fence = NULL;
3829 } else {
3830 fence->fence = device->ws->create_fence();
3831 if (!fence->fence) {
3832 vk_free2(&device->alloc, pAllocator, fence);
3833 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3834 }
3835 fence->syncobj = 0;
3836 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3837 device->ws->signal_fence(fence->fence);
3838 }
3839
3840 *pFence = radv_fence_to_handle(fence);
3841
3842 return VK_SUCCESS;
3843 }
3844
3845 void radv_DestroyFence(
3846 VkDevice _device,
3847 VkFence _fence,
3848 const VkAllocationCallbacks* pAllocator)
3849 {
3850 RADV_FROM_HANDLE(radv_device, device, _device);
3851 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3852
3853 if (!fence)
3854 return;
3855
3856 if (fence->temp_syncobj)
3857 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3858 if (fence->syncobj)
3859 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3860 if (fence->fence)
3861 device->ws->destroy_fence(fence->fence);
3862 if (fence->fence_wsi)
3863 fence->fence_wsi->destroy(fence->fence_wsi);
3864 vk_free2(&device->alloc, pAllocator, fence);
3865 }
3866
3867
3868 uint64_t radv_get_current_time(void)
3869 {
3870 struct timespec tv;
3871 clock_gettime(CLOCK_MONOTONIC, &tv);
3872 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3873 }
3874
3875 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3876 {
3877 uint64_t current_time = radv_get_current_time();
3878
3879 timeout = MIN2(UINT64_MAX - current_time, timeout);
3880
3881 return current_time + timeout;
3882 }
3883
3884
3885 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3886 uint32_t fenceCount, const VkFence *pFences)
3887 {
3888 for (uint32_t i = 0; i < fenceCount; ++i) {
3889 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3890 if (fence->fence == NULL || fence->syncobj ||
3891 fence->temp_syncobj || fence->fence_wsi ||
3892 (!device->ws->is_fence_waitable(fence->fence)))
3893 return false;
3894 }
3895 return true;
3896 }
3897
3898 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3899 {
3900 for (uint32_t i = 0; i < fenceCount; ++i) {
3901 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3902 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3903 return false;
3904 }
3905 return true;
3906 }
3907
3908 VkResult radv_WaitForFences(
3909 VkDevice _device,
3910 uint32_t fenceCount,
3911 const VkFence* pFences,
3912 VkBool32 waitAll,
3913 uint64_t timeout)
3914 {
3915 RADV_FROM_HANDLE(radv_device, device, _device);
3916 timeout = radv_get_absolute_timeout(timeout);
3917
3918 if (device->always_use_syncobj &&
3919 radv_all_fences_syncobj(fenceCount, pFences))
3920 {
3921 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3922 if (!handles)
3923 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3924
3925 for (uint32_t i = 0; i < fenceCount; ++i) {
3926 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3927 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3928 }
3929
3930 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3931
3932 free(handles);
3933 return success ? VK_SUCCESS : VK_TIMEOUT;
3934 }
3935
3936 if (!waitAll && fenceCount > 1) {
3937 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3938 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3939 uint32_t wait_count = 0;
3940 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3941 if (!fences)
3942 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3943
3944 for (uint32_t i = 0; i < fenceCount; ++i) {
3945 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3946
3947 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3948 free(fences);
3949 return VK_SUCCESS;
3950 }
3951
3952 fences[wait_count++] = fence->fence;
3953 }
3954
3955 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3956 waitAll, timeout - radv_get_current_time());
3957
3958 free(fences);
3959 return success ? VK_SUCCESS : VK_TIMEOUT;
3960 }
3961
3962 while(radv_get_current_time() <= timeout) {
3963 for (uint32_t i = 0; i < fenceCount; ++i) {
3964 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3965 return VK_SUCCESS;
3966 }
3967 }
3968 return VK_TIMEOUT;
3969 }
3970
3971 for (uint32_t i = 0; i < fenceCount; ++i) {
3972 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3973 bool expired = false;
3974
3975 if (fence->temp_syncobj) {
3976 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3977 return VK_TIMEOUT;
3978 continue;
3979 }
3980
3981 if (fence->syncobj) {
3982 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3983 return VK_TIMEOUT;
3984 continue;
3985 }
3986
3987 if (fence->fence) {
3988 if (!device->ws->is_fence_waitable(fence->fence)) {
3989 while(!device->ws->is_fence_waitable(fence->fence) &&
3990 radv_get_current_time() <= timeout)
3991 /* Do nothing */;
3992 }
3993
3994 expired = device->ws->fence_wait(device->ws,
3995 fence->fence,
3996 true, timeout);
3997 if (!expired)
3998 return VK_TIMEOUT;
3999 }
4000
4001 if (fence->fence_wsi) {
4002 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4003 if (result != VK_SUCCESS)
4004 return result;
4005 }
4006 }
4007
4008 return VK_SUCCESS;
4009 }
4010
4011 VkResult radv_ResetFences(VkDevice _device,
4012 uint32_t fenceCount,
4013 const VkFence *pFences)
4014 {
4015 RADV_FROM_HANDLE(radv_device, device, _device);
4016
4017 for (unsigned i = 0; i < fenceCount; ++i) {
4018 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4019 if (fence->fence)
4020 device->ws->reset_fence(fence->fence);
4021
4022 /* Per spec, we first restore the permanent payload, and then reset, so
4023 * having a temp syncobj should not skip resetting the permanent syncobj. */
4024 if (fence->temp_syncobj) {
4025 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4026 fence->temp_syncobj = 0;
4027 }
4028
4029 if (fence->syncobj) {
4030 device->ws->reset_syncobj(device->ws, fence->syncobj);
4031 }
4032 }
4033
4034 return VK_SUCCESS;
4035 }
4036
4037 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4038 {
4039 RADV_FROM_HANDLE(radv_device, device, _device);
4040 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4041
4042 if (fence->temp_syncobj) {
4043 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4044 return success ? VK_SUCCESS : VK_NOT_READY;
4045 }
4046
4047 if (fence->syncobj) {
4048 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4049 return success ? VK_SUCCESS : VK_NOT_READY;
4050 }
4051
4052 if (fence->fence) {
4053 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4054 return VK_NOT_READY;
4055 }
4056 if (fence->fence_wsi) {
4057 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4058
4059 if (result != VK_SUCCESS) {
4060 if (result == VK_TIMEOUT)
4061 return VK_NOT_READY;
4062 return result;
4063 }
4064 }
4065 return VK_SUCCESS;
4066 }
4067
4068
4069 // Queue semaphore functions
4070
4071 VkResult radv_CreateSemaphore(
4072 VkDevice _device,
4073 const VkSemaphoreCreateInfo* pCreateInfo,
4074 const VkAllocationCallbacks* pAllocator,
4075 VkSemaphore* pSemaphore)
4076 {
4077 RADV_FROM_HANDLE(radv_device, device, _device);
4078 const VkExportSemaphoreCreateInfo *export =
4079 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4080 VkExternalSemaphoreHandleTypeFlags handleTypes =
4081 export ? export->handleTypes : 0;
4082
4083 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4084 sizeof(*sem), 8,
4085 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4086 if (!sem)
4087 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4088
4089 sem->temp_syncobj = 0;
4090 /* create a syncobject if we are going to export this semaphore */
4091 if (device->always_use_syncobj || handleTypes) {
4092 assert (device->physical_device->rad_info.has_syncobj);
4093 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4094 if (ret) {
4095 vk_free2(&device->alloc, pAllocator, sem);
4096 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4097 }
4098 sem->sem = NULL;
4099 } else {
4100 sem->sem = device->ws->create_sem(device->ws);
4101 if (!sem->sem) {
4102 vk_free2(&device->alloc, pAllocator, sem);
4103 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4104 }
4105 sem->syncobj = 0;
4106 }
4107
4108 *pSemaphore = radv_semaphore_to_handle(sem);
4109 return VK_SUCCESS;
4110 }
4111
4112 void radv_DestroySemaphore(
4113 VkDevice _device,
4114 VkSemaphore _semaphore,
4115 const VkAllocationCallbacks* pAllocator)
4116 {
4117 RADV_FROM_HANDLE(radv_device, device, _device);
4118 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4119 if (!_semaphore)
4120 return;
4121
4122 if (sem->syncobj)
4123 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4124 else
4125 device->ws->destroy_sem(sem->sem);
4126 vk_free2(&device->alloc, pAllocator, sem);
4127 }
4128
4129 VkResult radv_CreateEvent(
4130 VkDevice _device,
4131 const VkEventCreateInfo* pCreateInfo,
4132 const VkAllocationCallbacks* pAllocator,
4133 VkEvent* pEvent)
4134 {
4135 RADV_FROM_HANDLE(radv_device, device, _device);
4136 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4137 sizeof(*event), 8,
4138 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4139
4140 if (!event)
4141 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4142
4143 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4144 RADEON_DOMAIN_GTT,
4145 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4146 RADV_BO_PRIORITY_FENCE);
4147 if (!event->bo) {
4148 vk_free2(&device->alloc, pAllocator, event);
4149 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4150 }
4151
4152 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4153
4154 *pEvent = radv_event_to_handle(event);
4155
4156 return VK_SUCCESS;
4157 }
4158
4159 void radv_DestroyEvent(
4160 VkDevice _device,
4161 VkEvent _event,
4162 const VkAllocationCallbacks* pAllocator)
4163 {
4164 RADV_FROM_HANDLE(radv_device, device, _device);
4165 RADV_FROM_HANDLE(radv_event, event, _event);
4166
4167 if (!event)
4168 return;
4169 device->ws->buffer_destroy(event->bo);
4170 vk_free2(&device->alloc, pAllocator, event);
4171 }
4172
4173 VkResult radv_GetEventStatus(
4174 VkDevice _device,
4175 VkEvent _event)
4176 {
4177 RADV_FROM_HANDLE(radv_event, event, _event);
4178
4179 if (*event->map == 1)
4180 return VK_EVENT_SET;
4181 return VK_EVENT_RESET;
4182 }
4183
4184 VkResult radv_SetEvent(
4185 VkDevice _device,
4186 VkEvent _event)
4187 {
4188 RADV_FROM_HANDLE(radv_event, event, _event);
4189 *event->map = 1;
4190
4191 return VK_SUCCESS;
4192 }
4193
4194 VkResult radv_ResetEvent(
4195 VkDevice _device,
4196 VkEvent _event)
4197 {
4198 RADV_FROM_HANDLE(radv_event, event, _event);
4199 *event->map = 0;
4200
4201 return VK_SUCCESS;
4202 }
4203
4204 VkResult radv_CreateBuffer(
4205 VkDevice _device,
4206 const VkBufferCreateInfo* pCreateInfo,
4207 const VkAllocationCallbacks* pAllocator,
4208 VkBuffer* pBuffer)
4209 {
4210 RADV_FROM_HANDLE(radv_device, device, _device);
4211 struct radv_buffer *buffer;
4212
4213 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4214
4215 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4216 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4217 if (buffer == NULL)
4218 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4219
4220 buffer->size = pCreateInfo->size;
4221 buffer->usage = pCreateInfo->usage;
4222 buffer->bo = NULL;
4223 buffer->offset = 0;
4224 buffer->flags = pCreateInfo->flags;
4225
4226 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4227 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4228
4229 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4230 buffer->bo = device->ws->buffer_create(device->ws,
4231 align64(buffer->size, 4096),
4232 4096, 0, RADEON_FLAG_VIRTUAL,
4233 RADV_BO_PRIORITY_VIRTUAL);
4234 if (!buffer->bo) {
4235 vk_free2(&device->alloc, pAllocator, buffer);
4236 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4237 }
4238 }
4239
4240 *pBuffer = radv_buffer_to_handle(buffer);
4241
4242 return VK_SUCCESS;
4243 }
4244
4245 void radv_DestroyBuffer(
4246 VkDevice _device,
4247 VkBuffer _buffer,
4248 const VkAllocationCallbacks* pAllocator)
4249 {
4250 RADV_FROM_HANDLE(radv_device, device, _device);
4251 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4252
4253 if (!buffer)
4254 return;
4255
4256 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4257 device->ws->buffer_destroy(buffer->bo);
4258
4259 vk_free2(&device->alloc, pAllocator, buffer);
4260 }
4261
4262 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4263 VkDevice device,
4264 const VkBufferDeviceAddressInfoEXT* pInfo)
4265 {
4266 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4267 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4268 }
4269
4270
4271 static inline unsigned
4272 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4273 {
4274 if (stencil)
4275 return plane->surface.u.legacy.stencil_tiling_index[level];
4276 else
4277 return plane->surface.u.legacy.tiling_index[level];
4278 }
4279
4280 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4281 {
4282 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4283 }
4284
4285 static uint32_t
4286 radv_init_dcc_control_reg(struct radv_device *device,
4287 struct radv_image_view *iview)
4288 {
4289 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4290 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4291 unsigned max_compressed_block_size;
4292 unsigned independent_128b_blocks;
4293 unsigned independent_64b_blocks;
4294
4295 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4296 return 0;
4297
4298 if (!device->physical_device->rad_info.has_dedicated_vram) {
4299 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4300 * dGPU and 64 for APU because all of our APUs to date use
4301 * DIMMs which have a request granularity size of 64B while all
4302 * other chips have a 32B request size.
4303 */
4304 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4305 }
4306
4307 if (device->physical_device->rad_info.chip_class >= GFX10) {
4308 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4309 independent_64b_blocks = 0;
4310 independent_128b_blocks = 1;
4311 } else {
4312 independent_128b_blocks = 0;
4313
4314 if (iview->image->info.samples > 1) {
4315 if (iview->image->planes[0].surface.bpe == 1)
4316 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4317 else if (iview->image->planes[0].surface.bpe == 2)
4318 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4319 }
4320
4321 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4322 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4323 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4324 /* If this DCC image is potentially going to be used in texture
4325 * fetches, we need some special settings.
4326 */
4327 independent_64b_blocks = 1;
4328 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4329 } else {
4330 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4331 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4332 * big as possible for better compression state.
4333 */
4334 independent_64b_blocks = 0;
4335 max_compressed_block_size = max_uncompressed_block_size;
4336 }
4337 }
4338
4339 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4340 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4341 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4342 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4343 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4344 }
4345
4346 static void
4347 radv_initialise_color_surface(struct radv_device *device,
4348 struct radv_color_buffer_info *cb,
4349 struct radv_image_view *iview)
4350 {
4351 const struct vk_format_description *desc;
4352 unsigned ntype, format, swap, endian;
4353 unsigned blend_clamp = 0, blend_bypass = 0;
4354 uint64_t va;
4355 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4356 const struct radeon_surf *surf = &plane->surface;
4357
4358 desc = vk_format_description(iview->vk_format);
4359
4360 memset(cb, 0, sizeof(*cb));
4361
4362 /* Intensity is implemented as Red, so treat it that way. */
4363 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4364
4365 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4366
4367 cb->cb_color_base = va >> 8;
4368
4369 if (device->physical_device->rad_info.chip_class >= GFX9) {
4370 struct gfx9_surf_meta_flags meta;
4371 if (iview->image->dcc_offset)
4372 meta = surf->u.gfx9.dcc;
4373 else
4374 meta = surf->u.gfx9.cmask;
4375
4376 if (device->physical_device->rad_info.chip_class >= GFX10) {
4377 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4378 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4379 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4380 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4381 } else {
4382 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4383 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4384 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4385 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4386 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4387 }
4388
4389 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4390 cb->cb_color_base |= surf->tile_swizzle;
4391 } else {
4392 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4393 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4394
4395 cb->cb_color_base += level_info->offset >> 8;
4396 if (level_info->mode == RADEON_SURF_MODE_2D)
4397 cb->cb_color_base |= surf->tile_swizzle;
4398
4399 pitch_tile_max = level_info->nblk_x / 8 - 1;
4400 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4401 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4402
4403 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4404 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4405 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4406
4407 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4408
4409 if (radv_image_has_fmask(iview->image)) {
4410 if (device->physical_device->rad_info.chip_class >= GFX7)
4411 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4412 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4413 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4414 } else {
4415 /* This must be set for fast clear to work without FMASK. */
4416 if (device->physical_device->rad_info.chip_class >= GFX7)
4417 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4418 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4419 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4420 }
4421 }
4422
4423 /* CMASK variables */
4424 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4425 va += iview->image->cmask.offset;
4426 cb->cb_color_cmask = va >> 8;
4427
4428 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4429 va += iview->image->dcc_offset;
4430
4431 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4432 device->physical_device->rad_info.chip_class <= GFX8)
4433 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4434
4435 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4436 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4437
4438 cb->cb_dcc_base = va >> 8;
4439 cb->cb_dcc_base |= dcc_tile_swizzle;
4440
4441 /* GFX10 field has the same base shift as the GFX6 field. */
4442 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4443 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4444 S_028C6C_SLICE_MAX_GFX10(max_slice);
4445
4446 if (iview->image->info.samples > 1) {
4447 unsigned log_samples = util_logbase2(iview->image->info.samples);
4448
4449 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4450 S_028C74_NUM_FRAGMENTS(log_samples);
4451 }
4452
4453 if (radv_image_has_fmask(iview->image)) {
4454 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4455 cb->cb_color_fmask = va >> 8;
4456 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4457 } else {
4458 cb->cb_color_fmask = cb->cb_color_base;
4459 }
4460
4461 ntype = radv_translate_color_numformat(iview->vk_format,
4462 desc,
4463 vk_format_get_first_non_void_channel(iview->vk_format));
4464 format = radv_translate_colorformat(iview->vk_format);
4465 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4466 radv_finishme("Illegal color\n");
4467 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4468 endian = radv_colorformat_endian_swap(format);
4469
4470 /* blend clamp should be set for all NORM/SRGB types */
4471 if (ntype == V_028C70_NUMBER_UNORM ||
4472 ntype == V_028C70_NUMBER_SNORM ||
4473 ntype == V_028C70_NUMBER_SRGB)
4474 blend_clamp = 1;
4475
4476 /* set blend bypass according to docs if SINT/UINT or
4477 8/24 COLOR variants */
4478 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4479 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4480 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4481 blend_clamp = 0;
4482 blend_bypass = 1;
4483 }
4484 #if 0
4485 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4486 (format == V_028C70_COLOR_8 ||
4487 format == V_028C70_COLOR_8_8 ||
4488 format == V_028C70_COLOR_8_8_8_8))
4489 ->color_is_int8 = true;
4490 #endif
4491 cb->cb_color_info = S_028C70_FORMAT(format) |
4492 S_028C70_COMP_SWAP(swap) |
4493 S_028C70_BLEND_CLAMP(blend_clamp) |
4494 S_028C70_BLEND_BYPASS(blend_bypass) |
4495 S_028C70_SIMPLE_FLOAT(1) |
4496 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4497 ntype != V_028C70_NUMBER_SNORM &&
4498 ntype != V_028C70_NUMBER_SRGB &&
4499 format != V_028C70_COLOR_8_24 &&
4500 format != V_028C70_COLOR_24_8) |
4501 S_028C70_NUMBER_TYPE(ntype) |
4502 S_028C70_ENDIAN(endian);
4503 if (radv_image_has_fmask(iview->image)) {
4504 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4505 if (device->physical_device->rad_info.chip_class == GFX6) {
4506 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4507 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4508 }
4509
4510 if (radv_image_is_tc_compat_cmask(iview->image)) {
4511 /* Allow the texture block to read FMASK directly
4512 * without decompressing it. This bit must be cleared
4513 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4514 * otherwise the operation doesn't happen.
4515 */
4516 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4517
4518 /* Set CMASK into a tiling format that allows the
4519 * texture block to read it.
4520 */
4521 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4522 }
4523 }
4524
4525 if (radv_image_has_cmask(iview->image) &&
4526 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4527 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4528
4529 if (radv_dcc_enabled(iview->image, iview->base_mip))
4530 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4531
4532 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4533
4534 /* This must be set for fast clear to work without FMASK. */
4535 if (!radv_image_has_fmask(iview->image) &&
4536 device->physical_device->rad_info.chip_class == GFX6) {
4537 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4538 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4539 }
4540
4541 if (device->physical_device->rad_info.chip_class >= GFX9) {
4542 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4543
4544 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4545 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4546 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4547 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4548
4549 if (device->physical_device->rad_info.chip_class >= GFX10) {
4550 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4551
4552 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4553 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4554 S_028EE0_RESOURCE_LEVEL(1);
4555 } else {
4556 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4557 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4558 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4559 }
4560
4561 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4562 S_028C68_MIP0_HEIGHT(height - 1) |
4563 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4564 }
4565 }
4566
4567 static unsigned
4568 radv_calc_decompress_on_z_planes(struct radv_device *device,
4569 struct radv_image_view *iview)
4570 {
4571 unsigned max_zplanes = 0;
4572
4573 assert(radv_image_is_tc_compat_htile(iview->image));
4574
4575 if (device->physical_device->rad_info.chip_class >= GFX9) {
4576 /* Default value for 32-bit depth surfaces. */
4577 max_zplanes = 4;
4578
4579 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4580 iview->image->info.samples > 1)
4581 max_zplanes = 2;
4582
4583 max_zplanes = max_zplanes + 1;
4584 } else {
4585 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4586 /* Do not enable Z plane compression for 16-bit depth
4587 * surfaces because isn't supported on GFX8. Only
4588 * 32-bit depth surfaces are supported by the hardware.
4589 * This allows to maintain shader compatibility and to
4590 * reduce the number of depth decompressions.
4591 */
4592 max_zplanes = 1;
4593 } else {
4594 if (iview->image->info.samples <= 1)
4595 max_zplanes = 5;
4596 else if (iview->image->info.samples <= 4)
4597 max_zplanes = 3;
4598 else
4599 max_zplanes = 2;
4600 }
4601 }
4602
4603 return max_zplanes;
4604 }
4605
4606 static void
4607 radv_initialise_ds_surface(struct radv_device *device,
4608 struct radv_ds_buffer_info *ds,
4609 struct radv_image_view *iview)
4610 {
4611 unsigned level = iview->base_mip;
4612 unsigned format, stencil_format;
4613 uint64_t va, s_offs, z_offs;
4614 bool stencil_only = false;
4615 const struct radv_image_plane *plane = &iview->image->planes[0];
4616 const struct radeon_surf *surf = &plane->surface;
4617
4618 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4619
4620 memset(ds, 0, sizeof(*ds));
4621 switch (iview->image->vk_format) {
4622 case VK_FORMAT_D24_UNORM_S8_UINT:
4623 case VK_FORMAT_X8_D24_UNORM_PACK32:
4624 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4625 ds->offset_scale = 2.0f;
4626 break;
4627 case VK_FORMAT_D16_UNORM:
4628 case VK_FORMAT_D16_UNORM_S8_UINT:
4629 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4630 ds->offset_scale = 4.0f;
4631 break;
4632 case VK_FORMAT_D32_SFLOAT:
4633 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4634 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4635 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4636 ds->offset_scale = 1.0f;
4637 break;
4638 case VK_FORMAT_S8_UINT:
4639 stencil_only = true;
4640 break;
4641 default:
4642 break;
4643 }
4644
4645 format = radv_translate_dbformat(iview->image->vk_format);
4646 stencil_format = surf->has_stencil ?
4647 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4648
4649 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4650 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4651 S_028008_SLICE_MAX(max_slice);
4652 if (device->physical_device->rad_info.chip_class >= GFX10) {
4653 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4654 S_028008_SLICE_MAX_HI(max_slice >> 11);
4655 }
4656
4657 ds->db_htile_data_base = 0;
4658 ds->db_htile_surface = 0;
4659
4660 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4661 s_offs = z_offs = va;
4662
4663 if (device->physical_device->rad_info.chip_class >= GFX9) {
4664 assert(surf->u.gfx9.surf_offset == 0);
4665 s_offs += surf->u.gfx9.stencil_offset;
4666
4667 ds->db_z_info = S_028038_FORMAT(format) |
4668 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4669 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4670 S_028038_MAXMIP(iview->image->info.levels - 1) |
4671 S_028038_ZRANGE_PRECISION(1);
4672 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4673 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4674
4675 if (device->physical_device->rad_info.chip_class == GFX9) {
4676 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4677 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4678 }
4679
4680 ds->db_depth_view |= S_028008_MIPID(level);
4681 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4682 S_02801C_Y_MAX(iview->image->info.height - 1);
4683
4684 if (radv_htile_enabled(iview->image, level)) {
4685 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4686
4687 if (radv_image_is_tc_compat_htile(iview->image)) {
4688 unsigned max_zplanes =
4689 radv_calc_decompress_on_z_planes(device, iview);
4690
4691 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4692
4693 if (device->physical_device->rad_info.chip_class >= GFX10) {
4694 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4695 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4696 } else {
4697 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4698 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4699 }
4700 }
4701
4702 if (!surf->has_stencil)
4703 /* Use all of the htile_buffer for depth if there's no stencil. */
4704 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4705 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4706 iview->image->htile_offset;
4707 ds->db_htile_data_base = va >> 8;
4708 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4709 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4710
4711 if (device->physical_device->rad_info.chip_class == GFX9) {
4712 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4713 }
4714 }
4715 } else {
4716 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4717
4718 if (stencil_only)
4719 level_info = &surf->u.legacy.stencil_level[level];
4720
4721 z_offs += surf->u.legacy.level[level].offset;
4722 s_offs += surf->u.legacy.stencil_level[level].offset;
4723
4724 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4725 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4726 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4727
4728 if (iview->image->info.samples > 1)
4729 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4730
4731 if (device->physical_device->rad_info.chip_class >= GFX7) {
4732 struct radeon_info *info = &device->physical_device->rad_info;
4733 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4734 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4735 unsigned macro_index = surf->u.legacy.macro_tile_index;
4736 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4737 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4738 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4739
4740 if (stencil_only)
4741 tile_mode = stencil_tile_mode;
4742
4743 ds->db_depth_info |=
4744 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4745 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4746 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4747 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4748 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4749 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4750 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4751 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4752 } else {
4753 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4754 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4755 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4756 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4757 if (stencil_only)
4758 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4759 }
4760
4761 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4762 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4763 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4764
4765 if (radv_htile_enabled(iview->image, level)) {
4766 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4767
4768 if (!surf->has_stencil &&
4769 !radv_image_is_tc_compat_htile(iview->image))
4770 /* Use all of the htile_buffer for depth if there's no stencil. */
4771 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4772
4773 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4774 iview->image->htile_offset;
4775 ds->db_htile_data_base = va >> 8;
4776 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4777
4778 if (radv_image_is_tc_compat_htile(iview->image)) {
4779 unsigned max_zplanes =
4780 radv_calc_decompress_on_z_planes(device, iview);
4781
4782 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4783 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4784 }
4785 }
4786 }
4787
4788 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4789 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4790 }
4791
4792 VkResult radv_CreateFramebuffer(
4793 VkDevice _device,
4794 const VkFramebufferCreateInfo* pCreateInfo,
4795 const VkAllocationCallbacks* pAllocator,
4796 VkFramebuffer* pFramebuffer)
4797 {
4798 RADV_FROM_HANDLE(radv_device, device, _device);
4799 struct radv_framebuffer *framebuffer;
4800
4801 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4802
4803 size_t size = sizeof(*framebuffer) +
4804 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4805 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4806 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4807 if (framebuffer == NULL)
4808 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4809
4810 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4811 framebuffer->width = pCreateInfo->width;
4812 framebuffer->height = pCreateInfo->height;
4813 framebuffer->layers = pCreateInfo->layers;
4814 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4815 VkImageView _iview = pCreateInfo->pAttachments[i];
4816 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4817 framebuffer->attachments[i].attachment = iview;
4818 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4819 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4820 } else {
4821 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4822 }
4823 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4824 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4825 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4826 }
4827
4828 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4829 return VK_SUCCESS;
4830 }
4831
4832 void radv_DestroyFramebuffer(
4833 VkDevice _device,
4834 VkFramebuffer _fb,
4835 const VkAllocationCallbacks* pAllocator)
4836 {
4837 RADV_FROM_HANDLE(radv_device, device, _device);
4838 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4839
4840 if (!fb)
4841 return;
4842 vk_free2(&device->alloc, pAllocator, fb);
4843 }
4844
4845 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4846 {
4847 switch (address_mode) {
4848 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4849 return V_008F30_SQ_TEX_WRAP;
4850 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4851 return V_008F30_SQ_TEX_MIRROR;
4852 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4853 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4854 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4855 return V_008F30_SQ_TEX_CLAMP_BORDER;
4856 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4857 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4858 default:
4859 unreachable("illegal tex wrap mode");
4860 break;
4861 }
4862 }
4863
4864 static unsigned
4865 radv_tex_compare(VkCompareOp op)
4866 {
4867 switch (op) {
4868 case VK_COMPARE_OP_NEVER:
4869 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4870 case VK_COMPARE_OP_LESS:
4871 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4872 case VK_COMPARE_OP_EQUAL:
4873 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4874 case VK_COMPARE_OP_LESS_OR_EQUAL:
4875 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4876 case VK_COMPARE_OP_GREATER:
4877 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4878 case VK_COMPARE_OP_NOT_EQUAL:
4879 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4880 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4881 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4882 case VK_COMPARE_OP_ALWAYS:
4883 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4884 default:
4885 unreachable("illegal compare mode");
4886 break;
4887 }
4888 }
4889
4890 static unsigned
4891 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4892 {
4893 switch (filter) {
4894 case VK_FILTER_NEAREST:
4895 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4896 V_008F38_SQ_TEX_XY_FILTER_POINT);
4897 case VK_FILTER_LINEAR:
4898 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4899 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4900 case VK_FILTER_CUBIC_IMG:
4901 default:
4902 fprintf(stderr, "illegal texture filter");
4903 return 0;
4904 }
4905 }
4906
4907 static unsigned
4908 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4909 {
4910 switch (mode) {
4911 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4912 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4913 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4914 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4915 default:
4916 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4917 }
4918 }
4919
4920 static unsigned
4921 radv_tex_bordercolor(VkBorderColor bcolor)
4922 {
4923 switch (bcolor) {
4924 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4925 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4926 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4927 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4928 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4929 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4930 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4931 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4932 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4933 default:
4934 break;
4935 }
4936 return 0;
4937 }
4938
4939 static unsigned
4940 radv_tex_aniso_filter(unsigned filter)
4941 {
4942 if (filter < 2)
4943 return 0;
4944 if (filter < 4)
4945 return 1;
4946 if (filter < 8)
4947 return 2;
4948 if (filter < 16)
4949 return 3;
4950 return 4;
4951 }
4952
4953 static unsigned
4954 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4955 {
4956 switch (mode) {
4957 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4958 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4959 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4960 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4961 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4962 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4963 default:
4964 break;
4965 }
4966 return 0;
4967 }
4968
4969 static uint32_t
4970 radv_get_max_anisotropy(struct radv_device *device,
4971 const VkSamplerCreateInfo *pCreateInfo)
4972 {
4973 if (device->force_aniso >= 0)
4974 return device->force_aniso;
4975
4976 if (pCreateInfo->anisotropyEnable &&
4977 pCreateInfo->maxAnisotropy > 1.0f)
4978 return (uint32_t)pCreateInfo->maxAnisotropy;
4979
4980 return 0;
4981 }
4982
4983 static void
4984 radv_init_sampler(struct radv_device *device,
4985 struct radv_sampler *sampler,
4986 const VkSamplerCreateInfo *pCreateInfo)
4987 {
4988 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4989 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4990 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4991 device->physical_device->rad_info.chip_class == GFX9;
4992 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4993
4994 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4995 vk_find_struct_const(pCreateInfo->pNext,
4996 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4997 if (sampler_reduction)
4998 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4999
5000 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5001 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5002 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5003 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5004 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5005 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5006 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5007 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5008 S_008F30_DISABLE_CUBE_WRAP(0) |
5009 S_008F30_COMPAT_MODE(compat_mode) |
5010 S_008F30_FILTER_MODE(filter_mode));
5011 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5012 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5013 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5014 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5015 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5016 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5017 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5018 S_008F38_MIP_POINT_PRECLAMP(0));
5019 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5020 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5021
5022 if (device->physical_device->rad_info.chip_class >= GFX10) {
5023 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5024 } else {
5025 sampler->state[2] |=
5026 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5027 S_008F38_FILTER_PREC_FIX(1) |
5028 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5029 }
5030 }
5031
5032 VkResult radv_CreateSampler(
5033 VkDevice _device,
5034 const VkSamplerCreateInfo* pCreateInfo,
5035 const VkAllocationCallbacks* pAllocator,
5036 VkSampler* pSampler)
5037 {
5038 RADV_FROM_HANDLE(radv_device, device, _device);
5039 struct radv_sampler *sampler;
5040
5041 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5042 vk_find_struct_const(pCreateInfo->pNext,
5043 SAMPLER_YCBCR_CONVERSION_INFO);
5044
5045 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5046
5047 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5048 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5049 if (!sampler)
5050 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5051
5052 radv_init_sampler(device, sampler, pCreateInfo);
5053
5054 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5055 *pSampler = radv_sampler_to_handle(sampler);
5056
5057 return VK_SUCCESS;
5058 }
5059
5060 void radv_DestroySampler(
5061 VkDevice _device,
5062 VkSampler _sampler,
5063 const VkAllocationCallbacks* pAllocator)
5064 {
5065 RADV_FROM_HANDLE(radv_device, device, _device);
5066 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5067
5068 if (!sampler)
5069 return;
5070 vk_free2(&device->alloc, pAllocator, sampler);
5071 }
5072
5073 /* vk_icd.h does not declare this function, so we declare it here to
5074 * suppress Wmissing-prototypes.
5075 */
5076 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5077 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5078
5079 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5080 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5081 {
5082 /* For the full details on loader interface versioning, see
5083 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5084 * What follows is a condensed summary, to help you navigate the large and
5085 * confusing official doc.
5086 *
5087 * - Loader interface v0 is incompatible with later versions. We don't
5088 * support it.
5089 *
5090 * - In loader interface v1:
5091 * - The first ICD entrypoint called by the loader is
5092 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5093 * entrypoint.
5094 * - The ICD must statically expose no other Vulkan symbol unless it is
5095 * linked with -Bsymbolic.
5096 * - Each dispatchable Vulkan handle created by the ICD must be
5097 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5098 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5099 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5100 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5101 * such loader-managed surfaces.
5102 *
5103 * - Loader interface v2 differs from v1 in:
5104 * - The first ICD entrypoint called by the loader is
5105 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5106 * statically expose this entrypoint.
5107 *
5108 * - Loader interface v3 differs from v2 in:
5109 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5110 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5111 * because the loader no longer does so.
5112 */
5113 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5114 return VK_SUCCESS;
5115 }
5116
5117 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5118 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5119 int *pFD)
5120 {
5121 RADV_FROM_HANDLE(radv_device, device, _device);
5122 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5123
5124 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5125
5126 /* At the moment, we support only the below handle types. */
5127 assert(pGetFdInfo->handleType ==
5128 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5129 pGetFdInfo->handleType ==
5130 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5131
5132 bool ret = radv_get_memory_fd(device, memory, pFD);
5133 if (ret == false)
5134 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5135 return VK_SUCCESS;
5136 }
5137
5138 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5139 VkExternalMemoryHandleTypeFlagBits handleType,
5140 int fd,
5141 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5142 {
5143 RADV_FROM_HANDLE(radv_device, device, _device);
5144
5145 switch (handleType) {
5146 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5147 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5148 return VK_SUCCESS;
5149
5150 default:
5151 /* The valid usage section for this function says:
5152 *
5153 * "handleType must not be one of the handle types defined as
5154 * opaque."
5155 *
5156 * So opaque handle types fall into the default "unsupported" case.
5157 */
5158 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5159 }
5160 }
5161
5162 static VkResult radv_import_opaque_fd(struct radv_device *device,
5163 int fd,
5164 uint32_t *syncobj)
5165 {
5166 uint32_t syncobj_handle = 0;
5167 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5168 if (ret != 0)
5169 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5170
5171 if (*syncobj)
5172 device->ws->destroy_syncobj(device->ws, *syncobj);
5173
5174 *syncobj = syncobj_handle;
5175 close(fd);
5176
5177 return VK_SUCCESS;
5178 }
5179
5180 static VkResult radv_import_sync_fd(struct radv_device *device,
5181 int fd,
5182 uint32_t *syncobj)
5183 {
5184 /* If we create a syncobj we do it locally so that if we have an error, we don't
5185 * leave a syncobj in an undetermined state in the fence. */
5186 uint32_t syncobj_handle = *syncobj;
5187 if (!syncobj_handle) {
5188 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5189 if (ret) {
5190 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5191 }
5192 }
5193
5194 if (fd == -1) {
5195 device->ws->signal_syncobj(device->ws, syncobj_handle);
5196 } else {
5197 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5198 if (ret != 0)
5199 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5200 }
5201
5202 *syncobj = syncobj_handle;
5203 if (fd != -1)
5204 close(fd);
5205
5206 return VK_SUCCESS;
5207 }
5208
5209 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5210 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5211 {
5212 RADV_FROM_HANDLE(radv_device, device, _device);
5213 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5214 uint32_t *syncobj_dst = NULL;
5215
5216 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5217 syncobj_dst = &sem->temp_syncobj;
5218 } else {
5219 syncobj_dst = &sem->syncobj;
5220 }
5221
5222 switch(pImportSemaphoreFdInfo->handleType) {
5223 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5224 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5225 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5226 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5227 default:
5228 unreachable("Unhandled semaphore handle type");
5229 }
5230 }
5231
5232 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5233 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5234 int *pFd)
5235 {
5236 RADV_FROM_HANDLE(radv_device, device, _device);
5237 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5238 int ret;
5239 uint32_t syncobj_handle;
5240
5241 if (sem->temp_syncobj)
5242 syncobj_handle = sem->temp_syncobj;
5243 else
5244 syncobj_handle = sem->syncobj;
5245
5246 switch(pGetFdInfo->handleType) {
5247 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5248 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5249 break;
5250 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5251 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5252 if (!ret) {
5253 if (sem->temp_syncobj) {
5254 close (sem->temp_syncobj);
5255 sem->temp_syncobj = 0;
5256 } else {
5257 device->ws->reset_syncobj(device->ws, syncobj_handle);
5258 }
5259 }
5260 break;
5261 default:
5262 unreachable("Unhandled semaphore handle type");
5263 }
5264
5265 if (ret)
5266 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5267 return VK_SUCCESS;
5268 }
5269
5270 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5271 VkPhysicalDevice physicalDevice,
5272 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5273 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5274 {
5275 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5276
5277 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5278 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5279 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5280 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5281 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5282 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5283 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5284 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5285 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5286 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5287 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5288 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5289 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5290 } else {
5291 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5292 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5293 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5294 }
5295 }
5296
5297 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5298 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5299 {
5300 RADV_FROM_HANDLE(radv_device, device, _device);
5301 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5302 uint32_t *syncobj_dst = NULL;
5303
5304
5305 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5306 syncobj_dst = &fence->temp_syncobj;
5307 } else {
5308 syncobj_dst = &fence->syncobj;
5309 }
5310
5311 switch(pImportFenceFdInfo->handleType) {
5312 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5313 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5314 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5315 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5316 default:
5317 unreachable("Unhandled fence handle type");
5318 }
5319 }
5320
5321 VkResult radv_GetFenceFdKHR(VkDevice _device,
5322 const VkFenceGetFdInfoKHR *pGetFdInfo,
5323 int *pFd)
5324 {
5325 RADV_FROM_HANDLE(radv_device, device, _device);
5326 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5327 int ret;
5328 uint32_t syncobj_handle;
5329
5330 if (fence->temp_syncobj)
5331 syncobj_handle = fence->temp_syncobj;
5332 else
5333 syncobj_handle = fence->syncobj;
5334
5335 switch(pGetFdInfo->handleType) {
5336 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5337 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5338 break;
5339 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5340 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5341 if (!ret) {
5342 if (fence->temp_syncobj) {
5343 close (fence->temp_syncobj);
5344 fence->temp_syncobj = 0;
5345 } else {
5346 device->ws->reset_syncobj(device->ws, syncobj_handle);
5347 }
5348 }
5349 break;
5350 default:
5351 unreachable("Unhandled fence handle type");
5352 }
5353
5354 if (ret)
5355 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5356 return VK_SUCCESS;
5357 }
5358
5359 void radv_GetPhysicalDeviceExternalFenceProperties(
5360 VkPhysicalDevice physicalDevice,
5361 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5362 VkExternalFenceProperties *pExternalFenceProperties)
5363 {
5364 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5365
5366 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5367 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5368 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5369 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5370 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5371 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5372 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5373 } else {
5374 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5375 pExternalFenceProperties->compatibleHandleTypes = 0;
5376 pExternalFenceProperties->externalFenceFeatures = 0;
5377 }
5378 }
5379
5380 VkResult
5381 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5382 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5383 const VkAllocationCallbacks* pAllocator,
5384 VkDebugReportCallbackEXT* pCallback)
5385 {
5386 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5387 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5388 pCreateInfo, pAllocator, &instance->alloc,
5389 pCallback);
5390 }
5391
5392 void
5393 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5394 VkDebugReportCallbackEXT _callback,
5395 const VkAllocationCallbacks* pAllocator)
5396 {
5397 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5398 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5399 _callback, pAllocator, &instance->alloc);
5400 }
5401
5402 void
5403 radv_DebugReportMessageEXT(VkInstance _instance,
5404 VkDebugReportFlagsEXT flags,
5405 VkDebugReportObjectTypeEXT objectType,
5406 uint64_t object,
5407 size_t location,
5408 int32_t messageCode,
5409 const char* pLayerPrefix,
5410 const char* pMessage)
5411 {
5412 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5413 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5414 object, location, messageCode, pLayerPrefix, pMessage);
5415 }
5416
5417 void
5418 radv_GetDeviceGroupPeerMemoryFeatures(
5419 VkDevice device,
5420 uint32_t heapIndex,
5421 uint32_t localDeviceIndex,
5422 uint32_t remoteDeviceIndex,
5423 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5424 {
5425 assert(localDeviceIndex == remoteDeviceIndex);
5426
5427 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5428 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5429 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5430 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5431 }
5432
5433 static const VkTimeDomainEXT radv_time_domains[] = {
5434 VK_TIME_DOMAIN_DEVICE_EXT,
5435 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5436 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5437 };
5438
5439 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5440 VkPhysicalDevice physicalDevice,
5441 uint32_t *pTimeDomainCount,
5442 VkTimeDomainEXT *pTimeDomains)
5443 {
5444 int d;
5445 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5446
5447 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5448 vk_outarray_append(&out, i) {
5449 *i = radv_time_domains[d];
5450 }
5451 }
5452
5453 return vk_outarray_status(&out);
5454 }
5455
5456 static uint64_t
5457 radv_clock_gettime(clockid_t clock_id)
5458 {
5459 struct timespec current;
5460 int ret;
5461
5462 ret = clock_gettime(clock_id, &current);
5463 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5464 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5465 if (ret < 0)
5466 return 0;
5467
5468 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5469 }
5470
5471 VkResult radv_GetCalibratedTimestampsEXT(
5472 VkDevice _device,
5473 uint32_t timestampCount,
5474 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5475 uint64_t *pTimestamps,
5476 uint64_t *pMaxDeviation)
5477 {
5478 RADV_FROM_HANDLE(radv_device, device, _device);
5479 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5480 int d;
5481 uint64_t begin, end;
5482 uint64_t max_clock_period = 0;
5483
5484 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5485
5486 for (d = 0; d < timestampCount; d++) {
5487 switch (pTimestampInfos[d].timeDomain) {
5488 case VK_TIME_DOMAIN_DEVICE_EXT:
5489 pTimestamps[d] = device->ws->query_value(device->ws,
5490 RADEON_TIMESTAMP);
5491 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5492 max_clock_period = MAX2(max_clock_period, device_period);
5493 break;
5494 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5495 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5496 max_clock_period = MAX2(max_clock_period, 1);
5497 break;
5498
5499 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5500 pTimestamps[d] = begin;
5501 break;
5502 default:
5503 pTimestamps[d] = 0;
5504 break;
5505 }
5506 }
5507
5508 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5509
5510 /*
5511 * The maximum deviation is the sum of the interval over which we
5512 * perform the sampling and the maximum period of any sampled
5513 * clock. That's because the maximum skew between any two sampled
5514 * clock edges is when the sampled clock with the largest period is
5515 * sampled at the end of that period but right at the beginning of the
5516 * sampling interval and some other clock is sampled right at the
5517 * begining of its sampling period and right at the end of the
5518 * sampling interval. Let's assume the GPU has the longest clock
5519 * period and that the application is sampling GPU and monotonic:
5520 *
5521 * s e
5522 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5523 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5524 *
5525 * g
5526 * 0 1 2 3
5527 * GPU -----_____-----_____-----_____-----_____
5528 *
5529 * m
5530 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5531 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5532 *
5533 * Interval <----------------->
5534 * Deviation <-------------------------->
5535 *
5536 * s = read(raw) 2
5537 * g = read(GPU) 1
5538 * m = read(monotonic) 2
5539 * e = read(raw) b
5540 *
5541 * We round the sample interval up by one tick to cover sampling error
5542 * in the interval clock
5543 */
5544
5545 uint64_t sample_interval = end - begin + 1;
5546
5547 *pMaxDeviation = sample_interval + max_clock_period;
5548
5549 return VK_SUCCESS;
5550 }
5551
5552 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5553 VkPhysicalDevice physicalDevice,
5554 VkSampleCountFlagBits samples,
5555 VkMultisamplePropertiesEXT* pMultisampleProperties)
5556 {
5557 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5558 VK_SAMPLE_COUNT_4_BIT |
5559 VK_SAMPLE_COUNT_8_BIT)) {
5560 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5561 } else {
5562 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5563 }
5564 }