2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_private.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
46 #include "util/debug.h"
49 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
51 uint32_t mesa_timestamp
, llvm_timestamp
;
53 memset(uuid
, 0, VK_UUID_SIZE
);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
58 memcpy(uuid
, &mesa_timestamp
, 4);
59 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
60 memcpy((char*)uuid
+ 8, &f
, 2);
61 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
66 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
68 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
71 static const VkExtensionProperties instance_extensions
[] = {
73 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
76 #ifdef VK_USE_PLATFORM_XCB_KHR
78 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
82 #ifdef VK_USE_PLATFORM_XLIB_KHR
84 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
88 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
90 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
95 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
99 .extensionName
= VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
103 .extensionName
= VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME
,
108 static const VkExtensionProperties common_device_extensions
[] = {
110 .extensionName
= VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME
,
114 .extensionName
= VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME
,
118 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
122 .extensionName
= VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME
,
126 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
130 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
134 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
138 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
142 .extensionName
= VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME
,
146 .extensionName
= VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME
,
150 .extensionName
= VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME
,
154 .extensionName
= VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
158 .extensionName
= VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME
,
162 .extensionName
= VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME
,
166 static const VkExtensionProperties ext_sema_device_extensions
[] = {
168 .extensionName
= VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME
,
172 .extensionName
= VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME
,
178 radv_extensions_register(struct radv_instance
*instance
,
179 struct radv_extensions
*extensions
,
180 const VkExtensionProperties
*new_ext
,
184 VkExtensionProperties
*new_ptr
;
186 assert(new_ext
&& num_ext
> 0);
189 return VK_ERROR_INITIALIZATION_FAILED
;
191 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
192 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
193 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
195 /* Old array continues to be valid, update nothing */
197 return VK_ERROR_OUT_OF_HOST_MEMORY
;
199 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
200 num_ext
* sizeof(VkExtensionProperties
));
201 extensions
->ext_array
= new_ptr
;
202 extensions
->num_ext
+= num_ext
;
208 radv_extensions_finish(struct radv_instance
*instance
,
209 struct radv_extensions
*extensions
)
214 radv_loge("Attemted to free invalid extension struct\n");
216 if (extensions
->ext_array
)
217 vk_free(&instance
->alloc
, extensions
->ext_array
);
221 is_extension_enabled(const VkExtensionProperties
*extensions
,
225 assert(extensions
&& name
);
227 for (uint32_t i
= 0; i
< num_ext
; i
++) {
228 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
236 get_chip_name(enum radeon_family family
)
239 case CHIP_TAHITI
: return "AMD RADV TAHITI";
240 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
241 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
242 case CHIP_OLAND
: return "AMD RADV OLAND";
243 case CHIP_HAINAN
: return "AMD RADV HAINAN";
244 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
245 case CHIP_KAVERI
: return "AMD RADV KAVERI";
246 case CHIP_KABINI
: return "AMD RADV KABINI";
247 case CHIP_HAWAII
: return "AMD RADV HAWAII";
248 case CHIP_MULLINS
: return "AMD RADV MULLINS";
249 case CHIP_TONGA
: return "AMD RADV TONGA";
250 case CHIP_ICELAND
: return "AMD RADV ICELAND";
251 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
252 case CHIP_FIJI
: return "AMD RADV FIJI";
253 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
254 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
255 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
256 case CHIP_STONEY
: return "AMD RADV STONEY";
257 case CHIP_VEGA10
: return "AMD RADV VEGA";
258 case CHIP_RAVEN
: return "AMD RADV RAVEN";
259 default: return "AMD RADV unknown";
264 radv_physical_device_init(struct radv_physical_device
*device
,
265 struct radv_instance
*instance
,
266 drmDevicePtr drm_device
)
268 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
270 drmVersionPtr version
;
273 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
275 return VK_ERROR_INCOMPATIBLE_DRIVER
;
277 version
= drmGetVersion(fd
);
280 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
281 "failed to get version %s: %m", path
);
284 if (strcmp(version
->name
, "amdgpu")) {
285 drmFreeVersion(version
);
287 return VK_ERROR_INCOMPATIBLE_DRIVER
;
289 drmFreeVersion(version
);
291 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
292 device
->instance
= instance
;
293 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
294 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
296 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
297 instance
->perftest_flags
);
299 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
303 device
->local_fd
= fd
;
304 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
305 result
= radv_init_wsi(device
);
306 if (result
!= VK_SUCCESS
) {
307 device
->ws
->destroy(device
->ws
);
311 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
312 radv_finish_wsi(device
);
313 device
->ws
->destroy(device
->ws
);
314 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
315 "cannot generate UUID");
319 result
= radv_extensions_register(instance
,
321 common_device_extensions
,
322 ARRAY_SIZE(common_device_extensions
));
323 if (result
!= VK_SUCCESS
)
326 if (device
->rad_info
.has_syncobj
) {
327 result
= radv_extensions_register(instance
,
329 ext_sema_device_extensions
,
330 ARRAY_SIZE(ext_sema_device_extensions
));
331 if (result
!= VK_SUCCESS
)
335 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
336 device
->name
= get_chip_name(device
->rad_info
.family
);
338 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
340 if (device
->rad_info
.family
== CHIP_STONEY
||
341 device
->rad_info
.chip_class
>= GFX9
) {
342 device
->has_rbplus
= true;
343 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
354 radv_physical_device_finish(struct radv_physical_device
*device
)
356 radv_extensions_finish(device
->instance
, &device
->extensions
);
357 radv_finish_wsi(device
);
358 device
->ws
->destroy(device
->ws
);
359 close(device
->local_fd
);
363 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
364 VkSystemAllocationScope allocationScope
)
370 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
371 size_t align
, VkSystemAllocationScope allocationScope
)
373 return realloc(pOriginal
, size
);
377 default_free_func(void *pUserData
, void *pMemory
)
382 static const VkAllocationCallbacks default_alloc
= {
384 .pfnAllocation
= default_alloc_func
,
385 .pfnReallocation
= default_realloc_func
,
386 .pfnFree
= default_free_func
,
389 static const struct debug_control radv_debug_options
[] = {
390 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
391 {"nodcc", RADV_DEBUG_NO_DCC
},
392 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
393 {"nocache", RADV_DEBUG_NO_CACHE
},
394 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
395 {"nohiz", RADV_DEBUG_NO_HIZ
},
396 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
397 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
398 {"allbos", RADV_DEBUG_ALL_BOS
},
399 {"noibs", RADV_DEBUG_NO_IBS
},
403 static const struct debug_control radv_perftest_options
[] = {
404 {"batchchain", RADV_PERFTEST_BATCHCHAIN
},
405 {"sisched", RADV_PERFTEST_SISCHED
},
409 VkResult
radv_CreateInstance(
410 const VkInstanceCreateInfo
* pCreateInfo
,
411 const VkAllocationCallbacks
* pAllocator
,
412 VkInstance
* pInstance
)
414 struct radv_instance
*instance
;
416 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
418 uint32_t client_version
;
419 if (pCreateInfo
->pApplicationInfo
&&
420 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
421 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
423 client_version
= VK_MAKE_VERSION(1, 0, 0);
426 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
427 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
428 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
429 "Client requested version %d.%d.%d",
430 VK_VERSION_MAJOR(client_version
),
431 VK_VERSION_MINOR(client_version
),
432 VK_VERSION_PATCH(client_version
));
435 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
436 if (!is_extension_enabled(instance_extensions
,
437 ARRAY_SIZE(instance_extensions
),
438 pCreateInfo
->ppEnabledExtensionNames
[i
]))
439 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
442 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
443 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
445 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
447 memset(instance
, 0, sizeof(*instance
));
449 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
452 instance
->alloc
= *pAllocator
;
454 instance
->alloc
= default_alloc
;
456 instance
->apiVersion
= client_version
;
457 instance
->physicalDeviceCount
= -1;
461 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
463 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
466 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
467 radv_perftest_options
);
469 *pInstance
= radv_instance_to_handle(instance
);
474 void radv_DestroyInstance(
475 VkInstance _instance
,
476 const VkAllocationCallbacks
* pAllocator
)
478 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
483 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
484 radv_physical_device_finish(instance
->physicalDevices
+ i
);
487 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
491 vk_free(&instance
->alloc
, instance
);
495 radv_enumerate_devices(struct radv_instance
*instance
)
497 /* TODO: Check for more devices ? */
498 drmDevicePtr devices
[8];
499 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
502 instance
->physicalDeviceCount
= 0;
504 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
506 return VK_ERROR_INCOMPATIBLE_DRIVER
;
508 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
509 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
510 devices
[i
]->bustype
== DRM_BUS_PCI
&&
511 devices
[i
]->deviceinfo
.pci
->vendor_id
== 0x1002) {
513 result
= radv_physical_device_init(instance
->physicalDevices
+
514 instance
->physicalDeviceCount
,
517 if (result
== VK_SUCCESS
)
518 ++instance
->physicalDeviceCount
;
519 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
523 drmFreeDevices(devices
, max_devices
);
528 VkResult
radv_EnumeratePhysicalDevices(
529 VkInstance _instance
,
530 uint32_t* pPhysicalDeviceCount
,
531 VkPhysicalDevice
* pPhysicalDevices
)
533 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
536 if (instance
->physicalDeviceCount
< 0) {
537 result
= radv_enumerate_devices(instance
);
538 if (result
!= VK_SUCCESS
&&
539 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
543 if (!pPhysicalDevices
) {
544 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
546 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
547 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
548 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
551 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
555 void radv_GetPhysicalDeviceFeatures(
556 VkPhysicalDevice physicalDevice
,
557 VkPhysicalDeviceFeatures
* pFeatures
)
559 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
560 bool is_gfx9
= pdevice
->rad_info
.chip_class
>= GFX9
;
561 memset(pFeatures
, 0, sizeof(*pFeatures
));
563 *pFeatures
= (VkPhysicalDeviceFeatures
) {
564 .robustBufferAccess
= true,
565 .fullDrawIndexUint32
= true,
566 .imageCubeArray
= true,
567 .independentBlend
= true,
568 .geometryShader
= !is_gfx9
,
569 .tessellationShader
= !is_gfx9
,
570 .sampleRateShading
= true,
571 .dualSrcBlend
= true,
573 .multiDrawIndirect
= true,
574 .drawIndirectFirstInstance
= true,
576 .depthBiasClamp
= true,
577 .fillModeNonSolid
= true,
582 .multiViewport
= true,
583 .samplerAnisotropy
= true,
584 .textureCompressionETC2
= false,
585 .textureCompressionASTC_LDR
= false,
586 .textureCompressionBC
= true,
587 .occlusionQueryPrecise
= true,
588 .pipelineStatisticsQuery
= true,
589 .vertexPipelineStoresAndAtomics
= true,
590 .fragmentStoresAndAtomics
= true,
591 .shaderTessellationAndGeometryPointSize
= true,
592 .shaderImageGatherExtended
= true,
593 .shaderStorageImageExtendedFormats
= true,
594 .shaderStorageImageMultisample
= false,
595 .shaderUniformBufferArrayDynamicIndexing
= true,
596 .shaderSampledImageArrayDynamicIndexing
= true,
597 .shaderStorageBufferArrayDynamicIndexing
= true,
598 .shaderStorageImageArrayDynamicIndexing
= true,
599 .shaderStorageImageReadWithoutFormat
= true,
600 .shaderStorageImageWriteWithoutFormat
= true,
601 .shaderClipDistance
= true,
602 .shaderCullDistance
= true,
603 .shaderFloat64
= true,
605 .shaderInt16
= false,
606 .sparseBinding
= true,
607 .variableMultisampleRate
= true,
608 .inheritedQueries
= true,
612 void radv_GetPhysicalDeviceFeatures2KHR(
613 VkPhysicalDevice physicalDevice
,
614 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
616 vk_foreach_struct(ext
, pFeatures
->pNext
) {
617 switch (ext
->sType
) {
618 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR
: {
619 VkPhysicalDeviceVariablePointerFeaturesKHR
*features
= (void *)ext
;
620 features
->variablePointersStorageBuffer
= true;
621 features
->variablePointers
= false;
628 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
631 void radv_GetPhysicalDeviceProperties(
632 VkPhysicalDevice physicalDevice
,
633 VkPhysicalDeviceProperties
* pProperties
)
635 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
636 VkSampleCountFlags sample_counts
= 0xf;
638 /* make sure that the entire descriptor set is addressable with a signed
639 * 32-bit int. So the sum of all limits scaled by descriptor size has to
640 * be at most 2 GiB. the combined image & samples object count as one of
641 * both. This limit is for the pipeline layout, not for the set layout, but
642 * there is no set limit, so we just set a pipeline limit. I don't think
643 * any app is going to hit this soon. */
644 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
645 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
646 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
647 32 /* sampler, largest when combined with image */ +
648 64 /* sampled image */ +
649 64 /* storage image */);
651 VkPhysicalDeviceLimits limits
= {
652 .maxImageDimension1D
= (1 << 14),
653 .maxImageDimension2D
= (1 << 14),
654 .maxImageDimension3D
= (1 << 11),
655 .maxImageDimensionCube
= (1 << 14),
656 .maxImageArrayLayers
= (1 << 11),
657 .maxTexelBufferElements
= 128 * 1024 * 1024,
658 .maxUniformBufferRange
= UINT32_MAX
,
659 .maxStorageBufferRange
= UINT32_MAX
,
660 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
661 .maxMemoryAllocationCount
= UINT32_MAX
,
662 .maxSamplerAllocationCount
= 64 * 1024,
663 .bufferImageGranularity
= 64, /* A cache line */
664 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
665 .maxBoundDescriptorSets
= MAX_SETS
,
666 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
667 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
668 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
669 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
670 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
671 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
672 .maxPerStageResources
= max_descriptor_set_size
,
673 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
674 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
675 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
676 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
677 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
678 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
679 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
680 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
681 .maxVertexInputAttributes
= 32,
682 .maxVertexInputBindings
= 32,
683 .maxVertexInputAttributeOffset
= 2047,
684 .maxVertexInputBindingStride
= 2048,
685 .maxVertexOutputComponents
= 128,
686 .maxTessellationGenerationLevel
= 64,
687 .maxTessellationPatchSize
= 32,
688 .maxTessellationControlPerVertexInputComponents
= 128,
689 .maxTessellationControlPerVertexOutputComponents
= 128,
690 .maxTessellationControlPerPatchOutputComponents
= 120,
691 .maxTessellationControlTotalOutputComponents
= 4096,
692 .maxTessellationEvaluationInputComponents
= 128,
693 .maxTessellationEvaluationOutputComponents
= 128,
694 .maxGeometryShaderInvocations
= 127,
695 .maxGeometryInputComponents
= 64,
696 .maxGeometryOutputComponents
= 128,
697 .maxGeometryOutputVertices
= 256,
698 .maxGeometryTotalOutputComponents
= 1024,
699 .maxFragmentInputComponents
= 128,
700 .maxFragmentOutputAttachments
= 8,
701 .maxFragmentDualSrcAttachments
= 1,
702 .maxFragmentCombinedOutputResources
= 8,
703 .maxComputeSharedMemorySize
= 32768,
704 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
705 .maxComputeWorkGroupInvocations
= 2048,
706 .maxComputeWorkGroupSize
= {
711 .subPixelPrecisionBits
= 4 /* FIXME */,
712 .subTexelPrecisionBits
= 4 /* FIXME */,
713 .mipmapPrecisionBits
= 4 /* FIXME */,
714 .maxDrawIndexedIndexValue
= UINT32_MAX
,
715 .maxDrawIndirectCount
= UINT32_MAX
,
716 .maxSamplerLodBias
= 16,
717 .maxSamplerAnisotropy
= 16,
718 .maxViewports
= MAX_VIEWPORTS
,
719 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
720 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
721 .viewportSubPixelBits
= 13, /* We take a float? */
722 .minMemoryMapAlignment
= 4096, /* A page */
723 .minTexelBufferOffsetAlignment
= 1,
724 .minUniformBufferOffsetAlignment
= 4,
725 .minStorageBufferOffsetAlignment
= 4,
726 .minTexelOffset
= -32,
727 .maxTexelOffset
= 31,
728 .minTexelGatherOffset
= -32,
729 .maxTexelGatherOffset
= 31,
730 .minInterpolationOffset
= -2,
731 .maxInterpolationOffset
= 2,
732 .subPixelInterpolationOffsetBits
= 8,
733 .maxFramebufferWidth
= (1 << 14),
734 .maxFramebufferHeight
= (1 << 14),
735 .maxFramebufferLayers
= (1 << 10),
736 .framebufferColorSampleCounts
= sample_counts
,
737 .framebufferDepthSampleCounts
= sample_counts
,
738 .framebufferStencilSampleCounts
= sample_counts
,
739 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
740 .maxColorAttachments
= MAX_RTS
,
741 .sampledImageColorSampleCounts
= sample_counts
,
742 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
743 .sampledImageDepthSampleCounts
= sample_counts
,
744 .sampledImageStencilSampleCounts
= sample_counts
,
745 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
746 .maxSampleMaskWords
= 1,
747 .timestampComputeAndGraphics
= true,
748 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
749 .maxClipDistances
= 8,
750 .maxCullDistances
= 8,
751 .maxCombinedClipAndCullDistances
= 8,
752 .discreteQueuePriorities
= 1,
753 .pointSizeRange
= { 0.125, 255.875 },
754 .lineWidthRange
= { 0.0, 7.9921875 },
755 .pointSizeGranularity
= (1.0 / 8.0),
756 .lineWidthGranularity
= (1.0 / 128.0),
757 .strictLines
= false, /* FINISHME */
758 .standardSampleLocations
= true,
759 .optimalBufferCopyOffsetAlignment
= 128,
760 .optimalBufferCopyRowPitchAlignment
= 128,
761 .nonCoherentAtomSize
= 64,
764 *pProperties
= (VkPhysicalDeviceProperties
) {
765 .apiVersion
= VK_MAKE_VERSION(1, 0, 42),
766 .driverVersion
= vk_get_driver_version(),
768 .deviceID
= pdevice
->rad_info
.pci_id
,
769 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
771 .sparseProperties
= {0},
774 strcpy(pProperties
->deviceName
, pdevice
->name
);
775 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
778 void radv_GetPhysicalDeviceProperties2KHR(
779 VkPhysicalDevice physicalDevice
,
780 VkPhysicalDeviceProperties2KHR
*pProperties
)
782 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
783 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
785 vk_foreach_struct(ext
, pProperties
->pNext
) {
786 switch (ext
->sType
) {
787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
788 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
789 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
790 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR
: {
794 VkPhysicalDeviceIDPropertiesKHR
*properties
= (VkPhysicalDeviceIDPropertiesKHR
*)ext
;
795 radv_device_get_cache_uuid(0, properties
->driverUUID
);
796 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
797 properties
->deviceLUIDValid
= false;
806 static void radv_get_physical_device_queue_family_properties(
807 struct radv_physical_device
* pdevice
,
809 VkQueueFamilyProperties
** pQueueFamilyProperties
)
811 int num_queue_families
= 1;
813 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
814 pdevice
->rad_info
.chip_class
>= CIK
&&
815 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
816 num_queue_families
++;
818 if (pQueueFamilyProperties
== NULL
) {
819 *pCount
= num_queue_families
;
828 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
829 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
830 VK_QUEUE_COMPUTE_BIT
|
831 VK_QUEUE_TRANSFER_BIT
|
832 VK_QUEUE_SPARSE_BINDING_BIT
,
834 .timestampValidBits
= 64,
835 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
840 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
841 pdevice
->rad_info
.chip_class
>= CIK
&&
842 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
844 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
845 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
846 VK_QUEUE_TRANSFER_BIT
|
847 VK_QUEUE_SPARSE_BINDING_BIT
,
848 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
849 .timestampValidBits
= 64,
850 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
858 void radv_GetPhysicalDeviceQueueFamilyProperties(
859 VkPhysicalDevice physicalDevice
,
861 VkQueueFamilyProperties
* pQueueFamilyProperties
)
863 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
864 if (!pQueueFamilyProperties
) {
865 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
868 VkQueueFamilyProperties
*properties
[] = {
869 pQueueFamilyProperties
+ 0,
870 pQueueFamilyProperties
+ 1,
871 pQueueFamilyProperties
+ 2,
873 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
874 assert(*pCount
<= 3);
877 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
878 VkPhysicalDevice physicalDevice
,
880 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
882 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
883 if (!pQueueFamilyProperties
) {
884 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
887 VkQueueFamilyProperties
*properties
[] = {
888 &pQueueFamilyProperties
[0].queueFamilyProperties
,
889 &pQueueFamilyProperties
[1].queueFamilyProperties
,
890 &pQueueFamilyProperties
[2].queueFamilyProperties
,
892 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
893 assert(*pCount
<= 3);
896 void radv_GetPhysicalDeviceMemoryProperties(
897 VkPhysicalDevice physicalDevice
,
898 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
900 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
902 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
904 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
905 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
906 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
907 .heapIndex
= RADV_MEM_HEAP_VRAM
,
909 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
910 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
911 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
912 .heapIndex
= RADV_MEM_HEAP_GTT
,
914 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
915 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
916 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
917 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
918 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
920 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
921 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
922 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
923 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
924 .heapIndex
= RADV_MEM_HEAP_GTT
,
927 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
928 uint64_t visible_vram_size
= MIN2(physical_device
->rad_info
.vram_size
,
929 physical_device
->rad_info
.vram_vis_size
);
931 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
932 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
933 .size
= physical_device
->rad_info
.vram_size
-
935 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
937 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
938 .size
= visible_vram_size
,
939 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
941 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
942 .size
= physical_device
->rad_info
.gart_size
,
947 void radv_GetPhysicalDeviceMemoryProperties2KHR(
948 VkPhysicalDevice physicalDevice
,
949 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
951 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
952 &pMemoryProperties
->memoryProperties
);
956 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
957 int queue_family_index
, int idx
)
959 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
960 queue
->device
= device
;
961 queue
->queue_family_index
= queue_family_index
;
962 queue
->queue_idx
= idx
;
964 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
966 return VK_ERROR_OUT_OF_HOST_MEMORY
;
972 radv_queue_finish(struct radv_queue
*queue
)
975 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
977 if (queue
->initial_preamble_cs
)
978 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
979 if (queue
->continue_preamble_cs
)
980 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
981 if (queue
->descriptor_bo
)
982 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
983 if (queue
->scratch_bo
)
984 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
985 if (queue
->esgs_ring_bo
)
986 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
987 if (queue
->gsvs_ring_bo
)
988 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
989 if (queue
->tess_factor_ring_bo
)
990 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
991 if (queue
->tess_offchip_ring_bo
)
992 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
993 if (queue
->compute_scratch_bo
)
994 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
998 radv_device_init_gs_info(struct radv_device
*device
)
1000 switch (device
->physical_device
->rad_info
.family
) {
1009 device
->gs_table_depth
= 16;
1018 case CHIP_POLARIS10
:
1019 case CHIP_POLARIS11
:
1020 case CHIP_POLARIS12
:
1023 device
->gs_table_depth
= 32;
1026 unreachable("unknown GPU");
1030 VkResult
radv_CreateDevice(
1031 VkPhysicalDevice physicalDevice
,
1032 const VkDeviceCreateInfo
* pCreateInfo
,
1033 const VkAllocationCallbacks
* pAllocator
,
1036 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1038 struct radv_device
*device
;
1040 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1041 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
1042 physical_device
->extensions
.num_ext
,
1043 pCreateInfo
->ppEnabledExtensionNames
[i
]))
1044 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
1047 /* Check enabled features */
1048 if (pCreateInfo
->pEnabledFeatures
) {
1049 VkPhysicalDeviceFeatures supported_features
;
1050 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1051 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1052 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1053 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1054 for (uint32_t i
= 0; i
< num_features
; i
++) {
1055 if (enabled_feature
[i
] && !supported_feature
[i
])
1056 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
1060 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
1062 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1064 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1066 memset(device
, 0, sizeof(*device
));
1068 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1069 device
->instance
= physical_device
->instance
;
1070 device
->physical_device
= physical_device
;
1072 device
->debug_flags
= device
->instance
->debug_flags
;
1074 device
->ws
= physical_device
->ws
;
1076 device
->alloc
= *pAllocator
;
1078 device
->alloc
= physical_device
->instance
->alloc
;
1080 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1081 list_inithead(&device
->shader_slabs
);
1083 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1084 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1085 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1087 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1088 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1089 if (!device
->queues
[qfi
]) {
1090 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1094 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1096 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1098 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1099 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
1100 if (result
!= VK_SUCCESS
)
1105 #if HAVE_LLVM < 0x0400
1106 device
->llvm_supports_spill
= false;
1108 device
->llvm_supports_spill
= true;
1111 /* The maximum number of scratch waves. Scratch space isn't divided
1112 * evenly between CUs. The number is only a function of the number of CUs.
1113 * We can decrease the constant to decrease the scratch buffer size.
1115 * sctx->scratch_waves must be >= the maximum posible size of
1116 * 1 threadgroup, so that the hw doesn't hang from being unable
1119 * The recommended value is 4 per CU at most. Higher numbers don't
1120 * bring much benefit, but they still occupy chip resources (think
1121 * async compute). I've seen ~2% performance difference between 4 and 32.
1123 uint32_t max_threads_per_block
= 2048;
1124 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1125 max_threads_per_block
/ 64);
1127 radv_device_init_gs_info(device
);
1129 device
->tess_offchip_block_dw_size
=
1130 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1131 device
->has_distributed_tess
=
1132 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1133 device
->physical_device
->rad_info
.max_se
>= 2;
1135 result
= radv_device_init_meta(device
);
1136 if (result
!= VK_SUCCESS
)
1139 radv_device_init_msaa(device
);
1141 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1142 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1144 case RADV_QUEUE_GENERAL
:
1145 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1146 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1147 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1149 case RADV_QUEUE_COMPUTE
:
1150 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1151 radeon_emit(device
->empty_cs
[family
], 0);
1154 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1156 device
->flush_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1158 case RADV_QUEUE_GENERAL
:
1159 case RADV_QUEUE_COMPUTE
:
1160 si_cs_emit_cache_flush(device
->flush_cs
[family
],
1162 device
->physical_device
->rad_info
.chip_class
,
1164 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1165 RADV_CMD_FLAG_INV_ICACHE
|
1166 RADV_CMD_FLAG_INV_SMEM_L1
|
1167 RADV_CMD_FLAG_INV_VMEM_L1
|
1168 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1171 device
->ws
->cs_finalize(device
->flush_cs
[family
]);
1173 device
->flush_shader_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1175 case RADV_QUEUE_GENERAL
:
1176 case RADV_QUEUE_COMPUTE
:
1177 si_cs_emit_cache_flush(device
->flush_shader_cs
[family
],
1179 device
->physical_device
->rad_info
.chip_class
,
1181 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1182 family
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) |
1183 RADV_CMD_FLAG_INV_ICACHE
|
1184 RADV_CMD_FLAG_INV_SMEM_L1
|
1185 RADV_CMD_FLAG_INV_VMEM_L1
|
1186 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1189 device
->ws
->cs_finalize(device
->flush_shader_cs
[family
]);
1192 if (getenv("RADV_TRACE_FILE")) {
1193 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
1194 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
1195 if (!device
->trace_bo
)
1198 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
1199 if (!device
->trace_id_ptr
)
1203 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1204 cik_create_gfx_config(device
);
1206 VkPipelineCacheCreateInfo ci
;
1207 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1210 ci
.pInitialData
= NULL
;
1211 ci
.initialDataSize
= 0;
1213 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1215 if (result
!= VK_SUCCESS
)
1218 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1220 *pDevice
= radv_device_to_handle(device
);
1224 if (device
->trace_bo
)
1225 device
->ws
->buffer_destroy(device
->trace_bo
);
1227 if (device
->gfx_init
)
1228 device
->ws
->buffer_destroy(device
->gfx_init
);
1230 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1231 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1232 radv_queue_finish(&device
->queues
[i
][q
]);
1233 if (device
->queue_count
[i
])
1234 vk_free(&device
->alloc
, device
->queues
[i
]);
1237 vk_free(&device
->alloc
, device
);
1241 void radv_DestroyDevice(
1243 const VkAllocationCallbacks
* pAllocator
)
1245 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1250 if (device
->trace_bo
)
1251 device
->ws
->buffer_destroy(device
->trace_bo
);
1253 if (device
->gfx_init
)
1254 device
->ws
->buffer_destroy(device
->gfx_init
);
1256 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1257 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1258 radv_queue_finish(&device
->queues
[i
][q
]);
1259 if (device
->queue_count
[i
])
1260 vk_free(&device
->alloc
, device
->queues
[i
]);
1261 if (device
->empty_cs
[i
])
1262 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1263 if (device
->flush_cs
[i
])
1264 device
->ws
->cs_destroy(device
->flush_cs
[i
]);
1265 if (device
->flush_shader_cs
[i
])
1266 device
->ws
->cs_destroy(device
->flush_shader_cs
[i
]);
1268 radv_device_finish_meta(device
);
1270 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1271 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1273 radv_destroy_shader_slabs(device
);
1275 vk_free(&device
->alloc
, device
);
1278 VkResult
radv_EnumerateInstanceExtensionProperties(
1279 const char* pLayerName
,
1280 uint32_t* pPropertyCount
,
1281 VkExtensionProperties
* pProperties
)
1283 if (pProperties
== NULL
) {
1284 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1288 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1289 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1291 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1292 return VK_INCOMPLETE
;
1297 VkResult
radv_EnumerateDeviceExtensionProperties(
1298 VkPhysicalDevice physicalDevice
,
1299 const char* pLayerName
,
1300 uint32_t* pPropertyCount
,
1301 VkExtensionProperties
* pProperties
)
1303 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1305 if (pProperties
== NULL
) {
1306 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1310 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1311 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1313 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1314 return VK_INCOMPLETE
;
1319 VkResult
radv_EnumerateInstanceLayerProperties(
1320 uint32_t* pPropertyCount
,
1321 VkLayerProperties
* pProperties
)
1323 if (pProperties
== NULL
) {
1324 *pPropertyCount
= 0;
1328 /* None supported at this time */
1329 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1332 VkResult
radv_EnumerateDeviceLayerProperties(
1333 VkPhysicalDevice physicalDevice
,
1334 uint32_t* pPropertyCount
,
1335 VkLayerProperties
* pProperties
)
1337 if (pProperties
== NULL
) {
1338 *pPropertyCount
= 0;
1342 /* None supported at this time */
1343 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1346 void radv_GetDeviceQueue(
1348 uint32_t queueFamilyIndex
,
1349 uint32_t queueIndex
,
1352 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1354 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1357 static void radv_dump_trace(struct radv_device
*device
,
1358 struct radeon_winsys_cs
*cs
)
1360 const char *filename
= getenv("RADV_TRACE_FILE");
1361 FILE *f
= fopen(filename
, "w");
1363 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1367 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1368 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1373 fill_geom_tess_rings(struct radv_queue
*queue
,
1375 bool add_sample_positions
,
1376 uint32_t esgs_ring_size
,
1377 struct radeon_winsys_bo
*esgs_ring_bo
,
1378 uint32_t gsvs_ring_size
,
1379 struct radeon_winsys_bo
*gsvs_ring_bo
,
1380 uint32_t tess_factor_ring_size
,
1381 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1382 uint32_t tess_offchip_ring_size
,
1383 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1385 uint64_t esgs_va
= 0, gsvs_va
= 0;
1386 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1387 uint32_t *desc
= &map
[4];
1390 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1392 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1393 if (tess_factor_ring_bo
)
1394 tess_factor_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1395 if (tess_offchip_ring_bo
)
1396 tess_offchip_va
= queue
->device
->ws
->buffer_get_va(tess_offchip_ring_bo
);
1398 /* stride 0, num records - size, add tid, swizzle, elsize4,
1401 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1402 S_008F04_STRIDE(0) |
1403 S_008F04_SWIZZLE_ENABLE(true);
1404 desc
[2] = esgs_ring_size
;
1405 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1409 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1410 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1411 S_008F0C_ELEMENT_SIZE(1) |
1412 S_008F0C_INDEX_STRIDE(3) |
1413 S_008F0C_ADD_TID_ENABLE(true);
1416 /* GS entry for ES->GS ring */
1417 /* stride 0, num records - size, elsize0,
1420 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1421 S_008F04_STRIDE(0) |
1422 S_008F04_SWIZZLE_ENABLE(false);
1423 desc
[2] = esgs_ring_size
;
1424 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1425 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1426 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1427 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1428 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1429 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1430 S_008F0C_ELEMENT_SIZE(0) |
1431 S_008F0C_INDEX_STRIDE(0) |
1432 S_008F0C_ADD_TID_ENABLE(false);
1435 /* VS entry for GS->VS ring */
1436 /* stride 0, num records - size, elsize0,
1439 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1440 S_008F04_STRIDE(0) |
1441 S_008F04_SWIZZLE_ENABLE(false);
1442 desc
[2] = gsvs_ring_size
;
1443 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1444 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1445 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1446 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1447 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1448 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1449 S_008F0C_ELEMENT_SIZE(0) |
1450 S_008F0C_INDEX_STRIDE(0) |
1451 S_008F0C_ADD_TID_ENABLE(false);
1454 /* stride gsvs_itemsize, num records 64
1455 elsize 4, index stride 16 */
1456 /* shader will patch stride and desc[2] */
1458 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1459 S_008F04_STRIDE(0) |
1460 S_008F04_SWIZZLE_ENABLE(true);
1462 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1463 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1464 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1465 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1466 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1467 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1468 S_008F0C_ELEMENT_SIZE(1) |
1469 S_008F0C_INDEX_STRIDE(1) |
1470 S_008F0C_ADD_TID_ENABLE(true);
1473 desc
[0] = tess_factor_va
;
1474 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1475 S_008F04_STRIDE(0) |
1476 S_008F04_SWIZZLE_ENABLE(false);
1477 desc
[2] = tess_factor_ring_size
;
1478 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1479 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1480 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1481 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1482 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1483 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1484 S_008F0C_ELEMENT_SIZE(0) |
1485 S_008F0C_INDEX_STRIDE(0) |
1486 S_008F0C_ADD_TID_ENABLE(false);
1489 desc
[0] = tess_offchip_va
;
1490 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1491 S_008F04_STRIDE(0) |
1492 S_008F04_SWIZZLE_ENABLE(false);
1493 desc
[2] = tess_offchip_ring_size
;
1494 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1495 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1496 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1497 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1498 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1499 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1500 S_008F0C_ELEMENT_SIZE(0) |
1501 S_008F0C_INDEX_STRIDE(0) |
1502 S_008F0C_ADD_TID_ENABLE(false);
1505 /* add sample positions after all rings */
1506 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1508 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1510 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1512 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1514 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1518 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1520 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1521 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1522 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1523 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1524 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1525 device
->physical_device
->rad_info
.max_se
;
1526 unsigned offchip_granularity
;
1527 unsigned hs_offchip_param
;
1528 switch (device
->tess_offchip_block_dw_size
) {
1533 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1536 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1540 switch (device
->physical_device
->rad_info
.chip_class
) {
1542 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1548 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1552 *max_offchip_buffers_p
= max_offchip_buffers
;
1553 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1554 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1555 --max_offchip_buffers
;
1557 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1558 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1561 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1563 return hs_offchip_param
;
1567 radv_get_preamble_cs(struct radv_queue
*queue
,
1568 uint32_t scratch_size
,
1569 uint32_t compute_scratch_size
,
1570 uint32_t esgs_ring_size
,
1571 uint32_t gsvs_ring_size
,
1572 bool needs_tess_rings
,
1573 bool needs_sample_positions
,
1574 struct radeon_winsys_cs
**initial_preamble_cs
,
1575 struct radeon_winsys_cs
**continue_preamble_cs
)
1577 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1578 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1579 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1580 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1581 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1582 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1583 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1584 struct radeon_winsys_cs
*dest_cs
[2] = {0};
1585 bool add_tess_rings
= false, add_sample_positions
= false;
1586 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1587 unsigned max_offchip_buffers
;
1588 unsigned hs_offchip_param
= 0;
1589 if (!queue
->has_tess_rings
) {
1590 if (needs_tess_rings
)
1591 add_tess_rings
= true;
1593 if (!queue
->has_sample_positions
) {
1594 if (needs_sample_positions
)
1595 add_sample_positions
= true;
1597 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1598 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1599 &max_offchip_buffers
);
1600 tess_offchip_ring_size
= max_offchip_buffers
*
1601 queue
->device
->tess_offchip_block_dw_size
* 4;
1603 if (scratch_size
<= queue
->scratch_size
&&
1604 compute_scratch_size
<= queue
->compute_scratch_size
&&
1605 esgs_ring_size
<= queue
->esgs_ring_size
&&
1606 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1607 !add_tess_rings
&& !add_sample_positions
&&
1608 queue
->initial_preamble_cs
) {
1609 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1610 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1611 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1612 *continue_preamble_cs
= NULL
;
1616 if (scratch_size
> queue
->scratch_size
) {
1617 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1621 RADEON_FLAG_NO_CPU_ACCESS
);
1625 scratch_bo
= queue
->scratch_bo
;
1627 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1628 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1629 compute_scratch_size
,
1632 RADEON_FLAG_NO_CPU_ACCESS
);
1633 if (!compute_scratch_bo
)
1637 compute_scratch_bo
= queue
->compute_scratch_bo
;
1639 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1640 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1644 RADEON_FLAG_NO_CPU_ACCESS
);
1648 esgs_ring_bo
= queue
->esgs_ring_bo
;
1649 esgs_ring_size
= queue
->esgs_ring_size
;
1652 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1653 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1657 RADEON_FLAG_NO_CPU_ACCESS
);
1661 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1662 gsvs_ring_size
= queue
->gsvs_ring_size
;
1665 if (add_tess_rings
) {
1666 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1667 tess_factor_ring_size
,
1670 RADEON_FLAG_NO_CPU_ACCESS
);
1671 if (!tess_factor_ring_bo
)
1673 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1674 tess_offchip_ring_size
,
1677 RADEON_FLAG_NO_CPU_ACCESS
);
1678 if (!tess_offchip_ring_bo
)
1681 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1682 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1685 if (scratch_bo
!= queue
->scratch_bo
||
1686 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1687 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1688 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1689 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1691 if (gsvs_ring_bo
|| esgs_ring_bo
||
1692 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1693 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1694 if (add_sample_positions
)
1695 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1697 else if (scratch_bo
)
1698 size
= 8; /* 2 dword */
1700 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1704 RADEON_FLAG_CPU_ACCESS
);
1708 descriptor_bo
= queue
->descriptor_bo
;
1710 for(int i
= 0; i
< 2; ++i
) {
1711 struct radeon_winsys_cs
*cs
= NULL
;
1712 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1713 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1720 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1723 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1726 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1728 if (tess_factor_ring_bo
)
1729 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1731 if (tess_offchip_ring_bo
)
1732 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1735 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1737 if (descriptor_bo
!= queue
->descriptor_bo
) {
1738 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1741 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1742 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1743 S_008F04_SWIZZLE_ENABLE(1);
1744 map
[0] = scratch_va
;
1748 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1749 add_sample_positions
)
1750 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1751 esgs_ring_size
, esgs_ring_bo
,
1752 gsvs_ring_size
, gsvs_ring_bo
,
1753 tess_factor_ring_size
, tess_factor_ring_bo
,
1754 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1756 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1759 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1760 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1761 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1762 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1763 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1766 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1767 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1768 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1769 radeon_emit(cs
, esgs_ring_size
>> 8);
1770 radeon_emit(cs
, gsvs_ring_size
>> 8);
1772 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1773 radeon_emit(cs
, esgs_ring_size
>> 8);
1774 radeon_emit(cs
, gsvs_ring_size
>> 8);
1778 if (tess_factor_ring_bo
) {
1779 uint64_t tf_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1780 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1781 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1782 S_030938_SIZE(tess_factor_ring_size
/ 4));
1783 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1785 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1786 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1789 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1791 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1792 S_008988_SIZE(tess_factor_ring_size
/ 4));
1793 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1795 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1800 if (descriptor_bo
) {
1801 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1802 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1803 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1804 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1805 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1806 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1808 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1810 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1811 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1812 radeon_emit(cs
, va
);
1813 radeon_emit(cs
, va
>> 32);
1817 if (compute_scratch_bo
) {
1818 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1819 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1820 S_008F04_SWIZZLE_ENABLE(1);
1822 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1824 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1825 radeon_emit(cs
, scratch_va
);
1826 radeon_emit(cs
, rsrc1
);
1830 si_cs_emit_cache_flush(cs
,
1832 queue
->device
->physical_device
->rad_info
.chip_class
,
1834 queue
->queue_family_index
== RING_COMPUTE
&&
1835 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1836 RADV_CMD_FLAG_INV_ICACHE
|
1837 RADV_CMD_FLAG_INV_SMEM_L1
|
1838 RADV_CMD_FLAG_INV_VMEM_L1
|
1839 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1842 if (!queue
->device
->ws
->cs_finalize(cs
))
1846 if (queue
->initial_preamble_cs
)
1847 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1849 if (queue
->continue_preamble_cs
)
1850 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1852 queue
->initial_preamble_cs
= dest_cs
[0];
1853 queue
->continue_preamble_cs
= dest_cs
[1];
1855 if (scratch_bo
!= queue
->scratch_bo
) {
1856 if (queue
->scratch_bo
)
1857 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1858 queue
->scratch_bo
= scratch_bo
;
1859 queue
->scratch_size
= scratch_size
;
1862 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1863 if (queue
->compute_scratch_bo
)
1864 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1865 queue
->compute_scratch_bo
= compute_scratch_bo
;
1866 queue
->compute_scratch_size
= compute_scratch_size
;
1869 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1870 if (queue
->esgs_ring_bo
)
1871 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1872 queue
->esgs_ring_bo
= esgs_ring_bo
;
1873 queue
->esgs_ring_size
= esgs_ring_size
;
1876 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1877 if (queue
->gsvs_ring_bo
)
1878 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1879 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1880 queue
->gsvs_ring_size
= gsvs_ring_size
;
1883 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1884 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1887 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1888 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1889 queue
->has_tess_rings
= true;
1892 if (descriptor_bo
!= queue
->descriptor_bo
) {
1893 if (queue
->descriptor_bo
)
1894 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1896 queue
->descriptor_bo
= descriptor_bo
;
1899 if (add_sample_positions
)
1900 queue
->has_sample_positions
= true;
1902 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1903 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1904 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1905 *continue_preamble_cs
= NULL
;
1908 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1910 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1911 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1912 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1913 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1914 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1915 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1916 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1917 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1918 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1919 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1920 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1921 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1922 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1923 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1924 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1925 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1928 static VkResult
radv_alloc_sem_counts(struct radv_winsys_sem_counts
*counts
,
1930 const VkSemaphore
*sems
,
1933 int syncobj_idx
= 0, sem_idx
= 0;
1937 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1938 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1940 if (sem
->temp_syncobj
|| sem
->syncobj
)
1941 counts
->syncobj_count
++;
1943 counts
->sem_count
++;
1946 if (counts
->syncobj_count
) {
1947 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
1948 if (!counts
->syncobj
)
1949 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1952 if (counts
->sem_count
) {
1953 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
1955 free(counts
->syncobj
);
1956 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1960 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1961 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1963 if (sem
->temp_syncobj
) {
1964 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
1966 /* after we wait on a temp import - drop it */
1967 sem
->temp_syncobj
= 0;
1970 else if (sem
->syncobj
)
1971 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
1974 counts
->sem
[sem_idx
++] = sem
->sem
;
1981 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
1983 free(sem_info
->wait
.syncobj
);
1984 free(sem_info
->wait
.sem
);
1985 free(sem_info
->signal
.syncobj
);
1986 free(sem_info
->signal
.sem
);
1989 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1991 const VkSemaphore
*wait_sems
,
1992 int num_signal_sems
,
1993 const VkSemaphore
*signal_sems
)
1996 memset(sem_info
, 0, sizeof(*sem_info
));
1998 ret
= radv_alloc_sem_counts(&sem_info
->wait
, num_wait_sems
, wait_sems
, true);
2001 ret
= radv_alloc_sem_counts(&sem_info
->signal
, num_signal_sems
, signal_sems
, false);
2003 radv_free_sem_info(sem_info
);
2005 /* caller can override these */
2006 sem_info
->cs_emit_wait
= true;
2007 sem_info
->cs_emit_signal
= true;
2011 VkResult
radv_QueueSubmit(
2013 uint32_t submitCount
,
2014 const VkSubmitInfo
* pSubmits
,
2017 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2018 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2019 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2020 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2022 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
2023 uint32_t scratch_size
= 0;
2024 uint32_t compute_scratch_size
= 0;
2025 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2026 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2028 bool fence_emitted
= false;
2029 bool tess_rings_needed
= false;
2030 bool sample_positions_needed
= false;
2032 /* Do this first so failing to allocate scratch buffers can't result in
2033 * partially executed submissions. */
2034 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2035 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2036 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2037 pSubmits
[i
].pCommandBuffers
[j
]);
2039 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2040 compute_scratch_size
= MAX2(compute_scratch_size
,
2041 cmd_buffer
->compute_scratch_size_needed
);
2042 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2043 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2044 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2045 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2049 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2050 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2051 sample_positions_needed
,
2052 &initial_preamble_cs
, &continue_preamble_cs
);
2053 if (result
!= VK_SUCCESS
)
2056 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2057 struct radeon_winsys_cs
**cs_array
;
2058 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2059 bool can_patch
= !do_flush
;
2061 struct radv_winsys_sem_info sem_info
;
2063 result
= radv_alloc_sem_info(&sem_info
,
2064 pSubmits
[i
].waitSemaphoreCount
,
2065 pSubmits
[i
].pWaitSemaphores
,
2066 pSubmits
[i
].signalSemaphoreCount
,
2067 pSubmits
[i
].pSignalSemaphores
);
2068 if (result
!= VK_SUCCESS
)
2071 if (!pSubmits
[i
].commandBufferCount
) {
2072 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2073 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2074 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2079 radv_loge("failed to submit CS %d\n", i
);
2082 fence_emitted
= true;
2084 radv_free_sem_info(&sem_info
);
2088 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
2089 (pSubmits
[i
].commandBufferCount
+ do_flush
));
2092 cs_array
[0] = pSubmits
[i
].waitSemaphoreCount
?
2093 queue
->device
->flush_shader_cs
[queue
->queue_family_index
] :
2094 queue
->device
->flush_cs
[queue
->queue_family_index
];
2096 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2097 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2098 pSubmits
[i
].pCommandBuffers
[j
]);
2099 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2101 cs_array
[j
+ do_flush
] = cmd_buffer
->cs
;
2102 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
2106 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
+ do_flush
; j
+= advance
) {
2107 advance
= MIN2(max_cs_submission
,
2108 pSubmits
[i
].commandBufferCount
+ do_flush
- j
);
2110 if (queue
->device
->trace_bo
)
2111 *queue
->device
->trace_id_ptr
= 0;
2113 sem_info
.cs_emit_wait
= j
== 0;
2114 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
+ do_flush
;
2116 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
2117 advance
, initial_preamble_cs
, continue_preamble_cs
,
2119 can_patch
, base_fence
);
2122 radv_loge("failed to submit CS %d\n", i
);
2125 fence_emitted
= true;
2126 if (queue
->device
->trace_bo
) {
2127 bool success
= queue
->device
->ws
->ctx_wait_idle(
2129 radv_queue_family_to_ring(
2130 queue
->queue_family_index
),
2133 if (!success
) { /* Hang */
2134 radv_dump_trace(queue
->device
, cs_array
[j
]);
2140 radv_free_sem_info(&sem_info
);
2145 if (!fence_emitted
) {
2146 struct radv_winsys_sem_info sem_info
= {0};
2147 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2148 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2149 1, NULL
, NULL
, &sem_info
,
2152 fence
->submitted
= true;
2158 VkResult
radv_QueueWaitIdle(
2161 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2163 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2164 radv_queue_family_to_ring(queue
->queue_family_index
),
2169 VkResult
radv_DeviceWaitIdle(
2172 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2174 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2175 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2176 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2182 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2183 VkInstance instance
,
2186 return radv_lookup_entrypoint(pName
);
2189 /* The loader wants us to expose a second GetInstanceProcAddr function
2190 * to work around certain LD_PRELOAD issues seen in apps.
2193 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2194 VkInstance instance
,
2198 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2199 VkInstance instance
,
2202 return radv_GetInstanceProcAddr(instance
, pName
);
2205 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2209 return radv_lookup_entrypoint(pName
);
2212 bool radv_get_memory_fd(struct radv_device
*device
,
2213 struct radv_device_memory
*memory
,
2216 struct radeon_bo_metadata metadata
;
2218 if (memory
->image
) {
2219 radv_init_metadata(device
, memory
->image
, &metadata
);
2220 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2223 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2227 VkResult
radv_AllocateMemory(
2229 const VkMemoryAllocateInfo
* pAllocateInfo
,
2230 const VkAllocationCallbacks
* pAllocator
,
2231 VkDeviceMemory
* pMem
)
2233 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2234 struct radv_device_memory
*mem
;
2236 enum radeon_bo_domain domain
;
2239 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2241 if (pAllocateInfo
->allocationSize
== 0) {
2242 /* Apparently, this is allowed */
2243 *pMem
= VK_NULL_HANDLE
;
2247 const VkImportMemoryFdInfoKHR
*import_info
=
2248 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
2249 const VkMemoryDedicatedAllocateInfoKHR
*dedicate_info
=
2250 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO_KHR
);
2252 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2253 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2255 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2257 if (dedicate_info
) {
2258 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2259 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2266 assert(import_info
->handleType
==
2267 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2268 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2271 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
2274 close(import_info
->fd
);
2279 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2280 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2281 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2282 domain
= RADEON_DOMAIN_GTT
;
2284 domain
= RADEON_DOMAIN_VRAM
;
2286 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2287 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2289 flags
|= RADEON_FLAG_CPU_ACCESS
;
2291 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2292 flags
|= RADEON_FLAG_GTT_WC
;
2294 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
2298 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2301 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2303 *pMem
= radv_device_memory_to_handle(mem
);
2308 vk_free2(&device
->alloc
, pAllocator
, mem
);
2313 void radv_FreeMemory(
2315 VkDeviceMemory _mem
,
2316 const VkAllocationCallbacks
* pAllocator
)
2318 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2319 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2324 device
->ws
->buffer_destroy(mem
->bo
);
2327 vk_free2(&device
->alloc
, pAllocator
, mem
);
2330 VkResult
radv_MapMemory(
2332 VkDeviceMemory _memory
,
2333 VkDeviceSize offset
,
2335 VkMemoryMapFlags flags
,
2338 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2339 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2346 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2352 return VK_ERROR_MEMORY_MAP_FAILED
;
2355 void radv_UnmapMemory(
2357 VkDeviceMemory _memory
)
2359 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2360 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2365 device
->ws
->buffer_unmap(mem
->bo
);
2368 VkResult
radv_FlushMappedMemoryRanges(
2370 uint32_t memoryRangeCount
,
2371 const VkMappedMemoryRange
* pMemoryRanges
)
2376 VkResult
radv_InvalidateMappedMemoryRanges(
2378 uint32_t memoryRangeCount
,
2379 const VkMappedMemoryRange
* pMemoryRanges
)
2384 void radv_GetBufferMemoryRequirements(
2387 VkMemoryRequirements
* pMemoryRequirements
)
2389 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2391 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2393 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2394 pMemoryRequirements
->alignment
= 4096;
2396 pMemoryRequirements
->alignment
= 16;
2398 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2401 void radv_GetBufferMemoryRequirements2KHR(
2403 const VkBufferMemoryRequirementsInfo2KHR
* pInfo
,
2404 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2406 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
2407 &pMemoryRequirements
->memoryRequirements
);
2409 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2410 switch (ext
->sType
) {
2411 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2412 VkMemoryDedicatedRequirementsKHR
*req
=
2413 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2414 req
->requiresDedicatedAllocation
= false;
2415 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2424 void radv_GetImageMemoryRequirements(
2427 VkMemoryRequirements
* pMemoryRequirements
)
2429 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2431 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2433 pMemoryRequirements
->size
= image
->size
;
2434 pMemoryRequirements
->alignment
= image
->alignment
;
2437 void radv_GetImageMemoryRequirements2KHR(
2439 const VkImageMemoryRequirementsInfo2KHR
* pInfo
,
2440 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2442 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
2443 &pMemoryRequirements
->memoryRequirements
);
2445 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
2447 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2448 switch (ext
->sType
) {
2449 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2450 VkMemoryDedicatedRequirementsKHR
*req
=
2451 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2452 req
->requiresDedicatedAllocation
= image
->shareable
;
2453 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2462 void radv_GetImageSparseMemoryRequirements(
2465 uint32_t* pSparseMemoryRequirementCount
,
2466 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2471 void radv_GetImageSparseMemoryRequirements2KHR(
2473 const VkImageSparseMemoryRequirementsInfo2KHR
* pInfo
,
2474 uint32_t* pSparseMemoryRequirementCount
,
2475 VkSparseImageMemoryRequirements2KHR
* pSparseMemoryRequirements
)
2480 void radv_GetDeviceMemoryCommitment(
2482 VkDeviceMemory memory
,
2483 VkDeviceSize
* pCommittedMemoryInBytes
)
2485 *pCommittedMemoryInBytes
= 0;
2488 VkResult
radv_BindBufferMemory(
2491 VkDeviceMemory _memory
,
2492 VkDeviceSize memoryOffset
)
2494 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2495 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2498 buffer
->bo
= mem
->bo
;
2499 buffer
->offset
= memoryOffset
;
2508 VkResult
radv_BindImageMemory(
2511 VkDeviceMemory _memory
,
2512 VkDeviceSize memoryOffset
)
2514 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2515 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2518 image
->bo
= mem
->bo
;
2519 image
->offset
= memoryOffset
;
2530 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2531 const VkSparseBufferMemoryBindInfo
*bind
)
2533 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2535 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2536 struct radv_device_memory
*mem
= NULL
;
2538 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2539 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2541 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2542 bind
->pBinds
[i
].resourceOffset
,
2543 bind
->pBinds
[i
].size
,
2544 mem
? mem
->bo
: NULL
,
2545 bind
->pBinds
[i
].memoryOffset
);
2550 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2551 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2553 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2555 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2556 struct radv_device_memory
*mem
= NULL
;
2558 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2559 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2561 device
->ws
->buffer_virtual_bind(image
->bo
,
2562 bind
->pBinds
[i
].resourceOffset
,
2563 bind
->pBinds
[i
].size
,
2564 mem
? mem
->bo
: NULL
,
2565 bind
->pBinds
[i
].memoryOffset
);
2569 VkResult
radv_QueueBindSparse(
2571 uint32_t bindInfoCount
,
2572 const VkBindSparseInfo
* pBindInfo
,
2575 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2576 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2577 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2578 bool fence_emitted
= false;
2580 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2581 struct radv_winsys_sem_info sem_info
;
2582 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2583 radv_sparse_buffer_bind_memory(queue
->device
,
2584 pBindInfo
[i
].pBufferBinds
+ j
);
2587 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2588 radv_sparse_image_opaque_bind_memory(queue
->device
,
2589 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2593 result
= radv_alloc_sem_info(&sem_info
,
2594 pBindInfo
[i
].waitSemaphoreCount
,
2595 pBindInfo
[i
].pWaitSemaphores
,
2596 pBindInfo
[i
].signalSemaphoreCount
,
2597 pBindInfo
[i
].pSignalSemaphores
);
2598 if (result
!= VK_SUCCESS
)
2601 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2602 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2603 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2607 fence_emitted
= true;
2609 fence
->submitted
= true;
2612 radv_free_sem_info(&sem_info
);
2616 if (fence
&& !fence_emitted
) {
2617 fence
->signalled
= true;
2623 VkResult
radv_CreateFence(
2625 const VkFenceCreateInfo
* pCreateInfo
,
2626 const VkAllocationCallbacks
* pAllocator
,
2629 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2630 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2632 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2635 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2637 memset(fence
, 0, sizeof(*fence
));
2638 fence
->submitted
= false;
2639 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2640 fence
->fence
= device
->ws
->create_fence();
2641 if (!fence
->fence
) {
2642 vk_free2(&device
->alloc
, pAllocator
, fence
);
2643 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2646 *pFence
= radv_fence_to_handle(fence
);
2651 void radv_DestroyFence(
2654 const VkAllocationCallbacks
* pAllocator
)
2656 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2657 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2661 device
->ws
->destroy_fence(fence
->fence
);
2662 vk_free2(&device
->alloc
, pAllocator
, fence
);
2665 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2667 uint64_t current_time
;
2670 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2671 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2673 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2675 return current_time
+ timeout
;
2678 VkResult
radv_WaitForFences(
2680 uint32_t fenceCount
,
2681 const VkFence
* pFences
,
2685 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2686 timeout
= radv_get_absolute_timeout(timeout
);
2688 if (!waitAll
&& fenceCount
> 1) {
2689 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2692 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2693 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2694 bool expired
= false;
2696 if (fence
->signalled
)
2699 if (!fence
->submitted
)
2702 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2706 fence
->signalled
= true;
2712 VkResult
radv_ResetFences(VkDevice device
,
2713 uint32_t fenceCount
,
2714 const VkFence
*pFences
)
2716 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2717 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2718 fence
->submitted
= fence
->signalled
= false;
2724 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2726 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2727 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2729 if (fence
->signalled
)
2731 if (!fence
->submitted
)
2732 return VK_NOT_READY
;
2734 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2735 return VK_NOT_READY
;
2741 // Queue semaphore functions
2743 VkResult
radv_CreateSemaphore(
2745 const VkSemaphoreCreateInfo
* pCreateInfo
,
2746 const VkAllocationCallbacks
* pAllocator
,
2747 VkSemaphore
* pSemaphore
)
2749 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2750 const VkExportSemaphoreCreateInfoKHR
*export
=
2751 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO_KHR
);
2752 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes
=
2753 export
? export
->handleTypes
: 0;
2755 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
2757 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2759 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2761 sem
->temp_syncobj
= 0;
2762 /* create a syncobject if we are going to export this semaphore */
2764 assert (device
->physical_device
->rad_info
.has_syncobj
);
2765 assert (handleTypes
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2766 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
2768 vk_free2(&device
->alloc
, pAllocator
, sem
);
2769 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2773 sem
->sem
= device
->ws
->create_sem(device
->ws
);
2775 vk_free2(&device
->alloc
, pAllocator
, sem
);
2776 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2781 *pSemaphore
= radv_semaphore_to_handle(sem
);
2785 void radv_DestroySemaphore(
2787 VkSemaphore _semaphore
,
2788 const VkAllocationCallbacks
* pAllocator
)
2790 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2791 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
2796 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
2798 device
->ws
->destroy_sem(sem
->sem
);
2799 vk_free2(&device
->alloc
, pAllocator
, sem
);
2802 VkResult
radv_CreateEvent(
2804 const VkEventCreateInfo
* pCreateInfo
,
2805 const VkAllocationCallbacks
* pAllocator
,
2808 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2809 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2811 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2814 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2816 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2818 RADEON_FLAG_CPU_ACCESS
);
2820 vk_free2(&device
->alloc
, pAllocator
, event
);
2821 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2824 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2826 *pEvent
= radv_event_to_handle(event
);
2831 void radv_DestroyEvent(
2834 const VkAllocationCallbacks
* pAllocator
)
2836 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2837 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2841 device
->ws
->buffer_destroy(event
->bo
);
2842 vk_free2(&device
->alloc
, pAllocator
, event
);
2845 VkResult
radv_GetEventStatus(
2849 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2851 if (*event
->map
== 1)
2852 return VK_EVENT_SET
;
2853 return VK_EVENT_RESET
;
2856 VkResult
radv_SetEvent(
2860 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2866 VkResult
radv_ResetEvent(
2870 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2876 VkResult
radv_CreateBuffer(
2878 const VkBufferCreateInfo
* pCreateInfo
,
2879 const VkAllocationCallbacks
* pAllocator
,
2882 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2883 struct radv_buffer
*buffer
;
2885 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2887 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2888 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2890 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2892 buffer
->size
= pCreateInfo
->size
;
2893 buffer
->usage
= pCreateInfo
->usage
;
2896 buffer
->flags
= pCreateInfo
->flags
;
2898 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2899 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2900 align64(buffer
->size
, 4096),
2901 4096, 0, RADEON_FLAG_VIRTUAL
);
2903 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2904 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2908 *pBuffer
= radv_buffer_to_handle(buffer
);
2913 void radv_DestroyBuffer(
2916 const VkAllocationCallbacks
* pAllocator
)
2918 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2919 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2924 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2925 device
->ws
->buffer_destroy(buffer
->bo
);
2927 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2930 static inline unsigned
2931 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2934 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2936 return image
->surface
.u
.legacy
.tiling_index
[level
];
2939 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2941 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2945 radv_initialise_color_surface(struct radv_device
*device
,
2946 struct radv_color_buffer_info
*cb
,
2947 struct radv_image_view
*iview
)
2949 const struct vk_format_description
*desc
;
2950 unsigned ntype
, format
, swap
, endian
;
2951 unsigned blend_clamp
= 0, blend_bypass
= 0;
2953 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2955 desc
= vk_format_description(iview
->vk_format
);
2957 memset(cb
, 0, sizeof(*cb
));
2959 /* Intensity is implemented as Red, so treat it that way. */
2960 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2962 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2964 cb
->cb_color_base
= va
>> 8;
2966 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2967 struct gfx9_surf_meta_flags meta
;
2968 if (iview
->image
->dcc_offset
)
2969 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
2971 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
2973 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2974 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2975 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2976 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2978 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
2980 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2981 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2983 cb
->cb_color_base
+= level_info
->offset
>> 8;
2984 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
2985 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
2987 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2988 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2989 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2991 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2992 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2993 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2995 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2996 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2998 if (iview
->image
->fmask
.size
) {
2999 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
3000 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
3001 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
3002 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
3004 /* This must be set for fast clear to work without FMASK. */
3005 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
3006 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3007 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3008 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3012 /* CMASK variables */
3013 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3014 va
+= iview
->image
->cmask
.offset
;
3015 cb
->cb_color_cmask
= va
>> 8;
3017 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3018 va
+= iview
->image
->dcc_offset
;
3019 cb
->cb_dcc_base
= va
>> 8;
3020 if (device
->physical_device
->rad_info
.chip_class
< GFX9
)
3021 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
3023 uint32_t max_slice
= radv_surface_layer_count(iview
);
3024 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
3025 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3027 if (iview
->image
->info
.samples
> 1) {
3028 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
3030 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
3031 S_028C74_NUM_FRAGMENTS(log_samples
);
3034 if (iview
->image
->fmask
.size
) {
3035 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
3036 cb
->cb_color_fmask
= va
>> 8;
3037 if (device
->physical_device
->rad_info
.chip_class
< GFX9
)
3038 cb
->cb_color_fmask
|= iview
->image
->surface
.tile_swizzle
;
3040 cb
->cb_color_fmask
= cb
->cb_color_base
;
3043 ntype
= radv_translate_color_numformat(iview
->vk_format
,
3045 vk_format_get_first_non_void_channel(iview
->vk_format
));
3046 format
= radv_translate_colorformat(iview
->vk_format
);
3047 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
3048 radv_finishme("Illegal color\n");
3049 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
3050 endian
= radv_colorformat_endian_swap(format
);
3052 /* blend clamp should be set for all NORM/SRGB types */
3053 if (ntype
== V_028C70_NUMBER_UNORM
||
3054 ntype
== V_028C70_NUMBER_SNORM
||
3055 ntype
== V_028C70_NUMBER_SRGB
)
3058 /* set blend bypass according to docs if SINT/UINT or
3059 8/24 COLOR variants */
3060 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
3061 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
3062 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
3067 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
3068 (format
== V_028C70_COLOR_8
||
3069 format
== V_028C70_COLOR_8_8
||
3070 format
== V_028C70_COLOR_8_8_8_8
))
3071 ->color_is_int8
= true;
3073 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
3074 S_028C70_COMP_SWAP(swap
) |
3075 S_028C70_BLEND_CLAMP(blend_clamp
) |
3076 S_028C70_BLEND_BYPASS(blend_bypass
) |
3077 S_028C70_SIMPLE_FLOAT(1) |
3078 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
3079 ntype
!= V_028C70_NUMBER_SNORM
&&
3080 ntype
!= V_028C70_NUMBER_SRGB
&&
3081 format
!= V_028C70_COLOR_8_24
&&
3082 format
!= V_028C70_COLOR_24_8
) |
3083 S_028C70_NUMBER_TYPE(ntype
) |
3084 S_028C70_ENDIAN(endian
);
3085 if (iview
->image
->info
.samples
> 1)
3086 if (iview
->image
->fmask
.size
)
3087 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
3089 if (iview
->image
->cmask
.size
&&
3090 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
3091 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
3093 if (iview
->image
->surface
.dcc_size
&& iview
->base_mip
< surf
->num_dcc_levels
)
3094 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
3096 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
3097 unsigned max_uncompressed_block_size
= 2;
3098 if (iview
->image
->info
.samples
> 1) {
3099 if (iview
->image
->surface
.bpe
== 1)
3100 max_uncompressed_block_size
= 0;
3101 else if (iview
->image
->surface
.bpe
== 2)
3102 max_uncompressed_block_size
= 1;
3105 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
3106 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3109 /* This must be set for fast clear to work without FMASK. */
3110 if (!iview
->image
->fmask
.size
&&
3111 device
->physical_device
->rad_info
.chip_class
== SI
) {
3112 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
3113 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
3116 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3117 uint32_t max_slice
= radv_surface_layer_count(iview
);
3118 unsigned mip0_depth
= iview
->base_layer
+ max_slice
- 1;
3120 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
3121 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
3122 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
3123 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->image
->info
.width
- 1) |
3124 S_028C68_MIP0_HEIGHT(iview
->image
->info
.height
- 1) |
3125 S_028C68_MAX_MIP(iview
->image
->info
.levels
);
3127 cb
->gfx9_epitch
= S_0287A0_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3133 radv_initialise_ds_surface(struct radv_device
*device
,
3134 struct radv_ds_buffer_info
*ds
,
3135 struct radv_image_view
*iview
)
3137 unsigned level
= iview
->base_mip
;
3138 unsigned format
, stencil_format
;
3139 uint64_t va
, s_offs
, z_offs
;
3140 bool stencil_only
= false;
3141 memset(ds
, 0, sizeof(*ds
));
3142 switch (iview
->image
->vk_format
) {
3143 case VK_FORMAT_D24_UNORM_S8_UINT
:
3144 case VK_FORMAT_X8_D24_UNORM_PACK32
:
3145 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3146 ds
->offset_scale
= 2.0f
;
3148 case VK_FORMAT_D16_UNORM
:
3149 case VK_FORMAT_D16_UNORM_S8_UINT
:
3150 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3151 ds
->offset_scale
= 4.0f
;
3153 case VK_FORMAT_D32_SFLOAT
:
3154 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
3155 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3156 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3157 ds
->offset_scale
= 1.0f
;
3159 case VK_FORMAT_S8_UINT
:
3160 stencil_only
= true;
3166 format
= radv_translate_dbformat(iview
->image
->vk_format
);
3167 stencil_format
= iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
?
3168 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
3170 uint32_t max_slice
= radv_surface_layer_count(iview
);
3171 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
3172 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3174 ds
->db_htile_data_base
= 0;
3175 ds
->db_htile_surface
= 0;
3177 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3178 s_offs
= z_offs
= va
;
3180 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3181 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
3182 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
3184 ds
->db_z_info
= S_028038_FORMAT(format
) |
3185 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
3186 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3187 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
3188 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
3189 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
3191 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3192 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
3193 ds
->db_depth_view
|= S_028008_MIPID(level
);
3195 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
3196 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
3198 /* Only use HTILE for the first level. */
3199 if (iview
->image
->surface
.htile_size
&& !level
) {
3200 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
3202 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
3203 /* Use all of the htile_buffer for depth if there's no stencil. */
3204 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
3205 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3206 iview
->image
->htile_offset
;
3207 ds
->db_htile_data_base
= va
>> 8;
3208 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
3209 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
3210 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
3213 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
3216 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
3218 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
3219 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
3221 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
3222 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
3223 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
3225 if (iview
->image
->info
.samples
> 1)
3226 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
3228 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3229 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
3230 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
3231 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3232 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
3233 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
3234 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
3235 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
3238 tile_mode
= stencil_tile_mode
;
3240 ds
->db_depth_info
|=
3241 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
3242 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
3243 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
3244 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
3245 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
3246 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
3247 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
3248 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
3250 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
3251 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3252 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
3253 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
3255 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3258 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
3259 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
3260 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
3262 if (iview
->image
->surface
.htile_size
&& !level
) {
3263 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
3265 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
3266 /* Use all of the htile_buffer for depth if there's no stencil. */
3267 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3269 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3270 iview
->image
->htile_offset
;
3271 ds
->db_htile_data_base
= va
>> 8;
3272 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3276 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3277 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3280 VkResult
radv_CreateFramebuffer(
3282 const VkFramebufferCreateInfo
* pCreateInfo
,
3283 const VkAllocationCallbacks
* pAllocator
,
3284 VkFramebuffer
* pFramebuffer
)
3286 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3287 struct radv_framebuffer
*framebuffer
;
3289 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3291 size_t size
= sizeof(*framebuffer
) +
3292 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3293 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3294 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3295 if (framebuffer
== NULL
)
3296 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3298 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3299 framebuffer
->width
= pCreateInfo
->width
;
3300 framebuffer
->height
= pCreateInfo
->height
;
3301 framebuffer
->layers
= pCreateInfo
->layers
;
3302 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3303 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3304 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3305 framebuffer
->attachments
[i
].attachment
= iview
;
3306 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3307 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3308 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3309 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3311 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3312 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3313 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3316 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3320 void radv_DestroyFramebuffer(
3323 const VkAllocationCallbacks
* pAllocator
)
3325 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3326 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3330 vk_free2(&device
->alloc
, pAllocator
, fb
);
3333 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3335 switch (address_mode
) {
3336 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3337 return V_008F30_SQ_TEX_WRAP
;
3338 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3339 return V_008F30_SQ_TEX_MIRROR
;
3340 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3341 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3342 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3343 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3344 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3345 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3347 unreachable("illegal tex wrap mode");
3353 radv_tex_compare(VkCompareOp op
)
3356 case VK_COMPARE_OP_NEVER
:
3357 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3358 case VK_COMPARE_OP_LESS
:
3359 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3360 case VK_COMPARE_OP_EQUAL
:
3361 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3362 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3363 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3364 case VK_COMPARE_OP_GREATER
:
3365 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3366 case VK_COMPARE_OP_NOT_EQUAL
:
3367 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3368 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3369 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3370 case VK_COMPARE_OP_ALWAYS
:
3371 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3373 unreachable("illegal compare mode");
3379 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3382 case VK_FILTER_NEAREST
:
3383 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3384 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3385 case VK_FILTER_LINEAR
:
3386 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3387 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3388 case VK_FILTER_CUBIC_IMG
:
3390 fprintf(stderr
, "illegal texture filter");
3396 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3399 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3400 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3401 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3402 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3404 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3409 radv_tex_bordercolor(VkBorderColor bcolor
)
3412 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3413 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3414 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3415 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3416 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3417 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3418 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3419 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3420 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3428 radv_tex_aniso_filter(unsigned filter
)
3442 radv_init_sampler(struct radv_device
*device
,
3443 struct radv_sampler
*sampler
,
3444 const VkSamplerCreateInfo
*pCreateInfo
)
3446 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3447 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3448 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3449 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3451 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3452 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3453 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3454 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3455 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3456 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3457 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3458 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3459 S_008F30_DISABLE_CUBE_WRAP(0) |
3460 S_008F30_COMPAT_MODE(is_vi
));
3461 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3462 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3463 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3464 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3465 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3466 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3467 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3468 S_008F38_MIP_POINT_PRECLAMP(0) |
3469 S_008F38_DISABLE_LSB_CEIL(1) |
3470 S_008F38_FILTER_PREC_FIX(1) |
3471 S_008F38_ANISO_OVERRIDE(is_vi
));
3472 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3473 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3476 VkResult
radv_CreateSampler(
3478 const VkSamplerCreateInfo
* pCreateInfo
,
3479 const VkAllocationCallbacks
* pAllocator
,
3480 VkSampler
* pSampler
)
3482 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3483 struct radv_sampler
*sampler
;
3485 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3487 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3488 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3490 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3492 radv_init_sampler(device
, sampler
, pCreateInfo
);
3493 *pSampler
= radv_sampler_to_handle(sampler
);
3498 void radv_DestroySampler(
3501 const VkAllocationCallbacks
* pAllocator
)
3503 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3504 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3508 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3511 /* vk_icd.h does not declare this function, so we declare it here to
3512 * suppress Wmissing-prototypes.
3514 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3515 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3517 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3518 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3520 /* For the full details on loader interface versioning, see
3521 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3522 * What follows is a condensed summary, to help you navigate the large and
3523 * confusing official doc.
3525 * - Loader interface v0 is incompatible with later versions. We don't
3528 * - In loader interface v1:
3529 * - The first ICD entrypoint called by the loader is
3530 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3532 * - The ICD must statically expose no other Vulkan symbol unless it is
3533 * linked with -Bsymbolic.
3534 * - Each dispatchable Vulkan handle created by the ICD must be
3535 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3536 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3537 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3538 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3539 * such loader-managed surfaces.
3541 * - Loader interface v2 differs from v1 in:
3542 * - The first ICD entrypoint called by the loader is
3543 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3544 * statically expose this entrypoint.
3546 * - Loader interface v3 differs from v2 in:
3547 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3548 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3549 * because the loader no longer does so.
3551 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3555 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
3556 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
3559 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3560 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
3562 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
3564 /* We support only one handle type. */
3565 assert(pGetFdInfo
->handleType
==
3566 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3568 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3570 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3574 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
3575 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
3577 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
3579 /* The valid usage section for this function says:
3581 * "handleType must not be one of the handle types defined as opaque."
3583 * Since we only handle opaque handles for now, there are no FD properties.
3585 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3588 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
3589 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
3591 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3592 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
3593 uint32_t syncobj_handle
= 0;
3594 assert(pImportSemaphoreFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3596 int ret
= device
->ws
->import_syncobj(device
->ws
, pImportSemaphoreFdInfo
->fd
, &syncobj_handle
);
3598 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3600 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR
) {
3601 sem
->temp_syncobj
= syncobj_handle
;
3603 sem
->syncobj
= syncobj_handle
;
3605 close(pImportSemaphoreFdInfo
->fd
);
3609 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
3610 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
3613 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3614 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
3616 uint32_t syncobj_handle
;
3618 assert(pGetFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3619 if (sem
->temp_syncobj
)
3620 syncobj_handle
= sem
->temp_syncobj
;
3622 syncobj_handle
= sem
->syncobj
;
3623 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
3625 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3629 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3630 VkPhysicalDevice physicalDevice
,
3631 const VkPhysicalDeviceExternalSemaphoreInfoKHR
* pExternalSemaphoreInfo
,
3632 VkExternalSemaphorePropertiesKHR
* pExternalSemaphoreProperties
)
3634 if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
3635 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3636 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3637 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
3638 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
3640 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
3641 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
3642 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;