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radv: Enable YCBCR conversion feature.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
121 }
122
123 static uint64_t
124 radv_get_visible_vram_size(struct radv_physical_device *device)
125 {
126 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
127 }
128
129 static uint64_t
130 radv_get_vram_size(struct radv_physical_device *device)
131 {
132 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
133 }
134
135 static void
136 radv_physical_device_init_mem_types(struct radv_physical_device *device)
137 {
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
139 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
140 uint64_t vram_size = radv_get_vram_size(device);
141 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
142 device->memory_properties.memoryHeapCount = 0;
143 if (vram_size > 0) {
144 vram_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
146 .size = vram_size,
147 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150 if (visible_vram_size) {
151 visible_vram_index = device->memory_properties.memoryHeapCount++;
152 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
153 .size = visible_vram_size,
154 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
155 };
156 }
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
162 };
163 }
164
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
166 unsigned type_count = 0;
167 if (vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
185 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
186 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
189 .heapIndex = visible_vram_index,
190 };
191 }
192 if (gart_index >= 0) {
193 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
194 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
195 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
198 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 .heapIndex = gart_index,
200 };
201 }
202 device->memory_properties.memoryTypeCount = type_count;
203 }
204
205 static void
206 radv_handle_env_var_force_family(struct radv_physical_device *device)
207 {
208 const char *family = getenv("RADV_FORCE_FAMILY");
209 unsigned i;
210
211 if (!family)
212 return;
213
214 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
215 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
216 /* Override family and chip_class. */
217 device->rad_info.family = i;
218
219 if (i >= CHIP_VEGA10)
220 device->rad_info.chip_class = GFX9;
221 else if (i >= CHIP_TONGA)
222 device->rad_info.chip_class = VI;
223 else if (i >= CHIP_BONAIRE)
224 device->rad_info.chip_class = CIK;
225 else
226 device->rad_info.chip_class = SI;
227
228 return;
229 }
230 }
231
232 fprintf(stderr, "radv: Unknown family: %s\n", family);
233 exit(1);
234 }
235
236 static VkResult
237 radv_physical_device_init(struct radv_physical_device *device,
238 struct radv_instance *instance,
239 drmDevicePtr drm_device)
240 {
241 const char *path = drm_device->nodes[DRM_NODE_RENDER];
242 VkResult result;
243 drmVersionPtr version;
244 int fd;
245 int master_fd = -1;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0) {
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Could not open device '%s'", path);
251
252 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
253 }
254
255 version = drmGetVersion(fd);
256 if (!version) {
257 close(fd);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not get the kernel driver version for device '%s'", path);
261
262 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
263 "failed to get version %s: %m", path);
264 }
265
266 if (strcmp(version->name, "amdgpu")) {
267 drmFreeVersion(version);
268 close(fd);
269
270 if (instance->debug_flags & RADV_DEBUG_STARTUP)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
272
273 return VK_ERROR_INCOMPATIBLE_DRIVER;
274 }
275 drmFreeVersion(version);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Found compatible device '%s'.", path);
279
280 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 device->instance = instance;
282
283 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
284 instance->perftest_flags);
285 if (!device->ws) {
286 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
287 goto fail;
288 }
289
290 if (instance->enabled_extensions.KHR_display) {
291 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
292 if (master_fd >= 0) {
293 uint32_t accel_working = 0;
294 struct drm_amdgpu_info request = {
295 .return_pointer = (uintptr_t)&accel_working,
296 .return_size = sizeof(accel_working),
297 .query = AMDGPU_INFO_ACCEL_WORKING
298 };
299
300 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
301 close(master_fd);
302 master_fd = -1;
303 }
304 }
305 }
306
307 device->master_fd = master_fd;
308 device->local_fd = fd;
309 device->ws->query_info(device->ws, &device->rad_info);
310
311 radv_handle_env_var_force_family(device);
312
313 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
314
315 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
316 device->ws->destroy(device->ws);
317 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags =
324 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
325 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
326
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
329 */
330 char buf[VK_UUID_SIZE * 2 + 1];
331 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
332 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
333
334 if (device->rad_info.chip_class < VI ||
335 device->rad_info.chip_class > GFX9)
336 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337
338 radv_get_driver_uuid(&device->driver_uuid);
339 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
340
341 if (device->rad_info.family == CHIP_STONEY ||
342 device->rad_info.chip_class >= GFX9) {
343 device->has_rbplus = true;
344 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
345 device->rad_info.family == CHIP_VEGA12 ||
346 device->rad_info.family == CHIP_RAVEN ||
347 device->rad_info.family == CHIP_RAVEN2;
348 }
349
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
351 * on SI.
352 */
353 device->has_clear_state = device->rad_info.chip_class >= CIK;
354
355 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
356
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
359 device->rad_info.family == CHIP_RAVEN;
360
361 /* Out-of-order primitive rasterization. */
362 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
363 device->rad_info.max_se >= 2;
364 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
365 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
366
367 device->dcc_msaa_allowed =
368 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
369
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
371 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
372 (device->rad_info.chip_class >= VI &&
373 device->rad_info.me_fw_feature >= 41);
374
375 radv_physical_device_init_mem_types(device);
376 radv_fill_device_extension_table(device, &device->supported_extensions);
377
378 device->bus_info = *drm_device->businfo.pci;
379
380 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
381 ac_print_gpu_info(&device->rad_info);
382
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
385 * semi-layers).
386 */
387 result = radv_init_wsi(device);
388 if (result != VK_SUCCESS) {
389 device->ws->destroy(device->ws);
390 vk_error(instance, result);
391 goto fail;
392 }
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {"nobinning", RADV_DEBUG_NOBINNING},
466 {NULL, 0}
467 };
468
469 const char *
470 radv_get_debug_option_name(int id)
471 {
472 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
473 return radv_debug_options[id].string;
474 }
475
476 static const struct debug_control radv_perftest_options[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
478 {"sisched", RADV_PERFTEST_SISCHED},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
481 {"bolist", RADV_PERFTEST_BO_LIST},
482 {NULL, 0}
483 };
484
485 const char *
486 radv_get_perftest_option_name(int id)
487 {
488 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
489 return radv_perftest_options[id].string;
490 }
491
492 static void
493 radv_handle_per_app_options(struct radv_instance *instance,
494 const VkApplicationInfo *info)
495 {
496 const char *name = info ? info->pApplicationName : NULL;
497
498 if (!name)
499 return;
500
501 if (!strcmp(name, "Talos - Linux - 32bit") ||
502 !strcmp(name, "Talos - Linux - 64bit")) {
503 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
506 */
507 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
508 }
509 } else if (!strcmp(name, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
512 }
513 }
514
515 static int radv_get_instance_extension_index(const char *name)
516 {
517 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
518 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
519 return i;
520 }
521 return -1;
522 }
523
524 static const char radv_dri_options_xml[] =
525 DRI_CONF_BEGIN
526 DRI_CONF_SECTION_QUALITY
527 DRI_CONF_ADAPTIVE_SYNC("true")
528 DRI_CONF_SECTION_END
529 DRI_CONF_END;
530
531 static void radv_init_dri_options(struct radv_instance *instance)
532 {
533 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
534 driParseConfigFiles(&instance->dri_options,
535 &instance->available_dri_options,
536 0, "radv", NULL);
537 }
538
539 VkResult radv_CreateInstance(
540 const VkInstanceCreateInfo* pCreateInfo,
541 const VkAllocationCallbacks* pAllocator,
542 VkInstance* pInstance)
543 {
544 struct radv_instance *instance;
545 VkResult result;
546
547 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
548
549 uint32_t client_version;
550 if (pCreateInfo->pApplicationInfo &&
551 pCreateInfo->pApplicationInfo->apiVersion != 0) {
552 client_version = pCreateInfo->pApplicationInfo->apiVersion;
553 } else {
554 client_version = VK_API_VERSION_1_0;
555 }
556
557 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
558 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
559 if (!instance)
560 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
561
562 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
563
564 if (pAllocator)
565 instance->alloc = *pAllocator;
566 else
567 instance->alloc = default_alloc;
568
569 instance->apiVersion = client_version;
570 instance->physicalDeviceCount = -1;
571
572 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
573 radv_debug_options);
574
575 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
576 radv_perftest_options);
577
578
579 if (instance->debug_flags & RADV_DEBUG_STARTUP)
580 radv_logi("Created an instance");
581
582 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
583 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
584 int index = radv_get_instance_extension_index(ext_name);
585
586 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
587 vk_free2(&default_alloc, pAllocator, instance);
588 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
589 }
590
591 instance->enabled_extensions.extensions[index] = true;
592 }
593
594 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
595 if (result != VK_SUCCESS) {
596 vk_free2(&default_alloc, pAllocator, instance);
597 return vk_error(instance, result);
598 }
599
600 _mesa_locale_init();
601 glsl_type_singleton_init_or_ref();
602
603 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
604
605 radv_init_dri_options(instance);
606 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
607
608 *pInstance = radv_instance_to_handle(instance);
609
610 return VK_SUCCESS;
611 }
612
613 void radv_DestroyInstance(
614 VkInstance _instance,
615 const VkAllocationCallbacks* pAllocator)
616 {
617 RADV_FROM_HANDLE(radv_instance, instance, _instance);
618
619 if (!instance)
620 return;
621
622 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
623 radv_physical_device_finish(instance->physicalDevices + i);
624 }
625
626 VG(VALGRIND_DESTROY_MEMPOOL(instance));
627
628 glsl_type_singleton_decref();
629 _mesa_locale_fini();
630
631 driDestroyOptionCache(&instance->dri_options);
632 driDestroyOptionInfo(&instance->available_dri_options);
633
634 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
635
636 vk_free(&instance->alloc, instance);
637 }
638
639 static VkResult
640 radv_enumerate_devices(struct radv_instance *instance)
641 {
642 /* TODO: Check for more devices ? */
643 drmDevicePtr devices[8];
644 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
645 int max_devices;
646
647 instance->physicalDeviceCount = 0;
648
649 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
650
651 if (instance->debug_flags & RADV_DEBUG_STARTUP)
652 radv_logi("Found %d drm nodes", max_devices);
653
654 if (max_devices < 1)
655 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
656
657 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
658 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
659 devices[i]->bustype == DRM_BUS_PCI &&
660 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
661
662 result = radv_physical_device_init(instance->physicalDevices +
663 instance->physicalDeviceCount,
664 instance,
665 devices[i]);
666 if (result == VK_SUCCESS)
667 ++instance->physicalDeviceCount;
668 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
669 break;
670 }
671 }
672 drmFreeDevices(devices, max_devices);
673
674 return result;
675 }
676
677 VkResult radv_EnumeratePhysicalDevices(
678 VkInstance _instance,
679 uint32_t* pPhysicalDeviceCount,
680 VkPhysicalDevice* pPhysicalDevices)
681 {
682 RADV_FROM_HANDLE(radv_instance, instance, _instance);
683 VkResult result;
684
685 if (instance->physicalDeviceCount < 0) {
686 result = radv_enumerate_devices(instance);
687 if (result != VK_SUCCESS &&
688 result != VK_ERROR_INCOMPATIBLE_DRIVER)
689 return result;
690 }
691
692 if (!pPhysicalDevices) {
693 *pPhysicalDeviceCount = instance->physicalDeviceCount;
694 } else {
695 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
696 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
697 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
698 }
699
700 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
701 : VK_SUCCESS;
702 }
703
704 VkResult radv_EnumeratePhysicalDeviceGroups(
705 VkInstance _instance,
706 uint32_t* pPhysicalDeviceGroupCount,
707 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
708 {
709 RADV_FROM_HANDLE(radv_instance, instance, _instance);
710 VkResult result;
711
712 if (instance->physicalDeviceCount < 0) {
713 result = radv_enumerate_devices(instance);
714 if (result != VK_SUCCESS &&
715 result != VK_ERROR_INCOMPATIBLE_DRIVER)
716 return result;
717 }
718
719 if (!pPhysicalDeviceGroupProperties) {
720 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
721 } else {
722 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
723 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
724 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
725 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
726 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
727 }
728 }
729 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
730 : VK_SUCCESS;
731 }
732
733 void radv_GetPhysicalDeviceFeatures(
734 VkPhysicalDevice physicalDevice,
735 VkPhysicalDeviceFeatures* pFeatures)
736 {
737 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
738 memset(pFeatures, 0, sizeof(*pFeatures));
739
740 *pFeatures = (VkPhysicalDeviceFeatures) {
741 .robustBufferAccess = true,
742 .fullDrawIndexUint32 = true,
743 .imageCubeArray = true,
744 .independentBlend = true,
745 .geometryShader = true,
746 .tessellationShader = true,
747 .sampleRateShading = true,
748 .dualSrcBlend = true,
749 .logicOp = true,
750 .multiDrawIndirect = true,
751 .drawIndirectFirstInstance = true,
752 .depthClamp = true,
753 .depthBiasClamp = true,
754 .fillModeNonSolid = true,
755 .depthBounds = true,
756 .wideLines = true,
757 .largePoints = true,
758 .alphaToOne = true,
759 .multiViewport = true,
760 .samplerAnisotropy = true,
761 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
762 .textureCompressionASTC_LDR = false,
763 .textureCompressionBC = true,
764 .occlusionQueryPrecise = true,
765 .pipelineStatisticsQuery = true,
766 .vertexPipelineStoresAndAtomics = true,
767 .fragmentStoresAndAtomics = true,
768 .shaderTessellationAndGeometryPointSize = true,
769 .shaderImageGatherExtended = true,
770 .shaderStorageImageExtendedFormats = true,
771 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
772 .shaderUniformBufferArrayDynamicIndexing = true,
773 .shaderSampledImageArrayDynamicIndexing = true,
774 .shaderStorageBufferArrayDynamicIndexing = true,
775 .shaderStorageImageArrayDynamicIndexing = true,
776 .shaderStorageImageReadWithoutFormat = true,
777 .shaderStorageImageWriteWithoutFormat = true,
778 .shaderClipDistance = true,
779 .shaderCullDistance = true,
780 .shaderFloat64 = true,
781 .shaderInt64 = true,
782 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
783 .sparseBinding = true,
784 .variableMultisampleRate = true,
785 .inheritedQueries = true,
786 };
787 }
788
789 void radv_GetPhysicalDeviceFeatures2(
790 VkPhysicalDevice physicalDevice,
791 VkPhysicalDeviceFeatures2 *pFeatures)
792 {
793 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
794 vk_foreach_struct(ext, pFeatures->pNext) {
795 switch (ext->sType) {
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
797 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
798 features->variablePointersStorageBuffer = true;
799 features->variablePointers = true;
800 break;
801 }
802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
803 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
804 features->multiview = true;
805 features->multiviewGeometryShader = true;
806 features->multiviewTessellationShader = true;
807 break;
808 }
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
810 VkPhysicalDeviceShaderDrawParameterFeatures *features =
811 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
812 features->shaderDrawParameters = true;
813 break;
814 }
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
816 VkPhysicalDeviceProtectedMemoryFeatures *features =
817 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
818 features->protectedMemory = false;
819 break;
820 }
821 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
822 VkPhysicalDevice16BitStorageFeatures *features =
823 (VkPhysicalDevice16BitStorageFeatures*)ext;
824 bool enabled = pdevice->rad_info.chip_class >= VI;
825 features->storageBuffer16BitAccess = enabled;
826 features->uniformAndStorageBuffer16BitAccess = enabled;
827 features->storagePushConstant16 = enabled;
828 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
829 break;
830 }
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
832 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
833 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
834 features->samplerYcbcrConversion = true;
835 break;
836 }
837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
838 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
839 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
840 features->shaderInputAttachmentArrayDynamicIndexing = true;
841 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
842 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
843 features->shaderUniformBufferArrayNonUniformIndexing = true;
844 features->shaderSampledImageArrayNonUniformIndexing = true;
845 features->shaderStorageBufferArrayNonUniformIndexing = true;
846 features->shaderStorageImageArrayNonUniformIndexing = true;
847 features->shaderInputAttachmentArrayNonUniformIndexing = true;
848 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
849 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
850 features->descriptorBindingUniformBufferUpdateAfterBind = true;
851 features->descriptorBindingSampledImageUpdateAfterBind = true;
852 features->descriptorBindingStorageImageUpdateAfterBind = true;
853 features->descriptorBindingStorageBufferUpdateAfterBind = true;
854 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
855 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
856 features->descriptorBindingUpdateUnusedWhilePending = true;
857 features->descriptorBindingPartiallyBound = true;
858 features->descriptorBindingVariableDescriptorCount = true;
859 features->runtimeDescriptorArray = true;
860 break;
861 }
862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
863 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
864 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
865 features->conditionalRendering = true;
866 features->inheritedConditionalRendering = false;
867 break;
868 }
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
870 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
871 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
872 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
873 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
877 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
878 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
879 features->transformFeedback = true;
880 features->geometryStreams = true;
881 break;
882 }
883 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
884 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
885 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
886 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
890 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
891 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
892 features->memoryPriority = VK_TRUE;
893 break;
894 }
895 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
896 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
897 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
898 features->bufferDeviceAddress = true;
899 features->bufferDeviceAddressCaptureReplay = false;
900 features->bufferDeviceAddressMultiDevice = false;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
904 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
905 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
906 features->depthClipEnable = true;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
910 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
911 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
912 features->hostQueryReset = true;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
916 VkPhysicalDevice8BitStorageFeaturesKHR *features =
917 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
918 bool enabled = pdevice->rad_info.chip_class >= VI;
919 features->storageBuffer8BitAccess = enabled;
920 features->uniformAndStorageBuffer8BitAccess = enabled;
921 features->storagePushConstant8 = enabled;
922 break;
923 }
924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
925 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
926 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
927 features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800;
928 features->shaderInt8 = true;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
932 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
933 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
934 /* TODO: Enable this once the driver supports 64-bit
935 * compare&swap atomic operations.
936 */
937 features->shaderBufferInt64Atomics = false;
938 features->shaderSharedInt64Atomics = false;
939 break;
940 }
941 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
942 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
943 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
944
945 features->inlineUniformBlock = true;
946 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
950 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
951 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
952 features->computeDerivativeGroupQuads = false;
953 features->computeDerivativeGroupLinear = true;
954 break;
955 }
956 default:
957 break;
958 }
959 }
960 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
961 }
962
963 void radv_GetPhysicalDeviceProperties(
964 VkPhysicalDevice physicalDevice,
965 VkPhysicalDeviceProperties* pProperties)
966 {
967 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
968 VkSampleCountFlags sample_counts = 0xf;
969
970 /* make sure that the entire descriptor set is addressable with a signed
971 * 32-bit int. So the sum of all limits scaled by descriptor size has to
972 * be at most 2 GiB. the combined image & samples object count as one of
973 * both. This limit is for the pipeline layout, not for the set layout, but
974 * there is no set limit, so we just set a pipeline limit. I don't think
975 * any app is going to hit this soon. */
976 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
977 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
978 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
979 32 /* sampler, largest when combined with image */ +
980 64 /* sampled image */ +
981 64 /* storage image */);
982
983 VkPhysicalDeviceLimits limits = {
984 .maxImageDimension1D = (1 << 14),
985 .maxImageDimension2D = (1 << 14),
986 .maxImageDimension3D = (1 << 11),
987 .maxImageDimensionCube = (1 << 14),
988 .maxImageArrayLayers = (1 << 11),
989 .maxTexelBufferElements = 128 * 1024 * 1024,
990 .maxUniformBufferRange = UINT32_MAX,
991 .maxStorageBufferRange = UINT32_MAX,
992 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
993 .maxMemoryAllocationCount = UINT32_MAX,
994 .maxSamplerAllocationCount = 64 * 1024,
995 .bufferImageGranularity = 64, /* A cache line */
996 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
997 .maxBoundDescriptorSets = MAX_SETS,
998 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
999 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1000 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1001 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1002 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1003 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1004 .maxPerStageResources = max_descriptor_set_size,
1005 .maxDescriptorSetSamplers = max_descriptor_set_size,
1006 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1007 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1008 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1009 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1010 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1011 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1012 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1013 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1014 .maxVertexInputBindings = MAX_VBS,
1015 .maxVertexInputAttributeOffset = 2047,
1016 .maxVertexInputBindingStride = 2048,
1017 .maxVertexOutputComponents = 128,
1018 .maxTessellationGenerationLevel = 64,
1019 .maxTessellationPatchSize = 32,
1020 .maxTessellationControlPerVertexInputComponents = 128,
1021 .maxTessellationControlPerVertexOutputComponents = 128,
1022 .maxTessellationControlPerPatchOutputComponents = 120,
1023 .maxTessellationControlTotalOutputComponents = 4096,
1024 .maxTessellationEvaluationInputComponents = 128,
1025 .maxTessellationEvaluationOutputComponents = 128,
1026 .maxGeometryShaderInvocations = 127,
1027 .maxGeometryInputComponents = 64,
1028 .maxGeometryOutputComponents = 128,
1029 .maxGeometryOutputVertices = 256,
1030 .maxGeometryTotalOutputComponents = 1024,
1031 .maxFragmentInputComponents = 128,
1032 .maxFragmentOutputAttachments = 8,
1033 .maxFragmentDualSrcAttachments = 1,
1034 .maxFragmentCombinedOutputResources = 8,
1035 .maxComputeSharedMemorySize = 32768,
1036 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1037 .maxComputeWorkGroupInvocations = 2048,
1038 .maxComputeWorkGroupSize = {
1039 2048,
1040 2048,
1041 2048
1042 },
1043 .subPixelPrecisionBits = 8,
1044 .subTexelPrecisionBits = 8,
1045 .mipmapPrecisionBits = 8,
1046 .maxDrawIndexedIndexValue = UINT32_MAX,
1047 .maxDrawIndirectCount = UINT32_MAX,
1048 .maxSamplerLodBias = 16,
1049 .maxSamplerAnisotropy = 16,
1050 .maxViewports = MAX_VIEWPORTS,
1051 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1052 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1053 .viewportSubPixelBits = 8,
1054 .minMemoryMapAlignment = 4096, /* A page */
1055 .minTexelBufferOffsetAlignment = 1,
1056 .minUniformBufferOffsetAlignment = 4,
1057 .minStorageBufferOffsetAlignment = 4,
1058 .minTexelOffset = -32,
1059 .maxTexelOffset = 31,
1060 .minTexelGatherOffset = -32,
1061 .maxTexelGatherOffset = 31,
1062 .minInterpolationOffset = -2,
1063 .maxInterpolationOffset = 2,
1064 .subPixelInterpolationOffsetBits = 8,
1065 .maxFramebufferWidth = (1 << 14),
1066 .maxFramebufferHeight = (1 << 14),
1067 .maxFramebufferLayers = (1 << 10),
1068 .framebufferColorSampleCounts = sample_counts,
1069 .framebufferDepthSampleCounts = sample_counts,
1070 .framebufferStencilSampleCounts = sample_counts,
1071 .framebufferNoAttachmentsSampleCounts = sample_counts,
1072 .maxColorAttachments = MAX_RTS,
1073 .sampledImageColorSampleCounts = sample_counts,
1074 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1075 .sampledImageDepthSampleCounts = sample_counts,
1076 .sampledImageStencilSampleCounts = sample_counts,
1077 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1078 .maxSampleMaskWords = 1,
1079 .timestampComputeAndGraphics = true,
1080 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1081 .maxClipDistances = 8,
1082 .maxCullDistances = 8,
1083 .maxCombinedClipAndCullDistances = 8,
1084 .discreteQueuePriorities = 2,
1085 .pointSizeRange = { 0.0, 8192.0 },
1086 .lineWidthRange = { 0.0, 7.9921875 },
1087 .pointSizeGranularity = (1.0 / 8.0),
1088 .lineWidthGranularity = (1.0 / 128.0),
1089 .strictLines = false, /* FINISHME */
1090 .standardSampleLocations = true,
1091 .optimalBufferCopyOffsetAlignment = 128,
1092 .optimalBufferCopyRowPitchAlignment = 128,
1093 .nonCoherentAtomSize = 64,
1094 };
1095
1096 *pProperties = (VkPhysicalDeviceProperties) {
1097 .apiVersion = radv_physical_device_api_version(pdevice),
1098 .driverVersion = vk_get_driver_version(),
1099 .vendorID = ATI_VENDOR_ID,
1100 .deviceID = pdevice->rad_info.pci_id,
1101 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1102 .limits = limits,
1103 .sparseProperties = {0},
1104 };
1105
1106 strcpy(pProperties->deviceName, pdevice->name);
1107 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1108 }
1109
1110 void radv_GetPhysicalDeviceProperties2(
1111 VkPhysicalDevice physicalDevice,
1112 VkPhysicalDeviceProperties2 *pProperties)
1113 {
1114 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1115 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1116
1117 vk_foreach_struct(ext, pProperties->pNext) {
1118 switch (ext->sType) {
1119 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1120 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1121 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1122 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1123 break;
1124 }
1125 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1126 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1127 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1128 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1129 properties->deviceLUIDValid = false;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1133 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1134 properties->maxMultiviewViewCount = MAX_VIEWS;
1135 properties->maxMultiviewInstanceIndex = INT_MAX;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1139 VkPhysicalDevicePointClippingProperties *properties =
1140 (VkPhysicalDevicePointClippingProperties*)ext;
1141 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1142 break;
1143 }
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1145 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1146 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1147 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1151 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1152 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1153 properties->minImportedHostPointerAlignment = 4096;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1157 VkPhysicalDeviceSubgroupProperties *properties =
1158 (VkPhysicalDeviceSubgroupProperties*)ext;
1159 properties->subgroupSize = 64;
1160 properties->supportedStages = VK_SHADER_STAGE_ALL;
1161 properties->supportedOperations =
1162 VK_SUBGROUP_FEATURE_BASIC_BIT |
1163 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1164 VK_SUBGROUP_FEATURE_QUAD_BIT |
1165 VK_SUBGROUP_FEATURE_VOTE_BIT;
1166 if (pdevice->rad_info.chip_class >= VI) {
1167 properties->supportedOperations |=
1168 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1169 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1170 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1171 }
1172 properties->quadOperationsInAllStages = true;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1176 VkPhysicalDeviceMaintenance3Properties *properties =
1177 (VkPhysicalDeviceMaintenance3Properties*)ext;
1178 /* Make sure everything is addressable by a signed 32-bit int, and
1179 * our largest descriptors are 96 bytes. */
1180 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1181 /* Our buffer size fields allow only this much */
1182 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1186 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1187 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1188 /* GFX6-8 only support single channel min/max filter. */
1189 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1190 properties->filterMinmaxSingleComponentFormats = true;
1191 break;
1192 }
1193 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1194 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1195 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1196
1197 /* Shader engines. */
1198 properties->shaderEngineCount =
1199 pdevice->rad_info.max_se;
1200 properties->shaderArraysPerEngineCount =
1201 pdevice->rad_info.max_sh_per_se;
1202 properties->computeUnitsPerShaderArray =
1203 pdevice->rad_info.num_good_cu_per_sh;
1204 properties->simdPerComputeUnit = 4;
1205 properties->wavefrontsPerSimd =
1206 pdevice->rad_info.family == CHIP_TONGA ||
1207 pdevice->rad_info.family == CHIP_ICELAND ||
1208 pdevice->rad_info.family == CHIP_POLARIS10 ||
1209 pdevice->rad_info.family == CHIP_POLARIS11 ||
1210 pdevice->rad_info.family == CHIP_POLARIS12 ||
1211 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1212 properties->wavefrontSize = 64;
1213
1214 /* SGPR. */
1215 properties->sgprsPerSimd =
1216 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1217 properties->minSgprAllocation =
1218 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1219 properties->maxSgprAllocation =
1220 pdevice->rad_info.family == CHIP_TONGA ||
1221 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1222 properties->sgprAllocationGranularity =
1223 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1224
1225 /* VGPR. */
1226 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1227 properties->minVgprAllocation = 4;
1228 properties->maxVgprAllocation = 256;
1229 properties->vgprAllocationGranularity = 4;
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1233 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1234 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1235 properties->maxVertexAttribDivisor = UINT32_MAX;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1239 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1240 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1241 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1242 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1243 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1244 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1245 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1246 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1247 properties->robustBufferAccessUpdateAfterBind = false;
1248 properties->quadDivergentImplicitLod = false;
1249
1250 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1251 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1252 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1253 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1254 32 /* sampler, largest when combined with image */ +
1255 64 /* sampled image */ +
1256 64 /* storage image */);
1257 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1258 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1259 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1260 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1261 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1262 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1263 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1264 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1265 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1266 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1267 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1268 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1269 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1270 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1271 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1272 break;
1273 }
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1275 VkPhysicalDeviceProtectedMemoryProperties *properties =
1276 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1277 properties->protectedNoFault = false;
1278 break;
1279 }
1280 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1281 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1282 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1283 properties->primitiveOverestimationSize = 0;
1284 properties->maxExtraPrimitiveOverestimationSize = 0;
1285 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1286 properties->primitiveUnderestimation = VK_FALSE;
1287 properties->conservativePointAndLineRasterization = VK_FALSE;
1288 properties->degenerateTrianglesRasterized = VK_FALSE;
1289 properties->degenerateLinesRasterized = VK_FALSE;
1290 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1291 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1292 break;
1293 }
1294 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1295 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1296 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1297 properties->pciDomain = pdevice->bus_info.domain;
1298 properties->pciBus = pdevice->bus_info.bus;
1299 properties->pciDevice = pdevice->bus_info.dev;
1300 properties->pciFunction = pdevice->bus_info.func;
1301 break;
1302 }
1303 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1304 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1305 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1306
1307 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1308 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1309 strcpy(driver_props->driverName, "radv");
1310
1311 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1312 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1313 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1314 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1315
1316 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1317 .major = 1,
1318 .minor = 1,
1319 .subminor = 2,
1320 .patch = 0,
1321 };
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1325 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1326 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1327 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1328 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1329 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1330 properties->maxTransformFeedbackStreamDataSize = 512;
1331 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1332 properties->maxTransformFeedbackBufferDataStride = 512;
1333 properties->transformFeedbackQueries = true;
1334 properties->transformFeedbackStreamsLinesTriangles = false;
1335 properties->transformFeedbackRasterizationStreamSelect = false;
1336 properties->transformFeedbackDraw = true;
1337 break;
1338 }
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1340 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1341 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1342
1343 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1344 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1345 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1346 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1347 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1348 break;
1349 }
1350 default:
1351 break;
1352 }
1353 }
1354 }
1355
1356 static void radv_get_physical_device_queue_family_properties(
1357 struct radv_physical_device* pdevice,
1358 uint32_t* pCount,
1359 VkQueueFamilyProperties** pQueueFamilyProperties)
1360 {
1361 int num_queue_families = 1;
1362 int idx;
1363 if (pdevice->rad_info.num_compute_rings > 0 &&
1364 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1365 num_queue_families++;
1366
1367 if (pQueueFamilyProperties == NULL) {
1368 *pCount = num_queue_families;
1369 return;
1370 }
1371
1372 if (!*pCount)
1373 return;
1374
1375 idx = 0;
1376 if (*pCount >= 1) {
1377 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1378 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1379 VK_QUEUE_COMPUTE_BIT |
1380 VK_QUEUE_TRANSFER_BIT |
1381 VK_QUEUE_SPARSE_BINDING_BIT,
1382 .queueCount = 1,
1383 .timestampValidBits = 64,
1384 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1385 };
1386 idx++;
1387 }
1388
1389 if (pdevice->rad_info.num_compute_rings > 0 &&
1390 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1391 if (*pCount > idx) {
1392 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1393 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1394 VK_QUEUE_TRANSFER_BIT |
1395 VK_QUEUE_SPARSE_BINDING_BIT,
1396 .queueCount = pdevice->rad_info.num_compute_rings,
1397 .timestampValidBits = 64,
1398 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1399 };
1400 idx++;
1401 }
1402 }
1403 *pCount = idx;
1404 }
1405
1406 void radv_GetPhysicalDeviceQueueFamilyProperties(
1407 VkPhysicalDevice physicalDevice,
1408 uint32_t* pCount,
1409 VkQueueFamilyProperties* pQueueFamilyProperties)
1410 {
1411 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1412 if (!pQueueFamilyProperties) {
1413 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1414 return;
1415 }
1416 VkQueueFamilyProperties *properties[] = {
1417 pQueueFamilyProperties + 0,
1418 pQueueFamilyProperties + 1,
1419 pQueueFamilyProperties + 2,
1420 };
1421 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1422 assert(*pCount <= 3);
1423 }
1424
1425 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1426 VkPhysicalDevice physicalDevice,
1427 uint32_t* pCount,
1428 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1429 {
1430 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1431 if (!pQueueFamilyProperties) {
1432 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1433 return;
1434 }
1435 VkQueueFamilyProperties *properties[] = {
1436 &pQueueFamilyProperties[0].queueFamilyProperties,
1437 &pQueueFamilyProperties[1].queueFamilyProperties,
1438 &pQueueFamilyProperties[2].queueFamilyProperties,
1439 };
1440 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1441 assert(*pCount <= 3);
1442 }
1443
1444 void radv_GetPhysicalDeviceMemoryProperties(
1445 VkPhysicalDevice physicalDevice,
1446 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1447 {
1448 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1449
1450 *pMemoryProperties = physical_device->memory_properties;
1451 }
1452
1453 static void
1454 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1455 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1456 {
1457 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1458 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1459 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1460 uint64_t vram_size = radv_get_vram_size(device);
1461 uint64_t gtt_size = device->rad_info.gart_size;
1462 uint64_t heap_budget, heap_usage;
1463
1464 /* For all memory heaps, the computation of budget is as follow:
1465 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1466 *
1467 * The Vulkan spec 1.1.97 says that the budget should include any
1468 * currently allocated device memory.
1469 *
1470 * Note that the application heap usages are not really accurate (eg.
1471 * in presence of shared buffers).
1472 */
1473 if (vram_size) {
1474 heap_usage = device->ws->query_value(device->ws,
1475 RADEON_ALLOCATED_VRAM);
1476
1477 heap_budget = vram_size -
1478 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1479 heap_usage;
1480
1481 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1482 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1483 }
1484
1485 if (visible_vram_size) {
1486 heap_usage = device->ws->query_value(device->ws,
1487 RADEON_ALLOCATED_VRAM_VIS);
1488
1489 heap_budget = visible_vram_size -
1490 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1491 heap_usage;
1492
1493 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1494 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1495 }
1496
1497 if (gtt_size) {
1498 heap_usage = device->ws->query_value(device->ws,
1499 RADEON_ALLOCATED_GTT);
1500
1501 heap_budget = gtt_size -
1502 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1503 heap_usage;
1504
1505 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1506 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1507 }
1508
1509 /* The heapBudget and heapUsage values must be zero for array elements
1510 * greater than or equal to
1511 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1512 */
1513 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1514 memoryBudget->heapBudget[i] = 0;
1515 memoryBudget->heapUsage[i] = 0;
1516 }
1517 }
1518
1519 void radv_GetPhysicalDeviceMemoryProperties2(
1520 VkPhysicalDevice physicalDevice,
1521 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1522 {
1523 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1524 &pMemoryProperties->memoryProperties);
1525
1526 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1527 vk_find_struct(pMemoryProperties->pNext,
1528 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1529 if (memory_budget)
1530 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1531 }
1532
1533 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1534 VkDevice _device,
1535 VkExternalMemoryHandleTypeFlagBits handleType,
1536 const void *pHostPointer,
1537 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1538 {
1539 RADV_FROM_HANDLE(radv_device, device, _device);
1540
1541 switch (handleType)
1542 {
1543 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1544 const struct radv_physical_device *physical_device = device->physical_device;
1545 uint32_t memoryTypeBits = 0;
1546 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1547 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1548 memoryTypeBits = (1 << i);
1549 break;
1550 }
1551 }
1552 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1553 return VK_SUCCESS;
1554 }
1555 default:
1556 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1557 }
1558 }
1559
1560 static enum radeon_ctx_priority
1561 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1562 {
1563 /* Default to MEDIUM when a specific global priority isn't requested */
1564 if (!pObj)
1565 return RADEON_CTX_PRIORITY_MEDIUM;
1566
1567 switch(pObj->globalPriority) {
1568 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1569 return RADEON_CTX_PRIORITY_REALTIME;
1570 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1571 return RADEON_CTX_PRIORITY_HIGH;
1572 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1573 return RADEON_CTX_PRIORITY_MEDIUM;
1574 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1575 return RADEON_CTX_PRIORITY_LOW;
1576 default:
1577 unreachable("Illegal global priority value");
1578 return RADEON_CTX_PRIORITY_INVALID;
1579 }
1580 }
1581
1582 static int
1583 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1584 uint32_t queue_family_index, int idx,
1585 VkDeviceQueueCreateFlags flags,
1586 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1587 {
1588 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1589 queue->device = device;
1590 queue->queue_family_index = queue_family_index;
1591 queue->queue_idx = idx;
1592 queue->priority = radv_get_queue_global_priority(global_priority);
1593 queue->flags = flags;
1594
1595 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1596 if (!queue->hw_ctx)
1597 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1598
1599 return VK_SUCCESS;
1600 }
1601
1602 static void
1603 radv_queue_finish(struct radv_queue *queue)
1604 {
1605 if (queue->hw_ctx)
1606 queue->device->ws->ctx_destroy(queue->hw_ctx);
1607
1608 if (queue->initial_full_flush_preamble_cs)
1609 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1610 if (queue->initial_preamble_cs)
1611 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1612 if (queue->continue_preamble_cs)
1613 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1614 if (queue->descriptor_bo)
1615 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1616 if (queue->scratch_bo)
1617 queue->device->ws->buffer_destroy(queue->scratch_bo);
1618 if (queue->esgs_ring_bo)
1619 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1620 if (queue->gsvs_ring_bo)
1621 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1622 if (queue->tess_rings_bo)
1623 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1624 if (queue->compute_scratch_bo)
1625 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1626 }
1627
1628 static void
1629 radv_bo_list_init(struct radv_bo_list *bo_list)
1630 {
1631 pthread_mutex_init(&bo_list->mutex, NULL);
1632 bo_list->list.count = bo_list->capacity = 0;
1633 bo_list->list.bos = NULL;
1634 }
1635
1636 static void
1637 radv_bo_list_finish(struct radv_bo_list *bo_list)
1638 {
1639 free(bo_list->list.bos);
1640 pthread_mutex_destroy(&bo_list->mutex);
1641 }
1642
1643 static VkResult radv_bo_list_add(struct radv_device *device,
1644 struct radeon_winsys_bo *bo)
1645 {
1646 struct radv_bo_list *bo_list = &device->bo_list;
1647
1648 if (bo->is_local)
1649 return VK_SUCCESS;
1650
1651 if (unlikely(!device->use_global_bo_list))
1652 return VK_SUCCESS;
1653
1654 pthread_mutex_lock(&bo_list->mutex);
1655 if (bo_list->list.count == bo_list->capacity) {
1656 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1657 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1658
1659 if (!data) {
1660 pthread_mutex_unlock(&bo_list->mutex);
1661 return VK_ERROR_OUT_OF_HOST_MEMORY;
1662 }
1663
1664 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1665 bo_list->capacity = capacity;
1666 }
1667
1668 bo_list->list.bos[bo_list->list.count++] = bo;
1669 pthread_mutex_unlock(&bo_list->mutex);
1670 return VK_SUCCESS;
1671 }
1672
1673 static void radv_bo_list_remove(struct radv_device *device,
1674 struct radeon_winsys_bo *bo)
1675 {
1676 struct radv_bo_list *bo_list = &device->bo_list;
1677
1678 if (bo->is_local)
1679 return;
1680
1681 if (unlikely(!device->use_global_bo_list))
1682 return;
1683
1684 pthread_mutex_lock(&bo_list->mutex);
1685 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1686 if (bo_list->list.bos[i] == bo) {
1687 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1688 --bo_list->list.count;
1689 break;
1690 }
1691 }
1692 pthread_mutex_unlock(&bo_list->mutex);
1693 }
1694
1695 static void
1696 radv_device_init_gs_info(struct radv_device *device)
1697 {
1698 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1699 device->physical_device->rad_info.family);
1700 }
1701
1702 static int radv_get_device_extension_index(const char *name)
1703 {
1704 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1705 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1706 return i;
1707 }
1708 return -1;
1709 }
1710
1711 static int
1712 radv_get_int_debug_option(const char *name, int default_value)
1713 {
1714 const char *str;
1715 int result;
1716
1717 str = getenv(name);
1718 if (!str) {
1719 result = default_value;
1720 } else {
1721 char *endptr;
1722
1723 result = strtol(str, &endptr, 0);
1724 if (str == endptr) {
1725 /* No digits founs. */
1726 result = default_value;
1727 }
1728 }
1729
1730 return result;
1731 }
1732
1733 VkResult radv_CreateDevice(
1734 VkPhysicalDevice physicalDevice,
1735 const VkDeviceCreateInfo* pCreateInfo,
1736 const VkAllocationCallbacks* pAllocator,
1737 VkDevice* pDevice)
1738 {
1739 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1740 VkResult result;
1741 struct radv_device *device;
1742
1743 bool keep_shader_info = false;
1744
1745 /* Check enabled features */
1746 if (pCreateInfo->pEnabledFeatures) {
1747 VkPhysicalDeviceFeatures supported_features;
1748 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1749 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1750 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1751 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1752 for (uint32_t i = 0; i < num_features; i++) {
1753 if (enabled_feature[i] && !supported_feature[i])
1754 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1755 }
1756 }
1757
1758 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1759 sizeof(*device), 8,
1760 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1761 if (!device)
1762 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1763
1764 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1765 device->instance = physical_device->instance;
1766 device->physical_device = physical_device;
1767
1768 device->ws = physical_device->ws;
1769 if (pAllocator)
1770 device->alloc = *pAllocator;
1771 else
1772 device->alloc = physical_device->instance->alloc;
1773
1774 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1775 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1776 int index = radv_get_device_extension_index(ext_name);
1777 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1778 vk_free(&device->alloc, device);
1779 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1780 }
1781
1782 device->enabled_extensions.extensions[index] = true;
1783 }
1784
1785 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1786
1787 /* With update after bind we can't attach bo's to the command buffer
1788 * from the descriptor set anymore, so we have to use a global BO list.
1789 */
1790 device->use_global_bo_list =
1791 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1792 device->enabled_extensions.EXT_descriptor_indexing ||
1793 device->enabled_extensions.EXT_buffer_device_address;
1794
1795 mtx_init(&device->shader_slab_mutex, mtx_plain);
1796 list_inithead(&device->shader_slabs);
1797
1798 radv_bo_list_init(&device->bo_list);
1799
1800 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1801 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1802 uint32_t qfi = queue_create->queueFamilyIndex;
1803 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1804 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1805
1806 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1807
1808 device->queues[qfi] = vk_alloc(&device->alloc,
1809 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1810 if (!device->queues[qfi]) {
1811 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1812 goto fail;
1813 }
1814
1815 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1816
1817 device->queue_count[qfi] = queue_create->queueCount;
1818
1819 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1820 result = radv_queue_init(device, &device->queues[qfi][q],
1821 qfi, q, queue_create->flags,
1822 global_priority);
1823 if (result != VK_SUCCESS)
1824 goto fail;
1825 }
1826 }
1827
1828 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1829 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1830
1831 /* Disabled and not implemented for now. */
1832 device->dfsm_allowed = device->pbb_allowed &&
1833 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1834 device->physical_device->rad_info.family == CHIP_RAVEN2);
1835
1836 #ifdef ANDROID
1837 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1838 #endif
1839
1840 /* The maximum number of scratch waves. Scratch space isn't divided
1841 * evenly between CUs. The number is only a function of the number of CUs.
1842 * We can decrease the constant to decrease the scratch buffer size.
1843 *
1844 * sctx->scratch_waves must be >= the maximum possible size of
1845 * 1 threadgroup, so that the hw doesn't hang from being unable
1846 * to start any.
1847 *
1848 * The recommended value is 4 per CU at most. Higher numbers don't
1849 * bring much benefit, but they still occupy chip resources (think
1850 * async compute). I've seen ~2% performance difference between 4 and 32.
1851 */
1852 uint32_t max_threads_per_block = 2048;
1853 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1854 max_threads_per_block / 64);
1855
1856 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1857
1858 if (device->physical_device->rad_info.chip_class >= CIK) {
1859 /* If the KMD allows it (there is a KMD hw register for it),
1860 * allow launching waves out-of-order.
1861 */
1862 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1863 }
1864
1865 radv_device_init_gs_info(device);
1866
1867 device->tess_offchip_block_dw_size =
1868 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1869 device->has_distributed_tess =
1870 device->physical_device->rad_info.chip_class >= VI &&
1871 device->physical_device->rad_info.max_se >= 2;
1872
1873 if (getenv("RADV_TRACE_FILE")) {
1874 const char *filename = getenv("RADV_TRACE_FILE");
1875
1876 keep_shader_info = true;
1877
1878 if (!radv_init_trace(device))
1879 goto fail;
1880
1881 fprintf(stderr, "*****************************************************************************\n");
1882 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1883 fprintf(stderr, "*****************************************************************************\n");
1884
1885 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1886 radv_dump_enabled_options(device, stderr);
1887 }
1888
1889 device->keep_shader_info = keep_shader_info;
1890
1891 result = radv_device_init_meta(device);
1892 if (result != VK_SUCCESS)
1893 goto fail;
1894
1895 radv_device_init_msaa(device);
1896
1897 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1898 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1899 switch (family) {
1900 case RADV_QUEUE_GENERAL:
1901 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1902 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1903 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1904 break;
1905 case RADV_QUEUE_COMPUTE:
1906 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1907 radeon_emit(device->empty_cs[family], 0);
1908 break;
1909 }
1910 device->ws->cs_finalize(device->empty_cs[family]);
1911 }
1912
1913 if (device->physical_device->rad_info.chip_class >= CIK)
1914 cik_create_gfx_config(device);
1915
1916 VkPipelineCacheCreateInfo ci;
1917 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1918 ci.pNext = NULL;
1919 ci.flags = 0;
1920 ci.pInitialData = NULL;
1921 ci.initialDataSize = 0;
1922 VkPipelineCache pc;
1923 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1924 &ci, NULL, &pc);
1925 if (result != VK_SUCCESS)
1926 goto fail_meta;
1927
1928 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1929
1930 device->force_aniso =
1931 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1932 if (device->force_aniso >= 0) {
1933 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1934 1 << util_logbase2(device->force_aniso));
1935 }
1936
1937 *pDevice = radv_device_to_handle(device);
1938 return VK_SUCCESS;
1939
1940 fail_meta:
1941 radv_device_finish_meta(device);
1942 fail:
1943 radv_bo_list_finish(&device->bo_list);
1944
1945 if (device->trace_bo)
1946 device->ws->buffer_destroy(device->trace_bo);
1947
1948 if (device->gfx_init)
1949 device->ws->buffer_destroy(device->gfx_init);
1950
1951 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1952 for (unsigned q = 0; q < device->queue_count[i]; q++)
1953 radv_queue_finish(&device->queues[i][q]);
1954 if (device->queue_count[i])
1955 vk_free(&device->alloc, device->queues[i]);
1956 }
1957
1958 vk_free(&device->alloc, device);
1959 return result;
1960 }
1961
1962 void radv_DestroyDevice(
1963 VkDevice _device,
1964 const VkAllocationCallbacks* pAllocator)
1965 {
1966 RADV_FROM_HANDLE(radv_device, device, _device);
1967
1968 if (!device)
1969 return;
1970
1971 if (device->trace_bo)
1972 device->ws->buffer_destroy(device->trace_bo);
1973
1974 if (device->gfx_init)
1975 device->ws->buffer_destroy(device->gfx_init);
1976
1977 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1978 for (unsigned q = 0; q < device->queue_count[i]; q++)
1979 radv_queue_finish(&device->queues[i][q]);
1980 if (device->queue_count[i])
1981 vk_free(&device->alloc, device->queues[i]);
1982 if (device->empty_cs[i])
1983 device->ws->cs_destroy(device->empty_cs[i]);
1984 }
1985 radv_device_finish_meta(device);
1986
1987 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1988 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1989
1990 radv_destroy_shader_slabs(device);
1991
1992 radv_bo_list_finish(&device->bo_list);
1993 vk_free(&device->alloc, device);
1994 }
1995
1996 VkResult radv_EnumerateInstanceLayerProperties(
1997 uint32_t* pPropertyCount,
1998 VkLayerProperties* pProperties)
1999 {
2000 if (pProperties == NULL) {
2001 *pPropertyCount = 0;
2002 return VK_SUCCESS;
2003 }
2004
2005 /* None supported at this time */
2006 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2007 }
2008
2009 VkResult radv_EnumerateDeviceLayerProperties(
2010 VkPhysicalDevice physicalDevice,
2011 uint32_t* pPropertyCount,
2012 VkLayerProperties* pProperties)
2013 {
2014 if (pProperties == NULL) {
2015 *pPropertyCount = 0;
2016 return VK_SUCCESS;
2017 }
2018
2019 /* None supported at this time */
2020 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2021 }
2022
2023 void radv_GetDeviceQueue2(
2024 VkDevice _device,
2025 const VkDeviceQueueInfo2* pQueueInfo,
2026 VkQueue* pQueue)
2027 {
2028 RADV_FROM_HANDLE(radv_device, device, _device);
2029 struct radv_queue *queue;
2030
2031 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2032 if (pQueueInfo->flags != queue->flags) {
2033 /* From the Vulkan 1.1.70 spec:
2034 *
2035 * "The queue returned by vkGetDeviceQueue2 must have the same
2036 * flags value from this structure as that used at device
2037 * creation time in a VkDeviceQueueCreateInfo instance. If no
2038 * matching flags were specified at device creation time then
2039 * pQueue will return VK_NULL_HANDLE."
2040 */
2041 *pQueue = VK_NULL_HANDLE;
2042 return;
2043 }
2044
2045 *pQueue = radv_queue_to_handle(queue);
2046 }
2047
2048 void radv_GetDeviceQueue(
2049 VkDevice _device,
2050 uint32_t queueFamilyIndex,
2051 uint32_t queueIndex,
2052 VkQueue* pQueue)
2053 {
2054 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2055 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2056 .queueFamilyIndex = queueFamilyIndex,
2057 .queueIndex = queueIndex
2058 };
2059
2060 radv_GetDeviceQueue2(_device, &info, pQueue);
2061 }
2062
2063 static void
2064 fill_geom_tess_rings(struct radv_queue *queue,
2065 uint32_t *map,
2066 bool add_sample_positions,
2067 uint32_t esgs_ring_size,
2068 struct radeon_winsys_bo *esgs_ring_bo,
2069 uint32_t gsvs_ring_size,
2070 struct radeon_winsys_bo *gsvs_ring_bo,
2071 uint32_t tess_factor_ring_size,
2072 uint32_t tess_offchip_ring_offset,
2073 uint32_t tess_offchip_ring_size,
2074 struct radeon_winsys_bo *tess_rings_bo)
2075 {
2076 uint32_t *desc = &map[4];
2077
2078 if (esgs_ring_bo) {
2079 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2080
2081 /* stride 0, num records - size, add tid, swizzle, elsize4,
2082 index stride 64 */
2083 desc[0] = esgs_va;
2084 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2085 S_008F04_STRIDE(0) |
2086 S_008F04_SWIZZLE_ENABLE(true);
2087 desc[2] = esgs_ring_size;
2088 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2089 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2090 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2091 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2092 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2093 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2094 S_008F0C_ELEMENT_SIZE(1) |
2095 S_008F0C_INDEX_STRIDE(3) |
2096 S_008F0C_ADD_TID_ENABLE(true);
2097
2098 /* GS entry for ES->GS ring */
2099 /* stride 0, num records - size, elsize0,
2100 index stride 0 */
2101 desc[4] = esgs_va;
2102 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2103 S_008F04_STRIDE(0) |
2104 S_008F04_SWIZZLE_ENABLE(false);
2105 desc[6] = esgs_ring_size;
2106 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2107 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2108 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2109 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2110 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2111 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2112 S_008F0C_ELEMENT_SIZE(0) |
2113 S_008F0C_INDEX_STRIDE(0) |
2114 S_008F0C_ADD_TID_ENABLE(false);
2115 }
2116
2117 desc += 8;
2118
2119 if (gsvs_ring_bo) {
2120 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2121
2122 /* VS entry for GS->VS ring */
2123 /* stride 0, num records - size, elsize0,
2124 index stride 0 */
2125 desc[0] = gsvs_va;
2126 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2127 S_008F04_STRIDE(0) |
2128 S_008F04_SWIZZLE_ENABLE(false);
2129 desc[2] = gsvs_ring_size;
2130 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2131 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2132 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2133 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2134 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2135 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2136 S_008F0C_ELEMENT_SIZE(0) |
2137 S_008F0C_INDEX_STRIDE(0) |
2138 S_008F0C_ADD_TID_ENABLE(false);
2139
2140 /* stride gsvs_itemsize, num records 64
2141 elsize 4, index stride 16 */
2142 /* shader will patch stride and desc[2] */
2143 desc[4] = gsvs_va;
2144 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2145 S_008F04_STRIDE(0) |
2146 S_008F04_SWIZZLE_ENABLE(true);
2147 desc[6] = 0;
2148 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2152 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2154 S_008F0C_ELEMENT_SIZE(1) |
2155 S_008F0C_INDEX_STRIDE(1) |
2156 S_008F0C_ADD_TID_ENABLE(true);
2157 }
2158
2159 desc += 8;
2160
2161 if (tess_rings_bo) {
2162 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2163 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2164
2165 desc[0] = tess_va;
2166 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2167 S_008F04_STRIDE(0) |
2168 S_008F04_SWIZZLE_ENABLE(false);
2169 desc[2] = tess_factor_ring_size;
2170 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2171 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2172 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2173 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2174 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2176 S_008F0C_ELEMENT_SIZE(0) |
2177 S_008F0C_INDEX_STRIDE(0) |
2178 S_008F0C_ADD_TID_ENABLE(false);
2179
2180 desc[4] = tess_offchip_va;
2181 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2182 S_008F04_STRIDE(0) |
2183 S_008F04_SWIZZLE_ENABLE(false);
2184 desc[6] = tess_offchip_ring_size;
2185 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2186 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2187 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2188 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2189 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2190 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2191 S_008F0C_ELEMENT_SIZE(0) |
2192 S_008F0C_INDEX_STRIDE(0) |
2193 S_008F0C_ADD_TID_ENABLE(false);
2194 }
2195
2196 desc += 8;
2197
2198 if (add_sample_positions) {
2199 /* add sample positions after all rings */
2200 memcpy(desc, queue->device->sample_locations_1x, 8);
2201 desc += 2;
2202 memcpy(desc, queue->device->sample_locations_2x, 16);
2203 desc += 4;
2204 memcpy(desc, queue->device->sample_locations_4x, 32);
2205 desc += 8;
2206 memcpy(desc, queue->device->sample_locations_8x, 64);
2207 }
2208 }
2209
2210 static unsigned
2211 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2212 {
2213 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2214 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2215 device->physical_device->rad_info.family != CHIP_STONEY;
2216 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2217 unsigned max_offchip_buffers;
2218 unsigned offchip_granularity;
2219 unsigned hs_offchip_param;
2220
2221 /*
2222 * Per RadeonSI:
2223 * This must be one less than the maximum number due to a hw limitation.
2224 * Various hardware bugs in SI, CIK, and GFX9 need this.
2225 *
2226 * Per AMDVLK:
2227 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2228 * Gfx7 should limit max_offchip_buffers to 508
2229 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2230 *
2231 * Follow AMDVLK here.
2232 */
2233 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2234 device->physical_device->rad_info.chip_class == CIK ||
2235 device->physical_device->rad_info.chip_class == SI)
2236 --max_offchip_buffers_per_se;
2237
2238 max_offchip_buffers = max_offchip_buffers_per_se *
2239 device->physical_device->rad_info.max_se;
2240
2241 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2242 * around by setting 4K granularity.
2243 */
2244 if (device->tess_offchip_block_dw_size == 4096) {
2245 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2246 offchip_granularity = V_03093C_X_4K_DWORDS;
2247 } else {
2248 assert(device->tess_offchip_block_dw_size == 8192);
2249 offchip_granularity = V_03093C_X_8K_DWORDS;
2250 }
2251
2252 switch (device->physical_device->rad_info.chip_class) {
2253 case SI:
2254 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2255 break;
2256 case CIK:
2257 case VI:
2258 case GFX9:
2259 default:
2260 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2261 break;
2262 }
2263
2264 *max_offchip_buffers_p = max_offchip_buffers;
2265 if (device->physical_device->rad_info.chip_class >= CIK) {
2266 if (device->physical_device->rad_info.chip_class >= VI)
2267 --max_offchip_buffers;
2268 hs_offchip_param =
2269 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2270 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2271 } else {
2272 hs_offchip_param =
2273 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2274 }
2275 return hs_offchip_param;
2276 }
2277
2278 static void
2279 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2280 struct radeon_winsys_bo *esgs_ring_bo,
2281 uint32_t esgs_ring_size,
2282 struct radeon_winsys_bo *gsvs_ring_bo,
2283 uint32_t gsvs_ring_size)
2284 {
2285 if (!esgs_ring_bo && !gsvs_ring_bo)
2286 return;
2287
2288 if (esgs_ring_bo)
2289 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2290
2291 if (gsvs_ring_bo)
2292 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2293
2294 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2295 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2296 radeon_emit(cs, esgs_ring_size >> 8);
2297 radeon_emit(cs, gsvs_ring_size >> 8);
2298 } else {
2299 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2300 radeon_emit(cs, esgs_ring_size >> 8);
2301 radeon_emit(cs, gsvs_ring_size >> 8);
2302 }
2303 }
2304
2305 static void
2306 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2307 unsigned hs_offchip_param, unsigned tf_ring_size,
2308 struct radeon_winsys_bo *tess_rings_bo)
2309 {
2310 uint64_t tf_va;
2311
2312 if (!tess_rings_bo)
2313 return;
2314
2315 tf_va = radv_buffer_get_va(tess_rings_bo);
2316
2317 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2318
2319 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2320 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2321 S_030938_SIZE(tf_ring_size / 4));
2322 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2323 tf_va >> 8);
2324 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2325 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2326 S_030944_BASE_HI(tf_va >> 40));
2327 }
2328 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2329 hs_offchip_param);
2330 } else {
2331 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2332 S_008988_SIZE(tf_ring_size / 4));
2333 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2334 tf_va >> 8);
2335 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2336 hs_offchip_param);
2337 }
2338 }
2339
2340 static void
2341 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2342 struct radeon_winsys_bo *compute_scratch_bo)
2343 {
2344 uint64_t scratch_va;
2345
2346 if (!compute_scratch_bo)
2347 return;
2348
2349 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2350
2351 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2352
2353 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2354 radeon_emit(cs, scratch_va);
2355 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2356 S_008F04_SWIZZLE_ENABLE(1));
2357 }
2358
2359 static void
2360 radv_emit_global_shader_pointers(struct radv_queue *queue,
2361 struct radeon_cmdbuf *cs,
2362 struct radeon_winsys_bo *descriptor_bo)
2363 {
2364 uint64_t va;
2365
2366 if (!descriptor_bo)
2367 return;
2368
2369 va = radv_buffer_get_va(descriptor_bo);
2370
2371 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2372
2373 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2374 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2375 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2376 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2377 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2378
2379 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2380 radv_emit_shader_pointer(queue->device, cs, regs[i],
2381 va, true);
2382 }
2383 } else {
2384 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2385 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2386 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2387 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2388 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2389 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2390
2391 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2392 radv_emit_shader_pointer(queue->device, cs, regs[i],
2393 va, true);
2394 }
2395 }
2396 }
2397
2398 static void
2399 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2400 {
2401 struct radv_device *device = queue->device;
2402
2403 if (device->gfx_init) {
2404 uint64_t va = radv_buffer_get_va(device->gfx_init);
2405
2406 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2407 radeon_emit(cs, va);
2408 radeon_emit(cs, va >> 32);
2409 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2410
2411 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2412 } else {
2413 struct radv_physical_device *physical_device = device->physical_device;
2414 si_emit_graphics(physical_device, cs);
2415 }
2416 }
2417
2418 static void
2419 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2420 {
2421 struct radv_physical_device *physical_device = queue->device->physical_device;
2422 si_emit_compute(physical_device, cs);
2423 }
2424
2425 static VkResult
2426 radv_get_preamble_cs(struct radv_queue *queue,
2427 uint32_t scratch_size,
2428 uint32_t compute_scratch_size,
2429 uint32_t esgs_ring_size,
2430 uint32_t gsvs_ring_size,
2431 bool needs_tess_rings,
2432 bool needs_sample_positions,
2433 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2434 struct radeon_cmdbuf **initial_preamble_cs,
2435 struct radeon_cmdbuf **continue_preamble_cs)
2436 {
2437 struct radeon_winsys_bo *scratch_bo = NULL;
2438 struct radeon_winsys_bo *descriptor_bo = NULL;
2439 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2440 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2441 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2442 struct radeon_winsys_bo *tess_rings_bo = NULL;
2443 struct radeon_cmdbuf *dest_cs[3] = {0};
2444 bool add_tess_rings = false, add_sample_positions = false;
2445 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2446 unsigned max_offchip_buffers;
2447 unsigned hs_offchip_param = 0;
2448 unsigned tess_offchip_ring_offset;
2449 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2450 if (!queue->has_tess_rings) {
2451 if (needs_tess_rings)
2452 add_tess_rings = true;
2453 }
2454 if (!queue->has_sample_positions) {
2455 if (needs_sample_positions)
2456 add_sample_positions = true;
2457 }
2458 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2459 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2460 &max_offchip_buffers);
2461 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2462 tess_offchip_ring_size = max_offchip_buffers *
2463 queue->device->tess_offchip_block_dw_size * 4;
2464
2465 if (scratch_size <= queue->scratch_size &&
2466 compute_scratch_size <= queue->compute_scratch_size &&
2467 esgs_ring_size <= queue->esgs_ring_size &&
2468 gsvs_ring_size <= queue->gsvs_ring_size &&
2469 !add_tess_rings && !add_sample_positions &&
2470 queue->initial_preamble_cs) {
2471 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2472 *initial_preamble_cs = queue->initial_preamble_cs;
2473 *continue_preamble_cs = queue->continue_preamble_cs;
2474 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2475 *continue_preamble_cs = NULL;
2476 return VK_SUCCESS;
2477 }
2478
2479 if (scratch_size > queue->scratch_size) {
2480 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2481 scratch_size,
2482 4096,
2483 RADEON_DOMAIN_VRAM,
2484 ring_bo_flags,
2485 RADV_BO_PRIORITY_SCRATCH);
2486 if (!scratch_bo)
2487 goto fail;
2488 } else
2489 scratch_bo = queue->scratch_bo;
2490
2491 if (compute_scratch_size > queue->compute_scratch_size) {
2492 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2493 compute_scratch_size,
2494 4096,
2495 RADEON_DOMAIN_VRAM,
2496 ring_bo_flags,
2497 RADV_BO_PRIORITY_SCRATCH);
2498 if (!compute_scratch_bo)
2499 goto fail;
2500
2501 } else
2502 compute_scratch_bo = queue->compute_scratch_bo;
2503
2504 if (esgs_ring_size > queue->esgs_ring_size) {
2505 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2506 esgs_ring_size,
2507 4096,
2508 RADEON_DOMAIN_VRAM,
2509 ring_bo_flags,
2510 RADV_BO_PRIORITY_SCRATCH);
2511 if (!esgs_ring_bo)
2512 goto fail;
2513 } else {
2514 esgs_ring_bo = queue->esgs_ring_bo;
2515 esgs_ring_size = queue->esgs_ring_size;
2516 }
2517
2518 if (gsvs_ring_size > queue->gsvs_ring_size) {
2519 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2520 gsvs_ring_size,
2521 4096,
2522 RADEON_DOMAIN_VRAM,
2523 ring_bo_flags,
2524 RADV_BO_PRIORITY_SCRATCH);
2525 if (!gsvs_ring_bo)
2526 goto fail;
2527 } else {
2528 gsvs_ring_bo = queue->gsvs_ring_bo;
2529 gsvs_ring_size = queue->gsvs_ring_size;
2530 }
2531
2532 if (add_tess_rings) {
2533 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2534 tess_offchip_ring_offset + tess_offchip_ring_size,
2535 256,
2536 RADEON_DOMAIN_VRAM,
2537 ring_bo_flags,
2538 RADV_BO_PRIORITY_SCRATCH);
2539 if (!tess_rings_bo)
2540 goto fail;
2541 } else {
2542 tess_rings_bo = queue->tess_rings_bo;
2543 }
2544
2545 if (scratch_bo != queue->scratch_bo ||
2546 esgs_ring_bo != queue->esgs_ring_bo ||
2547 gsvs_ring_bo != queue->gsvs_ring_bo ||
2548 tess_rings_bo != queue->tess_rings_bo ||
2549 add_sample_positions) {
2550 uint32_t size = 0;
2551 if (gsvs_ring_bo || esgs_ring_bo ||
2552 tess_rings_bo || add_sample_positions) {
2553 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2554 if (add_sample_positions)
2555 size += 128; /* 64+32+16+8 = 120 bytes */
2556 }
2557 else if (scratch_bo)
2558 size = 8; /* 2 dword */
2559
2560 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2561 size,
2562 4096,
2563 RADEON_DOMAIN_VRAM,
2564 RADEON_FLAG_CPU_ACCESS |
2565 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2566 RADEON_FLAG_READ_ONLY,
2567 RADV_BO_PRIORITY_DESCRIPTOR);
2568 if (!descriptor_bo)
2569 goto fail;
2570 } else
2571 descriptor_bo = queue->descriptor_bo;
2572
2573 if (descriptor_bo != queue->descriptor_bo) {
2574 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2575
2576 if (scratch_bo) {
2577 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2578 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2579 S_008F04_SWIZZLE_ENABLE(1);
2580 map[0] = scratch_va;
2581 map[1] = rsrc1;
2582 }
2583
2584 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2585 fill_geom_tess_rings(queue, map, add_sample_positions,
2586 esgs_ring_size, esgs_ring_bo,
2587 gsvs_ring_size, gsvs_ring_bo,
2588 tess_factor_ring_size,
2589 tess_offchip_ring_offset,
2590 tess_offchip_ring_size,
2591 tess_rings_bo);
2592
2593 queue->device->ws->buffer_unmap(descriptor_bo);
2594 }
2595
2596 for(int i = 0; i < 3; ++i) {
2597 struct radeon_cmdbuf *cs = NULL;
2598 cs = queue->device->ws->cs_create(queue->device->ws,
2599 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2600 if (!cs)
2601 goto fail;
2602
2603 dest_cs[i] = cs;
2604
2605 if (scratch_bo)
2606 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2607
2608 /* Emit initial configuration. */
2609 switch (queue->queue_family_index) {
2610 case RADV_QUEUE_GENERAL:
2611 radv_init_graphics_state(cs, queue);
2612 break;
2613 case RADV_QUEUE_COMPUTE:
2614 radv_init_compute_state(cs, queue);
2615 break;
2616 case RADV_QUEUE_TRANSFER:
2617 break;
2618 }
2619
2620 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2621 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2622 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2623 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2624 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2625 }
2626
2627 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2628 gsvs_ring_bo, gsvs_ring_size);
2629 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2630 tess_factor_ring_size, tess_rings_bo);
2631 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2632 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2633
2634 if (i == 0) {
2635 si_cs_emit_cache_flush(cs,
2636 queue->device->physical_device->rad_info.chip_class,
2637 NULL, 0,
2638 queue->queue_family_index == RING_COMPUTE &&
2639 queue->device->physical_device->rad_info.chip_class >= CIK,
2640 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2641 RADV_CMD_FLAG_INV_ICACHE |
2642 RADV_CMD_FLAG_INV_SMEM_L1 |
2643 RADV_CMD_FLAG_INV_VMEM_L1 |
2644 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2645 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2646 } else if (i == 1) {
2647 si_cs_emit_cache_flush(cs,
2648 queue->device->physical_device->rad_info.chip_class,
2649 NULL, 0,
2650 queue->queue_family_index == RING_COMPUTE &&
2651 queue->device->physical_device->rad_info.chip_class >= CIK,
2652 RADV_CMD_FLAG_INV_ICACHE |
2653 RADV_CMD_FLAG_INV_SMEM_L1 |
2654 RADV_CMD_FLAG_INV_VMEM_L1 |
2655 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2656 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2657 }
2658
2659 if (!queue->device->ws->cs_finalize(cs))
2660 goto fail;
2661 }
2662
2663 if (queue->initial_full_flush_preamble_cs)
2664 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2665
2666 if (queue->initial_preamble_cs)
2667 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2668
2669 if (queue->continue_preamble_cs)
2670 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2671
2672 queue->initial_full_flush_preamble_cs = dest_cs[0];
2673 queue->initial_preamble_cs = dest_cs[1];
2674 queue->continue_preamble_cs = dest_cs[2];
2675
2676 if (scratch_bo != queue->scratch_bo) {
2677 if (queue->scratch_bo)
2678 queue->device->ws->buffer_destroy(queue->scratch_bo);
2679 queue->scratch_bo = scratch_bo;
2680 queue->scratch_size = scratch_size;
2681 }
2682
2683 if (compute_scratch_bo != queue->compute_scratch_bo) {
2684 if (queue->compute_scratch_bo)
2685 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2686 queue->compute_scratch_bo = compute_scratch_bo;
2687 queue->compute_scratch_size = compute_scratch_size;
2688 }
2689
2690 if (esgs_ring_bo != queue->esgs_ring_bo) {
2691 if (queue->esgs_ring_bo)
2692 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2693 queue->esgs_ring_bo = esgs_ring_bo;
2694 queue->esgs_ring_size = esgs_ring_size;
2695 }
2696
2697 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2698 if (queue->gsvs_ring_bo)
2699 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2700 queue->gsvs_ring_bo = gsvs_ring_bo;
2701 queue->gsvs_ring_size = gsvs_ring_size;
2702 }
2703
2704 if (tess_rings_bo != queue->tess_rings_bo) {
2705 queue->tess_rings_bo = tess_rings_bo;
2706 queue->has_tess_rings = true;
2707 }
2708
2709 if (descriptor_bo != queue->descriptor_bo) {
2710 if (queue->descriptor_bo)
2711 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2712
2713 queue->descriptor_bo = descriptor_bo;
2714 }
2715
2716 if (add_sample_positions)
2717 queue->has_sample_positions = true;
2718
2719 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2720 *initial_preamble_cs = queue->initial_preamble_cs;
2721 *continue_preamble_cs = queue->continue_preamble_cs;
2722 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2723 *continue_preamble_cs = NULL;
2724 return VK_SUCCESS;
2725 fail:
2726 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2727 if (dest_cs[i])
2728 queue->device->ws->cs_destroy(dest_cs[i]);
2729 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2730 queue->device->ws->buffer_destroy(descriptor_bo);
2731 if (scratch_bo && scratch_bo != queue->scratch_bo)
2732 queue->device->ws->buffer_destroy(scratch_bo);
2733 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2734 queue->device->ws->buffer_destroy(compute_scratch_bo);
2735 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2736 queue->device->ws->buffer_destroy(esgs_ring_bo);
2737 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2738 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2739 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2740 queue->device->ws->buffer_destroy(tess_rings_bo);
2741 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2742 }
2743
2744 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2745 struct radv_winsys_sem_counts *counts,
2746 int num_sems,
2747 const VkSemaphore *sems,
2748 VkFence _fence,
2749 bool reset_temp)
2750 {
2751 int syncobj_idx = 0, sem_idx = 0;
2752
2753 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2754 return VK_SUCCESS;
2755
2756 for (uint32_t i = 0; i < num_sems; i++) {
2757 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2758
2759 if (sem->temp_syncobj || sem->syncobj)
2760 counts->syncobj_count++;
2761 else
2762 counts->sem_count++;
2763 }
2764
2765 if (_fence != VK_NULL_HANDLE) {
2766 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2767 if (fence->temp_syncobj || fence->syncobj)
2768 counts->syncobj_count++;
2769 }
2770
2771 if (counts->syncobj_count) {
2772 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2773 if (!counts->syncobj)
2774 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2775 }
2776
2777 if (counts->sem_count) {
2778 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2779 if (!counts->sem) {
2780 free(counts->syncobj);
2781 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2782 }
2783 }
2784
2785 for (uint32_t i = 0; i < num_sems; i++) {
2786 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2787
2788 if (sem->temp_syncobj) {
2789 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2790 }
2791 else if (sem->syncobj)
2792 counts->syncobj[syncobj_idx++] = sem->syncobj;
2793 else {
2794 assert(sem->sem);
2795 counts->sem[sem_idx++] = sem->sem;
2796 }
2797 }
2798
2799 if (_fence != VK_NULL_HANDLE) {
2800 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2801 if (fence->temp_syncobj)
2802 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2803 else if (fence->syncobj)
2804 counts->syncobj[syncobj_idx++] = fence->syncobj;
2805 }
2806
2807 return VK_SUCCESS;
2808 }
2809
2810 static void
2811 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2812 {
2813 free(sem_info->wait.syncobj);
2814 free(sem_info->wait.sem);
2815 free(sem_info->signal.syncobj);
2816 free(sem_info->signal.sem);
2817 }
2818
2819
2820 static void radv_free_temp_syncobjs(struct radv_device *device,
2821 int num_sems,
2822 const VkSemaphore *sems)
2823 {
2824 for (uint32_t i = 0; i < num_sems; i++) {
2825 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2826
2827 if (sem->temp_syncobj) {
2828 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2829 sem->temp_syncobj = 0;
2830 }
2831 }
2832 }
2833
2834 static VkResult
2835 radv_alloc_sem_info(struct radv_instance *instance,
2836 struct radv_winsys_sem_info *sem_info,
2837 int num_wait_sems,
2838 const VkSemaphore *wait_sems,
2839 int num_signal_sems,
2840 const VkSemaphore *signal_sems,
2841 VkFence fence)
2842 {
2843 VkResult ret;
2844 memset(sem_info, 0, sizeof(*sem_info));
2845
2846 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2847 if (ret)
2848 return ret;
2849 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2850 if (ret)
2851 radv_free_sem_info(sem_info);
2852
2853 /* caller can override these */
2854 sem_info->cs_emit_wait = true;
2855 sem_info->cs_emit_signal = true;
2856 return ret;
2857 }
2858
2859 /* Signals fence as soon as all the work currently put on queue is done. */
2860 static VkResult radv_signal_fence(struct radv_queue *queue,
2861 struct radv_fence *fence)
2862 {
2863 int ret;
2864 VkResult result;
2865 struct radv_winsys_sem_info sem_info;
2866
2867 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2868 radv_fence_to_handle(fence));
2869 if (result != VK_SUCCESS)
2870 return result;
2871
2872 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2873 &queue->device->empty_cs[queue->queue_family_index],
2874 1, NULL, NULL, &sem_info, NULL,
2875 false, fence->fence);
2876 radv_free_sem_info(&sem_info);
2877
2878 if (ret)
2879 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2880
2881 return VK_SUCCESS;
2882 }
2883
2884 VkResult radv_QueueSubmit(
2885 VkQueue _queue,
2886 uint32_t submitCount,
2887 const VkSubmitInfo* pSubmits,
2888 VkFence _fence)
2889 {
2890 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2891 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2892 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2893 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2894 int ret;
2895 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2896 uint32_t scratch_size = 0;
2897 uint32_t compute_scratch_size = 0;
2898 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2899 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2900 VkResult result;
2901 bool fence_emitted = false;
2902 bool tess_rings_needed = false;
2903 bool sample_positions_needed = false;
2904
2905 /* Do this first so failing to allocate scratch buffers can't result in
2906 * partially executed submissions. */
2907 for (uint32_t i = 0; i < submitCount; i++) {
2908 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2910 pSubmits[i].pCommandBuffers[j]);
2911
2912 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2913 compute_scratch_size = MAX2(compute_scratch_size,
2914 cmd_buffer->compute_scratch_size_needed);
2915 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2916 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2917 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2918 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2919 }
2920 }
2921
2922 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2923 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2924 sample_positions_needed, &initial_flush_preamble_cs,
2925 &initial_preamble_cs, &continue_preamble_cs);
2926 if (result != VK_SUCCESS)
2927 return result;
2928
2929 for (uint32_t i = 0; i < submitCount; i++) {
2930 struct radeon_cmdbuf **cs_array;
2931 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2932 bool can_patch = true;
2933 uint32_t advance;
2934 struct radv_winsys_sem_info sem_info;
2935
2936 result = radv_alloc_sem_info(queue->device->instance,
2937 &sem_info,
2938 pSubmits[i].waitSemaphoreCount,
2939 pSubmits[i].pWaitSemaphores,
2940 pSubmits[i].signalSemaphoreCount,
2941 pSubmits[i].pSignalSemaphores,
2942 _fence);
2943 if (result != VK_SUCCESS)
2944 return result;
2945
2946 if (!pSubmits[i].commandBufferCount) {
2947 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2948 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2949 &queue->device->empty_cs[queue->queue_family_index],
2950 1, NULL, NULL,
2951 &sem_info, NULL,
2952 false, base_fence);
2953 if (ret) {
2954 radv_loge("failed to submit CS %d\n", i);
2955 abort();
2956 }
2957 fence_emitted = true;
2958 }
2959 radv_free_sem_info(&sem_info);
2960 continue;
2961 }
2962
2963 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2964 (pSubmits[i].commandBufferCount));
2965
2966 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2967 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2968 pSubmits[i].pCommandBuffers[j]);
2969 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2970
2971 cs_array[j] = cmd_buffer->cs;
2972 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2973 can_patch = false;
2974
2975 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2976 }
2977
2978 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2979 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2980 const struct radv_winsys_bo_list *bo_list = NULL;
2981
2982 advance = MIN2(max_cs_submission,
2983 pSubmits[i].commandBufferCount - j);
2984
2985 if (queue->device->trace_bo)
2986 *queue->device->trace_id_ptr = 0;
2987
2988 sem_info.cs_emit_wait = j == 0;
2989 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2990
2991 if (unlikely(queue->device->use_global_bo_list)) {
2992 pthread_mutex_lock(&queue->device->bo_list.mutex);
2993 bo_list = &queue->device->bo_list.list;
2994 }
2995
2996 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2997 advance, initial_preamble, continue_preamble_cs,
2998 &sem_info, bo_list,
2999 can_patch, base_fence);
3000
3001 if (unlikely(queue->device->use_global_bo_list))
3002 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3003
3004 if (ret) {
3005 radv_loge("failed to submit CS %d\n", i);
3006 abort();
3007 }
3008 fence_emitted = true;
3009 if (queue->device->trace_bo) {
3010 radv_check_gpu_hangs(queue, cs_array[j]);
3011 }
3012 }
3013
3014 radv_free_temp_syncobjs(queue->device,
3015 pSubmits[i].waitSemaphoreCount,
3016 pSubmits[i].pWaitSemaphores);
3017 radv_free_sem_info(&sem_info);
3018 free(cs_array);
3019 }
3020
3021 if (fence) {
3022 if (!fence_emitted) {
3023 result = radv_signal_fence(queue, fence);
3024 if (result != VK_SUCCESS)
3025 return result;
3026 }
3027 fence->submitted = true;
3028 }
3029
3030 return VK_SUCCESS;
3031 }
3032
3033 VkResult radv_QueueWaitIdle(
3034 VkQueue _queue)
3035 {
3036 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3037
3038 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3039 radv_queue_family_to_ring(queue->queue_family_index),
3040 queue->queue_idx);
3041 return VK_SUCCESS;
3042 }
3043
3044 VkResult radv_DeviceWaitIdle(
3045 VkDevice _device)
3046 {
3047 RADV_FROM_HANDLE(radv_device, device, _device);
3048
3049 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3050 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3051 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3052 }
3053 }
3054 return VK_SUCCESS;
3055 }
3056
3057 VkResult radv_EnumerateInstanceExtensionProperties(
3058 const char* pLayerName,
3059 uint32_t* pPropertyCount,
3060 VkExtensionProperties* pProperties)
3061 {
3062 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3063
3064 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3065 if (radv_supported_instance_extensions.extensions[i]) {
3066 vk_outarray_append(&out, prop) {
3067 *prop = radv_instance_extensions[i];
3068 }
3069 }
3070 }
3071
3072 return vk_outarray_status(&out);
3073 }
3074
3075 VkResult radv_EnumerateDeviceExtensionProperties(
3076 VkPhysicalDevice physicalDevice,
3077 const char* pLayerName,
3078 uint32_t* pPropertyCount,
3079 VkExtensionProperties* pProperties)
3080 {
3081 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3082 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3083
3084 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3085 if (device->supported_extensions.extensions[i]) {
3086 vk_outarray_append(&out, prop) {
3087 *prop = radv_device_extensions[i];
3088 }
3089 }
3090 }
3091
3092 return vk_outarray_status(&out);
3093 }
3094
3095 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3096 VkInstance _instance,
3097 const char* pName)
3098 {
3099 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3100
3101 return radv_lookup_entrypoint_checked(pName,
3102 instance ? instance->apiVersion : 0,
3103 instance ? &instance->enabled_extensions : NULL,
3104 NULL);
3105 }
3106
3107 /* The loader wants us to expose a second GetInstanceProcAddr function
3108 * to work around certain LD_PRELOAD issues seen in apps.
3109 */
3110 PUBLIC
3111 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3112 VkInstance instance,
3113 const char* pName);
3114
3115 PUBLIC
3116 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3117 VkInstance instance,
3118 const char* pName)
3119 {
3120 return radv_GetInstanceProcAddr(instance, pName);
3121 }
3122
3123 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3124 VkDevice _device,
3125 const char* pName)
3126 {
3127 RADV_FROM_HANDLE(radv_device, device, _device);
3128
3129 return radv_lookup_entrypoint_checked(pName,
3130 device->instance->apiVersion,
3131 &device->instance->enabled_extensions,
3132 &device->enabled_extensions);
3133 }
3134
3135 bool radv_get_memory_fd(struct radv_device *device,
3136 struct radv_device_memory *memory,
3137 int *pFD)
3138 {
3139 struct radeon_bo_metadata metadata;
3140
3141 if (memory->image) {
3142 radv_init_metadata(device, memory->image, &metadata);
3143 device->ws->buffer_set_metadata(memory->bo, &metadata);
3144 }
3145
3146 return device->ws->buffer_get_fd(device->ws, memory->bo,
3147 pFD);
3148 }
3149
3150 static VkResult radv_alloc_memory(struct radv_device *device,
3151 const VkMemoryAllocateInfo* pAllocateInfo,
3152 const VkAllocationCallbacks* pAllocator,
3153 VkDeviceMemory* pMem)
3154 {
3155 struct radv_device_memory *mem;
3156 VkResult result;
3157 enum radeon_bo_domain domain;
3158 uint32_t flags = 0;
3159 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3160
3161 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3162
3163 if (pAllocateInfo->allocationSize == 0) {
3164 /* Apparently, this is allowed */
3165 *pMem = VK_NULL_HANDLE;
3166 return VK_SUCCESS;
3167 }
3168
3169 const VkImportMemoryFdInfoKHR *import_info =
3170 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3171 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3172 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3173 const VkExportMemoryAllocateInfo *export_info =
3174 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3175 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3176 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3177
3178 const struct wsi_memory_allocate_info *wsi_info =
3179 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3180
3181 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3182 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3183 if (mem == NULL)
3184 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3185
3186 if (wsi_info && wsi_info->implicit_sync)
3187 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3188
3189 if (dedicate_info) {
3190 mem->image = radv_image_from_handle(dedicate_info->image);
3191 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3192 } else {
3193 mem->image = NULL;
3194 mem->buffer = NULL;
3195 }
3196
3197 float priority_float = 0.5;
3198 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3199 vk_find_struct_const(pAllocateInfo->pNext,
3200 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3201 if (priority_ext)
3202 priority_float = priority_ext->priority;
3203
3204 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3205 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3206
3207 mem->user_ptr = NULL;
3208
3209 if (import_info) {
3210 assert(import_info->handleType ==
3211 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3212 import_info->handleType ==
3213 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3214 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3215 priority, NULL, NULL);
3216 if (!mem->bo) {
3217 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3218 goto fail;
3219 } else {
3220 close(import_info->fd);
3221 }
3222 } else if (host_ptr_info) {
3223 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3224 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3225 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3226 pAllocateInfo->allocationSize,
3227 priority);
3228 if (!mem->bo) {
3229 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3230 goto fail;
3231 } else {
3232 mem->user_ptr = host_ptr_info->pHostPointer;
3233 }
3234 } else {
3235 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3236 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3237 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3238 domain = RADEON_DOMAIN_GTT;
3239 else
3240 domain = RADEON_DOMAIN_VRAM;
3241
3242 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3243 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3244 else
3245 flags |= RADEON_FLAG_CPU_ACCESS;
3246
3247 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3248 flags |= RADEON_FLAG_GTT_WC;
3249
3250 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3251 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3252 if (device->use_global_bo_list) {
3253 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3254 }
3255 }
3256
3257 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3258 domain, flags, priority);
3259
3260 if (!mem->bo) {
3261 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3262 goto fail;
3263 }
3264 mem->type_index = mem_type_index;
3265 }
3266
3267 result = radv_bo_list_add(device, mem->bo);
3268 if (result != VK_SUCCESS)
3269 goto fail_bo;
3270
3271 *pMem = radv_device_memory_to_handle(mem);
3272
3273 return VK_SUCCESS;
3274
3275 fail_bo:
3276 device->ws->buffer_destroy(mem->bo);
3277 fail:
3278 vk_free2(&device->alloc, pAllocator, mem);
3279
3280 return result;
3281 }
3282
3283 VkResult radv_AllocateMemory(
3284 VkDevice _device,
3285 const VkMemoryAllocateInfo* pAllocateInfo,
3286 const VkAllocationCallbacks* pAllocator,
3287 VkDeviceMemory* pMem)
3288 {
3289 RADV_FROM_HANDLE(radv_device, device, _device);
3290 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3291 }
3292
3293 void radv_FreeMemory(
3294 VkDevice _device,
3295 VkDeviceMemory _mem,
3296 const VkAllocationCallbacks* pAllocator)
3297 {
3298 RADV_FROM_HANDLE(radv_device, device, _device);
3299 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3300
3301 if (mem == NULL)
3302 return;
3303
3304 radv_bo_list_remove(device, mem->bo);
3305 device->ws->buffer_destroy(mem->bo);
3306 mem->bo = NULL;
3307
3308 vk_free2(&device->alloc, pAllocator, mem);
3309 }
3310
3311 VkResult radv_MapMemory(
3312 VkDevice _device,
3313 VkDeviceMemory _memory,
3314 VkDeviceSize offset,
3315 VkDeviceSize size,
3316 VkMemoryMapFlags flags,
3317 void** ppData)
3318 {
3319 RADV_FROM_HANDLE(radv_device, device, _device);
3320 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3321
3322 if (mem == NULL) {
3323 *ppData = NULL;
3324 return VK_SUCCESS;
3325 }
3326
3327 if (mem->user_ptr)
3328 *ppData = mem->user_ptr;
3329 else
3330 *ppData = device->ws->buffer_map(mem->bo);
3331
3332 if (*ppData) {
3333 *ppData += offset;
3334 return VK_SUCCESS;
3335 }
3336
3337 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3338 }
3339
3340 void radv_UnmapMemory(
3341 VkDevice _device,
3342 VkDeviceMemory _memory)
3343 {
3344 RADV_FROM_HANDLE(radv_device, device, _device);
3345 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3346
3347 if (mem == NULL)
3348 return;
3349
3350 if (mem->user_ptr == NULL)
3351 device->ws->buffer_unmap(mem->bo);
3352 }
3353
3354 VkResult radv_FlushMappedMemoryRanges(
3355 VkDevice _device,
3356 uint32_t memoryRangeCount,
3357 const VkMappedMemoryRange* pMemoryRanges)
3358 {
3359 return VK_SUCCESS;
3360 }
3361
3362 VkResult radv_InvalidateMappedMemoryRanges(
3363 VkDevice _device,
3364 uint32_t memoryRangeCount,
3365 const VkMappedMemoryRange* pMemoryRanges)
3366 {
3367 return VK_SUCCESS;
3368 }
3369
3370 void radv_GetBufferMemoryRequirements(
3371 VkDevice _device,
3372 VkBuffer _buffer,
3373 VkMemoryRequirements* pMemoryRequirements)
3374 {
3375 RADV_FROM_HANDLE(radv_device, device, _device);
3376 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3377
3378 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3379
3380 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3381 pMemoryRequirements->alignment = 4096;
3382 else
3383 pMemoryRequirements->alignment = 16;
3384
3385 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3386 }
3387
3388 void radv_GetBufferMemoryRequirements2(
3389 VkDevice device,
3390 const VkBufferMemoryRequirementsInfo2 *pInfo,
3391 VkMemoryRequirements2 *pMemoryRequirements)
3392 {
3393 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3394 &pMemoryRequirements->memoryRequirements);
3395 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3396 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3397 switch (ext->sType) {
3398 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3399 VkMemoryDedicatedRequirements *req =
3400 (VkMemoryDedicatedRequirements *) ext;
3401 req->requiresDedicatedAllocation = buffer->shareable;
3402 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3403 break;
3404 }
3405 default:
3406 break;
3407 }
3408 }
3409 }
3410
3411 void radv_GetImageMemoryRequirements(
3412 VkDevice _device,
3413 VkImage _image,
3414 VkMemoryRequirements* pMemoryRequirements)
3415 {
3416 RADV_FROM_HANDLE(radv_device, device, _device);
3417 RADV_FROM_HANDLE(radv_image, image, _image);
3418
3419 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3420
3421 pMemoryRequirements->size = image->size;
3422 pMemoryRequirements->alignment = image->alignment;
3423 }
3424
3425 void radv_GetImageMemoryRequirements2(
3426 VkDevice device,
3427 const VkImageMemoryRequirementsInfo2 *pInfo,
3428 VkMemoryRequirements2 *pMemoryRequirements)
3429 {
3430 radv_GetImageMemoryRequirements(device, pInfo->image,
3431 &pMemoryRequirements->memoryRequirements);
3432
3433 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3434
3435 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3436 switch (ext->sType) {
3437 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3438 VkMemoryDedicatedRequirements *req =
3439 (VkMemoryDedicatedRequirements *) ext;
3440 req->requiresDedicatedAllocation = image->shareable;
3441 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3442 break;
3443 }
3444 default:
3445 break;
3446 }
3447 }
3448 }
3449
3450 void radv_GetImageSparseMemoryRequirements(
3451 VkDevice device,
3452 VkImage image,
3453 uint32_t* pSparseMemoryRequirementCount,
3454 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3455 {
3456 stub();
3457 }
3458
3459 void radv_GetImageSparseMemoryRequirements2(
3460 VkDevice device,
3461 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3462 uint32_t* pSparseMemoryRequirementCount,
3463 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3464 {
3465 stub();
3466 }
3467
3468 void radv_GetDeviceMemoryCommitment(
3469 VkDevice device,
3470 VkDeviceMemory memory,
3471 VkDeviceSize* pCommittedMemoryInBytes)
3472 {
3473 *pCommittedMemoryInBytes = 0;
3474 }
3475
3476 VkResult radv_BindBufferMemory2(VkDevice device,
3477 uint32_t bindInfoCount,
3478 const VkBindBufferMemoryInfo *pBindInfos)
3479 {
3480 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3481 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3482 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3483
3484 if (mem) {
3485 buffer->bo = mem->bo;
3486 buffer->offset = pBindInfos[i].memoryOffset;
3487 } else {
3488 buffer->bo = NULL;
3489 }
3490 }
3491 return VK_SUCCESS;
3492 }
3493
3494 VkResult radv_BindBufferMemory(
3495 VkDevice device,
3496 VkBuffer buffer,
3497 VkDeviceMemory memory,
3498 VkDeviceSize memoryOffset)
3499 {
3500 const VkBindBufferMemoryInfo info = {
3501 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3502 .buffer = buffer,
3503 .memory = memory,
3504 .memoryOffset = memoryOffset
3505 };
3506
3507 return radv_BindBufferMemory2(device, 1, &info);
3508 }
3509
3510 VkResult radv_BindImageMemory2(VkDevice device,
3511 uint32_t bindInfoCount,
3512 const VkBindImageMemoryInfo *pBindInfos)
3513 {
3514 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3515 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3516 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3517
3518 if (mem) {
3519 image->bo = mem->bo;
3520 image->offset = pBindInfos[i].memoryOffset;
3521 } else {
3522 image->bo = NULL;
3523 image->offset = 0;
3524 }
3525 }
3526 return VK_SUCCESS;
3527 }
3528
3529
3530 VkResult radv_BindImageMemory(
3531 VkDevice device,
3532 VkImage image,
3533 VkDeviceMemory memory,
3534 VkDeviceSize memoryOffset)
3535 {
3536 const VkBindImageMemoryInfo info = {
3537 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3538 .image = image,
3539 .memory = memory,
3540 .memoryOffset = memoryOffset
3541 };
3542
3543 return radv_BindImageMemory2(device, 1, &info);
3544 }
3545
3546
3547 static void
3548 radv_sparse_buffer_bind_memory(struct radv_device *device,
3549 const VkSparseBufferMemoryBindInfo *bind)
3550 {
3551 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3552
3553 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3554 struct radv_device_memory *mem = NULL;
3555
3556 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3557 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3558
3559 device->ws->buffer_virtual_bind(buffer->bo,
3560 bind->pBinds[i].resourceOffset,
3561 bind->pBinds[i].size,
3562 mem ? mem->bo : NULL,
3563 bind->pBinds[i].memoryOffset);
3564 }
3565 }
3566
3567 static void
3568 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3569 const VkSparseImageOpaqueMemoryBindInfo *bind)
3570 {
3571 RADV_FROM_HANDLE(radv_image, image, bind->image);
3572
3573 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3574 struct radv_device_memory *mem = NULL;
3575
3576 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3577 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3578
3579 device->ws->buffer_virtual_bind(image->bo,
3580 bind->pBinds[i].resourceOffset,
3581 bind->pBinds[i].size,
3582 mem ? mem->bo : NULL,
3583 bind->pBinds[i].memoryOffset);
3584 }
3585 }
3586
3587 VkResult radv_QueueBindSparse(
3588 VkQueue _queue,
3589 uint32_t bindInfoCount,
3590 const VkBindSparseInfo* pBindInfo,
3591 VkFence _fence)
3592 {
3593 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3594 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3595 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3596 bool fence_emitted = false;
3597 VkResult result;
3598 int ret;
3599
3600 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3601 struct radv_winsys_sem_info sem_info;
3602 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3603 radv_sparse_buffer_bind_memory(queue->device,
3604 pBindInfo[i].pBufferBinds + j);
3605 }
3606
3607 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3608 radv_sparse_image_opaque_bind_memory(queue->device,
3609 pBindInfo[i].pImageOpaqueBinds + j);
3610 }
3611
3612 VkResult result;
3613 result = radv_alloc_sem_info(queue->device->instance,
3614 &sem_info,
3615 pBindInfo[i].waitSemaphoreCount,
3616 pBindInfo[i].pWaitSemaphores,
3617 pBindInfo[i].signalSemaphoreCount,
3618 pBindInfo[i].pSignalSemaphores,
3619 _fence);
3620 if (result != VK_SUCCESS)
3621 return result;
3622
3623 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3624 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3625 &queue->device->empty_cs[queue->queue_family_index],
3626 1, NULL, NULL,
3627 &sem_info, NULL,
3628 false, base_fence);
3629 if (ret) {
3630 radv_loge("failed to submit CS %d\n", i);
3631 abort();
3632 }
3633
3634 fence_emitted = true;
3635 if (fence)
3636 fence->submitted = true;
3637 }
3638
3639 radv_free_sem_info(&sem_info);
3640
3641 }
3642
3643 if (fence) {
3644 if (!fence_emitted) {
3645 result = radv_signal_fence(queue, fence);
3646 if (result != VK_SUCCESS)
3647 return result;
3648 }
3649 fence->submitted = true;
3650 }
3651
3652 return VK_SUCCESS;
3653 }
3654
3655 VkResult radv_CreateFence(
3656 VkDevice _device,
3657 const VkFenceCreateInfo* pCreateInfo,
3658 const VkAllocationCallbacks* pAllocator,
3659 VkFence* pFence)
3660 {
3661 RADV_FROM_HANDLE(radv_device, device, _device);
3662 const VkExportFenceCreateInfo *export =
3663 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3664 VkExternalFenceHandleTypeFlags handleTypes =
3665 export ? export->handleTypes : 0;
3666
3667 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3668 sizeof(*fence), 8,
3669 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3670
3671 if (!fence)
3672 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3673
3674 fence->fence_wsi = NULL;
3675 fence->submitted = false;
3676 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3677 fence->temp_syncobj = 0;
3678 if (device->always_use_syncobj || handleTypes) {
3679 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3680 if (ret) {
3681 vk_free2(&device->alloc, pAllocator, fence);
3682 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3683 }
3684 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3685 device->ws->signal_syncobj(device->ws, fence->syncobj);
3686 }
3687 fence->fence = NULL;
3688 } else {
3689 fence->fence = device->ws->create_fence();
3690 if (!fence->fence) {
3691 vk_free2(&device->alloc, pAllocator, fence);
3692 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3693 }
3694 fence->syncobj = 0;
3695 }
3696
3697 *pFence = radv_fence_to_handle(fence);
3698
3699 return VK_SUCCESS;
3700 }
3701
3702 void radv_DestroyFence(
3703 VkDevice _device,
3704 VkFence _fence,
3705 const VkAllocationCallbacks* pAllocator)
3706 {
3707 RADV_FROM_HANDLE(radv_device, device, _device);
3708 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3709
3710 if (!fence)
3711 return;
3712
3713 if (fence->temp_syncobj)
3714 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3715 if (fence->syncobj)
3716 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3717 if (fence->fence)
3718 device->ws->destroy_fence(fence->fence);
3719 if (fence->fence_wsi)
3720 fence->fence_wsi->destroy(fence->fence_wsi);
3721 vk_free2(&device->alloc, pAllocator, fence);
3722 }
3723
3724
3725 uint64_t radv_get_current_time(void)
3726 {
3727 struct timespec tv;
3728 clock_gettime(CLOCK_MONOTONIC, &tv);
3729 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3730 }
3731
3732 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3733 {
3734 uint64_t current_time = radv_get_current_time();
3735
3736 timeout = MIN2(UINT64_MAX - current_time, timeout);
3737
3738 return current_time + timeout;
3739 }
3740
3741
3742 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3743 {
3744 for (uint32_t i = 0; i < fenceCount; ++i) {
3745 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3746 if (fence->fence == NULL || fence->syncobj ||
3747 fence->temp_syncobj ||
3748 (!fence->signalled && !fence->submitted))
3749 return false;
3750 }
3751 return true;
3752 }
3753
3754 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3755 {
3756 for (uint32_t i = 0; i < fenceCount; ++i) {
3757 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3758 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3759 return false;
3760 }
3761 return true;
3762 }
3763
3764 VkResult radv_WaitForFences(
3765 VkDevice _device,
3766 uint32_t fenceCount,
3767 const VkFence* pFences,
3768 VkBool32 waitAll,
3769 uint64_t timeout)
3770 {
3771 RADV_FROM_HANDLE(radv_device, device, _device);
3772 timeout = radv_get_absolute_timeout(timeout);
3773
3774 if (device->always_use_syncobj &&
3775 radv_all_fences_syncobj(fenceCount, pFences))
3776 {
3777 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3778 if (!handles)
3779 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3780
3781 for (uint32_t i = 0; i < fenceCount; ++i) {
3782 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3783 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3784 }
3785
3786 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3787
3788 free(handles);
3789 return success ? VK_SUCCESS : VK_TIMEOUT;
3790 }
3791
3792 if (!waitAll && fenceCount > 1) {
3793 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3794 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3795 uint32_t wait_count = 0;
3796 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3797 if (!fences)
3798 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3799
3800 for (uint32_t i = 0; i < fenceCount; ++i) {
3801 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3802
3803 if (fence->signalled) {
3804 free(fences);
3805 return VK_SUCCESS;
3806 }
3807
3808 fences[wait_count++] = fence->fence;
3809 }
3810
3811 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3812 waitAll, timeout - radv_get_current_time());
3813
3814 free(fences);
3815 return success ? VK_SUCCESS : VK_TIMEOUT;
3816 }
3817
3818 while(radv_get_current_time() <= timeout) {
3819 for (uint32_t i = 0; i < fenceCount; ++i) {
3820 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3821 return VK_SUCCESS;
3822 }
3823 }
3824 return VK_TIMEOUT;
3825 }
3826
3827 for (uint32_t i = 0; i < fenceCount; ++i) {
3828 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3829 bool expired = false;
3830
3831 if (fence->temp_syncobj) {
3832 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3833 return VK_TIMEOUT;
3834 continue;
3835 }
3836
3837 if (fence->syncobj) {
3838 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3839 return VK_TIMEOUT;
3840 continue;
3841 }
3842
3843 if (fence->signalled)
3844 continue;
3845
3846 if (fence->fence) {
3847 if (!fence->submitted) {
3848 while(radv_get_current_time() <= timeout &&
3849 !fence->submitted)
3850 /* Do nothing */;
3851
3852 if (!fence->submitted)
3853 return VK_TIMEOUT;
3854
3855 /* Recheck as it may have been set by
3856 * submitting operations. */
3857
3858 if (fence->signalled)
3859 continue;
3860 }
3861
3862 expired = device->ws->fence_wait(device->ws,
3863 fence->fence,
3864 true, timeout);
3865 if (!expired)
3866 return VK_TIMEOUT;
3867 }
3868
3869 if (fence->fence_wsi) {
3870 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3871 if (result != VK_SUCCESS)
3872 return result;
3873 }
3874
3875 fence->signalled = true;
3876 }
3877
3878 return VK_SUCCESS;
3879 }
3880
3881 VkResult radv_ResetFences(VkDevice _device,
3882 uint32_t fenceCount,
3883 const VkFence *pFences)
3884 {
3885 RADV_FROM_HANDLE(radv_device, device, _device);
3886
3887 for (unsigned i = 0; i < fenceCount; ++i) {
3888 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3889 fence->submitted = fence->signalled = false;
3890
3891 /* Per spec, we first restore the permanent payload, and then reset, so
3892 * having a temp syncobj should not skip resetting the permanent syncobj. */
3893 if (fence->temp_syncobj) {
3894 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3895 fence->temp_syncobj = 0;
3896 }
3897
3898 if (fence->syncobj) {
3899 device->ws->reset_syncobj(device->ws, fence->syncobj);
3900 }
3901 }
3902
3903 return VK_SUCCESS;
3904 }
3905
3906 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3907 {
3908 RADV_FROM_HANDLE(radv_device, device, _device);
3909 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3910
3911 if (fence->temp_syncobj) {
3912 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3913 return success ? VK_SUCCESS : VK_NOT_READY;
3914 }
3915
3916 if (fence->syncobj) {
3917 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3918 return success ? VK_SUCCESS : VK_NOT_READY;
3919 }
3920
3921 if (fence->signalled)
3922 return VK_SUCCESS;
3923 if (!fence->submitted)
3924 return VK_NOT_READY;
3925 if (fence->fence) {
3926 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3927 return VK_NOT_READY;
3928 }
3929 if (fence->fence_wsi) {
3930 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3931
3932 if (result != VK_SUCCESS) {
3933 if (result == VK_TIMEOUT)
3934 return VK_NOT_READY;
3935 return result;
3936 }
3937 }
3938 return VK_SUCCESS;
3939 }
3940
3941
3942 // Queue semaphore functions
3943
3944 VkResult radv_CreateSemaphore(
3945 VkDevice _device,
3946 const VkSemaphoreCreateInfo* pCreateInfo,
3947 const VkAllocationCallbacks* pAllocator,
3948 VkSemaphore* pSemaphore)
3949 {
3950 RADV_FROM_HANDLE(radv_device, device, _device);
3951 const VkExportSemaphoreCreateInfo *export =
3952 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3953 VkExternalSemaphoreHandleTypeFlags handleTypes =
3954 export ? export->handleTypes : 0;
3955
3956 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3957 sizeof(*sem), 8,
3958 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3959 if (!sem)
3960 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3961
3962 sem->temp_syncobj = 0;
3963 /* create a syncobject if we are going to export this semaphore */
3964 if (device->always_use_syncobj || handleTypes) {
3965 assert (device->physical_device->rad_info.has_syncobj);
3966 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3967 if (ret) {
3968 vk_free2(&device->alloc, pAllocator, sem);
3969 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3970 }
3971 sem->sem = NULL;
3972 } else {
3973 sem->sem = device->ws->create_sem(device->ws);
3974 if (!sem->sem) {
3975 vk_free2(&device->alloc, pAllocator, sem);
3976 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3977 }
3978 sem->syncobj = 0;
3979 }
3980
3981 *pSemaphore = radv_semaphore_to_handle(sem);
3982 return VK_SUCCESS;
3983 }
3984
3985 void radv_DestroySemaphore(
3986 VkDevice _device,
3987 VkSemaphore _semaphore,
3988 const VkAllocationCallbacks* pAllocator)
3989 {
3990 RADV_FROM_HANDLE(radv_device, device, _device);
3991 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3992 if (!_semaphore)
3993 return;
3994
3995 if (sem->syncobj)
3996 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3997 else
3998 device->ws->destroy_sem(sem->sem);
3999 vk_free2(&device->alloc, pAllocator, sem);
4000 }
4001
4002 VkResult radv_CreateEvent(
4003 VkDevice _device,
4004 const VkEventCreateInfo* pCreateInfo,
4005 const VkAllocationCallbacks* pAllocator,
4006 VkEvent* pEvent)
4007 {
4008 RADV_FROM_HANDLE(radv_device, device, _device);
4009 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4010 sizeof(*event), 8,
4011 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4012
4013 if (!event)
4014 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4015
4016 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4017 RADEON_DOMAIN_GTT,
4018 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4019 RADV_BO_PRIORITY_FENCE);
4020 if (!event->bo) {
4021 vk_free2(&device->alloc, pAllocator, event);
4022 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4023 }
4024
4025 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4026
4027 *pEvent = radv_event_to_handle(event);
4028
4029 return VK_SUCCESS;
4030 }
4031
4032 void radv_DestroyEvent(
4033 VkDevice _device,
4034 VkEvent _event,
4035 const VkAllocationCallbacks* pAllocator)
4036 {
4037 RADV_FROM_HANDLE(radv_device, device, _device);
4038 RADV_FROM_HANDLE(radv_event, event, _event);
4039
4040 if (!event)
4041 return;
4042 device->ws->buffer_destroy(event->bo);
4043 vk_free2(&device->alloc, pAllocator, event);
4044 }
4045
4046 VkResult radv_GetEventStatus(
4047 VkDevice _device,
4048 VkEvent _event)
4049 {
4050 RADV_FROM_HANDLE(radv_event, event, _event);
4051
4052 if (*event->map == 1)
4053 return VK_EVENT_SET;
4054 return VK_EVENT_RESET;
4055 }
4056
4057 VkResult radv_SetEvent(
4058 VkDevice _device,
4059 VkEvent _event)
4060 {
4061 RADV_FROM_HANDLE(radv_event, event, _event);
4062 *event->map = 1;
4063
4064 return VK_SUCCESS;
4065 }
4066
4067 VkResult radv_ResetEvent(
4068 VkDevice _device,
4069 VkEvent _event)
4070 {
4071 RADV_FROM_HANDLE(radv_event, event, _event);
4072 *event->map = 0;
4073
4074 return VK_SUCCESS;
4075 }
4076
4077 VkResult radv_CreateBuffer(
4078 VkDevice _device,
4079 const VkBufferCreateInfo* pCreateInfo,
4080 const VkAllocationCallbacks* pAllocator,
4081 VkBuffer* pBuffer)
4082 {
4083 RADV_FROM_HANDLE(radv_device, device, _device);
4084 struct radv_buffer *buffer;
4085
4086 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4087
4088 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4090 if (buffer == NULL)
4091 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4092
4093 buffer->size = pCreateInfo->size;
4094 buffer->usage = pCreateInfo->usage;
4095 buffer->bo = NULL;
4096 buffer->offset = 0;
4097 buffer->flags = pCreateInfo->flags;
4098
4099 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4100 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4101
4102 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4103 buffer->bo = device->ws->buffer_create(device->ws,
4104 align64(buffer->size, 4096),
4105 4096, 0, RADEON_FLAG_VIRTUAL,
4106 RADV_BO_PRIORITY_VIRTUAL);
4107 if (!buffer->bo) {
4108 vk_free2(&device->alloc, pAllocator, buffer);
4109 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4110 }
4111 }
4112
4113 *pBuffer = radv_buffer_to_handle(buffer);
4114
4115 return VK_SUCCESS;
4116 }
4117
4118 void radv_DestroyBuffer(
4119 VkDevice _device,
4120 VkBuffer _buffer,
4121 const VkAllocationCallbacks* pAllocator)
4122 {
4123 RADV_FROM_HANDLE(radv_device, device, _device);
4124 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4125
4126 if (!buffer)
4127 return;
4128
4129 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4130 device->ws->buffer_destroy(buffer->bo);
4131
4132 vk_free2(&device->alloc, pAllocator, buffer);
4133 }
4134
4135 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4136 VkDevice device,
4137 const VkBufferDeviceAddressInfoEXT* pInfo)
4138 {
4139 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4140 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4141 }
4142
4143
4144 static inline unsigned
4145 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4146 {
4147 if (stencil)
4148 return plane->surface.u.legacy.stencil_tiling_index[level];
4149 else
4150 return plane->surface.u.legacy.tiling_index[level];
4151 }
4152
4153 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4154 {
4155 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4156 }
4157
4158 static uint32_t
4159 radv_init_dcc_control_reg(struct radv_device *device,
4160 struct radv_image_view *iview)
4161 {
4162 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4163 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4164 unsigned max_compressed_block_size;
4165 unsigned independent_64b_blocks;
4166
4167 if (!radv_image_has_dcc(iview->image))
4168 return 0;
4169
4170 if (iview->image->info.samples > 1) {
4171 if (iview->image->planes[0].surface.bpe == 1)
4172 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4173 else if (iview->image->planes[0].surface.bpe == 2)
4174 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4175 }
4176
4177 if (!device->physical_device->rad_info.has_dedicated_vram) {
4178 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4179 * dGPU and 64 for APU because all of our APUs to date use
4180 * DIMMs which have a request granularity size of 64B while all
4181 * other chips have a 32B request size.
4182 */
4183 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4184 }
4185
4186 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4187 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4188 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4189 /* If this DCC image is potentially going to be used in texture
4190 * fetches, we need some special settings.
4191 */
4192 independent_64b_blocks = 1;
4193 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4194 } else {
4195 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4196 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4197 * big as possible for better compression state.
4198 */
4199 independent_64b_blocks = 0;
4200 max_compressed_block_size = max_uncompressed_block_size;
4201 }
4202
4203 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4204 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4205 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4206 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4207 }
4208
4209 static void
4210 radv_initialise_color_surface(struct radv_device *device,
4211 struct radv_color_buffer_info *cb,
4212 struct radv_image_view *iview)
4213 {
4214 const struct vk_format_description *desc;
4215 unsigned ntype, format, swap, endian;
4216 unsigned blend_clamp = 0, blend_bypass = 0;
4217 uint64_t va;
4218 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4219 const struct radeon_surf *surf = &plane->surface;
4220
4221 desc = vk_format_description(iview->vk_format);
4222
4223 memset(cb, 0, sizeof(*cb));
4224
4225 /* Intensity is implemented as Red, so treat it that way. */
4226 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4227
4228 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4229
4230 cb->cb_color_base = va >> 8;
4231
4232 if (device->physical_device->rad_info.chip_class >= GFX9) {
4233 struct gfx9_surf_meta_flags meta;
4234 if (iview->image->dcc_offset)
4235 meta = surf->u.gfx9.dcc;
4236 else
4237 meta = surf->u.gfx9.cmask;
4238
4239 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4240 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4241 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4242 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4243
4244 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4245 cb->cb_color_base |= surf->tile_swizzle;
4246
4247 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4248 } else {
4249 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4250 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4251
4252 cb->cb_color_base += level_info->offset >> 8;
4253 if (level_info->mode == RADEON_SURF_MODE_2D)
4254 cb->cb_color_base |= surf->tile_swizzle;
4255
4256 pitch_tile_max = level_info->nblk_x / 8 - 1;
4257 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4258 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4259
4260 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4261 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4262 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4263
4264 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4265
4266 if (radv_image_has_fmask(iview->image)) {
4267 if (device->physical_device->rad_info.chip_class >= CIK)
4268 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4269 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4270 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4271 } else {
4272 /* This must be set for fast clear to work without FMASK. */
4273 if (device->physical_device->rad_info.chip_class >= CIK)
4274 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4275 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4276 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4277 }
4278 }
4279
4280 /* CMASK variables */
4281 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4282 va += iview->image->cmask.offset;
4283 cb->cb_color_cmask = va >> 8;
4284
4285 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4286 va += iview->image->dcc_offset;
4287 cb->cb_dcc_base = va >> 8;
4288 cb->cb_dcc_base |= surf->tile_swizzle;
4289
4290 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4291 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4292 S_028C6C_SLICE_MAX(max_slice);
4293
4294 if (iview->image->info.samples > 1) {
4295 unsigned log_samples = util_logbase2(iview->image->info.samples);
4296
4297 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4298 S_028C74_NUM_FRAGMENTS(log_samples);
4299 }
4300
4301 if (radv_image_has_fmask(iview->image)) {
4302 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4303 cb->cb_color_fmask = va >> 8;
4304 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4305 } else {
4306 cb->cb_color_fmask = cb->cb_color_base;
4307 }
4308
4309 ntype = radv_translate_color_numformat(iview->vk_format,
4310 desc,
4311 vk_format_get_first_non_void_channel(iview->vk_format));
4312 format = radv_translate_colorformat(iview->vk_format);
4313 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4314 radv_finishme("Illegal color\n");
4315 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4316 endian = radv_colorformat_endian_swap(format);
4317
4318 /* blend clamp should be set for all NORM/SRGB types */
4319 if (ntype == V_028C70_NUMBER_UNORM ||
4320 ntype == V_028C70_NUMBER_SNORM ||
4321 ntype == V_028C70_NUMBER_SRGB)
4322 blend_clamp = 1;
4323
4324 /* set blend bypass according to docs if SINT/UINT or
4325 8/24 COLOR variants */
4326 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4327 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4328 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4329 blend_clamp = 0;
4330 blend_bypass = 1;
4331 }
4332 #if 0
4333 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4334 (format == V_028C70_COLOR_8 ||
4335 format == V_028C70_COLOR_8_8 ||
4336 format == V_028C70_COLOR_8_8_8_8))
4337 ->color_is_int8 = true;
4338 #endif
4339 cb->cb_color_info = S_028C70_FORMAT(format) |
4340 S_028C70_COMP_SWAP(swap) |
4341 S_028C70_BLEND_CLAMP(blend_clamp) |
4342 S_028C70_BLEND_BYPASS(blend_bypass) |
4343 S_028C70_SIMPLE_FLOAT(1) |
4344 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4345 ntype != V_028C70_NUMBER_SNORM &&
4346 ntype != V_028C70_NUMBER_SRGB &&
4347 format != V_028C70_COLOR_8_24 &&
4348 format != V_028C70_COLOR_24_8) |
4349 S_028C70_NUMBER_TYPE(ntype) |
4350 S_028C70_ENDIAN(endian);
4351 if (radv_image_has_fmask(iview->image)) {
4352 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4353 if (device->physical_device->rad_info.chip_class == SI) {
4354 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4355 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4356 }
4357 }
4358
4359 if (radv_image_has_cmask(iview->image) &&
4360 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4361 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4362
4363 if (radv_dcc_enabled(iview->image, iview->base_mip))
4364 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4365
4366 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4367
4368 /* This must be set for fast clear to work without FMASK. */
4369 if (!radv_image_has_fmask(iview->image) &&
4370 device->physical_device->rad_info.chip_class == SI) {
4371 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4372 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4373 }
4374
4375 if (device->physical_device->rad_info.chip_class >= GFX9) {
4376 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4377 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4378
4379 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4380 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4381 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4382 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4383 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4384 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4385 }
4386 }
4387
4388 static unsigned
4389 radv_calc_decompress_on_z_planes(struct radv_device *device,
4390 struct radv_image_view *iview)
4391 {
4392 unsigned max_zplanes = 0;
4393
4394 assert(radv_image_is_tc_compat_htile(iview->image));
4395
4396 if (device->physical_device->rad_info.chip_class >= GFX9) {
4397 /* Default value for 32-bit depth surfaces. */
4398 max_zplanes = 4;
4399
4400 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4401 iview->image->info.samples > 1)
4402 max_zplanes = 2;
4403
4404 max_zplanes = max_zplanes + 1;
4405 } else {
4406 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4407 /* Do not enable Z plane compression for 16-bit depth
4408 * surfaces because isn't supported on GFX8. Only
4409 * 32-bit depth surfaces are supported by the hardware.
4410 * This allows to maintain shader compatibility and to
4411 * reduce the number of depth decompressions.
4412 */
4413 max_zplanes = 1;
4414 } else {
4415 if (iview->image->info.samples <= 1)
4416 max_zplanes = 5;
4417 else if (iview->image->info.samples <= 4)
4418 max_zplanes = 3;
4419 else
4420 max_zplanes = 2;
4421 }
4422 }
4423
4424 return max_zplanes;
4425 }
4426
4427 static void
4428 radv_initialise_ds_surface(struct radv_device *device,
4429 struct radv_ds_buffer_info *ds,
4430 struct radv_image_view *iview)
4431 {
4432 unsigned level = iview->base_mip;
4433 unsigned format, stencil_format;
4434 uint64_t va, s_offs, z_offs;
4435 bool stencil_only = false;
4436 const struct radv_image_plane *plane = &iview->image->planes[0];
4437 const struct radeon_surf *surf = &plane->surface;
4438
4439 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4440
4441 memset(ds, 0, sizeof(*ds));
4442 switch (iview->image->vk_format) {
4443 case VK_FORMAT_D24_UNORM_S8_UINT:
4444 case VK_FORMAT_X8_D24_UNORM_PACK32:
4445 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4446 ds->offset_scale = 2.0f;
4447 break;
4448 case VK_FORMAT_D16_UNORM:
4449 case VK_FORMAT_D16_UNORM_S8_UINT:
4450 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4451 ds->offset_scale = 4.0f;
4452 break;
4453 case VK_FORMAT_D32_SFLOAT:
4454 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4455 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4456 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4457 ds->offset_scale = 1.0f;
4458 break;
4459 case VK_FORMAT_S8_UINT:
4460 stencil_only = true;
4461 break;
4462 default:
4463 break;
4464 }
4465
4466 format = radv_translate_dbformat(iview->image->vk_format);
4467 stencil_format = surf->has_stencil ?
4468 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4469
4470 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4471 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4472 S_028008_SLICE_MAX(max_slice);
4473
4474 ds->db_htile_data_base = 0;
4475 ds->db_htile_surface = 0;
4476
4477 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4478 s_offs = z_offs = va;
4479
4480 if (device->physical_device->rad_info.chip_class >= GFX9) {
4481 assert(surf->u.gfx9.surf_offset == 0);
4482 s_offs += surf->u.gfx9.stencil_offset;
4483
4484 ds->db_z_info = S_028038_FORMAT(format) |
4485 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4486 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4487 S_028038_MAXMIP(iview->image->info.levels - 1) |
4488 S_028038_ZRANGE_PRECISION(1);
4489 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4490 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4491
4492 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4493 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4494 ds->db_depth_view |= S_028008_MIPID(level);
4495
4496 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4497 S_02801C_Y_MAX(iview->image->info.height - 1);
4498
4499 if (radv_htile_enabled(iview->image, level)) {
4500 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4501
4502 if (radv_image_is_tc_compat_htile(iview->image)) {
4503 unsigned max_zplanes =
4504 radv_calc_decompress_on_z_planes(device, iview);
4505
4506 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4507 S_028038_ITERATE_FLUSH(1);
4508 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4509 }
4510
4511 if (!surf->has_stencil)
4512 /* Use all of the htile_buffer for depth if there's no stencil. */
4513 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4514 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4515 iview->image->htile_offset;
4516 ds->db_htile_data_base = va >> 8;
4517 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4518 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4519 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4520 }
4521 } else {
4522 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4523
4524 if (stencil_only)
4525 level_info = &surf->u.legacy.stencil_level[level];
4526
4527 z_offs += surf->u.legacy.level[level].offset;
4528 s_offs += surf->u.legacy.stencil_level[level].offset;
4529
4530 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4531 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4532 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4533
4534 if (iview->image->info.samples > 1)
4535 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4536
4537 if (device->physical_device->rad_info.chip_class >= CIK) {
4538 struct radeon_info *info = &device->physical_device->rad_info;
4539 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4540 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4541 unsigned macro_index = surf->u.legacy.macro_tile_index;
4542 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4543 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4544 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4545
4546 if (stencil_only)
4547 tile_mode = stencil_tile_mode;
4548
4549 ds->db_depth_info |=
4550 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4551 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4552 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4553 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4554 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4555 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4556 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4557 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4558 } else {
4559 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4560 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4561 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4562 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4563 if (stencil_only)
4564 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4565 }
4566
4567 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4568 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4569 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4570
4571 if (radv_htile_enabled(iview->image, level)) {
4572 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4573
4574 if (!surf->has_stencil &&
4575 !radv_image_is_tc_compat_htile(iview->image))
4576 /* Use all of the htile_buffer for depth if there's no stencil. */
4577 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4578
4579 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4580 iview->image->htile_offset;
4581 ds->db_htile_data_base = va >> 8;
4582 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4583
4584 if (radv_image_is_tc_compat_htile(iview->image)) {
4585 unsigned max_zplanes =
4586 radv_calc_decompress_on_z_planes(device, iview);
4587
4588 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4589 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4590 }
4591 }
4592 }
4593
4594 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4595 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4596 }
4597
4598 VkResult radv_CreateFramebuffer(
4599 VkDevice _device,
4600 const VkFramebufferCreateInfo* pCreateInfo,
4601 const VkAllocationCallbacks* pAllocator,
4602 VkFramebuffer* pFramebuffer)
4603 {
4604 RADV_FROM_HANDLE(radv_device, device, _device);
4605 struct radv_framebuffer *framebuffer;
4606
4607 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4608
4609 size_t size = sizeof(*framebuffer) +
4610 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4611 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4612 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4613 if (framebuffer == NULL)
4614 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4615
4616 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4617 framebuffer->width = pCreateInfo->width;
4618 framebuffer->height = pCreateInfo->height;
4619 framebuffer->layers = pCreateInfo->layers;
4620 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4621 VkImageView _iview = pCreateInfo->pAttachments[i];
4622 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4623 framebuffer->attachments[i].attachment = iview;
4624 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4625 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4626 } else {
4627 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4628 }
4629 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4630 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4631 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4632 }
4633
4634 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4635 return VK_SUCCESS;
4636 }
4637
4638 void radv_DestroyFramebuffer(
4639 VkDevice _device,
4640 VkFramebuffer _fb,
4641 const VkAllocationCallbacks* pAllocator)
4642 {
4643 RADV_FROM_HANDLE(radv_device, device, _device);
4644 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4645
4646 if (!fb)
4647 return;
4648 vk_free2(&device->alloc, pAllocator, fb);
4649 }
4650
4651 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4652 {
4653 switch (address_mode) {
4654 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4655 return V_008F30_SQ_TEX_WRAP;
4656 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4657 return V_008F30_SQ_TEX_MIRROR;
4658 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4659 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4660 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4661 return V_008F30_SQ_TEX_CLAMP_BORDER;
4662 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4663 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4664 default:
4665 unreachable("illegal tex wrap mode");
4666 break;
4667 }
4668 }
4669
4670 static unsigned
4671 radv_tex_compare(VkCompareOp op)
4672 {
4673 switch (op) {
4674 case VK_COMPARE_OP_NEVER:
4675 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4676 case VK_COMPARE_OP_LESS:
4677 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4678 case VK_COMPARE_OP_EQUAL:
4679 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4680 case VK_COMPARE_OP_LESS_OR_EQUAL:
4681 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4682 case VK_COMPARE_OP_GREATER:
4683 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4684 case VK_COMPARE_OP_NOT_EQUAL:
4685 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4686 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4687 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4688 case VK_COMPARE_OP_ALWAYS:
4689 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4690 default:
4691 unreachable("illegal compare mode");
4692 break;
4693 }
4694 }
4695
4696 static unsigned
4697 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4698 {
4699 switch (filter) {
4700 case VK_FILTER_NEAREST:
4701 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4702 V_008F38_SQ_TEX_XY_FILTER_POINT);
4703 case VK_FILTER_LINEAR:
4704 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4705 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4706 case VK_FILTER_CUBIC_IMG:
4707 default:
4708 fprintf(stderr, "illegal texture filter");
4709 return 0;
4710 }
4711 }
4712
4713 static unsigned
4714 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4715 {
4716 switch (mode) {
4717 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4718 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4719 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4720 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4721 default:
4722 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4723 }
4724 }
4725
4726 static unsigned
4727 radv_tex_bordercolor(VkBorderColor bcolor)
4728 {
4729 switch (bcolor) {
4730 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4731 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4732 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4733 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4734 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4735 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4736 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4737 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4738 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4739 default:
4740 break;
4741 }
4742 return 0;
4743 }
4744
4745 static unsigned
4746 radv_tex_aniso_filter(unsigned filter)
4747 {
4748 if (filter < 2)
4749 return 0;
4750 if (filter < 4)
4751 return 1;
4752 if (filter < 8)
4753 return 2;
4754 if (filter < 16)
4755 return 3;
4756 return 4;
4757 }
4758
4759 static unsigned
4760 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4761 {
4762 switch (mode) {
4763 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4764 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4765 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4766 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4767 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4768 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4769 default:
4770 break;
4771 }
4772 return 0;
4773 }
4774
4775 static uint32_t
4776 radv_get_max_anisotropy(struct radv_device *device,
4777 const VkSamplerCreateInfo *pCreateInfo)
4778 {
4779 if (device->force_aniso >= 0)
4780 return device->force_aniso;
4781
4782 if (pCreateInfo->anisotropyEnable &&
4783 pCreateInfo->maxAnisotropy > 1.0f)
4784 return (uint32_t)pCreateInfo->maxAnisotropy;
4785
4786 return 0;
4787 }
4788
4789 static void
4790 radv_init_sampler(struct radv_device *device,
4791 struct radv_sampler *sampler,
4792 const VkSamplerCreateInfo *pCreateInfo)
4793 {
4794 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4795 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4796 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4797 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4798
4799 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4800 vk_find_struct_const(pCreateInfo->pNext,
4801 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4802 if (sampler_reduction)
4803 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4804
4805 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4806 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4807 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4808 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4809 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4810 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4811 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4812 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4813 S_008F30_DISABLE_CUBE_WRAP(0) |
4814 S_008F30_COMPAT_MODE(is_vi) |
4815 S_008F30_FILTER_MODE(filter_mode));
4816 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4817 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4818 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4819 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4820 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4821 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4822 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4823 S_008F38_MIP_POINT_PRECLAMP(0) |
4824 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4825 S_008F38_FILTER_PREC_FIX(1) |
4826 S_008F38_ANISO_OVERRIDE(is_vi));
4827 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4828 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4829 }
4830
4831 VkResult radv_CreateSampler(
4832 VkDevice _device,
4833 const VkSamplerCreateInfo* pCreateInfo,
4834 const VkAllocationCallbacks* pAllocator,
4835 VkSampler* pSampler)
4836 {
4837 RADV_FROM_HANDLE(radv_device, device, _device);
4838 struct radv_sampler *sampler;
4839
4840 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4841 vk_find_struct_const(pCreateInfo->pNext,
4842 SAMPLER_YCBCR_CONVERSION_INFO);
4843
4844 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4845
4846 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4847 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4848 if (!sampler)
4849 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4850
4851 radv_init_sampler(device, sampler, pCreateInfo);
4852
4853 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4854 *pSampler = radv_sampler_to_handle(sampler);
4855
4856 return VK_SUCCESS;
4857 }
4858
4859 void radv_DestroySampler(
4860 VkDevice _device,
4861 VkSampler _sampler,
4862 const VkAllocationCallbacks* pAllocator)
4863 {
4864 RADV_FROM_HANDLE(radv_device, device, _device);
4865 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4866
4867 if (!sampler)
4868 return;
4869 vk_free2(&device->alloc, pAllocator, sampler);
4870 }
4871
4872 /* vk_icd.h does not declare this function, so we declare it here to
4873 * suppress Wmissing-prototypes.
4874 */
4875 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4876 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4877
4878 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4879 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4880 {
4881 /* For the full details on loader interface versioning, see
4882 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4883 * What follows is a condensed summary, to help you navigate the large and
4884 * confusing official doc.
4885 *
4886 * - Loader interface v0 is incompatible with later versions. We don't
4887 * support it.
4888 *
4889 * - In loader interface v1:
4890 * - The first ICD entrypoint called by the loader is
4891 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4892 * entrypoint.
4893 * - The ICD must statically expose no other Vulkan symbol unless it is
4894 * linked with -Bsymbolic.
4895 * - Each dispatchable Vulkan handle created by the ICD must be
4896 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4897 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4898 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4899 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4900 * such loader-managed surfaces.
4901 *
4902 * - Loader interface v2 differs from v1 in:
4903 * - The first ICD entrypoint called by the loader is
4904 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4905 * statically expose this entrypoint.
4906 *
4907 * - Loader interface v3 differs from v2 in:
4908 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4909 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4910 * because the loader no longer does so.
4911 */
4912 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4913 return VK_SUCCESS;
4914 }
4915
4916 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4917 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4918 int *pFD)
4919 {
4920 RADV_FROM_HANDLE(radv_device, device, _device);
4921 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4922
4923 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4924
4925 /* At the moment, we support only the below handle types. */
4926 assert(pGetFdInfo->handleType ==
4927 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4928 pGetFdInfo->handleType ==
4929 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4930
4931 bool ret = radv_get_memory_fd(device, memory, pFD);
4932 if (ret == false)
4933 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4934 return VK_SUCCESS;
4935 }
4936
4937 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4938 VkExternalMemoryHandleTypeFlagBits handleType,
4939 int fd,
4940 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4941 {
4942 RADV_FROM_HANDLE(radv_device, device, _device);
4943
4944 switch (handleType) {
4945 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4946 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4947 return VK_SUCCESS;
4948
4949 default:
4950 /* The valid usage section for this function says:
4951 *
4952 * "handleType must not be one of the handle types defined as
4953 * opaque."
4954 *
4955 * So opaque handle types fall into the default "unsupported" case.
4956 */
4957 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4958 }
4959 }
4960
4961 static VkResult radv_import_opaque_fd(struct radv_device *device,
4962 int fd,
4963 uint32_t *syncobj)
4964 {
4965 uint32_t syncobj_handle = 0;
4966 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4967 if (ret != 0)
4968 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4969
4970 if (*syncobj)
4971 device->ws->destroy_syncobj(device->ws, *syncobj);
4972
4973 *syncobj = syncobj_handle;
4974 close(fd);
4975
4976 return VK_SUCCESS;
4977 }
4978
4979 static VkResult radv_import_sync_fd(struct radv_device *device,
4980 int fd,
4981 uint32_t *syncobj)
4982 {
4983 /* If we create a syncobj we do it locally so that if we have an error, we don't
4984 * leave a syncobj in an undetermined state in the fence. */
4985 uint32_t syncobj_handle = *syncobj;
4986 if (!syncobj_handle) {
4987 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4988 if (ret) {
4989 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4990 }
4991 }
4992
4993 if (fd == -1) {
4994 device->ws->signal_syncobj(device->ws, syncobj_handle);
4995 } else {
4996 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4997 if (ret != 0)
4998 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4999 }
5000
5001 *syncobj = syncobj_handle;
5002 if (fd != -1)
5003 close(fd);
5004
5005 return VK_SUCCESS;
5006 }
5007
5008 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5009 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5010 {
5011 RADV_FROM_HANDLE(radv_device, device, _device);
5012 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5013 uint32_t *syncobj_dst = NULL;
5014
5015 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5016 syncobj_dst = &sem->temp_syncobj;
5017 } else {
5018 syncobj_dst = &sem->syncobj;
5019 }
5020
5021 switch(pImportSemaphoreFdInfo->handleType) {
5022 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5023 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5024 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5025 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5026 default:
5027 unreachable("Unhandled semaphore handle type");
5028 }
5029 }
5030
5031 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5032 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5033 int *pFd)
5034 {
5035 RADV_FROM_HANDLE(radv_device, device, _device);
5036 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5037 int ret;
5038 uint32_t syncobj_handle;
5039
5040 if (sem->temp_syncobj)
5041 syncobj_handle = sem->temp_syncobj;
5042 else
5043 syncobj_handle = sem->syncobj;
5044
5045 switch(pGetFdInfo->handleType) {
5046 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5047 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5048 break;
5049 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5050 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5051 if (!ret) {
5052 if (sem->temp_syncobj) {
5053 close (sem->temp_syncobj);
5054 sem->temp_syncobj = 0;
5055 } else {
5056 device->ws->reset_syncobj(device->ws, syncobj_handle);
5057 }
5058 }
5059 break;
5060 default:
5061 unreachable("Unhandled semaphore handle type");
5062 }
5063
5064 if (ret)
5065 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5066 return VK_SUCCESS;
5067 }
5068
5069 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5070 VkPhysicalDevice physicalDevice,
5071 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5072 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5073 {
5074 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5075
5076 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5077 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5078 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5079 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5080 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5081 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5082 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5083 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5084 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5085 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5086 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5087 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5088 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5089 } else {
5090 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5091 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5092 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5093 }
5094 }
5095
5096 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5097 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5098 {
5099 RADV_FROM_HANDLE(radv_device, device, _device);
5100 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5101 uint32_t *syncobj_dst = NULL;
5102
5103
5104 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5105 syncobj_dst = &fence->temp_syncobj;
5106 } else {
5107 syncobj_dst = &fence->syncobj;
5108 }
5109
5110 switch(pImportFenceFdInfo->handleType) {
5111 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5112 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5113 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5114 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5115 default:
5116 unreachable("Unhandled fence handle type");
5117 }
5118 }
5119
5120 VkResult radv_GetFenceFdKHR(VkDevice _device,
5121 const VkFenceGetFdInfoKHR *pGetFdInfo,
5122 int *pFd)
5123 {
5124 RADV_FROM_HANDLE(radv_device, device, _device);
5125 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5126 int ret;
5127 uint32_t syncobj_handle;
5128
5129 if (fence->temp_syncobj)
5130 syncobj_handle = fence->temp_syncobj;
5131 else
5132 syncobj_handle = fence->syncobj;
5133
5134 switch(pGetFdInfo->handleType) {
5135 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5136 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5137 break;
5138 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5139 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5140 if (!ret) {
5141 if (fence->temp_syncobj) {
5142 close (fence->temp_syncobj);
5143 fence->temp_syncobj = 0;
5144 } else {
5145 device->ws->reset_syncobj(device->ws, syncobj_handle);
5146 }
5147 }
5148 break;
5149 default:
5150 unreachable("Unhandled fence handle type");
5151 }
5152
5153 if (ret)
5154 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5155 return VK_SUCCESS;
5156 }
5157
5158 void radv_GetPhysicalDeviceExternalFenceProperties(
5159 VkPhysicalDevice physicalDevice,
5160 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5161 VkExternalFenceProperties *pExternalFenceProperties)
5162 {
5163 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5164
5165 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5166 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5167 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5168 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5169 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5170 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5171 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5172 } else {
5173 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5174 pExternalFenceProperties->compatibleHandleTypes = 0;
5175 pExternalFenceProperties->externalFenceFeatures = 0;
5176 }
5177 }
5178
5179 VkResult
5180 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5181 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5182 const VkAllocationCallbacks* pAllocator,
5183 VkDebugReportCallbackEXT* pCallback)
5184 {
5185 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5186 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5187 pCreateInfo, pAllocator, &instance->alloc,
5188 pCallback);
5189 }
5190
5191 void
5192 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5193 VkDebugReportCallbackEXT _callback,
5194 const VkAllocationCallbacks* pAllocator)
5195 {
5196 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5197 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5198 _callback, pAllocator, &instance->alloc);
5199 }
5200
5201 void
5202 radv_DebugReportMessageEXT(VkInstance _instance,
5203 VkDebugReportFlagsEXT flags,
5204 VkDebugReportObjectTypeEXT objectType,
5205 uint64_t object,
5206 size_t location,
5207 int32_t messageCode,
5208 const char* pLayerPrefix,
5209 const char* pMessage)
5210 {
5211 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5212 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5213 object, location, messageCode, pLayerPrefix, pMessage);
5214 }
5215
5216 void
5217 radv_GetDeviceGroupPeerMemoryFeatures(
5218 VkDevice device,
5219 uint32_t heapIndex,
5220 uint32_t localDeviceIndex,
5221 uint32_t remoteDeviceIndex,
5222 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5223 {
5224 assert(localDeviceIndex == remoteDeviceIndex);
5225
5226 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5227 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5228 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5229 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5230 }
5231
5232 static const VkTimeDomainEXT radv_time_domains[] = {
5233 VK_TIME_DOMAIN_DEVICE_EXT,
5234 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5235 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5236 };
5237
5238 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5239 VkPhysicalDevice physicalDevice,
5240 uint32_t *pTimeDomainCount,
5241 VkTimeDomainEXT *pTimeDomains)
5242 {
5243 int d;
5244 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5245
5246 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5247 vk_outarray_append(&out, i) {
5248 *i = radv_time_domains[d];
5249 }
5250 }
5251
5252 return vk_outarray_status(&out);
5253 }
5254
5255 static uint64_t
5256 radv_clock_gettime(clockid_t clock_id)
5257 {
5258 struct timespec current;
5259 int ret;
5260
5261 ret = clock_gettime(clock_id, &current);
5262 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5263 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5264 if (ret < 0)
5265 return 0;
5266
5267 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5268 }
5269
5270 VkResult radv_GetCalibratedTimestampsEXT(
5271 VkDevice _device,
5272 uint32_t timestampCount,
5273 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5274 uint64_t *pTimestamps,
5275 uint64_t *pMaxDeviation)
5276 {
5277 RADV_FROM_HANDLE(radv_device, device, _device);
5278 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5279 int d;
5280 uint64_t begin, end;
5281 uint64_t max_clock_period = 0;
5282
5283 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5284
5285 for (d = 0; d < timestampCount; d++) {
5286 switch (pTimestampInfos[d].timeDomain) {
5287 case VK_TIME_DOMAIN_DEVICE_EXT:
5288 pTimestamps[d] = device->ws->query_value(device->ws,
5289 RADEON_TIMESTAMP);
5290 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5291 max_clock_period = MAX2(max_clock_period, device_period);
5292 break;
5293 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5294 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5295 max_clock_period = MAX2(max_clock_period, 1);
5296 break;
5297
5298 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5299 pTimestamps[d] = begin;
5300 break;
5301 default:
5302 pTimestamps[d] = 0;
5303 break;
5304 }
5305 }
5306
5307 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5308
5309 /*
5310 * The maximum deviation is the sum of the interval over which we
5311 * perform the sampling and the maximum period of any sampled
5312 * clock. That's because the maximum skew between any two sampled
5313 * clock edges is when the sampled clock with the largest period is
5314 * sampled at the end of that period but right at the beginning of the
5315 * sampling interval and some other clock is sampled right at the
5316 * begining of its sampling period and right at the end of the
5317 * sampling interval. Let's assume the GPU has the longest clock
5318 * period and that the application is sampling GPU and monotonic:
5319 *
5320 * s e
5321 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5322 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5323 *
5324 * g
5325 * 0 1 2 3
5326 * GPU -----_____-----_____-----_____-----_____
5327 *
5328 * m
5329 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5330 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5331 *
5332 * Interval <----------------->
5333 * Deviation <-------------------------->
5334 *
5335 * s = read(raw) 2
5336 * g = read(GPU) 1
5337 * m = read(monotonic) 2
5338 * e = read(raw) b
5339 *
5340 * We round the sample interval up by one tick to cover sampling error
5341 * in the interval clock
5342 */
5343
5344 uint64_t sample_interval = end - begin + 1;
5345
5346 *pMaxDeviation = sample_interval + max_clock_period;
5347
5348 return VK_SUCCESS;
5349 }