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1ed5dc668d2bb3c1b3659076cbcbb51b38e9642d
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const VkImageCreateInfo *pCreateInfo,
40 VkFormat format)
41 {
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 if (!vk_format_is_compressed(format) &&
48 !vk_format_is_depth_or_stencil(format)
49 && device->physical_device->rad_info.chip_class <= GFX8) {
50 /* this causes hangs in some VK CTS tests on GFX9. */
51 /* Textures with a very small height are recommended to be linear. */
52 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
53 /* Only very thin and long 2D textures should benefit from
54 * linear_aligned. */
55 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
56 return RADEON_SURF_MODE_LINEAR_ALIGNED;
57 }
58
59 /* MSAA resources must be 2D tiled. */
60 if (pCreateInfo->samples > 1)
61 return RADEON_SURF_MODE_2D;
62
63 return RADEON_SURF_MODE_2D;
64 }
65
66 static bool
67 radv_use_tc_compat_htile_for_image(struct radv_device *device,
68 const VkImageCreateInfo *pCreateInfo,
69 VkFormat format)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
76 return false;
77
78 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
79 return false;
80
81 if (pCreateInfo->mipLevels > 1)
82 return false;
83
84 /* Do not enable TC-compatible HTILE if the image isn't readable by a
85 * shader because no texture fetches will happen.
86 */
87 if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
88 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
89 VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
90 return false;
91
92 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
93 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
94 */
95 if (pCreateInfo->samples >= 2 &&
96 (format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
97 (format == VK_FORMAT_D32_SFLOAT &&
98 device->physical_device->rad_info.chip_class == GFX10)))
99 return false;
100
101 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
102 * supports 32-bit. Though, it's possible to enable TC-compat for
103 * 16-bit depth surfaces if no Z planes are compressed.
104 */
105 if (format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
106 format != VK_FORMAT_D32_SFLOAT &&
107 format != VK_FORMAT_D16_UNORM)
108 return false;
109
110 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
111 const struct VkImageFormatListCreateInfo *format_list =
112 (const struct VkImageFormatListCreateInfo *)
113 vk_find_struct_const(pCreateInfo->pNext,
114 IMAGE_FORMAT_LIST_CREATE_INFO);
115
116 /* We have to ignore the existence of the list if viewFormatCount = 0 */
117 if (format_list && format_list->viewFormatCount) {
118 /* compatibility is transitive, so we only need to check
119 * one format with everything else.
120 */
121 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
122 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
123 continue;
124
125 if (format != format_list->pViewFormats[i])
126 return false;
127 }
128 } else {
129 return false;
130 }
131 }
132
133 return true;
134 }
135
136 static bool
137 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
138 {
139 if (info->bo_metadata) {
140 if (device->physical_device->rad_info.chip_class >= GFX9)
141 return info->bo_metadata->u.gfx9.scanout;
142 else
143 return info->bo_metadata->u.legacy.scanout;
144 }
145
146 return info->scanout;
147 }
148
149 static bool
150 radv_use_dcc_for_image(struct radv_device *device,
151 const struct radv_image *image,
152 const VkImageCreateInfo *pCreateInfo,
153 VkFormat format)
154 {
155 bool dcc_compatible_formats;
156 bool blendable;
157
158 /* DCC (Delta Color Compression) is only available for GFX8+. */
159 if (device->physical_device->rad_info.chip_class < GFX8)
160 return false;
161
162 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
163 return false;
164
165 if (image->shareable)
166 return false;
167
168 /* TODO: Enable DCC for storage images. */
169 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
170 return false;
171
172 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
173 return false;
174
175 if (vk_format_is_subsampled(format) ||
176 vk_format_get_plane_count(format) > 1)
177 return false;
178
179 /* TODO: Enable DCC for mipmaps on GFX9+. */
180 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
181 device->physical_device->rad_info.chip_class >= GFX9)
182 return false;
183
184 /* Do not enable DCC for mipmapped arrays because performance is worse. */
185 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
186 return false;
187
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
190 */
191 if (pCreateInfo->samples > 2 ||
192 (pCreateInfo->samples == 2 &&
193 !device->physical_device->dcc_msaa_allowed))
194 return false;
195
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats =
198 radv_is_colorbuffer_format_supported(format,
199 &blendable);
200
201 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
202 const struct VkImageFormatListCreateInfo *format_list =
203 (const struct VkImageFormatListCreateInfo *)
204 vk_find_struct_const(pCreateInfo->pNext,
205 IMAGE_FORMAT_LIST_CREATE_INFO);
206
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list && format_list->viewFormatCount) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
212 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
213 continue;
214
215 if (!radv_dcc_formats_compatible(format,
216 format_list->pViewFormats[i]))
217 dcc_compatible_formats = false;
218 }
219 } else {
220 dcc_compatible_formats = false;
221 }
222 }
223
224 if (!dcc_compatible_formats)
225 return false;
226
227 return true;
228 }
229
230 static bool
231 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
232 struct radv_image *image)
233 {
234 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
235 return false;
236
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device->physical_device->rad_info.chip_class < GFX8)
239 return false;
240
241 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
242 return false;
243
244 if (radv_image_has_dcc(image))
245 return false;
246
247 if (!radv_image_has_cmask(image))
248 return false;
249
250 return true;
251 }
252
253 static uint32_t si_get_bo_metadata_word1(const struct radv_device *device)
254 {
255 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
256 }
257
258 static bool
259 radv_is_valid_opaque_metadata(const struct radv_device *device,
260 const struct radeon_bo_metadata *md)
261 {
262 if (md->metadata[0] != 1 ||
263 md->metadata[1] != si_get_bo_metadata_word1(device))
264 return false;
265
266 if (md->size_metadata < 40)
267 return false;
268
269 return true;
270 }
271
272 static void
273 radv_patch_surface_from_metadata(struct radv_device *device,
274 struct radeon_surf *surface,
275 const struct radeon_bo_metadata *md)
276 {
277 surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
278
279 if (device->physical_device->rad_info.chip_class >= GFX9) {
280 if (md->u.gfx9.swizzle_mode > 0)
281 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
282 else
283 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
284
285 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
286 } else {
287 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
288 surface->u.legacy.bankw = md->u.legacy.bankw;
289 surface->u.legacy.bankh = md->u.legacy.bankh;
290 surface->u.legacy.tile_split = md->u.legacy.tile_split;
291 surface->u.legacy.mtilea = md->u.legacy.mtilea;
292 surface->u.legacy.num_banks = md->u.legacy.num_banks;
293
294 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
295 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
296 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
297 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
298 else
299 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
300
301 }
302 }
303
304 static VkResult
305 radv_patch_image_dimensions(struct radv_device *device,
306 struct radv_image *image,
307 const struct radv_image_create_info *create_info,
308 struct ac_surf_info *image_info)
309 {
310 unsigned width = image->info.width;
311 unsigned height = image->info.height;
312
313 /*
314 * minigbm sometimes allocates bigger images which is going to result in
315 * weird strides and other properties. Lets be lenient where possible and
316 * fail it on GFX10 (as we cannot cope there).
317 *
318 * Example hack: https://chromium-review.googlesource.com/c/chromiumos/platform/minigbm/+/1457777/
319 */
320 if (create_info->bo_metadata &&
321 radv_is_valid_opaque_metadata(device, create_info->bo_metadata)) {
322 const struct radeon_bo_metadata *md = create_info->bo_metadata;
323
324 if (device->physical_device->rad_info.chip_class >= GFX10) {
325 width = G_00A004_WIDTH_LO(md->metadata[3]) +
326 (G_00A008_WIDTH_HI(md->metadata[4]) << 2) + 1;
327 height = S_00A008_HEIGHT(md->metadata[4]) + 1;
328 } else {
329 width = G_008F18_WIDTH(md->metadata[4]) + 1;
330 height = G_008F18_HEIGHT(md->metadata[4]) + 1;
331 }
332 }
333
334 if (image->info.width == width && image->info.height == height)
335 return VK_SUCCESS;
336
337 if (width < image->info.width || height < image->info.height) {
338 fprintf(stderr,
339 "The imported image has smaller dimensions than the internal\n"
340 "dimensions. Using it is going to fail badly, so we reject\n"
341 "this import.\n"
342 "(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
343 image->info.width, image->info.height, width, height);
344 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
345 } else if (device->physical_device->rad_info.chip_class >= GFX10) {
346 fprintf(stderr,
347 "Tried to import an image with inconsistent width on GFX10.\n"
348 "As GFX10 has no separate stride fields we cannot cope with\n"
349 "an inconsistency in width and will fail this import.\n"
350 "(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
351 image->info.width, image->info.height, width, height);
352 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
353 } else {
354 fprintf(stderr,
355 "Tried to import an image with inconsistent width on pre-GFX10.\n"
356 "As GFX10 has no separate stride fields we cannot cope with\n"
357 "an inconsistency and would fail on GFX10.\n"
358 "(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
359 image->info.width, image->info.height, width, height);
360 }
361 image_info->width = width;
362 image_info->height = height;
363
364 return VK_SUCCESS;
365 }
366
367 static VkResult
368 radv_patch_image_from_extra_info(struct radv_device *device,
369 struct radv_image *image,
370 const struct radv_image_create_info *create_info,
371 struct ac_surf_info *image_info)
372 {
373 VkResult result = radv_patch_image_dimensions(device, image, create_info, image_info);
374 if (result != VK_SUCCESS)
375 return result;
376
377 for (unsigned plane = 0; plane < image->plane_count; ++plane) {
378 if (create_info->bo_metadata) {
379 radv_patch_surface_from_metadata(device, &image->planes[plane].surface,
380 create_info->bo_metadata);
381 }
382
383 if (radv_surface_has_scanout(device, create_info)) {
384 image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT;
385 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC;
386
387 image->info.surf_index = NULL;
388 }
389 }
390 return VK_SUCCESS;
391 }
392
393 static int
394 radv_init_surface(struct radv_device *device,
395 const struct radv_image *image,
396 struct radeon_surf *surface,
397 unsigned plane_id,
398 const VkImageCreateInfo *pCreateInfo,
399 VkFormat image_format)
400 {
401 unsigned array_mode = radv_choose_tiling(device, pCreateInfo, image_format);
402 VkFormat format = vk_format_get_plane_format(image_format, plane_id);
403 const struct vk_format_description *desc = vk_format_description(format);
404 bool is_depth, is_stencil;
405
406 is_depth = vk_format_has_depth(desc);
407 is_stencil = vk_format_has_stencil(desc);
408
409 surface->blk_w = vk_format_get_blockwidth(format);
410 surface->blk_h = vk_format_get_blockheight(format);
411
412 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
413 /* align byte per element on dword */
414 if (surface->bpe == 3) {
415 surface->bpe = 4;
416 }
417
418 surface->flags = RADEON_SURF_SET(array_mode, MODE);
419
420 switch (pCreateInfo->imageType){
421 case VK_IMAGE_TYPE_1D:
422 if (pCreateInfo->arrayLayers > 1)
423 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
424 else
425 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
426 break;
427 case VK_IMAGE_TYPE_2D:
428 if (pCreateInfo->arrayLayers > 1)
429 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
430 else
431 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
432 break;
433 case VK_IMAGE_TYPE_3D:
434 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
435 break;
436 default:
437 unreachable("unhandled image type");
438 }
439
440 if (is_depth) {
441 surface->flags |= RADEON_SURF_ZBUFFER;
442 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
443 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
444 }
445
446 if (is_stencil)
447 surface->flags |= RADEON_SURF_SBUFFER;
448
449 if (device->physical_device->rad_info.chip_class >= GFX9 &&
450 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
451 vk_format_get_blocksizebits(image_format) == 128 &&
452 vk_format_is_compressed(image_format))
453 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
454
455 if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
456 surface->flags |= RADEON_SURF_DISABLE_DCC;
457
458 return 0;
459 }
460
461 static inline unsigned
462 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
463 {
464 if (stencil)
465 return plane->surface.u.legacy.stencil_tiling_index[level];
466 else
467 return plane->surface.u.legacy.tiling_index[level];
468 }
469
470 static unsigned radv_map_swizzle(unsigned swizzle)
471 {
472 switch (swizzle) {
473 case VK_SWIZZLE_Y:
474 return V_008F0C_SQ_SEL_Y;
475 case VK_SWIZZLE_Z:
476 return V_008F0C_SQ_SEL_Z;
477 case VK_SWIZZLE_W:
478 return V_008F0C_SQ_SEL_W;
479 case VK_SWIZZLE_0:
480 return V_008F0C_SQ_SEL_0;
481 case VK_SWIZZLE_1:
482 return V_008F0C_SQ_SEL_1;
483 default: /* VK_SWIZZLE_X */
484 return V_008F0C_SQ_SEL_X;
485 }
486 }
487
488 static void
489 radv_make_buffer_descriptor(struct radv_device *device,
490 struct radv_buffer *buffer,
491 VkFormat vk_format,
492 unsigned offset,
493 unsigned range,
494 uint32_t *state)
495 {
496 const struct vk_format_description *desc;
497 unsigned stride;
498 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
499 uint64_t va = gpu_address + buffer->offset;
500 unsigned num_format, data_format;
501 int first_non_void;
502 desc = vk_format_description(vk_format);
503 first_non_void = vk_format_get_first_non_void_channel(vk_format);
504 stride = desc->block.bits / 8;
505
506 va += offset;
507 state[0] = va;
508 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
509 S_008F04_STRIDE(stride);
510
511 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
512 range /= stride;
513 }
514
515 state[2] = range;
516 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
517 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
518 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
519 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
520
521 if (device->physical_device->rad_info.chip_class >= GFX10) {
522 const struct gfx10_format *fmt = gfx10_format_description(vk_format);
523
524 /* OOB_SELECT chooses the out-of-bounds check:
525 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
526 * - 1: index >= NUM_RECORDS
527 * - 2: NUM_RECORDS == 0
528 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
529 * else: swizzle_address >= NUM_RECORDS
530 */
531 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
532 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
533 S_008F0C_RESOURCE_LEVEL(1);
534 } else {
535 num_format = radv_translate_buffer_numformat(desc, first_non_void);
536 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
537
538 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
539 assert(num_format != ~0);
540
541 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
542 S_008F0C_DATA_FORMAT(data_format);
543 }
544 }
545
546 static void
547 si_set_mutable_tex_desc_fields(struct radv_device *device,
548 struct radv_image *image,
549 const struct legacy_surf_level *base_level_info,
550 unsigned plane_id,
551 unsigned base_level, unsigned first_level,
552 unsigned block_width, bool is_stencil,
553 bool is_storage_image, bool disable_compression,
554 uint32_t *state)
555 {
556 struct radv_image_plane *plane = &image->planes[plane_id];
557 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
558 uint64_t va = gpu_address + plane->offset;
559 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
560 uint64_t meta_va = 0;
561 if (chip_class >= GFX9) {
562 if (is_stencil)
563 va += plane->surface.u.gfx9.stencil_offset;
564 else
565 va += plane->surface.u.gfx9.surf_offset;
566 } else
567 va += base_level_info->offset;
568
569 state[0] = va >> 8;
570 if (chip_class >= GFX9 ||
571 base_level_info->mode == RADEON_SURF_MODE_2D)
572 state[0] |= plane->surface.tile_swizzle;
573 state[1] &= C_008F14_BASE_ADDRESS_HI;
574 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
575
576 if (chip_class >= GFX8) {
577 state[6] &= C_008F28_COMPRESSION_EN;
578 state[7] = 0;
579 if (!disable_compression && radv_dcc_enabled(image, first_level)) {
580 meta_va = gpu_address + image->dcc_offset;
581 if (chip_class <= GFX8)
582 meta_va += base_level_info->dcc_offset;
583
584 unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
585 dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
586 meta_va |= dcc_tile_swizzle;
587 } else if (!disable_compression &&
588 radv_image_is_tc_compat_htile(image)) {
589 meta_va = gpu_address + image->htile_offset;
590 }
591
592 if (meta_va) {
593 state[6] |= S_008F28_COMPRESSION_EN(1);
594 if (chip_class <= GFX9)
595 state[7] = meta_va >> 8;
596 }
597 }
598
599 if (chip_class >= GFX10) {
600 state[3] &= C_00A00C_SW_MODE;
601
602 if (is_stencil) {
603 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
604 } else {
605 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
606 }
607
608 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
609 C_00A018_META_PIPE_ALIGNED;
610
611 if (meta_va) {
612 struct gfx9_surf_meta_flags meta = {
613 .rb_aligned = 1,
614 .pipe_aligned = 1,
615 };
616
617 if (image->dcc_offset)
618 meta = plane->surface.u.gfx9.dcc;
619
620 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
621 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
622 }
623
624 state[7] = meta_va >> 16;
625 } else if (chip_class == GFX9) {
626 state[3] &= C_008F1C_SW_MODE;
627 state[4] &= C_008F20_PITCH;
628
629 if (is_stencil) {
630 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
631 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
632 } else {
633 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
634 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
635 }
636
637 state[5] &= C_008F24_META_DATA_ADDRESS &
638 C_008F24_META_PIPE_ALIGNED &
639 C_008F24_META_RB_ALIGNED;
640 if (meta_va) {
641 struct gfx9_surf_meta_flags meta = {
642 .rb_aligned = 1,
643 .pipe_aligned = 1,
644 };
645
646 if (image->dcc_offset)
647 meta = plane->surface.u.gfx9.dcc;
648
649 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
650 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
651 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
652 }
653 } else {
654 /* GFX6-GFX8 */
655 unsigned pitch = base_level_info->nblk_x * block_width;
656 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
657
658 state[3] &= C_008F1C_TILING_INDEX;
659 state[3] |= S_008F1C_TILING_INDEX(index);
660 state[4] &= C_008F20_PITCH;
661 state[4] |= S_008F20_PITCH(pitch - 1);
662 }
663 }
664
665 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
666 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
667 {
668 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
669 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
670
671 /* GFX9 allocates 1D textures as 2D. */
672 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
673 image_type = VK_IMAGE_TYPE_2D;
674 switch (image_type) {
675 case VK_IMAGE_TYPE_1D:
676 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
677 case VK_IMAGE_TYPE_2D:
678 if (nr_samples > 1)
679 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
680 else
681 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
682 case VK_IMAGE_TYPE_3D:
683 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
684 return V_008F1C_SQ_RSRC_IMG_3D;
685 else
686 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
687 default:
688 unreachable("illegal image type");
689 }
690 }
691
692 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
693 {
694 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
695
696 if (swizzle[3] == VK_SWIZZLE_X) {
697 /* For the pre-defined border color values (white, opaque
698 * black, transparent black), the only thing that matters is
699 * that the alpha channel winds up in the correct place
700 * (because the RGB channels are all the same) so either of
701 * these enumerations will work.
702 */
703 if (swizzle[2] == VK_SWIZZLE_Y)
704 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
705 else
706 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
707 } else if (swizzle[0] == VK_SWIZZLE_X) {
708 if (swizzle[1] == VK_SWIZZLE_Y)
709 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
710 else
711 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
712 } else if (swizzle[1] == VK_SWIZZLE_X) {
713 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
714 } else if (swizzle[2] == VK_SWIZZLE_X) {
715 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
716 }
717
718 return bc_swizzle;
719 }
720
721 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
722 {
723 const struct vk_format_description *desc = vk_format_description(format);
724
725 if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1)
726 return desc->swizzle[3] == VK_SWIZZLE_X;
727
728 return radv_translate_colorswap(format, false) <= 1;
729 }
730 /**
731 * Build the sampler view descriptor for a texture (GFX10).
732 */
733 static void
734 gfx10_make_texture_descriptor(struct radv_device *device,
735 struct radv_image *image,
736 bool is_storage_image,
737 VkImageViewType view_type,
738 VkFormat vk_format,
739 const VkComponentMapping *mapping,
740 unsigned first_level, unsigned last_level,
741 unsigned first_layer, unsigned last_layer,
742 unsigned width, unsigned height, unsigned depth,
743 uint32_t *state,
744 uint32_t *fmask_state)
745 {
746 const struct vk_format_description *desc;
747 enum vk_swizzle swizzle[4];
748 unsigned img_format;
749 unsigned type;
750
751 desc = vk_format_description(vk_format);
752 img_format = gfx10_format_description(vk_format)->img_format;
753
754 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
755 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
756 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
757 } else {
758 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
759 }
760
761 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
762 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
763 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
764 height = 1;
765 depth = image->info.array_size;
766 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
767 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
768 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
769 depth = image->info.array_size;
770 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
771 depth = image->info.array_size / 6;
772
773 state[0] = 0;
774 state[1] = S_00A004_FORMAT(img_format) |
775 S_00A004_WIDTH_LO(width - 1);
776 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
777 S_00A008_HEIGHT(height - 1) |
778 S_00A008_RESOURCE_LEVEL(1);
779 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
780 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
781 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
782 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
783 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
784 0 : first_level) |
785 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
786 util_logbase2(image->info.samples) :
787 last_level) |
788 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
789 S_00A00C_TYPE(type);
790 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
791 * to know the total number of layers.
792 */
793 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
794 S_00A010_BASE_ARRAY(first_layer);
795 state[5] = S_00A014_ARRAY_PITCH(0) |
796 S_00A014_MAX_MIP(image->info.samples > 1 ?
797 util_logbase2(image->info.samples) :
798 image->info.levels - 1) |
799 S_00A014_PERF_MOD(4);
800 state[6] = 0;
801 state[7] = 0;
802
803 if (radv_dcc_enabled(image, first_level)) {
804 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
805 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
806 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
807 }
808
809 /* Initialize the sampler view for FMASK. */
810 if (radv_image_has_fmask(image)) {
811 uint64_t gpu_address = radv_buffer_get_va(image->bo);
812 uint32_t format;
813 uint64_t va;
814
815 assert(image->plane_count == 1);
816
817 va = gpu_address + image->offset + image->fmask_offset;
818
819 switch (image->info.samples) {
820 case 2:
821 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
822 break;
823 case 4:
824 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
825 break;
826 case 8:
827 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
828 break;
829 default:
830 unreachable("invalid nr_samples");
831 }
832
833 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
834 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
835 S_00A004_FORMAT(format) |
836 S_00A004_WIDTH_LO(width - 1);
837 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
838 S_00A008_HEIGHT(height - 1) |
839 S_00A008_RESOURCE_LEVEL(1);
840 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
841 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
842 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
843 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
844 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
845 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
846 fmask_state[4] = S_00A010_DEPTH(last_layer) |
847 S_00A010_BASE_ARRAY(first_layer);
848 fmask_state[5] = 0;
849 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
850 fmask_state[7] = 0;
851 } else if (fmask_state)
852 memset(fmask_state, 0, 8 * 4);
853 }
854
855 /**
856 * Build the sampler view descriptor for a texture (SI-GFX9)
857 */
858 static void
859 si_make_texture_descriptor(struct radv_device *device,
860 struct radv_image *image,
861 bool is_storage_image,
862 VkImageViewType view_type,
863 VkFormat vk_format,
864 const VkComponentMapping *mapping,
865 unsigned first_level, unsigned last_level,
866 unsigned first_layer, unsigned last_layer,
867 unsigned width, unsigned height, unsigned depth,
868 uint32_t *state,
869 uint32_t *fmask_state)
870 {
871 const struct vk_format_description *desc;
872 enum vk_swizzle swizzle[4];
873 int first_non_void;
874 unsigned num_format, data_format, type;
875
876 desc = vk_format_description(vk_format);
877
878 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
879 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
880 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
881 } else {
882 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
883 }
884
885 first_non_void = vk_format_get_first_non_void_channel(vk_format);
886
887 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
888 if (num_format == ~0) {
889 num_format = 0;
890 }
891
892 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
893 if (data_format == ~0) {
894 data_format = 0;
895 }
896
897 /* S8 with either Z16 or Z32 HTILE need a special format. */
898 if (device->physical_device->rad_info.chip_class == GFX9 &&
899 vk_format == VK_FORMAT_S8_UINT &&
900 radv_image_is_tc_compat_htile(image)) {
901 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
902 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
903 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
904 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
905 }
906 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
907 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
908 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
909 height = 1;
910 depth = image->info.array_size;
911 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
912 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
913 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
914 depth = image->info.array_size;
915 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
916 depth = image->info.array_size / 6;
917
918 state[0] = 0;
919 state[1] = (S_008F14_DATA_FORMAT(data_format) |
920 S_008F14_NUM_FORMAT(num_format));
921 state[2] = (S_008F18_WIDTH(width - 1) |
922 S_008F18_HEIGHT(height - 1) |
923 S_008F18_PERF_MOD(4));
924 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
925 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
926 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
927 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
928 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
929 0 : first_level) |
930 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
931 util_logbase2(image->info.samples) :
932 last_level) |
933 S_008F1C_TYPE(type));
934 state[4] = 0;
935 state[5] = S_008F24_BASE_ARRAY(first_layer);
936 state[6] = 0;
937 state[7] = 0;
938
939 if (device->physical_device->rad_info.chip_class == GFX9) {
940 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
941
942 /* Depth is the last accessible layer on Gfx9.
943 * The hw doesn't need to know the total number of layers.
944 */
945 if (type == V_008F1C_SQ_RSRC_IMG_3D)
946 state[4] |= S_008F20_DEPTH(depth - 1);
947 else
948 state[4] |= S_008F20_DEPTH(last_layer);
949
950 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
951 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
952 util_logbase2(image->info.samples) :
953 image->info.levels - 1);
954 } else {
955 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
956 state[4] |= S_008F20_DEPTH(depth - 1);
957 state[5] |= S_008F24_LAST_ARRAY(last_layer);
958 }
959 if (image->dcc_offset) {
960 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
961 } else {
962 /* The last dword is unused by hw. The shader uses it to clear
963 * bits in the first dword of sampler state.
964 */
965 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
966 if (first_level == last_level)
967 state[7] = C_008F30_MAX_ANISO_RATIO;
968 else
969 state[7] = 0xffffffff;
970 }
971 }
972
973 /* Initialize the sampler view for FMASK. */
974 if (radv_image_has_fmask(image)) {
975 uint32_t fmask_format, num_format;
976 uint64_t gpu_address = radv_buffer_get_va(image->bo);
977 uint64_t va;
978
979 assert(image->plane_count == 1);
980
981 va = gpu_address + image->offset + image->fmask_offset;
982
983 if (device->physical_device->rad_info.chip_class == GFX9) {
984 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
985 switch (image->info.samples) {
986 case 2:
987 num_format = V_008F14_IMG_FMASK_8_2_2;
988 break;
989 case 4:
990 num_format = V_008F14_IMG_FMASK_8_4_4;
991 break;
992 case 8:
993 num_format = V_008F14_IMG_FMASK_32_8_8;
994 break;
995 default:
996 unreachable("invalid nr_samples");
997 }
998 } else {
999 switch (image->info.samples) {
1000 case 2:
1001 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
1002 break;
1003 case 4:
1004 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
1005 break;
1006 case 8:
1007 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
1008 break;
1009 default:
1010 assert(0);
1011 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
1012 }
1013 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
1014 }
1015
1016 fmask_state[0] = va >> 8;
1017 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
1018 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
1019 S_008F14_DATA_FORMAT(fmask_format) |
1020 S_008F14_NUM_FORMAT(num_format);
1021 fmask_state[2] = S_008F18_WIDTH(width - 1) |
1022 S_008F18_HEIGHT(height - 1);
1023 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
1024 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
1025 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
1026 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
1027 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
1028 fmask_state[4] = 0;
1029 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
1030 fmask_state[6] = 0;
1031 fmask_state[7] = 0;
1032
1033 if (device->physical_device->rad_info.chip_class == GFX9) {
1034 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
1035 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
1036 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
1037 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
1038 S_008F24_META_RB_ALIGNED(1);
1039
1040 if (radv_image_is_tc_compat_cmask(image)) {
1041 va = gpu_address + image->offset + image->cmask_offset;
1042
1043 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
1044 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
1045 fmask_state[7] |= va >> 8;
1046 }
1047 } else {
1048 fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
1049 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
1050 S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
1051 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
1052
1053 if (radv_image_is_tc_compat_cmask(image)) {
1054 va = gpu_address + image->offset + image->cmask_offset;
1055
1056 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
1057 fmask_state[7] |= va >> 8;
1058 }
1059 }
1060 } else if (fmask_state)
1061 memset(fmask_state, 0, 8 * 4);
1062 }
1063
1064 static void
1065 radv_make_texture_descriptor(struct radv_device *device,
1066 struct radv_image *image,
1067 bool is_storage_image,
1068 VkImageViewType view_type,
1069 VkFormat vk_format,
1070 const VkComponentMapping *mapping,
1071 unsigned first_level, unsigned last_level,
1072 unsigned first_layer, unsigned last_layer,
1073 unsigned width, unsigned height, unsigned depth,
1074 uint32_t *state,
1075 uint32_t *fmask_state)
1076 {
1077 if (device->physical_device->rad_info.chip_class >= GFX10) {
1078 gfx10_make_texture_descriptor(device, image, is_storage_image,
1079 view_type, vk_format, mapping,
1080 first_level, last_level,
1081 first_layer, last_layer,
1082 width, height, depth,
1083 state, fmask_state);
1084 } else {
1085 si_make_texture_descriptor(device, image, is_storage_image,
1086 view_type, vk_format, mapping,
1087 first_level, last_level,
1088 first_layer, last_layer,
1089 width, height, depth,
1090 state, fmask_state);
1091 }
1092 }
1093
1094 static void
1095 radv_query_opaque_metadata(struct radv_device *device,
1096 struct radv_image *image,
1097 struct radeon_bo_metadata *md)
1098 {
1099 static const VkComponentMapping fixedmapping;
1100 uint32_t desc[8], i;
1101
1102 assert(image->plane_count == 1);
1103
1104 /* Metadata image format format version 1:
1105 * [0] = 1 (metadata format identifier)
1106 * [1] = (VENDOR_ID << 16) | PCI_ID
1107 * [2:9] = image descriptor for the whole resource
1108 * [2] is always 0, because the base address is cleared
1109 * [9] is the DCC offset bits [39:8] from the beginning of
1110 * the buffer
1111 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1112 */
1113 md->metadata[0] = 1; /* metadata image format version 1 */
1114
1115 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1116 md->metadata[1] = si_get_bo_metadata_word1(device);
1117
1118
1119 radv_make_texture_descriptor(device, image, false,
1120 (VkImageViewType)image->type, image->vk_format,
1121 &fixedmapping, 0, image->info.levels - 1, 0,
1122 image->info.array_size - 1,
1123 image->info.width, image->info.height,
1124 image->info.depth,
1125 desc, NULL);
1126
1127 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1128 image->planes[0].surface.blk_w, false, false, false, desc);
1129
1130 /* Clear the base address and set the relative DCC offset. */
1131 desc[0] = 0;
1132 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1133 desc[7] = image->dcc_offset >> 8;
1134
1135 /* Dwords [2:9] contain the image descriptor. */
1136 memcpy(&md->metadata[2], desc, sizeof(desc));
1137
1138 /* Dwords [10:..] contain the mipmap level offsets. */
1139 if (device->physical_device->rad_info.chip_class <= GFX8) {
1140 for (i = 0; i <= image->info.levels - 1; i++)
1141 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1142 md->size_metadata = (11 + image->info.levels - 1) * 4;
1143 } else
1144 md->size_metadata = 10 * 4;
1145 }
1146
1147 void
1148 radv_init_metadata(struct radv_device *device,
1149 struct radv_image *image,
1150 struct radeon_bo_metadata *metadata)
1151 {
1152 struct radeon_surf *surface = &image->planes[0].surface;
1153
1154 memset(metadata, 0, sizeof(*metadata));
1155
1156 if (device->physical_device->rad_info.chip_class >= GFX9) {
1157 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1158 metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1159 } else {
1160 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1161 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1162 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1163 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1164 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1165 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1166 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1167 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1168 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1169 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1170 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1171 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1172 }
1173 radv_query_opaque_metadata(device, image, metadata);
1174 }
1175
1176 void
1177 radv_image_override_offset_stride(struct radv_device *device,
1178 struct radv_image *image,
1179 uint64_t offset, uint32_t stride)
1180 {
1181 ac_surface_override_offset_stride(&device->physical_device->rad_info,
1182 &image->planes[0].surface,
1183 image->info.levels, offset, stride);
1184 }
1185
1186 static void
1187 radv_image_alloc_fmask(struct radv_device *device,
1188 struct radv_image *image)
1189 {
1190 unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
1191
1192 image->fmask_offset = align64(image->size, fmask_alignment);
1193 image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
1194 image->alignment = MAX2(image->alignment, fmask_alignment);
1195 }
1196
1197 static void
1198 radv_image_alloc_cmask(struct radv_device *device,
1199 struct radv_image *image)
1200 {
1201 unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
1202 unsigned cmask_size = image->planes[0].surface.cmask_size;
1203 uint32_t clear_value_size = 0;
1204
1205 if (!cmask_size)
1206 return;
1207
1208 assert(cmask_alignment);
1209
1210 image->cmask_offset = align64(image->size, cmask_alignment);
1211 /* + 8 for storing the clear values */
1212 if (!image->clear_value_offset) {
1213 image->clear_value_offset = image->cmask_offset + cmask_size;
1214 clear_value_size = 8;
1215 }
1216 image->size = image->cmask_offset + cmask_size + clear_value_size;
1217 image->alignment = MAX2(image->alignment, cmask_alignment);
1218 }
1219
1220 static void
1221 radv_image_alloc_dcc(struct radv_image *image)
1222 {
1223 assert(image->plane_count == 1);
1224
1225 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1226 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1227 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1228 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1229 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1230 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1231 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1232 }
1233
1234 static void
1235 radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
1236 {
1237 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1238
1239 /* + 8 for storing the clear values */
1240 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1241 image->size = image->clear_value_offset + image->info.levels * 8;
1242 if (radv_image_is_tc_compat_htile(image) &&
1243 device->physical_device->rad_info.has_tc_compat_zrange_bug) {
1244 /* Metadata for the TC-compatible HTILE hardware bug which
1245 * have to be fixed by updating ZRANGE_PRECISION when doing
1246 * fast depth clears to 0.0f.
1247 */
1248 image->tc_compat_zrange_offset = image->size;
1249 image->size = image->tc_compat_zrange_offset + image->info.levels * 4;
1250 }
1251 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1252 }
1253
1254 static inline bool
1255 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1256 {
1257 if (image->info.samples <= 1 &&
1258 image->info.width * image->info.height <= 512 * 512) {
1259 /* Do not enable CMASK or DCC for small surfaces where the cost
1260 * of the eliminate pass can be higher than the benefit of fast
1261 * clear. RadeonSI does this, but the image threshold is
1262 * different.
1263 */
1264 return false;
1265 }
1266
1267 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1268 (image->exclusive || image->queue_family_mask == 1);
1269 }
1270
1271 static inline bool
1272 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1273 {
1274 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1275 !radv_image_has_dcc(image))
1276 return false;
1277
1278 /* On GFX8, DCC layers can be interleaved and it's currently only
1279 * enabled if slice size is equal to the per slice fast clear size
1280 * because the driver assumes that portions of multiple layers are
1281 * contiguous during fast clears.
1282 */
1283 if (image->info.array_size > 1) {
1284 const struct legacy_surf_level *surf_level =
1285 &image->planes[0].surface.u.legacy.level[0];
1286
1287 assert(device->physical_device->rad_info.chip_class == GFX8);
1288
1289 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1290 return false;
1291 }
1292
1293 return true;
1294 }
1295
1296 static inline bool
1297 radv_image_can_enable_cmask(struct radv_image *image)
1298 {
1299 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1300 /* Do not enable CMASK for non-MSAA images (fast color clear)
1301 * because 128 bit formats are not supported, but FMASK might
1302 * still be used.
1303 */
1304 return false;
1305 }
1306
1307 return radv_image_can_enable_dcc_or_cmask(image) &&
1308 image->info.levels == 1 &&
1309 image->info.depth == 1 &&
1310 !image->planes[0].surface.is_linear;
1311 }
1312
1313 static inline bool
1314 radv_image_can_enable_fmask(struct radv_image *image)
1315 {
1316 return image->info.samples > 1 &&
1317 image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
1318 }
1319
1320 static inline bool
1321 radv_image_can_enable_htile(struct radv_image *image)
1322 {
1323 return radv_image_has_htile(image) &&
1324 image->info.levels == 1 &&
1325 image->info.width * image->info.height >= 8 * 8;
1326 }
1327
1328 static void radv_image_disable_dcc(struct radv_image *image)
1329 {
1330 for (unsigned i = 0; i < image->plane_count; ++i)
1331 image->planes[i].surface.dcc_size = 0;
1332 }
1333
1334 static void radv_image_disable_htile(struct radv_image *image)
1335 {
1336 for (unsigned i = 0; i < image->plane_count; ++i)
1337 image->planes[i].surface.htile_size = 0;
1338 }
1339
1340 VkResult
1341 radv_image_create_layout(struct radv_device *device,
1342 struct radv_image_create_info create_info,
1343 struct radv_image *image)
1344 {
1345 /* Check that we did not initialize things earlier */
1346 assert(!image->planes[0].surface.surf_size);
1347
1348 /* Clear the pCreateInfo pointer so we catch issues in the delayed case when we test in the
1349 * common internal case. */
1350 create_info.vk_info = NULL;
1351
1352 struct ac_surf_info image_info = image->info;
1353 VkResult result = radv_patch_image_from_extra_info(device, image, &create_info, &image_info);
1354 if (result != VK_SUCCESS)
1355 return result;
1356
1357 image->size = 0;
1358 image->alignment = 1;
1359 for (unsigned plane = 0; plane < image->plane_count; ++plane) {
1360 struct ac_surf_info info = image_info;
1361
1362 if (plane) {
1363 const struct vk_format_description *desc = vk_format_description(image->vk_format);
1364 assert(info.width % desc->width_divisor == 0);
1365 assert(info.height % desc->height_divisor == 0);
1366
1367 info.width /= desc->width_divisor;
1368 info.height /= desc->height_divisor;
1369 }
1370
1371 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1372
1373 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1374 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1375 image->alignment = image->planes[plane].surface.surf_alignment;
1376
1377 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1378 }
1379
1380 if (!create_info.no_metadata_planes) {
1381 /* Try to enable DCC first. */
1382 if (radv_image_can_enable_dcc(device, image)) {
1383 radv_image_alloc_dcc(image);
1384 if (image->info.samples > 1) {
1385 /* CMASK should be enabled because DCC fast
1386 * clear with MSAA needs it.
1387 */
1388 assert(radv_image_can_enable_cmask(image));
1389 radv_image_alloc_cmask(device, image);
1390 }
1391 } else {
1392 /* When DCC cannot be enabled, try CMASK. */
1393 radv_image_disable_dcc(image);
1394 if (radv_image_can_enable_cmask(image)) {
1395 radv_image_alloc_cmask(device, image);
1396 }
1397 }
1398
1399 /* Try to enable FMASK for multisampled images. */
1400 if (radv_image_can_enable_fmask(image)) {
1401 radv_image_alloc_fmask(device, image);
1402
1403 if (radv_use_tc_compat_cmask_for_image(device, image))
1404 image->tc_compatible_cmask = true;
1405 } else {
1406 /* Otherwise, try to enable HTILE for depth surfaces. */
1407 if (radv_image_can_enable_htile(image) &&
1408 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1409 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1410 radv_image_alloc_htile(device, image);
1411 } else {
1412 radv_image_disable_htile(image);
1413 }
1414 }
1415 } else {
1416 radv_image_disable_dcc(image);
1417 radv_image_disable_htile(image);
1418 }
1419
1420 assert(image->planes[0].surface.surf_size);
1421 return VK_SUCCESS;
1422 }
1423
1424 VkResult
1425 radv_image_create(VkDevice _device,
1426 const struct radv_image_create_info *create_info,
1427 const VkAllocationCallbacks* alloc,
1428 VkImage *pImage)
1429 {
1430 RADV_FROM_HANDLE(radv_device, device, _device);
1431 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1432 struct radv_image *image = NULL;
1433 VkFormat format = radv_select_android_external_format(pCreateInfo->pNext,
1434 pCreateInfo->format);
1435 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1436
1437 const unsigned plane_count = vk_format_get_plane_count(format);
1438 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1439
1440 radv_assert(pCreateInfo->mipLevels > 0);
1441 radv_assert(pCreateInfo->arrayLayers > 0);
1442 radv_assert(pCreateInfo->samples > 0);
1443 radv_assert(pCreateInfo->extent.width > 0);
1444 radv_assert(pCreateInfo->extent.height > 0);
1445 radv_assert(pCreateInfo->extent.depth > 0);
1446
1447 image = vk_zalloc2(&device->vk.alloc, alloc, image_struct_size, 8,
1448 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1449 if (!image)
1450 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1451
1452 image->type = pCreateInfo->imageType;
1453 image->info.width = pCreateInfo->extent.width;
1454 image->info.height = pCreateInfo->extent.height;
1455 image->info.depth = pCreateInfo->extent.depth;
1456 image->info.samples = pCreateInfo->samples;
1457 image->info.storage_samples = pCreateInfo->samples;
1458 image->info.array_size = pCreateInfo->arrayLayers;
1459 image->info.levels = pCreateInfo->mipLevels;
1460 image->info.num_channels = vk_format_get_nr_components(format);
1461
1462 image->vk_format = format;
1463 image->tiling = pCreateInfo->tiling;
1464 image->usage = pCreateInfo->usage;
1465 image->flags = pCreateInfo->flags;
1466 image->plane_count = plane_count;
1467
1468 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1469 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1470 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1471 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1472 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1473 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1474 else
1475 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1476 }
1477
1478 const VkExternalMemoryImageCreateInfo *external_info =
1479 vk_find_struct_const(pCreateInfo->pNext,
1480 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) ;
1481
1482 image->shareable = external_info;
1483 if (!vk_format_is_depth_or_stencil(format) && !image->shareable) {
1484 image->info.surf_index = &device->image_mrt_offset_counter;
1485 }
1486
1487 for (unsigned plane = 0; plane < image->plane_count; ++plane) {
1488 radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
1489 }
1490
1491 bool delay_layout = external_info &&
1492 (external_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID);
1493
1494 if (delay_layout) {
1495 *pImage = radv_image_to_handle(image);
1496 assert (!(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT));
1497 return VK_SUCCESS;
1498 }
1499
1500 ASSERTED VkResult result = radv_image_create_layout(device, *create_info, image);
1501 assert(result == VK_SUCCESS);
1502
1503 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1504 image->alignment = MAX2(image->alignment, 4096);
1505 image->size = align64(image->size, image->alignment);
1506 image->offset = 0;
1507
1508 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1509 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1510 if (!image->bo) {
1511 vk_free2(&device->vk.alloc, alloc, image);
1512 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1513 }
1514 }
1515
1516 *pImage = radv_image_to_handle(image);
1517
1518 return VK_SUCCESS;
1519 }
1520
1521 static void
1522 radv_image_view_make_descriptor(struct radv_image_view *iview,
1523 struct radv_device *device,
1524 VkFormat vk_format,
1525 const VkComponentMapping *components,
1526 bool is_storage_image, bool disable_compression,
1527 unsigned plane_id, unsigned descriptor_plane_id)
1528 {
1529 struct radv_image *image = iview->image;
1530 struct radv_image_plane *plane = &image->planes[plane_id];
1531 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1532 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1533 uint32_t blk_w;
1534 union radv_descriptor *descriptor;
1535 uint32_t hw_level = 0;
1536
1537 if (is_storage_image) {
1538 descriptor = &iview->storage_descriptor;
1539 } else {
1540 descriptor = &iview->descriptor;
1541 }
1542
1543 assert(vk_format_get_plane_count(vk_format) == 1);
1544 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1545 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1546
1547 if (device->physical_device->rad_info.chip_class >= GFX9)
1548 hw_level = iview->base_mip;
1549 radv_make_texture_descriptor(device, image, is_storage_image,
1550 iview->type,
1551 vk_format,
1552 components,
1553 hw_level, hw_level + iview->level_count - 1,
1554 iview->base_layer,
1555 iview->base_layer + iview->layer_count - 1,
1556 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1557 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1558 iview->extent.depth,
1559 descriptor->plane_descriptors[descriptor_plane_id],
1560 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1561
1562 const struct legacy_surf_level *base_level_info = NULL;
1563 if (device->physical_device->rad_info.chip_class <= GFX9) {
1564 if (is_stencil)
1565 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1566 else
1567 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1568 }
1569 si_set_mutable_tex_desc_fields(device, image,
1570 base_level_info,
1571 plane_id,
1572 iview->base_mip,
1573 iview->base_mip,
1574 blk_w, is_stencil, is_storage_image,
1575 is_storage_image || disable_compression,
1576 descriptor->plane_descriptors[descriptor_plane_id]);
1577 }
1578
1579 static unsigned
1580 radv_plane_from_aspect(VkImageAspectFlags mask)
1581 {
1582 switch(mask) {
1583 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1584 return 1;
1585 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1586 return 2;
1587 default:
1588 return 0;
1589 }
1590 }
1591
1592 VkFormat
1593 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1594 {
1595 switch(mask) {
1596 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1597 return image->planes[0].format;
1598 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1599 return image->planes[1].format;
1600 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1601 return image->planes[2].format;
1602 case VK_IMAGE_ASPECT_STENCIL_BIT:
1603 return vk_format_stencil_only(image->vk_format);
1604 case VK_IMAGE_ASPECT_DEPTH_BIT:
1605 return vk_format_depth_only(image->vk_format);
1606 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1607 return vk_format_depth_only(image->vk_format);
1608 default:
1609 return image->vk_format;
1610 }
1611 }
1612
1613 void
1614 radv_image_view_init(struct radv_image_view *iview,
1615 struct radv_device *device,
1616 const VkImageViewCreateInfo* pCreateInfo,
1617 const struct radv_image_view_extra_create_info* extra_create_info)
1618 {
1619 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1620 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1621
1622 switch (image->type) {
1623 case VK_IMAGE_TYPE_1D:
1624 case VK_IMAGE_TYPE_2D:
1625 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1626 break;
1627 case VK_IMAGE_TYPE_3D:
1628 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1629 <= radv_minify(image->info.depth, range->baseMipLevel));
1630 break;
1631 default:
1632 unreachable("bad VkImageType");
1633 }
1634 iview->image = image;
1635 iview->bo = image->bo;
1636 iview->type = pCreateInfo->viewType;
1637 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1638 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1639 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1640
1641 iview->vk_format = pCreateInfo->format;
1642
1643 /* If the image has an Android external format, pCreateInfo->format will be
1644 * VK_FORMAT_UNDEFINED. */
1645 if (iview->vk_format == VK_FORMAT_UNDEFINED)
1646 iview->vk_format = image->vk_format;
1647
1648 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1649 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1650 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1651 iview->vk_format = vk_format_depth_only(iview->vk_format);
1652 }
1653
1654 if (device->physical_device->rad_info.chip_class >= GFX9) {
1655 iview->extent = (VkExtent3D) {
1656 .width = image->info.width,
1657 .height = image->info.height,
1658 .depth = image->info.depth,
1659 };
1660 } else {
1661 iview->extent = (VkExtent3D) {
1662 .width = radv_minify(image->info.width , range->baseMipLevel),
1663 .height = radv_minify(image->info.height, range->baseMipLevel),
1664 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1665 };
1666 }
1667
1668 if (iview->vk_format != image->planes[iview->plane_id].format) {
1669 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1670 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1671 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1672 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1673
1674 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1675 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1676
1677 /* Comment ported from amdvlk -
1678 * If we have the following image:
1679 * Uncompressed pixels Compressed block sizes (4x4)
1680 * mip0: 22 x 22 6 x 6
1681 * mip1: 11 x 11 3 x 3
1682 * mip2: 5 x 5 2 x 2
1683 * mip3: 2 x 2 1 x 1
1684 * mip4: 1 x 1 1 x 1
1685 *
1686 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1687 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1688 * divide-by-two integer math):
1689 * mip0: 6x6
1690 * mip1: 3x3
1691 * mip2: 1x1
1692 * mip3: 1x1
1693 *
1694 * This means that mip2 will be missing texels.
1695 *
1696 * Fix this by calculating the base mip's width and height, then convert that, and round it
1697 * back up to get the level 0 size.
1698 * Clamp the converted size between the original values, and next power of two, which
1699 * means we don't oversize the image.
1700 */
1701 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1702 vk_format_is_compressed(image->vk_format) &&
1703 !vk_format_is_compressed(iview->vk_format)) {
1704 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1705 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1706
1707 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1708 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1709
1710 lvl_width <<= range->baseMipLevel;
1711 lvl_height <<= range->baseMipLevel;
1712
1713 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1714 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1715 }
1716 }
1717
1718 iview->base_layer = range->baseArrayLayer;
1719 iview->layer_count = radv_get_layerCount(image, range);
1720 iview->base_mip = range->baseMipLevel;
1721 iview->level_count = radv_get_levelCount(image, range);
1722
1723 bool disable_compression = extra_create_info ? extra_create_info->disable_compression: false;
1724 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1725 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1726 radv_image_view_make_descriptor(iview, device, format,
1727 &pCreateInfo->components,
1728 false, disable_compression,
1729 iview->plane_id + i, i);
1730 radv_image_view_make_descriptor(iview, device,
1731 format, &pCreateInfo->components,
1732 true, disable_compression,
1733 iview->plane_id + i, i);
1734 }
1735 }
1736
1737 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1738 VkImageLayout layout,
1739 bool in_render_loop,
1740 unsigned queue_mask)
1741 {
1742 if (radv_image_is_tc_compat_htile(image)) {
1743 if (layout == VK_IMAGE_LAYOUT_GENERAL &&
1744 !in_render_loop &&
1745 !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
1746 /* It should be safe to enable TC-compat HTILE with
1747 * VK_IMAGE_LAYOUT_GENERAL if we are not in a render
1748 * loop and if the image doesn't have the storage bit
1749 * set. This improves performance for apps that use
1750 * GENERAL for the main depth pass because this allows
1751 * compression and this reduces the number of
1752 * decompressions from/to GENERAL.
1753 */
1754 return true;
1755 }
1756
1757 return layout != VK_IMAGE_LAYOUT_GENERAL;
1758 }
1759
1760 return radv_image_has_htile(image) &&
1761 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1762 layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
1763 layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
1764 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1765 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1766 }
1767
1768 bool radv_layout_can_fast_clear(const struct radv_image *image,
1769 VkImageLayout layout,
1770 bool in_render_loop,
1771 unsigned queue_mask)
1772 {
1773 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1774 }
1775
1776 bool radv_layout_dcc_compressed(const struct radv_device *device,
1777 const struct radv_image *image,
1778 VkImageLayout layout,
1779 bool in_render_loop,
1780 unsigned queue_mask)
1781 {
1782 /* Don't compress compute transfer dst, as image stores are not supported. */
1783 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1784 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1785 return false;
1786
1787 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1788 }
1789
1790
1791 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1792 {
1793 if (!image->exclusive)
1794 return image->queue_family_mask;
1795 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1796 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1797 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1798 if (family == VK_QUEUE_FAMILY_IGNORED)
1799 return 1u << queue_family;
1800 return 1u << family;
1801 }
1802
1803 VkResult
1804 radv_CreateImage(VkDevice device,
1805 const VkImageCreateInfo *pCreateInfo,
1806 const VkAllocationCallbacks *pAllocator,
1807 VkImage *pImage)
1808 {
1809 #ifdef ANDROID
1810 const VkNativeBufferANDROID *gralloc_info =
1811 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1812
1813 if (gralloc_info)
1814 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1815 pAllocator, pImage);
1816 #endif
1817
1818 const struct wsi_image_create_info *wsi_info =
1819 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1820 bool scanout = wsi_info && wsi_info->scanout;
1821
1822 return radv_image_create(device,
1823 &(struct radv_image_create_info) {
1824 .vk_info = pCreateInfo,
1825 .scanout = scanout,
1826 },
1827 pAllocator,
1828 pImage);
1829 }
1830
1831 void
1832 radv_DestroyImage(VkDevice _device, VkImage _image,
1833 const VkAllocationCallbacks *pAllocator)
1834 {
1835 RADV_FROM_HANDLE(radv_device, device, _device);
1836 RADV_FROM_HANDLE(radv_image, image, _image);
1837
1838 if (!image)
1839 return;
1840
1841 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1842 device->ws->buffer_destroy(image->bo);
1843
1844 if (image->owned_memory != VK_NULL_HANDLE)
1845 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1846
1847 vk_free2(&device->vk.alloc, pAllocator, image);
1848 }
1849
1850 void radv_GetImageSubresourceLayout(
1851 VkDevice _device,
1852 VkImage _image,
1853 const VkImageSubresource* pSubresource,
1854 VkSubresourceLayout* pLayout)
1855 {
1856 RADV_FROM_HANDLE(radv_image, image, _image);
1857 RADV_FROM_HANDLE(radv_device, device, _device);
1858 int level = pSubresource->mipLevel;
1859 int layer = pSubresource->arrayLayer;
1860
1861 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1862
1863 struct radv_image_plane *plane = &image->planes[plane_id];
1864 struct radeon_surf *surface = &plane->surface;
1865
1866 if (device->physical_device->rad_info.chip_class >= GFX9) {
1867 uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0;
1868
1869 pLayout->offset = plane->offset + level_offset + surface->u.gfx9.surf_slice_size * layer;
1870 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1871 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1872 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1873 /* Adjust the number of bytes between each row because
1874 * the pitch is actually the number of components per
1875 * row.
1876 */
1877 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1878 } else {
1879 uint32_t pitch = surface->is_linear ? surface->u.gfx9.pitch[level] : surface->u.gfx9.surf_pitch;
1880
1881 assert(util_is_power_of_two_nonzero(surface->bpe));
1882 pLayout->rowPitch = pitch * surface->bpe;
1883 }
1884
1885 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1886 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1887 pLayout->size = surface->u.gfx9.surf_slice_size;
1888 if (image->type == VK_IMAGE_TYPE_3D)
1889 pLayout->size *= u_minify(image->info.depth, level);
1890 } else {
1891 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1892 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1893 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1894 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1895 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1896 if (image->type == VK_IMAGE_TYPE_3D)
1897 pLayout->size *= u_minify(image->info.depth, level);
1898 }
1899 }
1900
1901
1902 VkResult
1903 radv_CreateImageView(VkDevice _device,
1904 const VkImageViewCreateInfo *pCreateInfo,
1905 const VkAllocationCallbacks *pAllocator,
1906 VkImageView *pView)
1907 {
1908 RADV_FROM_HANDLE(radv_device, device, _device);
1909 struct radv_image_view *view;
1910
1911 view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
1912 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1913 if (view == NULL)
1914 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1915
1916 radv_image_view_init(view, device, pCreateInfo, NULL);
1917
1918 *pView = radv_image_view_to_handle(view);
1919
1920 return VK_SUCCESS;
1921 }
1922
1923 void
1924 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1925 const VkAllocationCallbacks *pAllocator)
1926 {
1927 RADV_FROM_HANDLE(radv_device, device, _device);
1928 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1929
1930 if (!iview)
1931 return;
1932 vk_free2(&device->vk.alloc, pAllocator, iview);
1933 }
1934
1935 void radv_buffer_view_init(struct radv_buffer_view *view,
1936 struct radv_device *device,
1937 const VkBufferViewCreateInfo* pCreateInfo)
1938 {
1939 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1940
1941 view->bo = buffer->bo;
1942 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1943 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1944 view->vk_format = pCreateInfo->format;
1945
1946 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1947 pCreateInfo->offset, view->range, view->state);
1948 }
1949
1950 VkResult
1951 radv_CreateBufferView(VkDevice _device,
1952 const VkBufferViewCreateInfo *pCreateInfo,
1953 const VkAllocationCallbacks *pAllocator,
1954 VkBufferView *pView)
1955 {
1956 RADV_FROM_HANDLE(radv_device, device, _device);
1957 struct radv_buffer_view *view;
1958
1959 view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
1960 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1961 if (!view)
1962 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1963
1964 radv_buffer_view_init(view, device, pCreateInfo);
1965
1966 *pView = radv_buffer_view_to_handle(view);
1967
1968 return VK_SUCCESS;
1969 }
1970
1971 void
1972 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1973 const VkAllocationCallbacks *pAllocator)
1974 {
1975 RADV_FROM_HANDLE(radv_device, device, _device);
1976 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1977
1978 if (!view)
1979 return;
1980
1981 vk_free2(&device->vk.alloc, pAllocator, view);
1982 }