2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
115 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
127 radv_surface_has_scanout(struct radv_device
*device
, const struct radv_image_create_info
*info
)
132 if (!info
->bo_metadata
)
135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
136 return info
->bo_metadata
->u
.gfx9
.swizzle_mode
== 0 || info
->bo_metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
138 return info
->bo_metadata
->u
.legacy
.scanout
;
143 radv_use_dcc_for_image(struct radv_device
*device
,
144 const struct radv_image
*image
,
145 const struct radv_image_create_info
*create_info
,
146 const VkImageCreateInfo
*pCreateInfo
)
148 bool dcc_compatible_formats
;
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
155 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
158 if (image
->shareable
)
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
163 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
166 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
169 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
170 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if (pCreateInfo
->mipLevels
> 1 &&
175 device
->physical_device
->rad_info
.chip_class
>= GFX9
)
178 /* TODO: Enable DCC for array layers. */
179 if (pCreateInfo
->arrayLayers
> 1)
182 /* Do not enable DCC for mipmapped arrays because performance is worse. */
183 if (pCreateInfo
->arrayLayers
> 1 && pCreateInfo
->mipLevels
> 1)
186 if (radv_surface_has_scanout(device
, create_info
))
189 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
190 * 2x can be enabled with an option.
192 if (pCreateInfo
->samples
> 2 ||
193 (pCreateInfo
->samples
== 2 &&
194 !device
->physical_device
->dcc_msaa_allowed
))
197 /* Determine if the formats are DCC compatible. */
198 dcc_compatible_formats
=
199 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
202 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
203 const struct VkImageFormatListCreateInfoKHR
*format_list
=
204 (const struct VkImageFormatListCreateInfoKHR
*)
205 vk_find_struct_const(pCreateInfo
->pNext
,
206 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
208 /* We have to ignore the existence of the list if viewFormatCount = 0 */
209 if (format_list
&& format_list
->viewFormatCount
) {
210 /* compatibility is transitive, so we only need to check
211 * one format with everything else. */
212 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
213 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
216 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
217 format_list
->pViewFormats
[i
]))
218 dcc_compatible_formats
= false;
221 dcc_compatible_formats
= false;
225 if (!dcc_compatible_formats
)
232 radv_use_tc_compat_cmask_for_image(struct radv_device
*device
,
233 struct radv_image
*image
)
235 if (!(device
->instance
->perftest_flags
& RADV_PERFTEST_TC_COMPAT_CMASK
))
238 /* TC-compat CMASK is only available for GFX8+. */
239 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
242 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
245 if (radv_image_has_dcc(image
))
248 if (!radv_image_has_cmask(image
))
255 radv_prefill_surface_from_metadata(struct radv_device
*device
,
256 struct radeon_surf
*surface
,
257 const struct radv_image_create_info
*create_info
)
259 const struct radeon_bo_metadata
*md
= create_info
->bo_metadata
;
260 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
261 if (md
->u
.gfx9
.swizzle_mode
> 0)
262 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
264 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
266 surface
->u
.gfx9
.surf
.swizzle_mode
= md
->u
.gfx9
.swizzle_mode
;
268 surface
->u
.legacy
.pipe_config
= md
->u
.legacy
.pipe_config
;
269 surface
->u
.legacy
.bankw
= md
->u
.legacy
.bankw
;
270 surface
->u
.legacy
.bankh
= md
->u
.legacy
.bankh
;
271 surface
->u
.legacy
.tile_split
= md
->u
.legacy
.tile_split
;
272 surface
->u
.legacy
.mtilea
= md
->u
.legacy
.mtilea
;
273 surface
->u
.legacy
.num_banks
= md
->u
.legacy
.num_banks
;
275 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
276 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
277 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
278 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
280 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
286 radv_init_surface(struct radv_device
*device
,
287 const struct radv_image
*image
,
288 struct radeon_surf
*surface
,
290 const struct radv_image_create_info
*create_info
)
292 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
293 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
294 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
295 const struct vk_format_description
*desc
= vk_format_description(format
);
296 bool is_depth
, is_stencil
;
298 is_depth
= vk_format_has_depth(desc
);
299 is_stencil
= vk_format_has_stencil(desc
);
301 surface
->blk_w
= vk_format_get_blockwidth(format
);
302 surface
->blk_h
= vk_format_get_blockheight(format
);
304 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
305 /* align byte per element on dword */
306 if (surface
->bpe
== 3) {
309 if (create_info
->bo_metadata
) {
310 radv_prefill_surface_from_metadata(device
, surface
, create_info
);
312 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
315 switch (pCreateInfo
->imageType
){
316 case VK_IMAGE_TYPE_1D
:
317 if (pCreateInfo
->arrayLayers
> 1)
318 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
320 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
322 case VK_IMAGE_TYPE_2D
:
323 if (pCreateInfo
->arrayLayers
> 1)
324 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
326 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
328 case VK_IMAGE_TYPE_3D
:
329 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
332 unreachable("unhandled image type");
336 surface
->flags
|= RADEON_SURF_ZBUFFER
;
337 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
338 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
342 surface
->flags
|= RADEON_SURF_SBUFFER
;
344 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
345 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
346 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
347 vk_format_is_compressed(pCreateInfo
->format
))
348 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
350 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
352 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
353 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
355 if (radv_surface_has_scanout(device
, create_info
))
356 surface
->flags
|= RADEON_SURF_SCANOUT
;
361 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
363 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
366 static inline unsigned
367 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
370 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
372 return plane
->surface
.u
.legacy
.tiling_index
[level
];
375 static unsigned radv_map_swizzle(unsigned swizzle
)
379 return V_008F0C_SQ_SEL_Y
;
381 return V_008F0C_SQ_SEL_Z
;
383 return V_008F0C_SQ_SEL_W
;
385 return V_008F0C_SQ_SEL_0
;
387 return V_008F0C_SQ_SEL_1
;
388 default: /* VK_SWIZZLE_X */
389 return V_008F0C_SQ_SEL_X
;
394 radv_make_buffer_descriptor(struct radv_device
*device
,
395 struct radv_buffer
*buffer
,
401 const struct vk_format_description
*desc
;
403 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
404 uint64_t va
= gpu_address
+ buffer
->offset
;
405 unsigned num_format
, data_format
;
407 desc
= vk_format_description(vk_format
);
408 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
409 stride
= desc
->block
.bits
/ 8;
411 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
412 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
414 assert(data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
);
415 assert(num_format
!= ~0);
419 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
420 S_008F04_STRIDE(stride
);
422 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
427 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
428 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
429 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
430 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
431 S_008F0C_NUM_FORMAT(num_format
) |
432 S_008F0C_DATA_FORMAT(data_format
);
436 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
437 struct radv_image
*image
,
438 const struct legacy_surf_level
*base_level_info
,
440 unsigned base_level
, unsigned first_level
,
441 unsigned block_width
, bool is_stencil
,
442 bool is_storage_image
, uint32_t *state
)
444 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
445 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
446 uint64_t va
= gpu_address
+ plane
->offset
;
447 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
448 uint64_t meta_va
= 0;
449 if (chip_class
>= GFX9
) {
451 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
453 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
455 va
+= base_level_info
->offset
;
458 if (chip_class
>= GFX9
||
459 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
460 state
[0] |= plane
->surface
.tile_swizzle
;
461 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
462 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
464 if (chip_class
>= GFX8
) {
465 state
[6] &= C_008F28_COMPRESSION_EN
;
467 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
468 meta_va
= gpu_address
+ image
->dcc_offset
;
469 if (chip_class
<= GFX8
)
470 meta_va
+= base_level_info
->dcc_offset
;
471 } else if (!is_storage_image
&&
472 radv_image_is_tc_compat_htile(image
)) {
473 meta_va
= gpu_address
+ image
->htile_offset
;
477 state
[6] |= S_008F28_COMPRESSION_EN(1);
478 state
[7] = meta_va
>> 8;
479 state
[7] |= plane
->surface
.tile_swizzle
;
483 if (chip_class
>= GFX9
) {
484 state
[3] &= C_008F1C_SW_MODE
;
485 state
[4] &= C_008F20_PITCH
;
488 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
489 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
491 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
492 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
495 state
[5] &= C_008F24_META_DATA_ADDRESS
&
496 C_008F24_META_PIPE_ALIGNED
&
497 C_008F24_META_RB_ALIGNED
;
499 struct gfx9_surf_meta_flags meta
;
501 if (image
->dcc_offset
)
502 meta
= plane
->surface
.u
.gfx9
.dcc
;
504 meta
= plane
->surface
.u
.gfx9
.htile
;
506 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
507 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
508 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
512 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
513 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
515 state
[3] &= C_008F1C_TILING_INDEX
;
516 state
[3] |= S_008F1C_TILING_INDEX(index
);
517 state
[4] &= C_008F20_PITCH
;
518 state
[4] |= S_008F20_PITCH(pitch
- 1);
522 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
523 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
525 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
526 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
528 /* GFX9 allocates 1D textures as 2D. */
529 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
530 image_type
= VK_IMAGE_TYPE_2D
;
531 switch (image_type
) {
532 case VK_IMAGE_TYPE_1D
:
533 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
534 case VK_IMAGE_TYPE_2D
:
536 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
538 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
539 case VK_IMAGE_TYPE_3D
:
540 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
541 return V_008F1C_SQ_RSRC_IMG_3D
;
543 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
545 unreachable("illegal image type");
549 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
551 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
553 if (swizzle
[3] == VK_SWIZZLE_X
) {
554 /* For the pre-defined border color values (white, opaque
555 * black, transparent black), the only thing that matters is
556 * that the alpha channel winds up in the correct place
557 * (because the RGB channels are all the same) so either of
558 * these enumerations will work.
560 if (swizzle
[2] == VK_SWIZZLE_Y
)
561 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
563 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
564 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
565 if (swizzle
[1] == VK_SWIZZLE_Y
)
566 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
568 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
569 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
570 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
571 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
572 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
579 * Build the sampler view descriptor for a texture.
582 si_make_texture_descriptor(struct radv_device
*device
,
583 struct radv_image
*image
,
584 bool is_storage_image
,
585 VkImageViewType view_type
,
587 const VkComponentMapping
*mapping
,
588 unsigned first_level
, unsigned last_level
,
589 unsigned first_layer
, unsigned last_layer
,
590 unsigned width
, unsigned height
, unsigned depth
,
592 uint32_t *fmask_state
)
594 const struct vk_format_description
*desc
;
595 enum vk_swizzle swizzle
[4];
597 unsigned num_format
, data_format
, type
;
599 desc
= vk_format_description(vk_format
);
601 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
602 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
603 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
605 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
608 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
610 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
611 if (num_format
== ~0) {
615 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
616 if (data_format
== ~0) {
620 /* S8 with either Z16 or Z32 HTILE need a special format. */
621 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
622 vk_format
== VK_FORMAT_S8_UINT
&&
623 radv_image_is_tc_compat_htile(image
)) {
624 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
625 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
626 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
627 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
629 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
630 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
631 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
633 depth
= image
->info
.array_size
;
634 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
635 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
636 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
637 depth
= image
->info
.array_size
;
638 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
639 depth
= image
->info
.array_size
/ 6;
642 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
643 S_008F14_NUM_FORMAT(num_format
));
644 state
[2] = (S_008F18_WIDTH(width
- 1) |
645 S_008F18_HEIGHT(height
- 1) |
646 S_008F18_PERF_MOD(4));
647 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
648 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
649 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
650 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
651 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
653 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
654 util_logbase2(image
->info
.samples
) :
656 S_008F1C_TYPE(type
));
658 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
662 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
663 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
665 /* Depth is the last accessible layer on Gfx9.
666 * The hw doesn't need to know the total number of layers.
668 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
669 state
[4] |= S_008F20_DEPTH(depth
- 1);
671 state
[4] |= S_008F20_DEPTH(last_layer
);
673 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
674 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
675 util_logbase2(image
->info
.samples
) :
676 image
->info
.levels
- 1);
678 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
679 state
[4] |= S_008F20_DEPTH(depth
- 1);
680 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
682 if (image
->dcc_offset
) {
683 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
685 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
687 /* The last dword is unused by hw. The shader uses it to clear
688 * bits in the first dword of sampler state.
690 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
691 if (first_level
== last_level
)
692 state
[7] = C_008F30_MAX_ANISO_RATIO
;
694 state
[7] = 0xffffffff;
698 /* Initialize the sampler view for FMASK. */
699 if (radv_image_has_fmask(image
)) {
700 uint32_t fmask_format
, num_format
;
701 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
704 assert(image
->plane_count
== 1);
706 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
708 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
709 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
710 switch (image
->info
.samples
) {
712 num_format
= V_008F14_IMG_FMASK_8_2_2
;
715 num_format
= V_008F14_IMG_FMASK_8_4_4
;
718 num_format
= V_008F14_IMG_FMASK_32_8_8
;
721 unreachable("invalid nr_samples");
724 switch (image
->info
.samples
) {
726 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
729 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
732 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
736 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
738 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
741 fmask_state
[0] = va
>> 8;
742 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
743 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
744 S_008F14_DATA_FORMAT(fmask_format
) |
745 S_008F14_NUM_FORMAT(num_format
);
746 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
747 S_008F18_HEIGHT(height
- 1);
748 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
749 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
750 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
751 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
752 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
754 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
758 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
759 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
760 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
761 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
762 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
763 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
765 if (radv_image_is_tc_compat_cmask(image
)) {
766 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
768 fmask_state
[5] |= S_008F24_META_DATA_ADDRESS(va
>> 40);
769 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
770 fmask_state
[7] |= va
>> 8;
773 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
774 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
775 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
776 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
778 if (radv_image_is_tc_compat_cmask(image
)) {
779 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
781 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
782 fmask_state
[7] |= va
>> 8;
785 } else if (fmask_state
)
786 memset(fmask_state
, 0, 8 * 4);
790 radv_query_opaque_metadata(struct radv_device
*device
,
791 struct radv_image
*image
,
792 struct radeon_bo_metadata
*md
)
794 static const VkComponentMapping fixedmapping
;
797 assert(image
->plane_count
== 1);
799 /* Metadata image format format version 1:
800 * [0] = 1 (metadata format identifier)
801 * [1] = (VENDOR_ID << 16) | PCI_ID
802 * [2:9] = image descriptor for the whole resource
803 * [2] is always 0, because the base address is cleared
804 * [9] is the DCC offset bits [39:8] from the beginning of
806 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
808 md
->metadata
[0] = 1; /* metadata image format version 1 */
810 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
811 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
814 si_make_texture_descriptor(device
, image
, false,
815 (VkImageViewType
)image
->type
, image
->vk_format
,
816 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
817 image
->info
.array_size
- 1,
818 image
->info
.width
, image
->info
.height
,
822 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
823 image
->planes
[0].surface
.blk_w
, false, false, desc
);
825 /* Clear the base address and set the relative DCC offset. */
827 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
828 desc
[7] = image
->dcc_offset
>> 8;
830 /* Dwords [2:9] contain the image descriptor. */
831 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
833 /* Dwords [10:..] contain the mipmap level offsets. */
834 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
835 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
836 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
837 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
842 radv_init_metadata(struct radv_device
*device
,
843 struct radv_image
*image
,
844 struct radeon_bo_metadata
*metadata
)
846 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
848 memset(metadata
, 0, sizeof(*metadata
));
850 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
851 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
853 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
854 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
855 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
856 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
857 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
858 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
859 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
860 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
861 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
862 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
863 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
864 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
866 radv_query_opaque_metadata(device
, image
, metadata
);
870 radv_image_override_offset_stride(struct radv_device
*device
,
871 struct radv_image
*image
,
872 uint64_t offset
, uint32_t stride
)
874 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
875 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
877 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
879 surface
->u
.gfx9
.surf_pitch
= stride
;
880 surface
->u
.gfx9
.surf_slice_size
=
881 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
883 surface
->u
.gfx9
.surf_offset
= offset
;
885 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
886 surface
->u
.legacy
.level
[0].slice_size_dw
=
887 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
890 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
891 surface
->u
.legacy
.level
[i
].offset
+= offset
;
897 /* The number of samples can be specified independently of the texture. */
899 radv_image_get_fmask_info(struct radv_device
*device
,
900 struct radv_image
*image
,
902 struct radv_fmask_info
*out
)
904 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
905 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
906 out
->size
= image
->planes
[0].surface
.fmask_size
;
907 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
911 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
912 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
913 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
914 out
->slice_size
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_size
;
915 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
916 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
917 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
918 out
->size
= image
->planes
[0].surface
.fmask_size
;
920 assert(!out
->tile_swizzle
|| !image
->shareable
);
924 radv_image_alloc_fmask(struct radv_device
*device
,
925 struct radv_image
*image
)
927 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
929 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
930 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
931 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
935 radv_image_get_cmask_info(struct radv_device
*device
,
936 struct radv_image
*image
,
937 struct radv_cmask_info
*out
)
939 assert(image
->plane_count
== 1);
941 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
942 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
943 out
->size
= image
->planes
[0].surface
.cmask_size
;
947 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.cmask_slice_tile_max
;
948 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
949 out
->slice_size
= image
->planes
[0].surface
.cmask_slice_size
;
950 out
->size
= image
->planes
[0].surface
.cmask_size
;
954 radv_image_alloc_cmask(struct radv_device
*device
,
955 struct radv_image
*image
)
957 uint32_t clear_value_size
= 0;
958 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
960 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
961 /* + 8 for storing the clear values */
962 if (!image
->clear_value_offset
) {
963 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
964 clear_value_size
= 8;
966 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
967 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
971 radv_image_alloc_dcc(struct radv_image
*image
)
973 assert(image
->plane_count
== 1);
975 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
976 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
977 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
978 image
->fce_pred_offset
= image
->clear_value_offset
+ 8 * image
->info
.levels
;
979 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16 * image
->info
.levels
;
980 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24 * image
->info
.levels
;
981 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
985 radv_image_alloc_htile(struct radv_image
*image
)
987 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
989 /* + 8 for storing the clear values */
990 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
991 image
->size
= image
->clear_value_offset
+ 8;
992 if (radv_image_is_tc_compat_htile(image
)) {
993 /* Metadata for the TC-compatible HTILE hardware bug which
994 * have to be fixed by updating ZRANGE_PRECISION when doing
995 * fast depth clears to 0.0f.
997 image
->tc_compat_zrange_offset
= image
->clear_value_offset
+ 8;
998 image
->size
= image
->clear_value_offset
+ 16;
1000 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
1004 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
1006 if (image
->info
.samples
<= 1 &&
1007 image
->info
.width
* image
->info
.height
<= 512 * 512) {
1008 /* Do not enable CMASK or DCC for small surfaces where the cost
1009 * of the eliminate pass can be higher than the benefit of fast
1010 * clear. RadeonSI does this, but the image threshold is
1016 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
1017 (image
->exclusive
|| image
->queue_family_mask
== 1);
1021 radv_image_can_enable_dcc(struct radv_image
*image
)
1023 return radv_image_can_enable_dcc_or_cmask(image
) &&
1024 radv_image_has_dcc(image
);
1028 radv_image_can_enable_cmask(struct radv_image
*image
)
1030 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
1031 /* Do not enable CMASK for non-MSAA images (fast color clear)
1032 * because 128 bit formats are not supported, but FMASK might
1038 return radv_image_can_enable_dcc_or_cmask(image
) &&
1039 image
->info
.levels
== 1 &&
1040 image
->info
.depth
== 1 &&
1041 !image
->planes
[0].surface
.is_linear
;
1045 radv_image_can_enable_fmask(struct radv_image
*image
)
1047 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
1051 radv_image_can_enable_htile(struct radv_image
*image
)
1053 return radv_image_has_htile(image
) &&
1054 image
->info
.levels
== 1 &&
1055 image
->info
.width
* image
->info
.height
>= 8 * 8;
1058 static void radv_image_disable_dcc(struct radv_image
*image
)
1060 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1061 image
->planes
[i
].surface
.dcc_size
= 0;
1064 static void radv_image_disable_htile(struct radv_image
*image
)
1066 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1067 image
->planes
[i
].surface
.htile_size
= 0;
1071 radv_image_create(VkDevice _device
,
1072 const struct radv_image_create_info
*create_info
,
1073 const VkAllocationCallbacks
* alloc
,
1076 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1077 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1078 struct radv_image
*image
= NULL
;
1079 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1081 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1082 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1084 radv_assert(pCreateInfo
->mipLevels
> 0);
1085 radv_assert(pCreateInfo
->arrayLayers
> 0);
1086 radv_assert(pCreateInfo
->samples
> 0);
1087 radv_assert(pCreateInfo
->extent
.width
> 0);
1088 radv_assert(pCreateInfo
->extent
.height
> 0);
1089 radv_assert(pCreateInfo
->extent
.depth
> 0);
1091 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1092 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1094 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1096 image
->type
= pCreateInfo
->imageType
;
1097 image
->info
.width
= pCreateInfo
->extent
.width
;
1098 image
->info
.height
= pCreateInfo
->extent
.height
;
1099 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1100 image
->info
.samples
= pCreateInfo
->samples
;
1101 image
->info
.storage_samples
= pCreateInfo
->samples
;
1102 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1103 image
->info
.levels
= pCreateInfo
->mipLevels
;
1104 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1106 image
->vk_format
= pCreateInfo
->format
;
1107 image
->tiling
= pCreateInfo
->tiling
;
1108 image
->usage
= pCreateInfo
->usage
;
1109 image
->flags
= pCreateInfo
->flags
;
1111 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1112 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1113 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1114 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
)
1115 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1117 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1120 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1121 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1122 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) &&
1123 !radv_surface_has_scanout(device
, create_info
) && !image
->shareable
) {
1124 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1127 image
->plane_count
= plane_count
;
1129 image
->alignment
= 1;
1130 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1131 struct ac_surf_info info
= image
->info
;
1132 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1135 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1136 assert(info
.width
% desc
->width_divisor
== 0);
1137 assert(info
.height
% desc
->height_divisor
== 0);
1139 info
.width
/= desc
->width_divisor
;
1140 info
.height
/= desc
->height_divisor
;
1143 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1145 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1146 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1147 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1149 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1152 if (!create_info
->no_metadata_planes
) {
1153 /* Try to enable DCC first. */
1154 if (radv_image_can_enable_dcc(image
)) {
1155 radv_image_alloc_dcc(image
);
1156 if (image
->info
.samples
> 1) {
1157 /* CMASK should be enabled because DCC fast
1158 * clear with MSAA needs it.
1160 assert(radv_image_can_enable_cmask(image
));
1161 radv_image_alloc_cmask(device
, image
);
1164 /* When DCC cannot be enabled, try CMASK. */
1165 radv_image_disable_dcc(image
);
1166 if (radv_image_can_enable_cmask(image
)) {
1167 radv_image_alloc_cmask(device
, image
);
1171 /* Try to enable FMASK for multisampled images. */
1172 if (radv_image_can_enable_fmask(image
)) {
1173 radv_image_alloc_fmask(device
, image
);
1175 if (radv_use_tc_compat_cmask_for_image(device
, image
))
1176 image
->tc_compatible_cmask
= true;
1178 /* Otherwise, try to enable HTILE for depth surfaces. */
1179 if (radv_image_can_enable_htile(image
) &&
1180 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1181 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1182 radv_image_alloc_htile(image
);
1184 radv_image_disable_htile(image
);
1188 radv_image_disable_dcc(image
);
1189 radv_image_disable_htile(image
);
1192 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1193 image
->alignment
= MAX2(image
->alignment
, 4096);
1194 image
->size
= align64(image
->size
, image
->alignment
);
1197 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1198 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1200 vk_free2(&device
->alloc
, alloc
, image
);
1201 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1205 *pImage
= radv_image_to_handle(image
);
1211 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1212 struct radv_device
*device
,
1214 const VkComponentMapping
*components
,
1215 bool is_storage_image
, unsigned plane_id
,
1216 unsigned descriptor_plane_id
)
1218 struct radv_image
*image
= iview
->image
;
1219 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1220 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1221 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1223 union radv_descriptor
*descriptor
;
1224 uint32_t hw_level
= 0;
1226 if (is_storage_image
) {
1227 descriptor
= &iview
->storage_descriptor
;
1229 descriptor
= &iview
->descriptor
;
1232 assert(vk_format_get_plane_count(vk_format
) == 1);
1233 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1234 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1236 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1237 hw_level
= iview
->base_mip
;
1238 si_make_texture_descriptor(device
, image
, is_storage_image
,
1242 hw_level
, hw_level
+ iview
->level_count
- 1,
1244 iview
->base_layer
+ iview
->layer_count
- 1,
1245 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1246 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1247 iview
->extent
.depth
,
1248 descriptor
->plane_descriptors
[descriptor_plane_id
],
1249 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1251 const struct legacy_surf_level
*base_level_info
= NULL
;
1252 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1254 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1256 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1258 si_set_mutable_tex_desc_fields(device
, image
,
1263 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1267 radv_plane_from_aspect(VkImageAspectFlags mask
)
1270 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1272 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1280 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1283 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1284 return image
->planes
[0].format
;
1285 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1286 return image
->planes
[1].format
;
1287 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1288 return image
->planes
[2].format
;
1289 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1290 return vk_format_stencil_only(image
->vk_format
);
1291 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1292 return vk_format_depth_only(image
->vk_format
);
1293 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1294 return vk_format_depth_only(image
->vk_format
);
1296 return image
->vk_format
;
1301 radv_image_view_init(struct radv_image_view
*iview
,
1302 struct radv_device
*device
,
1303 const VkImageViewCreateInfo
* pCreateInfo
)
1305 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1306 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1308 switch (image
->type
) {
1309 case VK_IMAGE_TYPE_1D
:
1310 case VK_IMAGE_TYPE_2D
:
1311 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1313 case VK_IMAGE_TYPE_3D
:
1314 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1315 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1318 unreachable("bad VkImageType");
1320 iview
->image
= image
;
1321 iview
->bo
= image
->bo
;
1322 iview
->type
= pCreateInfo
->viewType
;
1323 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1324 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1325 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1326 iview
->vk_format
= pCreateInfo
->format
;
1328 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1329 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1330 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1331 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1334 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1335 iview
->extent
= (VkExtent3D
) {
1336 .width
= image
->info
.width
,
1337 .height
= image
->info
.height
,
1338 .depth
= image
->info
.depth
,
1341 iview
->extent
= (VkExtent3D
) {
1342 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1343 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1344 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1348 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1349 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1350 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1351 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1352 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1354 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1355 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1357 /* Comment ported from amdvlk -
1358 * If we have the following image:
1359 * Uncompressed pixels Compressed block sizes (4x4)
1360 * mip0: 22 x 22 6 x 6
1361 * mip1: 11 x 11 3 x 3
1366 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1367 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1368 * divide-by-two integer math):
1374 * This means that mip2 will be missing texels.
1376 * Fix this by calculating the base mip's width and height, then convert that, and round it
1377 * back up to get the level 0 size.
1378 * Clamp the converted size between the original values, and next power of two, which
1379 * means we don't oversize the image.
1381 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1382 vk_format_is_compressed(image
->vk_format
) &&
1383 !vk_format_is_compressed(iview
->vk_format
)) {
1384 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1385 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1387 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1388 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1390 lvl_width
<<= range
->baseMipLevel
;
1391 lvl_height
<<= range
->baseMipLevel
;
1393 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1394 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1398 iview
->base_layer
= range
->baseArrayLayer
;
1399 iview
->layer_count
= radv_get_layerCount(image
, range
);
1400 iview
->base_mip
= range
->baseMipLevel
;
1401 iview
->level_count
= radv_get_levelCount(image
, range
);
1403 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1404 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1405 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1406 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1410 bool radv_layout_has_htile(const struct radv_image
*image
,
1411 VkImageLayout layout
,
1412 unsigned queue_mask
)
1414 if (radv_image_is_tc_compat_htile(image
))
1415 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1417 return radv_image_has_htile(image
) &&
1418 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1419 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1420 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1423 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1424 VkImageLayout layout
,
1425 unsigned queue_mask
)
1427 if (radv_image_is_tc_compat_htile(image
))
1428 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1430 return radv_image_has_htile(image
) &&
1431 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1432 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1433 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1436 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1437 VkImageLayout layout
,
1438 unsigned queue_mask
)
1440 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1443 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1444 VkImageLayout layout
,
1445 unsigned queue_mask
)
1447 /* Don't compress compute transfer dst, as image stores are not supported. */
1448 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1449 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1452 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1456 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1458 if (!image
->exclusive
)
1459 return image
->queue_family_mask
;
1460 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
1461 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1462 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1463 return 1u << queue_family
;
1464 return 1u << family
;
1468 radv_CreateImage(VkDevice device
,
1469 const VkImageCreateInfo
*pCreateInfo
,
1470 const VkAllocationCallbacks
*pAllocator
,
1474 const VkNativeBufferANDROID
*gralloc_info
=
1475 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1478 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1479 pAllocator
, pImage
);
1482 const struct wsi_image_create_info
*wsi_info
=
1483 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1484 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1486 return radv_image_create(device
,
1487 &(struct radv_image_create_info
) {
1488 .vk_info
= pCreateInfo
,
1496 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1497 const VkAllocationCallbacks
*pAllocator
)
1499 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1500 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1505 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1506 device
->ws
->buffer_destroy(image
->bo
);
1508 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1509 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1511 vk_free2(&device
->alloc
, pAllocator
, image
);
1514 void radv_GetImageSubresourceLayout(
1517 const VkImageSubresource
* pSubresource
,
1518 VkSubresourceLayout
* pLayout
)
1520 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1521 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1522 int level
= pSubresource
->mipLevel
;
1523 int layer
= pSubresource
->arrayLayer
;
1525 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1527 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1528 struct radeon_surf
*surface
= &plane
->surface
;
1530 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1531 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1532 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1533 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1534 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1535 /* Adjust the number of bytes between each row because
1536 * the pitch is actually the number of components per
1539 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1541 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1542 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1545 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1546 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1547 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1548 if (image
->type
== VK_IMAGE_TYPE_3D
)
1549 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1551 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1552 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1553 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1554 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1555 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1556 if (image
->type
== VK_IMAGE_TYPE_3D
)
1557 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1563 radv_CreateImageView(VkDevice _device
,
1564 const VkImageViewCreateInfo
*pCreateInfo
,
1565 const VkAllocationCallbacks
*pAllocator
,
1568 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1569 struct radv_image_view
*view
;
1571 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1572 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1574 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1576 radv_image_view_init(view
, device
, pCreateInfo
);
1578 *pView
= radv_image_view_to_handle(view
);
1584 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1585 const VkAllocationCallbacks
*pAllocator
)
1587 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1588 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1592 vk_free2(&device
->alloc
, pAllocator
, iview
);
1595 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1596 struct radv_device
*device
,
1597 const VkBufferViewCreateInfo
* pCreateInfo
)
1599 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1601 view
->bo
= buffer
->bo
;
1602 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1603 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1604 view
->vk_format
= pCreateInfo
->format
;
1606 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1607 pCreateInfo
->offset
, view
->range
, view
->state
);
1611 radv_CreateBufferView(VkDevice _device
,
1612 const VkBufferViewCreateInfo
*pCreateInfo
,
1613 const VkAllocationCallbacks
*pAllocator
,
1614 VkBufferView
*pView
)
1616 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1617 struct radv_buffer_view
*view
;
1619 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1620 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1622 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1624 radv_buffer_view_init(view
, device
, pCreateInfo
);
1626 *pView
= radv_buffer_view_to_handle(view
);
1632 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1633 const VkAllocationCallbacks
*pAllocator
)
1635 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1636 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1641 vk_free2(&device
->alloc
, pAllocator
, view
);